1 // 2 // Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 // CA 95054 USA or visit www.sun.com if you need additional information or 21 // have any questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Must be visible to the DFA in dfa_sparc.cpp 461 extern bool can_branch_register( Node *bol, Node *cmp ); 462 463 // Macros to extract hi & lo halves from a long pair. 464 // G0 is not part of any long pair, so assert on that. 465 // Prevents accidentally using G1 instead of G0. 466 #define LONG_HI_REG(x) (x) 467 #define LONG_LO_REG(x) (x) 468 469 %} 470 471 source %{ 472 #define __ _masm. 473 474 // Block initializing store 475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 476 477 // tertiary op of a LoadP or StoreP encoding 478 #define REGP_OP true 479 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 482 static Register reg_to_register_object(int register_encoding); 483 484 // Used by the DFA in dfa_sparc.cpp. 485 // Check for being able to use a V9 branch-on-register. Requires a 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 487 // extended. Doesn't work following an integer ADD, for example, because of 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 490 // replace them with zero, which could become sign-extension in a different OS 491 // release. There's no obvious reason why an interrupt will ever fill these 492 // bits with non-zero junk (the registers are reloaded with standard LD 493 // instructions which either zero-fill or sign-fill). 494 bool can_branch_register( Node *bol, Node *cmp ) { 495 if( !BranchOnRegister ) return false; 496 #ifdef _LP64 497 if( cmp->Opcode() == Op_CmpP ) 498 return true; // No problems with pointer compares 499 #endif 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525 } 526 527 // **************************************************************************** 528 529 // REQUIRED FUNCTIONALITY 530 531 // !!!!! Special hack to get all type of calls to specify the byte offset 532 // from the start of the call to the point where the return address 533 // will point. 534 // The "return address" is the address of the call instruction, plus 8. 535 536 int MachCallStaticJavaNode::ret_addr_offset() { 537 return NativeCall::instruction_size; // call; delay slot 538 } 539 540 int MachCallDynamicJavaNode::ret_addr_offset() { 541 int vtable_index = this->_vtable_index; 542 if (vtable_index < 0) { 543 // must be invalid_vtable_index, not nonvirtual_vtable_index 544 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 545 return (NativeMovConstReg::instruction_size + 546 NativeCall::instruction_size); // sethi; setlo; call; delay slot 547 } else { 548 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 549 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 550 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 551 int klass_load_size; 552 if (UseCompressedOops) { 553 assert(Universe::heap() != NULL, "java heap should be initialized"); 554 if (Universe::narrow_oop_base() == NULL) 555 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 556 else 557 klass_load_size = 3*BytesPerInstWord; 558 } else { 559 klass_load_size = 1*BytesPerInstWord; 560 } 561 if( Assembler::is_simm13(v_off) ) { 562 return klass_load_size + 563 (2*BytesPerInstWord + // ld_ptr, ld_ptr 564 NativeCall::instruction_size); // call; delay slot 565 } else { 566 return klass_load_size + 567 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 568 NativeCall::instruction_size); // call; delay slot 569 } 570 } 571 } 572 573 int MachCallRuntimeNode::ret_addr_offset() { 574 #ifdef _LP64 575 return NativeFarCall::instruction_size; // farcall; delay slot 576 #else 577 return NativeCall::instruction_size; // call; delay slot 578 #endif 579 } 580 581 // Indicate if the safepoint node needs the polling page as an input. 582 // Since Sparc does not have absolute addressing, it does. 583 bool SafePointNode::needs_polling_address_input() { 584 return true; 585 } 586 587 // emit an interrupt that is caught by the debugger (for debugging compiler) 588 void emit_break(CodeBuffer &cbuf) { 589 MacroAssembler _masm(&cbuf); 590 __ breakpoint_trap(); 591 } 592 593 #ifndef PRODUCT 594 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 595 st->print("TA"); 596 } 597 #endif 598 599 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 600 emit_break(cbuf); 601 } 602 603 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 604 return MachNode::size(ra_); 605 } 606 607 // Traceable jump 608 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 609 MacroAssembler _masm(&cbuf); 610 Register rdest = reg_to_register_object(jump_target); 611 __ JMP(rdest, 0); 612 __ delayed()->nop(); 613 } 614 615 // Traceable jump and set exception pc 616 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 617 MacroAssembler _masm(&cbuf); 618 Register rdest = reg_to_register_object(jump_target); 619 __ JMP(rdest, 0); 620 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 621 } 622 623 void emit_nop(CodeBuffer &cbuf) { 624 MacroAssembler _masm(&cbuf); 625 __ nop(); 626 } 627 628 void emit_illtrap(CodeBuffer &cbuf) { 629 MacroAssembler _masm(&cbuf); 630 __ illtrap(0); 631 } 632 633 634 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 635 assert(n->rule() != loadUB_rule, ""); 636 637 intptr_t offset = 0; 638 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 639 const Node* addr = n->get_base_and_disp(offset, adr_type); 640 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 641 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 642 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 643 atype = atype->add_offset(offset); 644 assert(disp32 == offset, "wrong disp32"); 645 return atype->_offset; 646 } 647 648 649 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 650 assert(n->rule() != loadUB_rule, ""); 651 652 intptr_t offset = 0; 653 Node* addr = n->in(2); 654 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 655 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 656 Node* a = addr->in(2/*AddPNode::Address*/); 657 Node* o = addr->in(3/*AddPNode::Offset*/); 658 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 659 atype = a->bottom_type()->is_ptr()->add_offset(offset); 660 assert(atype->isa_oop_ptr(), "still an oop"); 661 } 662 offset = atype->is_ptr()->_offset; 663 if (offset != Type::OffsetBot) offset += disp32; 664 return offset; 665 } 666 667 // Standard Sparc opcode form2 field breakdown 668 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 669 f0 &= (1<<19)-1; // Mask displacement to 19 bits 670 int op = (f30 << 30) | 671 (f29 << 29) | 672 (f25 << 25) | 673 (f22 << 22) | 674 (f20 << 20) | 675 (f19 << 19) | 676 (f0 << 0); 677 *((int*)(cbuf.code_end())) = op; 678 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 679 } 680 681 // Standard Sparc opcode form2 field breakdown 682 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 683 f0 >>= 10; // Drop 10 bits 684 f0 &= (1<<22)-1; // Mask displacement to 22 bits 685 int op = (f30 << 30) | 686 (f25 << 25) | 687 (f22 << 22) | 688 (f0 << 0); 689 *((int*)(cbuf.code_end())) = op; 690 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 691 } 692 693 // Standard Sparc opcode form3 field breakdown 694 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 695 int op = (f30 << 30) | 696 (f25 << 25) | 697 (f19 << 19) | 698 (f14 << 14) | 699 (f5 << 5) | 700 (f0 << 0); 701 *((int*)(cbuf.code_end())) = op; 702 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 703 } 704 705 // Standard Sparc opcode form3 field breakdown 706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 707 simm13 &= (1<<13)-1; // Mask to 13 bits 708 int op = (f30 << 30) | 709 (f25 << 25) | 710 (f19 << 19) | 711 (f14 << 14) | 712 (1 << 13) | // bit to indicate immediate-mode 713 (simm13<<0); 714 *((int*)(cbuf.code_end())) = op; 715 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 716 } 717 718 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 719 simm10 &= (1<<10)-1; // Mask to 10 bits 720 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 721 } 722 723 #ifdef ASSERT 724 // Helper function for VerifyOops in emit_form3_mem_reg 725 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 726 warning("VerifyOops encountered unexpected instruction:"); 727 n->dump(2); 728 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 729 } 730 #endif 731 732 733 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 734 int src1_enc, int disp32, int src2_enc, int dst_enc) { 735 736 #ifdef ASSERT 737 // The following code implements the +VerifyOops feature. 738 // It verifies oop values which are loaded into or stored out of 739 // the current method activation. +VerifyOops complements techniques 740 // like ScavengeALot, because it eagerly inspects oops in transit, 741 // as they enter or leave the stack, as opposed to ScavengeALot, 742 // which inspects oops "at rest", in the stack or heap, at safepoints. 743 // For this reason, +VerifyOops can sometimes detect bugs very close 744 // to their point of creation. It can also serve as a cross-check 745 // on the validity of oop maps, when used toegether with ScavengeALot. 746 747 // It would be good to verify oops at other points, especially 748 // when an oop is used as a base pointer for a load or store. 749 // This is presently difficult, because it is hard to know when 750 // a base address is biased or not. (If we had such information, 751 // it would be easy and useful to make a two-argument version of 752 // verify_oop which unbiases the base, and performs verification.) 753 754 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 755 bool is_verified_oop_base = false; 756 bool is_verified_oop_load = false; 757 bool is_verified_oop_store = false; 758 int tmp_enc = -1; 759 if (VerifyOops && src1_enc != R_SP_enc) { 760 // classify the op, mainly for an assert check 761 int st_op = 0, ld_op = 0; 762 switch (primary) { 763 case Assembler::stb_op3: st_op = Op_StoreB; break; 764 case Assembler::sth_op3: st_op = Op_StoreC; break; 765 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 766 case Assembler::stw_op3: st_op = Op_StoreI; break; 767 case Assembler::std_op3: st_op = Op_StoreL; break; 768 case Assembler::stf_op3: st_op = Op_StoreF; break; 769 case Assembler::stdf_op3: st_op = Op_StoreD; break; 770 771 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 772 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 773 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 774 case Assembler::ldx_op3: // may become LoadP or stay LoadI 775 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 776 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 777 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 778 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 779 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 780 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 781 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 782 783 default: ShouldNotReachHere(); 784 } 785 if (tertiary == REGP_OP) { 786 if (st_op == Op_StoreI) st_op = Op_StoreP; 787 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 788 else ShouldNotReachHere(); 789 if (st_op) { 790 // a store 791 // inputs are (0:control, 1:memory, 2:address, 3:value) 792 Node* n2 = n->in(3); 793 if (n2 != NULL) { 794 const Type* t = n2->bottom_type(); 795 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 796 } 797 } else { 798 // a load 799 const Type* t = n->bottom_type(); 800 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 801 } 802 } 803 804 if (ld_op) { 805 // a Load 806 // inputs are (0:control, 1:memory, 2:address) 807 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 808 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 809 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 810 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 811 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 812 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 813 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 814 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 815 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 816 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 817 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 818 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 819 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 820 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 821 !(n->rule() == loadUB_rule)) { 822 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 823 } 824 } else if (st_op) { 825 // a Store 826 // inputs are (0:control, 1:memory, 2:address, 3:value) 827 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 828 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 829 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 830 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 831 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 832 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 833 verify_oops_warning(n, n->ideal_Opcode(), st_op); 834 } 835 } 836 837 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 838 Node* addr = n->in(2); 839 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 840 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 841 if (atype != NULL) { 842 intptr_t offset = get_offset_from_base(n, atype, disp32); 843 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 844 if (offset != offset_2) { 845 get_offset_from_base(n, atype, disp32); 846 get_offset_from_base_2(n, atype, disp32); 847 } 848 assert(offset == offset_2, "different offsets"); 849 if (offset == disp32) { 850 // we now know that src1 is a true oop pointer 851 is_verified_oop_base = true; 852 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 853 if( primary == Assembler::ldd_op3 ) { 854 is_verified_oop_base = false; // Cannot 'ldd' into O7 855 } else { 856 tmp_enc = dst_enc; 857 dst_enc = R_O7_enc; // Load into O7; preserve source oop 858 assert(src1_enc != dst_enc, ""); 859 } 860 } 861 } 862 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 863 || offset == oopDesc::mark_offset_in_bytes())) { 864 // loading the mark should not be allowed either, but 865 // we don't check this since it conflicts with InlineObjectHash 866 // usage of LoadINode to get the mark. We could keep the 867 // check if we create a new LoadMarkNode 868 // but do not verify the object before its header is initialized 869 ShouldNotReachHere(); 870 } 871 } 872 } 873 } 874 } 875 #endif 876 877 uint instr; 878 instr = (Assembler::ldst_op << 30) 879 | (dst_enc << 25) 880 | (primary << 19) 881 | (src1_enc << 14); 882 883 uint index = src2_enc; 884 int disp = disp32; 885 886 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 887 disp += STACK_BIAS; 888 889 // We should have a compiler bailout here rather than a guarantee. 890 // Better yet would be some mechanism to handle variable-size matches correctly. 891 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 892 893 if( disp == 0 ) { 894 // use reg-reg form 895 // bit 13 is already zero 896 instr |= index; 897 } else { 898 // use reg-imm form 899 instr |= 0x00002000; // set bit 13 to one 900 instr |= disp & 0x1FFF; 901 } 902 903 uint *code = (uint*)cbuf.code_end(); 904 *code = instr; 905 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 906 907 #ifdef ASSERT 908 { 909 MacroAssembler _masm(&cbuf); 910 if (is_verified_oop_base) { 911 __ verify_oop(reg_to_register_object(src1_enc)); 912 } 913 if (is_verified_oop_store) { 914 __ verify_oop(reg_to_register_object(dst_enc)); 915 } 916 if (tmp_enc != -1) { 917 __ mov(O7, reg_to_register_object(tmp_enc)); 918 } 919 if (is_verified_oop_load) { 920 __ verify_oop(reg_to_register_object(dst_enc)); 921 } 922 } 923 #endif 924 } 925 926 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 927 // The method which records debug information at every safepoint 928 // expects the call to be the first instruction in the snippet as 929 // it creates a PcDesc structure which tracks the offset of a call 930 // from the start of the codeBlob. This offset is computed as 931 // code_end() - code_begin() of the code which has been emitted 932 // so far. 933 // In this particular case we have skirted around the problem by 934 // putting the "mov" instruction in the delay slot but the problem 935 // may bite us again at some other point and a cleaner/generic 936 // solution using relocations would be needed. 937 MacroAssembler _masm(&cbuf); 938 __ set_inst_mark(); 939 940 // We flush the current window just so that there is a valid stack copy 941 // the fact that the current window becomes active again instantly is 942 // not a problem there is nothing live in it. 943 944 #ifdef ASSERT 945 int startpos = __ offset(); 946 #endif /* ASSERT */ 947 948 #ifdef _LP64 949 // Calls to the runtime or native may not be reachable from compiled code, 950 // so we generate the far call sequence on 64 bit sparc. 951 // This code sequence is relocatable to any address, even on LP64. 952 if ( force_far_call ) { 953 __ relocate(rtype); 954 AddressLiteral dest(entry_point); 955 __ jumpl_to(dest, O7, O7); 956 } 957 else 958 #endif 959 { 960 __ call((address)entry_point, rtype); 961 } 962 963 if (preserve_g2) __ delayed()->mov(G2, L7); 964 else __ delayed()->nop(); 965 966 if (preserve_g2) __ mov(L7, G2); 967 968 #ifdef ASSERT 969 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 970 #ifdef _LP64 971 // Trash argument dump slots. 972 __ set(0xb0b8ac0db0b8ac0d, G1); 973 __ mov(G1, G5); 974 __ stx(G1, SP, STACK_BIAS + 0x80); 975 __ stx(G1, SP, STACK_BIAS + 0x88); 976 __ stx(G1, SP, STACK_BIAS + 0x90); 977 __ stx(G1, SP, STACK_BIAS + 0x98); 978 __ stx(G1, SP, STACK_BIAS + 0xA0); 979 __ stx(G1, SP, STACK_BIAS + 0xA8); 980 #else // _LP64 981 // this is also a native call, so smash the first 7 stack locations, 982 // and the various registers 983 984 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 985 // while [SP+0x44..0x58] are the argument dump slots. 986 __ set((intptr_t)0xbaadf00d, G1); 987 __ mov(G1, G5); 988 __ sllx(G1, 32, G1); 989 __ or3(G1, G5, G1); 990 __ mov(G1, G5); 991 __ stx(G1, SP, 0x40); 992 __ stx(G1, SP, 0x48); 993 __ stx(G1, SP, 0x50); 994 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 995 #endif // _LP64 996 } 997 #endif /*ASSERT*/ 998 } 999 1000 //============================================================================= 1001 // REQUIRED FUNCTIONALITY for encoding 1002 void emit_lo(CodeBuffer &cbuf, int val) { } 1003 void emit_hi(CodeBuffer &cbuf, int val) { } 1004 1005 1006 //============================================================================= 1007 1008 #ifndef PRODUCT 1009 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1010 Compile* C = ra_->C; 1011 1012 for (int i = 0; i < OptoPrologueNops; i++) { 1013 st->print_cr("NOP"); st->print("\t"); 1014 } 1015 1016 if( VerifyThread ) { 1017 st->print_cr("Verify_Thread"); st->print("\t"); 1018 } 1019 1020 size_t framesize = C->frame_slots() << LogBytesPerInt; 1021 1022 // Calls to C2R adapters often do not accept exceptional returns. 1023 // We require that their callers must bang for them. But be careful, because 1024 // some VM calls (such as call site linkage) can use several kilobytes of 1025 // stack. But the stack safety zone should account for that. 1026 // See bugs 4446381, 4468289, 4497237. 1027 if (C->need_stack_bang(framesize)) { 1028 st->print_cr("! stack bang"); st->print("\t"); 1029 } 1030 1031 if (Assembler::is_simm13(-framesize)) { 1032 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1033 } else { 1034 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1035 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1036 st->print ("SAVE R_SP,R_G3,R_SP"); 1037 } 1038 1039 } 1040 #endif 1041 1042 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1043 Compile* C = ra_->C; 1044 MacroAssembler _masm(&cbuf); 1045 1046 for (int i = 0; i < OptoPrologueNops; i++) { 1047 __ nop(); 1048 } 1049 1050 __ verify_thread(); 1051 1052 size_t framesize = C->frame_slots() << LogBytesPerInt; 1053 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1054 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1055 1056 // Calls to C2R adapters often do not accept exceptional returns. 1057 // We require that their callers must bang for them. But be careful, because 1058 // some VM calls (such as call site linkage) can use several kilobytes of 1059 // stack. But the stack safety zone should account for that. 1060 // See bugs 4446381, 4468289, 4497237. 1061 if (C->need_stack_bang(framesize)) { 1062 __ generate_stack_overflow_check(framesize); 1063 } 1064 1065 if (Assembler::is_simm13(-framesize)) { 1066 __ save(SP, -framesize, SP); 1067 } else { 1068 __ sethi(-framesize & ~0x3ff, G3); 1069 __ add(G3, -framesize & 0x3ff, G3); 1070 __ save(SP, G3, SP); 1071 } 1072 C->set_frame_complete( __ offset() ); 1073 } 1074 1075 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1076 return MachNode::size(ra_); 1077 } 1078 1079 int MachPrologNode::reloc() const { 1080 return 10; // a large enough number 1081 } 1082 1083 //============================================================================= 1084 #ifndef PRODUCT 1085 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1086 Compile* C = ra_->C; 1087 1088 if( do_polling() && ra_->C->is_method_compilation() ) { 1089 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1090 #ifdef _LP64 1091 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1092 #else 1093 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1094 #endif 1095 } 1096 1097 if( do_polling() ) 1098 st->print("RET\n\t"); 1099 1100 st->print("RESTORE"); 1101 } 1102 #endif 1103 1104 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1105 MacroAssembler _masm(&cbuf); 1106 Compile* C = ra_->C; 1107 1108 __ verify_thread(); 1109 1110 // If this does safepoint polling, then do it here 1111 if( do_polling() && ra_->C->is_method_compilation() ) { 1112 AddressLiteral polling_page(os::get_polling_page()); 1113 __ sethi(polling_page, L0); 1114 __ relocate(relocInfo::poll_return_type); 1115 __ ld_ptr( L0, 0, G0 ); 1116 } 1117 1118 // If this is a return, then stuff the restore in the delay slot 1119 if( do_polling() ) { 1120 __ ret(); 1121 __ delayed()->restore(); 1122 } else { 1123 __ restore(); 1124 } 1125 } 1126 1127 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1128 return MachNode::size(ra_); 1129 } 1130 1131 int MachEpilogNode::reloc() const { 1132 return 16; // a large enough number 1133 } 1134 1135 const Pipeline * MachEpilogNode::pipeline() const { 1136 return MachNode::pipeline_class(); 1137 } 1138 1139 int MachEpilogNode::safepoint_offset() const { 1140 assert( do_polling(), "no return for this epilog node"); 1141 return MacroAssembler::size_of_sethi(os::get_polling_page()); 1142 } 1143 1144 //============================================================================= 1145 1146 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1147 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1148 static enum RC rc_class( OptoReg::Name reg ) { 1149 if( !OptoReg::is_valid(reg) ) return rc_bad; 1150 if (OptoReg::is_stack(reg)) return rc_stack; 1151 VMReg r = OptoReg::as_VMReg(reg); 1152 if (r->is_Register()) return rc_int; 1153 assert(r->is_FloatRegister(), "must be"); 1154 return rc_float; 1155 } 1156 1157 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1158 if( cbuf ) { 1159 // Better yet would be some mechanism to handle variable-size matches correctly 1160 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1161 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1162 } else { 1163 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1164 } 1165 } 1166 #ifndef PRODUCT 1167 else if( !do_size ) { 1168 if( size != 0 ) st->print("\n\t"); 1169 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1170 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1171 } 1172 #endif 1173 return size+4; 1174 } 1175 1176 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1177 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1178 #ifndef PRODUCT 1179 else if( !do_size ) { 1180 if( size != 0 ) st->print("\n\t"); 1181 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1182 } 1183 #endif 1184 return size+4; 1185 } 1186 1187 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1188 PhaseRegAlloc *ra_, 1189 bool do_size, 1190 outputStream* st ) const { 1191 // Get registers to move 1192 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1193 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1194 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1195 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1196 1197 enum RC src_second_rc = rc_class(src_second); 1198 enum RC src_first_rc = rc_class(src_first); 1199 enum RC dst_second_rc = rc_class(dst_second); 1200 enum RC dst_first_rc = rc_class(dst_first); 1201 1202 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1203 1204 // Generate spill code! 1205 int size = 0; 1206 1207 if( src_first == dst_first && src_second == dst_second ) 1208 return size; // Self copy, no move 1209 1210 // -------------------------------------- 1211 // Check for mem-mem move. Load into unused float registers and fall into 1212 // the float-store case. 1213 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1214 int offset = ra_->reg2offset(src_first); 1215 // Further check for aligned-adjacent pair, so we can use a double load 1216 if( (src_first&1)==0 && src_first+1 == src_second ) { 1217 src_second = OptoReg::Name(R_F31_num); 1218 src_second_rc = rc_float; 1219 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1220 } else { 1221 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1222 } 1223 src_first = OptoReg::Name(R_F30_num); 1224 src_first_rc = rc_float; 1225 } 1226 1227 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1228 int offset = ra_->reg2offset(src_second); 1229 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1230 src_second = OptoReg::Name(R_F31_num); 1231 src_second_rc = rc_float; 1232 } 1233 1234 // -------------------------------------- 1235 // Check for float->int copy; requires a trip through memory 1236 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 1237 int offset = frame::register_save_words*wordSize; 1238 if( cbuf ) { 1239 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1240 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1241 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1242 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1243 } 1244 #ifndef PRODUCT 1245 else if( !do_size ) { 1246 if( size != 0 ) st->print("\n\t"); 1247 st->print( "SUB R_SP,16,R_SP\n"); 1248 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1249 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1250 st->print("\tADD R_SP,16,R_SP\n"); 1251 } 1252 #endif 1253 size += 16; 1254 } 1255 1256 // -------------------------------------- 1257 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1258 // In such cases, I have to do the big-endian swap. For aligned targets, the 1259 // hardware does the flop for me. Doubles are always aligned, so no problem 1260 // there. Misaligned sources only come from native-long-returns (handled 1261 // special below). 1262 #ifndef _LP64 1263 if( src_first_rc == rc_int && // source is already big-endian 1264 src_second_rc != rc_bad && // 64-bit move 1265 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1266 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1267 // Do the big-endian flop. 1268 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1269 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1270 } 1271 #endif 1272 1273 // -------------------------------------- 1274 // Check for integer reg-reg copy 1275 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1276 #ifndef _LP64 1277 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1278 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1279 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1280 // operand contains the least significant word of the 64-bit value and vice versa. 1281 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1282 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1283 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1284 if( cbuf ) { 1285 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1286 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1287 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1288 #ifndef PRODUCT 1289 } else if( !do_size ) { 1290 if( size != 0 ) st->print("\n\t"); 1291 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1292 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1293 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1294 #endif 1295 } 1296 return size+12; 1297 } 1298 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1299 // returning a long value in I0/I1 1300 // a SpillCopy must be able to target a return instruction's reg_class 1301 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1302 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1303 // operand contains the least significant word of the 64-bit value and vice versa. 1304 OptoReg::Name tdest = dst_first; 1305 1306 if (src_first == dst_first) { 1307 tdest = OptoReg::Name(R_O7_num); 1308 size += 4; 1309 } 1310 1311 if( cbuf ) { 1312 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1313 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1314 // ShrL_reg_imm6 1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1316 // ShrR_reg_imm6 src, 0, dst 1317 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1318 if (tdest != dst_first) { 1319 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1320 } 1321 } 1322 #ifndef PRODUCT 1323 else if( !do_size ) { 1324 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1325 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1326 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1327 if (tdest != dst_first) { 1328 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1329 } 1330 } 1331 #endif // PRODUCT 1332 return size+8; 1333 } 1334 #endif // !_LP64 1335 // Else normal reg-reg copy 1336 assert( src_second != dst_first, "smashed second before evacuating it" ); 1337 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1338 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1339 // This moves an aligned adjacent pair. 1340 // See if we are done. 1341 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1342 return size; 1343 } 1344 1345 // Check for integer store 1346 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1347 int offset = ra_->reg2offset(dst_first); 1348 // Further check for aligned-adjacent pair, so we can use a double store 1349 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1350 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1351 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1352 } 1353 1354 // Check for integer load 1355 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1356 int offset = ra_->reg2offset(src_first); 1357 // Further check for aligned-adjacent pair, so we can use a double load 1358 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1359 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1360 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1361 } 1362 1363 // Check for float reg-reg copy 1364 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1365 // Further check for aligned-adjacent pair, so we can use a double move 1366 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1367 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1368 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1369 } 1370 1371 // Check for float store 1372 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1373 int offset = ra_->reg2offset(dst_first); 1374 // Further check for aligned-adjacent pair, so we can use a double store 1375 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1376 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1377 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1378 } 1379 1380 // Check for float load 1381 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1382 int offset = ra_->reg2offset(src_first); 1383 // Further check for aligned-adjacent pair, so we can use a double load 1384 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1385 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1386 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1387 } 1388 1389 // -------------------------------------------------------------------- 1390 // Check for hi bits still needing moving. Only happens for misaligned 1391 // arguments to native calls. 1392 if( src_second == dst_second ) 1393 return size; // Self copy; no move 1394 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1395 1396 #ifndef _LP64 1397 // In the LP64 build, all registers can be moved as aligned/adjacent 1398 // pairs, so there's never any need to move the high bits separately. 1399 // The 32-bit builds have to deal with the 32-bit ABI which can force 1400 // all sorts of silly alignment problems. 1401 1402 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1403 // 32-bits of a 64-bit register, but are needed in low bits of another 1404 // register (else it's a hi-bits-to-hi-bits copy which should have 1405 // happened already as part of a 64-bit move) 1406 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1407 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1408 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1409 // Shift src_second down to dst_second's low bits. 1410 if( cbuf ) { 1411 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1412 #ifndef PRODUCT 1413 } else if( !do_size ) { 1414 if( size != 0 ) st->print("\n\t"); 1415 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1416 #endif 1417 } 1418 return size+4; 1419 } 1420 1421 // Check for high word integer store. Must down-shift the hi bits 1422 // into a temp register, then fall into the case of storing int bits. 1423 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1424 // Shift src_second down to dst_second's low bits. 1425 if( cbuf ) { 1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1427 #ifndef PRODUCT 1428 } else if( !do_size ) { 1429 if( size != 0 ) st->print("\n\t"); 1430 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1431 #endif 1432 } 1433 size+=4; 1434 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1435 } 1436 1437 // Check for high word integer load 1438 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1439 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1440 1441 // Check for high word integer store 1442 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1443 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1444 1445 // Check for high word float store 1446 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1447 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1448 1449 #endif // !_LP64 1450 1451 Unimplemented(); 1452 } 1453 1454 #ifndef PRODUCT 1455 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1456 implementation( NULL, ra_, false, st ); 1457 } 1458 #endif 1459 1460 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1461 implementation( &cbuf, ra_, false, NULL ); 1462 } 1463 1464 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1465 return implementation( NULL, ra_, true, NULL ); 1466 } 1467 1468 //============================================================================= 1469 #ifndef PRODUCT 1470 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1471 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1472 } 1473 #endif 1474 1475 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1476 MacroAssembler _masm(&cbuf); 1477 for(int i = 0; i < _count; i += 1) { 1478 __ nop(); 1479 } 1480 } 1481 1482 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1483 return 4 * _count; 1484 } 1485 1486 1487 //============================================================================= 1488 #ifndef PRODUCT 1489 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1490 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1491 int reg = ra_->get_reg_first(this); 1492 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1493 } 1494 #endif 1495 1496 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1497 MacroAssembler _masm(&cbuf); 1498 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1499 int reg = ra_->get_encode(this); 1500 1501 if (Assembler::is_simm13(offset)) { 1502 __ add(SP, offset, reg_to_register_object(reg)); 1503 } else { 1504 __ set(offset, O7); 1505 __ add(SP, O7, reg_to_register_object(reg)); 1506 } 1507 } 1508 1509 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1510 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1511 assert(ra_ == ra_->C->regalloc(), "sanity"); 1512 return ra_->C->scratch_emit_size(this); 1513 } 1514 1515 //============================================================================= 1516 1517 // emit call stub, compiled java to interpretor 1518 void emit_java_to_interp(CodeBuffer &cbuf ) { 1519 1520 // Stub is fixed up when the corresponding call is converted from calling 1521 // compiled code to calling interpreted code. 1522 // set (empty), G5 1523 // jmp -1 1524 1525 address mark = cbuf.inst_mark(); // get mark within main instrs section 1526 1527 MacroAssembler _masm(&cbuf); 1528 1529 address base = 1530 __ start_a_stub(Compile::MAX_stubs_size); 1531 if (base == NULL) return; // CodeBuffer::expand failed 1532 1533 // static stub relocation stores the instruction address of the call 1534 __ relocate(static_stub_Relocation::spec(mark)); 1535 1536 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1537 1538 __ set_inst_mark(); 1539 AddressLiteral addrlit(-1); 1540 __ JUMP(addrlit, G3, 0); 1541 1542 __ delayed()->nop(); 1543 1544 // Update current stubs pointer and restore code_end. 1545 __ end_a_stub(); 1546 } 1547 1548 // size of call stub, compiled java to interpretor 1549 uint size_java_to_interp() { 1550 // This doesn't need to be accurate but it must be larger or equal to 1551 // the real size of the stub. 1552 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1553 NativeJump::instruction_size + // sethi; jmp; nop 1554 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1555 } 1556 // relocation entries for call stub, compiled java to interpretor 1557 uint reloc_java_to_interp() { 1558 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1559 } 1560 1561 1562 //============================================================================= 1563 #ifndef PRODUCT 1564 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1565 st->print_cr("\nUEP:"); 1566 #ifdef _LP64 1567 if (UseCompressedOops) { 1568 assert(Universe::heap() != NULL, "java heap should be initialized"); 1569 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1570 st->print_cr("\tSLL R_G5,3,R_G5"); 1571 if (Universe::narrow_oop_base() != NULL) 1572 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1573 } else { 1574 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1575 } 1576 st->print_cr("\tCMP R_G5,R_G3" ); 1577 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1578 #else // _LP64 1579 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1580 st->print_cr("\tCMP R_G5,R_G3" ); 1581 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1582 #endif // _LP64 1583 } 1584 #endif 1585 1586 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1587 MacroAssembler _masm(&cbuf); 1588 Label L; 1589 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1590 Register temp_reg = G3; 1591 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1592 1593 // Load klass from receiver 1594 __ load_klass(O0, temp_reg); 1595 // Compare against expected klass 1596 __ cmp(temp_reg, G5_ic_reg); 1597 // Branch to miss code, checks xcc or icc depending 1598 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1599 } 1600 1601 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1602 return MachNode::size(ra_); 1603 } 1604 1605 1606 //============================================================================= 1607 1608 uint size_exception_handler() { 1609 if (TraceJumps) { 1610 return (400); // just a guess 1611 } 1612 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1613 } 1614 1615 uint size_deopt_handler() { 1616 if (TraceJumps) { 1617 return (400); // just a guess 1618 } 1619 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1620 } 1621 1622 // Emit exception handler code. 1623 int emit_exception_handler(CodeBuffer& cbuf) { 1624 Register temp_reg = G3; 1625 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); 1626 MacroAssembler _masm(&cbuf); 1627 1628 address base = 1629 __ start_a_stub(size_exception_handler()); 1630 if (base == NULL) return 0; // CodeBuffer::expand failed 1631 1632 int offset = __ offset(); 1633 1634 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1635 __ delayed()->nop(); 1636 1637 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1638 1639 __ end_a_stub(); 1640 1641 return offset; 1642 } 1643 1644 int emit_deopt_handler(CodeBuffer& cbuf) { 1645 // Can't use any of the current frame's registers as we may have deopted 1646 // at a poll and everything (including G3) can be live. 1647 Register temp_reg = L0; 1648 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1649 MacroAssembler _masm(&cbuf); 1650 1651 address base = 1652 __ start_a_stub(size_deopt_handler()); 1653 if (base == NULL) return 0; // CodeBuffer::expand failed 1654 1655 int offset = __ offset(); 1656 __ save_frame(0); 1657 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1658 __ delayed()->restore(); 1659 1660 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1661 1662 __ end_a_stub(); 1663 return offset; 1664 1665 } 1666 1667 // Given a register encoding, produce a Integer Register object 1668 static Register reg_to_register_object(int register_encoding) { 1669 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1670 return as_Register(register_encoding); 1671 } 1672 1673 // Given a register encoding, produce a single-precision Float Register object 1674 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1675 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1676 return as_SingleFloatRegister(register_encoding); 1677 } 1678 1679 // Given a register encoding, produce a double-precision Float Register object 1680 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1681 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1682 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1683 return as_DoubleFloatRegister(register_encoding); 1684 } 1685 1686 const bool Matcher::match_rule_supported(int opcode) { 1687 if (!has_match_rule(opcode)) 1688 return false; 1689 1690 switch (opcode) { 1691 case Op_CountLeadingZerosI: 1692 case Op_CountLeadingZerosL: 1693 case Op_CountTrailingZerosI: 1694 case Op_CountTrailingZerosL: 1695 if (!UsePopCountInstruction) 1696 return false; 1697 break; 1698 } 1699 1700 return true; // Per default match rules are supported. 1701 } 1702 1703 int Matcher::regnum_to_fpu_offset(int regnum) { 1704 return regnum - 32; // The FP registers are in the second chunk 1705 } 1706 1707 #ifdef ASSERT 1708 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1709 #endif 1710 1711 // Vector width in bytes 1712 const uint Matcher::vector_width_in_bytes(void) { 1713 return 8; 1714 } 1715 1716 // Vector ideal reg 1717 const uint Matcher::vector_ideal_reg(void) { 1718 return Op_RegD; 1719 } 1720 1721 // USII supports fxtof through the whole range of number, USIII doesn't 1722 const bool Matcher::convL2FSupported(void) { 1723 return VM_Version::has_fast_fxtof(); 1724 } 1725 1726 // Is this branch offset short enough that a short branch can be used? 1727 // 1728 // NOTE: If the platform does not provide any short branch variants, then 1729 // this method should return false for offset 0. 1730 bool Matcher::is_short_branch_offset(int rule, int offset) { 1731 return false; 1732 } 1733 1734 const bool Matcher::isSimpleConstant64(jlong value) { 1735 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1736 // Depends on optimizations in MacroAssembler::setx. 1737 int hi = (int)(value >> 32); 1738 int lo = (int)(value & ~0); 1739 return (hi == 0) || (hi == -1) || (lo == 0); 1740 } 1741 1742 // No scaling for the parameter the ClearArray node. 1743 const bool Matcher::init_array_count_is_in_bytes = true; 1744 1745 // Threshold size for cleararray. 1746 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1747 1748 // Should the Matcher clone shifts on addressing modes, expecting them to 1749 // be subsumed into complex addressing expressions or compute them into 1750 // registers? True for Intel but false for most RISCs 1751 const bool Matcher::clone_shift_expressions = false; 1752 1753 bool Matcher::narrow_oop_use_complex_address() { 1754 NOT_LP64(ShouldNotCallThis()); 1755 assert(UseCompressedOops, "only for comressed oops code"); 1756 return false; 1757 } 1758 1759 // Is it better to copy float constants, or load them directly from memory? 1760 // Intel can load a float constant from a direct address, requiring no 1761 // extra registers. Most RISCs will have to materialize an address into a 1762 // register first, so they would do better to copy the constant from stack. 1763 const bool Matcher::rematerialize_float_constants = false; 1764 1765 // If CPU can load and store mis-aligned doubles directly then no fixup is 1766 // needed. Else we split the double into 2 integer pieces and move it 1767 // piece-by-piece. Only happens when passing doubles into C code as the 1768 // Java calling convention forces doubles to be aligned. 1769 #ifdef _LP64 1770 const bool Matcher::misaligned_doubles_ok = true; 1771 #else 1772 const bool Matcher::misaligned_doubles_ok = false; 1773 #endif 1774 1775 // No-op on SPARC. 1776 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1777 } 1778 1779 // Advertise here if the CPU requires explicit rounding operations 1780 // to implement the UseStrictFP mode. 1781 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1782 1783 // Are floats conerted to double when stored to stack during deoptimization? 1784 // Sparc does not handle callee-save floats. 1785 bool Matcher::float_in_double() { return false; } 1786 1787 // Do ints take an entire long register or just half? 1788 // Note that we if-def off of _LP64. 1789 // The relevant question is how the int is callee-saved. In _LP64 1790 // the whole long is written but de-opt'ing will have to extract 1791 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1792 #ifdef _LP64 1793 const bool Matcher::int_in_long = true; 1794 #else 1795 const bool Matcher::int_in_long = false; 1796 #endif 1797 1798 // Return whether or not this register is ever used as an argument. This 1799 // function is used on startup to build the trampoline stubs in generateOptoStub. 1800 // Registers not mentioned will be killed by the VM call in the trampoline, and 1801 // arguments in those registers not be available to the callee. 1802 bool Matcher::can_be_java_arg( int reg ) { 1803 // Standard sparc 6 args in registers 1804 if( reg == R_I0_num || 1805 reg == R_I1_num || 1806 reg == R_I2_num || 1807 reg == R_I3_num || 1808 reg == R_I4_num || 1809 reg == R_I5_num ) return true; 1810 #ifdef _LP64 1811 // 64-bit builds can pass 64-bit pointers and longs in 1812 // the high I registers 1813 if( reg == R_I0H_num || 1814 reg == R_I1H_num || 1815 reg == R_I2H_num || 1816 reg == R_I3H_num || 1817 reg == R_I4H_num || 1818 reg == R_I5H_num ) return true; 1819 1820 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1821 return true; 1822 } 1823 1824 #else 1825 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1826 // Longs cannot be passed in O regs, because O regs become I regs 1827 // after a 'save' and I regs get their high bits chopped off on 1828 // interrupt. 1829 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1830 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1831 #endif 1832 // A few float args in registers 1833 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1834 1835 return false; 1836 } 1837 1838 bool Matcher::is_spillable_arg( int reg ) { 1839 return can_be_java_arg(reg); 1840 } 1841 1842 // Register for DIVI projection of divmodI 1843 RegMask Matcher::divI_proj_mask() { 1844 ShouldNotReachHere(); 1845 return RegMask(); 1846 } 1847 1848 // Register for MODI projection of divmodI 1849 RegMask Matcher::modI_proj_mask() { 1850 ShouldNotReachHere(); 1851 return RegMask(); 1852 } 1853 1854 // Register for DIVL projection of divmodL 1855 RegMask Matcher::divL_proj_mask() { 1856 ShouldNotReachHere(); 1857 return RegMask(); 1858 } 1859 1860 // Register for MODL projection of divmodL 1861 RegMask Matcher::modL_proj_mask() { 1862 ShouldNotReachHere(); 1863 return RegMask(); 1864 } 1865 1866 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1867 return RegMask(); 1868 } 1869 1870 %} 1871 1872 1873 // The intptr_t operand types, defined by textual substitution. 1874 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1875 #ifdef _LP64 1876 #define immX immL 1877 #define immX13 immL13 1878 #define immX13m7 immL13m7 1879 #define iRegX iRegL 1880 #define g1RegX g1RegL 1881 #else 1882 #define immX immI 1883 #define immX13 immI13 1884 #define immX13m7 immI13m7 1885 #define iRegX iRegI 1886 #define g1RegX g1RegI 1887 #endif 1888 1889 //----------ENCODING BLOCK----------------------------------------------------- 1890 // This block specifies the encoding classes used by the compiler to output 1891 // byte streams. Encoding classes are parameterized macros used by 1892 // Machine Instruction Nodes in order to generate the bit encoding of the 1893 // instruction. Operands specify their base encoding interface with the 1894 // interface keyword. There are currently supported four interfaces, 1895 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1896 // operand to generate a function which returns its register number when 1897 // queried. CONST_INTER causes an operand to generate a function which 1898 // returns the value of the constant when queried. MEMORY_INTER causes an 1899 // operand to generate four functions which return the Base Register, the 1900 // Index Register, the Scale Value, and the Offset Value of the operand when 1901 // queried. COND_INTER causes an operand to generate six functions which 1902 // return the encoding code (ie - encoding bits for the instruction) 1903 // associated with each basic boolean condition for a conditional instruction. 1904 // 1905 // Instructions specify two basic values for encoding. Again, a function 1906 // is available to check if the constant displacement is an oop. They use the 1907 // ins_encode keyword to specify their encoding classes (which must be 1908 // a sequence of enc_class names, and their parameters, specified in 1909 // the encoding block), and they use the 1910 // opcode keyword to specify, in order, their primary, secondary, and 1911 // tertiary opcode. Only the opcode sections which a particular instruction 1912 // needs for encoding need to be specified. 1913 encode %{ 1914 enc_class enc_untested %{ 1915 #ifdef ASSERT 1916 MacroAssembler _masm(&cbuf); 1917 __ untested("encoding"); 1918 #endif 1919 %} 1920 1921 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1922 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1923 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1924 %} 1925 1926 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1927 emit_form3_mem_reg(cbuf, this, $primary, -1, 1928 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1929 %} 1930 1931 enc_class form3_mem_prefetch_read( memory mem ) %{ 1932 emit_form3_mem_reg(cbuf, this, $primary, -1, 1933 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1934 %} 1935 1936 enc_class form3_mem_prefetch_write( memory mem ) %{ 1937 emit_form3_mem_reg(cbuf, this, $primary, -1, 1938 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 1939 %} 1940 1941 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 1942 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1943 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1944 guarantee($mem$$index == R_G0_enc, "double index?"); 1945 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 1946 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 1947 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 1948 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 1949 %} 1950 1951 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 1952 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1953 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1954 guarantee($mem$$index == R_G0_enc, "double index?"); 1955 // Load long with 2 instructions 1956 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 1957 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 1958 %} 1959 1960 //%%% form3_mem_plus_4_reg is a hack--get rid of it 1961 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 1962 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 1963 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 1964 %} 1965 1966 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 1967 // Encode a reg-reg copy. If it is useless, then empty encoding. 1968 if( $rs2$$reg != $rd$$reg ) 1969 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 1970 %} 1971 1972 // Target lo half of long 1973 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 1974 // Encode a reg-reg copy. If it is useless, then empty encoding. 1975 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 1976 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 1977 %} 1978 1979 // Source lo half of long 1980 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 1981 // Encode a reg-reg copy. If it is useless, then empty encoding. 1982 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 1983 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 1984 %} 1985 1986 // Target hi half of long 1987 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 1988 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 1989 %} 1990 1991 // Source lo half of long, and leave it sign extended. 1992 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 1993 // Sign extend low half 1994 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 1995 %} 1996 1997 // Source hi half of long, and leave it sign extended. 1998 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 1999 // Shift high half to low half 2000 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2001 %} 2002 2003 // Source hi half of long 2004 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2005 // Encode a reg-reg copy. If it is useless, then empty encoding. 2006 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2007 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2008 %} 2009 2010 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2011 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2012 %} 2013 2014 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2015 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2016 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2017 %} 2018 2019 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2020 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2021 // clear if nothing else is happening 2022 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2023 // blt,a,pn done 2024 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2025 // mov dst,-1 in delay slot 2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2027 %} 2028 2029 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2030 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2031 %} 2032 2033 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2035 %} 2036 2037 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2038 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2039 %} 2040 2041 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2042 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2043 %} 2044 2045 enc_class move_return_pc_to_o1() %{ 2046 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2047 %} 2048 2049 #ifdef _LP64 2050 /* %%% merge with enc_to_bool */ 2051 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2052 MacroAssembler _masm(&cbuf); 2053 2054 Register src_reg = reg_to_register_object($src$$reg); 2055 Register dst_reg = reg_to_register_object($dst$$reg); 2056 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2057 %} 2058 #endif 2059 2060 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2061 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2062 MacroAssembler _masm(&cbuf); 2063 2064 Register p_reg = reg_to_register_object($p$$reg); 2065 Register q_reg = reg_to_register_object($q$$reg); 2066 Register y_reg = reg_to_register_object($y$$reg); 2067 Register tmp_reg = reg_to_register_object($tmp$$reg); 2068 2069 __ subcc( p_reg, q_reg, p_reg ); 2070 __ add ( p_reg, y_reg, tmp_reg ); 2071 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2072 %} 2073 2074 enc_class form_d2i_helper(regD src, regF dst) %{ 2075 // fcmp %fcc0,$src,$src 2076 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2077 // branch %fcc0 not-nan, predict taken 2078 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2079 // fdtoi $src,$dst 2080 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2081 // fitos $dst,$dst (if nan) 2082 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2083 // clear $dst (if nan) 2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2085 // carry on here... 2086 %} 2087 2088 enc_class form_d2l_helper(regD src, regD dst) %{ 2089 // fcmp %fcc0,$src,$src check for NAN 2090 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2091 // branch %fcc0 not-nan, predict taken 2092 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2093 // fdtox $src,$dst convert in delay slot 2094 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2095 // fxtod $dst,$dst (if nan) 2096 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2097 // clear $dst (if nan) 2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2099 // carry on here... 2100 %} 2101 2102 enc_class form_f2i_helper(regF src, regF dst) %{ 2103 // fcmps %fcc0,$src,$src 2104 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2105 // branch %fcc0 not-nan, predict taken 2106 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2107 // fstoi $src,$dst 2108 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2109 // fitos $dst,$dst (if nan) 2110 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2111 // clear $dst (if nan) 2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2113 // carry on here... 2114 %} 2115 2116 enc_class form_f2l_helper(regF src, regD dst) %{ 2117 // fcmps %fcc0,$src,$src 2118 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2119 // branch %fcc0 not-nan, predict taken 2120 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2121 // fstox $src,$dst 2122 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2123 // fxtod $dst,$dst (if nan) 2124 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2125 // clear $dst (if nan) 2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2127 // carry on here... 2128 %} 2129 2130 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2131 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2132 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2133 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2134 2135 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2136 2137 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2138 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2139 2140 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2141 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2142 %} 2143 2144 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2146 %} 2147 2148 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2149 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2150 %} 2151 2152 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2154 %} 2155 2156 enc_class form3_convI2F(regF rs2, regF rd) %{ 2157 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2158 %} 2159 2160 // Encloding class for traceable jumps 2161 enc_class form_jmpl(g3RegP dest) %{ 2162 emit_jmpl(cbuf, $dest$$reg); 2163 %} 2164 2165 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2166 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2167 %} 2168 2169 enc_class form2_nop() %{ 2170 emit_nop(cbuf); 2171 %} 2172 2173 enc_class form2_illtrap() %{ 2174 emit_illtrap(cbuf); 2175 %} 2176 2177 2178 // Compare longs and convert into -1, 0, 1. 2179 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2180 // CMP $src1,$src2 2181 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2182 // blt,a,pn done 2183 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2184 // mov dst,-1 in delay slot 2185 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2186 // bgt,a,pn done 2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2188 // mov dst,1 in delay slot 2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2190 // CLR $dst 2191 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2192 %} 2193 2194 enc_class enc_PartialSubtypeCheck() %{ 2195 MacroAssembler _masm(&cbuf); 2196 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2197 __ delayed()->nop(); 2198 %} 2199 2200 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2201 MacroAssembler _masm(&cbuf); 2202 Label &L = *($labl$$label); 2203 Assembler::Predict predict_taken = 2204 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2205 2206 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2207 __ delayed()->nop(); 2208 %} 2209 2210 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2211 MacroAssembler _masm(&cbuf); 2212 Label &L = *($labl$$label); 2213 Assembler::Predict predict_taken = 2214 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2215 2216 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2217 __ delayed()->nop(); 2218 %} 2219 2220 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2221 MacroAssembler _masm(&cbuf); 2222 Label &L = *($labl$$label); 2223 Assembler::Predict predict_taken = 2224 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2225 2226 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2227 __ delayed()->nop(); 2228 %} 2229 2230 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2231 MacroAssembler _masm(&cbuf); 2232 Label &L = *($labl$$label); 2233 Assembler::Predict predict_taken = 2234 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2235 2236 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2237 __ delayed()->nop(); 2238 %} 2239 2240 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ 2241 MacroAssembler _masm(&cbuf); 2242 2243 Register switch_reg = as_Register($switch_val$$reg); 2244 Register table_reg = O7; 2245 2246 address table_base = __ address_table_constant(_index2label); 2247 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2248 2249 // Move table address into a register. 2250 __ set(table_base, table_reg, rspec); 2251 2252 // Jump to base address + switch value 2253 __ ld_ptr(table_reg, switch_reg, table_reg); 2254 __ jmp(table_reg, G0); 2255 __ delayed()->nop(); 2256 2257 %} 2258 2259 enc_class enc_ba( Label labl ) %{ 2260 MacroAssembler _masm(&cbuf); 2261 Label &L = *($labl$$label); 2262 __ ba(false, L); 2263 __ delayed()->nop(); 2264 %} 2265 2266 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2267 MacroAssembler _masm(&cbuf); 2268 Label &L = *$labl$$label; 2269 Assembler::Predict predict_taken = 2270 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2271 2272 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2273 __ delayed()->nop(); 2274 %} 2275 2276 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2277 int op = (Assembler::arith_op << 30) | 2278 ($dst$$reg << 25) | 2279 (Assembler::movcc_op3 << 19) | 2280 (1 << 18) | // cc2 bit for 'icc' 2281 ($cmp$$cmpcode << 14) | 2282 (0 << 13) | // select register move 2283 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2284 ($src$$reg << 0); 2285 *((int*)(cbuf.code_end())) = op; 2286 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2287 %} 2288 2289 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2290 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2291 int op = (Assembler::arith_op << 30) | 2292 ($dst$$reg << 25) | 2293 (Assembler::movcc_op3 << 19) | 2294 (1 << 18) | // cc2 bit for 'icc' 2295 ($cmp$$cmpcode << 14) | 2296 (1 << 13) | // select immediate move 2297 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2298 (simm11 << 0); 2299 *((int*)(cbuf.code_end())) = op; 2300 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2301 %} 2302 2303 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2304 int op = (Assembler::arith_op << 30) | 2305 ($dst$$reg << 25) | 2306 (Assembler::movcc_op3 << 19) | 2307 (0 << 18) | // cc2 bit for 'fccX' 2308 ($cmp$$cmpcode << 14) | 2309 (0 << 13) | // select register move 2310 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2311 ($src$$reg << 0); 2312 *((int*)(cbuf.code_end())) = op; 2313 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2314 %} 2315 2316 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2317 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2318 int op = (Assembler::arith_op << 30) | 2319 ($dst$$reg << 25) | 2320 (Assembler::movcc_op3 << 19) | 2321 (0 << 18) | // cc2 bit for 'fccX' 2322 ($cmp$$cmpcode << 14) | 2323 (1 << 13) | // select immediate move 2324 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2325 (simm11 << 0); 2326 *((int*)(cbuf.code_end())) = op; 2327 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2328 %} 2329 2330 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2331 int op = (Assembler::arith_op << 30) | 2332 ($dst$$reg << 25) | 2333 (Assembler::fpop2_op3 << 19) | 2334 (0 << 18) | 2335 ($cmp$$cmpcode << 14) | 2336 (1 << 13) | // select register move 2337 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2338 ($primary << 5) | // select single, double or quad 2339 ($src$$reg << 0); 2340 *((int*)(cbuf.code_end())) = op; 2341 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2342 %} 2343 2344 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2345 int op = (Assembler::arith_op << 30) | 2346 ($dst$$reg << 25) | 2347 (Assembler::fpop2_op3 << 19) | 2348 (0 << 18) | 2349 ($cmp$$cmpcode << 14) | 2350 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2351 ($primary << 5) | // select single, double or quad 2352 ($src$$reg << 0); 2353 *((int*)(cbuf.code_end())) = op; 2354 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2355 %} 2356 2357 // Used by the MIN/MAX encodings. Same as a CMOV, but 2358 // the condition comes from opcode-field instead of an argument. 2359 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2360 int op = (Assembler::arith_op << 30) | 2361 ($dst$$reg << 25) | 2362 (Assembler::movcc_op3 << 19) | 2363 (1 << 18) | // cc2 bit for 'icc' 2364 ($primary << 14) | 2365 (0 << 13) | // select register move 2366 (0 << 11) | // cc1, cc0 bits for 'icc' 2367 ($src$$reg << 0); 2368 *((int*)(cbuf.code_end())) = op; 2369 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2370 %} 2371 2372 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2373 int op = (Assembler::arith_op << 30) | 2374 ($dst$$reg << 25) | 2375 (Assembler::movcc_op3 << 19) | 2376 (6 << 16) | // cc2 bit for 'xcc' 2377 ($primary << 14) | 2378 (0 << 13) | // select register move 2379 (0 << 11) | // cc1, cc0 bits for 'icc' 2380 ($src$$reg << 0); 2381 *((int*)(cbuf.code_end())) = op; 2382 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2383 %} 2384 2385 // Utility encoding for loading a 64 bit Pointer into a register 2386 // The 64 bit pointer is stored in the generated code stream 2387 enc_class SetPtr( immP src, iRegP rd ) %{ 2388 Register dest = reg_to_register_object($rd$$reg); 2389 MacroAssembler _masm(&cbuf); 2390 // [RGV] This next line should be generated from ADLC 2391 if ( _opnds[1]->constant_is_oop() ) { 2392 intptr_t val = $src$$constant; 2393 __ set_oop_constant((jobject)val, dest); 2394 } else { // non-oop pointers, e.g. card mark base, heap top 2395 __ set($src$$constant, dest); 2396 } 2397 %} 2398 2399 enc_class Set13( immI13 src, iRegI rd ) %{ 2400 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2401 %} 2402 2403 enc_class SetHi22( immI src, iRegI rd ) %{ 2404 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2405 %} 2406 2407 enc_class Set32( immI src, iRegI rd ) %{ 2408 MacroAssembler _masm(&cbuf); 2409 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2410 %} 2411 2412 enc_class SetNull( iRegI rd ) %{ 2413 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); 2414 %} 2415 2416 enc_class call_epilog %{ 2417 if( VerifyStackAtCalls ) { 2418 MacroAssembler _masm(&cbuf); 2419 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2420 Register temp_reg = G3; 2421 __ add(SP, framesize, temp_reg); 2422 __ cmp(temp_reg, FP); 2423 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2424 } 2425 %} 2426 2427 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2428 // to G1 so the register allocator will not have to deal with the misaligned register 2429 // pair. 2430 enc_class adjust_long_from_native_call %{ 2431 #ifndef _LP64 2432 if (returns_long()) { 2433 // sllx O0,32,O0 2434 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2435 // srl O1,0,O1 2436 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2437 // or O0,O1,G1 2438 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2439 } 2440 #endif 2441 %} 2442 2443 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2444 // CALL directly to the runtime 2445 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2446 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2447 /*preserve_g2=*/true, /*force far call*/true); 2448 %} 2449 2450 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2451 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2452 // who we intended to call. 2453 if ( !_method ) { 2454 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2455 } else if (_optimized_virtual) { 2456 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2457 } else { 2458 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2459 } 2460 if( _method ) { // Emit stub for static call 2461 emit_java_to_interp(cbuf); 2462 } 2463 %} 2464 2465 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2466 MacroAssembler _masm(&cbuf); 2467 __ set_inst_mark(); 2468 int vtable_index = this->_vtable_index; 2469 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2470 if (vtable_index < 0) { 2471 // must be invalid_vtable_index, not nonvirtual_vtable_index 2472 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2473 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2474 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2475 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2476 // !!!!! 2477 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2478 // emit_call_dynamic_prologue( cbuf ); 2479 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2480 2481 address virtual_call_oop_addr = __ inst_mark(); 2482 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2483 // who we intended to call. 2484 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2485 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2486 } else { 2487 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2488 // Just go thru the vtable 2489 // get receiver klass (receiver already checked for non-null) 2490 // If we end up going thru a c2i adapter interpreter expects method in G5 2491 int off = __ offset(); 2492 __ load_klass(O0, G3_scratch); 2493 int klass_load_size; 2494 if (UseCompressedOops) { 2495 assert(Universe::heap() != NULL, "java heap should be initialized"); 2496 if (Universe::narrow_oop_base() == NULL) 2497 klass_load_size = 2*BytesPerInstWord; 2498 else 2499 klass_load_size = 3*BytesPerInstWord; 2500 } else { 2501 klass_load_size = 1*BytesPerInstWord; 2502 } 2503 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2504 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2505 if( __ is_simm13(v_off) ) { 2506 __ ld_ptr(G3, v_off, G5_method); 2507 } else { 2508 // Generate 2 instructions 2509 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2510 __ or3(G5_method, v_off & 0x3ff, G5_method); 2511 // ld_ptr, set_hi, set 2512 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2513 "Unexpected instruction size(s)"); 2514 __ ld_ptr(G3, G5_method, G5_method); 2515 } 2516 // NOTE: for vtable dispatches, the vtable entry will never be null. 2517 // However it may very well end up in handle_wrong_method if the 2518 // method is abstract for the particular class. 2519 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2520 // jump to target (either compiled code or c2iadapter) 2521 __ jmpl(G3_scratch, G0, O7); 2522 __ delayed()->nop(); 2523 } 2524 %} 2525 2526 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2527 MacroAssembler _masm(&cbuf); 2528 2529 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2530 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2531 // we might be calling a C2I adapter which needs it. 2532 2533 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2534 // Load nmethod 2535 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2536 2537 // CALL to compiled java, indirect the contents of G3 2538 __ set_inst_mark(); 2539 __ callr(temp_reg, G0); 2540 __ delayed()->nop(); 2541 %} 2542 2543 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2544 MacroAssembler _masm(&cbuf); 2545 Register Rdividend = reg_to_register_object($src1$$reg); 2546 Register Rdivisor = reg_to_register_object($src2$$reg); 2547 Register Rresult = reg_to_register_object($dst$$reg); 2548 2549 __ sra(Rdivisor, 0, Rdivisor); 2550 __ sra(Rdividend, 0, Rdividend); 2551 __ sdivx(Rdividend, Rdivisor, Rresult); 2552 %} 2553 2554 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2555 MacroAssembler _masm(&cbuf); 2556 2557 Register Rdividend = reg_to_register_object($src1$$reg); 2558 int divisor = $imm$$constant; 2559 Register Rresult = reg_to_register_object($dst$$reg); 2560 2561 __ sra(Rdividend, 0, Rdividend); 2562 __ sdivx(Rdividend, divisor, Rresult); 2563 %} 2564 2565 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2566 MacroAssembler _masm(&cbuf); 2567 Register Rsrc1 = reg_to_register_object($src1$$reg); 2568 Register Rsrc2 = reg_to_register_object($src2$$reg); 2569 Register Rdst = reg_to_register_object($dst$$reg); 2570 2571 __ sra( Rsrc1, 0, Rsrc1 ); 2572 __ sra( Rsrc2, 0, Rsrc2 ); 2573 __ mulx( Rsrc1, Rsrc2, Rdst ); 2574 __ srlx( Rdst, 32, Rdst ); 2575 %} 2576 2577 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2578 MacroAssembler _masm(&cbuf); 2579 Register Rdividend = reg_to_register_object($src1$$reg); 2580 Register Rdivisor = reg_to_register_object($src2$$reg); 2581 Register Rresult = reg_to_register_object($dst$$reg); 2582 Register Rscratch = reg_to_register_object($scratch$$reg); 2583 2584 assert(Rdividend != Rscratch, ""); 2585 assert(Rdivisor != Rscratch, ""); 2586 2587 __ sra(Rdividend, 0, Rdividend); 2588 __ sra(Rdivisor, 0, Rdivisor); 2589 __ sdivx(Rdividend, Rdivisor, Rscratch); 2590 __ mulx(Rscratch, Rdivisor, Rscratch); 2591 __ sub(Rdividend, Rscratch, Rresult); 2592 %} 2593 2594 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2595 MacroAssembler _masm(&cbuf); 2596 2597 Register Rdividend = reg_to_register_object($src1$$reg); 2598 int divisor = $imm$$constant; 2599 Register Rresult = reg_to_register_object($dst$$reg); 2600 Register Rscratch = reg_to_register_object($scratch$$reg); 2601 2602 assert(Rdividend != Rscratch, ""); 2603 2604 __ sra(Rdividend, 0, Rdividend); 2605 __ sdivx(Rdividend, divisor, Rscratch); 2606 __ mulx(Rscratch, divisor, Rscratch); 2607 __ sub(Rdividend, Rscratch, Rresult); 2608 %} 2609 2610 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2611 MacroAssembler _masm(&cbuf); 2612 2613 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2614 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2615 2616 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2617 %} 2618 2619 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2620 MacroAssembler _masm(&cbuf); 2621 2622 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2623 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2624 2625 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2626 %} 2627 2628 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2629 MacroAssembler _masm(&cbuf); 2630 2631 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2632 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2633 2634 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2635 %} 2636 2637 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2638 MacroAssembler _masm(&cbuf); 2639 2640 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2641 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2642 2643 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2644 %} 2645 2646 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2647 MacroAssembler _masm(&cbuf); 2648 2649 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2650 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2651 2652 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2653 %} 2654 2655 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2656 MacroAssembler _masm(&cbuf); 2657 2658 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2659 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2660 2661 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2662 %} 2663 2664 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2665 MacroAssembler _masm(&cbuf); 2666 2667 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2668 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2669 2670 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2671 %} 2672 2673 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2674 MacroAssembler _masm(&cbuf); 2675 2676 Register Roop = reg_to_register_object($oop$$reg); 2677 Register Rbox = reg_to_register_object($box$$reg); 2678 Register Rscratch = reg_to_register_object($scratch$$reg); 2679 Register Rmark = reg_to_register_object($scratch2$$reg); 2680 2681 assert(Roop != Rscratch, ""); 2682 assert(Roop != Rmark, ""); 2683 assert(Rbox != Rscratch, ""); 2684 assert(Rbox != Rmark, ""); 2685 2686 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2687 %} 2688 2689 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2690 MacroAssembler _masm(&cbuf); 2691 2692 Register Roop = reg_to_register_object($oop$$reg); 2693 Register Rbox = reg_to_register_object($box$$reg); 2694 Register Rscratch = reg_to_register_object($scratch$$reg); 2695 Register Rmark = reg_to_register_object($scratch2$$reg); 2696 2697 assert(Roop != Rscratch, ""); 2698 assert(Roop != Rmark, ""); 2699 assert(Rbox != Rscratch, ""); 2700 assert(Rbox != Rmark, ""); 2701 2702 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2703 %} 2704 2705 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2706 MacroAssembler _masm(&cbuf); 2707 Register Rmem = reg_to_register_object($mem$$reg); 2708 Register Rold = reg_to_register_object($old$$reg); 2709 Register Rnew = reg_to_register_object($new$$reg); 2710 2711 // casx_under_lock picks 1 of 3 encodings: 2712 // For 32-bit pointers you get a 32-bit CAS 2713 // For 64-bit pointers you get a 64-bit CASX 2714 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2715 __ cmp( Rold, Rnew ); 2716 %} 2717 2718 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2719 Register Rmem = reg_to_register_object($mem$$reg); 2720 Register Rold = reg_to_register_object($old$$reg); 2721 Register Rnew = reg_to_register_object($new$$reg); 2722 2723 MacroAssembler _masm(&cbuf); 2724 __ mov(Rnew, O7); 2725 __ casx(Rmem, Rold, O7); 2726 __ cmp( Rold, O7 ); 2727 %} 2728 2729 // raw int cas, used for compareAndSwap 2730 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2731 Register Rmem = reg_to_register_object($mem$$reg); 2732 Register Rold = reg_to_register_object($old$$reg); 2733 Register Rnew = reg_to_register_object($new$$reg); 2734 2735 MacroAssembler _masm(&cbuf); 2736 __ mov(Rnew, O7); 2737 __ cas(Rmem, Rold, O7); 2738 __ cmp( Rold, O7 ); 2739 %} 2740 2741 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2742 Register Rres = reg_to_register_object($res$$reg); 2743 2744 MacroAssembler _masm(&cbuf); 2745 __ mov(1, Rres); 2746 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2747 %} 2748 2749 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2750 Register Rres = reg_to_register_object($res$$reg); 2751 2752 MacroAssembler _masm(&cbuf); 2753 __ mov(1, Rres); 2754 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2755 %} 2756 2757 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2758 MacroAssembler _masm(&cbuf); 2759 Register Rdst = reg_to_register_object($dst$$reg); 2760 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2761 : reg_to_DoubleFloatRegister_object($src1$$reg); 2762 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2763 : reg_to_DoubleFloatRegister_object($src2$$reg); 2764 2765 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2766 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2767 %} 2768 2769 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate 2770 MacroAssembler _masm(&cbuf); 2771 Register dest = reg_to_register_object($dst$$reg); 2772 Register temp = reg_to_register_object($tmp$$reg); 2773 __ set64( $src$$constant, dest, temp ); 2774 %} 2775 2776 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2777 // Load a constant replicated "count" times with width "width" 2778 int bit_width = $width$$constant * 8; 2779 jlong elt_val = $src$$constant; 2780 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2781 jlong val = elt_val; 2782 for (int i = 0; i < $count$$constant - 1; i++) { 2783 val <<= bit_width; 2784 val |= elt_val; 2785 } 2786 jdouble dval = *(jdouble*)&val; // coerce to double type 2787 MacroAssembler _masm(&cbuf); 2788 address double_address = __ double_constant(dval); 2789 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2790 AddressLiteral addrlit(double_address, rspec); 2791 2792 __ sethi(addrlit, $tmp$$Register); 2793 // XXX This is a quick fix for 6833573. 2794 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 2795 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 2796 %} 2797 2798 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2799 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2800 MacroAssembler _masm(&cbuf); 2801 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2802 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2803 Register base_pointer_arg = reg_to_register_object($base$$reg); 2804 2805 Label loop; 2806 __ mov(nof_bytes_arg, nof_bytes_tmp); 2807 2808 // Loop and clear, walking backwards through the array. 2809 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2810 __ bind(loop); 2811 __ deccc(nof_bytes_tmp, 8); 2812 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2813 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2814 // %%%% this mini-loop must not cross a cache boundary! 2815 %} 2816 2817 2818 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2819 Label Ldone, Lloop; 2820 MacroAssembler _masm(&cbuf); 2821 2822 Register str1_reg = reg_to_register_object($str1$$reg); 2823 Register str2_reg = reg_to_register_object($str2$$reg); 2824 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2825 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2826 Register result_reg = reg_to_register_object($result$$reg); 2827 2828 assert(result_reg != str1_reg && 2829 result_reg != str2_reg && 2830 result_reg != cnt1_reg && 2831 result_reg != cnt2_reg , 2832 "need different registers"); 2833 2834 // Compute the minimum of the string lengths(str1_reg) and the 2835 // difference of the string lengths (stack) 2836 2837 // See if the lengths are different, and calculate min in str1_reg. 2838 // Stash diff in O7 in case we need it for a tie-breaker. 2839 Label Lskip; 2840 __ subcc(cnt1_reg, cnt2_reg, O7); 2841 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2842 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2843 // cnt2 is shorter, so use its count: 2844 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2845 __ bind(Lskip); 2846 2847 // reallocate cnt1_reg, cnt2_reg, result_reg 2848 // Note: limit_reg holds the string length pre-scaled by 2 2849 Register limit_reg = cnt1_reg; 2850 Register chr2_reg = cnt2_reg; 2851 Register chr1_reg = result_reg; 2852 // str{12} are the base pointers 2853 2854 // Is the minimum length zero? 2855 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2856 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2857 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2858 2859 // Load first characters 2860 __ lduh(str1_reg, 0, chr1_reg); 2861 __ lduh(str2_reg, 0, chr2_reg); 2862 2863 // Compare first characters 2864 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2865 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2866 assert(chr1_reg == result_reg, "result must be pre-placed"); 2867 __ delayed()->nop(); 2868 2869 { 2870 // Check after comparing first character to see if strings are equivalent 2871 Label LSkip2; 2872 // Check if the strings start at same location 2873 __ cmp(str1_reg, str2_reg); 2874 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2875 __ delayed()->nop(); 2876 2877 // Check if the length difference is zero (in O7) 2878 __ cmp(G0, O7); 2879 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2880 __ delayed()->mov(G0, result_reg); // result is zero 2881 2882 // Strings might not be equal 2883 __ bind(LSkip2); 2884 } 2885 2886 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2887 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2888 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2889 2890 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2891 __ add(str1_reg, limit_reg, str1_reg); 2892 __ add(str2_reg, limit_reg, str2_reg); 2893 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2894 2895 // Compare the rest of the characters 2896 __ lduh(str1_reg, limit_reg, chr1_reg); 2897 __ bind(Lloop); 2898 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2899 __ lduh(str2_reg, limit_reg, chr2_reg); 2900 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2901 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2902 assert(chr1_reg == result_reg, "result must be pre-placed"); 2903 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2904 // annul LDUH if branch is not taken to prevent access past end of string 2905 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2906 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2907 2908 // If strings are equal up to min length, return the length difference. 2909 __ mov(O7, result_reg); 2910 2911 // Otherwise, return the difference between the first mismatched chars. 2912 __ bind(Ldone); 2913 %} 2914 2915 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2916 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2917 MacroAssembler _masm(&cbuf); 2918 2919 Register str1_reg = reg_to_register_object($str1$$reg); 2920 Register str2_reg = reg_to_register_object($str2$$reg); 2921 Register cnt_reg = reg_to_register_object($cnt$$reg); 2922 Register tmp1_reg = O7; 2923 Register result_reg = reg_to_register_object($result$$reg); 2924 2925 assert(result_reg != str1_reg && 2926 result_reg != str2_reg && 2927 result_reg != cnt_reg && 2928 result_reg != tmp1_reg , 2929 "need different registers"); 2930 2931 __ cmp(str1_reg, str2_reg); //same char[] ? 2932 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2933 __ delayed()->add(G0, 1, result_reg); 2934 2935 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); 2936 __ delayed()->add(G0, 1, result_reg); // count == 0 2937 2938 //rename registers 2939 Register limit_reg = cnt_reg; 2940 Register chr1_reg = result_reg; 2941 Register chr2_reg = tmp1_reg; 2942 2943 //check for alignment and position the pointers to the ends 2944 __ or3(str1_reg, str2_reg, chr1_reg); 2945 __ andcc(chr1_reg, 0x3, chr1_reg); 2946 // notZero means at least one not 4-byte aligned. 2947 // We could optimize the case when both arrays are not aligned 2948 // but it is not frequent case and it requires additional checks. 2949 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 2950 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 2951 2952 // Compare char[] arrays aligned to 4 bytes. 2953 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 2954 chr1_reg, chr2_reg, Ldone); 2955 __ ba(false,Ldone); 2956 __ delayed()->add(G0, 1, result_reg); 2957 2958 // char by char compare 2959 __ bind(Lchar); 2960 __ add(str1_reg, limit_reg, str1_reg); 2961 __ add(str2_reg, limit_reg, str2_reg); 2962 __ neg(limit_reg); //negate count 2963 2964 __ lduh(str1_reg, limit_reg, chr1_reg); 2965 // Lchar_loop 2966 __ bind(Lchar_loop); 2967 __ lduh(str2_reg, limit_reg, chr2_reg); 2968 __ cmp(chr1_reg, chr2_reg); 2969 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 2970 __ delayed()->mov(G0, result_reg); //not equal 2971 __ inccc(limit_reg, sizeof(jchar)); 2972 // annul LDUH if branch is not taken to prevent access past end of string 2973 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 2974 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2975 2976 __ add(G0, 1, result_reg); //equal 2977 2978 __ bind(Ldone); 2979 %} 2980 2981 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 2982 Label Lvector, Ldone, Lloop; 2983 MacroAssembler _masm(&cbuf); 2984 2985 Register ary1_reg = reg_to_register_object($ary1$$reg); 2986 Register ary2_reg = reg_to_register_object($ary2$$reg); 2987 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2988 Register tmp2_reg = O7; 2989 Register result_reg = reg_to_register_object($result$$reg); 2990 2991 int length_offset = arrayOopDesc::length_offset_in_bytes(); 2992 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 2993 2994 // return true if the same array 2995 __ cmp(ary1_reg, ary2_reg); 2996 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2997 __ delayed()->add(G0, 1, result_reg); // equal 2998 2999 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3000 __ delayed()->mov(G0, result_reg); // not equal 3001 3002 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3003 __ delayed()->mov(G0, result_reg); // not equal 3004 3005 //load the lengths of arrays 3006 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3007 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3008 3009 // return false if the two arrays are not equal length 3010 __ cmp(tmp1_reg, tmp2_reg); 3011 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3012 __ delayed()->mov(G0, result_reg); // not equal 3013 3014 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); 3015 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3016 3017 // load array addresses 3018 __ add(ary1_reg, base_offset, ary1_reg); 3019 __ add(ary2_reg, base_offset, ary2_reg); 3020 3021 // renaming registers 3022 Register chr1_reg = result_reg; // for characters in ary1 3023 Register chr2_reg = tmp2_reg; // for characters in ary2 3024 Register limit_reg = tmp1_reg; // length 3025 3026 // set byte count 3027 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3028 3029 // Compare char[] arrays aligned to 4 bytes. 3030 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3031 chr1_reg, chr2_reg, Ldone); 3032 __ add(G0, 1, result_reg); // equals 3033 3034 __ bind(Ldone); 3035 %} 3036 3037 enc_class enc_rethrow() %{ 3038 cbuf.set_inst_mark(); 3039 Register temp_reg = G3; 3040 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3041 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3042 MacroAssembler _masm(&cbuf); 3043 #ifdef ASSERT 3044 __ save_frame(0); 3045 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3046 __ sethi(last_rethrow_addrlit, L1); 3047 Address addr(L1, last_rethrow_addrlit.low10()); 3048 __ get_pc(L2); 3049 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3050 __ st_ptr(L2, addr); 3051 __ restore(); 3052 #endif 3053 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3054 __ delayed()->nop(); 3055 %} 3056 3057 enc_class emit_mem_nop() %{ 3058 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3059 unsigned int *code = (unsigned int*)cbuf.code_end(); 3060 *code = (unsigned int)0xc0839040; 3061 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3062 %} 3063 3064 enc_class emit_fadd_nop() %{ 3065 // Generates the instruction FMOVS f31,f31 3066 unsigned int *code = (unsigned int*)cbuf.code_end(); 3067 *code = (unsigned int)0xbfa0003f; 3068 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3069 %} 3070 3071 enc_class emit_br_nop() %{ 3072 // Generates the instruction BPN,PN . 3073 unsigned int *code = (unsigned int*)cbuf.code_end(); 3074 *code = (unsigned int)0x00400000; 3075 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3076 %} 3077 3078 enc_class enc_membar_acquire %{ 3079 MacroAssembler _masm(&cbuf); 3080 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3081 %} 3082 3083 enc_class enc_membar_release %{ 3084 MacroAssembler _masm(&cbuf); 3085 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3086 %} 3087 3088 enc_class enc_membar_volatile %{ 3089 MacroAssembler _masm(&cbuf); 3090 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3091 %} 3092 3093 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3094 MacroAssembler _masm(&cbuf); 3095 Register src_reg = reg_to_register_object($src$$reg); 3096 Register dst_reg = reg_to_register_object($dst$$reg); 3097 __ sllx(src_reg, 56, dst_reg); 3098 __ srlx(dst_reg, 8, O7); 3099 __ or3 (dst_reg, O7, dst_reg); 3100 __ srlx(dst_reg, 16, O7); 3101 __ or3 (dst_reg, O7, dst_reg); 3102 __ srlx(dst_reg, 32, O7); 3103 __ or3 (dst_reg, O7, dst_reg); 3104 %} 3105 3106 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3107 MacroAssembler _masm(&cbuf); 3108 Register src_reg = reg_to_register_object($src$$reg); 3109 Register dst_reg = reg_to_register_object($dst$$reg); 3110 __ sll(src_reg, 24, dst_reg); 3111 __ srl(dst_reg, 8, O7); 3112 __ or3(dst_reg, O7, dst_reg); 3113 __ srl(dst_reg, 16, O7); 3114 __ or3(dst_reg, O7, dst_reg); 3115 %} 3116 3117 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3118 MacroAssembler _masm(&cbuf); 3119 Register src_reg = reg_to_register_object($src$$reg); 3120 Register dst_reg = reg_to_register_object($dst$$reg); 3121 __ sllx(src_reg, 48, dst_reg); 3122 __ srlx(dst_reg, 16, O7); 3123 __ or3 (dst_reg, O7, dst_reg); 3124 __ srlx(dst_reg, 32, O7); 3125 __ or3 (dst_reg, O7, dst_reg); 3126 %} 3127 3128 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3129 MacroAssembler _masm(&cbuf); 3130 Register src_reg = reg_to_register_object($src$$reg); 3131 Register dst_reg = reg_to_register_object($dst$$reg); 3132 __ sllx(src_reg, 32, dst_reg); 3133 __ srlx(dst_reg, 32, O7); 3134 __ or3 (dst_reg, O7, dst_reg); 3135 %} 3136 3137 %} 3138 3139 //----------FRAME-------------------------------------------------------------- 3140 // Definition of frame structure and management information. 3141 // 3142 // S T A C K L A Y O U T Allocators stack-slot number 3143 // | (to get allocators register number 3144 // G Owned by | | v add VMRegImpl::stack0) 3145 // r CALLER | | 3146 // o | +--------+ pad to even-align allocators stack-slot 3147 // w V | pad0 | numbers; owned by CALLER 3148 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3149 // h ^ | in | 5 3150 // | | args | 4 Holes in incoming args owned by SELF 3151 // | | | | 3 3152 // | | +--------+ 3153 // V | | old out| Empty on Intel, window on Sparc 3154 // | old |preserve| Must be even aligned. 3155 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3156 // | | in | 3 area for Intel ret address 3157 // Owned by |preserve| Empty on Sparc. 3158 // SELF +--------+ 3159 // | | pad2 | 2 pad to align old SP 3160 // | +--------+ 1 3161 // | | locks | 0 3162 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3163 // | | pad1 | 11 pad to align new SP 3164 // | +--------+ 3165 // | | | 10 3166 // | | spills | 9 spills 3167 // V | | 8 (pad0 slot for callee) 3168 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3169 // ^ | out | 7 3170 // | | args | 6 Holes in outgoing args owned by CALLEE 3171 // Owned by +--------+ 3172 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3173 // | new |preserve| Must be even-aligned. 3174 // | SP-+--------+----> Matcher::_new_SP, even aligned 3175 // | | | 3176 // 3177 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3178 // known from SELF's arguments and the Java calling convention. 3179 // Region 6-7 is determined per call site. 3180 // Note 2: If the calling convention leaves holes in the incoming argument 3181 // area, those holes are owned by SELF. Holes in the outgoing area 3182 // are owned by the CALLEE. Holes should not be nessecary in the 3183 // incoming area, as the Java calling convention is completely under 3184 // the control of the AD file. Doubles can be sorted and packed to 3185 // avoid holes. Holes in the outgoing arguments may be nessecary for 3186 // varargs C calling conventions. 3187 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3188 // even aligned with pad0 as needed. 3189 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3190 // region 6-11 is even aligned; it may be padded out more so that 3191 // the region from SP to FP meets the minimum stack alignment. 3192 3193 frame %{ 3194 // What direction does stack grow in (assumed to be same for native & Java) 3195 stack_direction(TOWARDS_LOW); 3196 3197 // These two registers define part of the calling convention 3198 // between compiled code and the interpreter. 3199 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3200 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3201 3202 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3203 cisc_spilling_operand_name(indOffset); 3204 3205 // Number of stack slots consumed by a Monitor enter 3206 #ifdef _LP64 3207 sync_stack_slots(2); 3208 #else 3209 sync_stack_slots(1); 3210 #endif 3211 3212 // Compiled code's Frame Pointer 3213 frame_pointer(R_SP); 3214 3215 // Stack alignment requirement 3216 stack_alignment(StackAlignmentInBytes); 3217 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3218 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3219 3220 // Number of stack slots between incoming argument block and the start of 3221 // a new frame. The PROLOG must add this many slots to the stack. The 3222 // EPILOG must remove this many slots. 3223 in_preserve_stack_slots(0); 3224 3225 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3226 // for calls to C. Supports the var-args backing area for register parms. 3227 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3228 #ifdef _LP64 3229 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3230 varargs_C_out_slots_killed(12); 3231 #else 3232 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3233 varargs_C_out_slots_killed( 7); 3234 #endif 3235 3236 // The after-PROLOG location of the return address. Location of 3237 // return address specifies a type (REG or STACK) and a number 3238 // representing the register number (i.e. - use a register name) or 3239 // stack slot. 3240 return_addr(REG R_I7); // Ret Addr is in register I7 3241 3242 // Body of function which returns an OptoRegs array locating 3243 // arguments either in registers or in stack slots for calling 3244 // java 3245 calling_convention %{ 3246 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3247 3248 %} 3249 3250 // Body of function which returns an OptoRegs array locating 3251 // arguments either in registers or in stack slots for callin 3252 // C. 3253 c_calling_convention %{ 3254 // This is obviously always outgoing 3255 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3256 %} 3257 3258 // Location of native (C/C++) and interpreter return values. This is specified to 3259 // be the same as Java. In the 32-bit VM, long values are actually returned from 3260 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3261 // to and from the register pairs is done by the appropriate call and epilog 3262 // opcodes. This simplifies the register allocator. 3263 c_return_value %{ 3264 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3265 #ifdef _LP64 3266 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3267 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3268 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3269 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3270 #else // !_LP64 3271 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3272 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3273 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3274 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3275 #endif 3276 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3277 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3278 %} 3279 3280 // Location of compiled Java return values. Same as C 3281 return_value %{ 3282 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3283 #ifdef _LP64 3284 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3285 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3286 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3287 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3288 #else // !_LP64 3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3293 #endif 3294 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3295 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3296 %} 3297 3298 %} 3299 3300 3301 //----------ATTRIBUTES--------------------------------------------------------- 3302 //----------Operand Attributes------------------------------------------------- 3303 op_attrib op_cost(1); // Required cost attribute 3304 3305 //----------Instruction Attributes--------------------------------------------- 3306 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3307 ins_attrib ins_size(32); // Required size attribute (in bits) 3308 ins_attrib ins_pc_relative(0); // Required PC Relative flag 3309 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3310 // non-matching short branch variant of some 3311 // long branch? 3312 3313 //----------OPERANDS----------------------------------------------------------- 3314 // Operand definitions must precede instruction definitions for correct parsing 3315 // in the ADLC because operands constitute user defined types which are used in 3316 // instruction definitions. 3317 3318 //----------Simple Operands---------------------------------------------------- 3319 // Immediate Operands 3320 // Integer Immediate: 32-bit 3321 operand immI() %{ 3322 match(ConI); 3323 3324 op_cost(0); 3325 // formats are generated automatically for constants and base registers 3326 format %{ %} 3327 interface(CONST_INTER); 3328 %} 3329 3330 // Integer Immediate: 8-bit 3331 operand immI8() %{ 3332 predicate(Assembler::is_simm(n->get_int(), 8)); 3333 match(ConI); 3334 op_cost(0); 3335 format %{ %} 3336 interface(CONST_INTER); 3337 %} 3338 3339 // Integer Immediate: 13-bit 3340 operand immI13() %{ 3341 predicate(Assembler::is_simm13(n->get_int())); 3342 match(ConI); 3343 op_cost(0); 3344 3345 format %{ %} 3346 interface(CONST_INTER); 3347 %} 3348 3349 // Integer Immediate: 13-bit minus 7 3350 operand immI13m7() %{ 3351 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3352 match(ConI); 3353 op_cost(0); 3354 3355 format %{ %} 3356 interface(CONST_INTER); 3357 %} 3358 3359 // Integer Immediate: 16-bit 3360 operand immI16() %{ 3361 predicate(Assembler::is_simm(n->get_int(), 16)); 3362 match(ConI); 3363 op_cost(0); 3364 format %{ %} 3365 interface(CONST_INTER); 3366 %} 3367 3368 // Unsigned (positive) Integer Immediate: 13-bit 3369 operand immU13() %{ 3370 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3371 match(ConI); 3372 op_cost(0); 3373 3374 format %{ %} 3375 interface(CONST_INTER); 3376 %} 3377 3378 // Integer Immediate: 6-bit 3379 operand immU6() %{ 3380 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3381 match(ConI); 3382 op_cost(0); 3383 format %{ %} 3384 interface(CONST_INTER); 3385 %} 3386 3387 // Integer Immediate: 11-bit 3388 operand immI11() %{ 3389 predicate(Assembler::is_simm(n->get_int(),11)); 3390 match(ConI); 3391 op_cost(0); 3392 format %{ %} 3393 interface(CONST_INTER); 3394 %} 3395 3396 // Integer Immediate: 0-bit 3397 operand immI0() %{ 3398 predicate(n->get_int() == 0); 3399 match(ConI); 3400 op_cost(0); 3401 3402 format %{ %} 3403 interface(CONST_INTER); 3404 %} 3405 3406 // Integer Immediate: the value 10 3407 operand immI10() %{ 3408 predicate(n->get_int() == 10); 3409 match(ConI); 3410 op_cost(0); 3411 3412 format %{ %} 3413 interface(CONST_INTER); 3414 %} 3415 3416 // Integer Immediate: the values 0-31 3417 operand immU5() %{ 3418 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3419 match(ConI); 3420 op_cost(0); 3421 3422 format %{ %} 3423 interface(CONST_INTER); 3424 %} 3425 3426 // Integer Immediate: the values 1-31 3427 operand immI_1_31() %{ 3428 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3429 match(ConI); 3430 op_cost(0); 3431 3432 format %{ %} 3433 interface(CONST_INTER); 3434 %} 3435 3436 // Integer Immediate: the values 32-63 3437 operand immI_32_63() %{ 3438 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3439 match(ConI); 3440 op_cost(0); 3441 3442 format %{ %} 3443 interface(CONST_INTER); 3444 %} 3445 3446 // Immediates for special shifts (sign extend) 3447 3448 // Integer Immediate: the value 16 3449 operand immI_16() %{ 3450 predicate(n->get_int() == 16); 3451 match(ConI); 3452 op_cost(0); 3453 3454 format %{ %} 3455 interface(CONST_INTER); 3456 %} 3457 3458 // Integer Immediate: the value 24 3459 operand immI_24() %{ 3460 predicate(n->get_int() == 24); 3461 match(ConI); 3462 op_cost(0); 3463 3464 format %{ %} 3465 interface(CONST_INTER); 3466 %} 3467 3468 // Integer Immediate: the value 255 3469 operand immI_255() %{ 3470 predicate( n->get_int() == 255 ); 3471 match(ConI); 3472 op_cost(0); 3473 3474 format %{ %} 3475 interface(CONST_INTER); 3476 %} 3477 3478 // Integer Immediate: the value 65535 3479 operand immI_65535() %{ 3480 predicate(n->get_int() == 65535); 3481 match(ConI); 3482 op_cost(0); 3483 3484 format %{ %} 3485 interface(CONST_INTER); 3486 %} 3487 3488 // Long Immediate: the value FF 3489 operand immL_FF() %{ 3490 predicate( n->get_long() == 0xFFL ); 3491 match(ConL); 3492 op_cost(0); 3493 3494 format %{ %} 3495 interface(CONST_INTER); 3496 %} 3497 3498 // Long Immediate: the value FFFF 3499 operand immL_FFFF() %{ 3500 predicate( n->get_long() == 0xFFFFL ); 3501 match(ConL); 3502 op_cost(0); 3503 3504 format %{ %} 3505 interface(CONST_INTER); 3506 %} 3507 3508 // Pointer Immediate: 32 or 64-bit 3509 operand immP() %{ 3510 match(ConP); 3511 3512 op_cost(5); 3513 // formats are generated automatically for constants and base registers 3514 format %{ %} 3515 interface(CONST_INTER); 3516 %} 3517 3518 operand immP13() %{ 3519 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3520 match(ConP); 3521 op_cost(0); 3522 3523 format %{ %} 3524 interface(CONST_INTER); 3525 %} 3526 3527 operand immP0() %{ 3528 predicate(n->get_ptr() == 0); 3529 match(ConP); 3530 op_cost(0); 3531 3532 format %{ %} 3533 interface(CONST_INTER); 3534 %} 3535 3536 operand immP_poll() %{ 3537 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3538 match(ConP); 3539 3540 // formats are generated automatically for constants and base registers 3541 format %{ %} 3542 interface(CONST_INTER); 3543 %} 3544 3545 // Pointer Immediate 3546 operand immN() 3547 %{ 3548 match(ConN); 3549 3550 op_cost(10); 3551 format %{ %} 3552 interface(CONST_INTER); 3553 %} 3554 3555 // NULL Pointer Immediate 3556 operand immN0() 3557 %{ 3558 predicate(n->get_narrowcon() == 0); 3559 match(ConN); 3560 3561 op_cost(0); 3562 format %{ %} 3563 interface(CONST_INTER); 3564 %} 3565 3566 operand immL() %{ 3567 match(ConL); 3568 op_cost(40); 3569 // formats are generated automatically for constants and base registers 3570 format %{ %} 3571 interface(CONST_INTER); 3572 %} 3573 3574 operand immL0() %{ 3575 predicate(n->get_long() == 0L); 3576 match(ConL); 3577 op_cost(0); 3578 // formats are generated automatically for constants and base registers 3579 format %{ %} 3580 interface(CONST_INTER); 3581 %} 3582 3583 // Long Immediate: 13-bit 3584 operand immL13() %{ 3585 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3586 match(ConL); 3587 op_cost(0); 3588 3589 format %{ %} 3590 interface(CONST_INTER); 3591 %} 3592 3593 // Long Immediate: 13-bit minus 7 3594 operand immL13m7() %{ 3595 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3596 match(ConL); 3597 op_cost(0); 3598 3599 format %{ %} 3600 interface(CONST_INTER); 3601 %} 3602 3603 // Long Immediate: low 32-bit mask 3604 operand immL_32bits() %{ 3605 predicate(n->get_long() == 0xFFFFFFFFL); 3606 match(ConL); 3607 op_cost(0); 3608 3609 format %{ %} 3610 interface(CONST_INTER); 3611 %} 3612 3613 // Double Immediate 3614 operand immD() %{ 3615 match(ConD); 3616 3617 op_cost(40); 3618 format %{ %} 3619 interface(CONST_INTER); 3620 %} 3621 3622 operand immD0() %{ 3623 #ifdef _LP64 3624 // on 64-bit architectures this comparision is faster 3625 predicate(jlong_cast(n->getd()) == 0); 3626 #else 3627 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3628 #endif 3629 match(ConD); 3630 3631 op_cost(0); 3632 format %{ %} 3633 interface(CONST_INTER); 3634 %} 3635 3636 // Float Immediate 3637 operand immF() %{ 3638 match(ConF); 3639 3640 op_cost(20); 3641 format %{ %} 3642 interface(CONST_INTER); 3643 %} 3644 3645 // Float Immediate: 0 3646 operand immF0() %{ 3647 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3648 match(ConF); 3649 3650 op_cost(0); 3651 format %{ %} 3652 interface(CONST_INTER); 3653 %} 3654 3655 // Integer Register Operands 3656 // Integer Register 3657 operand iRegI() %{ 3658 constraint(ALLOC_IN_RC(int_reg)); 3659 match(RegI); 3660 3661 match(notemp_iRegI); 3662 match(g1RegI); 3663 match(o0RegI); 3664 match(iRegIsafe); 3665 3666 format %{ %} 3667 interface(REG_INTER); 3668 %} 3669 3670 operand notemp_iRegI() %{ 3671 constraint(ALLOC_IN_RC(notemp_int_reg)); 3672 match(RegI); 3673 3674 match(o0RegI); 3675 3676 format %{ %} 3677 interface(REG_INTER); 3678 %} 3679 3680 operand o0RegI() %{ 3681 constraint(ALLOC_IN_RC(o0_regI)); 3682 match(iRegI); 3683 3684 format %{ %} 3685 interface(REG_INTER); 3686 %} 3687 3688 // Pointer Register 3689 operand iRegP() %{ 3690 constraint(ALLOC_IN_RC(ptr_reg)); 3691 match(RegP); 3692 3693 match(lock_ptr_RegP); 3694 match(g1RegP); 3695 match(g2RegP); 3696 match(g3RegP); 3697 match(g4RegP); 3698 match(i0RegP); 3699 match(o0RegP); 3700 match(o1RegP); 3701 match(l7RegP); 3702 3703 format %{ %} 3704 interface(REG_INTER); 3705 %} 3706 3707 operand sp_ptr_RegP() %{ 3708 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3709 match(RegP); 3710 match(iRegP); 3711 3712 format %{ %} 3713 interface(REG_INTER); 3714 %} 3715 3716 operand lock_ptr_RegP() %{ 3717 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3718 match(RegP); 3719 match(i0RegP); 3720 match(o0RegP); 3721 match(o1RegP); 3722 match(l7RegP); 3723 3724 format %{ %} 3725 interface(REG_INTER); 3726 %} 3727 3728 operand g1RegP() %{ 3729 constraint(ALLOC_IN_RC(g1_regP)); 3730 match(iRegP); 3731 3732 format %{ %} 3733 interface(REG_INTER); 3734 %} 3735 3736 operand g2RegP() %{ 3737 constraint(ALLOC_IN_RC(g2_regP)); 3738 match(iRegP); 3739 3740 format %{ %} 3741 interface(REG_INTER); 3742 %} 3743 3744 operand g3RegP() %{ 3745 constraint(ALLOC_IN_RC(g3_regP)); 3746 match(iRegP); 3747 3748 format %{ %} 3749 interface(REG_INTER); 3750 %} 3751 3752 operand g1RegI() %{ 3753 constraint(ALLOC_IN_RC(g1_regI)); 3754 match(iRegI); 3755 3756 format %{ %} 3757 interface(REG_INTER); 3758 %} 3759 3760 operand g3RegI() %{ 3761 constraint(ALLOC_IN_RC(g3_regI)); 3762 match(iRegI); 3763 3764 format %{ %} 3765 interface(REG_INTER); 3766 %} 3767 3768 operand g4RegI() %{ 3769 constraint(ALLOC_IN_RC(g4_regI)); 3770 match(iRegI); 3771 3772 format %{ %} 3773 interface(REG_INTER); 3774 %} 3775 3776 operand g4RegP() %{ 3777 constraint(ALLOC_IN_RC(g4_regP)); 3778 match(iRegP); 3779 3780 format %{ %} 3781 interface(REG_INTER); 3782 %} 3783 3784 operand i0RegP() %{ 3785 constraint(ALLOC_IN_RC(i0_regP)); 3786 match(iRegP); 3787 3788 format %{ %} 3789 interface(REG_INTER); 3790 %} 3791 3792 operand o0RegP() %{ 3793 constraint(ALLOC_IN_RC(o0_regP)); 3794 match(iRegP); 3795 3796 format %{ %} 3797 interface(REG_INTER); 3798 %} 3799 3800 operand o1RegP() %{ 3801 constraint(ALLOC_IN_RC(o1_regP)); 3802 match(iRegP); 3803 3804 format %{ %} 3805 interface(REG_INTER); 3806 %} 3807 3808 operand o2RegP() %{ 3809 constraint(ALLOC_IN_RC(o2_regP)); 3810 match(iRegP); 3811 3812 format %{ %} 3813 interface(REG_INTER); 3814 %} 3815 3816 operand o7RegP() %{ 3817 constraint(ALLOC_IN_RC(o7_regP)); 3818 match(iRegP); 3819 3820 format %{ %} 3821 interface(REG_INTER); 3822 %} 3823 3824 operand l7RegP() %{ 3825 constraint(ALLOC_IN_RC(l7_regP)); 3826 match(iRegP); 3827 3828 format %{ %} 3829 interface(REG_INTER); 3830 %} 3831 3832 operand o7RegI() %{ 3833 constraint(ALLOC_IN_RC(o7_regI)); 3834 match(iRegI); 3835 3836 format %{ %} 3837 interface(REG_INTER); 3838 %} 3839 3840 operand iRegN() %{ 3841 constraint(ALLOC_IN_RC(int_reg)); 3842 match(RegN); 3843 3844 format %{ %} 3845 interface(REG_INTER); 3846 %} 3847 3848 // Long Register 3849 operand iRegL() %{ 3850 constraint(ALLOC_IN_RC(long_reg)); 3851 match(RegL); 3852 3853 format %{ %} 3854 interface(REG_INTER); 3855 %} 3856 3857 operand o2RegL() %{ 3858 constraint(ALLOC_IN_RC(o2_regL)); 3859 match(iRegL); 3860 3861 format %{ %} 3862 interface(REG_INTER); 3863 %} 3864 3865 operand o7RegL() %{ 3866 constraint(ALLOC_IN_RC(o7_regL)); 3867 match(iRegL); 3868 3869 format %{ %} 3870 interface(REG_INTER); 3871 %} 3872 3873 operand g1RegL() %{ 3874 constraint(ALLOC_IN_RC(g1_regL)); 3875 match(iRegL); 3876 3877 format %{ %} 3878 interface(REG_INTER); 3879 %} 3880 3881 operand g3RegL() %{ 3882 constraint(ALLOC_IN_RC(g3_regL)); 3883 match(iRegL); 3884 3885 format %{ %} 3886 interface(REG_INTER); 3887 %} 3888 3889 // Int Register safe 3890 // This is 64bit safe 3891 operand iRegIsafe() %{ 3892 constraint(ALLOC_IN_RC(long_reg)); 3893 3894 match(iRegI); 3895 3896 format %{ %} 3897 interface(REG_INTER); 3898 %} 3899 3900 // Condition Code Flag Register 3901 operand flagsReg() %{ 3902 constraint(ALLOC_IN_RC(int_flags)); 3903 match(RegFlags); 3904 3905 format %{ "ccr" %} // both ICC and XCC 3906 interface(REG_INTER); 3907 %} 3908 3909 // Condition Code Register, unsigned comparisons. 3910 operand flagsRegU() %{ 3911 constraint(ALLOC_IN_RC(int_flags)); 3912 match(RegFlags); 3913 3914 format %{ "icc_U" %} 3915 interface(REG_INTER); 3916 %} 3917 3918 // Condition Code Register, pointer comparisons. 3919 operand flagsRegP() %{ 3920 constraint(ALLOC_IN_RC(int_flags)); 3921 match(RegFlags); 3922 3923 #ifdef _LP64 3924 format %{ "xcc_P" %} 3925 #else 3926 format %{ "icc_P" %} 3927 #endif 3928 interface(REG_INTER); 3929 %} 3930 3931 // Condition Code Register, long comparisons. 3932 operand flagsRegL() %{ 3933 constraint(ALLOC_IN_RC(int_flags)); 3934 match(RegFlags); 3935 3936 format %{ "xcc_L" %} 3937 interface(REG_INTER); 3938 %} 3939 3940 // Condition Code Register, floating comparisons, unordered same as "less". 3941 operand flagsRegF() %{ 3942 constraint(ALLOC_IN_RC(float_flags)); 3943 match(RegFlags); 3944 match(flagsRegF0); 3945 3946 format %{ %} 3947 interface(REG_INTER); 3948 %} 3949 3950 operand flagsRegF0() %{ 3951 constraint(ALLOC_IN_RC(float_flag0)); 3952 match(RegFlags); 3953 3954 format %{ %} 3955 interface(REG_INTER); 3956 %} 3957 3958 3959 // Condition Code Flag Register used by long compare 3960 operand flagsReg_long_LTGE() %{ 3961 constraint(ALLOC_IN_RC(int_flags)); 3962 match(RegFlags); 3963 format %{ "icc_LTGE" %} 3964 interface(REG_INTER); 3965 %} 3966 operand flagsReg_long_EQNE() %{ 3967 constraint(ALLOC_IN_RC(int_flags)); 3968 match(RegFlags); 3969 format %{ "icc_EQNE" %} 3970 interface(REG_INTER); 3971 %} 3972 operand flagsReg_long_LEGT() %{ 3973 constraint(ALLOC_IN_RC(int_flags)); 3974 match(RegFlags); 3975 format %{ "icc_LEGT" %} 3976 interface(REG_INTER); 3977 %} 3978 3979 3980 operand regD() %{ 3981 constraint(ALLOC_IN_RC(dflt_reg)); 3982 match(RegD); 3983 3984 match(regD_low); 3985 3986 format %{ %} 3987 interface(REG_INTER); 3988 %} 3989 3990 operand regF() %{ 3991 constraint(ALLOC_IN_RC(sflt_reg)); 3992 match(RegF); 3993 3994 format %{ %} 3995 interface(REG_INTER); 3996 %} 3997 3998 operand regD_low() %{ 3999 constraint(ALLOC_IN_RC(dflt_low_reg)); 4000 match(regD); 4001 4002 format %{ %} 4003 interface(REG_INTER); 4004 %} 4005 4006 // Special Registers 4007 4008 // Method Register 4009 operand inline_cache_regP(iRegP reg) %{ 4010 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4011 match(reg); 4012 format %{ %} 4013 interface(REG_INTER); 4014 %} 4015 4016 operand interpreter_method_oop_regP(iRegP reg) %{ 4017 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4018 match(reg); 4019 format %{ %} 4020 interface(REG_INTER); 4021 %} 4022 4023 4024 //----------Complex Operands--------------------------------------------------- 4025 // Indirect Memory Reference 4026 operand indirect(sp_ptr_RegP reg) %{ 4027 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4028 match(reg); 4029 4030 op_cost(100); 4031 format %{ "[$reg]" %} 4032 interface(MEMORY_INTER) %{ 4033 base($reg); 4034 index(0x0); 4035 scale(0x0); 4036 disp(0x0); 4037 %} 4038 %} 4039 4040 // Indirect with simm13 Offset 4041 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4042 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4043 match(AddP reg offset); 4044 4045 op_cost(100); 4046 format %{ "[$reg + $offset]" %} 4047 interface(MEMORY_INTER) %{ 4048 base($reg); 4049 index(0x0); 4050 scale(0x0); 4051 disp($offset); 4052 %} 4053 %} 4054 4055 // Indirect with simm13 Offset minus 7 4056 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4057 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4058 match(AddP reg offset); 4059 4060 op_cost(100); 4061 format %{ "[$reg + $offset]" %} 4062 interface(MEMORY_INTER) %{ 4063 base($reg); 4064 index(0x0); 4065 scale(0x0); 4066 disp($offset); 4067 %} 4068 %} 4069 4070 // Note: Intel has a swapped version also, like this: 4071 //operand indOffsetX(iRegI reg, immP offset) %{ 4072 // constraint(ALLOC_IN_RC(int_reg)); 4073 // match(AddP offset reg); 4074 // 4075 // op_cost(100); 4076 // format %{ "[$reg + $offset]" %} 4077 // interface(MEMORY_INTER) %{ 4078 // base($reg); 4079 // index(0x0); 4080 // scale(0x0); 4081 // disp($offset); 4082 // %} 4083 //%} 4084 //// However, it doesn't make sense for SPARC, since 4085 // we have no particularly good way to embed oops in 4086 // single instructions. 4087 4088 // Indirect with Register Index 4089 operand indIndex(iRegP addr, iRegX index) %{ 4090 constraint(ALLOC_IN_RC(ptr_reg)); 4091 match(AddP addr index); 4092 4093 op_cost(100); 4094 format %{ "[$addr + $index]" %} 4095 interface(MEMORY_INTER) %{ 4096 base($addr); 4097 index($index); 4098 scale(0x0); 4099 disp(0x0); 4100 %} 4101 %} 4102 4103 //----------Special Memory Operands-------------------------------------------- 4104 // Stack Slot Operand - This operand is used for loading and storing temporary 4105 // values on the stack where a match requires a value to 4106 // flow through memory. 4107 operand stackSlotI(sRegI reg) %{ 4108 constraint(ALLOC_IN_RC(stack_slots)); 4109 op_cost(100); 4110 //match(RegI); 4111 format %{ "[$reg]" %} 4112 interface(MEMORY_INTER) %{ 4113 base(0xE); // R_SP 4114 index(0x0); 4115 scale(0x0); 4116 disp($reg); // Stack Offset 4117 %} 4118 %} 4119 4120 operand stackSlotP(sRegP reg) %{ 4121 constraint(ALLOC_IN_RC(stack_slots)); 4122 op_cost(100); 4123 //match(RegP); 4124 format %{ "[$reg]" %} 4125 interface(MEMORY_INTER) %{ 4126 base(0xE); // R_SP 4127 index(0x0); 4128 scale(0x0); 4129 disp($reg); // Stack Offset 4130 %} 4131 %} 4132 4133 operand stackSlotF(sRegF reg) %{ 4134 constraint(ALLOC_IN_RC(stack_slots)); 4135 op_cost(100); 4136 //match(RegF); 4137 format %{ "[$reg]" %} 4138 interface(MEMORY_INTER) %{ 4139 base(0xE); // R_SP 4140 index(0x0); 4141 scale(0x0); 4142 disp($reg); // Stack Offset 4143 %} 4144 %} 4145 operand stackSlotD(sRegD reg) %{ 4146 constraint(ALLOC_IN_RC(stack_slots)); 4147 op_cost(100); 4148 //match(RegD); 4149 format %{ "[$reg]" %} 4150 interface(MEMORY_INTER) %{ 4151 base(0xE); // R_SP 4152 index(0x0); 4153 scale(0x0); 4154 disp($reg); // Stack Offset 4155 %} 4156 %} 4157 operand stackSlotL(sRegL reg) %{ 4158 constraint(ALLOC_IN_RC(stack_slots)); 4159 op_cost(100); 4160 //match(RegL); 4161 format %{ "[$reg]" %} 4162 interface(MEMORY_INTER) %{ 4163 base(0xE); // R_SP 4164 index(0x0); 4165 scale(0x0); 4166 disp($reg); // Stack Offset 4167 %} 4168 %} 4169 4170 // Operands for expressing Control Flow 4171 // NOTE: Label is a predefined operand which should not be redefined in 4172 // the AD file. It is generically handled within the ADLC. 4173 4174 //----------Conditional Branch Operands---------------------------------------- 4175 // Comparison Op - This is the operation of the comparison, and is limited to 4176 // the following set of codes: 4177 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4178 // 4179 // Other attributes of the comparison, such as unsignedness, are specified 4180 // by the comparison instruction that sets a condition code flags register. 4181 // That result is represented by a flags operand whose subtype is appropriate 4182 // to the unsignedness (etc.) of the comparison. 4183 // 4184 // Later, the instruction which matches both the Comparison Op (a Bool) and 4185 // the flags (produced by the Cmp) specifies the coding of the comparison op 4186 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4187 4188 operand cmpOp() %{ 4189 match(Bool); 4190 4191 format %{ "" %} 4192 interface(COND_INTER) %{ 4193 equal(0x1); 4194 not_equal(0x9); 4195 less(0x3); 4196 greater_equal(0xB); 4197 less_equal(0x2); 4198 greater(0xA); 4199 %} 4200 %} 4201 4202 // Comparison Op, unsigned 4203 operand cmpOpU() %{ 4204 match(Bool); 4205 4206 format %{ "u" %} 4207 interface(COND_INTER) %{ 4208 equal(0x1); 4209 not_equal(0x9); 4210 less(0x5); 4211 greater_equal(0xD); 4212 less_equal(0x4); 4213 greater(0xC); 4214 %} 4215 %} 4216 4217 // Comparison Op, pointer (same as unsigned) 4218 operand cmpOpP() %{ 4219 match(Bool); 4220 4221 format %{ "p" %} 4222 interface(COND_INTER) %{ 4223 equal(0x1); 4224 not_equal(0x9); 4225 less(0x5); 4226 greater_equal(0xD); 4227 less_equal(0x4); 4228 greater(0xC); 4229 %} 4230 %} 4231 4232 // Comparison Op, branch-register encoding 4233 operand cmpOp_reg() %{ 4234 match(Bool); 4235 4236 format %{ "" %} 4237 interface(COND_INTER) %{ 4238 equal (0x1); 4239 not_equal (0x5); 4240 less (0x3); 4241 greater_equal(0x7); 4242 less_equal (0x2); 4243 greater (0x6); 4244 %} 4245 %} 4246 4247 // Comparison Code, floating, unordered same as less 4248 operand cmpOpF() %{ 4249 match(Bool); 4250 4251 format %{ "fl" %} 4252 interface(COND_INTER) %{ 4253 equal(0x9); 4254 not_equal(0x1); 4255 less(0x3); 4256 greater_equal(0xB); 4257 less_equal(0xE); 4258 greater(0x6); 4259 %} 4260 %} 4261 4262 // Used by long compare 4263 operand cmpOp_commute() %{ 4264 match(Bool); 4265 4266 format %{ "" %} 4267 interface(COND_INTER) %{ 4268 equal(0x1); 4269 not_equal(0x9); 4270 less(0xA); 4271 greater_equal(0x2); 4272 less_equal(0xB); 4273 greater(0x3); 4274 %} 4275 %} 4276 4277 //----------OPERAND CLASSES---------------------------------------------------- 4278 // Operand Classes are groups of operands that are used to simplify 4279 // instruction definitions by not requiring the AD writer to specify separate 4280 // instructions for every form of operand when the instruction accepts 4281 // multiple operand types with the same basic encoding and format. The classic 4282 // case of this is memory operands. 4283 opclass memory( indirect, indOffset13, indIndex ); 4284 opclass indIndexMemory( indIndex ); 4285 4286 //----------PIPELINE----------------------------------------------------------- 4287 pipeline %{ 4288 4289 //----------ATTRIBUTES--------------------------------------------------------- 4290 attributes %{ 4291 fixed_size_instructions; // Fixed size instructions 4292 branch_has_delay_slot; // Branch has delay slot following 4293 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4294 instruction_unit_size = 4; // An instruction is 4 bytes long 4295 instruction_fetch_unit_size = 16; // The processor fetches one line 4296 instruction_fetch_units = 1; // of 16 bytes 4297 4298 // List of nop instructions 4299 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4300 %} 4301 4302 //----------RESOURCES---------------------------------------------------------- 4303 // Resources are the functional units available to the machine 4304 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4305 4306 //----------PIPELINE DESCRIPTION----------------------------------------------- 4307 // Pipeline Description specifies the stages in the machine's pipeline 4308 4309 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4310 4311 //----------PIPELINE CLASSES--------------------------------------------------- 4312 // Pipeline Classes describe the stages in which input and output are 4313 // referenced by the hardware pipeline. 4314 4315 // Integer ALU reg-reg operation 4316 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4317 single_instruction; 4318 dst : E(write); 4319 src1 : R(read); 4320 src2 : R(read); 4321 IALU : R; 4322 %} 4323 4324 // Integer ALU reg-reg long operation 4325 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4326 instruction_count(2); 4327 dst : E(write); 4328 src1 : R(read); 4329 src2 : R(read); 4330 IALU : R; 4331 IALU : R; 4332 %} 4333 4334 // Integer ALU reg-reg long dependent operation 4335 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4336 instruction_count(1); multiple_bundles; 4337 dst : E(write); 4338 src1 : R(read); 4339 src2 : R(read); 4340 cr : E(write); 4341 IALU : R(2); 4342 %} 4343 4344 // Integer ALU reg-imm operaion 4345 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4346 single_instruction; 4347 dst : E(write); 4348 src1 : R(read); 4349 IALU : R; 4350 %} 4351 4352 // Integer ALU reg-reg operation with condition code 4353 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4354 single_instruction; 4355 dst : E(write); 4356 cr : E(write); 4357 src1 : R(read); 4358 src2 : R(read); 4359 IALU : R; 4360 %} 4361 4362 // Integer ALU reg-imm operation with condition code 4363 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4364 single_instruction; 4365 dst : E(write); 4366 cr : E(write); 4367 src1 : R(read); 4368 IALU : R; 4369 %} 4370 4371 // Integer ALU zero-reg operation 4372 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4373 single_instruction; 4374 dst : E(write); 4375 src2 : R(read); 4376 IALU : R; 4377 %} 4378 4379 // Integer ALU zero-reg operation with condition code only 4380 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4381 single_instruction; 4382 cr : E(write); 4383 src : R(read); 4384 IALU : R; 4385 %} 4386 4387 // Integer ALU reg-reg operation with condition code only 4388 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4389 single_instruction; 4390 cr : E(write); 4391 src1 : R(read); 4392 src2 : R(read); 4393 IALU : R; 4394 %} 4395 4396 // Integer ALU reg-imm operation with condition code only 4397 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4398 single_instruction; 4399 cr : E(write); 4400 src1 : R(read); 4401 IALU : R; 4402 %} 4403 4404 // Integer ALU reg-reg-zero operation with condition code only 4405 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4406 single_instruction; 4407 cr : E(write); 4408 src1 : R(read); 4409 src2 : R(read); 4410 IALU : R; 4411 %} 4412 4413 // Integer ALU reg-imm-zero operation with condition code only 4414 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4415 single_instruction; 4416 cr : E(write); 4417 src1 : R(read); 4418 IALU : R; 4419 %} 4420 4421 // Integer ALU reg-reg operation with condition code, src1 modified 4422 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4423 single_instruction; 4424 cr : E(write); 4425 src1 : E(write); 4426 src1 : R(read); 4427 src2 : R(read); 4428 IALU : R; 4429 %} 4430 4431 // Integer ALU reg-imm operation with condition code, src1 modified 4432 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4433 single_instruction; 4434 cr : E(write); 4435 src1 : E(write); 4436 src1 : R(read); 4437 IALU : R; 4438 %} 4439 4440 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4441 multiple_bundles; 4442 dst : E(write)+4; 4443 cr : E(write); 4444 src1 : R(read); 4445 src2 : R(read); 4446 IALU : R(3); 4447 BR : R(2); 4448 %} 4449 4450 // Integer ALU operation 4451 pipe_class ialu_none(iRegI dst) %{ 4452 single_instruction; 4453 dst : E(write); 4454 IALU : R; 4455 %} 4456 4457 // Integer ALU reg operation 4458 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4459 single_instruction; may_have_no_code; 4460 dst : E(write); 4461 src : R(read); 4462 IALU : R; 4463 %} 4464 4465 // Integer ALU reg conditional operation 4466 // This instruction has a 1 cycle stall, and cannot execute 4467 // in the same cycle as the instruction setting the condition 4468 // code. We kludge this by pretending to read the condition code 4469 // 1 cycle earlier, and by marking the functional units as busy 4470 // for 2 cycles with the result available 1 cycle later than 4471 // is really the case. 4472 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4473 single_instruction; 4474 op2_out : C(write); 4475 op1 : R(read); 4476 cr : R(read); // This is really E, with a 1 cycle stall 4477 BR : R(2); 4478 MS : R(2); 4479 %} 4480 4481 #ifdef _LP64 4482 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4483 instruction_count(1); multiple_bundles; 4484 dst : C(write)+1; 4485 src : R(read)+1; 4486 IALU : R(1); 4487 BR : E(2); 4488 MS : E(2); 4489 %} 4490 #endif 4491 4492 // Integer ALU reg operation 4493 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4494 single_instruction; may_have_no_code; 4495 dst : E(write); 4496 src : R(read); 4497 IALU : R; 4498 %} 4499 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4500 single_instruction; may_have_no_code; 4501 dst : E(write); 4502 src : R(read); 4503 IALU : R; 4504 %} 4505 4506 // Two integer ALU reg operations 4507 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4508 instruction_count(2); 4509 dst : E(write); 4510 src : R(read); 4511 A0 : R; 4512 A1 : R; 4513 %} 4514 4515 // Two integer ALU reg operations 4516 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4517 instruction_count(2); may_have_no_code; 4518 dst : E(write); 4519 src : R(read); 4520 A0 : R; 4521 A1 : R; 4522 %} 4523 4524 // Integer ALU imm operation 4525 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4526 single_instruction; 4527 dst : E(write); 4528 IALU : R; 4529 %} 4530 4531 // Integer ALU reg-reg with carry operation 4532 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4533 single_instruction; 4534 dst : E(write); 4535 src1 : R(read); 4536 src2 : R(read); 4537 IALU : R; 4538 %} 4539 4540 // Integer ALU cc operation 4541 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4542 single_instruction; 4543 dst : E(write); 4544 cc : R(read); 4545 IALU : R; 4546 %} 4547 4548 // Integer ALU cc / second IALU operation 4549 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4550 instruction_count(1); multiple_bundles; 4551 dst : E(write)+1; 4552 src : R(read); 4553 IALU : R; 4554 %} 4555 4556 // Integer ALU cc / second IALU operation 4557 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4558 instruction_count(1); multiple_bundles; 4559 dst : E(write)+1; 4560 p : R(read); 4561 q : R(read); 4562 IALU : R; 4563 %} 4564 4565 // Integer ALU hi-lo-reg operation 4566 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4567 instruction_count(1); multiple_bundles; 4568 dst : E(write)+1; 4569 IALU : R(2); 4570 %} 4571 4572 // Float ALU hi-lo-reg operation (with temp) 4573 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4574 instruction_count(1); multiple_bundles; 4575 dst : E(write)+1; 4576 IALU : R(2); 4577 %} 4578 4579 // Long Constant 4580 pipe_class loadConL( iRegL dst, immL src ) %{ 4581 instruction_count(2); multiple_bundles; 4582 dst : E(write)+1; 4583 IALU : R(2); 4584 IALU : R(2); 4585 %} 4586 4587 // Pointer Constant 4588 pipe_class loadConP( iRegP dst, immP src ) %{ 4589 instruction_count(0); multiple_bundles; 4590 fixed_latency(6); 4591 %} 4592 4593 // Polling Address 4594 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4595 #ifdef _LP64 4596 instruction_count(0); multiple_bundles; 4597 fixed_latency(6); 4598 #else 4599 dst : E(write); 4600 IALU : R; 4601 #endif 4602 %} 4603 4604 // Long Constant small 4605 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4606 instruction_count(2); 4607 dst : E(write); 4608 IALU : R; 4609 IALU : R; 4610 %} 4611 4612 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4613 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4614 instruction_count(1); multiple_bundles; 4615 src : R(read); 4616 dst : M(write)+1; 4617 IALU : R; 4618 MS : E; 4619 %} 4620 4621 // Integer ALU nop operation 4622 pipe_class ialu_nop() %{ 4623 single_instruction; 4624 IALU : R; 4625 %} 4626 4627 // Integer ALU nop operation 4628 pipe_class ialu_nop_A0() %{ 4629 single_instruction; 4630 A0 : R; 4631 %} 4632 4633 // Integer ALU nop operation 4634 pipe_class ialu_nop_A1() %{ 4635 single_instruction; 4636 A1 : R; 4637 %} 4638 4639 // Integer Multiply reg-reg operation 4640 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4641 single_instruction; 4642 dst : E(write); 4643 src1 : R(read); 4644 src2 : R(read); 4645 MS : R(5); 4646 %} 4647 4648 // Integer Multiply reg-imm operation 4649 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4650 single_instruction; 4651 dst : E(write); 4652 src1 : R(read); 4653 MS : R(5); 4654 %} 4655 4656 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4657 single_instruction; 4658 dst : E(write)+4; 4659 src1 : R(read); 4660 src2 : R(read); 4661 MS : R(6); 4662 %} 4663 4664 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4665 single_instruction; 4666 dst : E(write)+4; 4667 src1 : R(read); 4668 MS : R(6); 4669 %} 4670 4671 // Integer Divide reg-reg 4672 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4673 instruction_count(1); multiple_bundles; 4674 dst : E(write); 4675 temp : E(write); 4676 src1 : R(read); 4677 src2 : R(read); 4678 temp : R(read); 4679 MS : R(38); 4680 %} 4681 4682 // Integer Divide reg-imm 4683 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4684 instruction_count(1); multiple_bundles; 4685 dst : E(write); 4686 temp : E(write); 4687 src1 : R(read); 4688 temp : R(read); 4689 MS : R(38); 4690 %} 4691 4692 // Long Divide 4693 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4694 dst : E(write)+71; 4695 src1 : R(read); 4696 src2 : R(read)+1; 4697 MS : R(70); 4698 %} 4699 4700 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4701 dst : E(write)+71; 4702 src1 : R(read); 4703 MS : R(70); 4704 %} 4705 4706 // Floating Point Add Float 4707 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4708 single_instruction; 4709 dst : X(write); 4710 src1 : E(read); 4711 src2 : E(read); 4712 FA : R; 4713 %} 4714 4715 // Floating Point Add Double 4716 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4717 single_instruction; 4718 dst : X(write); 4719 src1 : E(read); 4720 src2 : E(read); 4721 FA : R; 4722 %} 4723 4724 // Floating Point Conditional Move based on integer flags 4725 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4726 single_instruction; 4727 dst : X(write); 4728 src : E(read); 4729 cr : R(read); 4730 FA : R(2); 4731 BR : R(2); 4732 %} 4733 4734 // Floating Point Conditional Move based on integer flags 4735 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4736 single_instruction; 4737 dst : X(write); 4738 src : E(read); 4739 cr : R(read); 4740 FA : R(2); 4741 BR : R(2); 4742 %} 4743 4744 // Floating Point Multiply Float 4745 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4746 single_instruction; 4747 dst : X(write); 4748 src1 : E(read); 4749 src2 : E(read); 4750 FM : R; 4751 %} 4752 4753 // Floating Point Multiply Double 4754 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4755 single_instruction; 4756 dst : X(write); 4757 src1 : E(read); 4758 src2 : E(read); 4759 FM : R; 4760 %} 4761 4762 // Floating Point Divide Float 4763 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4764 single_instruction; 4765 dst : X(write); 4766 src1 : E(read); 4767 src2 : E(read); 4768 FM : R; 4769 FDIV : C(14); 4770 %} 4771 4772 // Floating Point Divide Double 4773 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4774 single_instruction; 4775 dst : X(write); 4776 src1 : E(read); 4777 src2 : E(read); 4778 FM : R; 4779 FDIV : C(17); 4780 %} 4781 4782 // Floating Point Move/Negate/Abs Float 4783 pipe_class faddF_reg(regF dst, regF src) %{ 4784 single_instruction; 4785 dst : W(write); 4786 src : E(read); 4787 FA : R(1); 4788 %} 4789 4790 // Floating Point Move/Negate/Abs Double 4791 pipe_class faddD_reg(regD dst, regD src) %{ 4792 single_instruction; 4793 dst : W(write); 4794 src : E(read); 4795 FA : R; 4796 %} 4797 4798 // Floating Point Convert F->D 4799 pipe_class fcvtF2D(regD dst, regF src) %{ 4800 single_instruction; 4801 dst : X(write); 4802 src : E(read); 4803 FA : R; 4804 %} 4805 4806 // Floating Point Convert I->D 4807 pipe_class fcvtI2D(regD dst, regF src) %{ 4808 single_instruction; 4809 dst : X(write); 4810 src : E(read); 4811 FA : R; 4812 %} 4813 4814 // Floating Point Convert LHi->D 4815 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4816 single_instruction; 4817 dst : X(write); 4818 src : E(read); 4819 FA : R; 4820 %} 4821 4822 // Floating Point Convert L->D 4823 pipe_class fcvtL2D(regD dst, regF src) %{ 4824 single_instruction; 4825 dst : X(write); 4826 src : E(read); 4827 FA : R; 4828 %} 4829 4830 // Floating Point Convert L->F 4831 pipe_class fcvtL2F(regD dst, regF src) %{ 4832 single_instruction; 4833 dst : X(write); 4834 src : E(read); 4835 FA : R; 4836 %} 4837 4838 // Floating Point Convert D->F 4839 pipe_class fcvtD2F(regD dst, regF src) %{ 4840 single_instruction; 4841 dst : X(write); 4842 src : E(read); 4843 FA : R; 4844 %} 4845 4846 // Floating Point Convert I->L 4847 pipe_class fcvtI2L(regD dst, regF src) %{ 4848 single_instruction; 4849 dst : X(write); 4850 src : E(read); 4851 FA : R; 4852 %} 4853 4854 // Floating Point Convert D->F 4855 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4856 instruction_count(1); multiple_bundles; 4857 dst : X(write)+6; 4858 src : E(read); 4859 FA : R; 4860 %} 4861 4862 // Floating Point Convert D->L 4863 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4864 instruction_count(1); multiple_bundles; 4865 dst : X(write)+6; 4866 src : E(read); 4867 FA : R; 4868 %} 4869 4870 // Floating Point Convert F->I 4871 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4872 instruction_count(1); multiple_bundles; 4873 dst : X(write)+6; 4874 src : E(read); 4875 FA : R; 4876 %} 4877 4878 // Floating Point Convert F->L 4879 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4880 instruction_count(1); multiple_bundles; 4881 dst : X(write)+6; 4882 src : E(read); 4883 FA : R; 4884 %} 4885 4886 // Floating Point Convert I->F 4887 pipe_class fcvtI2F(regF dst, regF src) %{ 4888 single_instruction; 4889 dst : X(write); 4890 src : E(read); 4891 FA : R; 4892 %} 4893 4894 // Floating Point Compare 4895 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4896 single_instruction; 4897 cr : X(write); 4898 src1 : E(read); 4899 src2 : E(read); 4900 FA : R; 4901 %} 4902 4903 // Floating Point Compare 4904 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4905 single_instruction; 4906 cr : X(write); 4907 src1 : E(read); 4908 src2 : E(read); 4909 FA : R; 4910 %} 4911 4912 // Floating Add Nop 4913 pipe_class fadd_nop() %{ 4914 single_instruction; 4915 FA : R; 4916 %} 4917 4918 // Integer Store to Memory 4919 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4920 single_instruction; 4921 mem : R(read); 4922 src : C(read); 4923 MS : R; 4924 %} 4925 4926 // Integer Store to Memory 4927 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4928 single_instruction; 4929 mem : R(read); 4930 src : C(read); 4931 MS : R; 4932 %} 4933 4934 // Integer Store Zero to Memory 4935 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4936 single_instruction; 4937 mem : R(read); 4938 MS : R; 4939 %} 4940 4941 // Special Stack Slot Store 4942 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4943 single_instruction; 4944 stkSlot : R(read); 4945 src : C(read); 4946 MS : R; 4947 %} 4948 4949 // Special Stack Slot Store 4950 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4951 instruction_count(2); multiple_bundles; 4952 stkSlot : R(read); 4953 src : C(read); 4954 MS : R(2); 4955 %} 4956 4957 // Float Store 4958 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4959 single_instruction; 4960 mem : R(read); 4961 src : C(read); 4962 MS : R; 4963 %} 4964 4965 // Float Store 4966 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4967 single_instruction; 4968 mem : R(read); 4969 MS : R; 4970 %} 4971 4972 // Double Store 4973 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4974 instruction_count(1); 4975 mem : R(read); 4976 src : C(read); 4977 MS : R; 4978 %} 4979 4980 // Double Store 4981 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4982 single_instruction; 4983 mem : R(read); 4984 MS : R; 4985 %} 4986 4987 // Special Stack Slot Float Store 4988 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4989 single_instruction; 4990 stkSlot : R(read); 4991 src : C(read); 4992 MS : R; 4993 %} 4994 4995 // Special Stack Slot Double Store 4996 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4997 single_instruction; 4998 stkSlot : R(read); 4999 src : C(read); 5000 MS : R; 5001 %} 5002 5003 // Integer Load (when sign bit propagation not needed) 5004 pipe_class iload_mem(iRegI dst, memory mem) %{ 5005 single_instruction; 5006 mem : R(read); 5007 dst : C(write); 5008 MS : R; 5009 %} 5010 5011 // Integer Load from stack operand 5012 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5013 single_instruction; 5014 mem : R(read); 5015 dst : C(write); 5016 MS : R; 5017 %} 5018 5019 // Integer Load (when sign bit propagation or masking is needed) 5020 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5021 single_instruction; 5022 mem : R(read); 5023 dst : M(write); 5024 MS : R; 5025 %} 5026 5027 // Float Load 5028 pipe_class floadF_mem(regF dst, memory mem) %{ 5029 single_instruction; 5030 mem : R(read); 5031 dst : M(write); 5032 MS : R; 5033 %} 5034 5035 // Float Load 5036 pipe_class floadD_mem(regD dst, memory mem) %{ 5037 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5038 mem : R(read); 5039 dst : M(write); 5040 MS : R; 5041 %} 5042 5043 // Float Load 5044 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5045 single_instruction; 5046 stkSlot : R(read); 5047 dst : M(write); 5048 MS : R; 5049 %} 5050 5051 // Float Load 5052 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5053 single_instruction; 5054 stkSlot : R(read); 5055 dst : M(write); 5056 MS : R; 5057 %} 5058 5059 // Memory Nop 5060 pipe_class mem_nop() %{ 5061 single_instruction; 5062 MS : R; 5063 %} 5064 5065 pipe_class sethi(iRegP dst, immI src) %{ 5066 single_instruction; 5067 dst : E(write); 5068 IALU : R; 5069 %} 5070 5071 pipe_class loadPollP(iRegP poll) %{ 5072 single_instruction; 5073 poll : R(read); 5074 MS : R; 5075 %} 5076 5077 pipe_class br(Universe br, label labl) %{ 5078 single_instruction_with_delay_slot; 5079 BR : R; 5080 %} 5081 5082 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5083 single_instruction_with_delay_slot; 5084 cr : E(read); 5085 BR : R; 5086 %} 5087 5088 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5089 single_instruction_with_delay_slot; 5090 op1 : E(read); 5091 BR : R; 5092 MS : R; 5093 %} 5094 5095 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5096 single_instruction_with_delay_slot; 5097 cr : E(read); 5098 BR : R; 5099 %} 5100 5101 pipe_class br_nop() %{ 5102 single_instruction; 5103 BR : R; 5104 %} 5105 5106 pipe_class simple_call(method meth) %{ 5107 instruction_count(2); multiple_bundles; force_serialization; 5108 fixed_latency(100); 5109 BR : R(1); 5110 MS : R(1); 5111 A0 : R(1); 5112 %} 5113 5114 pipe_class compiled_call(method meth) %{ 5115 instruction_count(1); multiple_bundles; force_serialization; 5116 fixed_latency(100); 5117 MS : R(1); 5118 %} 5119 5120 pipe_class call(method meth) %{ 5121 instruction_count(0); multiple_bundles; force_serialization; 5122 fixed_latency(100); 5123 %} 5124 5125 pipe_class tail_call(Universe ignore, label labl) %{ 5126 single_instruction; has_delay_slot; 5127 fixed_latency(100); 5128 BR : R(1); 5129 MS : R(1); 5130 %} 5131 5132 pipe_class ret(Universe ignore) %{ 5133 single_instruction; has_delay_slot; 5134 BR : R(1); 5135 MS : R(1); 5136 %} 5137 5138 pipe_class ret_poll(g3RegP poll) %{ 5139 instruction_count(3); has_delay_slot; 5140 poll : E(read); 5141 MS : R; 5142 %} 5143 5144 // The real do-nothing guy 5145 pipe_class empty( ) %{ 5146 instruction_count(0); 5147 %} 5148 5149 pipe_class long_memory_op() %{ 5150 instruction_count(0); multiple_bundles; force_serialization; 5151 fixed_latency(25); 5152 MS : R(1); 5153 %} 5154 5155 // Check-cast 5156 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5157 array : R(read); 5158 match : R(read); 5159 IALU : R(2); 5160 BR : R(2); 5161 MS : R; 5162 %} 5163 5164 // Convert FPU flags into +1,0,-1 5165 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5166 src1 : E(read); 5167 src2 : E(read); 5168 dst : E(write); 5169 FA : R; 5170 MS : R(2); 5171 BR : R(2); 5172 %} 5173 5174 // Compare for p < q, and conditionally add y 5175 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5176 p : E(read); 5177 q : E(read); 5178 y : E(read); 5179 IALU : R(3) 5180 %} 5181 5182 // Perform a compare, then move conditionally in a branch delay slot. 5183 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5184 src2 : E(read); 5185 srcdst : E(read); 5186 IALU : R; 5187 BR : R; 5188 %} 5189 5190 // Define the class for the Nop node 5191 define %{ 5192 MachNop = ialu_nop; 5193 %} 5194 5195 %} 5196 5197 //----------INSTRUCTIONS------------------------------------------------------- 5198 5199 //------------Special Stack Slot instructions - no match rules----------------- 5200 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5201 // No match rule to avoid chain rule match. 5202 effect(DEF dst, USE src); 5203 ins_cost(MEMORY_REF_COST); 5204 size(4); 5205 format %{ "LDF $src,$dst\t! stkI to regF" %} 5206 opcode(Assembler::ldf_op3); 5207 ins_encode(simple_form3_mem_reg(src, dst)); 5208 ins_pipe(floadF_stk); 5209 %} 5210 5211 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5212 // No match rule to avoid chain rule match. 5213 effect(DEF dst, USE src); 5214 ins_cost(MEMORY_REF_COST); 5215 size(4); 5216 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5217 opcode(Assembler::lddf_op3); 5218 ins_encode(simple_form3_mem_reg(src, dst)); 5219 ins_pipe(floadD_stk); 5220 %} 5221 5222 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5223 // No match rule to avoid chain rule match. 5224 effect(DEF dst, USE src); 5225 ins_cost(MEMORY_REF_COST); 5226 size(4); 5227 format %{ "STF $src,$dst\t! regF to stkI" %} 5228 opcode(Assembler::stf_op3); 5229 ins_encode(simple_form3_mem_reg(dst, src)); 5230 ins_pipe(fstoreF_stk_reg); 5231 %} 5232 5233 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5234 // No match rule to avoid chain rule match. 5235 effect(DEF dst, USE src); 5236 ins_cost(MEMORY_REF_COST); 5237 size(4); 5238 format %{ "STDF $src,$dst\t! regD to stkL" %} 5239 opcode(Assembler::stdf_op3); 5240 ins_encode(simple_form3_mem_reg(dst, src)); 5241 ins_pipe(fstoreD_stk_reg); 5242 %} 5243 5244 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5245 effect(DEF dst, USE src); 5246 ins_cost(MEMORY_REF_COST*2); 5247 size(8); 5248 format %{ "STW $src,$dst.hi\t! long\n\t" 5249 "STW R_G0,$dst.lo" %} 5250 opcode(Assembler::stw_op3); 5251 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5252 ins_pipe(lstoreI_stk_reg); 5253 %} 5254 5255 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5256 // No match rule to avoid chain rule match. 5257 effect(DEF dst, USE src); 5258 ins_cost(MEMORY_REF_COST); 5259 size(4); 5260 format %{ "STX $src,$dst\t! regL to stkD" %} 5261 opcode(Assembler::stx_op3); 5262 ins_encode(simple_form3_mem_reg( dst, src ) ); 5263 ins_pipe(istore_stk_reg); 5264 %} 5265 5266 //---------- Chain stack slots between similar types -------- 5267 5268 // Load integer from stack slot 5269 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5270 match(Set dst src); 5271 ins_cost(MEMORY_REF_COST); 5272 5273 size(4); 5274 format %{ "LDUW $src,$dst\t!stk" %} 5275 opcode(Assembler::lduw_op3); 5276 ins_encode(simple_form3_mem_reg( src, dst ) ); 5277 ins_pipe(iload_mem); 5278 %} 5279 5280 // Store integer to stack slot 5281 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5282 match(Set dst src); 5283 ins_cost(MEMORY_REF_COST); 5284 5285 size(4); 5286 format %{ "STW $src,$dst\t!stk" %} 5287 opcode(Assembler::stw_op3); 5288 ins_encode(simple_form3_mem_reg( dst, src ) ); 5289 ins_pipe(istore_mem_reg); 5290 %} 5291 5292 // Load long from stack slot 5293 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5294 match(Set dst src); 5295 5296 ins_cost(MEMORY_REF_COST); 5297 size(4); 5298 format %{ "LDX $src,$dst\t! long" %} 5299 opcode(Assembler::ldx_op3); 5300 ins_encode(simple_form3_mem_reg( src, dst ) ); 5301 ins_pipe(iload_mem); 5302 %} 5303 5304 // Store long to stack slot 5305 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5306 match(Set dst src); 5307 5308 ins_cost(MEMORY_REF_COST); 5309 size(4); 5310 format %{ "STX $src,$dst\t! long" %} 5311 opcode(Assembler::stx_op3); 5312 ins_encode(simple_form3_mem_reg( dst, src ) ); 5313 ins_pipe(istore_mem_reg); 5314 %} 5315 5316 #ifdef _LP64 5317 // Load pointer from stack slot, 64-bit encoding 5318 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5319 match(Set dst src); 5320 ins_cost(MEMORY_REF_COST); 5321 size(4); 5322 format %{ "LDX $src,$dst\t!ptr" %} 5323 opcode(Assembler::ldx_op3); 5324 ins_encode(simple_form3_mem_reg( src, dst ) ); 5325 ins_pipe(iload_mem); 5326 %} 5327 5328 // Store pointer to stack slot 5329 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5330 match(Set dst src); 5331 ins_cost(MEMORY_REF_COST); 5332 size(4); 5333 format %{ "STX $src,$dst\t!ptr" %} 5334 opcode(Assembler::stx_op3); 5335 ins_encode(simple_form3_mem_reg( dst, src ) ); 5336 ins_pipe(istore_mem_reg); 5337 %} 5338 #else // _LP64 5339 // Load pointer from stack slot, 32-bit encoding 5340 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5341 match(Set dst src); 5342 ins_cost(MEMORY_REF_COST); 5343 format %{ "LDUW $src,$dst\t!ptr" %} 5344 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5345 ins_encode(simple_form3_mem_reg( src, dst ) ); 5346 ins_pipe(iload_mem); 5347 %} 5348 5349 // Store pointer to stack slot 5350 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5351 match(Set dst src); 5352 ins_cost(MEMORY_REF_COST); 5353 format %{ "STW $src,$dst\t!ptr" %} 5354 opcode(Assembler::stw_op3, Assembler::ldst_op); 5355 ins_encode(simple_form3_mem_reg( dst, src ) ); 5356 ins_pipe(istore_mem_reg); 5357 %} 5358 #endif // _LP64 5359 5360 //------------Special Nop instructions for bundling - no match rules----------- 5361 // Nop using the A0 functional unit 5362 instruct Nop_A0() %{ 5363 ins_cost(0); 5364 5365 format %{ "NOP ! Alu Pipeline" %} 5366 opcode(Assembler::or_op3, Assembler::arith_op); 5367 ins_encode( form2_nop() ); 5368 ins_pipe(ialu_nop_A0); 5369 %} 5370 5371 // Nop using the A1 functional unit 5372 instruct Nop_A1( ) %{ 5373 ins_cost(0); 5374 5375 format %{ "NOP ! Alu Pipeline" %} 5376 opcode(Assembler::or_op3, Assembler::arith_op); 5377 ins_encode( form2_nop() ); 5378 ins_pipe(ialu_nop_A1); 5379 %} 5380 5381 // Nop using the memory functional unit 5382 instruct Nop_MS( ) %{ 5383 ins_cost(0); 5384 5385 format %{ "NOP ! Memory Pipeline" %} 5386 ins_encode( emit_mem_nop ); 5387 ins_pipe(mem_nop); 5388 %} 5389 5390 // Nop using the floating add functional unit 5391 instruct Nop_FA( ) %{ 5392 ins_cost(0); 5393 5394 format %{ "NOP ! Floating Add Pipeline" %} 5395 ins_encode( emit_fadd_nop ); 5396 ins_pipe(fadd_nop); 5397 %} 5398 5399 // Nop using the branch functional unit 5400 instruct Nop_BR( ) %{ 5401 ins_cost(0); 5402 5403 format %{ "NOP ! Branch Pipeline" %} 5404 ins_encode( emit_br_nop ); 5405 ins_pipe(br_nop); 5406 %} 5407 5408 //----------Load/Store/Move Instructions--------------------------------------- 5409 //----------Load Instructions-------------------------------------------------- 5410 // Load Byte (8bit signed) 5411 instruct loadB(iRegI dst, memory mem) %{ 5412 match(Set dst (LoadB mem)); 5413 ins_cost(MEMORY_REF_COST); 5414 5415 size(4); 5416 format %{ "LDSB $mem,$dst\t! byte" %} 5417 ins_encode %{ 5418 __ ldsb($mem$$Address, $dst$$Register); 5419 %} 5420 ins_pipe(iload_mask_mem); 5421 %} 5422 5423 // Load Byte (8bit signed) into a Long Register 5424 instruct loadB2L(iRegL dst, memory mem) %{ 5425 match(Set dst (ConvI2L (LoadB mem))); 5426 ins_cost(MEMORY_REF_COST); 5427 5428 size(4); 5429 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5430 ins_encode %{ 5431 __ ldsb($mem$$Address, $dst$$Register); 5432 %} 5433 ins_pipe(iload_mask_mem); 5434 %} 5435 5436 // Load Unsigned Byte (8bit UNsigned) into an int reg 5437 instruct loadUB(iRegI dst, memory mem) %{ 5438 match(Set dst (LoadUB mem)); 5439 ins_cost(MEMORY_REF_COST); 5440 5441 size(4); 5442 format %{ "LDUB $mem,$dst\t! ubyte" %} 5443 ins_encode %{ 5444 __ ldub($mem$$Address, $dst$$Register); 5445 %} 5446 ins_pipe(iload_mem); 5447 %} 5448 5449 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5450 instruct loadUB2L(iRegL dst, memory mem) %{ 5451 match(Set dst (ConvI2L (LoadUB mem))); 5452 ins_cost(MEMORY_REF_COST); 5453 5454 size(4); 5455 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5456 ins_encode %{ 5457 __ ldub($mem$$Address, $dst$$Register); 5458 %} 5459 ins_pipe(iload_mem); 5460 %} 5461 5462 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5463 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5464 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5465 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5466 5467 size(2*4); 5468 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5469 "AND $dst,$mask,$dst" %} 5470 ins_encode %{ 5471 __ ldub($mem$$Address, $dst$$Register); 5472 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5473 %} 5474 ins_pipe(iload_mem); 5475 %} 5476 5477 // Load Short (16bit signed) 5478 instruct loadS(iRegI dst, memory mem) %{ 5479 match(Set dst (LoadS mem)); 5480 ins_cost(MEMORY_REF_COST); 5481 5482 size(4); 5483 format %{ "LDSH $mem,$dst\t! short" %} 5484 ins_encode %{ 5485 __ ldsh($mem$$Address, $dst$$Register); 5486 %} 5487 ins_pipe(iload_mask_mem); 5488 %} 5489 5490 // Load Short (16 bit signed) to Byte (8 bit signed) 5491 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5492 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5493 ins_cost(MEMORY_REF_COST); 5494 5495 size(4); 5496 5497 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5498 ins_encode %{ 5499 __ ldsb($mem$$Address, $dst$$Register, 1); 5500 %} 5501 ins_pipe(iload_mask_mem); 5502 %} 5503 5504 // Load Short (16bit signed) into a Long Register 5505 instruct loadS2L(iRegL dst, memory mem) %{ 5506 match(Set dst (ConvI2L (LoadS mem))); 5507 ins_cost(MEMORY_REF_COST); 5508 5509 size(4); 5510 format %{ "LDSH $mem,$dst\t! short -> long" %} 5511 ins_encode %{ 5512 __ ldsh($mem$$Address, $dst$$Register); 5513 %} 5514 ins_pipe(iload_mask_mem); 5515 %} 5516 5517 // Load Unsigned Short/Char (16bit UNsigned) 5518 instruct loadUS(iRegI dst, memory mem) %{ 5519 match(Set dst (LoadUS mem)); 5520 ins_cost(MEMORY_REF_COST); 5521 5522 size(4); 5523 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5524 ins_encode %{ 5525 __ lduh($mem$$Address, $dst$$Register); 5526 %} 5527 ins_pipe(iload_mem); 5528 %} 5529 5530 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5531 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5532 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5533 ins_cost(MEMORY_REF_COST); 5534 5535 size(4); 5536 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5537 ins_encode %{ 5538 __ ldsb($mem$$Address, $dst$$Register, 1); 5539 %} 5540 ins_pipe(iload_mask_mem); 5541 %} 5542 5543 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5544 instruct loadUS2L(iRegL dst, memory mem) %{ 5545 match(Set dst (ConvI2L (LoadUS mem))); 5546 ins_cost(MEMORY_REF_COST); 5547 5548 size(4); 5549 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5550 ins_encode %{ 5551 __ lduh($mem$$Address, $dst$$Register); 5552 %} 5553 ins_pipe(iload_mem); 5554 %} 5555 5556 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5557 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5558 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5559 ins_cost(MEMORY_REF_COST); 5560 5561 size(4); 5562 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5563 ins_encode %{ 5564 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5565 %} 5566 ins_pipe(iload_mem); 5567 %} 5568 5569 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5570 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5571 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5572 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5573 5574 size(2*4); 5575 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5576 "AND $dst,$mask,$dst" %} 5577 ins_encode %{ 5578 Register Rdst = $dst$$Register; 5579 __ lduh($mem$$Address, Rdst); 5580 __ and3(Rdst, $mask$$constant, Rdst); 5581 %} 5582 ins_pipe(iload_mem); 5583 %} 5584 5585 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5586 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5587 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5588 effect(TEMP dst, TEMP tmp); 5589 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5590 5591 size((3+1)*4); // set may use two instructions. 5592 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5593 "SET $mask,$tmp\n\t" 5594 "AND $dst,$tmp,$dst" %} 5595 ins_encode %{ 5596 Register Rdst = $dst$$Register; 5597 Register Rtmp = $tmp$$Register; 5598 __ lduh($mem$$Address, Rdst); 5599 __ set($mask$$constant, Rtmp); 5600 __ and3(Rdst, Rtmp, Rdst); 5601 %} 5602 ins_pipe(iload_mem); 5603 %} 5604 5605 // Load Integer 5606 instruct loadI(iRegI dst, memory mem) %{ 5607 match(Set dst (LoadI mem)); 5608 ins_cost(MEMORY_REF_COST); 5609 5610 size(4); 5611 format %{ "LDUW $mem,$dst\t! int" %} 5612 ins_encode %{ 5613 __ lduw($mem$$Address, $dst$$Register); 5614 %} 5615 ins_pipe(iload_mem); 5616 %} 5617 5618 // Load Integer to Byte (8 bit signed) 5619 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5620 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5621 ins_cost(MEMORY_REF_COST); 5622 5623 size(4); 5624 5625 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5626 ins_encode %{ 5627 __ ldsb($mem$$Address, $dst$$Register, 3); 5628 %} 5629 ins_pipe(iload_mask_mem); 5630 %} 5631 5632 // Load Integer to Unsigned Byte (8 bit UNsigned) 5633 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5634 match(Set dst (AndI (LoadI mem) mask)); 5635 ins_cost(MEMORY_REF_COST); 5636 5637 size(4); 5638 5639 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5640 ins_encode %{ 5641 __ ldub($mem$$Address, $dst$$Register, 3); 5642 %} 5643 ins_pipe(iload_mask_mem); 5644 %} 5645 5646 // Load Integer to Short (16 bit signed) 5647 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5648 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5649 ins_cost(MEMORY_REF_COST); 5650 5651 size(4); 5652 5653 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5654 ins_encode %{ 5655 __ ldsh($mem$$Address, $dst$$Register, 2); 5656 %} 5657 ins_pipe(iload_mask_mem); 5658 %} 5659 5660 // Load Integer to Unsigned Short (16 bit UNsigned) 5661 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5662 match(Set dst (AndI (LoadI mem) mask)); 5663 ins_cost(MEMORY_REF_COST); 5664 5665 size(4); 5666 5667 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5668 ins_encode %{ 5669 __ lduh($mem$$Address, $dst$$Register, 2); 5670 %} 5671 ins_pipe(iload_mask_mem); 5672 %} 5673 5674 // Load Integer into a Long Register 5675 instruct loadI2L(iRegL dst, memory mem) %{ 5676 match(Set dst (ConvI2L (LoadI mem))); 5677 ins_cost(MEMORY_REF_COST); 5678 5679 size(4); 5680 format %{ "LDSW $mem,$dst\t! int -> long" %} 5681 ins_encode %{ 5682 __ ldsw($mem$$Address, $dst$$Register); 5683 %} 5684 ins_pipe(iload_mask_mem); 5685 %} 5686 5687 // Load Integer with mask 0xFF into a Long Register 5688 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5689 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5690 ins_cost(MEMORY_REF_COST); 5691 5692 size(4); 5693 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5694 ins_encode %{ 5695 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5696 %} 5697 ins_pipe(iload_mem); 5698 %} 5699 5700 // Load Integer with mask 0xFFFF into a Long Register 5701 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5702 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5703 ins_cost(MEMORY_REF_COST); 5704 5705 size(4); 5706 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5707 ins_encode %{ 5708 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5709 %} 5710 ins_pipe(iload_mem); 5711 %} 5712 5713 // Load Integer with a 13-bit mask into a Long Register 5714 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5715 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5716 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5717 5718 size(2*4); 5719 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5720 "AND $dst,$mask,$dst" %} 5721 ins_encode %{ 5722 Register Rdst = $dst$$Register; 5723 __ lduw($mem$$Address, Rdst); 5724 __ and3(Rdst, $mask$$constant, Rdst); 5725 %} 5726 ins_pipe(iload_mem); 5727 %} 5728 5729 // Load Integer with a 32-bit mask into a Long Register 5730 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5731 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5732 effect(TEMP dst, TEMP tmp); 5733 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5734 5735 size((3+1)*4); // set may use two instructions. 5736 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5737 "SET $mask,$tmp\n\t" 5738 "AND $dst,$tmp,$dst" %} 5739 ins_encode %{ 5740 Register Rdst = $dst$$Register; 5741 Register Rtmp = $tmp$$Register; 5742 __ lduw($mem$$Address, Rdst); 5743 __ set($mask$$constant, Rtmp); 5744 __ and3(Rdst, Rtmp, Rdst); 5745 %} 5746 ins_pipe(iload_mem); 5747 %} 5748 5749 // Load Unsigned Integer into a Long Register 5750 instruct loadUI2L(iRegL dst, memory mem) %{ 5751 match(Set dst (LoadUI2L mem)); 5752 ins_cost(MEMORY_REF_COST); 5753 5754 size(4); 5755 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5756 ins_encode %{ 5757 __ lduw($mem$$Address, $dst$$Register); 5758 %} 5759 ins_pipe(iload_mem); 5760 %} 5761 5762 // Load Long - aligned 5763 instruct loadL(iRegL dst, memory mem ) %{ 5764 match(Set dst (LoadL mem)); 5765 ins_cost(MEMORY_REF_COST); 5766 5767 size(4); 5768 format %{ "LDX $mem,$dst\t! long" %} 5769 ins_encode %{ 5770 __ ldx($mem$$Address, $dst$$Register); 5771 %} 5772 ins_pipe(iload_mem); 5773 %} 5774 5775 // Load Long - UNaligned 5776 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5777 match(Set dst (LoadL_unaligned mem)); 5778 effect(KILL tmp); 5779 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5780 size(16); 5781 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5782 "\tLDUW $mem ,$dst\n" 5783 "\tSLLX #32, $dst, $dst\n" 5784 "\tOR $dst, R_O7, $dst" %} 5785 opcode(Assembler::lduw_op3); 5786 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5787 ins_pipe(iload_mem); 5788 %} 5789 5790 // Load Aligned Packed Byte into a Double Register 5791 instruct loadA8B(regD dst, memory mem) %{ 5792 match(Set dst (Load8B mem)); 5793 ins_cost(MEMORY_REF_COST); 5794 size(4); 5795 format %{ "LDDF $mem,$dst\t! packed8B" %} 5796 opcode(Assembler::lddf_op3); 5797 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5798 ins_pipe(floadD_mem); 5799 %} 5800 5801 // Load Aligned Packed Char into a Double Register 5802 instruct loadA4C(regD dst, memory mem) %{ 5803 match(Set dst (Load4C mem)); 5804 ins_cost(MEMORY_REF_COST); 5805 size(4); 5806 format %{ "LDDF $mem,$dst\t! packed4C" %} 5807 opcode(Assembler::lddf_op3); 5808 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5809 ins_pipe(floadD_mem); 5810 %} 5811 5812 // Load Aligned Packed Short into a Double Register 5813 instruct loadA4S(regD dst, memory mem) %{ 5814 match(Set dst (Load4S mem)); 5815 ins_cost(MEMORY_REF_COST); 5816 size(4); 5817 format %{ "LDDF $mem,$dst\t! packed4S" %} 5818 opcode(Assembler::lddf_op3); 5819 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5820 ins_pipe(floadD_mem); 5821 %} 5822 5823 // Load Aligned Packed Int into a Double Register 5824 instruct loadA2I(regD dst, memory mem) %{ 5825 match(Set dst (Load2I mem)); 5826 ins_cost(MEMORY_REF_COST); 5827 size(4); 5828 format %{ "LDDF $mem,$dst\t! packed2I" %} 5829 opcode(Assembler::lddf_op3); 5830 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5831 ins_pipe(floadD_mem); 5832 %} 5833 5834 // Load Range 5835 instruct loadRange(iRegI dst, memory mem) %{ 5836 match(Set dst (LoadRange mem)); 5837 ins_cost(MEMORY_REF_COST); 5838 5839 size(4); 5840 format %{ "LDUW $mem,$dst\t! range" %} 5841 opcode(Assembler::lduw_op3); 5842 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5843 ins_pipe(iload_mem); 5844 %} 5845 5846 // Load Integer into %f register (for fitos/fitod) 5847 instruct loadI_freg(regF dst, memory mem) %{ 5848 match(Set dst (LoadI mem)); 5849 ins_cost(MEMORY_REF_COST); 5850 size(4); 5851 5852 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5853 opcode(Assembler::ldf_op3); 5854 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5855 ins_pipe(floadF_mem); 5856 %} 5857 5858 // Load Pointer 5859 instruct loadP(iRegP dst, memory mem) %{ 5860 match(Set dst (LoadP mem)); 5861 ins_cost(MEMORY_REF_COST); 5862 size(4); 5863 5864 #ifndef _LP64 5865 format %{ "LDUW $mem,$dst\t! ptr" %} 5866 ins_encode %{ 5867 __ lduw($mem$$Address, $dst$$Register); 5868 %} 5869 #else 5870 format %{ "LDX $mem,$dst\t! ptr" %} 5871 ins_encode %{ 5872 __ ldx($mem$$Address, $dst$$Register); 5873 %} 5874 #endif 5875 ins_pipe(iload_mem); 5876 %} 5877 5878 // Load Compressed Pointer 5879 instruct loadN(iRegN dst, memory mem) %{ 5880 match(Set dst (LoadN mem)); 5881 ins_cost(MEMORY_REF_COST); 5882 size(4); 5883 5884 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5885 ins_encode %{ 5886 __ lduw($mem$$Address, $dst$$Register); 5887 %} 5888 ins_pipe(iload_mem); 5889 %} 5890 5891 // Load Klass Pointer 5892 instruct loadKlass(iRegP dst, memory mem) %{ 5893 match(Set dst (LoadKlass mem)); 5894 ins_cost(MEMORY_REF_COST); 5895 size(4); 5896 5897 #ifndef _LP64 5898 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5899 ins_encode %{ 5900 __ lduw($mem$$Address, $dst$$Register); 5901 %} 5902 #else 5903 format %{ "LDX $mem,$dst\t! klass ptr" %} 5904 ins_encode %{ 5905 __ ldx($mem$$Address, $dst$$Register); 5906 %} 5907 #endif 5908 ins_pipe(iload_mem); 5909 %} 5910 5911 // Load narrow Klass Pointer 5912 instruct loadNKlass(iRegN dst, memory mem) %{ 5913 match(Set dst (LoadNKlass mem)); 5914 ins_cost(MEMORY_REF_COST); 5915 size(4); 5916 5917 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5918 ins_encode %{ 5919 __ lduw($mem$$Address, $dst$$Register); 5920 %} 5921 ins_pipe(iload_mem); 5922 %} 5923 5924 // Load Double 5925 instruct loadD(regD dst, memory mem) %{ 5926 match(Set dst (LoadD mem)); 5927 ins_cost(MEMORY_REF_COST); 5928 5929 size(4); 5930 format %{ "LDDF $mem,$dst" %} 5931 opcode(Assembler::lddf_op3); 5932 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5933 ins_pipe(floadD_mem); 5934 %} 5935 5936 // Load Double - UNaligned 5937 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5938 match(Set dst (LoadD_unaligned mem)); 5939 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5940 size(8); 5941 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5942 "\tLDF $mem+4,$dst.lo\t!" %} 5943 opcode(Assembler::ldf_op3); 5944 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5945 ins_pipe(iload_mem); 5946 %} 5947 5948 // Load Float 5949 instruct loadF(regF dst, memory mem) %{ 5950 match(Set dst (LoadF mem)); 5951 ins_cost(MEMORY_REF_COST); 5952 5953 size(4); 5954 format %{ "LDF $mem,$dst" %} 5955 opcode(Assembler::ldf_op3); 5956 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5957 ins_pipe(floadF_mem); 5958 %} 5959 5960 // Load Constant 5961 instruct loadConI( iRegI dst, immI src ) %{ 5962 match(Set dst src); 5963 ins_cost(DEFAULT_COST * 3/2); 5964 format %{ "SET $src,$dst" %} 5965 ins_encode( Set32(src, dst) ); 5966 ins_pipe(ialu_hi_lo_reg); 5967 %} 5968 5969 instruct loadConI13( iRegI dst, immI13 src ) %{ 5970 match(Set dst src); 5971 5972 size(4); 5973 format %{ "MOV $src,$dst" %} 5974 ins_encode( Set13( src, dst ) ); 5975 ins_pipe(ialu_imm); 5976 %} 5977 5978 instruct loadConP(iRegP dst, immP src) %{ 5979 match(Set dst src); 5980 ins_cost(DEFAULT_COST * 3/2); 5981 format %{ "SET $src,$dst\t!ptr" %} 5982 // This rule does not use "expand" unlike loadConI because then 5983 // the result type is not known to be an Oop. An ADLC 5984 // enhancement will be needed to make that work - not worth it! 5985 5986 ins_encode( SetPtr( src, dst ) ); 5987 ins_pipe(loadConP); 5988 5989 %} 5990 5991 instruct loadConP0(iRegP dst, immP0 src) %{ 5992 match(Set dst src); 5993 5994 size(4); 5995 format %{ "CLR $dst\t!ptr" %} 5996 ins_encode( SetNull( dst ) ); 5997 ins_pipe(ialu_imm); 5998 %} 5999 6000 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6001 match(Set dst src); 6002 ins_cost(DEFAULT_COST); 6003 format %{ "SET $src,$dst\t!ptr" %} 6004 ins_encode %{ 6005 AddressLiteral polling_page(os::get_polling_page()); 6006 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6007 %} 6008 ins_pipe(loadConP_poll); 6009 %} 6010 6011 instruct loadConN0(iRegN dst, immN0 src) %{ 6012 match(Set dst src); 6013 6014 size(4); 6015 format %{ "CLR $dst\t! compressed NULL ptr" %} 6016 ins_encode( SetNull( dst ) ); 6017 ins_pipe(ialu_imm); 6018 %} 6019 6020 instruct loadConN(iRegN dst, immN src) %{ 6021 match(Set dst src); 6022 ins_cost(DEFAULT_COST * 3/2); 6023 format %{ "SET $src,$dst\t! compressed ptr" %} 6024 ins_encode %{ 6025 Register dst = $dst$$Register; 6026 __ set_narrow_oop((jobject)$src$$constant, dst); 6027 %} 6028 ins_pipe(ialu_hi_lo_reg); 6029 %} 6030 6031 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ 6032 // %%% maybe this should work like loadConD 6033 match(Set dst src); 6034 effect(KILL tmp); 6035 ins_cost(DEFAULT_COST * 4); 6036 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} 6037 ins_encode( LdImmL(src, dst, tmp) ); 6038 ins_pipe(loadConL); 6039 %} 6040 6041 instruct loadConL0( iRegL dst, immL0 src ) %{ 6042 match(Set dst src); 6043 ins_cost(DEFAULT_COST); 6044 size(4); 6045 format %{ "CLR $dst\t! long" %} 6046 ins_encode( Set13( src, dst ) ); 6047 ins_pipe(ialu_imm); 6048 %} 6049 6050 instruct loadConL13( iRegL dst, immL13 src ) %{ 6051 match(Set dst src); 6052 ins_cost(DEFAULT_COST * 2); 6053 6054 size(4); 6055 format %{ "MOV $src,$dst\t! long" %} 6056 ins_encode( Set13( src, dst ) ); 6057 ins_pipe(ialu_imm); 6058 %} 6059 6060 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 6061 match(Set dst src); 6062 effect(KILL tmp); 6063 6064 #ifdef _LP64 6065 size(8*4); 6066 #else 6067 size(2*4); 6068 #endif 6069 6070 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 6071 "LDF [$tmp+lo(&$src)],$dst" %} 6072 ins_encode %{ 6073 address float_address = __ float_constant($src$$constant); 6074 RelocationHolder rspec = internal_word_Relocation::spec(float_address); 6075 AddressLiteral addrlit(float_address, rspec); 6076 6077 __ sethi(addrlit, $tmp$$Register); 6078 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6079 %} 6080 ins_pipe(loadConFD); 6081 %} 6082 6083 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 6084 match(Set dst src); 6085 effect(KILL tmp); 6086 6087 #ifdef _LP64 6088 size(8*4); 6089 #else 6090 size(2*4); 6091 #endif 6092 6093 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 6094 "LDDF [$tmp+lo(&$src)],$dst" %} 6095 ins_encode %{ 6096 address double_address = __ double_constant($src$$constant); 6097 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 6098 AddressLiteral addrlit(double_address, rspec); 6099 6100 __ sethi(addrlit, $tmp$$Register); 6101 // XXX This is a quick fix for 6833573. 6102 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6103 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 6104 %} 6105 ins_pipe(loadConFD); 6106 %} 6107 6108 // Prefetch instructions. 6109 // Must be safe to execute with invalid address (cannot fault). 6110 6111 instruct prefetchr( memory mem ) %{ 6112 match( PrefetchRead mem ); 6113 ins_cost(MEMORY_REF_COST); 6114 6115 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6116 opcode(Assembler::prefetch_op3); 6117 ins_encode( form3_mem_prefetch_read( mem ) ); 6118 ins_pipe(iload_mem); 6119 %} 6120 6121 instruct prefetchw( memory mem ) %{ 6122 predicate(AllocatePrefetchStyle != 3 ); 6123 match( PrefetchWrite mem ); 6124 ins_cost(MEMORY_REF_COST); 6125 6126 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6127 opcode(Assembler::prefetch_op3); 6128 ins_encode( form3_mem_prefetch_write( mem ) ); 6129 ins_pipe(iload_mem); 6130 %} 6131 6132 // Use BIS instruction to prefetch. 6133 instruct prefetchw_bis( memory mem ) %{ 6134 predicate(AllocatePrefetchStyle == 3); 6135 match( PrefetchWrite mem ); 6136 ins_cost(MEMORY_REF_COST); 6137 6138 format %{ "STXA G0,$mem\t! // Block initializing store" %} 6139 ins_encode %{ 6140 Register base = as_Register($mem$$base); 6141 int disp = $mem$$disp; 6142 if (disp != 0) { 6143 __ add(base, AllocatePrefetchStepSize, base); 6144 } 6145 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 6146 %} 6147 ins_pipe(istore_mem_reg); 6148 %} 6149 6150 //----------Store Instructions------------------------------------------------- 6151 // Store Byte 6152 instruct storeB(memory mem, iRegI src) %{ 6153 match(Set mem (StoreB mem src)); 6154 ins_cost(MEMORY_REF_COST); 6155 6156 size(4); 6157 format %{ "STB $src,$mem\t! byte" %} 6158 opcode(Assembler::stb_op3); 6159 ins_encode(simple_form3_mem_reg( mem, src ) ); 6160 ins_pipe(istore_mem_reg); 6161 %} 6162 6163 instruct storeB0(memory mem, immI0 src) %{ 6164 match(Set mem (StoreB mem src)); 6165 ins_cost(MEMORY_REF_COST); 6166 6167 size(4); 6168 format %{ "STB $src,$mem\t! byte" %} 6169 opcode(Assembler::stb_op3); 6170 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6171 ins_pipe(istore_mem_zero); 6172 %} 6173 6174 instruct storeCM0(memory mem, immI0 src) %{ 6175 match(Set mem (StoreCM mem src)); 6176 ins_cost(MEMORY_REF_COST); 6177 6178 size(4); 6179 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6180 opcode(Assembler::stb_op3); 6181 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6182 ins_pipe(istore_mem_zero); 6183 %} 6184 6185 // Store Char/Short 6186 instruct storeC(memory mem, iRegI src) %{ 6187 match(Set mem (StoreC mem src)); 6188 ins_cost(MEMORY_REF_COST); 6189 6190 size(4); 6191 format %{ "STH $src,$mem\t! short" %} 6192 opcode(Assembler::sth_op3); 6193 ins_encode(simple_form3_mem_reg( mem, src ) ); 6194 ins_pipe(istore_mem_reg); 6195 %} 6196 6197 instruct storeC0(memory mem, immI0 src) %{ 6198 match(Set mem (StoreC mem src)); 6199 ins_cost(MEMORY_REF_COST); 6200 6201 size(4); 6202 format %{ "STH $src,$mem\t! short" %} 6203 opcode(Assembler::sth_op3); 6204 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6205 ins_pipe(istore_mem_zero); 6206 %} 6207 6208 // Store Integer 6209 instruct storeI(memory mem, iRegI src) %{ 6210 match(Set mem (StoreI mem src)); 6211 ins_cost(MEMORY_REF_COST); 6212 6213 size(4); 6214 format %{ "STW $src,$mem" %} 6215 opcode(Assembler::stw_op3); 6216 ins_encode(simple_form3_mem_reg( mem, src ) ); 6217 ins_pipe(istore_mem_reg); 6218 %} 6219 6220 // Store Long 6221 instruct storeL(memory mem, iRegL src) %{ 6222 match(Set mem (StoreL mem src)); 6223 ins_cost(MEMORY_REF_COST); 6224 size(4); 6225 format %{ "STX $src,$mem\t! long" %} 6226 opcode(Assembler::stx_op3); 6227 ins_encode(simple_form3_mem_reg( mem, src ) ); 6228 ins_pipe(istore_mem_reg); 6229 %} 6230 6231 instruct storeI0(memory mem, immI0 src) %{ 6232 match(Set mem (StoreI mem src)); 6233 ins_cost(MEMORY_REF_COST); 6234 6235 size(4); 6236 format %{ "STW $src,$mem" %} 6237 opcode(Assembler::stw_op3); 6238 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6239 ins_pipe(istore_mem_zero); 6240 %} 6241 6242 instruct storeL0(memory mem, immL0 src) %{ 6243 match(Set mem (StoreL mem src)); 6244 ins_cost(MEMORY_REF_COST); 6245 6246 size(4); 6247 format %{ "STX $src,$mem" %} 6248 opcode(Assembler::stx_op3); 6249 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6250 ins_pipe(istore_mem_zero); 6251 %} 6252 6253 // Store Integer from float register (used after fstoi) 6254 instruct storeI_Freg(memory mem, regF src) %{ 6255 match(Set mem (StoreI mem src)); 6256 ins_cost(MEMORY_REF_COST); 6257 6258 size(4); 6259 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6260 opcode(Assembler::stf_op3); 6261 ins_encode(simple_form3_mem_reg( mem, src ) ); 6262 ins_pipe(fstoreF_mem_reg); 6263 %} 6264 6265 // Store Pointer 6266 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6267 match(Set dst (StoreP dst src)); 6268 ins_cost(MEMORY_REF_COST); 6269 size(4); 6270 6271 #ifndef _LP64 6272 format %{ "STW $src,$dst\t! ptr" %} 6273 opcode(Assembler::stw_op3, 0, REGP_OP); 6274 #else 6275 format %{ "STX $src,$dst\t! ptr" %} 6276 opcode(Assembler::stx_op3, 0, REGP_OP); 6277 #endif 6278 ins_encode( form3_mem_reg( dst, src ) ); 6279 ins_pipe(istore_mem_spORreg); 6280 %} 6281 6282 instruct storeP0(memory dst, immP0 src) %{ 6283 match(Set dst (StoreP dst src)); 6284 ins_cost(MEMORY_REF_COST); 6285 size(4); 6286 6287 #ifndef _LP64 6288 format %{ "STW $src,$dst\t! ptr" %} 6289 opcode(Assembler::stw_op3, 0, REGP_OP); 6290 #else 6291 format %{ "STX $src,$dst\t! ptr" %} 6292 opcode(Assembler::stx_op3, 0, REGP_OP); 6293 #endif 6294 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6295 ins_pipe(istore_mem_zero); 6296 %} 6297 6298 // Store Compressed Pointer 6299 instruct storeN(memory dst, iRegN src) %{ 6300 match(Set dst (StoreN dst src)); 6301 ins_cost(MEMORY_REF_COST); 6302 size(4); 6303 6304 format %{ "STW $src,$dst\t! compressed ptr" %} 6305 ins_encode %{ 6306 Register base = as_Register($dst$$base); 6307 Register index = as_Register($dst$$index); 6308 Register src = $src$$Register; 6309 if (index != G0) { 6310 __ stw(src, base, index); 6311 } else { 6312 __ stw(src, base, $dst$$disp); 6313 } 6314 %} 6315 ins_pipe(istore_mem_spORreg); 6316 %} 6317 6318 instruct storeN0(memory dst, immN0 src) %{ 6319 match(Set dst (StoreN dst src)); 6320 ins_cost(MEMORY_REF_COST); 6321 size(4); 6322 6323 format %{ "STW $src,$dst\t! compressed ptr" %} 6324 ins_encode %{ 6325 Register base = as_Register($dst$$base); 6326 Register index = as_Register($dst$$index); 6327 if (index != G0) { 6328 __ stw(0, base, index); 6329 } else { 6330 __ stw(0, base, $dst$$disp); 6331 } 6332 %} 6333 ins_pipe(istore_mem_zero); 6334 %} 6335 6336 // Store Double 6337 instruct storeD( memory mem, regD src) %{ 6338 match(Set mem (StoreD mem src)); 6339 ins_cost(MEMORY_REF_COST); 6340 6341 size(4); 6342 format %{ "STDF $src,$mem" %} 6343 opcode(Assembler::stdf_op3); 6344 ins_encode(simple_form3_mem_reg( mem, src ) ); 6345 ins_pipe(fstoreD_mem_reg); 6346 %} 6347 6348 instruct storeD0( memory mem, immD0 src) %{ 6349 match(Set mem (StoreD mem src)); 6350 ins_cost(MEMORY_REF_COST); 6351 6352 size(4); 6353 format %{ "STX $src,$mem" %} 6354 opcode(Assembler::stx_op3); 6355 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6356 ins_pipe(fstoreD_mem_zero); 6357 %} 6358 6359 // Store Float 6360 instruct storeF( memory mem, regF src) %{ 6361 match(Set mem (StoreF mem src)); 6362 ins_cost(MEMORY_REF_COST); 6363 6364 size(4); 6365 format %{ "STF $src,$mem" %} 6366 opcode(Assembler::stf_op3); 6367 ins_encode(simple_form3_mem_reg( mem, src ) ); 6368 ins_pipe(fstoreF_mem_reg); 6369 %} 6370 6371 instruct storeF0( memory mem, immF0 src) %{ 6372 match(Set mem (StoreF mem src)); 6373 ins_cost(MEMORY_REF_COST); 6374 6375 size(4); 6376 format %{ "STW $src,$mem\t! storeF0" %} 6377 opcode(Assembler::stw_op3); 6378 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6379 ins_pipe(fstoreF_mem_zero); 6380 %} 6381 6382 // Store Aligned Packed Bytes in Double register to memory 6383 instruct storeA8B(memory mem, regD src) %{ 6384 match(Set mem (Store8B mem src)); 6385 ins_cost(MEMORY_REF_COST); 6386 size(4); 6387 format %{ "STDF $src,$mem\t! packed8B" %} 6388 opcode(Assembler::stdf_op3); 6389 ins_encode(simple_form3_mem_reg( mem, src ) ); 6390 ins_pipe(fstoreD_mem_reg); 6391 %} 6392 6393 // Convert oop pointer into compressed form 6394 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6395 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6396 match(Set dst (EncodeP src)); 6397 format %{ "encode_heap_oop $src, $dst" %} 6398 ins_encode %{ 6399 __ encode_heap_oop($src$$Register, $dst$$Register); 6400 %} 6401 ins_pipe(ialu_reg); 6402 %} 6403 6404 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6405 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6406 match(Set dst (EncodeP src)); 6407 format %{ "encode_heap_oop_not_null $src, $dst" %} 6408 ins_encode %{ 6409 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6410 %} 6411 ins_pipe(ialu_reg); 6412 %} 6413 6414 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6415 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6416 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6417 match(Set dst (DecodeN src)); 6418 format %{ "decode_heap_oop $src, $dst" %} 6419 ins_encode %{ 6420 __ decode_heap_oop($src$$Register, $dst$$Register); 6421 %} 6422 ins_pipe(ialu_reg); 6423 %} 6424 6425 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6426 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6427 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6428 match(Set dst (DecodeN src)); 6429 format %{ "decode_heap_oop_not_null $src, $dst" %} 6430 ins_encode %{ 6431 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6432 %} 6433 ins_pipe(ialu_reg); 6434 %} 6435 6436 6437 // Store Zero into Aligned Packed Bytes 6438 instruct storeA8B0(memory mem, immI0 zero) %{ 6439 match(Set mem (Store8B mem zero)); 6440 ins_cost(MEMORY_REF_COST); 6441 size(4); 6442 format %{ "STX $zero,$mem\t! packed8B" %} 6443 opcode(Assembler::stx_op3); 6444 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6445 ins_pipe(fstoreD_mem_zero); 6446 %} 6447 6448 // Store Aligned Packed Chars/Shorts in Double register to memory 6449 instruct storeA4C(memory mem, regD src) %{ 6450 match(Set mem (Store4C mem src)); 6451 ins_cost(MEMORY_REF_COST); 6452 size(4); 6453 format %{ "STDF $src,$mem\t! packed4C" %} 6454 opcode(Assembler::stdf_op3); 6455 ins_encode(simple_form3_mem_reg( mem, src ) ); 6456 ins_pipe(fstoreD_mem_reg); 6457 %} 6458 6459 // Store Zero into Aligned Packed Chars/Shorts 6460 instruct storeA4C0(memory mem, immI0 zero) %{ 6461 match(Set mem (Store4C mem (Replicate4C zero))); 6462 ins_cost(MEMORY_REF_COST); 6463 size(4); 6464 format %{ "STX $zero,$mem\t! packed4C" %} 6465 opcode(Assembler::stx_op3); 6466 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6467 ins_pipe(fstoreD_mem_zero); 6468 %} 6469 6470 // Store Aligned Packed Ints in Double register to memory 6471 instruct storeA2I(memory mem, regD src) %{ 6472 match(Set mem (Store2I mem src)); 6473 ins_cost(MEMORY_REF_COST); 6474 size(4); 6475 format %{ "STDF $src,$mem\t! packed2I" %} 6476 opcode(Assembler::stdf_op3); 6477 ins_encode(simple_form3_mem_reg( mem, src ) ); 6478 ins_pipe(fstoreD_mem_reg); 6479 %} 6480 6481 // Store Zero into Aligned Packed Ints 6482 instruct storeA2I0(memory mem, immI0 zero) %{ 6483 match(Set mem (Store2I mem zero)); 6484 ins_cost(MEMORY_REF_COST); 6485 size(4); 6486 format %{ "STX $zero,$mem\t! packed2I" %} 6487 opcode(Assembler::stx_op3); 6488 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6489 ins_pipe(fstoreD_mem_zero); 6490 %} 6491 6492 6493 //----------MemBar Instructions----------------------------------------------- 6494 // Memory barrier flavors 6495 6496 instruct membar_acquire() %{ 6497 match(MemBarAcquire); 6498 ins_cost(4*MEMORY_REF_COST); 6499 6500 size(0); 6501 format %{ "MEMBAR-acquire" %} 6502 ins_encode( enc_membar_acquire ); 6503 ins_pipe(long_memory_op); 6504 %} 6505 6506 instruct membar_acquire_lock() %{ 6507 match(MemBarAcquire); 6508 predicate(Matcher::prior_fast_lock(n)); 6509 ins_cost(0); 6510 6511 size(0); 6512 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6513 ins_encode( ); 6514 ins_pipe(empty); 6515 %} 6516 6517 instruct membar_release() %{ 6518 match(MemBarRelease); 6519 ins_cost(4*MEMORY_REF_COST); 6520 6521 size(0); 6522 format %{ "MEMBAR-release" %} 6523 ins_encode( enc_membar_release ); 6524 ins_pipe(long_memory_op); 6525 %} 6526 6527 instruct membar_release_lock() %{ 6528 match(MemBarRelease); 6529 predicate(Matcher::post_fast_unlock(n)); 6530 ins_cost(0); 6531 6532 size(0); 6533 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6534 ins_encode( ); 6535 ins_pipe(empty); 6536 %} 6537 6538 instruct membar_volatile() %{ 6539 match(MemBarVolatile); 6540 ins_cost(4*MEMORY_REF_COST); 6541 6542 size(4); 6543 format %{ "MEMBAR-volatile" %} 6544 ins_encode( enc_membar_volatile ); 6545 ins_pipe(long_memory_op); 6546 %} 6547 6548 instruct unnecessary_membar_volatile() %{ 6549 match(MemBarVolatile); 6550 predicate(Matcher::post_store_load_barrier(n)); 6551 ins_cost(0); 6552 6553 size(0); 6554 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6555 ins_encode( ); 6556 ins_pipe(empty); 6557 %} 6558 6559 //----------Register Move Instructions----------------------------------------- 6560 instruct roundDouble_nop(regD dst) %{ 6561 match(Set dst (RoundDouble dst)); 6562 ins_cost(0); 6563 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6564 ins_encode( ); 6565 ins_pipe(empty); 6566 %} 6567 6568 6569 instruct roundFloat_nop(regF dst) %{ 6570 match(Set dst (RoundFloat dst)); 6571 ins_cost(0); 6572 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6573 ins_encode( ); 6574 ins_pipe(empty); 6575 %} 6576 6577 6578 // Cast Index to Pointer for unsafe natives 6579 instruct castX2P(iRegX src, iRegP dst) %{ 6580 match(Set dst (CastX2P src)); 6581 6582 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6583 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6584 ins_pipe(ialu_reg); 6585 %} 6586 6587 // Cast Pointer to Index for unsafe natives 6588 instruct castP2X(iRegP src, iRegX dst) %{ 6589 match(Set dst (CastP2X src)); 6590 6591 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6592 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6593 ins_pipe(ialu_reg); 6594 %} 6595 6596 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6597 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6598 match(Set stkSlot src); // chain rule 6599 ins_cost(MEMORY_REF_COST); 6600 format %{ "STDF $src,$stkSlot\t!stk" %} 6601 opcode(Assembler::stdf_op3); 6602 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6603 ins_pipe(fstoreD_stk_reg); 6604 %} 6605 6606 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6607 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6608 match(Set dst stkSlot); // chain rule 6609 ins_cost(MEMORY_REF_COST); 6610 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6611 opcode(Assembler::lddf_op3); 6612 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6613 ins_pipe(floadD_stk); 6614 %} 6615 6616 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6617 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6618 match(Set stkSlot src); // chain rule 6619 ins_cost(MEMORY_REF_COST); 6620 format %{ "STF $src,$stkSlot\t!stk" %} 6621 opcode(Assembler::stf_op3); 6622 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6623 ins_pipe(fstoreF_stk_reg); 6624 %} 6625 6626 //----------Conditional Move--------------------------------------------------- 6627 // Conditional move 6628 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6629 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6630 ins_cost(150); 6631 format %{ "MOV$cmp $pcc,$src,$dst" %} 6632 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6633 ins_pipe(ialu_reg); 6634 %} 6635 6636 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6637 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6638 ins_cost(140); 6639 format %{ "MOV$cmp $pcc,$src,$dst" %} 6640 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6641 ins_pipe(ialu_imm); 6642 %} 6643 6644 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6645 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6646 ins_cost(150); 6647 size(4); 6648 format %{ "MOV$cmp $icc,$src,$dst" %} 6649 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6650 ins_pipe(ialu_reg); 6651 %} 6652 6653 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6655 ins_cost(140); 6656 size(4); 6657 format %{ "MOV$cmp $icc,$src,$dst" %} 6658 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6659 ins_pipe(ialu_imm); 6660 %} 6661 6662 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6664 ins_cost(150); 6665 size(4); 6666 format %{ "MOV$cmp $icc,$src,$dst" %} 6667 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6668 ins_pipe(ialu_reg); 6669 %} 6670 6671 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6673 ins_cost(140); 6674 size(4); 6675 format %{ "MOV$cmp $icc,$src,$dst" %} 6676 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6677 ins_pipe(ialu_imm); 6678 %} 6679 6680 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6681 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6682 ins_cost(150); 6683 size(4); 6684 format %{ "MOV$cmp $fcc,$src,$dst" %} 6685 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6686 ins_pipe(ialu_reg); 6687 %} 6688 6689 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6691 ins_cost(140); 6692 size(4); 6693 format %{ "MOV$cmp $fcc,$src,$dst" %} 6694 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6695 ins_pipe(ialu_imm); 6696 %} 6697 6698 // Conditional move for RegN. Only cmov(reg,reg). 6699 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6700 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6701 ins_cost(150); 6702 format %{ "MOV$cmp $pcc,$src,$dst" %} 6703 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6704 ins_pipe(ialu_reg); 6705 %} 6706 6707 // This instruction also works with CmpN so we don't need cmovNN_reg. 6708 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6709 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6710 ins_cost(150); 6711 size(4); 6712 format %{ "MOV$cmp $icc,$src,$dst" %} 6713 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6714 ins_pipe(ialu_reg); 6715 %} 6716 6717 // This instruction also works with CmpN so we don't need cmovNN_reg. 6718 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6719 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6720 ins_cost(150); 6721 size(4); 6722 format %{ "MOV$cmp $icc,$src,$dst" %} 6723 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6724 ins_pipe(ialu_reg); 6725 %} 6726 6727 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6728 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6729 ins_cost(150); 6730 size(4); 6731 format %{ "MOV$cmp $fcc,$src,$dst" %} 6732 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6733 ins_pipe(ialu_reg); 6734 %} 6735 6736 // Conditional move 6737 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6738 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6739 ins_cost(150); 6740 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6741 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6742 ins_pipe(ialu_reg); 6743 %} 6744 6745 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6746 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6747 ins_cost(140); 6748 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6749 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6750 ins_pipe(ialu_imm); 6751 %} 6752 6753 // This instruction also works with CmpN so we don't need cmovPN_reg. 6754 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6755 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6756 ins_cost(150); 6757 6758 size(4); 6759 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6760 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6761 ins_pipe(ialu_reg); 6762 %} 6763 6764 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6765 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6766 ins_cost(150); 6767 6768 size(4); 6769 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6771 ins_pipe(ialu_reg); 6772 %} 6773 6774 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6775 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6776 ins_cost(140); 6777 6778 size(4); 6779 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6781 ins_pipe(ialu_imm); 6782 %} 6783 6784 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6785 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6786 ins_cost(140); 6787 6788 size(4); 6789 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6790 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6791 ins_pipe(ialu_imm); 6792 %} 6793 6794 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6795 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6796 ins_cost(150); 6797 size(4); 6798 format %{ "MOV$cmp $fcc,$src,$dst" %} 6799 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6800 ins_pipe(ialu_imm); 6801 %} 6802 6803 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6804 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6805 ins_cost(140); 6806 size(4); 6807 format %{ "MOV$cmp $fcc,$src,$dst" %} 6808 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6809 ins_pipe(ialu_imm); 6810 %} 6811 6812 // Conditional move 6813 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6814 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6815 ins_cost(150); 6816 opcode(0x101); 6817 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6818 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6819 ins_pipe(int_conditional_float_move); 6820 %} 6821 6822 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6823 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6824 ins_cost(150); 6825 6826 size(4); 6827 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6828 opcode(0x101); 6829 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6830 ins_pipe(int_conditional_float_move); 6831 %} 6832 6833 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6834 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6835 ins_cost(150); 6836 6837 size(4); 6838 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6839 opcode(0x101); 6840 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6841 ins_pipe(int_conditional_float_move); 6842 %} 6843 6844 // Conditional move, 6845 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6846 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6847 ins_cost(150); 6848 size(4); 6849 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6850 opcode(0x1); 6851 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6852 ins_pipe(int_conditional_double_move); 6853 %} 6854 6855 // Conditional move 6856 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6857 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6858 ins_cost(150); 6859 size(4); 6860 opcode(0x102); 6861 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6862 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6863 ins_pipe(int_conditional_double_move); 6864 %} 6865 6866 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6867 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6868 ins_cost(150); 6869 6870 size(4); 6871 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6872 opcode(0x102); 6873 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6874 ins_pipe(int_conditional_double_move); 6875 %} 6876 6877 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6878 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6879 ins_cost(150); 6880 6881 size(4); 6882 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6883 opcode(0x102); 6884 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6885 ins_pipe(int_conditional_double_move); 6886 %} 6887 6888 // Conditional move, 6889 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6890 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6891 ins_cost(150); 6892 size(4); 6893 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6894 opcode(0x2); 6895 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6896 ins_pipe(int_conditional_double_move); 6897 %} 6898 6899 // Conditional move 6900 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6901 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6902 ins_cost(150); 6903 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6904 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6905 ins_pipe(ialu_reg); 6906 %} 6907 6908 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6909 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6910 ins_cost(140); 6911 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6912 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6913 ins_pipe(ialu_imm); 6914 %} 6915 6916 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6917 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6918 ins_cost(150); 6919 6920 size(4); 6921 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6923 ins_pipe(ialu_reg); 6924 %} 6925 6926 6927 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6928 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6929 ins_cost(150); 6930 6931 size(4); 6932 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6933 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6934 ins_pipe(ialu_reg); 6935 %} 6936 6937 6938 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6939 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6940 ins_cost(150); 6941 6942 size(4); 6943 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6944 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6945 ins_pipe(ialu_reg); 6946 %} 6947 6948 6949 6950 //----------OS and Locking Instructions---------------------------------------- 6951 6952 // This name is KNOWN by the ADLC and cannot be changed. 6953 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6954 // for this guy. 6955 instruct tlsLoadP(g2RegP dst) %{ 6956 match(Set dst (ThreadLocal)); 6957 6958 size(0); 6959 ins_cost(0); 6960 format %{ "# TLS is in G2" %} 6961 ins_encode( /*empty encoding*/ ); 6962 ins_pipe(ialu_none); 6963 %} 6964 6965 instruct checkCastPP( iRegP dst ) %{ 6966 match(Set dst (CheckCastPP dst)); 6967 6968 size(0); 6969 format %{ "# checkcastPP of $dst" %} 6970 ins_encode( /*empty encoding*/ ); 6971 ins_pipe(empty); 6972 %} 6973 6974 6975 instruct castPP( iRegP dst ) %{ 6976 match(Set dst (CastPP dst)); 6977 format %{ "# castPP of $dst" %} 6978 ins_encode( /*empty encoding*/ ); 6979 ins_pipe(empty); 6980 %} 6981 6982 instruct castII( iRegI dst ) %{ 6983 match(Set dst (CastII dst)); 6984 format %{ "# castII of $dst" %} 6985 ins_encode( /*empty encoding*/ ); 6986 ins_cost(0); 6987 ins_pipe(empty); 6988 %} 6989 6990 //----------Arithmetic Instructions-------------------------------------------- 6991 // Addition Instructions 6992 // Register Addition 6993 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6994 match(Set dst (AddI src1 src2)); 6995 6996 size(4); 6997 format %{ "ADD $src1,$src2,$dst" %} 6998 ins_encode %{ 6999 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7000 %} 7001 ins_pipe(ialu_reg_reg); 7002 %} 7003 7004 // Immediate Addition 7005 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7006 match(Set dst (AddI src1 src2)); 7007 7008 size(4); 7009 format %{ "ADD $src1,$src2,$dst" %} 7010 opcode(Assembler::add_op3, Assembler::arith_op); 7011 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7012 ins_pipe(ialu_reg_imm); 7013 %} 7014 7015 // Pointer Register Addition 7016 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7017 match(Set dst (AddP src1 src2)); 7018 7019 size(4); 7020 format %{ "ADD $src1,$src2,$dst" %} 7021 opcode(Assembler::add_op3, Assembler::arith_op); 7022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7023 ins_pipe(ialu_reg_reg); 7024 %} 7025 7026 // Pointer Immediate Addition 7027 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7028 match(Set dst (AddP src1 src2)); 7029 7030 size(4); 7031 format %{ "ADD $src1,$src2,$dst" %} 7032 opcode(Assembler::add_op3, Assembler::arith_op); 7033 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7034 ins_pipe(ialu_reg_imm); 7035 %} 7036 7037 // Long Addition 7038 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7039 match(Set dst (AddL src1 src2)); 7040 7041 size(4); 7042 format %{ "ADD $src1,$src2,$dst\t! long" %} 7043 opcode(Assembler::add_op3, Assembler::arith_op); 7044 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7045 ins_pipe(ialu_reg_reg); 7046 %} 7047 7048 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7049 match(Set dst (AddL src1 con)); 7050 7051 size(4); 7052 format %{ "ADD $src1,$con,$dst" %} 7053 opcode(Assembler::add_op3, Assembler::arith_op); 7054 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7055 ins_pipe(ialu_reg_imm); 7056 %} 7057 7058 //----------Conditional_store-------------------------------------------------- 7059 // Conditional-store of the updated heap-top. 7060 // Used during allocation of the shared heap. 7061 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7062 7063 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7064 instruct loadPLocked(iRegP dst, memory mem) %{ 7065 match(Set dst (LoadPLocked mem)); 7066 ins_cost(MEMORY_REF_COST); 7067 7068 #ifndef _LP64 7069 size(4); 7070 format %{ "LDUW $mem,$dst\t! ptr" %} 7071 opcode(Assembler::lduw_op3, 0, REGP_OP); 7072 #else 7073 format %{ "LDX $mem,$dst\t! ptr" %} 7074 opcode(Assembler::ldx_op3, 0, REGP_OP); 7075 #endif 7076 ins_encode( form3_mem_reg( mem, dst ) ); 7077 ins_pipe(iload_mem); 7078 %} 7079 7080 // LoadL-locked. Same as a regular long load when used with a compare-swap 7081 instruct loadLLocked(iRegL dst, memory mem) %{ 7082 match(Set dst (LoadLLocked mem)); 7083 ins_cost(MEMORY_REF_COST); 7084 size(4); 7085 format %{ "LDX $mem,$dst\t! long" %} 7086 opcode(Assembler::ldx_op3); 7087 ins_encode(simple_form3_mem_reg( mem, dst ) ); 7088 ins_pipe(iload_mem); 7089 %} 7090 7091 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7092 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7093 effect( KILL newval ); 7094 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7095 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7096 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7097 ins_pipe( long_memory_op ); 7098 %} 7099 7100 // Conditional-store of an int value. 7101 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7102 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7103 effect( KILL newval ); 7104 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7105 "CMP $oldval,$newval\t\t! See if we made progress" %} 7106 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7107 ins_pipe( long_memory_op ); 7108 %} 7109 7110 // Conditional-store of a long value. 7111 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7112 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7113 effect( KILL newval ); 7114 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7115 "CMP $oldval,$newval\t\t! See if we made progress" %} 7116 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7117 ins_pipe( long_memory_op ); 7118 %} 7119 7120 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7121 7122 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7123 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7124 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7125 format %{ 7126 "MOV $newval,O7\n\t" 7127 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7128 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7129 "MOV 1,$res\n\t" 7130 "MOVne xcc,R_G0,$res" 7131 %} 7132 ins_encode( enc_casx(mem_ptr, oldval, newval), 7133 enc_lflags_ne_to_boolean(res) ); 7134 ins_pipe( long_memory_op ); 7135 %} 7136 7137 7138 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7139 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7140 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7141 format %{ 7142 "MOV $newval,O7\n\t" 7143 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7144 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7145 "MOV 1,$res\n\t" 7146 "MOVne icc,R_G0,$res" 7147 %} 7148 ins_encode( enc_casi(mem_ptr, oldval, newval), 7149 enc_iflags_ne_to_boolean(res) ); 7150 ins_pipe( long_memory_op ); 7151 %} 7152 7153 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7154 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7155 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7156 format %{ 7157 "MOV $newval,O7\n\t" 7158 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7159 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7160 "MOV 1,$res\n\t" 7161 "MOVne xcc,R_G0,$res" 7162 %} 7163 #ifdef _LP64 7164 ins_encode( enc_casx(mem_ptr, oldval, newval), 7165 enc_lflags_ne_to_boolean(res) ); 7166 #else 7167 ins_encode( enc_casi(mem_ptr, oldval, newval), 7168 enc_iflags_ne_to_boolean(res) ); 7169 #endif 7170 ins_pipe( long_memory_op ); 7171 %} 7172 7173 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7174 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7175 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7176 format %{ 7177 "MOV $newval,O7\n\t" 7178 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7179 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7180 "MOV 1,$res\n\t" 7181 "MOVne icc,R_G0,$res" 7182 %} 7183 ins_encode( enc_casi(mem_ptr, oldval, newval), 7184 enc_iflags_ne_to_boolean(res) ); 7185 ins_pipe( long_memory_op ); 7186 %} 7187 7188 //--------------------- 7189 // Subtraction Instructions 7190 // Register Subtraction 7191 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7192 match(Set dst (SubI src1 src2)); 7193 7194 size(4); 7195 format %{ "SUB $src1,$src2,$dst" %} 7196 opcode(Assembler::sub_op3, Assembler::arith_op); 7197 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7198 ins_pipe(ialu_reg_reg); 7199 %} 7200 7201 // Immediate Subtraction 7202 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7203 match(Set dst (SubI src1 src2)); 7204 7205 size(4); 7206 format %{ "SUB $src1,$src2,$dst" %} 7207 opcode(Assembler::sub_op3, Assembler::arith_op); 7208 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7209 ins_pipe(ialu_reg_imm); 7210 %} 7211 7212 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7213 match(Set dst (SubI zero src2)); 7214 7215 size(4); 7216 format %{ "NEG $src2,$dst" %} 7217 opcode(Assembler::sub_op3, Assembler::arith_op); 7218 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7219 ins_pipe(ialu_zero_reg); 7220 %} 7221 7222 // Long subtraction 7223 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7224 match(Set dst (SubL src1 src2)); 7225 7226 size(4); 7227 format %{ "SUB $src1,$src2,$dst\t! long" %} 7228 opcode(Assembler::sub_op3, Assembler::arith_op); 7229 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7230 ins_pipe(ialu_reg_reg); 7231 %} 7232 7233 // Immediate Subtraction 7234 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7235 match(Set dst (SubL src1 con)); 7236 7237 size(4); 7238 format %{ "SUB $src1,$con,$dst\t! long" %} 7239 opcode(Assembler::sub_op3, Assembler::arith_op); 7240 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7241 ins_pipe(ialu_reg_imm); 7242 %} 7243 7244 // Long negation 7245 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7246 match(Set dst (SubL zero src2)); 7247 7248 size(4); 7249 format %{ "NEG $src2,$dst\t! long" %} 7250 opcode(Assembler::sub_op3, Assembler::arith_op); 7251 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7252 ins_pipe(ialu_zero_reg); 7253 %} 7254 7255 // Multiplication Instructions 7256 // Integer Multiplication 7257 // Register Multiplication 7258 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7259 match(Set dst (MulI src1 src2)); 7260 7261 size(4); 7262 format %{ "MULX $src1,$src2,$dst" %} 7263 opcode(Assembler::mulx_op3, Assembler::arith_op); 7264 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7265 ins_pipe(imul_reg_reg); 7266 %} 7267 7268 // Immediate Multiplication 7269 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7270 match(Set dst (MulI src1 src2)); 7271 7272 size(4); 7273 format %{ "MULX $src1,$src2,$dst" %} 7274 opcode(Assembler::mulx_op3, Assembler::arith_op); 7275 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7276 ins_pipe(imul_reg_imm); 7277 %} 7278 7279 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7280 match(Set dst (MulL src1 src2)); 7281 ins_cost(DEFAULT_COST * 5); 7282 size(4); 7283 format %{ "MULX $src1,$src2,$dst\t! long" %} 7284 opcode(Assembler::mulx_op3, Assembler::arith_op); 7285 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7286 ins_pipe(mulL_reg_reg); 7287 %} 7288 7289 // Immediate Multiplication 7290 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7291 match(Set dst (MulL src1 src2)); 7292 ins_cost(DEFAULT_COST * 5); 7293 size(4); 7294 format %{ "MULX $src1,$src2,$dst" %} 7295 opcode(Assembler::mulx_op3, Assembler::arith_op); 7296 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7297 ins_pipe(mulL_reg_imm); 7298 %} 7299 7300 // Integer Division 7301 // Register Division 7302 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7303 match(Set dst (DivI src1 src2)); 7304 ins_cost((2+71)*DEFAULT_COST); 7305 7306 format %{ "SRA $src2,0,$src2\n\t" 7307 "SRA $src1,0,$src1\n\t" 7308 "SDIVX $src1,$src2,$dst" %} 7309 ins_encode( idiv_reg( src1, src2, dst ) ); 7310 ins_pipe(sdiv_reg_reg); 7311 %} 7312 7313 // Immediate Division 7314 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7315 match(Set dst (DivI src1 src2)); 7316 ins_cost((2+71)*DEFAULT_COST); 7317 7318 format %{ "SRA $src1,0,$src1\n\t" 7319 "SDIVX $src1,$src2,$dst" %} 7320 ins_encode( idiv_imm( src1, src2, dst ) ); 7321 ins_pipe(sdiv_reg_imm); 7322 %} 7323 7324 //----------Div-By-10-Expansion------------------------------------------------ 7325 // Extract hi bits of a 32x32->64 bit multiply. 7326 // Expand rule only, not matched 7327 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7328 effect( DEF dst, USE src1, USE src2 ); 7329 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7330 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7331 ins_encode( enc_mul_hi(dst,src1,src2)); 7332 ins_pipe(sdiv_reg_reg); 7333 %} 7334 7335 // Magic constant, reciprocal of 10 7336 instruct loadConI_x66666667(iRegIsafe dst) %{ 7337 effect( DEF dst ); 7338 7339 size(8); 7340 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7341 ins_encode( Set32(0x66666667, dst) ); 7342 ins_pipe(ialu_hi_lo_reg); 7343 %} 7344 7345 // Register Shift Right Arithmetic Long by 32-63 7346 instruct sra_31( iRegI dst, iRegI src ) %{ 7347 effect( DEF dst, USE src ); 7348 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7349 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7350 ins_pipe(ialu_reg_reg); 7351 %} 7352 7353 // Arithmetic Shift Right by 8-bit immediate 7354 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7355 effect( DEF dst, USE src ); 7356 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7357 opcode(Assembler::sra_op3, Assembler::arith_op); 7358 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7359 ins_pipe(ialu_reg_imm); 7360 %} 7361 7362 // Integer DIV with 10 7363 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7364 match(Set dst (DivI src div)); 7365 ins_cost((6+6)*DEFAULT_COST); 7366 expand %{ 7367 iRegIsafe tmp1; // Killed temps; 7368 iRegIsafe tmp2; // Killed temps; 7369 iRegI tmp3; // Killed temps; 7370 iRegI tmp4; // Killed temps; 7371 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7372 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7373 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7374 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7375 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7376 %} 7377 %} 7378 7379 // Register Long Division 7380 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7381 match(Set dst (DivL src1 src2)); 7382 ins_cost(DEFAULT_COST*71); 7383 size(4); 7384 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7385 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7386 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7387 ins_pipe(divL_reg_reg); 7388 %} 7389 7390 // Register Long Division 7391 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7392 match(Set dst (DivL src1 src2)); 7393 ins_cost(DEFAULT_COST*71); 7394 size(4); 7395 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7396 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7397 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7398 ins_pipe(divL_reg_imm); 7399 %} 7400 7401 // Integer Remainder 7402 // Register Remainder 7403 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7404 match(Set dst (ModI src1 src2)); 7405 effect( KILL ccr, KILL temp); 7406 7407 format %{ "SREM $src1,$src2,$dst" %} 7408 ins_encode( irem_reg(src1, src2, dst, temp) ); 7409 ins_pipe(sdiv_reg_reg); 7410 %} 7411 7412 // Immediate Remainder 7413 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7414 match(Set dst (ModI src1 src2)); 7415 effect( KILL ccr, KILL temp); 7416 7417 format %{ "SREM $src1,$src2,$dst" %} 7418 ins_encode( irem_imm(src1, src2, dst, temp) ); 7419 ins_pipe(sdiv_reg_imm); 7420 %} 7421 7422 // Register Long Remainder 7423 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7424 effect(DEF dst, USE src1, USE src2); 7425 size(4); 7426 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7427 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7428 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7429 ins_pipe(divL_reg_reg); 7430 %} 7431 7432 // Register Long Division 7433 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7434 effect(DEF dst, USE src1, USE src2); 7435 size(4); 7436 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7437 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7438 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7439 ins_pipe(divL_reg_imm); 7440 %} 7441 7442 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7443 effect(DEF dst, USE src1, USE src2); 7444 size(4); 7445 format %{ "MULX $src1,$src2,$dst\t! long" %} 7446 opcode(Assembler::mulx_op3, Assembler::arith_op); 7447 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7448 ins_pipe(mulL_reg_reg); 7449 %} 7450 7451 // Immediate Multiplication 7452 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7453 effect(DEF dst, USE src1, USE src2); 7454 size(4); 7455 format %{ "MULX $src1,$src2,$dst" %} 7456 opcode(Assembler::mulx_op3, Assembler::arith_op); 7457 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7458 ins_pipe(mulL_reg_imm); 7459 %} 7460 7461 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7462 effect(DEF dst, USE src1, USE src2); 7463 size(4); 7464 format %{ "SUB $src1,$src2,$dst\t! long" %} 7465 opcode(Assembler::sub_op3, Assembler::arith_op); 7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7467 ins_pipe(ialu_reg_reg); 7468 %} 7469 7470 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7471 effect(DEF dst, USE src1, USE src2); 7472 size(4); 7473 format %{ "SUB $src1,$src2,$dst\t! long" %} 7474 opcode(Assembler::sub_op3, Assembler::arith_op); 7475 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7476 ins_pipe(ialu_reg_reg); 7477 %} 7478 7479 // Register Long Remainder 7480 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7481 match(Set dst (ModL src1 src2)); 7482 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7483 expand %{ 7484 iRegL tmp1; 7485 iRegL tmp2; 7486 divL_reg_reg_1(tmp1, src1, src2); 7487 mulL_reg_reg_1(tmp2, tmp1, src2); 7488 subL_reg_reg_1(dst, src1, tmp2); 7489 %} 7490 %} 7491 7492 // Register Long Remainder 7493 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7494 match(Set dst (ModL src1 src2)); 7495 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7496 expand %{ 7497 iRegL tmp1; 7498 iRegL tmp2; 7499 divL_reg_imm13_1(tmp1, src1, src2); 7500 mulL_reg_imm13_1(tmp2, tmp1, src2); 7501 subL_reg_reg_2 (dst, src1, tmp2); 7502 %} 7503 %} 7504 7505 // Integer Shift Instructions 7506 // Register Shift Left 7507 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7508 match(Set dst (LShiftI src1 src2)); 7509 7510 size(4); 7511 format %{ "SLL $src1,$src2,$dst" %} 7512 opcode(Assembler::sll_op3, Assembler::arith_op); 7513 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7514 ins_pipe(ialu_reg_reg); 7515 %} 7516 7517 // Register Shift Left Immediate 7518 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7519 match(Set dst (LShiftI src1 src2)); 7520 7521 size(4); 7522 format %{ "SLL $src1,$src2,$dst" %} 7523 opcode(Assembler::sll_op3, Assembler::arith_op); 7524 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7525 ins_pipe(ialu_reg_imm); 7526 %} 7527 7528 // Register Shift Left 7529 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7530 match(Set dst (LShiftL src1 src2)); 7531 7532 size(4); 7533 format %{ "SLLX $src1,$src2,$dst" %} 7534 opcode(Assembler::sllx_op3, Assembler::arith_op); 7535 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7536 ins_pipe(ialu_reg_reg); 7537 %} 7538 7539 // Register Shift Left Immediate 7540 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7541 match(Set dst (LShiftL src1 src2)); 7542 7543 size(4); 7544 format %{ "SLLX $src1,$src2,$dst" %} 7545 opcode(Assembler::sllx_op3, Assembler::arith_op); 7546 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7547 ins_pipe(ialu_reg_imm); 7548 %} 7549 7550 // Register Arithmetic Shift Right 7551 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7552 match(Set dst (RShiftI src1 src2)); 7553 size(4); 7554 format %{ "SRA $src1,$src2,$dst" %} 7555 opcode(Assembler::sra_op3, Assembler::arith_op); 7556 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7557 ins_pipe(ialu_reg_reg); 7558 %} 7559 7560 // Register Arithmetic Shift Right Immediate 7561 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7562 match(Set dst (RShiftI src1 src2)); 7563 7564 size(4); 7565 format %{ "SRA $src1,$src2,$dst" %} 7566 opcode(Assembler::sra_op3, Assembler::arith_op); 7567 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7568 ins_pipe(ialu_reg_imm); 7569 %} 7570 7571 // Register Shift Right Arithmatic Long 7572 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7573 match(Set dst (RShiftL src1 src2)); 7574 7575 size(4); 7576 format %{ "SRAX $src1,$src2,$dst" %} 7577 opcode(Assembler::srax_op3, Assembler::arith_op); 7578 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7579 ins_pipe(ialu_reg_reg); 7580 %} 7581 7582 // Register Shift Left Immediate 7583 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7584 match(Set dst (RShiftL src1 src2)); 7585 7586 size(4); 7587 format %{ "SRAX $src1,$src2,$dst" %} 7588 opcode(Assembler::srax_op3, Assembler::arith_op); 7589 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7590 ins_pipe(ialu_reg_imm); 7591 %} 7592 7593 // Register Shift Right 7594 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7595 match(Set dst (URShiftI src1 src2)); 7596 7597 size(4); 7598 format %{ "SRL $src1,$src2,$dst" %} 7599 opcode(Assembler::srl_op3, Assembler::arith_op); 7600 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7601 ins_pipe(ialu_reg_reg); 7602 %} 7603 7604 // Register Shift Right Immediate 7605 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7606 match(Set dst (URShiftI src1 src2)); 7607 7608 size(4); 7609 format %{ "SRL $src1,$src2,$dst" %} 7610 opcode(Assembler::srl_op3, Assembler::arith_op); 7611 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7612 ins_pipe(ialu_reg_imm); 7613 %} 7614 7615 // Register Shift Right 7616 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7617 match(Set dst (URShiftL src1 src2)); 7618 7619 size(4); 7620 format %{ "SRLX $src1,$src2,$dst" %} 7621 opcode(Assembler::srlx_op3, Assembler::arith_op); 7622 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7623 ins_pipe(ialu_reg_reg); 7624 %} 7625 7626 // Register Shift Right Immediate 7627 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7628 match(Set dst (URShiftL src1 src2)); 7629 7630 size(4); 7631 format %{ "SRLX $src1,$src2,$dst" %} 7632 opcode(Assembler::srlx_op3, Assembler::arith_op); 7633 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7634 ins_pipe(ialu_reg_imm); 7635 %} 7636 7637 // Register Shift Right Immediate with a CastP2X 7638 #ifdef _LP64 7639 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7640 match(Set dst (URShiftL (CastP2X src1) src2)); 7641 size(4); 7642 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7643 opcode(Assembler::srlx_op3, Assembler::arith_op); 7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7645 ins_pipe(ialu_reg_imm); 7646 %} 7647 #else 7648 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7649 match(Set dst (URShiftI (CastP2X src1) src2)); 7650 size(4); 7651 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7652 opcode(Assembler::srl_op3, Assembler::arith_op); 7653 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7654 ins_pipe(ialu_reg_imm); 7655 %} 7656 #endif 7657 7658 7659 //----------Floating Point Arithmetic Instructions----------------------------- 7660 7661 // Add float single precision 7662 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7663 match(Set dst (AddF src1 src2)); 7664 7665 size(4); 7666 format %{ "FADDS $src1,$src2,$dst" %} 7667 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7668 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7669 ins_pipe(faddF_reg_reg); 7670 %} 7671 7672 // Add float double precision 7673 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7674 match(Set dst (AddD src1 src2)); 7675 7676 size(4); 7677 format %{ "FADDD $src1,$src2,$dst" %} 7678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7679 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7680 ins_pipe(faddD_reg_reg); 7681 %} 7682 7683 // Sub float single precision 7684 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7685 match(Set dst (SubF src1 src2)); 7686 7687 size(4); 7688 format %{ "FSUBS $src1,$src2,$dst" %} 7689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7690 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7691 ins_pipe(faddF_reg_reg); 7692 %} 7693 7694 // Sub float double precision 7695 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7696 match(Set dst (SubD src1 src2)); 7697 7698 size(4); 7699 format %{ "FSUBD $src1,$src2,$dst" %} 7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7701 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7702 ins_pipe(faddD_reg_reg); 7703 %} 7704 7705 // Mul float single precision 7706 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7707 match(Set dst (MulF src1 src2)); 7708 7709 size(4); 7710 format %{ "FMULS $src1,$src2,$dst" %} 7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7712 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7713 ins_pipe(fmulF_reg_reg); 7714 %} 7715 7716 // Mul float double precision 7717 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7718 match(Set dst (MulD src1 src2)); 7719 7720 size(4); 7721 format %{ "FMULD $src1,$src2,$dst" %} 7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7723 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7724 ins_pipe(fmulD_reg_reg); 7725 %} 7726 7727 // Div float single precision 7728 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7729 match(Set dst (DivF src1 src2)); 7730 7731 size(4); 7732 format %{ "FDIVS $src1,$src2,$dst" %} 7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7734 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7735 ins_pipe(fdivF_reg_reg); 7736 %} 7737 7738 // Div float double precision 7739 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7740 match(Set dst (DivD src1 src2)); 7741 7742 size(4); 7743 format %{ "FDIVD $src1,$src2,$dst" %} 7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7745 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7746 ins_pipe(fdivD_reg_reg); 7747 %} 7748 7749 // Absolute float double precision 7750 instruct absD_reg(regD dst, regD src) %{ 7751 match(Set dst (AbsD src)); 7752 7753 format %{ "FABSd $src,$dst" %} 7754 ins_encode(fabsd(dst, src)); 7755 ins_pipe(faddD_reg); 7756 %} 7757 7758 // Absolute float single precision 7759 instruct absF_reg(regF dst, regF src) %{ 7760 match(Set dst (AbsF src)); 7761 7762 format %{ "FABSs $src,$dst" %} 7763 ins_encode(fabss(dst, src)); 7764 ins_pipe(faddF_reg); 7765 %} 7766 7767 instruct negF_reg(regF dst, regF src) %{ 7768 match(Set dst (NegF src)); 7769 7770 size(4); 7771 format %{ "FNEGs $src,$dst" %} 7772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7773 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7774 ins_pipe(faddF_reg); 7775 %} 7776 7777 instruct negD_reg(regD dst, regD src) %{ 7778 match(Set dst (NegD src)); 7779 7780 format %{ "FNEGd $src,$dst" %} 7781 ins_encode(fnegd(dst, src)); 7782 ins_pipe(faddD_reg); 7783 %} 7784 7785 // Sqrt float double precision 7786 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7787 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7788 7789 size(4); 7790 format %{ "FSQRTS $src,$dst" %} 7791 ins_encode(fsqrts(dst, src)); 7792 ins_pipe(fdivF_reg_reg); 7793 %} 7794 7795 // Sqrt float double precision 7796 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7797 match(Set dst (SqrtD src)); 7798 7799 size(4); 7800 format %{ "FSQRTD $src,$dst" %} 7801 ins_encode(fsqrtd(dst, src)); 7802 ins_pipe(fdivD_reg_reg); 7803 %} 7804 7805 //----------Logical Instructions----------------------------------------------- 7806 // And Instructions 7807 // Register And 7808 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7809 match(Set dst (AndI src1 src2)); 7810 7811 size(4); 7812 format %{ "AND $src1,$src2,$dst" %} 7813 opcode(Assembler::and_op3, Assembler::arith_op); 7814 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7815 ins_pipe(ialu_reg_reg); 7816 %} 7817 7818 // Immediate And 7819 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7820 match(Set dst (AndI src1 src2)); 7821 7822 size(4); 7823 format %{ "AND $src1,$src2,$dst" %} 7824 opcode(Assembler::and_op3, Assembler::arith_op); 7825 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7826 ins_pipe(ialu_reg_imm); 7827 %} 7828 7829 // Register And Long 7830 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7831 match(Set dst (AndL src1 src2)); 7832 7833 ins_cost(DEFAULT_COST); 7834 size(4); 7835 format %{ "AND $src1,$src2,$dst\t! long" %} 7836 opcode(Assembler::and_op3, Assembler::arith_op); 7837 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7838 ins_pipe(ialu_reg_reg); 7839 %} 7840 7841 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7842 match(Set dst (AndL src1 con)); 7843 7844 ins_cost(DEFAULT_COST); 7845 size(4); 7846 format %{ "AND $src1,$con,$dst\t! long" %} 7847 opcode(Assembler::and_op3, Assembler::arith_op); 7848 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7849 ins_pipe(ialu_reg_imm); 7850 %} 7851 7852 // Or Instructions 7853 // Register Or 7854 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7855 match(Set dst (OrI src1 src2)); 7856 7857 size(4); 7858 format %{ "OR $src1,$src2,$dst" %} 7859 opcode(Assembler::or_op3, Assembler::arith_op); 7860 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7861 ins_pipe(ialu_reg_reg); 7862 %} 7863 7864 // Immediate Or 7865 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7866 match(Set dst (OrI src1 src2)); 7867 7868 size(4); 7869 format %{ "OR $src1,$src2,$dst" %} 7870 opcode(Assembler::or_op3, Assembler::arith_op); 7871 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7872 ins_pipe(ialu_reg_imm); 7873 %} 7874 7875 // Register Or Long 7876 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7877 match(Set dst (OrL src1 src2)); 7878 7879 ins_cost(DEFAULT_COST); 7880 size(4); 7881 format %{ "OR $src1,$src2,$dst\t! long" %} 7882 opcode(Assembler::or_op3, Assembler::arith_op); 7883 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7884 ins_pipe(ialu_reg_reg); 7885 %} 7886 7887 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7888 match(Set dst (OrL src1 con)); 7889 ins_cost(DEFAULT_COST*2); 7890 7891 ins_cost(DEFAULT_COST); 7892 size(4); 7893 format %{ "OR $src1,$con,$dst\t! long" %} 7894 opcode(Assembler::or_op3, Assembler::arith_op); 7895 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7896 ins_pipe(ialu_reg_imm); 7897 %} 7898 7899 #ifndef _LP64 7900 7901 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 7902 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 7903 match(Set dst (OrI src1 (CastP2X src2))); 7904 7905 size(4); 7906 format %{ "OR $src1,$src2,$dst" %} 7907 opcode(Assembler::or_op3, Assembler::arith_op); 7908 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7909 ins_pipe(ialu_reg_reg); 7910 %} 7911 7912 #else 7913 7914 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7915 match(Set dst (OrL src1 (CastP2X src2))); 7916 7917 ins_cost(DEFAULT_COST); 7918 size(4); 7919 format %{ "OR $src1,$src2,$dst\t! long" %} 7920 opcode(Assembler::or_op3, Assembler::arith_op); 7921 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7922 ins_pipe(ialu_reg_reg); 7923 %} 7924 7925 #endif 7926 7927 // Xor Instructions 7928 // Register Xor 7929 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7930 match(Set dst (XorI src1 src2)); 7931 7932 size(4); 7933 format %{ "XOR $src1,$src2,$dst" %} 7934 opcode(Assembler::xor_op3, Assembler::arith_op); 7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7936 ins_pipe(ialu_reg_reg); 7937 %} 7938 7939 // Immediate Xor 7940 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7941 match(Set dst (XorI src1 src2)); 7942 7943 size(4); 7944 format %{ "XOR $src1,$src2,$dst" %} 7945 opcode(Assembler::xor_op3, Assembler::arith_op); 7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7947 ins_pipe(ialu_reg_imm); 7948 %} 7949 7950 // Register Xor Long 7951 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7952 match(Set dst (XorL src1 src2)); 7953 7954 ins_cost(DEFAULT_COST); 7955 size(4); 7956 format %{ "XOR $src1,$src2,$dst\t! long" %} 7957 opcode(Assembler::xor_op3, Assembler::arith_op); 7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7959 ins_pipe(ialu_reg_reg); 7960 %} 7961 7962 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7963 match(Set dst (XorL src1 con)); 7964 7965 ins_cost(DEFAULT_COST); 7966 size(4); 7967 format %{ "XOR $src1,$con,$dst\t! long" %} 7968 opcode(Assembler::xor_op3, Assembler::arith_op); 7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7970 ins_pipe(ialu_reg_imm); 7971 %} 7972 7973 //----------Convert to Boolean------------------------------------------------- 7974 // Nice hack for 32-bit tests but doesn't work for 7975 // 64-bit pointers. 7976 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7977 match(Set dst (Conv2B src)); 7978 effect( KILL ccr ); 7979 ins_cost(DEFAULT_COST*2); 7980 format %{ "CMP R_G0,$src\n\t" 7981 "ADDX R_G0,0,$dst" %} 7982 ins_encode( enc_to_bool( src, dst ) ); 7983 ins_pipe(ialu_reg_ialu); 7984 %} 7985 7986 #ifndef _LP64 7987 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 7988 match(Set dst (Conv2B src)); 7989 effect( KILL ccr ); 7990 ins_cost(DEFAULT_COST*2); 7991 format %{ "CMP R_G0,$src\n\t" 7992 "ADDX R_G0,0,$dst" %} 7993 ins_encode( enc_to_bool( src, dst ) ); 7994 ins_pipe(ialu_reg_ialu); 7995 %} 7996 #else 7997 instruct convP2B( iRegI dst, iRegP src ) %{ 7998 match(Set dst (Conv2B src)); 7999 ins_cost(DEFAULT_COST*2); 8000 format %{ "MOV $src,$dst\n\t" 8001 "MOVRNZ $src,1,$dst" %} 8002 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8003 ins_pipe(ialu_clr_and_mover); 8004 %} 8005 #endif 8006 8007 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8008 match(Set dst (CmpLTMask p q)); 8009 effect( KILL ccr ); 8010 ins_cost(DEFAULT_COST*4); 8011 format %{ "CMP $p,$q\n\t" 8012 "MOV #0,$dst\n\t" 8013 "BLT,a .+8\n\t" 8014 "MOV #-1,$dst" %} 8015 ins_encode( enc_ltmask(p,q,dst) ); 8016 ins_pipe(ialu_reg_reg_ialu); 8017 %} 8018 8019 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8020 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8021 effect(KILL ccr, TEMP tmp); 8022 ins_cost(DEFAULT_COST*3); 8023 8024 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8025 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8026 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8027 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8028 ins_pipe( cadd_cmpltmask ); 8029 %} 8030 8031 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8032 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 8033 effect( KILL ccr, TEMP tmp); 8034 ins_cost(DEFAULT_COST*3); 8035 8036 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8037 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8038 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8039 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8040 ins_pipe( cadd_cmpltmask ); 8041 %} 8042 8043 //----------Arithmetic Conversion Instructions--------------------------------- 8044 // The conversions operations are all Alpha sorted. Please keep it that way! 8045 8046 instruct convD2F_reg(regF dst, regD src) %{ 8047 match(Set dst (ConvD2F src)); 8048 size(4); 8049 format %{ "FDTOS $src,$dst" %} 8050 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8051 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8052 ins_pipe(fcvtD2F); 8053 %} 8054 8055 8056 // Convert a double to an int in a float register. 8057 // If the double is a NAN, stuff a zero in instead. 8058 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8059 effect(DEF dst, USE src, KILL fcc0); 8060 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8061 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8062 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8063 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8064 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8065 "skip:" %} 8066 ins_encode(form_d2i_helper(src,dst)); 8067 ins_pipe(fcvtD2I); 8068 %} 8069 8070 instruct convD2I_reg(stackSlotI dst, regD src) %{ 8071 match(Set dst (ConvD2I src)); 8072 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8073 expand %{ 8074 regF tmp; 8075 convD2I_helper(tmp, src); 8076 regF_to_stkI(dst, tmp); 8077 %} 8078 %} 8079 8080 // Convert a double to a long in a double register. 8081 // If the double is a NAN, stuff a zero in instead. 8082 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8083 effect(DEF dst, USE src, KILL fcc0); 8084 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8085 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8086 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8087 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8088 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8089 "skip:" %} 8090 ins_encode(form_d2l_helper(src,dst)); 8091 ins_pipe(fcvtD2L); 8092 %} 8093 8094 8095 // Double to Long conversion 8096 instruct convD2L_reg(stackSlotL dst, regD src) %{ 8097 match(Set dst (ConvD2L src)); 8098 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8099 expand %{ 8100 regD tmp; 8101 convD2L_helper(tmp, src); 8102 regD_to_stkL(dst, tmp); 8103 %} 8104 %} 8105 8106 8107 instruct convF2D_reg(regD dst, regF src) %{ 8108 match(Set dst (ConvF2D src)); 8109 format %{ "FSTOD $src,$dst" %} 8110 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8111 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8112 ins_pipe(fcvtF2D); 8113 %} 8114 8115 8116 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8117 effect(DEF dst, USE src, KILL fcc0); 8118 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8119 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8120 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8121 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8122 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8123 "skip:" %} 8124 ins_encode(form_f2i_helper(src,dst)); 8125 ins_pipe(fcvtF2I); 8126 %} 8127 8128 instruct convF2I_reg(stackSlotI dst, regF src) %{ 8129 match(Set dst (ConvF2I src)); 8130 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8131 expand %{ 8132 regF tmp; 8133 convF2I_helper(tmp, src); 8134 regF_to_stkI(dst, tmp); 8135 %} 8136 %} 8137 8138 8139 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8140 effect(DEF dst, USE src, KILL fcc0); 8141 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8142 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8143 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8144 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8145 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8146 "skip:" %} 8147 ins_encode(form_f2l_helper(src,dst)); 8148 ins_pipe(fcvtF2L); 8149 %} 8150 8151 // Float to Long conversion 8152 instruct convF2L_reg(stackSlotL dst, regF src) %{ 8153 match(Set dst (ConvF2L src)); 8154 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8155 expand %{ 8156 regD tmp; 8157 convF2L_helper(tmp, src); 8158 regD_to_stkL(dst, tmp); 8159 %} 8160 %} 8161 8162 8163 instruct convI2D_helper(regD dst, regF tmp) %{ 8164 effect(USE tmp, DEF dst); 8165 format %{ "FITOD $tmp,$dst" %} 8166 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8167 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8168 ins_pipe(fcvtI2D); 8169 %} 8170 8171 instruct convI2D_reg(stackSlotI src, regD dst) %{ 8172 match(Set dst (ConvI2D src)); 8173 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8174 expand %{ 8175 regF tmp; 8176 stkI_to_regF( tmp, src); 8177 convI2D_helper( dst, tmp); 8178 %} 8179 %} 8180 8181 instruct convI2D_mem( regD_low dst, memory mem ) %{ 8182 match(Set dst (ConvI2D (LoadI mem))); 8183 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8184 size(8); 8185 format %{ "LDF $mem,$dst\n\t" 8186 "FITOD $dst,$dst" %} 8187 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8188 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8189 ins_pipe(floadF_mem); 8190 %} 8191 8192 8193 instruct convI2F_helper(regF dst, regF tmp) %{ 8194 effect(DEF dst, USE tmp); 8195 format %{ "FITOS $tmp,$dst" %} 8196 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8197 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8198 ins_pipe(fcvtI2F); 8199 %} 8200 8201 instruct convI2F_reg( regF dst, stackSlotI src ) %{ 8202 match(Set dst (ConvI2F src)); 8203 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8204 expand %{ 8205 regF tmp; 8206 stkI_to_regF(tmp,src); 8207 convI2F_helper(dst, tmp); 8208 %} 8209 %} 8210 8211 instruct convI2F_mem( regF dst, memory mem ) %{ 8212 match(Set dst (ConvI2F (LoadI mem))); 8213 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8214 size(8); 8215 format %{ "LDF $mem,$dst\n\t" 8216 "FITOS $dst,$dst" %} 8217 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8218 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8219 ins_pipe(floadF_mem); 8220 %} 8221 8222 8223 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8224 match(Set dst (ConvI2L src)); 8225 size(4); 8226 format %{ "SRA $src,0,$dst\t! int->long" %} 8227 opcode(Assembler::sra_op3, Assembler::arith_op); 8228 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8229 ins_pipe(ialu_reg_reg); 8230 %} 8231 8232 // Zero-extend convert int to long 8233 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8234 match(Set dst (AndL (ConvI2L src) mask) ); 8235 size(4); 8236 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8237 opcode(Assembler::srl_op3, Assembler::arith_op); 8238 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8239 ins_pipe(ialu_reg_reg); 8240 %} 8241 8242 // Zero-extend long 8243 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8244 match(Set dst (AndL src mask) ); 8245 size(4); 8246 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8247 opcode(Assembler::srl_op3, Assembler::arith_op); 8248 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8249 ins_pipe(ialu_reg_reg); 8250 %} 8251 8252 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8253 match(Set dst (MoveF2I src)); 8254 effect(DEF dst, USE src); 8255 ins_cost(MEMORY_REF_COST); 8256 8257 size(4); 8258 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8259 opcode(Assembler::lduw_op3); 8260 ins_encode(simple_form3_mem_reg( src, dst ) ); 8261 ins_pipe(iload_mem); 8262 %} 8263 8264 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8265 match(Set dst (MoveI2F src)); 8266 effect(DEF dst, USE src); 8267 ins_cost(MEMORY_REF_COST); 8268 8269 size(4); 8270 format %{ "LDF $src,$dst\t! MoveI2F" %} 8271 opcode(Assembler::ldf_op3); 8272 ins_encode(simple_form3_mem_reg(src, dst)); 8273 ins_pipe(floadF_stk); 8274 %} 8275 8276 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8277 match(Set dst (MoveD2L src)); 8278 effect(DEF dst, USE src); 8279 ins_cost(MEMORY_REF_COST); 8280 8281 size(4); 8282 format %{ "LDX $src,$dst\t! MoveD2L" %} 8283 opcode(Assembler::ldx_op3); 8284 ins_encode(simple_form3_mem_reg( src, dst ) ); 8285 ins_pipe(iload_mem); 8286 %} 8287 8288 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8289 match(Set dst (MoveL2D src)); 8290 effect(DEF dst, USE src); 8291 ins_cost(MEMORY_REF_COST); 8292 8293 size(4); 8294 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8295 opcode(Assembler::lddf_op3); 8296 ins_encode(simple_form3_mem_reg(src, dst)); 8297 ins_pipe(floadD_stk); 8298 %} 8299 8300 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8301 match(Set dst (MoveF2I src)); 8302 effect(DEF dst, USE src); 8303 ins_cost(MEMORY_REF_COST); 8304 8305 size(4); 8306 format %{ "STF $src,$dst\t!MoveF2I" %} 8307 opcode(Assembler::stf_op3); 8308 ins_encode(simple_form3_mem_reg(dst, src)); 8309 ins_pipe(fstoreF_stk_reg); 8310 %} 8311 8312 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8313 match(Set dst (MoveI2F src)); 8314 effect(DEF dst, USE src); 8315 ins_cost(MEMORY_REF_COST); 8316 8317 size(4); 8318 format %{ "STW $src,$dst\t!MoveI2F" %} 8319 opcode(Assembler::stw_op3); 8320 ins_encode(simple_form3_mem_reg( dst, src ) ); 8321 ins_pipe(istore_mem_reg); 8322 %} 8323 8324 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8325 match(Set dst (MoveD2L src)); 8326 effect(DEF dst, USE src); 8327 ins_cost(MEMORY_REF_COST); 8328 8329 size(4); 8330 format %{ "STDF $src,$dst\t!MoveD2L" %} 8331 opcode(Assembler::stdf_op3); 8332 ins_encode(simple_form3_mem_reg(dst, src)); 8333 ins_pipe(fstoreD_stk_reg); 8334 %} 8335 8336 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8337 match(Set dst (MoveL2D src)); 8338 effect(DEF dst, USE src); 8339 ins_cost(MEMORY_REF_COST); 8340 8341 size(4); 8342 format %{ "STX $src,$dst\t!MoveL2D" %} 8343 opcode(Assembler::stx_op3); 8344 ins_encode(simple_form3_mem_reg( dst, src ) ); 8345 ins_pipe(istore_mem_reg); 8346 %} 8347 8348 8349 //----------- 8350 // Long to Double conversion using V8 opcodes. 8351 // Still useful because cheetah traps and becomes 8352 // amazingly slow for some common numbers. 8353 8354 // Magic constant, 0x43300000 8355 instruct loadConI_x43300000(iRegI dst) %{ 8356 effect(DEF dst); 8357 size(4); 8358 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8359 ins_encode(SetHi22(0x43300000, dst)); 8360 ins_pipe(ialu_none); 8361 %} 8362 8363 // Magic constant, 0x41f00000 8364 instruct loadConI_x41f00000(iRegI dst) %{ 8365 effect(DEF dst); 8366 size(4); 8367 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8368 ins_encode(SetHi22(0x41f00000, dst)); 8369 ins_pipe(ialu_none); 8370 %} 8371 8372 // Construct a double from two float halves 8373 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8374 effect(DEF dst, USE src1, USE src2); 8375 size(8); 8376 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8377 "FMOVS $src2.lo,$dst.lo" %} 8378 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8379 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8380 ins_pipe(faddD_reg_reg); 8381 %} 8382 8383 // Convert integer in high half of a double register (in the lower half of 8384 // the double register file) to double 8385 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8386 effect(DEF dst, USE src); 8387 size(4); 8388 format %{ "FITOD $src,$dst" %} 8389 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8390 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8391 ins_pipe(fcvtLHi2D); 8392 %} 8393 8394 // Add float double precision 8395 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8396 effect(DEF dst, USE src1, USE src2); 8397 size(4); 8398 format %{ "FADDD $src1,$src2,$dst" %} 8399 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8400 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8401 ins_pipe(faddD_reg_reg); 8402 %} 8403 8404 // Sub float double precision 8405 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8406 effect(DEF dst, USE src1, USE src2); 8407 size(4); 8408 format %{ "FSUBD $src1,$src2,$dst" %} 8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8410 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8411 ins_pipe(faddD_reg_reg); 8412 %} 8413 8414 // Mul float double precision 8415 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8416 effect(DEF dst, USE src1, USE src2); 8417 size(4); 8418 format %{ "FMULD $src1,$src2,$dst" %} 8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8420 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8421 ins_pipe(fmulD_reg_reg); 8422 %} 8423 8424 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8425 match(Set dst (ConvL2D src)); 8426 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8427 8428 expand %{ 8429 regD_low tmpsrc; 8430 iRegI ix43300000; 8431 iRegI ix41f00000; 8432 stackSlotL lx43300000; 8433 stackSlotL lx41f00000; 8434 regD_low dx43300000; 8435 regD dx41f00000; 8436 regD tmp1; 8437 regD_low tmp2; 8438 regD tmp3; 8439 regD tmp4; 8440 8441 stkL_to_regD(tmpsrc, src); 8442 8443 loadConI_x43300000(ix43300000); 8444 loadConI_x41f00000(ix41f00000); 8445 regI_to_stkLHi(lx43300000, ix43300000); 8446 regI_to_stkLHi(lx41f00000, ix41f00000); 8447 stkL_to_regD(dx43300000, lx43300000); 8448 stkL_to_regD(dx41f00000, lx41f00000); 8449 8450 convI2D_regDHi_regD(tmp1, tmpsrc); 8451 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8452 subD_regD_regD(tmp3, tmp2, dx43300000); 8453 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8454 addD_regD_regD(dst, tmp3, tmp4); 8455 %} 8456 %} 8457 8458 // Long to Double conversion using fast fxtof 8459 instruct convL2D_helper(regD dst, regD tmp) %{ 8460 effect(DEF dst, USE tmp); 8461 size(4); 8462 format %{ "FXTOD $tmp,$dst" %} 8463 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8464 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8465 ins_pipe(fcvtL2D); 8466 %} 8467 8468 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 8469 predicate(VM_Version::has_fast_fxtof()); 8470 match(Set dst (ConvL2D src)); 8471 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8472 expand %{ 8473 regD tmp; 8474 stkL_to_regD(tmp, src); 8475 convL2D_helper(dst, tmp); 8476 %} 8477 %} 8478 8479 //----------- 8480 // Long to Float conversion using V8 opcodes. 8481 // Still useful because cheetah traps and becomes 8482 // amazingly slow for some common numbers. 8483 8484 // Long to Float conversion using fast fxtof 8485 instruct convL2F_helper(regF dst, regD tmp) %{ 8486 effect(DEF dst, USE tmp); 8487 size(4); 8488 format %{ "FXTOS $tmp,$dst" %} 8489 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8490 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8491 ins_pipe(fcvtL2F); 8492 %} 8493 8494 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 8495 match(Set dst (ConvL2F src)); 8496 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8497 expand %{ 8498 regD tmp; 8499 stkL_to_regD(tmp, src); 8500 convL2F_helper(dst, tmp); 8501 %} 8502 %} 8503 //----------- 8504 8505 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8506 match(Set dst (ConvL2I src)); 8507 #ifndef _LP64 8508 format %{ "MOV $src.lo,$dst\t! long->int" %} 8509 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8510 ins_pipe(ialu_move_reg_I_to_L); 8511 #else 8512 size(4); 8513 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8514 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8515 ins_pipe(ialu_reg); 8516 #endif 8517 %} 8518 8519 // Register Shift Right Immediate 8520 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8521 match(Set dst (ConvL2I (RShiftL src cnt))); 8522 8523 size(4); 8524 format %{ "SRAX $src,$cnt,$dst" %} 8525 opcode(Assembler::srax_op3, Assembler::arith_op); 8526 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8527 ins_pipe(ialu_reg_imm); 8528 %} 8529 8530 // Replicate scalar to packed byte values in Double register 8531 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8532 effect(DEF dst, USE src); 8533 format %{ "SLLX $src,56,$dst\n\t" 8534 "SRLX $dst, 8,O7\n\t" 8535 "OR $dst,O7,$dst\n\t" 8536 "SRLX $dst,16,O7\n\t" 8537 "OR $dst,O7,$dst\n\t" 8538 "SRLX $dst,32,O7\n\t" 8539 "OR $dst,O7,$dst\t! replicate8B" %} 8540 ins_encode( enc_repl8b(src, dst)); 8541 ins_pipe(ialu_reg); 8542 %} 8543 8544 // Replicate scalar to packed byte values in Double register 8545 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8546 match(Set dst (Replicate8B src)); 8547 expand %{ 8548 iRegL tmp; 8549 Repl8B_reg_helper(tmp, src); 8550 regL_to_stkD(dst, tmp); 8551 %} 8552 %} 8553 8554 // Replicate scalar constant to packed byte values in Double register 8555 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ 8556 match(Set dst (Replicate8B src)); 8557 #ifdef _LP64 8558 size(36); 8559 #else 8560 size(8); 8561 #endif 8562 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" 8563 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} 8564 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); 8565 ins_pipe(loadConFD); 8566 %} 8567 8568 // Replicate scalar to packed char values into stack slot 8569 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8570 effect(DEF dst, USE src); 8571 format %{ "SLLX $src,48,$dst\n\t" 8572 "SRLX $dst,16,O7\n\t" 8573 "OR $dst,O7,$dst\n\t" 8574 "SRLX $dst,32,O7\n\t" 8575 "OR $dst,O7,$dst\t! replicate4C" %} 8576 ins_encode( enc_repl4s(src, dst) ); 8577 ins_pipe(ialu_reg); 8578 %} 8579 8580 // Replicate scalar to packed char values into stack slot 8581 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8582 match(Set dst (Replicate4C src)); 8583 expand %{ 8584 iRegL tmp; 8585 Repl4C_reg_helper(tmp, src); 8586 regL_to_stkD(dst, tmp); 8587 %} 8588 %} 8589 8590 // Replicate scalar constant to packed char values in Double register 8591 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ 8592 match(Set dst (Replicate4C src)); 8593 #ifdef _LP64 8594 size(36); 8595 #else 8596 size(8); 8597 #endif 8598 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" 8599 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8600 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8601 ins_pipe(loadConFD); 8602 %} 8603 8604 // Replicate scalar to packed short values into stack slot 8605 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8606 effect(DEF dst, USE src); 8607 format %{ "SLLX $src,48,$dst\n\t" 8608 "SRLX $dst,16,O7\n\t" 8609 "OR $dst,O7,$dst\n\t" 8610 "SRLX $dst,32,O7\n\t" 8611 "OR $dst,O7,$dst\t! replicate4S" %} 8612 ins_encode( enc_repl4s(src, dst) ); 8613 ins_pipe(ialu_reg); 8614 %} 8615 8616 // Replicate scalar to packed short values into stack slot 8617 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8618 match(Set dst (Replicate4S src)); 8619 expand %{ 8620 iRegL tmp; 8621 Repl4S_reg_helper(tmp, src); 8622 regL_to_stkD(dst, tmp); 8623 %} 8624 %} 8625 8626 // Replicate scalar constant to packed short values in Double register 8627 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ 8628 match(Set dst (Replicate4S src)); 8629 #ifdef _LP64 8630 size(36); 8631 #else 8632 size(8); 8633 #endif 8634 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" 8635 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8636 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8637 ins_pipe(loadConFD); 8638 %} 8639 8640 // Replicate scalar to packed int values in Double register 8641 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8642 effect(DEF dst, USE src); 8643 format %{ "SLLX $src,32,$dst\n\t" 8644 "SRLX $dst,32,O7\n\t" 8645 "OR $dst,O7,$dst\t! replicate2I" %} 8646 ins_encode( enc_repl2i(src, dst)); 8647 ins_pipe(ialu_reg); 8648 %} 8649 8650 // Replicate scalar to packed int values in Double register 8651 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8652 match(Set dst (Replicate2I src)); 8653 expand %{ 8654 iRegL tmp; 8655 Repl2I_reg_helper(tmp, src); 8656 regL_to_stkD(dst, tmp); 8657 %} 8658 %} 8659 8660 // Replicate scalar zero constant to packed int values in Double register 8661 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ 8662 match(Set dst (Replicate2I src)); 8663 #ifdef _LP64 8664 size(36); 8665 #else 8666 size(8); 8667 #endif 8668 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" 8669 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} 8670 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); 8671 ins_pipe(loadConFD); 8672 %} 8673 8674 //----------Control Flow Instructions------------------------------------------ 8675 // Compare Instructions 8676 // Compare Integers 8677 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8678 match(Set icc (CmpI op1 op2)); 8679 effect( DEF icc, USE op1, USE op2 ); 8680 8681 size(4); 8682 format %{ "CMP $op1,$op2" %} 8683 opcode(Assembler::subcc_op3, Assembler::arith_op); 8684 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8685 ins_pipe(ialu_cconly_reg_reg); 8686 %} 8687 8688 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8689 match(Set icc (CmpU op1 op2)); 8690 8691 size(4); 8692 format %{ "CMP $op1,$op2\t! unsigned" %} 8693 opcode(Assembler::subcc_op3, Assembler::arith_op); 8694 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8695 ins_pipe(ialu_cconly_reg_reg); 8696 %} 8697 8698 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8699 match(Set icc (CmpI op1 op2)); 8700 effect( DEF icc, USE op1 ); 8701 8702 size(4); 8703 format %{ "CMP $op1,$op2" %} 8704 opcode(Assembler::subcc_op3, Assembler::arith_op); 8705 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8706 ins_pipe(ialu_cconly_reg_imm); 8707 %} 8708 8709 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8710 match(Set icc (CmpI (AndI op1 op2) zero)); 8711 8712 size(4); 8713 format %{ "BTST $op2,$op1" %} 8714 opcode(Assembler::andcc_op3, Assembler::arith_op); 8715 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8716 ins_pipe(ialu_cconly_reg_reg_zero); 8717 %} 8718 8719 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8720 match(Set icc (CmpI (AndI op1 op2) zero)); 8721 8722 size(4); 8723 format %{ "BTST $op2,$op1" %} 8724 opcode(Assembler::andcc_op3, Assembler::arith_op); 8725 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8726 ins_pipe(ialu_cconly_reg_imm_zero); 8727 %} 8728 8729 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8730 match(Set xcc (CmpL op1 op2)); 8731 effect( DEF xcc, USE op1, USE op2 ); 8732 8733 size(4); 8734 format %{ "CMP $op1,$op2\t\t! long" %} 8735 opcode(Assembler::subcc_op3, Assembler::arith_op); 8736 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8737 ins_pipe(ialu_cconly_reg_reg); 8738 %} 8739 8740 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8741 match(Set xcc (CmpL op1 con)); 8742 effect( DEF xcc, USE op1, USE con ); 8743 8744 size(4); 8745 format %{ "CMP $op1,$con\t\t! long" %} 8746 opcode(Assembler::subcc_op3, Assembler::arith_op); 8747 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8748 ins_pipe(ialu_cconly_reg_reg); 8749 %} 8750 8751 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8752 match(Set xcc (CmpL (AndL op1 op2) zero)); 8753 effect( DEF xcc, USE op1, USE op2 ); 8754 8755 size(4); 8756 format %{ "BTST $op1,$op2\t\t! long" %} 8757 opcode(Assembler::andcc_op3, Assembler::arith_op); 8758 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8759 ins_pipe(ialu_cconly_reg_reg); 8760 %} 8761 8762 // useful for checking the alignment of a pointer: 8763 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8764 match(Set xcc (CmpL (AndL op1 con) zero)); 8765 effect( DEF xcc, USE op1, USE con ); 8766 8767 size(4); 8768 format %{ "BTST $op1,$con\t\t! long" %} 8769 opcode(Assembler::andcc_op3, Assembler::arith_op); 8770 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8771 ins_pipe(ialu_cconly_reg_reg); 8772 %} 8773 8774 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8775 match(Set icc (CmpU op1 op2)); 8776 8777 size(4); 8778 format %{ "CMP $op1,$op2\t! unsigned" %} 8779 opcode(Assembler::subcc_op3, Assembler::arith_op); 8780 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8781 ins_pipe(ialu_cconly_reg_imm); 8782 %} 8783 8784 // Compare Pointers 8785 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8786 match(Set pcc (CmpP op1 op2)); 8787 8788 size(4); 8789 format %{ "CMP $op1,$op2\t! ptr" %} 8790 opcode(Assembler::subcc_op3, Assembler::arith_op); 8791 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8792 ins_pipe(ialu_cconly_reg_reg); 8793 %} 8794 8795 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8796 match(Set pcc (CmpP op1 op2)); 8797 8798 size(4); 8799 format %{ "CMP $op1,$op2\t! ptr" %} 8800 opcode(Assembler::subcc_op3, Assembler::arith_op); 8801 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8802 ins_pipe(ialu_cconly_reg_imm); 8803 %} 8804 8805 // Compare Narrow oops 8806 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8807 match(Set icc (CmpN op1 op2)); 8808 8809 size(4); 8810 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8811 opcode(Assembler::subcc_op3, Assembler::arith_op); 8812 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8813 ins_pipe(ialu_cconly_reg_reg); 8814 %} 8815 8816 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8817 match(Set icc (CmpN op1 op2)); 8818 8819 size(4); 8820 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8821 opcode(Assembler::subcc_op3, Assembler::arith_op); 8822 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8823 ins_pipe(ialu_cconly_reg_imm); 8824 %} 8825 8826 //----------Max and Min-------------------------------------------------------- 8827 // Min Instructions 8828 // Conditional move for min 8829 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8830 effect( USE_DEF op2, USE op1, USE icc ); 8831 8832 size(4); 8833 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8834 opcode(Assembler::less); 8835 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8836 ins_pipe(ialu_reg_flags); 8837 %} 8838 8839 // Min Register with Register. 8840 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8841 match(Set op2 (MinI op1 op2)); 8842 ins_cost(DEFAULT_COST*2); 8843 expand %{ 8844 flagsReg icc; 8845 compI_iReg(icc,op1,op2); 8846 cmovI_reg_lt(op2,op1,icc); 8847 %} 8848 %} 8849 8850 // Max Instructions 8851 // Conditional move for max 8852 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8853 effect( USE_DEF op2, USE op1, USE icc ); 8854 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8855 opcode(Assembler::greater); 8856 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8857 ins_pipe(ialu_reg_flags); 8858 %} 8859 8860 // Max Register with Register 8861 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8862 match(Set op2 (MaxI op1 op2)); 8863 ins_cost(DEFAULT_COST*2); 8864 expand %{ 8865 flagsReg icc; 8866 compI_iReg(icc,op1,op2); 8867 cmovI_reg_gt(op2,op1,icc); 8868 %} 8869 %} 8870 8871 8872 //----------Float Compares---------------------------------------------------- 8873 // Compare floating, generate condition code 8874 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8875 match(Set fcc (CmpF src1 src2)); 8876 8877 size(4); 8878 format %{ "FCMPs $fcc,$src1,$src2" %} 8879 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8880 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8881 ins_pipe(faddF_fcc_reg_reg_zero); 8882 %} 8883 8884 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8885 match(Set fcc (CmpD src1 src2)); 8886 8887 size(4); 8888 format %{ "FCMPd $fcc,$src1,$src2" %} 8889 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8890 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8891 ins_pipe(faddD_fcc_reg_reg_zero); 8892 %} 8893 8894 8895 // Compare floating, generate -1,0,1 8896 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8897 match(Set dst (CmpF3 src1 src2)); 8898 effect(KILL fcc0); 8899 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8900 format %{ "fcmpl $dst,$src1,$src2" %} 8901 // Primary = float 8902 opcode( true ); 8903 ins_encode( floating_cmp( dst, src1, src2 ) ); 8904 ins_pipe( floating_cmp ); 8905 %} 8906 8907 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8908 match(Set dst (CmpD3 src1 src2)); 8909 effect(KILL fcc0); 8910 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8911 format %{ "dcmpl $dst,$src1,$src2" %} 8912 // Primary = double (not float) 8913 opcode( false ); 8914 ins_encode( floating_cmp( dst, src1, src2 ) ); 8915 ins_pipe( floating_cmp ); 8916 %} 8917 8918 //----------Branches--------------------------------------------------------- 8919 // Jump 8920 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8921 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8922 match(Jump switch_val); 8923 8924 ins_cost(350); 8925 8926 format %{ "SETHI [hi(table_base)],O7\n\t" 8927 "ADD O7, lo(table_base), O7\n\t" 8928 "LD [O7+$switch_val], O7\n\t" 8929 "JUMP O7" 8930 %} 8931 ins_encode( jump_enc( switch_val, table) ); 8932 ins_pc_relative(1); 8933 ins_pipe(ialu_reg_reg); 8934 %} 8935 8936 // Direct Branch. Use V8 version with longer range. 8937 instruct branch(label labl) %{ 8938 match(Goto); 8939 effect(USE labl); 8940 8941 size(8); 8942 ins_cost(BRANCH_COST); 8943 format %{ "BA $labl" %} 8944 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 8945 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 8946 ins_encode( enc_ba( labl ) ); 8947 ins_pc_relative(1); 8948 ins_pipe(br); 8949 %} 8950 8951 // Conditional Direct Branch 8952 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8953 match(If cmp icc); 8954 effect(USE labl); 8955 8956 size(8); 8957 ins_cost(BRANCH_COST); 8958 format %{ "BP$cmp $icc,$labl" %} 8959 // Prim = bits 24-22, Secnd = bits 31-30 8960 ins_encode( enc_bp( labl, cmp, icc ) ); 8961 ins_pc_relative(1); 8962 ins_pipe(br_cc); 8963 %} 8964 8965 // Branch-on-register tests all 64 bits. We assume that values 8966 // in 64-bit registers always remains zero or sign extended 8967 // unless our code munges the high bits. Interrupts can chop 8968 // the high order bits to zero or sign at any time. 8969 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 8970 match(If cmp (CmpI op1 zero)); 8971 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8972 effect(USE labl); 8973 8974 size(8); 8975 ins_cost(BRANCH_COST); 8976 format %{ "BR$cmp $op1,$labl" %} 8977 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8978 ins_pc_relative(1); 8979 ins_pipe(br_reg); 8980 %} 8981 8982 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 8983 match(If cmp (CmpP op1 null)); 8984 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8985 effect(USE labl); 8986 8987 size(8); 8988 ins_cost(BRANCH_COST); 8989 format %{ "BR$cmp $op1,$labl" %} 8990 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8991 ins_pc_relative(1); 8992 ins_pipe(br_reg); 8993 %} 8994 8995 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 8996 match(If cmp (CmpL op1 zero)); 8997 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8998 effect(USE labl); 8999 9000 size(8); 9001 ins_cost(BRANCH_COST); 9002 format %{ "BR$cmp $op1,$labl" %} 9003 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9004 ins_pc_relative(1); 9005 ins_pipe(br_reg); 9006 %} 9007 9008 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9009 match(If cmp icc); 9010 effect(USE labl); 9011 9012 format %{ "BP$cmp $icc,$labl" %} 9013 // Prim = bits 24-22, Secnd = bits 31-30 9014 ins_encode( enc_bp( labl, cmp, icc ) ); 9015 ins_pc_relative(1); 9016 ins_pipe(br_cc); 9017 %} 9018 9019 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9020 match(If cmp pcc); 9021 effect(USE labl); 9022 9023 size(8); 9024 ins_cost(BRANCH_COST); 9025 format %{ "BP$cmp $pcc,$labl" %} 9026 // Prim = bits 24-22, Secnd = bits 31-30 9027 ins_encode( enc_bpx( labl, cmp, pcc ) ); 9028 ins_pc_relative(1); 9029 ins_pipe(br_cc); 9030 %} 9031 9032 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9033 match(If cmp fcc); 9034 effect(USE labl); 9035 9036 size(8); 9037 ins_cost(BRANCH_COST); 9038 format %{ "FBP$cmp $fcc,$labl" %} 9039 // Prim = bits 24-22, Secnd = bits 31-30 9040 ins_encode( enc_fbp( labl, cmp, fcc ) ); 9041 ins_pc_relative(1); 9042 ins_pipe(br_fcc); 9043 %} 9044 9045 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9046 match(CountedLoopEnd cmp icc); 9047 effect(USE labl); 9048 9049 size(8); 9050 ins_cost(BRANCH_COST); 9051 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9052 // Prim = bits 24-22, Secnd = bits 31-30 9053 ins_encode( enc_bp( labl, cmp, icc ) ); 9054 ins_pc_relative(1); 9055 ins_pipe(br_cc); 9056 %} 9057 9058 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9059 match(CountedLoopEnd cmp icc); 9060 effect(USE labl); 9061 9062 size(8); 9063 ins_cost(BRANCH_COST); 9064 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9065 // Prim = bits 24-22, Secnd = bits 31-30 9066 ins_encode( enc_bp( labl, cmp, icc ) ); 9067 ins_pc_relative(1); 9068 ins_pipe(br_cc); 9069 %} 9070 9071 // ============================================================================ 9072 // Long Compare 9073 // 9074 // Currently we hold longs in 2 registers. Comparing such values efficiently 9075 // is tricky. The flavor of compare used depends on whether we are testing 9076 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9077 // The GE test is the negated LT test. The LE test can be had by commuting 9078 // the operands (yielding a GE test) and then negating; negate again for the 9079 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9080 // NE test is negated from that. 9081 9082 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9083 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9084 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9085 // are collapsed internally in the ADLC's dfa-gen code. The match for 9086 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9087 // foo match ends up with the wrong leaf. One fix is to not match both 9088 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9089 // both forms beat the trinary form of long-compare and both are very useful 9090 // on Intel which has so few registers. 9091 9092 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9093 match(If cmp xcc); 9094 effect(USE labl); 9095 9096 size(8); 9097 ins_cost(BRANCH_COST); 9098 format %{ "BP$cmp $xcc,$labl" %} 9099 // Prim = bits 24-22, Secnd = bits 31-30 9100 ins_encode( enc_bpl( labl, cmp, xcc ) ); 9101 ins_pc_relative(1); 9102 ins_pipe(br_cc); 9103 %} 9104 9105 // Manifest a CmpL3 result in an integer register. Very painful. 9106 // This is the test to avoid. 9107 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9108 match(Set dst (CmpL3 src1 src2) ); 9109 effect( KILL ccr ); 9110 ins_cost(6*DEFAULT_COST); 9111 size(24); 9112 format %{ "CMP $src1,$src2\t\t! long\n" 9113 "\tBLT,a,pn done\n" 9114 "\tMOV -1,$dst\t! delay slot\n" 9115 "\tBGT,a,pn done\n" 9116 "\tMOV 1,$dst\t! delay slot\n" 9117 "\tCLR $dst\n" 9118 "done:" %} 9119 ins_encode( cmpl_flag(src1,src2,dst) ); 9120 ins_pipe(cmpL_reg); 9121 %} 9122 9123 // Conditional move 9124 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9125 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9126 ins_cost(150); 9127 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9128 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9129 ins_pipe(ialu_reg); 9130 %} 9131 9132 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9133 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9134 ins_cost(140); 9135 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9136 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9137 ins_pipe(ialu_imm); 9138 %} 9139 9140 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9141 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9142 ins_cost(150); 9143 format %{ "MOV$cmp $xcc,$src,$dst" %} 9144 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9145 ins_pipe(ialu_reg); 9146 %} 9147 9148 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9149 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9150 ins_cost(140); 9151 format %{ "MOV$cmp $xcc,$src,$dst" %} 9152 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9153 ins_pipe(ialu_imm); 9154 %} 9155 9156 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9157 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9158 ins_cost(150); 9159 format %{ "MOV$cmp $xcc,$src,$dst" %} 9160 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9161 ins_pipe(ialu_reg); 9162 %} 9163 9164 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9165 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9166 ins_cost(150); 9167 format %{ "MOV$cmp $xcc,$src,$dst" %} 9168 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9169 ins_pipe(ialu_reg); 9170 %} 9171 9172 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9173 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9174 ins_cost(140); 9175 format %{ "MOV$cmp $xcc,$src,$dst" %} 9176 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9177 ins_pipe(ialu_imm); 9178 %} 9179 9180 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9181 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9182 ins_cost(150); 9183 opcode(0x101); 9184 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9185 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9186 ins_pipe(int_conditional_float_move); 9187 %} 9188 9189 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9190 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9191 ins_cost(150); 9192 opcode(0x102); 9193 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9194 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9195 ins_pipe(int_conditional_float_move); 9196 %} 9197 9198 // ============================================================================ 9199 // Safepoint Instruction 9200 instruct safePoint_poll(iRegP poll) %{ 9201 match(SafePoint poll); 9202 effect(USE poll); 9203 9204 size(4); 9205 #ifdef _LP64 9206 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9207 #else 9208 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9209 #endif 9210 ins_encode %{ 9211 __ relocate(relocInfo::poll_type); 9212 __ ld_ptr($poll$$Register, 0, G0); 9213 %} 9214 ins_pipe(loadPollP); 9215 %} 9216 9217 // ============================================================================ 9218 // Call Instructions 9219 // Call Java Static Instruction 9220 instruct CallStaticJavaDirect( method meth ) %{ 9221 match(CallStaticJava); 9222 effect(USE meth); 9223 9224 size(8); 9225 ins_cost(CALL_COST); 9226 format %{ "CALL,static ; NOP ==> " %} 9227 ins_encode( Java_Static_Call( meth ), call_epilog ); 9228 ins_pc_relative(1); 9229 ins_pipe(simple_call); 9230 %} 9231 9232 // Call Java Dynamic Instruction 9233 instruct CallDynamicJavaDirect( method meth ) %{ 9234 match(CallDynamicJava); 9235 effect(USE meth); 9236 9237 ins_cost(CALL_COST); 9238 format %{ "SET (empty),R_G5\n\t" 9239 "CALL,dynamic ; NOP ==> " %} 9240 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9241 ins_pc_relative(1); 9242 ins_pipe(call); 9243 %} 9244 9245 // Call Runtime Instruction 9246 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9247 match(CallRuntime); 9248 effect(USE meth, KILL l7); 9249 ins_cost(CALL_COST); 9250 format %{ "CALL,runtime" %} 9251 ins_encode( Java_To_Runtime( meth ), 9252 call_epilog, adjust_long_from_native_call ); 9253 ins_pc_relative(1); 9254 ins_pipe(simple_call); 9255 %} 9256 9257 // Call runtime without safepoint - same as CallRuntime 9258 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9259 match(CallLeaf); 9260 effect(USE meth, KILL l7); 9261 ins_cost(CALL_COST); 9262 format %{ "CALL,runtime leaf" %} 9263 ins_encode( Java_To_Runtime( meth ), 9264 call_epilog, 9265 adjust_long_from_native_call ); 9266 ins_pc_relative(1); 9267 ins_pipe(simple_call); 9268 %} 9269 9270 // Call runtime without safepoint - same as CallLeaf 9271 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9272 match(CallLeafNoFP); 9273 effect(USE meth, KILL l7); 9274 ins_cost(CALL_COST); 9275 format %{ "CALL,runtime leaf nofp" %} 9276 ins_encode( Java_To_Runtime( meth ), 9277 call_epilog, 9278 adjust_long_from_native_call ); 9279 ins_pc_relative(1); 9280 ins_pipe(simple_call); 9281 %} 9282 9283 // Tail Call; Jump from runtime stub to Java code. 9284 // Also known as an 'interprocedural jump'. 9285 // Target of jump will eventually return to caller. 9286 // TailJump below removes the return address. 9287 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9288 match(TailCall jump_target method_oop ); 9289 9290 ins_cost(CALL_COST); 9291 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9292 ins_encode(form_jmpl(jump_target)); 9293 ins_pipe(tail_call); 9294 %} 9295 9296 9297 // Return Instruction 9298 instruct Ret() %{ 9299 match(Return); 9300 9301 // The epilogue node did the ret already. 9302 size(0); 9303 format %{ "! return" %} 9304 ins_encode(); 9305 ins_pipe(empty); 9306 %} 9307 9308 9309 // Tail Jump; remove the return address; jump to target. 9310 // TailCall above leaves the return address around. 9311 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9312 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9313 // "restore" before this instruction (in Epilogue), we need to materialize it 9314 // in %i0. 9315 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9316 match( TailJump jump_target ex_oop ); 9317 ins_cost(CALL_COST); 9318 format %{ "! discard R_O7\n\t" 9319 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9320 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9321 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9322 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9323 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9324 ins_pipe(tail_call); 9325 %} 9326 9327 // Create exception oop: created by stack-crawling runtime code. 9328 // Created exception is now available to this handler, and is setup 9329 // just prior to jumping to this handler. No code emitted. 9330 instruct CreateException( o0RegP ex_oop ) 9331 %{ 9332 match(Set ex_oop (CreateEx)); 9333 ins_cost(0); 9334 9335 size(0); 9336 // use the following format syntax 9337 format %{ "! exception oop is in R_O0; no code emitted" %} 9338 ins_encode(); 9339 ins_pipe(empty); 9340 %} 9341 9342 9343 // Rethrow exception: 9344 // The exception oop will come in the first argument position. 9345 // Then JUMP (not call) to the rethrow stub code. 9346 instruct RethrowException() 9347 %{ 9348 match(Rethrow); 9349 ins_cost(CALL_COST); 9350 9351 // use the following format syntax 9352 format %{ "Jmp rethrow_stub" %} 9353 ins_encode(enc_rethrow); 9354 ins_pipe(tail_call); 9355 %} 9356 9357 9358 // Die now 9359 instruct ShouldNotReachHere( ) 9360 %{ 9361 match(Halt); 9362 ins_cost(CALL_COST); 9363 9364 size(4); 9365 // Use the following format syntax 9366 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9367 ins_encode( form2_illtrap() ); 9368 ins_pipe(tail_call); 9369 %} 9370 9371 // ============================================================================ 9372 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9373 // array for an instance of the superklass. Set a hidden internal cache on a 9374 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9375 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9376 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9377 match(Set index (PartialSubtypeCheck sub super)); 9378 effect( KILL pcc, KILL o7 ); 9379 ins_cost(DEFAULT_COST*10); 9380 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9381 ins_encode( enc_PartialSubtypeCheck() ); 9382 ins_pipe(partial_subtype_check_pipe); 9383 %} 9384 9385 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9386 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9387 effect( KILL idx, KILL o7 ); 9388 ins_cost(DEFAULT_COST*10); 9389 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9390 ins_encode( enc_PartialSubtypeCheck() ); 9391 ins_pipe(partial_subtype_check_pipe); 9392 %} 9393 9394 9395 // ============================================================================ 9396 // inlined locking and unlocking 9397 9398 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9399 match(Set pcc (FastLock object box)); 9400 9401 effect(KILL scratch, TEMP scratch2); 9402 ins_cost(100); 9403 9404 size(4*112); // conservative overestimation ... 9405 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9406 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9407 ins_pipe(long_memory_op); 9408 %} 9409 9410 9411 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9412 match(Set pcc (FastUnlock object box)); 9413 effect(KILL scratch, TEMP scratch2); 9414 ins_cost(100); 9415 9416 size(4*120); // conservative overestimation ... 9417 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9418 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9419 ins_pipe(long_memory_op); 9420 %} 9421 9422 // Count and Base registers are fixed because the allocator cannot 9423 // kill unknown registers. The encodings are generic. 9424 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9425 match(Set dummy (ClearArray cnt base)); 9426 effect(TEMP temp, KILL ccr); 9427 ins_cost(300); 9428 format %{ "MOV $cnt,$temp\n" 9429 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9430 " BRge loop\t\t! Clearing loop\n" 9431 " STX G0,[$base+$temp]\t! delay slot" %} 9432 ins_encode( enc_Clear_Array(cnt, base, temp) ); 9433 ins_pipe(long_memory_op); 9434 %} 9435 9436 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9437 o7RegI tmp, flagsReg ccr) %{ 9438 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9439 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9440 ins_cost(300); 9441 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9442 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 9443 ins_pipe(long_memory_op); 9444 %} 9445 9446 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9447 o7RegI tmp, flagsReg ccr) %{ 9448 match(Set result (StrEquals (Binary str1 str2) cnt)); 9449 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9450 ins_cost(300); 9451 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 9452 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 9453 ins_pipe(long_memory_op); 9454 %} 9455 9456 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9457 o7RegI tmp2, flagsReg ccr) %{ 9458 match(Set result (AryEq ary1 ary2)); 9459 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9460 ins_cost(300); 9461 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9462 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 9463 ins_pipe(long_memory_op); 9464 %} 9465 9466 9467 //---------- Zeros Count Instructions ------------------------------------------ 9468 9469 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9470 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9471 match(Set dst (CountLeadingZerosI src)); 9472 effect(TEMP dst, TEMP tmp, KILL cr); 9473 9474 // x |= (x >> 1); 9475 // x |= (x >> 2); 9476 // x |= (x >> 4); 9477 // x |= (x >> 8); 9478 // x |= (x >> 16); 9479 // return (WORDBITS - popc(x)); 9480 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 9481 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 9482 "OR $dst,$tmp,$dst\n\t" 9483 "SRL $dst,2,$tmp\n\t" 9484 "OR $dst,$tmp,$dst\n\t" 9485 "SRL $dst,4,$tmp\n\t" 9486 "OR $dst,$tmp,$dst\n\t" 9487 "SRL $dst,8,$tmp\n\t" 9488 "OR $dst,$tmp,$dst\n\t" 9489 "SRL $dst,16,$tmp\n\t" 9490 "OR $dst,$tmp,$dst\n\t" 9491 "POPC $dst,$dst\n\t" 9492 "MOV 32,$tmp\n\t" 9493 "SUB $tmp,$dst,$dst" %} 9494 ins_encode %{ 9495 Register Rdst = $dst$$Register; 9496 Register Rsrc = $src$$Register; 9497 Register Rtmp = $tmp$$Register; 9498 __ srl(Rsrc, 1, Rtmp); 9499 __ srl(Rsrc, 0, Rdst); 9500 __ or3(Rdst, Rtmp, Rdst); 9501 __ srl(Rdst, 2, Rtmp); 9502 __ or3(Rdst, Rtmp, Rdst); 9503 __ srl(Rdst, 4, Rtmp); 9504 __ or3(Rdst, Rtmp, Rdst); 9505 __ srl(Rdst, 8, Rtmp); 9506 __ or3(Rdst, Rtmp, Rdst); 9507 __ srl(Rdst, 16, Rtmp); 9508 __ or3(Rdst, Rtmp, Rdst); 9509 __ popc(Rdst, Rdst); 9510 __ mov(BitsPerInt, Rtmp); 9511 __ sub(Rtmp, Rdst, Rdst); 9512 %} 9513 ins_pipe(ialu_reg); 9514 %} 9515 9516 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9517 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9518 match(Set dst (CountLeadingZerosL src)); 9519 effect(TEMP dst, TEMP tmp, KILL cr); 9520 9521 // x |= (x >> 1); 9522 // x |= (x >> 2); 9523 // x |= (x >> 4); 9524 // x |= (x >> 8); 9525 // x |= (x >> 16); 9526 // x |= (x >> 32); 9527 // return (WORDBITS - popc(x)); 9528 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 9529 "OR $src,$tmp,$dst\n\t" 9530 "SRLX $dst,2,$tmp\n\t" 9531 "OR $dst,$tmp,$dst\n\t" 9532 "SRLX $dst,4,$tmp\n\t" 9533 "OR $dst,$tmp,$dst\n\t" 9534 "SRLX $dst,8,$tmp\n\t" 9535 "OR $dst,$tmp,$dst\n\t" 9536 "SRLX $dst,16,$tmp\n\t" 9537 "OR $dst,$tmp,$dst\n\t" 9538 "SRLX $dst,32,$tmp\n\t" 9539 "OR $dst,$tmp,$dst\n\t" 9540 "POPC $dst,$dst\n\t" 9541 "MOV 64,$tmp\n\t" 9542 "SUB $tmp,$dst,$dst" %} 9543 ins_encode %{ 9544 Register Rdst = $dst$$Register; 9545 Register Rsrc = $src$$Register; 9546 Register Rtmp = $tmp$$Register; 9547 __ srlx(Rsrc, 1, Rtmp); 9548 __ or3(Rsrc, Rtmp, Rdst); 9549 __ srlx(Rdst, 2, Rtmp); 9550 __ or3(Rdst, Rtmp, Rdst); 9551 __ srlx(Rdst, 4, Rtmp); 9552 __ or3(Rdst, Rtmp, Rdst); 9553 __ srlx(Rdst, 8, Rtmp); 9554 __ or3(Rdst, Rtmp, Rdst); 9555 __ srlx(Rdst, 16, Rtmp); 9556 __ or3(Rdst, Rtmp, Rdst); 9557 __ srlx(Rdst, 32, Rtmp); 9558 __ or3(Rdst, Rtmp, Rdst); 9559 __ popc(Rdst, Rdst); 9560 __ mov(BitsPerLong, Rtmp); 9561 __ sub(Rtmp, Rdst, Rdst); 9562 %} 9563 ins_pipe(ialu_reg); 9564 %} 9565 9566 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ 9567 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9568 match(Set dst (CountTrailingZerosI src)); 9569 effect(TEMP dst, KILL cr); 9570 9571 // return popc(~x & (x - 1)); 9572 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 9573 "ANDN $dst,$src,$dst\n\t" 9574 "SRL $dst,R_G0,$dst\n\t" 9575 "POPC $dst,$dst" %} 9576 ins_encode %{ 9577 Register Rdst = $dst$$Register; 9578 Register Rsrc = $src$$Register; 9579 __ sub(Rsrc, 1, Rdst); 9580 __ andn(Rdst, Rsrc, Rdst); 9581 __ srl(Rdst, G0, Rdst); 9582 __ popc(Rdst, Rdst); 9583 %} 9584 ins_pipe(ialu_reg); 9585 %} 9586 9587 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ 9588 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9589 match(Set dst (CountTrailingZerosL src)); 9590 effect(TEMP dst, KILL cr); 9591 9592 // return popc(~x & (x - 1)); 9593 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 9594 "ANDN $dst,$src,$dst\n\t" 9595 "POPC $dst,$dst" %} 9596 ins_encode %{ 9597 Register Rdst = $dst$$Register; 9598 Register Rsrc = $src$$Register; 9599 __ sub(Rsrc, 1, Rdst); 9600 __ andn(Rdst, Rsrc, Rdst); 9601 __ popc(Rdst, Rdst); 9602 %} 9603 ins_pipe(ialu_reg); 9604 %} 9605 9606 9607 //---------- Population Count Instructions ------------------------------------- 9608 9609 instruct popCountI(iRegI dst, iRegI src) %{ 9610 predicate(UsePopCountInstruction); 9611 match(Set dst (PopCountI src)); 9612 9613 format %{ "POPC $src, $dst" %} 9614 ins_encode %{ 9615 __ popc($src$$Register, $dst$$Register); 9616 %} 9617 ins_pipe(ialu_reg); 9618 %} 9619 9620 // Note: Long.bitCount(long) returns an int. 9621 instruct popCountL(iRegI dst, iRegL src) %{ 9622 predicate(UsePopCountInstruction); 9623 match(Set dst (PopCountL src)); 9624 9625 format %{ "POPC $src, $dst" %} 9626 ins_encode %{ 9627 __ popc($src$$Register, $dst$$Register); 9628 %} 9629 ins_pipe(ialu_reg); 9630 %} 9631 9632 9633 // ============================================================================ 9634 //------------Bytes reverse-------------------------------------------------- 9635 9636 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 9637 match(Set dst (ReverseBytesI src)); 9638 9639 // Op cost is artificially doubled to make sure that load or store 9640 // instructions are preferred over this one which requires a spill 9641 // onto a stack slot. 9642 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9643 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9644 9645 ins_encode %{ 9646 __ set($src$$disp + STACK_BIAS, O7); 9647 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9648 %} 9649 ins_pipe( iload_mem ); 9650 %} 9651 9652 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 9653 match(Set dst (ReverseBytesL src)); 9654 9655 // Op cost is artificially doubled to make sure that load or store 9656 // instructions are preferred over this one which requires a spill 9657 // onto a stack slot. 9658 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9659 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9660 9661 ins_encode %{ 9662 __ set($src$$disp + STACK_BIAS, O7); 9663 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9664 %} 9665 ins_pipe( iload_mem ); 9666 %} 9667 9668 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 9669 match(Set dst (ReverseBytesUS src)); 9670 9671 // Op cost is artificially doubled to make sure that load or store 9672 // instructions are preferred over this one which requires a spill 9673 // onto a stack slot. 9674 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9675 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 9676 9677 ins_encode %{ 9678 // the value was spilled as an int so bias the load 9679 __ set($src$$disp + STACK_BIAS + 2, O7); 9680 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9681 %} 9682 ins_pipe( iload_mem ); 9683 %} 9684 9685 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 9686 match(Set dst (ReverseBytesS src)); 9687 9688 // Op cost is artificially doubled to make sure that load or store 9689 // instructions are preferred over this one which requires a spill 9690 // onto a stack slot. 9691 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9692 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 9693 9694 ins_encode %{ 9695 // the value was spilled as an int so bias the load 9696 __ set($src$$disp + STACK_BIAS + 2, O7); 9697 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9698 %} 9699 ins_pipe( iload_mem ); 9700 %} 9701 9702 // Load Integer reversed byte order 9703 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 9704 match(Set dst (ReverseBytesI (LoadI src))); 9705 9706 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9707 size(4); 9708 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9709 9710 ins_encode %{ 9711 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9712 %} 9713 ins_pipe(iload_mem); 9714 %} 9715 9716 // Load Long - aligned and reversed 9717 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 9718 match(Set dst (ReverseBytesL (LoadL src))); 9719 9720 ins_cost(MEMORY_REF_COST); 9721 size(4); 9722 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9723 9724 ins_encode %{ 9725 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9726 %} 9727 ins_pipe(iload_mem); 9728 %} 9729 9730 // Load unsigned short / char reversed byte order 9731 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 9732 match(Set dst (ReverseBytesUS (LoadUS src))); 9733 9734 ins_cost(MEMORY_REF_COST); 9735 size(4); 9736 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 9737 9738 ins_encode %{ 9739 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9740 %} 9741 ins_pipe(iload_mem); 9742 %} 9743 9744 // Load short reversed byte order 9745 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 9746 match(Set dst (ReverseBytesS (LoadS src))); 9747 9748 ins_cost(MEMORY_REF_COST); 9749 size(4); 9750 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 9751 9752 ins_encode %{ 9753 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9754 %} 9755 ins_pipe(iload_mem); 9756 %} 9757 9758 // Store Integer reversed byte order 9759 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 9760 match(Set dst (StoreI dst (ReverseBytesI src))); 9761 9762 ins_cost(MEMORY_REF_COST); 9763 size(4); 9764 format %{ "STWA $src, $dst\t!asi=primary_little" %} 9765 9766 ins_encode %{ 9767 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9768 %} 9769 ins_pipe(istore_mem_reg); 9770 %} 9771 9772 // Store Long reversed byte order 9773 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 9774 match(Set dst (StoreL dst (ReverseBytesL src))); 9775 9776 ins_cost(MEMORY_REF_COST); 9777 size(4); 9778 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9779 9780 ins_encode %{ 9781 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9782 %} 9783 ins_pipe(istore_mem_reg); 9784 %} 9785 9786 // Store unsighed short/char reversed byte order 9787 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 9788 match(Set dst (StoreC dst (ReverseBytesUS src))); 9789 9790 ins_cost(MEMORY_REF_COST); 9791 size(4); 9792 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9793 9794 ins_encode %{ 9795 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9796 %} 9797 ins_pipe(istore_mem_reg); 9798 %} 9799 9800 // Store short reversed byte order 9801 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 9802 match(Set dst (StoreC dst (ReverseBytesS src))); 9803 9804 ins_cost(MEMORY_REF_COST); 9805 size(4); 9806 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9807 9808 ins_encode %{ 9809 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9810 %} 9811 ins_pipe(istore_mem_reg); 9812 %} 9813 9814 //----------PEEPHOLE RULES----------------------------------------------------- 9815 // These must follow all instruction definitions as they use the names 9816 // defined in the instructions definitions. 9817 // 9818 // peepmatch ( root_instr_name [preceding_instruction]* ); 9819 // 9820 // peepconstraint %{ 9821 // (instruction_number.operand_name relational_op instruction_number.operand_name 9822 // [, ...] ); 9823 // // instruction numbers are zero-based using left to right order in peepmatch 9824 // 9825 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9826 // // provide an instruction_number.operand_name for each operand that appears 9827 // // in the replacement instruction's match rule 9828 // 9829 // ---------VM FLAGS--------------------------------------------------------- 9830 // 9831 // All peephole optimizations can be turned off using -XX:-OptoPeephole 9832 // 9833 // Each peephole rule is given an identifying number starting with zero and 9834 // increasing by one in the order seen by the parser. An individual peephole 9835 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9836 // on the command-line. 9837 // 9838 // ---------CURRENT LIMITATIONS---------------------------------------------- 9839 // 9840 // Only match adjacent instructions in same basic block 9841 // Only equality constraints 9842 // Only constraints between operands, not (0.dest_reg == EAX_enc) 9843 // Only one replacement instruction 9844 // 9845 // ---------EXAMPLE---------------------------------------------------------- 9846 // 9847 // // pertinent parts of existing instructions in architecture description 9848 // instruct movI(eRegI dst, eRegI src) %{ 9849 // match(Set dst (CopyI src)); 9850 // %} 9851 // 9852 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9853 // match(Set dst (AddI dst src)); 9854 // effect(KILL cr); 9855 // %} 9856 // 9857 // // Change (inc mov) to lea 9858 // peephole %{ 9859 // // increment preceeded by register-register move 9860 // peepmatch ( incI_eReg movI ); 9861 // // require that the destination register of the increment 9862 // // match the destination register of the move 9863 // peepconstraint ( 0.dst == 1.dst ); 9864 // // construct a replacement instruction that sets 9865 // // the destination to ( move's source register + one ) 9866 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9867 // %} 9868 // 9869 9870 // // Change load of spilled value to only a spill 9871 // instruct storeI(memory mem, eRegI src) %{ 9872 // match(Set mem (StoreI mem src)); 9873 // %} 9874 // 9875 // instruct loadI(eRegI dst, memory mem) %{ 9876 // match(Set dst (LoadI mem)); 9877 // %} 9878 // 9879 // peephole %{ 9880 // peepmatch ( loadI storeI ); 9881 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9882 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9883 // %} 9884 9885 //----------SMARTSPILL RULES--------------------------------------------------- 9886 // These must follow all instruction definitions as they use the names 9887 // defined in the instructions definitions. 9888 // 9889 // SPARC will probably not have any of these rules due to RISC instruction set. 9890 9891 //----------PIPELINE----------------------------------------------------------- 9892 // Rules which define the behavior of the target architectures pipeline.