1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129
130 #else
131 // rscratch1 will apear in 32bit code that is dead but of course must compile
132 // Using noreg ensures if the dead code is incorrectly live and executed it
133 // will cause an assertion failure
134 #define rscratch1 noreg
135
136 #endif // _LP64
137
138 // JSR 292 fixed register usages:
139 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
140
141 // Address is an abstraction used to represent a memory location
142 // using any of the amd64 addressing modes with one object.
143 //
144 // Note: A register location is represented via a Register, not
145 // via an address for efficiency & simplicity reasons.
146
147 class ArrayAddress;
148
149 class Address VALUE_OBJ_CLASS_SPEC {
150 public:
151 enum ScaleFactor {
152 no_scale = -1,
153 times_1 = 0,
154 times_2 = 1,
155 times_4 = 2,
156 times_8 = 3,
157 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
158 };
159 static ScaleFactor times(int size) {
160 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
161 if (size == 8) return times_8;
162 if (size == 4) return times_4;
163 if (size == 2) return times_2;
164 return times_1;
165 }
166 static int scale_size(ScaleFactor scale) {
167 assert(scale != no_scale, "");
168 assert(((1 << (int)times_1) == 1 &&
169 (1 << (int)times_2) == 2 &&
170 (1 << (int)times_4) == 4 &&
171 (1 << (int)times_8) == 8), "");
172 return (1 << (int)scale);
173 }
174
175 private:
176 Register _base;
177 Register _index;
178 ScaleFactor _scale;
179 int _disp;
180 RelocationHolder _rspec;
181
182 // Easily misused constructors make them private
183 // %%% can we make these go away?
184 NOT_LP64(Address(address loc, RelocationHolder spec);)
185 Address(int disp, address loc, relocInfo::relocType rtype);
186 Address(int disp, address loc, RelocationHolder spec);
187
188 public:
189
190 int disp() { return _disp; }
191 // creation
192 Address()
193 : _base(noreg),
194 _index(noreg),
195 _scale(no_scale),
196 _disp(0) {
197 }
198
199 // No default displacement otherwise Register can be implicitly
200 // converted to 0(Register) which is quite a different animal.
201
202 Address(Register base, int disp)
203 : _base(base),
204 _index(noreg),
205 _scale(no_scale),
206 _disp(disp) {
207 }
208
209 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
210 : _base (base),
211 _index(index),
212 _scale(scale),
213 _disp (disp) {
214 assert(!index->is_valid() == (scale == Address::no_scale),
215 "inconsistent address");
216 }
217
218 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
219 : _base (base),
220 _index(index.register_or_noreg()),
221 _scale(scale),
222 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
223 if (!index.is_register()) scale = Address::no_scale;
224 assert(!_index->is_valid() == (scale == Address::no_scale),
225 "inconsistent address");
226 }
227
228 Address plus_disp(int disp) const {
229 Address a = (*this);
230 a._disp += disp;
231 return a;
232 }
233
234 // The following two overloads are used in connection with the
235 // ByteSize type (see sizes.hpp). They simplify the use of
236 // ByteSize'd arguments in assembly code. Note that their equivalent
237 // for the optimized build are the member functions with int disp
238 // argument since ByteSize is mapped to an int type in that case.
239 //
240 // Note: DO NOT introduce similar overloaded functions for WordSize
241 // arguments as in the optimized mode, both ByteSize and WordSize
242 // are mapped to the same type and thus the compiler cannot make a
243 // distinction anymore (=> compiler errors).
244
245 #ifdef ASSERT
246 Address(Register base, ByteSize disp)
247 : _base(base),
248 _index(noreg),
249 _scale(no_scale),
250 _disp(in_bytes(disp)) {
251 }
252
253 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
254 : _base(base),
255 _index(index),
256 _scale(scale),
257 _disp(in_bytes(disp)) {
258 assert(!index->is_valid() == (scale == Address::no_scale),
259 "inconsistent address");
260 }
261
262 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
263 : _base (base),
264 _index(index.register_or_noreg()),
265 _scale(scale),
266 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
267 if (!index.is_register()) scale = Address::no_scale;
268 assert(!_index->is_valid() == (scale == Address::no_scale),
269 "inconsistent address");
270 }
271
272 #endif // ASSERT
273
274 // accessors
275 bool uses(Register reg) const { return _base == reg || _index == reg; }
276 Register base() const { return _base; }
277 Register index() const { return _index; }
278 ScaleFactor scale() const { return _scale; }
279 int disp() const { return _disp; }
280
281 // Convert the raw encoding form into the form expected by the constructor for
282 // Address. An index of 4 (rsp) corresponds to having no index, so convert
283 // that to noreg for the Address constructor.
284 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
285
286 static Address make_array(ArrayAddress);
287
288 private:
289 bool base_needs_rex() const {
290 return _base != noreg && _base->encoding() >= 8;
291 }
292
293 bool index_needs_rex() const {
294 return _index != noreg &&_index->encoding() >= 8;
295 }
296
297 relocInfo::relocType reloc() const { return _rspec.type(); }
298
299 friend class Assembler;
300 friend class MacroAssembler;
301 friend class LIR_Assembler; // base/index/scale/disp
302 };
303
304 //
305 // AddressLiteral has been split out from Address because operands of this type
306 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
307 // the few instructions that need to deal with address literals are unique and the
308 // MacroAssembler does not have to implement every instruction in the Assembler
309 // in order to search for address literals that may need special handling depending
310 // on the instruction and the platform. As small step on the way to merging i486/amd64
311 // directories.
312 //
313 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
314 friend class ArrayAddress;
315 RelocationHolder _rspec;
316 // Typically we use AddressLiterals we want to use their rval
317 // However in some situations we want the lval (effect address) of the item.
318 // We provide a special factory for making those lvals.
319 bool _is_lval;
320
321 // If the target is far we'll need to load the ea of this to
322 // a register to reach it. Otherwise if near we can do rip
323 // relative addressing.
324
325 address _target;
326
327 protected:
328 // creation
329 AddressLiteral()
330 : _is_lval(false),
331 _target(NULL)
332 {}
333
334 public:
335
336
337 AddressLiteral(address target, relocInfo::relocType rtype);
338
339 AddressLiteral(address target, RelocationHolder const& rspec)
340 : _rspec(rspec),
341 _is_lval(false),
342 _target(target)
343 {}
344
345 AddressLiteral addr() {
346 AddressLiteral ret = *this;
347 ret._is_lval = true;
348 return ret;
349 }
350
351
352 private:
353
354 address target() { return _target; }
355 bool is_lval() { return _is_lval; }
356
357 relocInfo::relocType reloc() const { return _rspec.type(); }
358 const RelocationHolder& rspec() const { return _rspec; }
359
360 friend class Assembler;
361 friend class MacroAssembler;
362 friend class Address;
363 friend class LIR_Assembler;
364 };
365
366 // Convience classes
367 class RuntimeAddress: public AddressLiteral {
368
369 public:
370
371 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
372
373 };
374
375 class OopAddress: public AddressLiteral {
376
377 public:
378
379 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
380
381 };
382
383 class ExternalAddress: public AddressLiteral {
384
385 public:
386
387 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
388
389 };
390
391 class InternalAddress: public AddressLiteral {
392
393 public:
394
395 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
396
397 };
398
399 // x86 can do array addressing as a single operation since disp can be an absolute
400 // address amd64 can't. We create a class that expresses the concept but does extra
401 // magic on amd64 to get the final result
402
403 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
404 private:
405
406 AddressLiteral _base;
407 Address _index;
408
409 public:
410
411 ArrayAddress() {};
412 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
413 AddressLiteral base() { return _base; }
414 Address index() { return _index; }
415
416 };
417
418 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
419
420 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
421 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
422 // is what you get. The Assembler is generating code into a CodeBuffer.
423
424 class Assembler : public AbstractAssembler {
425 friend class AbstractAssembler; // for the non-virtual hack
426 friend class LIR_Assembler; // as_Address()
427 friend class StubGenerator;
428
429 public:
430 enum Condition { // The x86 condition codes used for conditional jumps/moves.
431 zero = 0x4,
432 notZero = 0x5,
433 equal = 0x4,
434 notEqual = 0x5,
435 less = 0xc,
436 lessEqual = 0xe,
437 greater = 0xf,
438 greaterEqual = 0xd,
439 below = 0x2,
440 belowEqual = 0x6,
441 above = 0x7,
442 aboveEqual = 0x3,
443 overflow = 0x0,
444 noOverflow = 0x1,
445 carrySet = 0x2,
446 carryClear = 0x3,
447 negative = 0x8,
448 positive = 0x9,
449 parity = 0xa,
450 noParity = 0xb
451 };
452
453 enum Prefix {
454 // segment overrides
455 CS_segment = 0x2e,
456 SS_segment = 0x36,
457 DS_segment = 0x3e,
458 ES_segment = 0x26,
459 FS_segment = 0x64,
460 GS_segment = 0x65,
461
462 REX = 0x40,
463
464 REX_B = 0x41,
465 REX_X = 0x42,
466 REX_XB = 0x43,
467 REX_R = 0x44,
468 REX_RB = 0x45,
469 REX_RX = 0x46,
470 REX_RXB = 0x47,
471
472 REX_W = 0x48,
473
474 REX_WB = 0x49,
475 REX_WX = 0x4A,
476 REX_WXB = 0x4B,
477 REX_WR = 0x4C,
478 REX_WRB = 0x4D,
479 REX_WRX = 0x4E,
480 REX_WRXB = 0x4F
481 };
482
483 enum WhichOperand {
484 // input to locate_operand, and format code for relocations
485 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
486 disp32_operand = 1, // embedded 32-bit displacement or address
487 call32_operand = 2, // embedded 32-bit self-relative displacement
488 #ifndef _LP64
489 _WhichOperand_limit = 3
490 #else
491 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
492 _WhichOperand_limit = 4
493 #endif
494 };
495
496
497
498 // NOTE: The general philopsophy of the declarations here is that 64bit versions
499 // of instructions are freely declared without the need for wrapping them an ifdef.
500 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
501 // In the .cpp file the implementations are wrapped so that they are dropped out
502 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
503 // to the size it was prior to merging up the 32bit and 64bit assemblers.
504 //
505 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
506 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
507
508 private:
509
510
511 // 64bit prefixes
512 int prefix_and_encode(int reg_enc, bool byteinst = false);
513 int prefixq_and_encode(int reg_enc);
514
515 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
516 int prefixq_and_encode(int dst_enc, int src_enc);
517
518 void prefix(Register reg);
519 void prefix(Address adr);
520 void prefixq(Address adr);
521
522 void prefix(Address adr, Register reg, bool byteinst = false);
523 void prefixq(Address adr, Register reg);
524
525 void prefix(Address adr, XMMRegister reg);
526
527 void prefetch_prefix(Address src);
528
529 // Helper functions for groups of instructions
530 void emit_arith_b(int op1, int op2, Register dst, int imm8);
531
532 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
533 // only 32bit??
534 void emit_arith(int op1, int op2, Register dst, jobject obj);
535 void emit_arith(int op1, int op2, Register dst, Register src);
536
537 void emit_operand(Register reg,
538 Register base, Register index, Address::ScaleFactor scale,
539 int disp,
540 RelocationHolder const& rspec,
541 int rip_relative_correction = 0);
542
543 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
544
545 // operands that only take the original 32bit registers
546 void emit_operand32(Register reg, Address adr);
547
548 void emit_operand(XMMRegister reg,
549 Register base, Register index, Address::ScaleFactor scale,
550 int disp,
551 RelocationHolder const& rspec);
552
553 void emit_operand(XMMRegister reg, Address adr);
554
555 void emit_operand(MMXRegister reg, Address adr);
556
557 // workaround gcc (3.2.1-7) bug
558 void emit_operand(Address adr, MMXRegister reg);
559
560
561 // Immediate-to-memory forms
562 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
563
564 void emit_farith(int b1, int b2, int i);
565
566
567 protected:
568 #ifdef ASSERT
569 void check_relocation(RelocationHolder const& rspec, int format);
570 #endif
571
572 inline void emit_long64(jlong x);
573
574 void emit_data(jint data, relocInfo::relocType rtype, int format);
575 void emit_data(jint data, RelocationHolder const& rspec, int format);
576 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
577 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
578
579
580 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
581
582 // These are all easily abused and hence protected
583
584 // 32BIT ONLY SECTION
585 #ifndef _LP64
586 // Make these disappear in 64bit mode since they would never be correct
587 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
588 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
589
590 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
591 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
592
593 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
594 #else
595 // 64BIT ONLY SECTION
596 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
597
598 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
599 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
600
601 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
602 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
603 #endif // _LP64
604
605 // These are unique in that we are ensured by the caller that the 32bit
606 // relative in these instructions will always be able to reach the potentially
607 // 64bit address described by entry. Since they can take a 64bit address they
608 // don't have the 32 suffix like the other instructions in this class.
609
610 void call_literal(address entry, RelocationHolder const& rspec);
611 void jmp_literal(address entry, RelocationHolder const& rspec);
612
613 // Avoid using directly section
614 // Instructions in this section are actually usable by anyone without danger
615 // of failure but have performance issues that are addressed my enhanced
616 // instructions which will do the proper thing base on the particular cpu.
617 // We protect them because we don't trust you...
618
619 // Don't use next inc() and dec() methods directly. INC & DEC instructions
620 // could cause a partial flag stall since they don't set CF flag.
621 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
622 // which call inc() & dec() or add() & sub() in accordance with
623 // the product flag UseIncDec value.
624
625 void decl(Register dst);
626 void decl(Address dst);
627 void decq(Register dst);
628 void decq(Address dst);
629
630 void incl(Register dst);
631 void incl(Address dst);
632 void incq(Register dst);
633 void incq(Address dst);
634
635 // New cpus require use of movsd and movss to avoid partial register stall
636 // when loading from memory. But for old Opteron use movlpd instead of movsd.
637 // The selection is done in MacroAssembler::movdbl() and movflt().
638
639 // Move Scalar Single-Precision Floating-Point Values
640 void movss(XMMRegister dst, Address src);
641 void movss(XMMRegister dst, XMMRegister src);
642 void movss(Address dst, XMMRegister src);
643
644 // Move Scalar Double-Precision Floating-Point Values
645 void movsd(XMMRegister dst, Address src);
646 void movsd(XMMRegister dst, XMMRegister src);
647 void movsd(Address dst, XMMRegister src);
648 void movlpd(XMMRegister dst, Address src);
649
650 // New cpus require use of movaps and movapd to avoid partial register stall
651 // when moving between registers.
652 void movaps(XMMRegister dst, XMMRegister src);
653 void movapd(XMMRegister dst, XMMRegister src);
654
655 // End avoid using directly
656
657
658 // Instruction prefixes
659 void prefix(Prefix p);
660
661 public:
662
663 // Creation
664 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
665
666 // Decoding
667 static address locate_operand(address inst, WhichOperand which);
668 static address locate_next_instruction(address inst);
669
670 // Utilities
671
672 #ifdef _LP64
673 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
674 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
675 #else
676 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
677 static bool is_simm32(int32_t x) { return true; }
678 #endif // LP64
679
680 // Generic instructions
681 // Does 32bit or 64bit as needed for the platform. In some sense these
682 // belong in macro assembler but there is no need for both varieties to exist
683
684 void lea(Register dst, Address src);
685
686 void mov(Register dst, Register src);
687
688 void pusha();
689 void popa();
690
691 void pushf();
692 void popf();
693
694 void push(int32_t imm32);
695
696 void push(Register src);
697
698 void pop(Register dst);
699
700 // These are dummies to prevent surprise implicit conversions to Register
701 void push(void* v);
702 void pop(void* v);
703
704
705 // These do register sized moves/scans
706 void rep_mov();
707 void rep_set();
708 void repne_scan();
709 #ifdef _LP64
710 void repne_scanl();
711 #endif
712
713 // Vanilla instructions in lexical order
714
715 void adcl(Register dst, int32_t imm32);
716 void adcl(Register dst, Address src);
717 void adcl(Register dst, Register src);
718
719 void adcq(Register dst, int32_t imm32);
720 void adcq(Register dst, Address src);
721 void adcq(Register dst, Register src);
722
723
724 void addl(Address dst, int32_t imm32);
725 void addl(Address dst, Register src);
726 void addl(Register dst, int32_t imm32);
727 void addl(Register dst, Address src);
728 void addl(Register dst, Register src);
729
730 void addq(Address dst, int32_t imm32);
731 void addq(Address dst, Register src);
732 void addq(Register dst, int32_t imm32);
733 void addq(Register dst, Address src);
734 void addq(Register dst, Register src);
735
736
737 void addr_nop_4();
738 void addr_nop_5();
739 void addr_nop_7();
740 void addr_nop_8();
741
742 // Add Scalar Double-Precision Floating-Point Values
743 void addsd(XMMRegister dst, Address src);
744 void addsd(XMMRegister dst, XMMRegister src);
745
746 // Add Scalar Single-Precision Floating-Point Values
747 void addss(XMMRegister dst, Address src);
748 void addss(XMMRegister dst, XMMRegister src);
749
750 void andl(Register dst, int32_t imm32);
751 void andl(Register dst, Address src);
752 void andl(Register dst, Register src);
753
754 void andq(Register dst, int32_t imm32);
755 void andq(Register dst, Address src);
756 void andq(Register dst, Register src);
757
758
759 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
760 void andpd(XMMRegister dst, Address src);
761 void andpd(XMMRegister dst, XMMRegister src);
762
763 void bsfl(Register dst, Register src);
764 void bsrl(Register dst, Register src);
765
766 #ifdef _LP64
767 void bsfq(Register dst, Register src);
768 void bsrq(Register dst, Register src);
769 #endif
770
771 void bswapl(Register reg);
772
773 void bswapq(Register reg);
774
775 void call(Label& L, relocInfo::relocType rtype);
776 void call(Register reg); // push pc; pc <- reg
777 void call(Address adr); // push pc; pc <- adr
778
779 void cdql();
780
781 void cdqq();
782
783 void cld() { emit_byte(0xfc); }
784
785 void clflush(Address adr);
786
787 void cmovl(Condition cc, Register dst, Register src);
788 void cmovl(Condition cc, Register dst, Address src);
789
790 void cmovq(Condition cc, Register dst, Register src);
791 void cmovq(Condition cc, Register dst, Address src);
792
793
794 void cmpb(Address dst, int imm8);
795
796 void cmpl(Address dst, int32_t imm32);
797
798 void cmpl(Register dst, int32_t imm32);
799 void cmpl(Register dst, Register src);
800 void cmpl(Register dst, Address src);
801
802 void cmpq(Address dst, int32_t imm32);
803 void cmpq(Address dst, Register src);
804
805 void cmpq(Register dst, int32_t imm32);
806 void cmpq(Register dst, Register src);
807 void cmpq(Register dst, Address src);
808
809 // these are dummies used to catch attempting to convert NULL to Register
810 void cmpl(Register dst, void* junk); // dummy
811 void cmpq(Register dst, void* junk); // dummy
812
813 void cmpw(Address dst, int imm16);
814
815 void cmpxchg8 (Address adr);
816
817 void cmpxchgl(Register reg, Address adr);
818
819 void cmpxchgq(Register reg, Address adr);
820
821 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
822 void comisd(XMMRegister dst, Address src);
823
824 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
825 void comiss(XMMRegister dst, Address src);
826
827 // Identify processor type and features
828 void cpuid() {
829 emit_byte(0x0F);
830 emit_byte(0xA2);
831 }
832
833 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
834 void cvtsd2ss(XMMRegister dst, XMMRegister src);
835
836 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
837 void cvtsi2sdl(XMMRegister dst, Register src);
838 void cvtsi2sdq(XMMRegister dst, Register src);
839
840 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
841 void cvtsi2ssl(XMMRegister dst, Register src);
842 void cvtsi2ssq(XMMRegister dst, Register src);
843
844 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
845 void cvtdq2pd(XMMRegister dst, XMMRegister src);
846
847 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
848 void cvtdq2ps(XMMRegister dst, XMMRegister src);
849
850 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
851 void cvtss2sd(XMMRegister dst, XMMRegister src);
852
853 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
854 void cvttsd2sil(Register dst, Address src);
855 void cvttsd2sil(Register dst, XMMRegister src);
856 void cvttsd2siq(Register dst, XMMRegister src);
857
858 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
859 void cvttss2sil(Register dst, XMMRegister src);
860 void cvttss2siq(Register dst, XMMRegister src);
861
862 // Divide Scalar Double-Precision Floating-Point Values
863 void divsd(XMMRegister dst, Address src);
864 void divsd(XMMRegister dst, XMMRegister src);
865
866 // Divide Scalar Single-Precision Floating-Point Values
867 void divss(XMMRegister dst, Address src);
868 void divss(XMMRegister dst, XMMRegister src);
869
870 void emms();
871
872 void fabs();
873
874 void fadd(int i);
875
876 void fadd_d(Address src);
877 void fadd_s(Address src);
878
879 // "Alternate" versions of x87 instructions place result down in FPU
880 // stack instead of on TOS
881
882 void fadda(int i); // "alternate" fadd
883 void faddp(int i = 1);
884
885 void fchs();
886
887 void fcom(int i);
888
889 void fcomp(int i = 1);
890 void fcomp_d(Address src);
891 void fcomp_s(Address src);
892
893 void fcompp();
894
895 void fcos();
896
897 void fdecstp();
898
899 void fdiv(int i);
900 void fdiv_d(Address src);
901 void fdivr_s(Address src);
902 void fdiva(int i); // "alternate" fdiv
903 void fdivp(int i = 1);
904
905 void fdivr(int i);
906 void fdivr_d(Address src);
907 void fdiv_s(Address src);
908
909 void fdivra(int i); // "alternate" reversed fdiv
910
911 void fdivrp(int i = 1);
912
913 void ffree(int i = 0);
914
915 void fild_d(Address adr);
916 void fild_s(Address adr);
917
918 void fincstp();
919
920 void finit();
921
922 void fist_s (Address adr);
923 void fistp_d(Address adr);
924 void fistp_s(Address adr);
925
926 void fld1();
927
928 void fld_d(Address adr);
929 void fld_s(Address adr);
930 void fld_s(int index);
931 void fld_x(Address adr); // extended-precision (80-bit) format
932
933 void fldcw(Address src);
934
935 void fldenv(Address src);
936
937 void fldlg2();
938
939 void fldln2();
940
941 void fldz();
942
943 void flog();
944 void flog10();
945
946 void fmul(int i);
947
948 void fmul_d(Address src);
949 void fmul_s(Address src);
950
951 void fmula(int i); // "alternate" fmul
952
953 void fmulp(int i = 1);
954
955 void fnsave(Address dst);
956
957 void fnstcw(Address src);
958
959 void fnstsw_ax();
960
961 void fprem();
962 void fprem1();
963
964 void frstor(Address src);
965
966 void fsin();
967
968 void fsqrt();
969
970 void fst_d(Address adr);
971 void fst_s(Address adr);
972
973 void fstp_d(Address adr);
974 void fstp_d(int index);
975 void fstp_s(Address adr);
976 void fstp_x(Address adr); // extended-precision (80-bit) format
977
978 void fsub(int i);
979 void fsub_d(Address src);
980 void fsub_s(Address src);
981
982 void fsuba(int i); // "alternate" fsub
983
984 void fsubp(int i = 1);
985
986 void fsubr(int i);
987 void fsubr_d(Address src);
988 void fsubr_s(Address src);
989
990 void fsubra(int i); // "alternate" reversed fsub
991
992 void fsubrp(int i = 1);
993
994 void ftan();
995
996 void ftst();
997
998 void fucomi(int i = 1);
999 void fucomip(int i = 1);
1000
1001 void fwait();
1002
1003 void fxch(int i = 1);
1004
1005 void fxrstor(Address src);
1006
1007 void fxsave(Address dst);
1008
1009 void fyl2x();
1010
1011 void hlt();
1012
1013 void idivl(Register src);
1014
1015 void idivq(Register src);
1016
1017 void imull(Register dst, Register src);
1018 void imull(Register dst, Register src, int value);
1019
1020 void imulq(Register dst, Register src);
1021 void imulq(Register dst, Register src, int value);
1022
1023
1024 // jcc is the generic conditional branch generator to run-
1025 // time routines, jcc is used for branches to labels. jcc
1026 // takes a branch opcode (cc) and a label (L) and generates
1027 // either a backward branch or a forward branch and links it
1028 // to the label fixup chain. Usage:
1029 //
1030 // Label L; // unbound label
1031 // jcc(cc, L); // forward branch to unbound label
1032 // bind(L); // bind label to the current pc
1033 // jcc(cc, L); // backward branch to bound label
1034 // bind(L); // illegal: a label may be bound only once
1035 //
1036 // Note: The same Label can be used for forward and backward branches
1037 // but it may be bound only once.
1038
1039 void jcc(Condition cc, Label& L,
1040 relocInfo::relocType rtype = relocInfo::none);
1041
1042 // Conditional jump to a 8-bit offset to L.
1043 // WARNING: be very careful using this for forward jumps. If the label is
1044 // not bound within an 8-bit offset of this instruction, a run-time error
1045 // will occur.
1046 void jccb(Condition cc, Label& L);
1047
1048 void jmp(Address entry); // pc <- entry
1049
1050 // Label operations & relative jumps (PPUM Appendix D)
1051 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1052
1053 void jmp(Register entry); // pc <- entry
1054
1055 // Unconditional 8-bit offset jump to L.
1056 // WARNING: be very careful using this for forward jumps. If the label is
1057 // not bound within an 8-bit offset of this instruction, a run-time error
1058 // will occur.
1059 void jmpb(Label& L);
1060
1061 void ldmxcsr( Address src );
1062
1063 void leal(Register dst, Address src);
1064
1065 void leaq(Register dst, Address src);
1066
1067 void lfence() {
1068 emit_byte(0x0F);
1069 emit_byte(0xAE);
1070 emit_byte(0xE8);
1071 }
1072
1073 void lock();
1074
1075 void lzcntl(Register dst, Register src);
1076
1077 #ifdef _LP64
1078 void lzcntq(Register dst, Register src);
1079 #endif
1080
1081 enum Membar_mask_bits {
1082 StoreStore = 1 << 3,
1083 LoadStore = 1 << 2,
1084 StoreLoad = 1 << 1,
1085 LoadLoad = 1 << 0
1086 };
1087
1088 // Serializes memory and blows flags
1089 void membar(Membar_mask_bits order_constraint) {
1090 if (os::is_MP()) {
1091 // We only have to handle StoreLoad
1092 if (order_constraint & StoreLoad) {
1093 // All usable chips support "locked" instructions which suffice
1094 // as barriers, and are much faster than the alternative of
1095 // using cpuid instruction. We use here a locked add [esp],0.
1096 // This is conveniently otherwise a no-op except for blowing
1097 // flags.
1098 // Any change to this code may need to revisit other places in
1099 // the code where this idiom is used, in particular the
1100 // orderAccess code.
1101 lock();
1102 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1103 }
1104 }
1105 }
1106
1107 void mfence();
1108
1109 // Moves
1110
1111 void mov64(Register dst, int64_t imm64);
1112
1113 void movb(Address dst, Register src);
1114 void movb(Address dst, int imm8);
1115 void movb(Register dst, Address src);
1116
1117 void movdl(XMMRegister dst, Register src);
1118 void movdl(Register dst, XMMRegister src);
1119
1120 // Move Double Quadword
1121 void movdq(XMMRegister dst, Register src);
1122 void movdq(Register dst, XMMRegister src);
1123
1124 // Move Aligned Double Quadword
1125 void movdqa(Address dst, XMMRegister src);
1126 void movdqa(XMMRegister dst, Address src);
1127 void movdqa(XMMRegister dst, XMMRegister src);
1128
1129 // Move Unaligned Double Quadword
1130 void movdqu(Address dst, XMMRegister src);
1131 void movdqu(XMMRegister dst, Address src);
1132 void movdqu(XMMRegister dst, XMMRegister src);
1133
1134 void movl(Register dst, int32_t imm32);
1135 void movl(Address dst, int32_t imm32);
1136 void movl(Register dst, Register src);
1137 void movl(Register dst, Address src);
1138 void movl(Address dst, Register src);
1139
1140 // These dummies prevent using movl from converting a zero (like NULL) into Register
1141 // by giving the compiler two choices it can't resolve
1142
1143 void movl(Address dst, void* junk);
1144 void movl(Register dst, void* junk);
1145
1146 #ifdef _LP64
1147 void movq(Register dst, Register src);
1148 void movq(Register dst, Address src);
1149 void movq(Address dst, Register src);
1150 #endif
1151
1152 void movq(Address dst, MMXRegister src );
1153 void movq(MMXRegister dst, Address src );
1154
1155 #ifdef _LP64
1156 // These dummies prevent using movq from converting a zero (like NULL) into Register
1157 // by giving the compiler two choices it can't resolve
1158
1159 void movq(Address dst, void* dummy);
1160 void movq(Register dst, void* dummy);
1161 #endif
1162
1163 // Move Quadword
1164 void movq(Address dst, XMMRegister src);
1165 void movq(XMMRegister dst, Address src);
1166
1167 void movsbl(Register dst, Address src);
1168 void movsbl(Register dst, Register src);
1169
1170 #ifdef _LP64
1171 void movsbq(Register dst, Address src);
1172 void movsbq(Register dst, Register src);
1173
1174 // Move signed 32bit immediate to 64bit extending sign
1175 void movslq(Address dst, int32_t imm64);
1176 void movslq(Register dst, int32_t imm64);
1177
1178 void movslq(Register dst, Address src);
1179 void movslq(Register dst, Register src);
1180 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1181 #endif
1182
1183 void movswl(Register dst, Address src);
1184 void movswl(Register dst, Register src);
1185
1186 #ifdef _LP64
1187 void movswq(Register dst, Address src);
1188 void movswq(Register dst, Register src);
1189 #endif
1190
1191 void movw(Address dst, int imm16);
1192 void movw(Register dst, Address src);
1193 void movw(Address dst, Register src);
1194
1195 void movzbl(Register dst, Address src);
1196 void movzbl(Register dst, Register src);
1197
1198 #ifdef _LP64
1199 void movzbq(Register dst, Address src);
1200 void movzbq(Register dst, Register src);
1201 #endif
1202
1203 void movzwl(Register dst, Address src);
1204 void movzwl(Register dst, Register src);
1205
1206 #ifdef _LP64
1207 void movzwq(Register dst, Address src);
1208 void movzwq(Register dst, Register src);
1209 #endif
1210
1211 void mull(Address src);
1212 void mull(Register src);
1213
1214 // Multiply Scalar Double-Precision Floating-Point Values
1215 void mulsd(XMMRegister dst, Address src);
1216 void mulsd(XMMRegister dst, XMMRegister src);
1217
1218 // Multiply Scalar Single-Precision Floating-Point Values
1219 void mulss(XMMRegister dst, Address src);
1220 void mulss(XMMRegister dst, XMMRegister src);
1221
1222 void negl(Register dst);
1223
1224 #ifdef _LP64
1225 void negq(Register dst);
1226 #endif
1227
1228 void nop(int i = 1);
1229
1230 void notl(Register dst);
1231
1232 #ifdef _LP64
1233 void notq(Register dst);
1234 #endif
1235
1236 void orl(Address dst, int32_t imm32);
1237 void orl(Register dst, int32_t imm32);
1238 void orl(Register dst, Address src);
1239 void orl(Register dst, Register src);
1240
1241 void orq(Address dst, int32_t imm32);
1242 void orq(Register dst, int32_t imm32);
1243 void orq(Register dst, Address src);
1244 void orq(Register dst, Register src);
1245
1246 // SSE4.2 string instructions
1247 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1248 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1249
1250 #ifndef _LP64 // no 32bit push/pop on amd64
1251 void popl(Address dst);
1252 #endif
1253
1254 #ifdef _LP64
1255 void popq(Address dst);
1256 #endif
1257
1258 void popcntl(Register dst, Address src);
1259 void popcntl(Register dst, Register src);
1260
1261 #ifdef _LP64
1262 void popcntq(Register dst, Address src);
1263 void popcntq(Register dst, Register src);
1264 #endif
1265
1266 // Prefetches (SSE, SSE2, 3DNOW only)
1267
1268 void prefetchnta(Address src);
1269 void prefetchr(Address src);
1270 void prefetcht0(Address src);
1271 void prefetcht1(Address src);
1272 void prefetcht2(Address src);
1273 void prefetchw(Address src);
1274
1275 // Shuffle Packed Doublewords
1276 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1277 void pshufd(XMMRegister dst, Address src, int mode);
1278
1279 // Shuffle Packed Low Words
1280 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1281 void pshuflw(XMMRegister dst, Address src, int mode);
1282
1283 // Shift Right Logical Quadword Immediate
1284 void psrlq(XMMRegister dst, int shift);
1285
1286 // Logical Compare Double Quadword
1287 void ptest(XMMRegister dst, XMMRegister src);
1288 void ptest(XMMRegister dst, Address src);
1289
1290 // Interleave Low Bytes
1291 void punpcklbw(XMMRegister dst, XMMRegister src);
1292
1293 #ifndef _LP64 // no 32bit push/pop on amd64
1294 void pushl(Address src);
1295 #endif
1296
1297 void pushq(Address src);
1298
1299 // Xor Packed Byte Integer Values
1300 void pxor(XMMRegister dst, Address src);
1301 void pxor(XMMRegister dst, XMMRegister src);
1302
1303 void rcll(Register dst, int imm8);
1304
1305 void rclq(Register dst, int imm8);
1306
1307 void ret(int imm16);
1308
1309 void sahf();
1310
1311 void sarl(Register dst, int imm8);
1312 void sarl(Register dst);
1313
1314 void sarq(Register dst, int imm8);
1315 void sarq(Register dst);
1316
1317 void sbbl(Address dst, int32_t imm32);
1318 void sbbl(Register dst, int32_t imm32);
1319 void sbbl(Register dst, Address src);
1320 void sbbl(Register dst, Register src);
1321
1322 void sbbq(Address dst, int32_t imm32);
1323 void sbbq(Register dst, int32_t imm32);
1324 void sbbq(Register dst, Address src);
1325 void sbbq(Register dst, Register src);
1326
1327 void setb(Condition cc, Register dst);
1328
1329 void shldl(Register dst, Register src);
1330
1331 void shll(Register dst, int imm8);
1332 void shll(Register dst);
1333
1334 void shlq(Register dst, int imm8);
1335 void shlq(Register dst);
1336
1337 void shrdl(Register dst, Register src);
1338
1339 void shrl(Register dst, int imm8);
1340 void shrl(Register dst);
1341
1342 void shrq(Register dst, int imm8);
1343 void shrq(Register dst);
1344
1345 void smovl(); // QQQ generic?
1346
1347 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1348 void sqrtsd(XMMRegister dst, Address src);
1349 void sqrtsd(XMMRegister dst, XMMRegister src);
1350
1351 void std() { emit_byte(0xfd); }
1352
1353 void stmxcsr( Address dst );
1354
1355 void subl(Address dst, int32_t imm32);
1356 void subl(Address dst, Register src);
1357 void subl(Register dst, int32_t imm32);
1358 void subl(Register dst, Address src);
1359 void subl(Register dst, Register src);
1360
1361 void subq(Address dst, int32_t imm32);
1362 void subq(Address dst, Register src);
1363 void subq(Register dst, int32_t imm32);
1364 void subq(Register dst, Address src);
1365 void subq(Register dst, Register src);
1366
1367
1368 // Subtract Scalar Double-Precision Floating-Point Values
1369 void subsd(XMMRegister dst, Address src);
1370 void subsd(XMMRegister dst, XMMRegister src);
1371
1372 // Subtract Scalar Single-Precision Floating-Point Values
1373 void subss(XMMRegister dst, Address src);
1374 void subss(XMMRegister dst, XMMRegister src);
1375
1376 void testb(Register dst, int imm8);
1377
1378 void testl(Register dst, int32_t imm32);
1379 void testl(Register dst, Register src);
1380 void testl(Register dst, Address src);
1381
1382 void testq(Register dst, int32_t imm32);
1383 void testq(Register dst, Register src);
1384
1385
1386 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1387 void ucomisd(XMMRegister dst, Address src);
1388 void ucomisd(XMMRegister dst, XMMRegister src);
1389
1390 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1391 void ucomiss(XMMRegister dst, Address src);
1392 void ucomiss(XMMRegister dst, XMMRegister src);
1393
1394 void xaddl(Address dst, Register src);
1395
1396 void xaddq(Address dst, Register src);
1397
1398 void xchgl(Register reg, Address adr);
1399 void xchgl(Register dst, Register src);
1400
1401 void xchgq(Register reg, Address adr);
1402 void xchgq(Register dst, Register src);
1403
1404 void xorl(Register dst, int32_t imm32);
1405 void xorl(Register dst, Address src);
1406 void xorl(Register dst, Register src);
1407
1408 void xorq(Register dst, Address src);
1409 void xorq(Register dst, Register src);
1410
1411 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1412 void xorpd(XMMRegister dst, Address src);
1413 void xorpd(XMMRegister dst, XMMRegister src);
1414
1415 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1416 void xorps(XMMRegister dst, Address src);
1417 void xorps(XMMRegister dst, XMMRegister src);
1418
1419 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1420 };
1421
1422
1423 // MacroAssembler extends Assembler by frequently used macros.
1424 //
1425 // Instructions for which a 'better' code sequence exists depending
1426 // on arguments should also go in here.
1427
1428 class MacroAssembler: public Assembler {
1429 friend class LIR_Assembler;
1430 friend class Runtime1; // as_Address()
1431 protected:
1432
1433 Address as_Address(AddressLiteral adr);
1434 Address as_Address(ArrayAddress adr);
1435
1436 // Support for VM calls
1437 //
1438 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1439 // may customize this version by overriding it for its purposes (e.g., to save/restore
1440 // additional registers when doing a VM call).
1441 #ifdef CC_INTERP
1442 // c++ interpreter never wants to use interp_masm version of call_VM
1443 #define VIRTUAL
1444 #else
1445 #define VIRTUAL virtual
1446 #endif
1447
1448 VIRTUAL void call_VM_leaf_base(
1449 address entry_point, // the entry point
1450 int number_of_arguments // the number of arguments to pop after the call
1451 );
1452
1453 // This is the base routine called by the different versions of call_VM. The interpreter
1454 // may customize this version by overriding it for its purposes (e.g., to save/restore
1455 // additional registers when doing a VM call).
1456 //
1457 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1458 // returns the register which contains the thread upon return. If a thread register has been
1459 // specified, the return value will correspond to that register. If no last_java_sp is specified
1460 // (noreg) than rsp will be used instead.
1461 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1462 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1463 Register java_thread, // the thread if computed before ; use noreg otherwise
1464 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1465 address entry_point, // the entry point
1466 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1467 bool check_exceptions // whether to check for pending exceptions after return
1468 );
1469
1470 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1471 // The implementation is only non-empty for the InterpreterMacroAssembler,
1472 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1473 virtual void check_and_handle_popframe(Register java_thread);
1474 virtual void check_and_handle_earlyret(Register java_thread);
1475
1476 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1477
1478 // helpers for FPU flag access
1479 // tmp is a temporary register, if none is available use noreg
1480 void save_rax (Register tmp);
1481 void restore_rax(Register tmp);
1482
1483 public:
1484 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1485
1486 // Support for NULL-checks
1487 //
1488 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1489 // If the accessed location is M[reg + offset] and the offset is known, provide the
1490 // offset. No explicit code generation is needed if the offset is within a certain
1491 // range (0 <= offset <= page_size).
1492
1493 void null_check(Register reg, int offset = -1);
1494 static bool needs_explicit_null_check(intptr_t offset);
1495
1496 // Required platform-specific helpers for Label::patch_instructions.
1497 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1498 void pd_patch_instruction(address branch, address target);
1499 #ifndef PRODUCT
1500 static void pd_print_patched_instruction(address branch);
1501 #endif
1502
1503 // The following 4 methods return the offset of the appropriate move instruction
1504
1505 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1506 int load_unsigned_byte(Register dst, Address src);
1507 int load_unsigned_short(Register dst, Address src);
1508
1509 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1510 int load_signed_byte(Register dst, Address src);
1511 int load_signed_short(Register dst, Address src);
1512
1513 // Support for sign-extension (hi:lo = extend_sign(lo))
1514 void extend_sign(Register hi, Register lo);
1515
1516 // Loading values by size and signed-ness
1517 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
1518
1519 // Support for inc/dec with optimal instruction selection depending on value
1520
1521 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1522 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1523
1524 void decrementl(Address dst, int value = 1);
1525 void decrementl(Register reg, int value = 1);
1526
1527 void decrementq(Register reg, int value = 1);
1528 void decrementq(Address dst, int value = 1);
1529
1530 void incrementl(Address dst, int value = 1);
1531 void incrementl(Register reg, int value = 1);
1532
1533 void incrementq(Register reg, int value = 1);
1534 void incrementq(Address dst, int value = 1);
1535
1536
1537 // Support optimal SSE move instructions.
1538 void movflt(XMMRegister dst, XMMRegister src) {
1539 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1540 else { movss (dst, src); return; }
1541 }
1542 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1543 void movflt(XMMRegister dst, AddressLiteral src);
1544 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1545
1546 void movdbl(XMMRegister dst, XMMRegister src) {
1547 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1548 else { movsd (dst, src); return; }
1549 }
1550
1551 void movdbl(XMMRegister dst, AddressLiteral src);
1552
1553 void movdbl(XMMRegister dst, Address src) {
1554 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1555 else { movlpd(dst, src); return; }
1556 }
1557 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1558
1559 void incrementl(AddressLiteral dst);
1560 void incrementl(ArrayAddress dst);
1561
1562 // Alignment
1563 void align(int modulus);
1564
1565 // Misc
1566 void fat_nop(); // 5 byte nop
1567
1568 // Stack frame creation/removal
1569 void enter();
1570 void leave();
1571
1572 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1573 // The pointer will be loaded into the thread register.
1574 void get_thread(Register thread);
1575
1576
1577 // Support for VM calls
1578 //
1579 // It is imperative that all calls into the VM are handled via the call_VM macros.
1580 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1581 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1582
1583
1584 void call_VM(Register oop_result,
1585 address entry_point,
1586 bool check_exceptions = true);
1587 void call_VM(Register oop_result,
1588 address entry_point,
1589 Register arg_1,
1590 bool check_exceptions = true);
1591 void call_VM(Register oop_result,
1592 address entry_point,
1593 Register arg_1, Register arg_2,
1594 bool check_exceptions = true);
1595 void call_VM(Register oop_result,
1596 address entry_point,
1597 Register arg_1, Register arg_2, Register arg_3,
1598 bool check_exceptions = true);
1599
1600 // Overloadings with last_Java_sp
1601 void call_VM(Register oop_result,
1602 Register last_java_sp,
1603 address entry_point,
1604 int number_of_arguments = 0,
1605 bool check_exceptions = true);
1606 void call_VM(Register oop_result,
1607 Register last_java_sp,
1608 address entry_point,
1609 Register arg_1, bool
1610 check_exceptions = true);
1611 void call_VM(Register oop_result,
1612 Register last_java_sp,
1613 address entry_point,
1614 Register arg_1, Register arg_2,
1615 bool check_exceptions = true);
1616 void call_VM(Register oop_result,
1617 Register last_java_sp,
1618 address entry_point,
1619 Register arg_1, Register arg_2, Register arg_3,
1620 bool check_exceptions = true);
1621
1622 void call_VM_leaf(address entry_point,
1623 int number_of_arguments = 0);
1624 void call_VM_leaf(address entry_point,
1625 Register arg_1);
1626 void call_VM_leaf(address entry_point,
1627 Register arg_1, Register arg_2);
1628 void call_VM_leaf(address entry_point,
1629 Register arg_1, Register arg_2, Register arg_3);
1630
1631 // last Java Frame (fills frame anchor)
1632 void set_last_Java_frame(Register thread,
1633 Register last_java_sp,
1634 Register last_java_fp,
1635 address last_java_pc);
1636
1637 // thread in the default location (r15_thread on 64bit)
1638 void set_last_Java_frame(Register last_java_sp,
1639 Register last_java_fp,
1640 address last_java_pc);
1641
1642 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1643
1644 // thread in the default location (r15_thread on 64bit)
1645 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1646
1647 // Stores
1648 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1649 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1650
1651 void g1_write_barrier_pre(Register obj,
1652 #ifndef _LP64
1653 Register thread,
1654 #endif
1655 Register tmp,
1656 Register tmp2,
1657 bool tosca_live);
1658 void g1_write_barrier_post(Register store_addr,
1659 Register new_val,
1660 #ifndef _LP64
1661 Register thread,
1662 #endif
1663 Register tmp,
1664 Register tmp2);
1665
1666
1667 // split store_check(Register obj) to enhance instruction interleaving
1668 void store_check_part_1(Register obj);
1669 void store_check_part_2(Register obj);
1670
1671 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1672 void c2bool(Register x);
1673
1674 // C++ bool manipulation
1675
1676 void movbool(Register dst, Address src);
1677 void movbool(Address dst, bool boolconst);
1678 void movbool(Address dst, Register src);
1679 void testbool(Register dst);
1680
1681 // oop manipulations
1682 void load_klass(Register dst, Register src);
1683 void store_klass(Register dst, Register src);
1684
1685 void load_heap_oop(Register dst, Address src);
1686 void store_heap_oop(Address dst, Register src);
1687
1688 // Used for storing NULL. All other oop constants should be
1689 // stored using routines that take a jobject.
1690 void store_heap_oop_null(Address dst);
1691
1692 void load_prototype_header(Register dst, Register src);
1693
1694 #ifdef _LP64
1695 void store_klass_gap(Register dst, Register src);
1696
1697 // This dummy is to prevent a call to store_heap_oop from
1698 // converting a zero (like NULL) into a Register by giving
1699 // the compiler two choices it can't resolve
1700
1701 void store_heap_oop(Address dst, void* dummy);
1702
1703 void encode_heap_oop(Register r);
1704 void decode_heap_oop(Register r);
1705 void encode_heap_oop_not_null(Register r);
1706 void decode_heap_oop_not_null(Register r);
1707 void encode_heap_oop_not_null(Register dst, Register src);
1708 void decode_heap_oop_not_null(Register dst, Register src);
1709
1710 void set_narrow_oop(Register dst, jobject obj);
1711 void set_narrow_oop(Address dst, jobject obj);
1712 void cmp_narrow_oop(Register dst, jobject obj);
1713 void cmp_narrow_oop(Address dst, jobject obj);
1714
1715 // if heap base register is used - reinit it with the correct value
1716 void reinit_heapbase();
1717
1718 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1719
1720 #endif // _LP64
1721
1722 // Int division/remainder for Java
1723 // (as idivl, but checks for special case as described in JVM spec.)
1724 // returns idivl instruction offset for implicit exception handling
1725 int corrected_idivl(Register reg);
1726
1727 // Long division/remainder for Java
1728 // (as idivq, but checks for special case as described in JVM spec.)
1729 // returns idivq instruction offset for implicit exception handling
1730 int corrected_idivq(Register reg);
1731
1732 void int3();
1733
1734 // Long operation macros for a 32bit cpu
1735 // Long negation for Java
1736 void lneg(Register hi, Register lo);
1737
1738 // Long multiplication for Java
1739 // (destroys contents of eax, ebx, ecx and edx)
1740 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1741
1742 // Long shifts for Java
1743 // (semantics as described in JVM spec.)
1744 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1745 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1746
1747 // Long compare for Java
1748 // (semantics as described in JVM spec.)
1749 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1750
1751
1752 // misc
1753
1754 // Sign extension
1755 void sign_extend_short(Register reg);
1756 void sign_extend_byte(Register reg);
1757
1758 // Division by power of 2, rounding towards 0
1759 void division_with_shift(Register reg, int shift_value);
1760
1761 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1762 //
1763 // CF (corresponds to C0) if x < y
1764 // PF (corresponds to C2) if unordered
1765 // ZF (corresponds to C3) if x = y
1766 //
1767 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1768 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1769 void fcmp(Register tmp);
1770 // Variant of the above which allows y to be further down the stack
1771 // and which only pops x and y if specified. If pop_right is
1772 // specified then pop_left must also be specified.
1773 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1774
1775 // Floating-point comparison for Java
1776 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1777 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1778 // (semantics as described in JVM spec.)
1779 void fcmp2int(Register dst, bool unordered_is_less);
1780 // Variant of the above which allows y to be further down the stack
1781 // and which only pops x and y if specified. If pop_right is
1782 // specified then pop_left must also be specified.
1783 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1784
1785 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1786 // tmp is a temporary register, if none is available use noreg
1787 void fremr(Register tmp);
1788
1789
1790 // same as fcmp2int, but using SSE2
1791 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1792 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1793
1794 // Inlined sin/cos generator for Java; must not use CPU instruction
1795 // directly on Intel as it does not have high enough precision
1796 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1797 // number of FPU stack slots in use; all but the topmost will
1798 // require saving if a slow case is necessary. Assumes argument is
1799 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1800 // this code.
1801 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1802
1803 // branch to L if FPU flag C2 is set/not set
1804 // tmp is a temporary register, if none is available use noreg
1805 void jC2 (Register tmp, Label& L);
1806 void jnC2(Register tmp, Label& L);
1807
1808 // Pop ST (ffree & fincstp combined)
1809 void fpop();
1810
1811 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1812 void push_fTOS();
1813
1814 // pops double TOS element from CPU stack and pushes on FPU stack
1815 void pop_fTOS();
1816
1817 void empty_FPU_stack();
1818
1819 void push_IU_state();
1820 void pop_IU_state();
1821
1822 void push_FPU_state();
1823 void pop_FPU_state();
1824
1825 void push_CPU_state();
1826 void pop_CPU_state();
1827
1828 // Round up to a power of two
1829 void round_to(Register reg, int modulus);
1830
1831 // Callee saved registers handling
1832 void push_callee_saved_registers();
1833 void pop_callee_saved_registers();
1834
1835 // allocation
1836 void eden_allocate(
1837 Register obj, // result: pointer to object after successful allocation
1838 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1839 int con_size_in_bytes, // object size in bytes if known at compile time
1840 Register t1, // temp register
1841 Label& slow_case // continuation point if fast allocation fails
1842 );
1843 void tlab_allocate(
1844 Register obj, // result: pointer to object after successful allocation
1845 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1846 int con_size_in_bytes, // object size in bytes if known at compile time
1847 Register t1, // temp register
1848 Register t2, // temp register
1849 Label& slow_case // continuation point if fast allocation fails
1850 );
1851 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1852
1853 // interface method calling
1854 void lookup_interface_method(Register recv_klass,
1855 Register intf_klass,
1856 RegisterOrConstant itable_index,
1857 Register method_result,
1858 Register scan_temp,
1859 Label& no_such_interface);
1860
1861 // Test sub_klass against super_klass, with fast and slow paths.
1862
1863 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1864 // One of the three labels can be NULL, meaning take the fall-through.
1865 // If super_check_offset is -1, the value is loaded up from super_klass.
1866 // No registers are killed, except temp_reg.
1867 void check_klass_subtype_fast_path(Register sub_klass,
1868 Register super_klass,
1869 Register temp_reg,
1870 Label* L_success,
1871 Label* L_failure,
1872 Label* L_slow_path,
1873 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1874
1875 // The rest of the type check; must be wired to a corresponding fast path.
1876 // It does not repeat the fast path logic, so don't use it standalone.
1877 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1878 // Updates the sub's secondary super cache as necessary.
1879 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1880 void check_klass_subtype_slow_path(Register sub_klass,
1881 Register super_klass,
1882 Register temp_reg,
1883 Register temp2_reg,
1884 Label* L_success,
1885 Label* L_failure,
1886 bool set_cond_codes = false);
1887
1888 // Simplified, combined version, good for typical uses.
1889 // Falls through on failure.
1890 void check_klass_subtype(Register sub_klass,
1891 Register super_klass,
1892 Register temp_reg,
1893 Label& L_success);
1894
1895 // method handles (JSR 292)
1896 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1897 Register temp_reg,
1898 Label& wrong_method_type);
1899 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1900 Register temp_reg);
1901 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1902 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1903
1904
1905 //----
1906 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1907
1908 // Debugging
1909
1910 // only if +VerifyOops
1911 void verify_oop(Register reg, const char* s = "broken oop");
1912 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1913
1914 // only if +VerifyFPU
1915 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1916
1917 // prints msg, dumps registers and stops execution
1918 void stop(const char* msg);
1919
1920 // prints msg and continues
1921 void warn(const char* msg);
1922
1923 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1924 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1925
1926 void os_breakpoint();
1927
1928 void untested() { stop("untested"); }
1929
1930 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1931
1932 void should_not_reach_here() { stop("should not reach here"); }
1933
1934 void print_CPU_state();
1935
1936 // Stack overflow checking
1937 void bang_stack_with_offset(int offset) {
1938 // stack grows down, caller passes positive offset
1939 assert(offset > 0, "must bang with negative offset");
1940 movl(Address(rsp, (-offset)), rax);
1941 }
1942
1943 // Writes to stack successive pages until offset reached to check for
1944 // stack overflow + shadow pages. Also, clobbers tmp
1945 void bang_stack_size(Register size, Register tmp);
1946
1947 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1948 Register tmp,
1949 int offset);
1950
1951 // Support for serializing memory accesses between threads
1952 void serialize_memory(Register thread, Register tmp);
1953
1954 void verify_tlab();
1955
1956 // Biased locking support
1957 // lock_reg and obj_reg must be loaded up with the appropriate values.
1958 // swap_reg must be rax, and is killed.
1959 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1960 // be killed; if not supplied, push/pop will be used internally to
1961 // allocate a temporary (inefficient, avoid if possible).
1962 // Optional slow case is for implementations (interpreter and C1) which branch to
1963 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1964 // Returns offset of first potentially-faulting instruction for null
1965 // check info (currently consumed only by C1). If
1966 // swap_reg_contains_mark is true then returns -1 as it is assumed
1967 // the calling code has already passed any potential faults.
1968 int biased_locking_enter(Register lock_reg, Register obj_reg,
1969 Register swap_reg, Register tmp_reg,
1970 bool swap_reg_contains_mark,
1971 Label& done, Label* slow_case = NULL,
1972 BiasedLockingCounters* counters = NULL);
1973 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1974
1975
1976 Condition negate_condition(Condition cond);
1977
1978 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1979 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1980 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1981 // here in MacroAssembler. The major exception to this rule is call
1982
1983 // Arithmetics
1984
1985
1986 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1987 void addptr(Address dst, Register src);
1988
1989 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1990 void addptr(Register dst, int32_t src);
1991 void addptr(Register dst, Register src);
1992
1993 void andptr(Register dst, int32_t src);
1994 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1995
1996 void cmp8(AddressLiteral src1, int imm);
1997
1998 // renamed to drag out the casting of address to int32_t/intptr_t
1999 void cmp32(Register src1, int32_t imm);
2000
2001 void cmp32(AddressLiteral src1, int32_t imm);
2002 // compare reg - mem, or reg - &mem
2003 void cmp32(Register src1, AddressLiteral src2);
2004
2005 void cmp32(Register src1, Address src2);
2006
2007 #ifndef _LP64
2008 void cmpoop(Address dst, jobject obj);
2009 void cmpoop(Register dst, jobject obj);
2010 #endif // _LP64
2011
2012 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2013 void cmpptr(Address src1, AddressLiteral src2);
2014
2015 void cmpptr(Register src1, AddressLiteral src2);
2016
2017 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2018 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2019 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2020
2021 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2022 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2023
2024 // cmp64 to avoild hiding cmpq
2025 void cmp64(Register src1, AddressLiteral src);
2026
2027 void cmpxchgptr(Register reg, Address adr);
2028
2029 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2030
2031
2032 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2033
2034
2035 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2036
2037 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2038
2039 void shlptr(Register dst, int32_t shift);
2040 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2041
2042 void shrptr(Register dst, int32_t shift);
2043 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2044
2045 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2046 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2047
2048 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2049
2050 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2051 void subptr(Register dst, int32_t src);
2052 void subptr(Register dst, Register src);
2053
2054
2055 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2056 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2057
2058 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2059 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2060
2061 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2062
2063
2064
2065 // Helper functions for statistics gathering.
2066 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2067 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2068 // Unconditional atomic increment.
2069 void atomic_incl(AddressLiteral counter_addr);
2070
2071 void lea(Register dst, AddressLiteral adr);
2072 void lea(Address dst, AddressLiteral adr);
2073 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2074
2075 void leal32(Register dst, Address src) { leal(dst, src); }
2076
2077 void test32(Register src1, AddressLiteral src2);
2078
2079 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2080 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2081 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2082
2083 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2084 void testptr(Register src1, Register src2);
2085
2086 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2087 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2088
2089 // Calls
2090
2091 void call(Label& L, relocInfo::relocType rtype);
2092 void call(Register entry);
2093
2094 // NOTE: this call tranfers to the effective address of entry NOT
2095 // the address contained by entry. This is because this is more natural
2096 // for jumps/calls.
2097 void call(AddressLiteral entry);
2098
2099 // Jumps
2100
2101 // NOTE: these jumps tranfer to the effective address of dst NOT
2102 // the address contained by dst. This is because this is more natural
2103 // for jumps/calls.
2104 void jump(AddressLiteral dst);
2105 void jump_cc(Condition cc, AddressLiteral dst);
2106
2107 // 32bit can do a case table jump in one instruction but we no longer allow the base
2108 // to be installed in the Address class. This jump will tranfers to the address
2109 // contained in the location described by entry (not the address of entry)
2110 void jump(ArrayAddress entry);
2111
2112 // Floating
2113
2114 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2115 void andpd(XMMRegister dst, AddressLiteral src);
2116
2117 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2118 void comiss(XMMRegister dst, AddressLiteral src);
2119
2120 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2121 void comisd(XMMRegister dst, AddressLiteral src);
2122
2123 void fldcw(Address src) { Assembler::fldcw(src); }
2124 void fldcw(AddressLiteral src);
2125
2126 void fld_s(int index) { Assembler::fld_s(index); }
2127 void fld_s(Address src) { Assembler::fld_s(src); }
2128 void fld_s(AddressLiteral src);
2129
2130 void fld_d(Address src) { Assembler::fld_d(src); }
2131 void fld_d(AddressLiteral src);
2132
2133 void fld_x(Address src) { Assembler::fld_x(src); }
2134 void fld_x(AddressLiteral src);
2135
2136 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2137 void ldmxcsr(AddressLiteral src);
2138
2139 private:
2140 // these are private because users should be doing movflt/movdbl
2141
2142 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2143 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2144 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2145 void movss(XMMRegister dst, AddressLiteral src);
2146
2147 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2148 void movlpd(XMMRegister dst, AddressLiteral src);
2149
2150 public:
2151
2152 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2153 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2154 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2155 void movsd(XMMRegister dst, AddressLiteral src);
2156
2157 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2158 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2159 void ucomiss(XMMRegister dst, AddressLiteral src);
2160
2161 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2162 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2163 void ucomisd(XMMRegister dst, AddressLiteral src);
2164
2165 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2166 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2167 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2168 void xorpd(XMMRegister dst, AddressLiteral src);
2169
2170 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2171 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2172 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2173 void xorps(XMMRegister dst, AddressLiteral src);
2174
2175 // Data
2176
2177 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2178
2179 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2180 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2181
2182 void movoop(Register dst, jobject obj);
2183 void movoop(Address dst, jobject obj);
2184
2185 void movptr(ArrayAddress dst, Register src);
2186 // can this do an lea?
2187 void movptr(Register dst, ArrayAddress src);
2188
2189 void movptr(Register dst, Address src);
2190
2191 void movptr(Register dst, AddressLiteral src);
2192
2193 void movptr(Register dst, intptr_t src);
2194 void movptr(Register dst, Register src);
2195 void movptr(Address dst, intptr_t src);
2196
2197 void movptr(Address dst, Register src);
2198
2199 #ifdef _LP64
2200 // Generally the next two are only used for moving NULL
2201 // Although there are situations in initializing the mark word where
2202 // they could be used. They are dangerous.
2203
2204 // They only exist on LP64 so that int32_t and intptr_t are not the same
2205 // and we have ambiguous declarations.
2206
2207 void movptr(Address dst, int32_t imm32);
2208 void movptr(Register dst, int32_t imm32);
2209 #endif // _LP64
2210
2211 // to avoid hiding movl
2212 void mov32(AddressLiteral dst, Register src);
2213 void mov32(Register dst, AddressLiteral src);
2214
2215 // to avoid hiding movb
2216 void movbyte(ArrayAddress dst, int src);
2217
2218 // Can push value or effective address
2219 void pushptr(AddressLiteral src);
2220
2221 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2222 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2223
2224 void pushoop(jobject obj);
2225
2226 // sign extend as need a l to ptr sized element
2227 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2228 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2229
2230 // IndexOf strings.
2231 void string_indexof(Register str1, Register str2,
2232 Register cnt1, Register cnt2, Register result,
2233 XMMRegister vec, Register tmp);
2234
2235 // Compare strings.
2236 void string_compare(Register str1, Register str2,
2237 Register cnt1, Register cnt2, Register result,
2238 XMMRegister vec1, XMMRegister vec2);
2239
2240 // Compare char[] arrays.
2241 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2242 Register limit, Register result, Register chr,
2243 XMMRegister vec1, XMMRegister vec2);
2244
2245 // Fill primitive arrays
2246 void generate_fill(BasicType t, bool aligned,
2247 Register to, Register value, Register count,
2248 Register rtmp, XMMRegister xtmp);
2249
2250 #undef VIRTUAL
2251
2252 };
2253
2254 /**
2255 * class SkipIfEqual:
2256 *
2257 * Instantiating this class will result in assembly code being output that will
2258 * jump around any code emitted between the creation of the instance and it's
2259 * automatic destruction at the end of a scope block, depending on the value of
2260 * the flag passed to the constructor, which will be checked at run-time.
2261 */
2262 class SkipIfEqual {
2263 private:
2264 MacroAssembler* _masm;
2265 Label _label;
2266
2267 public:
2268 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2269 ~SkipIfEqual();
2270 };
2271
2272 #ifdef ASSERT
2273 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2274 #endif