58 AllocatePrefetchLines = 3;
59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 AllocateInstancePrefetchLines = 1;
62
63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 AllocatePrefetchStyle = allocate_prefetch_style();
65
66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 (AllocatePrefetchDistance > 0), "invalid value");
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 (AllocatePrefetchDistance <= 0)) {
70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 }
72
73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 warning("BIS instructions are not available on this CPU");
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 }
77
78 UseSSE = 0; // Only on x86 and x64
79
80 _supports_cx8 = has_v9();
81
82 if (is_niagara()) {
83 // Indirect branch is the same cost as direct
84 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
85 FLAG_SET_DEFAULT(UseInlineCaches, false);
86 }
87 // Align loops on a single instruction boundary.
88 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
89 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
90 }
91 // When using CMS, we cannot use memset() in BOT updates because
92 // the sun4v/CMT version in libc_psr uses BIS which exposes
93 // "phantom zeros" to concurrent readers. See 6948537.
94 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
95 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
96 }
97 #ifdef _LP64
163 // T4 and newer Sparc cpus have new compare and branch instruction.
164 if (has_cbcond()) {
165 if (FLAG_IS_DEFAULT(UseCBCond)) {
166 FLAG_SET_DEFAULT(UseCBCond, true);
167 }
168 } else if (UseCBCond) {
169 warning("CBCOND instruction is not available on this CPU");
170 FLAG_SET_DEFAULT(UseCBCond, false);
171 }
172
173 assert(BlockZeroingLowLimit > 0, "invalid value");
174 if (has_block_zeroing()) {
175 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
176 FLAG_SET_DEFAULT(UseBlockZeroing, true);
177 }
178 } else if (UseBlockZeroing) {
179 warning("BIS zeroing instructions are not available on this CPU");
180 FLAG_SET_DEFAULT(UseBlockZeroing, false);
181 }
182
183 #ifdef COMPILER2
184 // T4 and newer Sparc cpus have fast RDPC.
185 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
186 // FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
187 }
188
189 // Currently not supported anywhere.
190 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
191
192 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
193 #endif
194
195 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
196 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
197
198 char buf[512];
199 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
200 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
201 (has_hardware_popc() ? ", popc" : ""),
202 (has_vis1() ? ", vis1" : ""),
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58 AllocatePrefetchLines = 3;
59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 AllocateInstancePrefetchLines = 1;
62
63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 AllocatePrefetchStyle = allocate_prefetch_style();
65
66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 (AllocatePrefetchDistance > 0), "invalid value");
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 (AllocatePrefetchDistance <= 0)) {
70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 }
72
73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 warning("BIS instructions are not available on this CPU");
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 }
77
78 if (has_v9()) {
79 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
80 if (ArraycopySrcPrefetchDistance >= 4096)
81 ArraycopySrcPrefetchDistance = 4064;
82 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
83 if (ArraycopyDstPrefetchDistance >= 4096)
84 ArraycopyDstPrefetchDistance = 4064;
85 } else {
86 if (ArraycopySrcPrefetchDistance > 0) {
87 warning("prefetch instructions are not available on this CPU");
88 FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0);
89 }
90 if (ArraycopyDstPrefetchDistance > 0) {
91 warning("prefetch instructions are not available on this CPU");
92 FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0);
93 }
94 }
95
96 UseSSE = 0; // Only on x86 and x64
97
98 _supports_cx8 = has_v9();
99
100 if (is_niagara()) {
101 // Indirect branch is the same cost as direct
102 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
103 FLAG_SET_DEFAULT(UseInlineCaches, false);
104 }
105 // Align loops on a single instruction boundary.
106 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
107 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
108 }
109 // When using CMS, we cannot use memset() in BOT updates because
110 // the sun4v/CMT version in libc_psr uses BIS which exposes
111 // "phantom zeros" to concurrent readers. See 6948537.
112 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
113 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
114 }
115 #ifdef _LP64
181 // T4 and newer Sparc cpus have new compare and branch instruction.
182 if (has_cbcond()) {
183 if (FLAG_IS_DEFAULT(UseCBCond)) {
184 FLAG_SET_DEFAULT(UseCBCond, true);
185 }
186 } else if (UseCBCond) {
187 warning("CBCOND instruction is not available on this CPU");
188 FLAG_SET_DEFAULT(UseCBCond, false);
189 }
190
191 assert(BlockZeroingLowLimit > 0, "invalid value");
192 if (has_block_zeroing()) {
193 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
194 FLAG_SET_DEFAULT(UseBlockZeroing, true);
195 }
196 } else if (UseBlockZeroing) {
197 warning("BIS zeroing instructions are not available on this CPU");
198 FLAG_SET_DEFAULT(UseBlockZeroing, false);
199 }
200
201 assert(BlockCopyLowLimit > 0, "invalid value");
202 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
203 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
204 FLAG_SET_DEFAULT(UseBlockCopy, true);
205 }
206 } else if (UseBlockCopy) {
207 warning("BIS instructions are not available or expensive on this CPU");
208 FLAG_SET_DEFAULT(UseBlockCopy, false);
209 }
210
211 #ifdef COMPILER2
212 // T4 and newer Sparc cpus have fast RDPC.
213 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
214 // FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
215 }
216
217 // Currently not supported anywhere.
218 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
219
220 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
221 #endif
222
223 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
224 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
225
226 char buf[512];
227 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
228 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
229 (has_hardware_popc() ? ", popc" : ""),
230 (has_vis1() ? ", vis1" : ""),
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