src/cpu/sparc/vm/assembler_sparc.hpp
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*** old/src/cpu/sparc/vm/assembler_sparc.hpp	Wed Aug 24 15:01:35 2011
--- new/src/cpu/sparc/vm/assembler_sparc.hpp	Wed Aug 24 15:01:35 2011

*** 884,893 **** --- 884,894 ---- return is_in_wdisp_range(a, b, 30); } enum ASIs { // page 72, v9 ASI_PRIMARY = 0x80, + ASI_PRIMARY_NOFAULT = 0x82, ASI_PRIMARY_LITTLE = 0x88, // Block initializing store ASI_ST_BLKINIT_PRIMARY = 0xE2, // Most-Recently-Used (MRU) BIS variant ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
*** 1784,1796 **** --- 1785,1800 ---- inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | ! u_field(1, 13, 13) | ! immed(true) | simm(simm13a, 13)); } - inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } + // wrasi(d, imm) stores (d xor imm) to asi + inline void wrasi(Register d, int simm13a) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | + u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } // VIS3 instructions
*** 2629,2638 **** --- 2633,2644 ---- // Compare char[] arrays aligned to 4 bytes. void char_arrays_equals(Register ary1, Register ary2, Register limit, Register result, Register chr1, Register chr2, Label& Ldone); + // Use BIS for zeroing + void bis_zeroing(Register to, Register count, Register temp, Label& Ldone); #undef VIRTUAL };

src/cpu/sparc/vm/assembler_sparc.hpp
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