1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #include "precompiled.hpp"
26 #include "libadt/vectset.hpp"
27 #include "memory/allocation.inline.hpp"
28 #include "opto/addnode.hpp"
29 #include "opto/c2compiler.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/cfgnode.hpp"
32 #include "opto/chaitin.hpp"
33 #include "opto/loopnode.hpp"
34 #include "opto/machnode.hpp"
35
36 //------------------------------Split--------------------------------------
37 // Walk the graph in RPO and for each lrg which spills, propagate reaching
38 // definitions. During propagation, split the live range around regions of
39 // High Register Pressure (HRP). If a Def is in a region of Low Register
40 // Pressure (LRP), it will not get spilled until we encounter a region of
41 // HRP between it and one of its uses. We will spill at the transition
42 // point between LRP and HRP. Uses in the HRP region will use the spilled
43 // Def. The first Use outside the HRP region will generate a SpillCopy to
44 // hoist the live range back up into a register, and all subsequent uses
45 // will use that new Def until another HRP region is encountered. Defs in
46 // HRP regions will get trailing SpillCopies to push the LRG down into the
47 // stack immediately.
48 //
49 // As a side effect, unlink from (hence make dead) coalesced copies.
50 //
51
52 static const char out_of_nodes[] = "out of nodes during split";
53
54 //------------------------------get_spillcopy_wide-----------------------------
55 // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the
56 // wide ideal-register spill-mask if possible. If the 'wide-mask' does
57 // not cover the input (or output), use the input (or output) mask instead.
58 Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) {
59 // If ideal reg doesn't exist we've got a bad schedule happening
60 // that is forcing us to spill something that isn't spillable.
61 // Bail rather than abort
62 int ireg = def->ideal_reg();
63 if( ireg == 0 || ireg == Op_RegFlags ) {
64 assert(false, "attempted to spill a non-spillable item");
65 C->record_method_not_compilable("attempted to spill a non-spillable item");
66 return NULL;
67 }
68 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
69 return NULL;
70 }
71 const RegMask *i_mask = &def->out_RegMask();
72 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
73 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
74 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
75 const RegMask *w_o_mask;
76
77 if( w_mask->overlap( *o_mask ) && // Overlap AND
78 ((ireg != Op_RegL && ireg != Op_RegD // Single use or aligned
79 #ifdef _LP64
80 && ireg != Op_RegP
81 #endif
82 ) || o_mask->is_aligned_Pairs()) ) {
83 // Don't come here for mis-aligned doubles
84 w_o_mask = w_mask;
85 } else { // wide ideal mask does not overlap with o_mask
86 // Mis-aligned doubles come here and XMM->FPR moves on x86.
87 w_o_mask = o_mask; // Must target desired registers
88 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
89 // a reg-reg move or do I need a trip across register classes
90 // (and thus through memory)?
91 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
92 // Here we assume a trip through memory is required.
93 w_i_mask = &C->FIRST_STACK_mask();
94 }
95 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask );
96 }
97
98 //------------------------------insert_proj------------------------------------
99 // Insert the spill at chosen location. Skip over any intervening Proj's or
100 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
101 // instead. Update high-pressure indices. Create a new live range.
102 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
103 // Skip intervening ProjNodes. Do not insert between a ProjNode and
104 // its definer.
105 while( i < b->_nodes.size() &&
106 (b->_nodes[i]->is_Proj() ||
107 b->_nodes[i]->is_Phi() ) )
108 i++;
109
110 // Do not insert between a call and his Catch
111 if( b->_nodes[i]->is_Catch() ) {
112 // Put the instruction at the top of the fall-thru block.
113 // Find the fall-thru projection
114 while( 1 ) {
115 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj();
116 if( cp->_con == CatchProjNode::fall_through_index )
117 break;
118 }
119 int sidx = i - b->end_idx()-1;
120 b = b->_succs[sidx]; // Switch to successor block
121 i = 1; // Right at start of block
122 }
123
124 b->_nodes.insert(i,spill); // Insert node in block
125 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect
126 // Adjust the point where we go hi-pressure
127 if( i <= b->_ihrp_index ) b->_ihrp_index++;
128 if( i <= b->_fhrp_index ) b->_fhrp_index++;
129
130 // Assign a new Live Range Number to the SpillCopy and grow
131 // the node->live range mapping.
132 new_lrg(spill,maxlrg);
133 }
134
135 //------------------------------split_DEF--------------------------------------
136 // There are four categories of Split; UP/DOWN x DEF/USE
137 // Only three of these really occur as DOWN/USE will always color
138 // Any Split with a DEF cannot CISC-Spill now. Thus we need
139 // two helper routines, one for Split DEFS (insert after instruction),
140 // one for Split USES (insert before instruction). DEF insertion
141 // happens inside Split, where the Leaveblock array is updated.
142 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
143 #ifdef ASSERT
144 // Increment the counter for this lrg
145 splits.at_put(slidx, splits.at(slidx)+1);
146 #endif
147 // If we are spilling the memory op for an implicit null check, at the
148 // null check location (ie - null check is in HRP block) we need to do
149 // the null-check first, then spill-down in the following block.
150 // (The implicit_null_check function ensures the use is also dominated
151 // by the branch-not-taken block.)
152 Node *be = b->end();
153 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) {
154 // Spill goes in the branch-not-taken block
155 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue];
156 loc = 0; // Just past the Region
157 }
158 assert( loc >= 0, "must insert past block head" );
159
160 // Get a def-side SpillCopy
161 Node *spill = get_spillcopy_wide(def,NULL,0);
162 // Did we fail to split?, then bail
163 if (!spill) {
164 return 0;
165 }
166
167 // Insert the spill at chosen location
168 insert_proj( b, loc+1, spill, maxlrg++);
169
170 // Insert new node into Reaches array
171 Reachblock[slidx] = spill;
172 // Update debug list of reaching down definitions by adding this one
173 debug_defs[slidx] = spill;
174
175 // return updated count of live ranges
176 return maxlrg;
177 }
178
179 //------------------------------split_USE--------------------------------------
180 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
181 // Debug uses want to know if def is already stack enabled.
182 uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
183 #ifdef ASSERT
184 // Increment the counter for this lrg
185 splits.at_put(slidx, splits.at(slidx)+1);
186 #endif
187
188 // Some setup stuff for handling debug node uses
189 JVMState* jvms = use->jvms();
190 uint debug_start = jvms ? jvms->debug_start() : 999999;
191 uint debug_end = jvms ? jvms->debug_end() : 999999;
192
193 //-------------------------------------------
194 // Check for use of debug info
195 if (useidx >= debug_start && useidx < debug_end) {
196 // Actually it's perfectly legal for constant debug info to appear
197 // just unlikely. In this case the optimizer left a ConI of a 4
198 // as both inputs to a Phi with only a debug use. It's a single-def
199 // live range of a rematerializable value. The live range spills,
200 // rematerializes and now the ConI directly feeds into the debug info.
201 // assert(!def->is_Con(), "constant debug info already constructed directly");
202
203 // Special split handling for Debug Info
204 // If DEF is DOWN, just hook the edge and return
205 // If DEF is UP, Split it DOWN for this USE.
206 if( def->is_Mach() ) {
207 if( def_down ) {
208 // DEF is DOWN, so connect USE directly to the DEF
209 use->set_req(useidx, def);
210 } else {
211 // Block and index where the use occurs.
212 Block *b = _cfg._bbs[use->_idx];
213 // Put the clone just prior to use
214 int bindex = b->find_node(use);
215 // DEF is UP, so must copy it DOWN and hook in USE
216 // Insert SpillCopy before the USE, which uses DEF as its input,
217 // and defs a new live range, which is used by this node.
218 Node *spill = get_spillcopy_wide(def,use,useidx);
219 // did we fail to split?
220 if (!spill) {
221 // Bail
222 return 0;
223 }
224 // insert into basic block
225 insert_proj( b, bindex, spill, maxlrg++ );
226 // Use the new split
227 use->set_req(useidx,spill);
228 }
229 // No further split handling needed for this use
230 return maxlrg;
231 } // End special splitting for debug info live range
232 } // If debug info
233
234 // CISC-SPILLING
235 // Finally, check to see if USE is CISC-Spillable, and if so,
236 // gather_lrg_masks will add the flags bit to its mask, and
237 // no use side copy is needed. This frees up the live range
238 // register choices without causing copy coalescing, etc.
239 if( UseCISCSpill && cisc_sp ) {
240 int inp = use->cisc_operand();
241 if( inp != AdlcVMDeps::Not_cisc_spillable )
242 // Convert operand number to edge index number
243 inp = use->as_Mach()->operand_index(inp);
244 if( inp == (int)useidx ) {
245 use->set_req(useidx, def);
246 #ifndef PRODUCT
247 if( TraceCISCSpill ) {
248 tty->print(" set_split: ");
249 use->dump();
250 }
251 #endif
252 return maxlrg;
253 }
254 }
255
256 //-------------------------------------------
257 // Insert a Copy before the use
258
259 // Block and index where the use occurs.
260 int bindex;
261 // Phi input spill-copys belong at the end of the prior block
262 if( use->is_Phi() ) {
263 b = _cfg._bbs[b->pred(useidx)->_idx];
264 bindex = b->end_idx();
265 } else {
266 // Put the clone just prior to use
267 bindex = b->find_node(use);
268 }
269
270 Node *spill = get_spillcopy_wide( def, use, useidx );
271 if( !spill ) return 0; // Bailed out
272 // Insert SpillCopy before the USE, which uses the reaching DEF as
273 // its input, and defs a new live range, which is used by this node.
274 insert_proj( b, bindex, spill, maxlrg++ );
275 // Use the spill/clone
276 use->set_req(useidx,spill);
277
278 // return updated live range count
279 return maxlrg;
280 }
281
282 //------------------------------clone_node----------------------------
283 // Clone node with anti dependence check.
284 Node* clone_node(Node* def, Block *b, Compile* C) {
285 if (def->needs_anti_dependence_check()) {
286 #ifdef ASSERT
287 if (Verbose) {
288 tty->print_cr("RA attempts to clone node with anti_dependence:");
289 def->dump(-1); tty->cr();
290 tty->print_cr("into block:");
291 b->dump();
292 }
293 #endif
294 if (C->subsume_loads() == true && !C->failing()) {
295 // Retry with subsume_loads == false
296 // If this is the first failure, the sentinel string will "stick"
297 // to the Compile object, and the C2Compiler will see it and retry.
298 C->record_failure(C2Compiler::retry_no_subsuming_loads());
299 } else {
300 // Bailout without retry
301 C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence");
302 }
303 return 0;
304 }
305 return def->clone();
306 }
307
308 //------------------------------split_Rematerialize----------------------------
309 // Clone a local copy of the def.
310 Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) {
311 // The input live ranges will be stretched to the site of the new
312 // instruction. They might be stretched past a def and will thus
313 // have the old and new values of the same live range alive at the
314 // same time - a definite no-no. Split out private copies of
315 // the inputs.
316 if( def->req() > 1 ) {
317 for( uint i = 1; i < def->req(); i++ ) {
318 Node *in = def->in(i);
319 // Check for single-def (LRG cannot redefined)
320 uint lidx = n2lidx(in);
321 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy
322 if (lrgs(lidx).is_singledef()) continue;
323
324 Block *b_def = _cfg._bbs[def->_idx];
325 int idx_def = b_def->find_node(def);
326 Node *in_spill = get_spillcopy_wide( in, def, i );
327 if( !in_spill ) return 0; // Bailed out
328 insert_proj(b_def,idx_def,in_spill,maxlrg++);
329 if( b_def == b )
330 insidx++;
331 def->set_req(i,in_spill);
332 }
333 }
334
335 Node *spill = clone_node(def, b, C);
336 if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
337 // Check when generating nodes
338 return 0;
339 }
340
341 // See if any inputs are currently being spilled, and take the
342 // latest copy of spilled inputs.
343 if( spill->req() > 1 ) {
344 for( uint i = 1; i < spill->req(); i++ ) {
345 Node *in = spill->in(i);
346 uint lidx = Find_id(in);
347
348 // Walk backwards thru spill copy node intermediates
349 if (walkThru) {
350 while ( in->is_SpillCopy() && lidx >= _maxlrg ) {
351 in = in->in(1);
352 lidx = Find_id(in);
353 }
354
355 if (lidx < _maxlrg && lrgs(lidx).is_multidef()) {
356 // walkThru found a multidef LRG, which is unsafe to use, so
357 // just keep the original def used in the clone.
358 in = spill->in(i);
359 lidx = Find_id(in);
360 }
361 }
362
363 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) {
364 Node *rdef = Reachblock[lrg2reach[lidx]];
365 if( rdef ) spill->set_req(i,rdef);
366 }
367 }
368 }
369
370
371 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
372 // Rematerialized op is def->spilled+1
373 set_was_spilled(spill);
374 if( _spilled_once.test(def->_idx) )
375 set_was_spilled(spill);
376
377 insert_proj( b, insidx, spill, maxlrg++ );
378 #ifdef ASSERT
379 // Increment the counter for this lrg
380 splits.at_put(slidx, splits.at(slidx)+1);
381 #endif
382 // See if the cloned def kills any flags, and copy those kills as well
383 uint i = insidx+1;
384 if( clone_projs( b, i, def, spill, maxlrg ) ) {
385 // Adjust the point where we go hi-pressure
386 if( i <= b->_ihrp_index ) b->_ihrp_index++;
387 if( i <= b->_fhrp_index ) b->_fhrp_index++;
388 }
389
390 return spill;
391 }
392
393 //------------------------------is_high_pressure-------------------------------
394 // Function to compute whether or not this live range is "high pressure"
395 // in this block - whether it spills eagerly or not.
396 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
397 if( lrg->_was_spilled1 ) return true;
398 // Forced spilling due to conflict? Then split only at binding uses
399 // or defs, not for supposed capacity problems.
400 // CNC - Turned off 7/8/99, causes too much spilling
401 // if( lrg->_is_bound ) return false;
402
403 // Not yet reached the high-pressure cutoff point, so low pressure
404 uint hrp_idx = lrg->_is_float ? b->_fhrp_index : b->_ihrp_index;
405 if( insidx < hrp_idx ) return false;
406 // Register pressure for the block as a whole depends on reg class
407 int block_pres = lrg->_is_float ? b->_freg_pressure : b->_reg_pressure;
408 // Bound live ranges will split at the binding points first;
409 // Intermediate splits should assume the live range's register set
410 // got "freed up" and that num_regs will become INT_PRESSURE.
411 int bound_pres = lrg->_is_float ? FLOATPRESSURE : INTPRESSURE;
412 // Effective register pressure limit.
413 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
414 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
415 // High pressure if block pressure requires more register freedom
416 // than live range has.
417 return block_pres >= lrg_pres;
418 }
419
420
421 //------------------------------prompt_use---------------------------------
422 // True if lidx is used before any real register is def'd in the block
423 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
424 if( lrgs(lidx)._was_spilled2 ) return false;
425
426 // Scan block for 1st use.
427 for( uint i = 1; i <= b->end_idx(); i++ ) {
428 Node *n = b->_nodes[i];
429 // Ignore PHI use, these can be up or down
430 if( n->is_Phi() ) continue;
431 for( uint j = 1; j < n->req(); j++ )
432 if( Find_id(n->in(j)) == lidx )
433 return true; // Found 1st use!
434 if( n->out_RegMask().is_NotEmpty() ) return false;
435 }
436 return false;
437 }
438
439 //------------------------------Split--------------------------------------
440 //----------Split Routine----------
441 // ***** NEW SPLITTING HEURISTIC *****
442 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
443 // Else, no split unless there is a HRP block between a DEF and
444 // one of its uses, and then split at the HRP block.
445 //
446 // USES: If USE is in HRP, split at use to leave main LRG on stack.
447 // Else, hoist LRG back up to register only (ie - split is also DEF)
448 // We will compute a new maxlrg as we go
449 uint PhaseChaitin::Split( uint maxlrg ) {
450 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); )
451
452 uint bidx, pidx, slidx, insidx, inpidx, twoidx;
453 uint non_phi = 1, spill_cnt = 0;
454 Node **Reachblock;
455 Node *n1, *n2, *n3;
456 Node_List *defs,*phis;
457 bool *UPblock;
458 bool u1, u2, u3;
459 Block *b, *pred;
460 PhiNode *phi;
461 GrowableArray<uint> lidxs;
462
463 // Array of counters to count splits per live range
464 GrowableArray<uint> splits;
465
466 //----------Setup Code----------
467 // Create a convenient mapping from lrg numbers to reaches/leaves indices
468 uint *lrg2reach = NEW_RESOURCE_ARRAY( uint, _maxlrg );
469 // Keep track of DEFS & Phis for later passes
470 defs = new Node_List();
471 phis = new Node_List();
472 // Gather info on which LRG's are spilling, and build maps
473 for( bidx = 1; bidx < _maxlrg; bidx++ ) {
474 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
475 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
476 lrg2reach[bidx] = spill_cnt;
477 spill_cnt++;
478 lidxs.append(bidx);
479 #ifdef ASSERT
480 // Initialize the split counts to zero
481 splits.append(0);
482 #endif
483 #ifndef PRODUCT
484 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 )
485 tty->print_cr("Warning, 2nd spill of L%d",bidx);
486 #endif
487 }
488 }
489
490 // Create side arrays for propagating reaching defs info.
491 // Each block needs a node pointer for each spilling live range for the
492 // Def which is live into the block. Phi nodes handle multiple input
493 // Defs by querying the output of their predecessor blocks and resolving
494 // them to a single Def at the phi. The pointer is updated for each
495 // Def in the block, and then becomes the output for the block when
496 // processing of the block is complete. We also need to track whether
497 // a Def is UP or DOWN. UP means that it should get a register (ie -
498 // it is always in LRP regions), and DOWN means that it is probably
499 // on the stack (ie - it crosses HRP regions).
500 Node ***Reaches = NEW_RESOURCE_ARRAY( Node**, _cfg._num_blocks+1 );
501 bool **UP = NEW_RESOURCE_ARRAY( bool*, _cfg._num_blocks+1 );
502 Node **debug_defs = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
503 VectorSet **UP_entry= NEW_RESOURCE_ARRAY( VectorSet*, spill_cnt );
504
505 // Initialize Reaches & UP
506 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) {
507 Reaches[bidx] = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
508 UP[bidx] = NEW_RESOURCE_ARRAY( bool, spill_cnt );
509 Node **Reachblock = Reaches[bidx];
510 bool *UPblock = UP[bidx];
511 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
512 UPblock[slidx] = true; // Assume they start in registers
513 Reachblock[slidx] = NULL; // Assume that no def is present
514 }
515 }
516
517 // Initialize to array of empty vectorsets
518 for( slidx = 0; slidx < spill_cnt; slidx++ )
519 UP_entry[slidx] = new VectorSet(Thread::current()->resource_area());
520
521 //----------PASS 1----------
522 //----------Propagation & Node Insertion Code----------
523 // Walk the Blocks in RPO for DEF & USE info
524 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
525
526 if (C->check_node_count(spill_cnt, out_of_nodes)) {
527 return 0;
528 }
529
530 b = _cfg._blocks[bidx];
531 // Reaches & UP arrays for this block
532 Reachblock = Reaches[b->_pre_order];
533 UPblock = UP[b->_pre_order];
534 // Reset counter of start of non-Phi nodes in block
535 non_phi = 1;
536 //----------Block Entry Handling----------
537 // Check for need to insert a new phi
538 // Cycle through this block's predecessors, collecting Reaches
539 // info for each spilled LRG. If they are identical, no phi is
540 // needed. If they differ, check for a phi, and insert if missing,
541 // or update edges if present. Set current block's Reaches set to
542 // be either the phi's or the reaching def, as appropriate.
543 // If no Phi is needed, check if the LRG needs to spill on entry
544 // to the block due to HRP.
545 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
546 // Grab the live range number
547 uint lidx = lidxs.at(slidx);
548 // Do not bother splitting or putting in Phis for single-def
549 // rematerialized live ranges. This happens alot to constants
550 // with long live ranges.
551 if( lrgs(lidx).is_singledef() &&
552 lrgs(lidx)._def->rematerialize() ) {
553 // reset the Reaches & UP entries
554 Reachblock[slidx] = lrgs(lidx)._def;
555 UPblock[slidx] = true;
556 // Record following instruction in case 'n' rematerializes and
557 // kills flags
558 Block *pred1 = _cfg._bbs[b->pred(1)->_idx];
559 continue;
560 }
561
562 // Initialize needs_phi and needs_split
563 bool needs_phi = false;
564 bool needs_split = false;
565 bool has_phi = false;
566 // Walk the predecessor blocks to check inputs for that live range
567 // Grab predecessor block header
568 n1 = b->pred(1);
569 // Grab the appropriate reaching def info for inpidx
570 pred = _cfg._bbs[n1->_idx];
571 pidx = pred->_pre_order;
572 Node **Ltmp = Reaches[pidx];
573 bool *Utmp = UP[pidx];
574 n1 = Ltmp[slidx];
575 u1 = Utmp[slidx];
576 // Initialize node for saving type info
577 n3 = n1;
578 u3 = u1;
579
580 // Compare inputs to see if a Phi is needed
581 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
582 // Grab predecessor block headers
583 n2 = b->pred(inpidx);
584 // Grab the appropriate reaching def info for inpidx
585 pred = _cfg._bbs[n2->_idx];
586 pidx = pred->_pre_order;
587 Ltmp = Reaches[pidx];
588 Utmp = UP[pidx];
589 n2 = Ltmp[slidx];
590 u2 = Utmp[slidx];
591 // For each LRG, decide if a phi is necessary
592 if( n1 != n2 ) {
593 needs_phi = true;
594 }
595 // See if the phi has mismatched inputs, UP vs. DOWN
596 if( n1 && n2 && (u1 != u2) ) {
597 needs_split = true;
598 }
599 // Move n2/u2 to n1/u1 for next iteration
600 n1 = n2;
601 u1 = u2;
602 // Preserve a non-NULL predecessor for later type referencing
603 if( (n3 == NULL) && (n2 != NULL) ){
604 n3 = n2;
605 u3 = u2;
606 }
607 } // End for all potential Phi inputs
608
609 // check block for appropriate phinode & update edges
610 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
611 n1 = b->_nodes[insidx];
612 // bail if this is not a phi
613 phi = n1->is_Phi() ? n1->as_Phi() : NULL;
614 if( phi == NULL ) {
615 // Keep track of index of first non-PhiNode instruction in block
616 non_phi = insidx;
617 // break out of the for loop as we have handled all phi nodes
618 break;
619 }
620 // must be looking at a phi
621 if( Find_id(n1) == lidxs.at(slidx) ) {
622 // found the necessary phi
623 needs_phi = false;
624 has_phi = true;
625 // initialize the Reaches entry for this LRG
626 Reachblock[slidx] = phi;
627 break;
628 } // end if found correct phi
629 } // end for all phi's
630
631 // If a phi is needed or exist, check for it
632 if( needs_phi || has_phi ) {
633 // add new phinode if one not already found
634 if( needs_phi ) {
635 // create a new phi node and insert it into the block
636 // type is taken from left over pointer to a predecessor
637 assert(n3,"No non-NULL reaching DEF for a Phi");
638 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type());
639 // initialize the Reaches entry for this LRG
640 Reachblock[slidx] = phi;
641
642 // add node to block & node_to_block mapping
643 insert_proj( b, insidx++, phi, maxlrg++ );
644 non_phi++;
645 // Reset new phi's mapping to be the spilling live range
646 _names.map(phi->_idx, lidx);
647 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping");
648 } // end if not found correct phi
649 // Here you have either found or created the Phi, so record it
650 assert(phi != NULL,"Must have a Phi Node here");
651 phis->push(phi);
652 // PhiNodes should either force the LRG UP or DOWN depending
653 // on its inputs and the register pressure in the Phi's block.
654 UPblock[slidx] = true; // Assume new DEF is UP
655 // If entering a high-pressure area with no immediate use,
656 // assume Phi is DOWN
657 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
658 UPblock[slidx] = false;
659 // If we are not split up/down and all inputs are down, then we
660 // are down
661 if( !needs_split && !u3 )
662 UPblock[slidx] = false;
663 } // end if phi is needed
664
665 // Do not need a phi, so grab the reaching DEF
666 else {
667 // Grab predecessor block header
668 n1 = b->pred(1);
669 // Grab the appropriate reaching def info for k
670 pred = _cfg._bbs[n1->_idx];
671 pidx = pred->_pre_order;
672 Node **Ltmp = Reaches[pidx];
673 bool *Utmp = UP[pidx];
674 // reset the Reaches & UP entries
675 Reachblock[slidx] = Ltmp[slidx];
676 UPblock[slidx] = Utmp[slidx];
677 } // end else no Phi is needed
678 } // end for all spilling live ranges
679 // DEBUG
680 #ifndef PRODUCT
681 if(trace_spilling()) {
682 tty->print("/`\nBlock %d: ", b->_pre_order);
683 tty->print("Reaching Definitions after Phi handling\n");
684 for( uint x = 0; x < spill_cnt; x++ ) {
685 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
686 if( Reachblock[x] )
687 Reachblock[x]->dump();
688 else
689 tty->print("Undefined\n");
690 }
691 }
692 #endif
693
694 //----------Non-Phi Node Splitting----------
695 // Since phi-nodes have now been handled, the Reachblock array for this
696 // block is initialized with the correct starting value for the defs which
697 // reach non-phi instructions in this block. Thus, process non-phi
698 // instructions normally, inserting SpillCopy nodes for all spill
699 // locations.
700
701 // Memoize any DOWN reaching definitions for use as DEBUG info
702 for( insidx = 0; insidx < spill_cnt; insidx++ ) {
703 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
704 if( UPblock[insidx] ) // Memoize UP decision at block start
705 UP_entry[insidx]->set( b->_pre_order );
706 }
707
708 //----------Walk Instructions in the Block and Split----------
709 // For all non-phi instructions in the block
710 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
711 Node *n = b->_nodes[insidx];
712 // Find the defining Node's live range index
713 uint defidx = Find_id(n);
714 uint cnt = n->req();
715
716 if( n->is_Phi() ) {
717 // Skip phi nodes after removing dead copies.
718 if( defidx < _maxlrg ) {
719 // Check for useless Phis. These appear if we spill, then
720 // coalesce away copies. Dont touch Phis in spilling live
721 // ranges; they are busy getting modifed in this pass.
722 if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
723 uint i;
724 Node *u = NULL;
725 // Look for the Phi merging 2 unique inputs
726 for( i = 1; i < cnt; i++ ) {
727 // Ignore repeats and self
728 if( n->in(i) != u && n->in(i) != n ) {
729 // Found a unique input
730 if( u != NULL ) // If it's the 2nd, bail out
731 break;
732 u = n->in(i); // Else record it
733 }
734 }
735 assert( u, "at least 1 valid input expected" );
736 if( i >= cnt ) { // Found one unique input
737 assert(Find_id(n) == Find_id(u), "should be the same lrg");
738 n->replace_by(u); // Then replace with unique input
739 n->disconnect_inputs(NULL);
740 b->_nodes.remove(insidx);
741 insidx--;
742 b->_ihrp_index--;
743 b->_fhrp_index--;
744 }
745 }
746 }
747 continue;
748 }
749 assert( insidx > b->_ihrp_index ||
750 (b->_reg_pressure < (uint)INTPRESSURE) ||
751 b->_ihrp_index > 4000000 ||
752 b->_ihrp_index >= b->end_idx() ||
753 !b->_nodes[b->_ihrp_index]->is_Proj(), "" );
754 assert( insidx > b->_fhrp_index ||
755 (b->_freg_pressure < (uint)FLOATPRESSURE) ||
756 b->_fhrp_index > 4000000 ||
757 b->_fhrp_index >= b->end_idx() ||
758 !b->_nodes[b->_fhrp_index]->is_Proj(), "" );
759
760 // ********** Handle Crossing HRP Boundry **********
761 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
762 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
763 // Check for need to split at HRP boundary - split if UP
764 n1 = Reachblock[slidx];
765 // bail out if no reaching DEF
766 if( n1 == NULL ) continue;
767 // bail out if live range is 'isolated' around inner loop
768 uint lidx = lidxs.at(slidx);
769 // If live range is currently UP
770 if( UPblock[slidx] ) {
771 // set location to insert spills at
772 // SPLIT DOWN HERE - NO CISC SPILL
773 if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
774 !n1->rematerialize() ) {
775 // If there is already a valid stack definition available, use it
776 if( debug_defs[slidx] != NULL ) {
777 Reachblock[slidx] = debug_defs[slidx];
778 }
779 else {
780 // Insert point is just past last use or def in the block
781 int insert_point = insidx-1;
782 while( insert_point > 0 ) {
783 Node *n = b->_nodes[insert_point];
784 // Hit top of block? Quit going backwards
785 if( n->is_Phi() ) break;
786 // Found a def? Better split after it.
787 if( n2lidx(n) == lidx ) break;
788 // Look for a use
789 uint i;
790 for( i = 1; i < n->req(); i++ )
791 if( n2lidx(n->in(i)) == lidx )
792 break;
793 // Found a use? Better split after it.
794 if( i < n->req() ) break;
795 insert_point--;
796 }
797 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
798 // If it wasn't split bail
799 if (!maxlrg) {
800 return 0;
801 }
802 insidx++;
803 }
804 // This is a new DEF, so update UP
805 UPblock[slidx] = false;
806 #ifndef PRODUCT
807 // DEBUG
808 if( trace_spilling() ) {
809 tty->print("\nNew Split DOWN DEF of Spill Idx ");
810 tty->print("%d, UP %d:\n",slidx,false);
811 n1->dump();
812 }
813 #endif
814 }
815 } // end if LRG is UP
816 } // end for all spilling live ranges
817 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" );
818 } // end if crossing HRP Boundry
819
820 // If the LRG index is oob, then this is a new spillcopy, skip it.
821 if( defidx >= _maxlrg ) {
822 continue;
823 }
824 LRG &deflrg = lrgs(defidx);
825 uint copyidx = n->is_Copy();
826 // Remove coalesced copy from CFG
827 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) {
828 n->replace_by( n->in(copyidx) );
829 n->set_req( copyidx, NULL );
830 b->_nodes.remove(insidx--);
831 b->_ihrp_index--; // Adjust the point where we go hi-pressure
832 b->_fhrp_index--;
833 continue;
834 }
835
836 #define DERIVED 0
837
838 // ********** Handle USES **********
839 bool nullcheck = false;
840 // Implicit null checks never use the spilled value
841 if( n->is_MachNullCheck() )
842 nullcheck = true;
843 if( !nullcheck ) {
844 // Search all inputs for a Spill-USE
845 JVMState* jvms = n->jvms();
846 uint oopoff = jvms ? jvms->oopoff() : cnt;
847 uint old_last = cnt - 1;
848 for( inpidx = 1; inpidx < cnt; inpidx++ ) {
849 // Derived/base pairs may be added to our inputs during this loop.
850 // If inpidx > old_last, then one of these new inputs is being
851 // handled. Skip the derived part of the pair, but process
852 // the base like any other input.
853 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) {
854 continue; // skip derived_debug added below
855 }
856 // Get lidx of input
857 uint useidx = Find_id(n->in(inpidx));
858 // Not a brand-new split, and it is a spill use
859 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) {
860 // Check for valid reaching DEF
861 slidx = lrg2reach[useidx];
862 Node *def = Reachblock[slidx];
863 assert( def != NULL, "Using Undefined Value in Split()\n");
864
865 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
866 // monitor references do not care where they live, so just hook
867 if ( jvms && jvms->is_monitor_use(inpidx) ) {
868 // The effect of this clone is to drop the node out of the block,
869 // so that the allocator does not see it anymore, and therefore
870 // does not attempt to assign it a register.
871 def = clone_node(def, b, C);
872 if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
873 return 0;
874 }
875 _names.extend(def->_idx,0);
876 _cfg._bbs.map(def->_idx,b);
877 n->set_req(inpidx, def);
878 continue;
879 }
880
881 // Rematerializable? Then clone def at use site instead
882 // of store/load
883 if( def->rematerialize() ) {
884 int old_size = b->_nodes.size();
885 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
886 if( !def ) return 0; // Bail out
887 insidx += b->_nodes.size()-old_size;
888 }
889
890 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
891 // Base pointers and oopmap references do not care where they live.
892 if ((inpidx >= oopoff) ||
893 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
894 if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
895 // This def has been rematerialized a couple of times without
896 // progress. It doesn't care if it lives UP or DOWN, so
897 // spill it down now.
898 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx);
899 // If it wasn't split bail
900 if (!maxlrg) {
901 return 0;
902 }
903 insidx++; // Reset iterator to skip USE side split
904 } else {
905 // Just hook the def edge
906 n->set_req(inpidx, def);
907 }
908
909 if (inpidx >= oopoff) {
910 // After oopoff, we have derived/base pairs. We must mention all
911 // derived pointers here as derived/base pairs for GC. If the
912 // derived value is spilling and we have a copy both in Reachblock
913 // (called here 'def') and debug_defs[slidx] we need to mention
914 // both in derived/base pairs or kill one.
915 Node *derived_debug = debug_defs[slidx];
916 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
917 mach && mach->ideal_Opcode() != Op_Halt &&
918 derived_debug != NULL &&
919 derived_debug != def ) { // Actual 2nd value appears
920 // We have already set 'def' as a derived value.
921 // Also set debug_defs[slidx] as a derived value.
922 uint k;
923 for( k = oopoff; k < cnt; k += 2 )
924 if( n->in(k) == derived_debug )
925 break; // Found an instance of debug derived
926 if( k == cnt ) {// No instance of debug_defs[slidx]
927 // Add a derived/base pair to cover the debug info.
928 // We have to process the added base later since it is not
929 // handled yet at this point but skip derived part.
930 assert(((n->req() - oopoff) & 1) == DERIVED,
931 "must match skip condition above");
932 n->add_req( derived_debug ); // this will be skipped above
933 n->add_req( n->in(inpidx+1) ); // this will be processed
934 // Increment cnt to handle added input edges on
935 // subsequent iterations.
936 cnt += 2;
937 }
938 }
939 }
940 continue;
941 }
942 // Special logic for DEBUG info
943 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
944 uint debug_start = jvms->debug_start();
945 // If this is debug info use & there is a reaching DOWN def
946 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
947 assert(inpidx < oopoff, "handle only debug info here");
948 // Just hook it in & move on
949 n->set_req(inpidx, debug_defs[slidx]);
950 // (Note that this can make two sides of a split live at the
951 // same time: The debug def on stack, and another def in a
952 // register. The GC needs to know about both of them, but any
953 // derived pointers after oopoff will refer to only one of the
954 // two defs and the GC would therefore miss the other. Thus
955 // this hack is only allowed for debug info which is Java state
956 // and therefore never a derived pointer.)
957 continue;
958 }
959 }
960 // Grab register mask info
961 const RegMask &dmask = def->out_RegMask();
962 const RegMask &umask = n->in_RegMask(inpidx);
963
964 assert(inpidx < oopoff, "cannot use-split oop map info");
965
966 bool dup = UPblock[slidx];
967 bool uup = umask.is_UP();
968
969 // Need special logic to handle bound USES. Insert a split at this
970 // bound use if we can't rematerialize the def, or if we need the
971 // split to form a misaligned pair.
972 if( !umask.is_AllStack() &&
973 (int)umask.Size() <= lrgs(useidx).num_regs() &&
974 (!def->rematerialize() ||
975 umask.is_misaligned_Pair())) {
976 // These need a Split regardless of overlap or pressure
977 // SPLIT - NO DEF - NO CISC SPILL
978 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
979 // If it wasn't split bail
980 if (!maxlrg) {
981 return 0;
982 }
983 insidx++; // Reset iterator to skip USE side split
984 continue;
985 }
986
987 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
988 // The use at the call can force the def down so insert
989 // a split before the use to allow the def more freedom.
990 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
991 // If it wasn't split bail
992 if (!maxlrg) {
993 return 0;
994 }
995 insidx++; // Reset iterator to skip USE side split
996 continue;
997 }
998
999 // Here is the logic chart which describes USE Splitting:
1000 // 0 = false or DOWN, 1 = true or UP
1001 //
1002 // Overlap | DEF | USE | Action
1003 //-------------------------------------------------------
1004 // 0 | 0 | 0 | Copy - mem -> mem
1005 // 0 | 0 | 1 | Split-UP - Check HRP
1006 // 0 | 1 | 0 | Split-DOWN - Debug Info?
1007 // 0 | 1 | 1 | Copy - reg -> reg
1008 // 1 | 0 | 0 | Reset Input Edge (no Split)
1009 // 1 | 0 | 1 | Split-UP - Check HRP
1010 // 1 | 1 | 0 | Split-DOWN - Debug Info?
1011 // 1 | 1 | 1 | Reset Input Edge (no Split)
1012 //
1013 // So, if (dup == uup), then overlap test determines action,
1014 // with true being no split, and false being copy. Else,
1015 // if DEF is DOWN, Split-UP, and check HRP to decide on
1016 // resetting DEF. Finally if DEF is UP, Split-DOWN, with
1017 // special handling for Debug Info.
1018 if( dup == uup ) {
1019 if( dmask.overlap(umask) ) {
1020 // Both are either up or down, and there is overlap, No Split
1021 n->set_req(inpidx, def);
1022 }
1023 else { // Both are either up or down, and there is no overlap
1024 if( dup ) { // If UP, reg->reg copy
1025 // COPY ACROSS HERE - NO DEF - NO CISC SPILL
1026 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1027 // If it wasn't split bail
1028 if (!maxlrg) {
1029 return 0;
1030 }
1031 insidx++; // Reset iterator to skip USE side split
1032 }
1033 else { // DOWN, mem->mem copy
1034 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
1035 // First Split-UP to move value into Register
1036 uint def_ideal = def->ideal_reg();
1037 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
1038 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm);
1039 insert_proj( b, insidx, spill, maxlrg );
1040 // Then Split-DOWN as if previous Split was DEF
1041 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
1042 // If it wasn't split bail
1043 if (!maxlrg) {
1044 return 0;
1045 }
1046 insidx += 2; // Reset iterator to skip USE side splits
1047 }
1048 } // End else no overlap
1049 } // End if dup == uup
1050 // dup != uup, so check dup for direction of Split
1051 else {
1052 if( dup ) { // If UP, Split-DOWN and check Debug Info
1053 // If this node is already a SpillCopy, just patch the edge
1054 // except the case of spilling to stack.
1055 if( n->is_SpillCopy() ) {
1056 RegMask tmp_rm(umask);
1057 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
1058 if( dmask.overlap(tmp_rm) ) {
1059 if( def != n->in(inpidx) ) {
1060 n->set_req(inpidx, def);
1061 }
1062 continue;
1063 }
1064 }
1065 // COPY DOWN HERE - NO DEF - NO CISC SPILL
1066 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1067 // If it wasn't split bail
1068 if (!maxlrg) {
1069 return 0;
1070 }
1071 insidx++; // Reset iterator to skip USE side split
1072 // Check for debug-info split. Capture it for later
1073 // debug splits of the same value
1074 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
1075 debug_defs[slidx] = n->in(inpidx);
1076
1077 }
1078 else { // DOWN, Split-UP and check register pressure
1079 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
1080 // COPY UP HERE - NO DEF - CISC SPILL
1081 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1082 // If it wasn't split bail
1083 if (!maxlrg) {
1084 return 0;
1085 }
1086 insidx++; // Reset iterator to skip USE side split
1087 } else { // LRP
1088 // COPY UP HERE - WITH DEF - NO CISC SPILL
1089 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1090 // If it wasn't split bail
1091 if (!maxlrg) {
1092 return 0;
1093 }
1094 // Flag this lift-up in a low-pressure block as
1095 // already-spilled, so if it spills again it will
1096 // spill hard (instead of not spilling hard and
1097 // coalescing away).
1098 set_was_spilled(n->in(inpidx));
1099 // Since this is a new DEF, update Reachblock & UP
1100 Reachblock[slidx] = n->in(inpidx);
1101 UPblock[slidx] = true;
1102 insidx++; // Reset iterator to skip USE side split
1103 }
1104 } // End else DOWN
1105 } // End dup != uup
1106 } // End if Spill USE
1107 } // End For All Inputs
1108 } // End If not nullcheck
1109
1110 // ********** Handle DEFS **********
1111 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1112 // just reset the Reaches info in LRP regions. DEFS must always update
1113 // UP info.
1114 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1115 uint slidx = lrg2reach[defidx];
1116 // Add to defs list for later assignment of new live range number
1117 defs->push(n);
1118 // Set a flag on the Node indicating it has already spilled.
1119 // Only do it for capacity spills not conflict spills.
1120 if( !deflrg._direct_conflict )
1121 set_was_spilled(n);
1122 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1123 // Grab UP info for DEF
1124 const RegMask &dmask = n->out_RegMask();
1125 bool defup = dmask.is_UP();
1126 // Only split at Def if this is a HRP block or bound (and spilled once)
1127 if( !n->rematerialize() &&
1128 (((dmask.is_bound1() || dmask.is_bound2() || dmask.is_misaligned_Pair()) &&
1129 (deflrg._direct_conflict || deflrg._must_spill)) ||
1130 // Check for LRG being up in a register and we are inside a high
1131 // pressure area. Spill it down immediately.
1132 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1133 assert( !n->rematerialize(), "" );
1134 assert( !n->is_SpillCopy(), "" );
1135 // Do a split at the def site.
1136 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1137 // If it wasn't split bail
1138 if (!maxlrg) {
1139 return 0;
1140 }
1141 // Split DEF's Down
1142 UPblock[slidx] = 0;
1143 #ifndef PRODUCT
1144 // DEBUG
1145 if( trace_spilling() ) {
1146 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1147 tty->print("%d, UP %d:\n",slidx,false);
1148 n->dump();
1149 }
1150 #endif
1151 }
1152 else { // Neither bound nor HRP, must be LRP
1153 // otherwise, just record the def
1154 Reachblock[slidx] = n;
1155 // UP should come from the outRegmask() of the DEF
1156 UPblock[slidx] = defup;
1157 // Update debug list of reaching down definitions, kill if DEF is UP
1158 debug_defs[slidx] = defup ? NULL : n;
1159 #ifndef PRODUCT
1160 // DEBUG
1161 if( trace_spilling() ) {
1162 tty->print("\nNew DEF of Spill Idx ");
1163 tty->print("%d, UP %d:\n",slidx,defup);
1164 n->dump();
1165 }
1166 #endif
1167 } // End else LRP
1168 } // End if spill def
1169
1170 // ********** Split Left Over Mem-Mem Moves **********
1171 // Check for mem-mem copies and split them now. Do not do this
1172 // to copies about to be spilled; they will be Split shortly.
1173 if( copyidx ) {
1174 Node *use = n->in(copyidx);
1175 uint useidx = Find_id(use);
1176 if( useidx < _maxlrg && // This is not a new split
1177 OptoReg::is_stack(deflrg.reg()) &&
1178 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
1179 LRG &uselrg = lrgs(useidx);
1180 if( OptoReg::is_stack(uselrg.reg()) &&
1181 uselrg.reg() < LRG::SPILL_REG && // USE is from stack
1182 deflrg.reg() != uselrg.reg() ) { // Not trivially removed
1183 uint def_ideal_reg = Matcher::base2reg[n->bottom_type()->base()];
1184 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
1185 const RegMask &use_rm = n->in_RegMask(copyidx);
1186 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL
1187 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes
1188 return 0;
1189 }
1190 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm);
1191 n->set_req(copyidx,spill);
1192 n->as_MachSpillCopy()->set_in_RegMask(def_rm);
1193 // Put the spill just before the copy
1194 insert_proj( b, insidx++, spill, maxlrg++ );
1195 }
1196 }
1197 }
1198 }
1199 } // End For All Instructions in Block - Non-PHI Pass
1200
1201 // Check if each LRG is live out of this block so as not to propagate
1202 // beyond the last use of a LRG.
1203 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1204 uint defidx = lidxs.at(slidx);
1205 IndexSet *liveout = _live->live(b);
1206 if( !liveout->member(defidx) ) {
1207 #ifdef ASSERT
1208 // The index defidx is not live. Check the liveout array to ensure that
1209 // it contains no members which compress to defidx. Finding such an
1210 // instance may be a case to add liveout adjustment in compress_uf_map().
1211 // See 5063219.
1212 uint member;
1213 IndexSetIterator isi(liveout);
1214 while ((member = isi.next()) != 0) {
1215 assert(defidx != Find_const(member), "Live out member has not been compressed");
1216 }
1217 #endif
1218 Reachblock[slidx] = NULL;
1219 } else {
1220 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
1221 }
1222 }
1223 #ifndef PRODUCT
1224 if( trace_spilling() )
1225 b->dump();
1226 #endif
1227 } // End For All Blocks
1228
1229 //----------PASS 2----------
1230 // Reset all DEF live range numbers here
1231 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1232 // Grab the def
1233 n1 = defs->at(insidx);
1234 // Set new lidx for DEF
1235 new_lrg(n1, maxlrg++);
1236 }
1237 //----------Phi Node Splitting----------
1238 // Clean up a phi here, and assign a new live range number
1239 // Cycle through this block's predecessors, collecting Reaches
1240 // info for each spilled LRG and update edges.
1241 // Walk the phis list to patch inputs, split phis, and name phis
1242 uint lrgs_before_phi_split = maxlrg;
1243 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1244 Node *phi = phis->at(insidx);
1245 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1246 Block *b = _cfg._bbs[phi->_idx];
1247 // Grab the live range number
1248 uint lidx = Find_id(phi);
1249 uint slidx = lrg2reach[lidx];
1250 // Update node to lidx map
1251 new_lrg(phi, maxlrg++);
1252 // Get PASS1's up/down decision for the block.
1253 int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
1254
1255 // Force down if double-spilling live range
1256 if( lrgs(lidx)._was_spilled1 )
1257 phi_up = false;
1258
1259 // When splitting a Phi we an split it normal or "inverted".
1260 // An inverted split makes the splits target the Phi's UP/DOWN
1261 // sense inverted; then the Phi is followed by a final def-side
1262 // split to invert back. It changes which blocks the spill code
1263 // goes in.
1264
1265 // Walk the predecessor blocks and assign the reaching def to the Phi.
1266 // Split Phi nodes by placing USE side splits wherever the reaching
1267 // DEF has the wrong UP/DOWN value.
1268 for( uint i = 1; i < b->num_preds(); i++ ) {
1269 // Get predecessor block pre-order number
1270 Block *pred = _cfg._bbs[b->pred(i)->_idx];
1271 pidx = pred->_pre_order;
1272 // Grab reaching def
1273 Node *def = Reaches[pidx][slidx];
1274 assert( def, "must have reaching def" );
1275 // If input up/down sense and reg-pressure DISagree
1276 if( def->rematerialize() ) {
1277 // Place the rematerialized node above any MSCs created during
1278 // phi node splitting. end_idx points at the insertion point
1279 // so look at the node before it.
1280 int insert = pred->end_idx();
1281 while (insert >= 1 &&
1282 pred->_nodes[insert - 1]->is_SpillCopy() &&
1283 Find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) {
1284 insert--;
1285 }
1286 def = split_Rematerialize( def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false );
1287 if( !def ) return 0; // Bail out
1288 }
1289 // Update the Phi's input edge array
1290 phi->set_req(i,def);
1291 // Grab the UP/DOWN sense for the input
1292 u1 = UP[pidx][slidx];
1293 if( u1 != (phi_up != 0)) {
1294 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1295 // If it wasn't split bail
1296 if (!maxlrg) {
1297 return 0;
1298 }
1299 }
1300 } // End for all inputs to the Phi
1301 } // End for all Phi Nodes
1302 // Update _maxlrg to save Union asserts
1303 _maxlrg = maxlrg;
1304
1305
1306 //----------PASS 3----------
1307 // Pass over all Phi's to union the live ranges
1308 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1309 Node *phi = phis->at(insidx);
1310 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1311 // Walk all inputs to Phi and Union input live range with Phi live range
1312 for( uint i = 1; i < phi->req(); i++ ) {
1313 // Grab the input node
1314 Node *n = phi->in(i);
1315 assert( n, "" );
1316 uint lidx = Find(n);
1317 uint pidx = Find(phi);
1318 if( lidx < pidx )
1319 Union(n, phi);
1320 else if( lidx > pidx )
1321 Union(phi, n);
1322 } // End for all inputs to the Phi Node
1323 } // End for all Phi Nodes
1324 // Now union all two address instructions
1325 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1326 // Grab the def
1327 n1 = defs->at(insidx);
1328 // Set new lidx for DEF & handle 2-addr instructions
1329 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) {
1330 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1331 // Union the input and output live ranges
1332 uint lr1 = Find(n1);
1333 uint lr2 = Find(n1->in(twoidx));
1334 if( lr1 < lr2 )
1335 Union(n1, n1->in(twoidx));
1336 else if( lr1 > lr2 )
1337 Union(n1->in(twoidx), n1);
1338 } // End if two address
1339 } // End for all defs
1340 // DEBUG
1341 #ifdef ASSERT
1342 // Validate all live range index assignments
1343 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
1344 b = _cfg._blocks[bidx];
1345 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) {
1346 Node *n = b->_nodes[insidx];
1347 uint defidx = Find(n);
1348 assert(defidx < _maxlrg,"Bad live range index in Split");
1349 assert(defidx < maxlrg,"Bad live range index in Split");
1350 }
1351 }
1352 // Issue a warning if splitting made no progress
1353 int noprogress = 0;
1354 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1355 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) {
1356 tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
1357 //BREAKPOINT;
1358 }
1359 else {
1360 noprogress++;
1361 }
1362 }
1363 if(!noprogress) {
1364 tty->print_cr("Failed to make progress in Split");
1365 //BREAKPOINT;
1366 }
1367 #endif
1368 // Return updated count of live ranges
1369 return maxlrg;
1370 }