src/cpu/sparc/vm/sparc.ad

*** 469,481 ****
  %}
  
  source %{
  #define __ _masm.
  
- // Block initializing store
- #define ASI_BLK_INIT_QUAD_LDD_P    0xE2
- 
  // tertiary op of a LoadP or StoreP encoding
  #define REGP_OP true
  
  static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
  static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
--- 469,478 ----
*** 6267,6312 ****
  // Must be safe to execute with invalid address (cannot fault).
  
  instruct prefetchr( memory mem ) %{
    match( PrefetchRead mem );
    ins_cost(MEMORY_REF_COST);
  
    format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
    opcode(Assembler::prefetch_op3);
    ins_encode( form3_mem_prefetch_read( mem ) );
    ins_pipe(iload_mem);
  %}
  
  instruct prefetchw( memory mem ) %{
-   predicate(AllocatePrefetchStyle != 3 );
    match( PrefetchWrite mem );
    ins_cost(MEMORY_REF_COST);
  
    format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
    opcode(Assembler::prefetch_op3);
    ins_encode( form3_mem_prefetch_write( mem ) );
    ins_pipe(iload_mem);
  %}
  
! // Use BIS instruction to prefetch.
! instruct prefetchw_bis( memory mem ) %{
!   predicate(AllocatePrefetchStyle == 3);
!   match( PrefetchWrite mem );
    ins_cost(MEMORY_REF_COST);
  
!   format %{ "STXA   G0,$mem\t! // Block initializing store" %}
    ins_encode %{
!      Register base = as_Register($mem$$base);
!      int disp = $mem$$disp;
!      if (disp != 0) {
!        __ add(base, AllocatePrefetchStepSize, base);
!      }
!      __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
    %}
    ins_pipe(istore_mem_reg);
  %}
  
  //----------Store Instructions-------------------------------------------------
  // Store Byte
  instruct storeB(memory mem, iRegI src) %{
    match(Set mem (StoreB mem src));
    ins_cost(MEMORY_REF_COST);
--- 6264,6347 ----
  // Must be safe to execute with invalid address (cannot fault).
  
  instruct prefetchr( memory mem ) %{
    match( PrefetchRead mem );
    ins_cost(MEMORY_REF_COST);
+   size(4);
  
    format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
    opcode(Assembler::prefetch_op3);
    ins_encode( form3_mem_prefetch_read( mem ) );
    ins_pipe(iload_mem);
  %}
  
  instruct prefetchw( memory mem ) %{
    match( PrefetchWrite mem );
    ins_cost(MEMORY_REF_COST);
+   size(4);
  
    format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
    opcode(Assembler::prefetch_op3);
    ins_encode( form3_mem_prefetch_write( mem ) );
    ins_pipe(iload_mem);
  %}
  
! // Prefetch instructions for allocation.
! 
! instruct prefetchAlloc( memory mem ) %{
!   predicate(AllocatePrefetchInstr == 0);
!   match( PrefetchAllocation mem );
    ins_cost(MEMORY_REF_COST);
+   size(4);
  
!   format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
!   opcode(Assembler::prefetch_op3);
!   ins_encode( form3_mem_prefetch_write( mem ) );
!   ins_pipe(iload_mem);
! %}
! 
! // Use BIS instruction to prefetch for allocation.
! // Could fault, need space at the end of TLAB.
! instruct prefetchAlloc_bis( iRegP dst ) %{
!   predicate(AllocatePrefetchInstr == 1);
!   match( PrefetchAllocation dst );
!   ins_cost(MEMORY_REF_COST);
!   size(4);
! 
!   format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
    ins_encode %{
!     __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
    %}
    ins_pipe(istore_mem_reg);
  %}
  
+ // Next code is used for finding next cache line address to prefetch.
+ 
+ instruct cacheLineAdr32( iRegP dst, iRegP src, immI13 mask ) %{
+   match(Set dst (CastX2P (AndI (CastP2X src) mask)));
+   ins_cost(DEFAULT_COST);
+   size(4);
+ 
+   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
+   ins_encode %{
+     __ and3($src$$Register, $mask$$constant, $dst$$Register);
+   %}
+   ins_pipe(ialu_reg_imm);
+ %}
+ 
+ instruct cacheLineAdr64( iRegP dst, iRegP src, immL13 mask ) %{
+   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
+   ins_cost(DEFAULT_COST);
+   size(4);
+ 
+   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
+   ins_encode %{
+     __ and3($src$$Register, $mask$$constant, $dst$$Register);
+   %}
+   ins_pipe(ialu_reg_imm);
+ %}
+ 
  //----------Store Instructions-------------------------------------------------
  // Store Byte
  instruct storeB(memory mem, iRegI src) %{
    match(Set mem (StoreB mem src));
    ins_cost(MEMORY_REF_COST);