454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
6252
6253 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6254 match(Set dst con);
6255 effect(KILL tmp);
6256 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6257 ins_encode %{
6258 // XXX This is a quick fix for 6833573.
6259 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6260 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6261 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6262 %}
6263 ins_pipe(loadConFD);
6264 %}
6265
6266 // Prefetch instructions.
6267 // Must be safe to execute with invalid address (cannot fault).
6268
6269 instruct prefetchr( memory mem ) %{
6270 match( PrefetchRead mem );
6271 ins_cost(MEMORY_REF_COST);
6272
6273 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6274 opcode(Assembler::prefetch_op3);
6275 ins_encode( form3_mem_prefetch_read( mem ) );
6276 ins_pipe(iload_mem);
6277 %}
6278
6279 instruct prefetchw( memory mem ) %{
6280 predicate(AllocatePrefetchStyle != 3 );
6281 match( PrefetchWrite mem );
6282 ins_cost(MEMORY_REF_COST);
6283
6284 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6285 opcode(Assembler::prefetch_op3);
6286 ins_encode( form3_mem_prefetch_write( mem ) );
6287 ins_pipe(iload_mem);
6288 %}
6289
6290 // Use BIS instruction to prefetch.
6291 instruct prefetchw_bis( memory mem ) %{
6292 predicate(AllocatePrefetchStyle == 3);
6293 match( PrefetchWrite mem );
6294 ins_cost(MEMORY_REF_COST);
6295
6296 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6297 ins_encode %{
6298 Register base = as_Register($mem$$base);
6299 int disp = $mem$$disp;
6300 if (disp != 0) {
6301 __ add(base, AllocatePrefetchStepSize, base);
6302 }
6303 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6304 %}
6305 ins_pipe(istore_mem_reg);
6306 %}
6307
6308 //----------Store Instructions-------------------------------------------------
6309 // Store Byte
6310 instruct storeB(memory mem, iRegI src) %{
6311 match(Set mem (StoreB mem src));
6312 ins_cost(MEMORY_REF_COST);
6313
6314 size(4);
6315 format %{ "STB $src,$mem\t! byte" %}
6316 opcode(Assembler::stb_op3);
6317 ins_encode(simple_form3_mem_reg( mem, src ) );
6318 ins_pipe(istore_mem_reg);
6319 %}
6320
6321 instruct storeB0(memory mem, immI0 src) %{
6322 match(Set mem (StoreB mem src));
6323 ins_cost(MEMORY_REF_COST);
6324
6325 size(4);
6326 format %{ "STB $src,$mem\t! byte" %}
6327 opcode(Assembler::stb_op3);
|
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
476
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
480
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
6249
6250 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6251 match(Set dst con);
6252 effect(KILL tmp);
6253 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6254 ins_encode %{
6255 // XXX This is a quick fix for 6833573.
6256 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6257 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6258 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6259 %}
6260 ins_pipe(loadConFD);
6261 %}
6262
6263 // Prefetch instructions.
6264 // Must be safe to execute with invalid address (cannot fault).
6265
6266 instruct prefetchr( memory mem ) %{
6267 match( PrefetchRead mem );
6268 ins_cost(MEMORY_REF_COST);
6269 size(4);
6270
6271 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6272 opcode(Assembler::prefetch_op3);
6273 ins_encode( form3_mem_prefetch_read( mem ) );
6274 ins_pipe(iload_mem);
6275 %}
6276
6277 instruct prefetchw( memory mem ) %{
6278 match( PrefetchWrite mem );
6279 ins_cost(MEMORY_REF_COST);
6280 size(4);
6281
6282 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6283 opcode(Assembler::prefetch_op3);
6284 ins_encode( form3_mem_prefetch_write( mem ) );
6285 ins_pipe(iload_mem);
6286 %}
6287
6288 // Prefetch instructions for allocation.
6289
6290 instruct prefetchAlloc( memory mem ) %{
6291 predicate(AllocatePrefetchInstr == 0);
6292 match( PrefetchAllocation mem );
6293 ins_cost(MEMORY_REF_COST);
6294 size(4);
6295
6296 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6297 opcode(Assembler::prefetch_op3);
6298 ins_encode( form3_mem_prefetch_write( mem ) );
6299 ins_pipe(iload_mem);
6300 %}
6301
6302 // Use BIS instruction to prefetch for allocation.
6303 // Could fault, need space at the end of TLAB.
6304 instruct prefetchAlloc_bis( iRegP dst ) %{
6305 predicate(AllocatePrefetchInstr == 1);
6306 match( PrefetchAllocation dst );
6307 ins_cost(MEMORY_REF_COST);
6308 size(4);
6309
6310 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6311 ins_encode %{
6312 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6313 %}
6314 ins_pipe(istore_mem_reg);
6315 %}
6316
6317 // Next code is used for finding next cache line address to prefetch.
6318
6319 instruct cacheLineAdr32( iRegP dst, iRegP src, immI13 mask ) %{
6320 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6321 ins_cost(DEFAULT_COST);
6322 size(4);
6323
6324 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6325 ins_encode %{
6326 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6327 %}
6328 ins_pipe(ialu_reg_imm);
6329 %}
6330
6331 instruct cacheLineAdr64( iRegP dst, iRegP src, immL13 mask ) %{
6332 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6333 ins_cost(DEFAULT_COST);
6334 size(4);
6335
6336 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6337 ins_encode %{
6338 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6339 %}
6340 ins_pipe(ialu_reg_imm);
6341 %}
6342
6343 //----------Store Instructions-------------------------------------------------
6344 // Store Byte
6345 instruct storeB(memory mem, iRegI src) %{
6346 match(Set mem (StoreB mem src));
6347 ins_cost(MEMORY_REF_COST);
6348
6349 size(4);
6350 format %{ "STB $src,$mem\t! byte" %}
6351 opcode(Assembler::stb_op3);
6352 ins_encode(simple_form3_mem_reg( mem, src ) );
6353 ins_pipe(istore_mem_reg);
6354 %}
6355
6356 instruct storeB0(memory mem, immI0 src) %{
6357 match(Set mem (StoreB mem src));
6358 ins_cost(MEMORY_REF_COST);
6359
6360 size(4);
6361 format %{ "STB $src,$mem\t! byte" %}
6362 opcode(Assembler::stb_op3);
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