1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "assembler_sparc.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_sparc.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37
38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = "";
40
41 void VM_Version::initialize() {
42 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 PrefetchFieldsAhead = prefetch_fields_ahead();
46
47 // Allocation prefetch settings
48 intx cache_line_size = L1_data_cache_line_size();
49 if( cache_line_size > AllocatePrefetchStepSize )
50 AllocatePrefetchStepSize = cache_line_size;
51 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
52 AllocatePrefetchLines = 3; // Optimistic value
53 assert( AllocatePrefetchLines > 0, "invalid value");
54 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
55 AllocatePrefetchLines = 1; // Conservative value
56
57 AllocatePrefetchDistance = allocate_prefetch_distance();
58 AllocatePrefetchStyle = allocate_prefetch_style();
59
60 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
61
62 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
63 warning("BIS instructions are not available on this CPU");
64 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
65 }
66
67 UseSSE = 0; // Only on x86 and x64
68
69 _supports_cx8 = has_v9();
70
71 if (is_niagara()) {
72 // Indirect branch is the same cost as direct
73 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
74 FLAG_SET_DEFAULT(UseInlineCaches, false);
75 }
76 // Align loops on a single instruction boundary.
77 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
78 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
79 }
80 // When using CMS, we cannot use memset() in BOT updates because
81 // the sun4v/CMT version in libc_psr uses BIS which exposes
82 // "phantom zeros" to concurrent readers. See 6948537.
83 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
84 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
85 }
86 #ifdef _LP64
87 // 32-bit oops don't make sense for the 64-bit VM on sparc
88 // since the 32-bit VM has the same registers and smaller objects.
89 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
90 #endif // _LP64
91 #ifdef COMPILER2
92 // Indirect branch is the same cost as direct
93 if (FLAG_IS_DEFAULT(UseJumpTables)) {
94 FLAG_SET_DEFAULT(UseJumpTables, true);
95 }
96 // Single-issue, so entry and loop tops are
97 // aligned on a single instruction boundary
98 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
99 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
100 }
101 if (is_niagara_plus()) {
102 if (has_blk_init() && AllocatePrefetchStyle > 0 &&
103 FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
104 // Use BIS instruction for allocation prefetch.
105 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
106 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
107 // Use smaller prefetch distance on N2 with BIS
108 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
109 }
110 }
111 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
112 // Use different prefetch distance without BIS
113 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
114 }
115 }
116 #endif
117 }
118
119 // Use hardware population count instruction if available.
120 if (has_hardware_popc()) {
121 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
122 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
123 }
124 } else if (UsePopCountInstruction) {
125 warning("POPC instruction is not available on this CPU");
126 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
127 }
128
129 // T4 and newer Sparc cpus have new compare and branch instruction.
130 if (has_cbcond()) {
131 if (FLAG_IS_DEFAULT(UseCBCond)) {
132 FLAG_SET_DEFAULT(UseCBCond, true);
133 }
134 } else if (UseCBCond) {
135 warning("CBCOND instruction is not available on this CPU");
136 FLAG_SET_DEFAULT(UseCBCond, false);
137 }
138
139 #ifdef COMPILER2
140 // T4 and newer Sparc cpus have fast RDPC.
141 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
142 // FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
143 }
144
145 // Currently not supported anywhere.
146 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
147
148 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
149 #endif
150
151 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
152 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
153
154 char buf[512];
155 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
156 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
157 (has_hardware_popc() ? ", popc" : ""),
158 (has_vis1() ? ", vis1" : ""),
159 (has_vis2() ? ", vis2" : ""),
160 (has_vis3() ? ", vis3" : ""),
161 (has_blk_init() ? ", blk_init" : ""),
162 (has_cbcond() ? ", cbcond" : ""),
163 (is_ultra3() ? ", ultra3" : ""),
164 (is_sun4v() ? ", sun4v" : ""),
165 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
166 (is_sparc64() ? ", sparc64" : ""),
167 (!has_hardware_mul32() ? ", no-mul32" : ""),
168 (!has_hardware_div32() ? ", no-div32" : ""),
169 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
170
171 // buf is started with ", " or is empty
172 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
173
174 // UseVIS is set to the smallest of what hardware supports and what
175 // the command line requires. I.e., you cannot set UseVIS to 3 on
176 // older UltraSparc which do not support it.
177 if (UseVIS > 3) UseVIS=3;
178 if (UseVIS < 0) UseVIS=0;
179 if (!has_vis3()) // Drop to 2 if no VIS3 support
180 UseVIS = MIN2((intx)2,UseVIS);
181 if (!has_vis2()) // Drop to 1 if no VIS2 support
182 UseVIS = MIN2((intx)1,UseVIS);
183 if (!has_vis1()) // Drop to 0 if no VIS1 support
184 UseVIS = 0;
185
186 #ifndef PRODUCT
187 if (PrintMiscellaneous && Verbose) {
188 tty->print("Allocation: ");
189 if (AllocatePrefetchStyle <= 0) {
190 tty->print_cr("no prefetching");
191 } else {
192 if (AllocatePrefetchLines > 1) {
193 tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
194 } else {
195 tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance);
196 }
197 }
198 if (PrefetchCopyIntervalInBytes > 0) {
199 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
200 }
201 if (PrefetchScanIntervalInBytes > 0) {
202 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
203 }
204 if (PrefetchFieldsAhead > 0) {
205 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
206 }
207 }
208 #endif // PRODUCT
209 }
210
211 void VM_Version::print_features() {
212 tty->print_cr("Version:%s", cpu_features());
213 }
214
215 int VM_Version::determine_features() {
216 if (UseV8InstrsOnly) {
217 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
218 return generic_v8_m;
219 }
220
221 int features = platform_features(unknown_m); // platform_features() is os_arch specific
222
223 if (features == unknown_m) {
224 features = generic_v9_m;
225 warning("Cannot recognize SPARC version. Default to V9");
226 }
227
228 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
229 if (UseNiagaraInstrs) { // Force code generation for Niagara
230 if (is_T_family(features)) {
231 // Happy to accomodate...
232 } else {
233 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
234 features |= T_family_m;
235 }
236 } else {
237 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
238 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
239 features &= ~(T_family_m | T1_model_m);
240 } else {
241 // Happy to accomodate...
242 }
243 }
244
245 return features;
246 }
247
248 static int saved_features = 0;
249
250 void VM_Version::allow_all() {
251 saved_features = _features;
252 _features = all_features_m;
253 }
254
255 void VM_Version::revert() {
256 _features = saved_features;
257 }
258
259 unsigned int VM_Version::calc_parallel_worker_threads() {
260 unsigned int result;
261 if (is_niagara_plus()) {
262 result = nof_parallel_worker_threads(5, 16, 8);
263 } else {
264 result = nof_parallel_worker_threads(5, 8, 8);
265 }
266 return result;
267 }