7308
7309 // Prefetch instructions.
7310 // Must be safe to execute with invalid address (cannot fault).
7311
7312 instruct prefetchr0( memory mem ) %{
7313 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7314 match(PrefetchRead mem);
7315 ins_cost(0);
7316 size(0);
7317 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7318 ins_encode();
7319 ins_pipe(empty);
7320 %}
7321
7322 instruct prefetchr( memory mem ) %{
7323 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7324 match(PrefetchRead mem);
7325 ins_cost(100);
7326
7327 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7328 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7329 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7330 ins_pipe(ialu_mem);
7331 %}
7332
7333 instruct prefetchrNTA( memory mem ) %{
7334 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7335 match(PrefetchRead mem);
7336 ins_cost(100);
7337
7338 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7339 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7340 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7341 ins_pipe(ialu_mem);
7342 %}
7343
7344 instruct prefetchrT0( memory mem ) %{
7345 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7346 match(PrefetchRead mem);
7347 ins_cost(100);
7348
7349 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7350 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7351 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7352 ins_pipe(ialu_mem);
7353 %}
7354
7355 instruct prefetchrT2( memory mem ) %{
7356 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7357 match(PrefetchRead mem);
7358 ins_cost(100);
7359
7360 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7361 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7362 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7363 ins_pipe(ialu_mem);
7364 %}
7365
7366 instruct prefetchw0( memory mem ) %{
7367 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7368 match(PrefetchWrite mem);
7369 ins_cost(0);
7370 size(0);
7371 format %{ "Prefetch (non-SSE is empty encoding)" %}
7372 ins_encode();
7373 ins_pipe(empty);
7374 %}
7375
7376 instruct prefetchw( memory mem ) %{
7377 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || AllocatePrefetchInstr==3);
7378 match( PrefetchWrite mem );
7379 ins_cost(100);
7380
7381 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7382 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7383 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7384 ins_pipe(ialu_mem);
7385 %}
7386
7387 instruct prefetchwNTA( memory mem ) %{
7388 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7389 match(PrefetchWrite mem);
7390 ins_cost(100);
7391
7392 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7393 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7394 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7395 ins_pipe(ialu_mem);
7396 %}
7397
7398 instruct prefetchwT0( memory mem ) %{
7399 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7400 match(PrefetchWrite mem);
7401 ins_cost(100);
7402
7403 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7404 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7405 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7406 ins_pipe(ialu_mem);
7407 %}
7408
7409 instruct prefetchwT2( memory mem ) %{
7410 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7411 match(PrefetchWrite mem);
7412 ins_cost(100);
7413
7414 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7415 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7416 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7417 ins_pipe(ialu_mem);
7418 %}
7419
7420 //----------Store Instructions-------------------------------------------------
7421
7422 // Store Byte
7423 instruct storeB(memory mem, xRegI src) %{
7424 match(Set mem (StoreB mem src));
7425
7426 ins_cost(125);
7427 format %{ "MOV8 $mem,$src" %}
7428 opcode(0x88);
7429 ins_encode( OpcP, RegMem( src, mem ) );
7430 ins_pipe( ialu_mem_reg );
7431 %}
7432
7433 // Store Char/Short
7434 instruct storeC(memory mem, eRegI src) %{
7435 match(Set mem (StoreC mem src));
7436
|
7308
7309 // Prefetch instructions.
7310 // Must be safe to execute with invalid address (cannot fault).
7311
7312 instruct prefetchr0( memory mem ) %{
7313 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7314 match(PrefetchRead mem);
7315 ins_cost(0);
7316 size(0);
7317 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7318 ins_encode();
7319 ins_pipe(empty);
7320 %}
7321
7322 instruct prefetchr( memory mem ) %{
7323 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7324 match(PrefetchRead mem);
7325 ins_cost(100);
7326
7327 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7328 ins_encode %{
7329 __ prefetchr($mem$$Address);
7330 %}
7331 ins_pipe(ialu_mem);
7332 %}
7333
7334 instruct prefetchrNTA( memory mem ) %{
7335 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7336 match(PrefetchRead mem);
7337 ins_cost(100);
7338
7339 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7340 ins_encode %{
7341 __ prefetchnta($mem$$Address);
7342 %}
7343 ins_pipe(ialu_mem);
7344 %}
7345
7346 instruct prefetchrT0( memory mem ) %{
7347 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7348 match(PrefetchRead mem);
7349 ins_cost(100);
7350
7351 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7352 ins_encode %{
7353 __ prefetcht0($mem$$Address);
7354 %}
7355 ins_pipe(ialu_mem);
7356 %}
7357
7358 instruct prefetchrT2( memory mem ) %{
7359 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7360 match(PrefetchRead mem);
7361 ins_cost(100);
7362
7363 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7364 ins_encode %{
7365 __ prefetcht2($mem$$Address);
7366 %}
7367 ins_pipe(ialu_mem);
7368 %}
7369
7370 instruct prefetchw0( memory mem ) %{
7371 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7372 match(PrefetchWrite mem);
7373 ins_cost(0);
7374 size(0);
7375 format %{ "Prefetch (non-SSE is empty encoding)" %}
7376 ins_encode();
7377 ins_pipe(empty);
7378 %}
7379
7380 instruct prefetchw( memory mem ) %{
7381 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
7382 match( PrefetchWrite mem );
7383 ins_cost(100);
7384
7385 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7386 ins_encode %{
7387 __ prefetchw($mem$$Address);
7388 %}
7389 ins_pipe(ialu_mem);
7390 %}
7391
7392 instruct prefetchwNTA( memory mem ) %{
7393 predicate(UseSSE>=1);
7394 match(PrefetchWrite mem);
7395 ins_cost(100);
7396
7397 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7398 ins_encode %{
7399 __ prefetchnta($mem$$Address);
7400 %}
7401 ins_pipe(ialu_mem);
7402 %}
7403
7404 // Prefetch instructions for allocation.
7405
7406 instruct prefetchAlloc0( memory mem ) %{
7407 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
7408 match(PrefetchAllocation mem);
7409 ins_cost(0);
7410 size(0);
7411 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
7412 ins_encode();
7413 ins_pipe(empty);
7414 %}
7415
7416 instruct prefetchAlloc( memory mem ) %{
7417 predicate(AllocatePrefetchInstr==3);
7418 match( PrefetchAllocation mem );
7419 ins_cost(100);
7420
7421 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
7422 ins_encode %{
7423 __ prefetchw($mem$$Address);
7424 %}
7425 ins_pipe(ialu_mem);
7426 %}
7427
7428 instruct prefetchAllocNTA( memory mem ) %{
7429 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7430 match(PrefetchAllocation mem);
7431 ins_cost(100);
7432
7433 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
7434 ins_encode %{
7435 __ prefetchnta($mem$$Address);
7436 %}
7437 ins_pipe(ialu_mem);
7438 %}
7439
7440 instruct prefetchAllocT0( memory mem ) %{
7441 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7442 match(PrefetchAllocation mem);
7443 ins_cost(100);
7444
7445 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
7446 ins_encode %{
7447 __ prefetcht0($mem$$Address);
7448 %}
7449 ins_pipe(ialu_mem);
7450 %}
7451
7452 instruct prefetchAllocT2( memory mem ) %{
7453 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7454 match(PrefetchAllocation mem);
7455 ins_cost(100);
7456
7457 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
7458 ins_encode %{
7459 __ prefetcht2($mem$$Address);
7460 %}
7461 ins_pipe(ialu_mem);
7462 %}
7463
7464 //----------Store Instructions-------------------------------------------------
7465
7466 // Store Byte
7467 instruct storeB(memory mem, xRegI src) %{
7468 match(Set mem (StoreB mem src));
7469
7470 ins_cost(125);
7471 format %{ "MOV8 $mem,$src" %}
7472 opcode(0x88);
7473 ins_encode( OpcP, RegMem( src, mem ) );
7474 ins_pipe( ialu_mem_reg );
7475 %}
7476
7477 // Store Char/Short
7478 instruct storeC(memory mem, eRegI src) %{
7479 match(Set mem (StoreC mem src));
7480
|