6600 %{
6601 match(Set dst src);
6602
6603 ins_cost(125);
6604 format %{ "movsd $dst, $src\t# double stk" %}
6605 ins_encode %{
6606 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6607 %}
6608 ins_pipe(pipe_slow); // XXX
6609 %}
6610
6611 // Prefetch instructions.
6612 // Must be safe to execute with invalid address (cannot fault).
6613
6614 instruct prefetchr( memory mem ) %{
6615 predicate(ReadPrefetchInstr==3);
6616 match(PrefetchRead mem);
6617 ins_cost(125);
6618
6619 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6620 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6621 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6622 ins_pipe(ialu_mem);
6623 %}
6624
6625 instruct prefetchrNTA( memory mem ) %{
6626 predicate(ReadPrefetchInstr==0);
6627 match(PrefetchRead mem);
6628 ins_cost(125);
6629
6630 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6631 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6632 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6633 ins_pipe(ialu_mem);
6634 %}
6635
6636 instruct prefetchrT0( memory mem ) %{
6637 predicate(ReadPrefetchInstr==1);
6638 match(PrefetchRead mem);
6639 ins_cost(125);
6640
6641 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6642 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6643 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6644 ins_pipe(ialu_mem);
6645 %}
6646
6647 instruct prefetchrT2( memory mem ) %{
6648 predicate(ReadPrefetchInstr==2);
6649 match(PrefetchRead mem);
6650 ins_cost(125);
6651
6652 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6653 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6654 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6655 ins_pipe(ialu_mem);
6656 %}
6657
6658 instruct prefetchw( memory mem ) %{
6659 predicate(AllocatePrefetchInstr==3);
6660 match(PrefetchWrite mem);
6661 ins_cost(125);
6662
6663 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6664 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6665 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6666 ins_pipe(ialu_mem);
6667 %}
6668
6669 instruct prefetchwNTA( memory mem ) %{
6670 predicate(AllocatePrefetchInstr==0);
6671 match(PrefetchWrite mem);
6672 ins_cost(125);
6673
6674 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6675 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6676 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6677 ins_pipe(ialu_mem);
6678 %}
6679
6680 instruct prefetchwT0( memory mem ) %{
6681 predicate(AllocatePrefetchInstr==1);
6682 match(PrefetchWrite mem);
6683 ins_cost(125);
6684
6685 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6686 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6687 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6688 ins_pipe(ialu_mem);
6689 %}
6690
6691 instruct prefetchwT2( memory mem ) %{
6692 predicate(AllocatePrefetchInstr==2);
6693 match(PrefetchWrite mem);
6694 ins_cost(125);
6695
6696 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6697 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6698 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6699 ins_pipe(ialu_mem);
6700 %}
6701
6702 //----------Store Instructions-------------------------------------------------
6703
6704 // Store Byte
6705 instruct storeB(memory mem, rRegI src)
6706 %{
6707 match(Set mem (StoreB mem src));
6708
6709 ins_cost(125); // XXX
6710 format %{ "movb $mem, $src\t# byte" %}
6711 opcode(0x88);
6712 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6713 ins_pipe(ialu_mem_reg);
6714 %}
6715
6716 // Store Char/Short
6717 instruct storeC(memory mem, rRegI src)
6718 %{
|
6600 %{
6601 match(Set dst src);
6602
6603 ins_cost(125);
6604 format %{ "movsd $dst, $src\t# double stk" %}
6605 ins_encode %{
6606 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6607 %}
6608 ins_pipe(pipe_slow); // XXX
6609 %}
6610
6611 // Prefetch instructions.
6612 // Must be safe to execute with invalid address (cannot fault).
6613
6614 instruct prefetchr( memory mem ) %{
6615 predicate(ReadPrefetchInstr==3);
6616 match(PrefetchRead mem);
6617 ins_cost(125);
6618
6619 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6620 ins_encode %{
6621 __ prefetchr($mem$$Address);
6622 %}
6623 ins_pipe(ialu_mem);
6624 %}
6625
6626 instruct prefetchrNTA( memory mem ) %{
6627 predicate(ReadPrefetchInstr==0);
6628 match(PrefetchRead mem);
6629 ins_cost(125);
6630
6631 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6632 ins_encode %{
6633 __ prefetchnta($mem$$Address);
6634 %}
6635 ins_pipe(ialu_mem);
6636 %}
6637
6638 instruct prefetchrT0( memory mem ) %{
6639 predicate(ReadPrefetchInstr==1);
6640 match(PrefetchRead mem);
6641 ins_cost(125);
6642
6643 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6644 ins_encode %{
6645 __ prefetcht0($mem$$Address);
6646 %}
6647 ins_pipe(ialu_mem);
6648 %}
6649
6650 instruct prefetchrT2( memory mem ) %{
6651 predicate(ReadPrefetchInstr==2);
6652 match(PrefetchRead mem);
6653 ins_cost(125);
6654
6655 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6656 ins_encode %{
6657 __ prefetcht2($mem$$Address);
6658 %}
6659 ins_pipe(ialu_mem);
6660 %}
6661
6662 instruct prefetchwNTA( memory mem ) %{
6663 match(PrefetchWrite mem);
6664 ins_cost(125);
6665
6666 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6667 ins_encode %{
6668 __ prefetchnta($mem$$Address);
6669 %}
6670 ins_pipe(ialu_mem);
6671 %}
6672
6673 // Prefetch instructions for allocation.
6674
6675 instruct prefetchAlloc( memory mem ) %{
6676 predicate(AllocatePrefetchInstr==3);
6677 match(PrefetchAllocation mem);
6678 ins_cost(125);
6679
6680 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6681 ins_encode %{
6682 __ prefetchw($mem$$Address);
6683 %}
6684 ins_pipe(ialu_mem);
6685 %}
6686
6687 instruct prefetchAllocNTA( memory mem ) %{
6688 predicate(AllocatePrefetchInstr==0);
6689 match(PrefetchAllocation mem);
6690 ins_cost(125);
6691
6692 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6693 ins_encode %{
6694 __ prefetchnta($mem$$Address);
6695 %}
6696 ins_pipe(ialu_mem);
6697 %}
6698
6699 instruct prefetchAllocT0( memory mem ) %{
6700 predicate(AllocatePrefetchInstr==1);
6701 match(PrefetchAllocation mem);
6702 ins_cost(125);
6703
6704 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6705 ins_encode %{
6706 __ prefetcht0($mem$$Address);
6707 %}
6708 ins_pipe(ialu_mem);
6709 %}
6710
6711 instruct prefetchAllocT2( memory mem ) %{
6712 predicate(AllocatePrefetchInstr==2);
6713 match(PrefetchAllocation mem);
6714 ins_cost(125);
6715
6716 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6717 ins_encode %{
6718 __ prefetcht2($mem$$Address);
6719 %}
6720 ins_pipe(ialu_mem);
6721 %}
6722
6723 //----------Store Instructions-------------------------------------------------
6724
6725 // Store Byte
6726 instruct storeB(memory mem, rRegI src)
6727 %{
6728 match(Set mem (StoreB mem src));
6729
6730 ins_cost(125); // XXX
6731 format %{ "movb $mem, $src\t# byte" %}
6732 opcode(0x88);
6733 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6734 ins_pipe(ialu_mem_reg);
6735 %}
6736
6737 // Store Char/Short
6738 instruct storeC(memory mem, rRegI src)
6739 %{
|