1843 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1844   // The passed offset is relative to address of the branch.
1845   // Don't need to adjust the offset.
1846   return UseCBCond && Assembler::is_simm(offset, 12);
1847 }
1848 
1849 const bool Matcher::isSimpleConstant64(jlong value) {
1850   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1851   // Depends on optimizations in MacroAssembler::setx.
1852   int hi = (int)(value >> 32);
1853   int lo = (int)(value & ~0);
1854   return (hi == 0) || (hi == -1) || (lo == 0);
1855 }
1856 
1857 // No scaling for the parameter the ClearArray node.
1858 const bool Matcher::init_array_count_is_in_bytes = true;
1859 
1860 // Threshold size for cleararray.
1861 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1862 








1863 // Should the Matcher clone shifts on addressing modes, expecting them to
1864 // be subsumed into complex addressing expressions or compute them into
1865 // registers?  True for Intel but false for most RISCs
1866 const bool Matcher::clone_shift_expressions = false;
1867 
1868 // Do we need to mask the count passed to shift instructions or does
1869 // the cpu only look at the lower 5/6 bits anyway?
1870 const bool Matcher::need_masked_shift_count = false;
1871 
1872 bool Matcher::narrow_oop_use_complex_address() {
1873   NOT_LP64(ShouldNotCallThis());
1874   assert(UseCompressedOops, "only for compressed oops code");
1875   return false;
1876 }
1877 
1878 // Is it better to copy float constants, or load them directly from memory?
1879 // Intel can load a float constant from a direct address, requiring no
1880 // extra registers.  Most RISCs will have to materialize an address into a
1881 // register first, so they would do better to copy the constant from stack.
1882 const bool Matcher::rematerialize_float_constants = false;

1843 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1844   // The passed offset is relative to address of the branch.
1845   // Don't need to adjust the offset.
1846   return UseCBCond && Assembler::is_simm(offset, 12);
1847 }
1848 
1849 const bool Matcher::isSimpleConstant64(jlong value) {
1850   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1851   // Depends on optimizations in MacroAssembler::setx.
1852   int hi = (int)(value >> 32);
1853   int lo = (int)(value & ~0);
1854   return (hi == 0) || (hi == -1) || (lo == 0);
1855 }
1856 
1857 // No scaling for the parameter the ClearArray node.
1858 const bool Matcher::init_array_count_is_in_bytes = true;
1859 
1860 // Threshold size for cleararray.
1861 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1862 
1863 // No additional cost for CMOVL.
1864 const int Matcher::long_cmove_cost() { return 0; }
1865 
1866 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1867 const int Matcher::float_cmove_cost() {
1868   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1869 }
1870 
1871 // Should the Matcher clone shifts on addressing modes, expecting them to
1872 // be subsumed into complex addressing expressions or compute them into
1873 // registers?  True for Intel but false for most RISCs
1874 const bool Matcher::clone_shift_expressions = false;
1875 
1876 // Do we need to mask the count passed to shift instructions or does
1877 // the cpu only look at the lower 5/6 bits anyway?
1878 const bool Matcher::need_masked_shift_count = false;
1879 
1880 bool Matcher::narrow_oop_use_complex_address() {
1881   NOT_LP64(ShouldNotCallThis());
1882   assert(UseCompressedOops, "only for compressed oops code");
1883   return false;
1884 }
1885 
1886 // Is it better to copy float constants, or load them directly from memory?
1887 // Intel can load a float constant from a direct address, requiring no
1888 // extra registers.  Most RISCs will have to materialize an address into a
1889 // register first, so they would do better to copy the constant from stack.
1890 const bool Matcher::rematerialize_float_constants = false;