516
517 case REP8(0xB8): // movl/q r, #32/#64(oop?)
518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
519 // these asserts are somewhat nonsensical
520 #ifndef _LP64
521 assert(which == imm_operand || which == disp32_operand, "");
522 #else
523 assert((which == call32_operand || which == imm_operand) && is_64bit ||
524 which == narrow_oop_operand && !is_64bit, "");
525 #endif // _LP64
526 return ip;
527
528 case 0x69: // imul r, a, #32
529 case 0xC7: // movl a, #32(oop?)
530 tail_size = 4;
531 debug_only(has_disp32 = true); // has both kinds of operands!
532 break;
533
534 case 0x0F: // movx..., etc.
535 switch (0xFF & *ip++) {
536 case 0x12: // movlps
537 case 0x28: // movaps
538 case 0x2E: // ucomiss
539 case 0x2F: // comiss
540 case 0x54: // andps
541 case 0x55: // andnps
542 case 0x56: // orps
543 case 0x57: // xorps
544 case 0x6E: // movd
545 case 0x7E: // movd
546 case 0xAE: // ldmxcsr a
547 // 64bit side says it these have both operands but that doesn't
548 // appear to be true
549 debug_only(has_disp32 = true);
550 break;
551
552 case 0xAD: // shrd r, a, %cl
553 case 0xAF: // imul r, a
554 case 0xBE: // movsbl r, a (movsxb)
555 case 0xBF: // movswl r, a (movsxw)
556 case 0xB6: // movzbl r, a (movzxb)
557 case 0xB7: // movzwl r, a (movzxw)
558 case REP16(0x40): // cmovl cc, r, a
559 case 0xB0: // cmpxchgb
560 case 0xB1: // cmpxchg
561 case 0xC1: // xaddl
562 case 0xC7: // cmpxchg8
563 case REP16(0x90): // setcc a
564 debug_only(has_disp32 = true);
565 // fall out of the switch to decode the address
566 break;
567
568 case 0xAC: // shrd r, a, #8
569 debug_only(has_disp32 = true);
570 tail_size = 1; // the imm8
571 break;
572
573 case REP16(0x80): // jcc rdisp32
574 if (which == end_pc_operand) return ip + 4;
575 assert(which == call32_operand, "jcc has no disp32 or imm");
576 return ip;
577 default:
578 ShouldNotReachHere();
579 }
580 break;
581
582 case 0x81: // addl a, #32; addl r, #32
583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
584 // on 32bit in the case of cmpl, the imm might be an oop
585 tail_size = 4;
586 debug_only(has_disp32 = true); // has both kinds of operands!
587 break;
608 case REP4(0x30): // xor...
609 case REP4(0x08): // or...
610 case REP4(0x18): // sbb...
611 case REP4(0x28): // sub...
612 case 0xF7: // mull a
613 case 0x8D: // lea r, a
614 case 0x87: // xchg r, a
615 case REP4(0x38): // cmp...
616 case 0x85: // test r, a
617 debug_only(has_disp32 = true); // has both kinds of operands!
618 break;
619
620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
621 case 0xC6: // movb a, #8
622 case 0x80: // cmpb a, #8
623 case 0x6B: // imul r, a, #8
624 debug_only(has_disp32 = true); // has both kinds of operands!
625 tail_size = 1; // the imm8
626 break;
627
628 case 0xE8: // call rdisp32
629 case 0xE9: // jmp rdisp32
630 if (which == end_pc_operand) return ip + 4;
631 assert(which == call32_operand, "call has no disp32 or imm");
632 return ip;
633
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
637 case 0xDD: // fld_d a; fst_d a; fstp_d a
638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
639 case 0xDF: // fild_d a; fistp_d a
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
643 debug_only(has_disp32 = true);
644 break;
645
646 case 0xF0: // Lock
647 assert(os::is_MP(), "only on MP");
648 goto again_after_prefix;
649
650 case 0xF3: // For SSE
651 case 0xF2: // For SSE2
652 switch (0xFF & *ip++) {
653 case REX:
654 case REX_B:
655 case REX_X:
656 case REX_XB:
657 case REX_R:
658 case REX_RB:
659 case REX_RX:
660 case REX_RXB:
661 case REX_W:
662 case REX_WB:
663 case REX_WX:
664 case REX_WXB:
665 case REX_WR:
901
902 void Assembler::addr_nop_7() {
903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
904 emit_byte(0x0F);
905 emit_byte(0x1F);
906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
907 emit_long(0); // 32-bits offset (4 bytes)
908 }
909
910 void Assembler::addr_nop_8() {
911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
912 emit_byte(0x0F);
913 emit_byte(0x1F);
914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
916 emit_long(0); // 32-bits offset (4 bytes)
917 }
918
919 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
921 emit_byte(0xF2);
922 int encode = prefix_and_encode(dst->encoding(), src->encoding());
923 emit_byte(0x0F);
924 emit_byte(0x58);
925 emit_byte(0xC0 | encode);
926 }
927
928 void Assembler::addsd(XMMRegister dst, Address src) {
929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
930 InstructionMark im(this);
931 emit_byte(0xF2);
932 prefix(src, dst);
933 emit_byte(0x0F);
934 emit_byte(0x58);
935 emit_operand(dst, src);
936 }
937
938 void Assembler::addss(XMMRegister dst, XMMRegister src) {
939 NOT_LP64(assert(VM_Version::supports_sse(), ""));
940 emit_byte(0xF3);
941 int encode = prefix_and_encode(dst->encoding(), src->encoding());
942 emit_byte(0x0F);
943 emit_byte(0x58);
944 emit_byte(0xC0 | encode);
945 }
946
947 void Assembler::addss(XMMRegister dst, Address src) {
948 NOT_LP64(assert(VM_Version::supports_sse(), ""));
949 InstructionMark im(this);
950 emit_byte(0xF3);
951 prefix(src, dst);
952 emit_byte(0x0F);
953 emit_byte(0x58);
954 emit_operand(dst, src);
955 }
956
957 void Assembler::andl(Register dst, int32_t imm32) {
958 prefix(dst);
959 emit_arith(0x81, 0xE0, dst, imm32);
960 }
961
962 void Assembler::andl(Register dst, Address src) {
963 InstructionMark im(this);
964 prefix(src, dst);
965 emit_byte(0x23);
966 emit_operand(dst, src);
967 }
968
969 void Assembler::andl(Register dst, Register src) {
970 (void) prefix_and_encode(dst->encoding(), src->encoding());
971 emit_arith(0x23, 0xC0, dst, src);
972 }
973
974 void Assembler::andpd(XMMRegister dst, Address src) {
975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
976 InstructionMark im(this);
977 emit_byte(0x66);
978 prefix(src, dst);
979 emit_byte(0x0F);
980 emit_byte(0x54);
981 emit_operand(dst, src);
982 }
983
984 void Assembler::bsfl(Register dst, Register src) {
985 int encode = prefix_and_encode(dst->encoding(), src->encoding());
986 emit_byte(0x0F);
987 emit_byte(0xBC);
988 emit_byte(0xC0 | encode);
989 }
990
991 void Assembler::bsrl(Register dst, Register src) {
992 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
993 int encode = prefix_and_encode(dst->encoding(), src->encoding());
994 emit_byte(0x0F);
995 emit_byte(0xBD);
996 emit_byte(0xC0 | encode);
997 }
998
999 void Assembler::bswapl(Register reg) { // bswap
1000 int encode = prefix_and_encode(reg->encoding());
1001 emit_byte(0x0F);
1002 emit_byte(0xC8 | encode);
1003 }
1140 movl(rax, adr);
1141 if (reg != rax) {
1142 Label L ;
1143 jcc(Assembler::notEqual, L);
1144 movl(adr, reg);
1145 bind(L);
1146 }
1147 } else {
1148 InstructionMark im(this);
1149 prefix(adr, reg);
1150 emit_byte(0x0F);
1151 emit_byte(0xB1);
1152 emit_operand(reg, adr);
1153 }
1154 }
1155
1156 void Assembler::comisd(XMMRegister dst, Address src) {
1157 // NOTE: dbx seems to decode this as comiss even though the
1158 // 0x66 is there. Strangly ucomisd comes out correct
1159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1160 emit_byte(0x66);
1161 comiss(dst, src);
1162 }
1163
1164 void Assembler::comiss(XMMRegister dst, Address src) {
1165 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1166
1167 InstructionMark im(this);
1168 prefix(src, dst);
1169 emit_byte(0x0F);
1170 emit_byte(0x2F);
1171 emit_operand(dst, src);
1172 }
1173
1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1175 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1176 emit_byte(0xF3);
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1178 emit_byte(0x0F);
1179 emit_byte(0xE6);
1180 emit_byte(0xC0 | encode);
1181 }
1182
1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1184 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1185 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1186 emit_byte(0x0F);
1187 emit_byte(0x5B);
1188 emit_byte(0xC0 | encode);
1189 }
1190
1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1193 emit_byte(0xF2);
1194 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1195 emit_byte(0x0F);
1196 emit_byte(0x5A);
1197 emit_byte(0xC0 | encode);
1198 }
1199
1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1202 emit_byte(0xF2);
1203 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1204 emit_byte(0x0F);
1205 emit_byte(0x2A);
1206 emit_byte(0xC0 | encode);
1207 }
1208
1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1210 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1211 emit_byte(0xF3);
1212 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1213 emit_byte(0x0F);
1214 emit_byte(0x2A);
1215 emit_byte(0xC0 | encode);
1216 }
1217
1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1220 emit_byte(0xF3);
1221 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1222 emit_byte(0x0F);
1223 emit_byte(0x5A);
1224 emit_byte(0xC0 | encode);
1225 }
1226
1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1228 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1229 emit_byte(0xF2);
1230 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1231 emit_byte(0x0F);
1232 emit_byte(0x2C);
1233 emit_byte(0xC0 | encode);
1234 }
1235
1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1237 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1238 emit_byte(0xF3);
1239 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1240 emit_byte(0x0F);
1241 emit_byte(0x2C);
1242 emit_byte(0xC0 | encode);
1243 }
1244
1245 void Assembler::decl(Address dst) {
1246 // Don't use it directly. Use MacroAssembler::decrement() instead.
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_byte(0xFF);
1250 emit_operand(rcx, dst);
1251 }
1252
1253 void Assembler::divsd(XMMRegister dst, Address src) {
1254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1255 InstructionMark im(this);
1256 emit_byte(0xF2);
1257 prefix(src, dst);
1258 emit_byte(0x0F);
1259 emit_byte(0x5E);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1265 emit_byte(0xF2);
1266 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1267 emit_byte(0x0F);
1268 emit_byte(0x5E);
1269 emit_byte(0xC0 | encode);
1270 }
1271
1272 void Assembler::divss(XMMRegister dst, Address src) {
1273 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1274 InstructionMark im(this);
1275 emit_byte(0xF3);
1276 prefix(src, dst);
1277 emit_byte(0x0F);
1278 emit_byte(0x5E);
1279 emit_operand(dst, src);
1280 }
1281
1282 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1283 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1284 emit_byte(0xF3);
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1286 emit_byte(0x0F);
1287 emit_byte(0x5E);
1288 emit_byte(0xC0 | encode);
1289 }
1290
1291 void Assembler::emms() {
1292 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1293 emit_byte(0x0F);
1294 emit_byte(0x77);
1295 }
1296
1297 void Assembler::hlt() {
1298 emit_byte(0xF4);
1299 }
1300
1301 void Assembler::idivl(Register src) {
1302 int encode = prefix_and_encode(src->encoding());
1303 emit_byte(0xF7);
1304 emit_byte(0xF8 | encode);
1305 }
1306
1492 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1493 emit_byte(0x0F);
1494 emit_byte(0xBD);
1495 emit_byte(0xC0 | encode);
1496 }
1497
1498 // Emit mfence instruction
1499 void Assembler::mfence() {
1500 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1501 emit_byte( 0x0F );
1502 emit_byte( 0xAE );
1503 emit_byte( 0xF0 );
1504 }
1505
1506 void Assembler::mov(Register dst, Register src) {
1507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1508 }
1509
1510 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1511 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1512 int dstenc = dst->encoding();
1513 int srcenc = src->encoding();
1514 emit_byte(0x66);
1515 if (dstenc < 8) {
1516 if (srcenc >= 8) {
1517 prefix(REX_B);
1518 srcenc -= 8;
1519 }
1520 } else {
1521 if (srcenc < 8) {
1522 prefix(REX_R);
1523 } else {
1524 prefix(REX_RB);
1525 srcenc -= 8;
1526 }
1527 dstenc -= 8;
1528 }
1529 emit_byte(0x0F);
1530 emit_byte(0x28);
1531 emit_byte(0xC0 | dstenc << 3 | srcenc);
1532 }
1533
1534 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1535 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1536 int dstenc = dst->encoding();
1537 int srcenc = src->encoding();
1538 if (dstenc < 8) {
1539 if (srcenc >= 8) {
1540 prefix(REX_B);
1541 srcenc -= 8;
1542 }
1543 } else {
1544 if (srcenc < 8) {
1545 prefix(REX_R);
1546 } else {
1547 prefix(REX_RB);
1548 srcenc -= 8;
1549 }
1550 dstenc -= 8;
1551 }
1552 emit_byte(0x0F);
1553 emit_byte(0x28);
1554 emit_byte(0xC0 | dstenc << 3 | srcenc);
1555 }
1556
1557 void Assembler::movb(Register dst, Address src) {
1558 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1559 InstructionMark im(this);
1560 prefix(src, dst, true);
1561 emit_byte(0x8A);
1562 emit_operand(dst, src);
1563 }
1564
1565
1566 void Assembler::movb(Address dst, int imm8) {
1567 InstructionMark im(this);
1568 prefix(dst);
1569 emit_byte(0xC6);
1570 emit_operand(rax, dst, 1);
1571 emit_byte(imm8);
1572 }
1573
1574
1575 void Assembler::movb(Address dst, Register src) {
1576 assert(src->has_byte_register(), "must have byte register");
1577 InstructionMark im(this);
1578 prefix(dst, src, true);
1579 emit_byte(0x88);
1580 emit_operand(src, dst);
1581 }
1582
1583 void Assembler::movdl(XMMRegister dst, Register src) {
1584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1585 emit_byte(0x66);
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1587 emit_byte(0x0F);
1588 emit_byte(0x6E);
1589 emit_byte(0xC0 | encode);
1590 }
1591
1592 void Assembler::movdl(Register dst, XMMRegister src) {
1593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1594 emit_byte(0x66);
1595 // swap src/dst to get correct prefix
1596 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1597 emit_byte(0x0F);
1598 emit_byte(0x7E);
1599 emit_byte(0xC0 | encode);
1600 }
1601
1602 void Assembler::movdl(XMMRegister dst, Address src) {
1603 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1604 InstructionMark im(this);
1605 emit_byte(0x66);
1606 prefix(src, dst);
1607 emit_byte(0x0F);
1608 emit_byte(0x6E);
1609 emit_operand(dst, src);
1610 }
1611
1612
1613 void Assembler::movdqa(XMMRegister dst, Address src) {
1614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1615 InstructionMark im(this);
1616 emit_byte(0x66);
1617 prefix(src, dst);
1618 emit_byte(0x0F);
1619 emit_byte(0x6F);
1620 emit_operand(dst, src);
1621 }
1622
1623 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1624 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1625 emit_byte(0x66);
1626 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1627 emit_byte(0x0F);
1628 emit_byte(0x6F);
1629 emit_byte(0xC0 | encode);
1630 }
1631
1632 void Assembler::movdqa(Address dst, XMMRegister src) {
1633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1634 InstructionMark im(this);
1635 emit_byte(0x66);
1636 prefix(dst, src);
1637 emit_byte(0x0F);
1638 emit_byte(0x7F);
1639 emit_operand(src, dst);
1640 }
1641
1642 void Assembler::movdqu(XMMRegister dst, Address src) {
1643 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1644 InstructionMark im(this);
1645 emit_byte(0xF3);
1646 prefix(src, dst);
1647 emit_byte(0x0F);
1648 emit_byte(0x6F);
1649 emit_operand(dst, src);
1650 }
1651
1652 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1654 emit_byte(0xF3);
1655 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1656 emit_byte(0x0F);
1657 emit_byte(0x6F);
1658 emit_byte(0xC0 | encode);
1659 }
1660
1661 void Assembler::movdqu(Address dst, XMMRegister src) {
1662 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1663 InstructionMark im(this);
1664 emit_byte(0xF3);
1665 prefix(dst, src);
1666 emit_byte(0x0F);
1667 emit_byte(0x7F);
1668 emit_operand(src, dst);
1669 }
1670
1671 // Uses zero extension on 64bit
1672
1673 void Assembler::movl(Register dst, int32_t imm32) {
1674 int encode = prefix_and_encode(dst->encoding());
1675 emit_byte(0xB8 | encode);
1676 emit_long(imm32);
1677 }
1678
1679 void Assembler::movl(Register dst, Register src) {
1680 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1681 emit_byte(0x8B);
1682 emit_byte(0xC0 | encode);
1683 }
1684
1685 void Assembler::movl(Register dst, Address src) {
1686 InstructionMark im(this);
1693 InstructionMark im(this);
1694 prefix(dst);
1695 emit_byte(0xC7);
1696 emit_operand(rax, dst, 4);
1697 emit_long(imm32);
1698 }
1699
1700 void Assembler::movl(Address dst, Register src) {
1701 InstructionMark im(this);
1702 prefix(dst, src);
1703 emit_byte(0x89);
1704 emit_operand(src, dst);
1705 }
1706
1707 // New cpus require to use movsd and movss to avoid partial register stall
1708 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1709 // The selection is done in MacroAssembler::movdbl() and movflt().
1710 void Assembler::movlpd(XMMRegister dst, Address src) {
1711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1712 InstructionMark im(this);
1713 emit_byte(0x66);
1714 prefix(src, dst);
1715 emit_byte(0x0F);
1716 emit_byte(0x12);
1717 emit_operand(dst, src);
1718 }
1719
1720 void Assembler::movq( MMXRegister dst, Address src ) {
1721 assert( VM_Version::supports_mmx(), "" );
1722 emit_byte(0x0F);
1723 emit_byte(0x6F);
1724 emit_operand(dst, src);
1725 }
1726
1727 void Assembler::movq( Address dst, MMXRegister src ) {
1728 assert( VM_Version::supports_mmx(), "" );
1729 emit_byte(0x0F);
1730 emit_byte(0x7F);
1731 // workaround gcc (3.2.1-7a) bug
1732 // In that version of gcc with only an emit_operand(MMX, Address)
1733 // gcc will tail jump and try and reverse the parameters completely
1734 // obliterating dst in the process. By having a version available
1735 // that doesn't need to swap the args at the tail jump the bug is
1736 // avoided.
1737 emit_operand(dst, src);
1738 }
1739
1740 void Assembler::movq(XMMRegister dst, Address src) {
1741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1742 InstructionMark im(this);
1743 emit_byte(0xF3);
1744 prefix(src, dst);
1745 emit_byte(0x0F);
1746 emit_byte(0x7E);
1747 emit_operand(dst, src);
1748 }
1749
1750 void Assembler::movq(Address dst, XMMRegister src) {
1751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1752 InstructionMark im(this);
1753 emit_byte(0x66);
1754 prefix(dst, src);
1755 emit_byte(0x0F);
1756 emit_byte(0xD6);
1757 emit_operand(src, dst);
1758 }
1759
1760 void Assembler::movsbl(Register dst, Address src) { // movsxb
1761 InstructionMark im(this);
1762 prefix(src, dst);
1763 emit_byte(0x0F);
1764 emit_byte(0xBE);
1765 emit_operand(dst, src);
1766 }
1767
1768 void Assembler::movsbl(Register dst, Register src) { // movsxb
1769 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1770 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1771 emit_byte(0x0F);
1772 emit_byte(0xBE);
1773 emit_byte(0xC0 | encode);
1774 }
1775
1776 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1777 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1778 emit_byte(0xF2);
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1780 emit_byte(0x0F);
1781 emit_byte(0x10);
1782 emit_byte(0xC0 | encode);
1783 }
1784
1785 void Assembler::movsd(XMMRegister dst, Address src) {
1786 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1787 InstructionMark im(this);
1788 emit_byte(0xF2);
1789 prefix(src, dst);
1790 emit_byte(0x0F);
1791 emit_byte(0x10);
1792 emit_operand(dst, src);
1793 }
1794
1795 void Assembler::movsd(Address dst, XMMRegister src) {
1796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797 InstructionMark im(this);
1798 emit_byte(0xF2);
1799 prefix(dst, src);
1800 emit_byte(0x0F);
1801 emit_byte(0x11);
1802 emit_operand(src, dst);
1803 }
1804
1805 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1806 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1807 emit_byte(0xF3);
1808 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1809 emit_byte(0x0F);
1810 emit_byte(0x10);
1811 emit_byte(0xC0 | encode);
1812 }
1813
1814 void Assembler::movss(XMMRegister dst, Address src) {
1815 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1816 InstructionMark im(this);
1817 emit_byte(0xF3);
1818 prefix(src, dst);
1819 emit_byte(0x0F);
1820 emit_byte(0x10);
1821 emit_operand(dst, src);
1822 }
1823
1824 void Assembler::movss(Address dst, XMMRegister src) {
1825 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1826 InstructionMark im(this);
1827 emit_byte(0xF3);
1828 prefix(dst, src);
1829 emit_byte(0x0F);
1830 emit_byte(0x11);
1831 emit_operand(src, dst);
1832 }
1833
1834 void Assembler::movswl(Register dst, Address src) { // movsxw
1835 InstructionMark im(this);
1836 prefix(src, dst);
1837 emit_byte(0x0F);
1838 emit_byte(0xBF);
1839 emit_operand(dst, src);
1840 }
1841
1842 void Assembler::movswl(Register dst, Register src) { // movsxw
1843 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1844 emit_byte(0x0F);
1845 emit_byte(0xBF);
1846 emit_byte(0xC0 | encode);
1847 }
1848
1849 void Assembler::movw(Address dst, int imm16) {
1902 emit_byte(0xB7);
1903 emit_byte(0xC0 | encode);
1904 }
1905
1906 void Assembler::mull(Address src) {
1907 InstructionMark im(this);
1908 prefix(src);
1909 emit_byte(0xF7);
1910 emit_operand(rsp, src);
1911 }
1912
1913 void Assembler::mull(Register src) {
1914 int encode = prefix_and_encode(src->encoding());
1915 emit_byte(0xF7);
1916 emit_byte(0xE0 | encode);
1917 }
1918
1919 void Assembler::mulsd(XMMRegister dst, Address src) {
1920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1921 InstructionMark im(this);
1922 emit_byte(0xF2);
1923 prefix(src, dst);
1924 emit_byte(0x0F);
1925 emit_byte(0x59);
1926 emit_operand(dst, src);
1927 }
1928
1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1931 emit_byte(0xF2);
1932 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1933 emit_byte(0x0F);
1934 emit_byte(0x59);
1935 emit_byte(0xC0 | encode);
1936 }
1937
1938 void Assembler::mulss(XMMRegister dst, Address src) {
1939 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1940 InstructionMark im(this);
1941 emit_byte(0xF3);
1942 prefix(src, dst);
1943 emit_byte(0x0F);
1944 emit_byte(0x59);
1945 emit_operand(dst, src);
1946 }
1947
1948 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1949 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1950 emit_byte(0xF3);
1951 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1952 emit_byte(0x0F);
1953 emit_byte(0x59);
1954 emit_byte(0xC0 | encode);
1955 }
1956
1957 void Assembler::negl(Register dst) {
1958 int encode = prefix_and_encode(dst->encoding());
1959 emit_byte(0xF7);
1960 emit_byte(0xD8 | encode);
1961 }
1962
1963 void Assembler::nop(int i) {
1964 #ifdef ASSERT
1965 assert(i > 0, " ");
1966 // The fancy nops aren't currently recognized by debuggers making it a
1967 // pain to disassemble code while debugging. If asserts are on clearly
1968 // speed is not an issue so simply use the single byte traditional nop
1969 // to do alignment.
1970
1971 for (; i > 0 ; i--) emit_byte(0x90);
1972 return;
2220 emit_arith_operand(0x81, rcx, dst, imm32);
2221 }
2222
2223 void Assembler::orl(Register dst, int32_t imm32) {
2224 prefix(dst);
2225 emit_arith(0x81, 0xC8, dst, imm32);
2226 }
2227
2228 void Assembler::orl(Register dst, Address src) {
2229 InstructionMark im(this);
2230 prefix(src, dst);
2231 emit_byte(0x0B);
2232 emit_operand(dst, src);
2233 }
2234
2235 void Assembler::orl(Register dst, Register src) {
2236 (void) prefix_and_encode(dst->encoding(), src->encoding());
2237 emit_arith(0x0B, 0xC0, dst, src);
2238 }
2239
2240 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2241 assert(VM_Version::supports_sse4_2(), "");
2242
2243 InstructionMark im(this);
2244 emit_byte(0x66);
2245 prefix(src, dst);
2246 emit_byte(0x0F);
2247 emit_byte(0x3A);
2248 emit_byte(0x61);
2249 emit_operand(dst, src);
2250 emit_byte(imm8);
2251 }
2252
2253 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2254 assert(VM_Version::supports_sse4_2(), "");
2255
2256 emit_byte(0x66);
2257 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2258 emit_byte(0x0F);
2259 emit_byte(0x3A);
2260 emit_byte(0x61);
2261 emit_byte(0xC0 | encode);
2262 emit_byte(imm8);
2263 }
2264
2265 // generic
2266 void Assembler::pop(Register dst) {
2267 int encode = prefix_and_encode(dst->encoding());
2268 emit_byte(0x58 | encode);
2269 }
2270
2271 void Assembler::popcntl(Register dst, Address src) {
2272 assert(VM_Version::supports_popcnt(), "must support");
2273 InstructionMark im(this);
2274 emit_byte(0xF3);
2275 prefix(src, dst);
2276 emit_byte(0x0F);
2277 emit_byte(0xB8);
2278 emit_operand(dst, src);
2279 }
2280
2281 void Assembler::popcntl(Register dst, Register src) {
2282 assert(VM_Version::supports_popcnt(), "must support");
2283 emit_byte(0xF3);
2284 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2343 InstructionMark im(this);
2344 prefetch_prefix(src);
2345 emit_byte(0x18);
2346 emit_operand(rbx, src); // 3, src
2347 }
2348
2349 void Assembler::prefetchw(Address src) {
2350 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2351 InstructionMark im(this);
2352 prefetch_prefix(src);
2353 emit_byte(0x0D);
2354 emit_operand(rcx, src); // 1, src
2355 }
2356
2357 void Assembler::prefix(Prefix p) {
2358 a_byte(p);
2359 }
2360
2361 void Assembler::por(XMMRegister dst, XMMRegister src) {
2362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2363
2364 emit_byte(0x66);
2365 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2366 emit_byte(0x0F);
2367
2368 emit_byte(0xEB);
2369 emit_byte(0xC0 | encode);
2370 }
2371
2372 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2373 assert(isByte(mode), "invalid value");
2374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2375
2376 emit_byte(0x66);
2377 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2378 emit_byte(0x0F);
2379 emit_byte(0x70);
2380 emit_byte(0xC0 | encode);
2381 emit_byte(mode & 0xFF);
2382
2383 }
2384
2385 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2386 assert(isByte(mode), "invalid value");
2387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2388
2389 InstructionMark im(this);
2390 emit_byte(0x66);
2391 prefix(src, dst);
2392 emit_byte(0x0F);
2393 emit_byte(0x70);
2394 emit_operand(dst, src);
2395 emit_byte(mode & 0xFF);
2396 }
2397
2398 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2399 assert(isByte(mode), "invalid value");
2400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2401
2402 emit_byte(0xF2);
2403 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2404 emit_byte(0x0F);
2405 emit_byte(0x70);
2406 emit_byte(0xC0 | encode);
2407 emit_byte(mode & 0xFF);
2408 }
2409
2410 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2411 assert(isByte(mode), "invalid value");
2412 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2413
2414 InstructionMark im(this);
2415 emit_byte(0xF2);
2416 prefix(src, dst); // QQ new
2417 emit_byte(0x0F);
2418 emit_byte(0x70);
2419 emit_operand(dst, src);
2420 emit_byte(mode & 0xFF);
2421 }
2422
2423 void Assembler::psrlq(XMMRegister dst, int shift) {
2424 // Shift 64 bit value logically right by specified number of bits.
2425 // HMM Table D-1 says sse2 or mmx.
2426 // Do not confuse it with psrldq SSE2 instruction which
2427 // shifts 128 bit value in xmm register by number of bytes.
2428 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2429
2430 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2431 emit_byte(0x66);
2432 emit_byte(0x0F);
2433 emit_byte(0x73);
2434 emit_byte(0xC0 | encode);
2435 emit_byte(shift);
2436 }
2437
2438 void Assembler::psrldq(XMMRegister dst, int shift) {
2439 // Shift 128 bit value in xmm register by number of bytes.
2440 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2441
2442 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding());
2443 emit_byte(0x66);
2444 emit_byte(0x0F);
2445 emit_byte(0x73);
2446 emit_byte(0xC0 | encode);
2447 emit_byte(shift);
2448 }
2449
2450 void Assembler::ptest(XMMRegister dst, Address src) {
2451 assert(VM_Version::supports_sse4_1(), "");
2452
2453 InstructionMark im(this);
2454 emit_byte(0x66);
2455 prefix(src, dst);
2456 emit_byte(0x0F);
2457 emit_byte(0x38);
2458 emit_byte(0x17);
2459 emit_operand(dst, src);
2460 }
2461
2462 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2463 assert(VM_Version::supports_sse4_1(), "");
2464
2465 emit_byte(0x66);
2466 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2467 emit_byte(0x0F);
2468 emit_byte(0x38);
2469 emit_byte(0x17);
2470 emit_byte(0xC0 | encode);
2471 }
2472
2473 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2475 emit_byte(0x66);
2476 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2477 emit_byte(0x0F);
2478 emit_byte(0x60);
2479 emit_byte(0xC0 | encode);
2480 }
2481
2482 void Assembler::push(int32_t imm32) {
2483 // in 64bits we push 64bits onto the stack but only
2484 // take a 32bit immediate
2485 emit_byte(0x68);
2486 emit_long(imm32);
2487 }
2488
2489 void Assembler::push(Register src) {
2490 int encode = prefix_and_encode(src->encoding());
2491
2492 emit_byte(0x50 | encode);
2493 }
2494
2495 void Assembler::pushf() {
2496 emit_byte(0x9C);
2497 }
2498
2499 #ifndef _LP64 // no 32bit push/pop on amd64
2500 void Assembler::pushl(Address src) {
2501 // Note this will push 64bit on 64bit
2502 InstructionMark im(this);
2503 prefix(src);
2504 emit_byte(0xFF);
2505 emit_operand(rsi, src);
2506 }
2507 #endif
2508
2509 void Assembler::pxor(XMMRegister dst, Address src) {
2510 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2511 InstructionMark im(this);
2512 emit_byte(0x66);
2513 prefix(src, dst);
2514 emit_byte(0x0F);
2515 emit_byte(0xEF);
2516 emit_operand(dst, src);
2517 }
2518
2519 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2521 InstructionMark im(this);
2522 emit_byte(0x66);
2523 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2524 emit_byte(0x0F);
2525 emit_byte(0xEF);
2526 emit_byte(0xC0 | encode);
2527 }
2528
2529 void Assembler::rcll(Register dst, int imm8) {
2530 assert(isShiftCount(imm8), "illegal shift count");
2531 int encode = prefix_and_encode(dst->encoding());
2532 if (imm8 == 1) {
2533 emit_byte(0xD1);
2534 emit_byte(0xD0 | encode);
2535 } else {
2536 emit_byte(0xC1);
2537 emit_byte(0xD0 | encode);
2538 emit_byte(imm8);
2539 }
2540 }
2541
2542 // copies data from [esi] to [edi] using rcx pointer sized words
2543 // generic
2544 void Assembler::rep_mov() {
2666 void Assembler::shrl(Register dst, int imm8) {
2667 assert(isShiftCount(imm8), "illegal shift count");
2668 int encode = prefix_and_encode(dst->encoding());
2669 emit_byte(0xC1);
2670 emit_byte(0xE8 | encode);
2671 emit_byte(imm8);
2672 }
2673
2674 void Assembler::shrl(Register dst) {
2675 int encode = prefix_and_encode(dst->encoding());
2676 emit_byte(0xD3);
2677 emit_byte(0xE8 | encode);
2678 }
2679
2680 // copies a single word from [esi] to [edi]
2681 void Assembler::smovl() {
2682 emit_byte(0xA5);
2683 }
2684
2685 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2686 // HMM Table D-1 says sse2
2687 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2689 emit_byte(0xF2);
2690 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2691 emit_byte(0x0F);
2692 emit_byte(0x51);
2693 emit_byte(0xC0 | encode);
2694 }
2695
2696 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2698 InstructionMark im(this);
2699 emit_byte(0xF2);
2700 prefix(src, dst);
2701 emit_byte(0x0F);
2702 emit_byte(0x51);
2703 emit_operand(dst, src);
2704 }
2705
2706 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2707 // HMM Table D-1 says sse2
2708 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2710 emit_byte(0xF3);
2711 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2712 emit_byte(0x0F);
2713 emit_byte(0x51);
2714 emit_byte(0xC0 | encode);
2715 }
2716
2717 void Assembler::sqrtss(XMMRegister dst, Address src) {
2718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2719 InstructionMark im(this);
2720 emit_byte(0xF3);
2721 prefix(src, dst);
2722 emit_byte(0x0F);
2723 emit_byte(0x51);
2724 emit_operand(dst, src);
2725 }
2726
2727 void Assembler::stmxcsr( Address dst) {
2728 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2729 InstructionMark im(this);
2730 prefix(dst);
2731 emit_byte(0x0F);
2732 emit_byte(0xAE);
2733 emit_operand(as_Register(3), dst);
2734 }
2735
2736 void Assembler::subl(Address dst, int32_t imm32) {
2737 InstructionMark im(this);
2738 prefix(dst);
2739 emit_arith_operand(0x81, rbp, dst, imm32);
2740 }
2741
2742 void Assembler::subl(Address dst, Register src) {
2748
2749 void Assembler::subl(Register dst, int32_t imm32) {
2750 prefix(dst);
2751 emit_arith(0x81, 0xE8, dst, imm32);
2752 }
2753
2754 void Assembler::subl(Register dst, Address src) {
2755 InstructionMark im(this);
2756 prefix(src, dst);
2757 emit_byte(0x2B);
2758 emit_operand(dst, src);
2759 }
2760
2761 void Assembler::subl(Register dst, Register src) {
2762 (void) prefix_and_encode(dst->encoding(), src->encoding());
2763 emit_arith(0x2B, 0xC0, dst, src);
2764 }
2765
2766 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2767 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2768 emit_byte(0xF2);
2769 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2770 emit_byte(0x0F);
2771 emit_byte(0x5C);
2772 emit_byte(0xC0 | encode);
2773 }
2774
2775 void Assembler::subsd(XMMRegister dst, Address src) {
2776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2777 InstructionMark im(this);
2778 emit_byte(0xF2);
2779 prefix(src, dst);
2780 emit_byte(0x0F);
2781 emit_byte(0x5C);
2782 emit_operand(dst, src);
2783 }
2784
2785 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2786 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2787 emit_byte(0xF3);
2788 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2789 emit_byte(0x0F);
2790 emit_byte(0x5C);
2791 emit_byte(0xC0 | encode);
2792 }
2793
2794 void Assembler::subss(XMMRegister dst, Address src) {
2795 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2796 InstructionMark im(this);
2797 emit_byte(0xF3);
2798 prefix(src, dst);
2799 emit_byte(0x0F);
2800 emit_byte(0x5C);
2801 emit_operand(dst, src);
2802 }
2803
2804 void Assembler::testb(Register dst, int imm8) {
2805 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2806 (void) prefix_and_encode(dst->encoding(), true);
2807 emit_arith_b(0xF6, 0xC0, dst, imm8);
2808 }
2809
2810 void Assembler::testl(Register dst, int32_t imm32) {
2811 // not using emit_arith because test
2812 // doesn't support sign-extension of
2813 // 8bit operands
2814 int encode = dst->encoding();
2815 if (encode == 0) {
2816 emit_byte(0xA9);
2817 } else {
2818 encode = prefix_and_encode(encode);
2819 emit_byte(0xF7);
2820 emit_byte(0xC0 | encode);
2821 }
2822 emit_long(imm32);
2823 }
2824
2825 void Assembler::testl(Register dst, Register src) {
2826 (void) prefix_and_encode(dst->encoding(), src->encoding());
2827 emit_arith(0x85, 0xC0, dst, src);
2828 }
2829
2830 void Assembler::testl(Register dst, Address src) {
2831 InstructionMark im(this);
2832 prefix(src, dst);
2833 emit_byte(0x85);
2834 emit_operand(dst, src);
2835 }
2836
2837 void Assembler::ucomisd(XMMRegister dst, Address src) {
2838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2839 emit_byte(0x66);
2840 ucomiss(dst, src);
2841 }
2842
2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2844 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2845 emit_byte(0x66);
2846 ucomiss(dst, src);
2847 }
2848
2849 void Assembler::ucomiss(XMMRegister dst, Address src) {
2850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2851
2852 InstructionMark im(this);
2853 prefix(src, dst);
2854 emit_byte(0x0F);
2855 emit_byte(0x2E);
2856 emit_operand(dst, src);
2857 }
2858
2859 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2860 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2861 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2862 emit_byte(0x0F);
2863 emit_byte(0x2E);
2864 emit_byte(0xC0 | encode);
2865 }
2866
2867
2868 void Assembler::xaddl(Address dst, Register src) {
2869 InstructionMark im(this);
2870 prefix(dst, src);
2871 emit_byte(0x0F);
2872 emit_byte(0xC1);
2873 emit_operand(src, dst);
2874 }
2875
2876 void Assembler::xchgl(Register dst, Address src) { // xchg
2877 InstructionMark im(this);
2878 prefix(src, dst);
2879 emit_byte(0x87);
2880 emit_operand(dst, src);
2881 }
2882
2888
2889 void Assembler::xorl(Register dst, int32_t imm32) {
2890 prefix(dst);
2891 emit_arith(0x81, 0xF0, dst, imm32);
2892 }
2893
2894 void Assembler::xorl(Register dst, Address src) {
2895 InstructionMark im(this);
2896 prefix(src, dst);
2897 emit_byte(0x33);
2898 emit_operand(dst, src);
2899 }
2900
2901 void Assembler::xorl(Register dst, Register src) {
2902 (void) prefix_and_encode(dst->encoding(), src->encoding());
2903 emit_arith(0x33, 0xC0, dst, src);
2904 }
2905
2906 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2907 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2908 emit_byte(0x66);
2909 xorps(dst, src);
2910 }
2911
2912 void Assembler::xorpd(XMMRegister dst, Address src) {
2913 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2914 InstructionMark im(this);
2915 emit_byte(0x66);
2916 prefix(src, dst);
2917 emit_byte(0x0F);
2918 emit_byte(0x57);
2919 emit_operand(dst, src);
2920 }
2921
2922
2923 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2924 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2925 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2926 emit_byte(0x0F);
2927 emit_byte(0x57);
2928 emit_byte(0xC0 | encode);
2929 }
2930
2931 void Assembler::xorps(XMMRegister dst, Address src) {
2932 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2933 InstructionMark im(this);
2934 prefix(src, dst);
2935 emit_byte(0x0F);
2936 emit_byte(0x57);
2937 emit_operand(dst, src);
2938 }
2939
2940 #ifndef _LP64
2941 // 32bit only pieces of the assembler
2942
2943 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2944 // NO PREFIX AS NEVER 64BIT
2945 InstructionMark im(this);
2946 emit_byte(0x81);
2947 emit_byte(0xF8 | src1->encoding());
2948 emit_data(imm32, rspec, 0);
2949 }
2950
2951 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2952 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2953 InstructionMark im(this);
2954 emit_byte(0x81);
2955 emit_operand(rdi, src1);
3377
3378 void Assembler::fucomip(int i) {
3379 // make sure the instruction is supported (introduced for P6, together with cmov)
3380 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3381 emit_farith(0xDF, 0xE8, i);
3382 }
3383
3384 void Assembler::fwait() {
3385 emit_byte(0x9B);
3386 }
3387
3388 void Assembler::fxch(int i) {
3389 emit_farith(0xD9, 0xC8, i);
3390 }
3391
3392 void Assembler::fyl2x() {
3393 emit_byte(0xD9);
3394 emit_byte(0xF1);
3395 }
3396
3397
3398 #ifndef _LP64
3399
3400 void Assembler::incl(Register dst) {
3401 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3402 emit_byte(0x40 | dst->encoding());
3403 }
3404
3405 void Assembler::lea(Register dst, Address src) {
3406 leal(dst, src);
3407 }
3408
3409 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3410 InstructionMark im(this);
3411 emit_byte(0xC7);
3412 emit_operand(rax, dst);
3413 emit_data((int)imm32, rspec, 0);
3414 }
3415
3416 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3417 InstructionMark im(this);
3739 prefix(REX_X);
3740 }
3741 }
3742 } else {
3743 if (adr.base_needs_rex()) {
3744 if (adr.index_needs_rex()) {
3745 prefix(REX_RXB);
3746 } else {
3747 prefix(REX_RB);
3748 }
3749 } else {
3750 if (adr.index_needs_rex()) {
3751 prefix(REX_RX);
3752 } else {
3753 prefix(REX_R);
3754 }
3755 }
3756 }
3757 }
3758
3759 void Assembler::adcq(Register dst, int32_t imm32) {
3760 (void) prefixq_and_encode(dst->encoding());
3761 emit_arith(0x81, 0xD0, dst, imm32);
3762 }
3763
3764 void Assembler::adcq(Register dst, Address src) {
3765 InstructionMark im(this);
3766 prefixq(src, dst);
3767 emit_byte(0x13);
3768 emit_operand(dst, src);
3769 }
3770
3771 void Assembler::adcq(Register dst, Register src) {
3772 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3773 emit_arith(0x13, 0xC0, dst, src);
3774 }
3775
3776 void Assembler::addq(Address dst, int32_t imm32) {
3777 InstructionMark im(this);
3778 prefixq(dst);
3901 emit_arith(0x3B, 0xC0, dst, src);
3902 }
3903
3904 void Assembler::cmpq(Register dst, Address src) {
3905 InstructionMark im(this);
3906 prefixq(src, dst);
3907 emit_byte(0x3B);
3908 emit_operand(dst, src);
3909 }
3910
3911 void Assembler::cmpxchgq(Register reg, Address adr) {
3912 InstructionMark im(this);
3913 prefixq(adr, reg);
3914 emit_byte(0x0F);
3915 emit_byte(0xB1);
3916 emit_operand(reg, adr);
3917 }
3918
3919 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3921 emit_byte(0xF2);
3922 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3923 emit_byte(0x0F);
3924 emit_byte(0x2A);
3925 emit_byte(0xC0 | encode);
3926 }
3927
3928 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3929 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3930 emit_byte(0xF3);
3931 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3932 emit_byte(0x0F);
3933 emit_byte(0x2A);
3934 emit_byte(0xC0 | encode);
3935 }
3936
3937 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3938 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3939 emit_byte(0xF2);
3940 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3941 emit_byte(0x0F);
3942 emit_byte(0x2C);
3943 emit_byte(0xC0 | encode);
3944 }
3945
3946 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3947 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3948 emit_byte(0xF3);
3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3950 emit_byte(0x0F);
3951 emit_byte(0x2C);
3952 emit_byte(0xC0 | encode);
3953 }
3954
3955 void Assembler::decl(Register dst) {
3956 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3957 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3958 int encode = prefix_and_encode(dst->encoding());
3959 emit_byte(0xFF);
3960 emit_byte(0xC8 | encode);
3961 }
3962
3963 void Assembler::decq(Register dst) {
3964 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3965 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3966 int encode = prefixq_and_encode(dst->encoding());
3967 emit_byte(0xFF);
3968 emit_byte(0xC8 | encode);
3969 }
3970
4090
4091 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4092 InstructionMark im(this);
4093 prefix(src1);
4094 emit_byte(0x81);
4095 emit_operand(rax, src1, 4);
4096 emit_data((int)imm32, rspec, narrow_oop_operand);
4097 }
4098
4099 void Assembler::lzcntq(Register dst, Register src) {
4100 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4101 emit_byte(0xF3);
4102 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4103 emit_byte(0x0F);
4104 emit_byte(0xBD);
4105 emit_byte(0xC0 | encode);
4106 }
4107
4108 void Assembler::movdq(XMMRegister dst, Register src) {
4109 // table D-1 says MMX/SSE2
4110 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4111 emit_byte(0x66);
4112 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4113 emit_byte(0x0F);
4114 emit_byte(0x6E);
4115 emit_byte(0xC0 | encode);
4116 }
4117
4118 void Assembler::movdq(Register dst, XMMRegister src) {
4119 // table D-1 says MMX/SSE2
4120 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4121 emit_byte(0x66);
4122 // swap src/dst to get correct prefix
4123 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4124 emit_byte(0x0F);
4125 emit_byte(0x7E);
4126 emit_byte(0xC0 | encode);
4127 }
4128
4129 void Assembler::movq(Register dst, Register src) {
4130 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4131 emit_byte(0x8B);
4132 emit_byte(0xC0 | encode);
4133 }
4134
4135 void Assembler::movq(Register dst, Address src) {
4136 InstructionMark im(this);
4137 prefixq(src, dst);
4138 emit_byte(0x8B);
4139 emit_operand(dst, src);
4140 }
4141
4142 void Assembler::movq(Address dst, Register src) {
4143 InstructionMark im(this);
4144 prefixq(dst, src);
5663 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5664 }
5665 }
5666
5667 #endif // _LP64
5668
5669 // Now versions that are common to 32/64 bit
5670
5671 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5672 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5673 }
5674
5675 void MacroAssembler::addptr(Register dst, Register src) {
5676 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5677 }
5678
5679 void MacroAssembler::addptr(Address dst, Register src) {
5680 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5681 }
5682
5683 void MacroAssembler::align(int modulus) {
5684 if (offset() % modulus != 0) {
5685 nop(modulus - (offset() % modulus));
5686 }
5687 }
5688
5689 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5690 if (reachable(src)) {
5691 andpd(dst, as_Address(src));
5692 } else {
5693 lea(rscratch1, src);
5694 andpd(dst, Address(rscratch1, 0));
5695 }
5696 }
5697
5698 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5699 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5700 }
5701
5702 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5703 pushf();
5704 if (os::is_MP())
5705 lock();
5706 incrementl(counter_addr);
5707 popf();
5708 }
5709
5710 // Writes to stack successive pages until offset reached to check for
5711 // stack overflow + shadow pages. This clobbers tmp.
5712 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5713 movptr(tmp, rsp);
5714 // Bang stack for total size given plus shadow page size.
5715 // Bang one page at a time because large size can bang beyond yellow and
5716 // red zones.
5717 Label loop;
6251
6252 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6253 if (reachable(adr)) {
6254 if (os::is_MP())
6255 lock();
6256 cmpxchgptr(reg, as_Address(adr));
6257 } else {
6258 lea(rscratch1, adr);
6259 if (os::is_MP())
6260 lock();
6261 cmpxchgptr(reg, Address(rscratch1, 0));
6262 }
6263 }
6264
6265 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6266 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6267 }
6268
6269 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6270 if (reachable(src)) {
6271 comisd(dst, as_Address(src));
6272 } else {
6273 lea(rscratch1, src);
6274 comisd(dst, Address(rscratch1, 0));
6275 }
6276 }
6277
6278 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6279 if (reachable(src)) {
6280 comiss(dst, as_Address(src));
6281 } else {
6282 lea(rscratch1, src);
6283 comiss(dst, Address(rscratch1, 0));
6284 }
6285 }
6286
6287
6288 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6289 Condition negated_cond = negate_condition(cond);
6290 Label L;
6291 jcc(negated_cond, L);
6292 atomic_incl(counter_addr);
6293 bind(L);
6294 }
6295
6296 int MacroAssembler::corrected_idivl(Register reg) {
6297 // Full implementation of Java idiv and irem; checks for
6298 // special case as described in JVM spec., p.243 & p.271.
6299 // The function returns the (pc) offset of the idivl
6300 // instruction - may be needed for implicit exceptions.
6301 //
6302 // normal case special case
6303 //
6347 /* else */ { subl(dst, value) ; return; }
6348 }
6349
6350 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6351 assert (shift_value > 0, "illegal shift value");
6352 Label _is_positive;
6353 testl (reg, reg);
6354 jcc (Assembler::positive, _is_positive);
6355 int offset = (1 << shift_value) - 1 ;
6356
6357 if (offset == 1) {
6358 incrementl(reg);
6359 } else {
6360 addl(reg, offset);
6361 }
6362
6363 bind (_is_positive);
6364 sarl(reg, shift_value);
6365 }
6366
6367 // !defined(COMPILER2) is because of stupid core builds
6368 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6369 void MacroAssembler::empty_FPU_stack() {
6370 if (VM_Version::supports_mmx()) {
6371 emms();
6372 } else {
6373 for (int i = 8; i-- > 0; ) ffree(i);
6374 }
6375 }
6376 #endif // !LP64 || C1 || !C2
6377
6378
6379 // Defines obj, preserves var_size_in_bytes
6380 void MacroAssembler::eden_allocate(Register obj,
6381 Register var_size_in_bytes,
6382 int con_size_in_bytes,
6383 Register t1,
6384 Label& slow_case) {
6385 assert(obj == rax, "obj must be in rax, for cmpxchg");
6386 assert_different_registers(obj, var_size_in_bytes, t1);
6786 }
6787 }
6788
6789 void MacroAssembler::movptr(Register dst, Register src) {
6790 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6791 }
6792
6793 void MacroAssembler::movptr(Register dst, Address src) {
6794 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6795 }
6796
6797 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6798 void MacroAssembler::movptr(Register dst, intptr_t src) {
6799 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6800 }
6801
6802 void MacroAssembler::movptr(Address dst, Register src) {
6803 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6804 }
6805
6806 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6807 if (reachable(src)) {
6808 movss(dst, as_Address(src));
6809 } else {
6810 lea(rscratch1, src);
6811 movss(dst, Address(rscratch1, 0));
6812 }
6813 }
6814
6815 void MacroAssembler::null_check(Register reg, int offset) {
6816 if (needs_explicit_null_check(offset)) {
6817 // provoke OS NULL exception if reg = NULL by
6818 // accessing M[reg] w/o changing any (non-CC) registers
6819 // NOTE: cmpl is plenty here to provoke a segv
6820 cmpptr(rax, Address(reg, 0));
6821 // Note: should probably use testl(rax, Address(reg, 0));
6822 // may be shorter code (however, this version of
6823 // testl needs to be implemented first)
6824 } else {
6825 // nothing to do, (later) access of M[reg + offset]
6826 // will provoke OS NULL exception if reg = NULL
6827 }
6828 }
6829
6830 void MacroAssembler::os_breakpoint() {
6831 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6832 // (e.g., MSVC can't call ps() otherwise)
6833 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6834 }
6973 } else {
6974 shll(reg, 24);
6975 sarl(reg, 24);
6976 }
6977 }
6978
6979 void MacroAssembler::sign_extend_short(Register reg) {
6980 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6981 movswl(reg, reg); // movsxw
6982 } else {
6983 shll(reg, 16);
6984 sarl(reg, 16);
6985 }
6986 }
6987
6988 void MacroAssembler::testl(Register dst, AddressLiteral src) {
6989 assert(reachable(src), "Address should be reachable");
6990 testl(dst, as_Address(src));
6991 }
6992
6993 //////////////////////////////////////////////////////////////////////////////////
6994 #ifndef SERIALGC
6995
6996 void MacroAssembler::g1_write_barrier_pre(Register obj,
6997 Register pre_val,
6998 Register thread,
6999 Register tmp,
7000 bool tosca_live,
7001 bool expand_call) {
7002
7003 // If expand_call is true then we expand the call_VM_leaf macro
7004 // directly to skip generating the check by
7005 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
7006
7007 #ifdef _LP64
7008 assert(thread == r15_thread, "must be");
7009 #endif // _LP64
7010
7011 Label done;
7012 Label runtime;
7858 }
7859
7860 if (L_failure == &L_fallthrough)
7861 jccb(Assembler::notEqual, *L_failure);
7862 else jcc(Assembler::notEqual, *L_failure);
7863
7864 // Success. Cache the super we found and proceed in triumph.
7865 movptr(super_cache_addr, super_klass);
7866
7867 if (L_success != &L_fallthrough) {
7868 jmp(*L_success);
7869 }
7870
7871 #undef IS_A_TEMP
7872
7873 bind(L_fallthrough);
7874 }
7875
7876
7877 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7878 ucomisd(dst, as_Address(src));
7879 }
7880
7881 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7882 ucomiss(dst, as_Address(src));
7883 }
7884
7885 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7886 if (reachable(src)) {
7887 xorpd(dst, as_Address(src));
7888 } else {
7889 lea(rscratch1, src);
7890 xorpd(dst, Address(rscratch1, 0));
7891 }
7892 }
7893
7894 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7895 if (reachable(src)) {
7896 xorps(dst, as_Address(src));
7897 } else {
7898 lea(rscratch1, src);
7899 xorps(dst, Address(rscratch1, 0));
7900 }
7901 }
7902
7903 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
7904 if (VM_Version::supports_cmov()) {
7905 cmovl(cc, dst, src);
7906 } else {
7907 Label L;
7908 jccb(negate_condition(cc), L);
7909 movl(dst, src);
7910 bind(L);
7911 }
7912 }
7913
7914 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
7915 if (VM_Version::supports_cmov()) {
7916 cmovl(cc, dst, src);
7917 } else {
7918 Label L;
7919 jccb(negate_condition(cc), L);
|
516
517 case REP8(0xB8): // movl/q r, #32/#64(oop?)
518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
519 // these asserts are somewhat nonsensical
520 #ifndef _LP64
521 assert(which == imm_operand || which == disp32_operand, "");
522 #else
523 assert((which == call32_operand || which == imm_operand) && is_64bit ||
524 which == narrow_oop_operand && !is_64bit, "");
525 #endif // _LP64
526 return ip;
527
528 case 0x69: // imul r, a, #32
529 case 0xC7: // movl a, #32(oop?)
530 tail_size = 4;
531 debug_only(has_disp32 = true); // has both kinds of operands!
532 break;
533
534 case 0x0F: // movx..., etc.
535 switch (0xFF & *ip++) {
536 case 0x3A: // pcmpestri
537 tail_size = 1;
538 case 0x38: // ptest, pmovzxbw
539 ip++; // skip opcode
540 debug_only(has_disp32 = true); // has both kinds of operands!
541 break;
542
543 case 0x70: // pshufd r, r/a, #8
544 debug_only(has_disp32 = true); // has both kinds of operands!
545 case 0x73: // psrldq r, #8
546 tail_size = 1;
547 break;
548
549 case 0x12: // movlps
550 case 0x28: // movaps
551 case 0x2E: // ucomiss
552 case 0x2F: // comiss
553 case 0x54: // andps
554 case 0x55: // andnps
555 case 0x56: // orps
556 case 0x57: // xorps
557 case 0x6E: // movd
558 case 0x7E: // movd
559 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
560 debug_only(has_disp32 = true);
561 break;
562
563 case 0xAD: // shrd r, a, %cl
564 case 0xAF: // imul r, a
565 case 0xBE: // movsbl r, a (movsxb)
566 case 0xBF: // movswl r, a (movsxw)
567 case 0xB6: // movzbl r, a (movzxb)
568 case 0xB7: // movzwl r, a (movzxw)
569 case REP16(0x40): // cmovl cc, r, a
570 case 0xB0: // cmpxchgb
571 case 0xB1: // cmpxchg
572 case 0xC1: // xaddl
573 case 0xC7: // cmpxchg8
574 case REP16(0x90): // setcc a
575 debug_only(has_disp32 = true);
576 // fall out of the switch to decode the address
577 break;
578
579 case 0xC4: // pinsrw r, a, #8
580 debug_only(has_disp32 = true);
581 case 0xC5: // pextrw r, r, #8
582 tail_size = 1; // the imm8
583 break;
584
585 case 0xAC: // shrd r, a, #8
586 debug_only(has_disp32 = true);
587 tail_size = 1; // the imm8
588 break;
589
590 case REP16(0x80): // jcc rdisp32
591 if (which == end_pc_operand) return ip + 4;
592 assert(which == call32_operand, "jcc has no disp32 or imm");
593 return ip;
594 default:
595 ShouldNotReachHere();
596 }
597 break;
598
599 case 0x81: // addl a, #32; addl r, #32
600 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
601 // on 32bit in the case of cmpl, the imm might be an oop
602 tail_size = 4;
603 debug_only(has_disp32 = true); // has both kinds of operands!
604 break;
625 case REP4(0x30): // xor...
626 case REP4(0x08): // or...
627 case REP4(0x18): // sbb...
628 case REP4(0x28): // sub...
629 case 0xF7: // mull a
630 case 0x8D: // lea r, a
631 case 0x87: // xchg r, a
632 case REP4(0x38): // cmp...
633 case 0x85: // test r, a
634 debug_only(has_disp32 = true); // has both kinds of operands!
635 break;
636
637 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
638 case 0xC6: // movb a, #8
639 case 0x80: // cmpb a, #8
640 case 0x6B: // imul r, a, #8
641 debug_only(has_disp32 = true); // has both kinds of operands!
642 tail_size = 1; // the imm8
643 break;
644
645 case 0xC4: // VEX_3bytes
646 case 0xC5: // VEX_2bytes
647 assert((UseAVX > 0), "shouldn't have VEX prefix");
648 assert(ip == inst+1, "no prefixes allowed");
649 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
650 // but they have prefix 0x0F and processed when 0x0F processed above.
651 //
652 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
653 // instructions (these instructions are not supported in 64-bit mode).
654 // To distinguish them bits [7:6] are set in the VEX second byte since
655 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
656 // those VEX bits REX and vvvv bits are inverted.
657 //
658 // Fortunately C2 doesn't generate these instructions so we don't need
659 // to check for them in product version.
660
661 // Check second byte
662 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
663
664 // First byte
665 if ((0xFF & *inst) == VEX_3bytes) {
666 ip++; // third byte
667 is_64bit = ((VEX_W & *ip) == VEX_W);
668 }
669 ip++; // opcode
670 // To find the end of instruction (which == end_pc_operand).
671 switch (0xFF & *ip) {
672 case 0x61: // pcmpestri r, r/a, #8
673 case 0x70: // pshufd r, r/a, #8
674 case 0x73: // psrldq r, #8
675 tail_size = 1; // the imm8
676 break;
677 default:
678 break;
679 }
680 ip++; // skip opcode
681 debug_only(has_disp32 = true); // has both kinds of operands!
682 break;
683
684 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
685 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
686 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
687 case 0xDD: // fld_d a; fst_d a; fstp_d a
688 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
689 case 0xDF: // fild_d a; fistp_d a
690 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
691 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
692 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
693 debug_only(has_disp32 = true);
694 break;
695
696 case 0xE8: // call rdisp32
697 case 0xE9: // jmp rdisp32
698 if (which == end_pc_operand) return ip + 4;
699 assert(which == call32_operand, "call has no disp32 or imm");
700 return ip;
701
702 case 0xF0: // Lock
703 assert(os::is_MP(), "only on MP");
704 goto again_after_prefix;
705
706 case 0xF3: // For SSE
707 case 0xF2: // For SSE2
708 switch (0xFF & *ip++) {
709 case REX:
710 case REX_B:
711 case REX_X:
712 case REX_XB:
713 case REX_R:
714 case REX_RB:
715 case REX_RX:
716 case REX_RXB:
717 case REX_W:
718 case REX_WB:
719 case REX_WX:
720 case REX_WXB:
721 case REX_WR:
957
958 void Assembler::addr_nop_7() {
959 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
960 emit_byte(0x0F);
961 emit_byte(0x1F);
962 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
963 emit_long(0); // 32-bits offset (4 bytes)
964 }
965
966 void Assembler::addr_nop_8() {
967 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
968 emit_byte(0x0F);
969 emit_byte(0x1F);
970 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
971 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
972 emit_long(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
976 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
977 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
978 emit_byte(0x58);
979 emit_byte(0xC0 | encode);
980 }
981
982 void Assembler::addsd(XMMRegister dst, Address src) {
983 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
984 InstructionMark im(this);
985 simd_prefix(dst, dst, src, VEX_SIMD_F2);
986 emit_byte(0x58);
987 emit_operand(dst, src);
988 }
989
990 void Assembler::addss(XMMRegister dst, XMMRegister src) {
991 NOT_LP64(assert(VM_Version::supports_sse(), ""));
992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
993 emit_byte(0x58);
994 emit_byte(0xC0 | encode);
995 }
996
997 void Assembler::addss(XMMRegister dst, Address src) {
998 NOT_LP64(assert(VM_Version::supports_sse(), ""));
999 InstructionMark im(this);
1000 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1001 emit_byte(0x58);
1002 emit_operand(dst, src);
1003 }
1004
1005 void Assembler::andl(Address dst, int32_t imm32) {
1006 InstructionMark im(this);
1007 prefix(dst);
1008 emit_byte(0x81);
1009 emit_operand(rsp, dst, 4);
1010 emit_long(imm32);
1011 }
1012
1013 void Assembler::andl(Register dst, int32_t imm32) {
1014 prefix(dst);
1015 emit_arith(0x81, 0xE0, dst, imm32);
1016 }
1017
1018 void Assembler::andl(Register dst, Address src) {
1019 InstructionMark im(this);
1020 prefix(src, dst);
1021 emit_byte(0x23);
1022 emit_operand(dst, src);
1023 }
1024
1025 void Assembler::andl(Register dst, Register src) {
1026 (void) prefix_and_encode(dst->encoding(), src->encoding());
1027 emit_arith(0x23, 0xC0, dst, src);
1028 }
1029
1030 void Assembler::andpd(XMMRegister dst, Address src) {
1031 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1032 InstructionMark im(this);
1033 simd_prefix(dst, dst, src, VEX_SIMD_66);
1034 emit_byte(0x54);
1035 emit_operand(dst, src);
1036 }
1037
1038 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1039 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1040 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1041 emit_byte(0x54);
1042 emit_byte(0xC0 | encode);
1043 }
1044
1045 void Assembler::andps(XMMRegister dst, Address src) {
1046 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1047 InstructionMark im(this);
1048 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1049 emit_byte(0x54);
1050 emit_operand(dst, src);
1051 }
1052
1053 void Assembler::andps(XMMRegister dst, XMMRegister src) {
1054 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1056 emit_byte(0x54);
1057 emit_byte(0xC0 | encode);
1058 }
1059
1060 void Assembler::bsfl(Register dst, Register src) {
1061 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1062 emit_byte(0x0F);
1063 emit_byte(0xBC);
1064 emit_byte(0xC0 | encode);
1065 }
1066
1067 void Assembler::bsrl(Register dst, Register src) {
1068 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1069 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1070 emit_byte(0x0F);
1071 emit_byte(0xBD);
1072 emit_byte(0xC0 | encode);
1073 }
1074
1075 void Assembler::bswapl(Register reg) { // bswap
1076 int encode = prefix_and_encode(reg->encoding());
1077 emit_byte(0x0F);
1078 emit_byte(0xC8 | encode);
1079 }
1216 movl(rax, adr);
1217 if (reg != rax) {
1218 Label L ;
1219 jcc(Assembler::notEqual, L);
1220 movl(adr, reg);
1221 bind(L);
1222 }
1223 } else {
1224 InstructionMark im(this);
1225 prefix(adr, reg);
1226 emit_byte(0x0F);
1227 emit_byte(0xB1);
1228 emit_operand(reg, adr);
1229 }
1230 }
1231
1232 void Assembler::comisd(XMMRegister dst, Address src) {
1233 // NOTE: dbx seems to decode this as comiss even though the
1234 // 0x66 is there. Strangly ucomisd comes out correct
1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1236 InstructionMark im(this);
1237 simd_prefix(dst, src, VEX_SIMD_66);
1238 emit_byte(0x2F);
1239 emit_operand(dst, src);
1240 }
1241
1242 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1243 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1244 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1245 emit_byte(0x2F);
1246 emit_byte(0xC0 | encode);
1247 }
1248
1249 void Assembler::comiss(XMMRegister dst, Address src) {
1250 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1251 InstructionMark im(this);
1252 simd_prefix(dst, src, VEX_SIMD_NONE);
1253 emit_byte(0x2F);
1254 emit_operand(dst, src);
1255 }
1256
1257 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1258 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1259 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1260 emit_byte(0x2F);
1261 emit_byte(0xC0 | encode);
1262 }
1263
1264 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1265 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1266 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1267 emit_byte(0xE6);
1268 emit_byte(0xC0 | encode);
1269 }
1270
1271 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1273 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1274 emit_byte(0x5B);
1275 emit_byte(0xC0 | encode);
1276 }
1277
1278 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1279 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1281 emit_byte(0x5A);
1282 emit_byte(0xC0 | encode);
1283 }
1284
1285 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1287 InstructionMark im(this);
1288 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1289 emit_byte(0x5A);
1290 emit_operand(dst, src);
1291 }
1292
1293 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1294 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1295 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1296 emit_byte(0x2A);
1297 emit_byte(0xC0 | encode);
1298 }
1299
1300 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1301 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1302 InstructionMark im(this);
1303 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1304 emit_byte(0x2A);
1305 emit_operand(dst, src);
1306 }
1307
1308 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1309 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1310 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1311 emit_byte(0x2A);
1312 emit_byte(0xC0 | encode);
1313 }
1314
1315 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1316 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1317 InstructionMark im(this);
1318 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1319 emit_byte(0x2A);
1320 emit_operand(dst, src);
1321 }
1322
1323 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1324 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1325 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1326 emit_byte(0x5A);
1327 emit_byte(0xC0 | encode);
1328 }
1329
1330 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1331 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1332 InstructionMark im(this);
1333 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1334 emit_byte(0x5A);
1335 emit_operand(dst, src);
1336 }
1337
1338
1339 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1341 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1342 emit_byte(0x2C);
1343 emit_byte(0xC0 | encode);
1344 }
1345
1346 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1347 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1348 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1349 emit_byte(0x2C);
1350 emit_byte(0xC0 | encode);
1351 }
1352
1353 void Assembler::decl(Address dst) {
1354 // Don't use it directly. Use MacroAssembler::decrement() instead.
1355 InstructionMark im(this);
1356 prefix(dst);
1357 emit_byte(0xFF);
1358 emit_operand(rcx, dst);
1359 }
1360
1361 void Assembler::divsd(XMMRegister dst, Address src) {
1362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1363 InstructionMark im(this);
1364 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1365 emit_byte(0x5E);
1366 emit_operand(dst, src);
1367 }
1368
1369 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1371 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1372 emit_byte(0x5E);
1373 emit_byte(0xC0 | encode);
1374 }
1375
1376 void Assembler::divss(XMMRegister dst, Address src) {
1377 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1378 InstructionMark im(this);
1379 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1380 emit_byte(0x5E);
1381 emit_operand(dst, src);
1382 }
1383
1384 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1385 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1386 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1387 emit_byte(0x5E);
1388 emit_byte(0xC0 | encode);
1389 }
1390
1391 void Assembler::emms() {
1392 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1393 emit_byte(0x0F);
1394 emit_byte(0x77);
1395 }
1396
1397 void Assembler::hlt() {
1398 emit_byte(0xF4);
1399 }
1400
1401 void Assembler::idivl(Register src) {
1402 int encode = prefix_and_encode(src->encoding());
1403 emit_byte(0xF7);
1404 emit_byte(0xF8 | encode);
1405 }
1406
1592 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1593 emit_byte(0x0F);
1594 emit_byte(0xBD);
1595 emit_byte(0xC0 | encode);
1596 }
1597
1598 // Emit mfence instruction
1599 void Assembler::mfence() {
1600 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1601 emit_byte( 0x0F );
1602 emit_byte( 0xAE );
1603 emit_byte( 0xF0 );
1604 }
1605
1606 void Assembler::mov(Register dst, Register src) {
1607 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1608 }
1609
1610 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1612 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1613 emit_byte(0x28);
1614 emit_byte(0xC0 | encode);
1615 }
1616
1617 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1618 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1619 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1620 emit_byte(0x28);
1621 emit_byte(0xC0 | encode);
1622 }
1623
1624 void Assembler::movb(Register dst, Address src) {
1625 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1626 InstructionMark im(this);
1627 prefix(src, dst, true);
1628 emit_byte(0x8A);
1629 emit_operand(dst, src);
1630 }
1631
1632
1633 void Assembler::movb(Address dst, int imm8) {
1634 InstructionMark im(this);
1635 prefix(dst);
1636 emit_byte(0xC6);
1637 emit_operand(rax, dst, 1);
1638 emit_byte(imm8);
1639 }
1640
1641
1642 void Assembler::movb(Address dst, Register src) {
1643 assert(src->has_byte_register(), "must have byte register");
1644 InstructionMark im(this);
1645 prefix(dst, src, true);
1646 emit_byte(0x88);
1647 emit_operand(src, dst);
1648 }
1649
1650 void Assembler::movdl(XMMRegister dst, Register src) {
1651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1652 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1653 emit_byte(0x6E);
1654 emit_byte(0xC0 | encode);
1655 }
1656
1657 void Assembler::movdl(Register dst, XMMRegister src) {
1658 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1659 // swap src/dst to get correct prefix
1660 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1661 emit_byte(0x7E);
1662 emit_byte(0xC0 | encode);
1663 }
1664
1665 void Assembler::movdl(XMMRegister dst, Address src) {
1666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1667 InstructionMark im(this);
1668 simd_prefix(dst, src, VEX_SIMD_66);
1669 emit_byte(0x6E);
1670 emit_operand(dst, src);
1671 }
1672
1673 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1675 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1676 emit_byte(0x6F);
1677 emit_byte(0xC0 | encode);
1678 }
1679
1680 void Assembler::movdqu(XMMRegister dst, Address src) {
1681 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1682 InstructionMark im(this);
1683 simd_prefix(dst, src, VEX_SIMD_F3);
1684 emit_byte(0x6F);
1685 emit_operand(dst, src);
1686 }
1687
1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1690 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1691 emit_byte(0x6F);
1692 emit_byte(0xC0 | encode);
1693 }
1694
1695 void Assembler::movdqu(Address dst, XMMRegister src) {
1696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1697 InstructionMark im(this);
1698 simd_prefix(dst, src, VEX_SIMD_F3);
1699 emit_byte(0x7F);
1700 emit_operand(src, dst);
1701 }
1702
1703 // Uses zero extension on 64bit
1704
1705 void Assembler::movl(Register dst, int32_t imm32) {
1706 int encode = prefix_and_encode(dst->encoding());
1707 emit_byte(0xB8 | encode);
1708 emit_long(imm32);
1709 }
1710
1711 void Assembler::movl(Register dst, Register src) {
1712 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1713 emit_byte(0x8B);
1714 emit_byte(0xC0 | encode);
1715 }
1716
1717 void Assembler::movl(Register dst, Address src) {
1718 InstructionMark im(this);
1725 InstructionMark im(this);
1726 prefix(dst);
1727 emit_byte(0xC7);
1728 emit_operand(rax, dst, 4);
1729 emit_long(imm32);
1730 }
1731
1732 void Assembler::movl(Address dst, Register src) {
1733 InstructionMark im(this);
1734 prefix(dst, src);
1735 emit_byte(0x89);
1736 emit_operand(src, dst);
1737 }
1738
1739 // New cpus require to use movsd and movss to avoid partial register stall
1740 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1741 // The selection is done in MacroAssembler::movdbl() and movflt().
1742 void Assembler::movlpd(XMMRegister dst, Address src) {
1743 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1744 InstructionMark im(this);
1745 simd_prefix(dst, dst, src, VEX_SIMD_66);
1746 emit_byte(0x12);
1747 emit_operand(dst, src);
1748 }
1749
1750 void Assembler::movq( MMXRegister dst, Address src ) {
1751 assert( VM_Version::supports_mmx(), "" );
1752 emit_byte(0x0F);
1753 emit_byte(0x6F);
1754 emit_operand(dst, src);
1755 }
1756
1757 void Assembler::movq( Address dst, MMXRegister src ) {
1758 assert( VM_Version::supports_mmx(), "" );
1759 emit_byte(0x0F);
1760 emit_byte(0x7F);
1761 // workaround gcc (3.2.1-7a) bug
1762 // In that version of gcc with only an emit_operand(MMX, Address)
1763 // gcc will tail jump and try and reverse the parameters completely
1764 // obliterating dst in the process. By having a version available
1765 // that doesn't need to swap the args at the tail jump the bug is
1766 // avoided.
1767 emit_operand(dst, src);
1768 }
1769
1770 void Assembler::movq(XMMRegister dst, Address src) {
1771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1772 InstructionMark im(this);
1773 simd_prefix(dst, src, VEX_SIMD_F3);
1774 emit_byte(0x7E);
1775 emit_operand(dst, src);
1776 }
1777
1778 void Assembler::movq(Address dst, XMMRegister src) {
1779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1780 InstructionMark im(this);
1781 simd_prefix(dst, src, VEX_SIMD_66);
1782 emit_byte(0xD6);
1783 emit_operand(src, dst);
1784 }
1785
1786 void Assembler::movsbl(Register dst, Address src) { // movsxb
1787 InstructionMark im(this);
1788 prefix(src, dst);
1789 emit_byte(0x0F);
1790 emit_byte(0xBE);
1791 emit_operand(dst, src);
1792 }
1793
1794 void Assembler::movsbl(Register dst, Register src) { // movsxb
1795 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1796 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1797 emit_byte(0x0F);
1798 emit_byte(0xBE);
1799 emit_byte(0xC0 | encode);
1800 }
1801
1802 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1805 emit_byte(0x10);
1806 emit_byte(0xC0 | encode);
1807 }
1808
1809 void Assembler::movsd(XMMRegister dst, Address src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionMark im(this);
1812 simd_prefix(dst, src, VEX_SIMD_F2);
1813 emit_byte(0x10);
1814 emit_operand(dst, src);
1815 }
1816
1817 void Assembler::movsd(Address dst, XMMRegister src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionMark im(this);
1820 simd_prefix(dst, src, VEX_SIMD_F2);
1821 emit_byte(0x11);
1822 emit_operand(src, dst);
1823 }
1824
1825 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1826 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1827 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1828 emit_byte(0x10);
1829 emit_byte(0xC0 | encode);
1830 }
1831
1832 void Assembler::movss(XMMRegister dst, Address src) {
1833 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1834 InstructionMark im(this);
1835 simd_prefix(dst, src, VEX_SIMD_F3);
1836 emit_byte(0x10);
1837 emit_operand(dst, src);
1838 }
1839
1840 void Assembler::movss(Address dst, XMMRegister src) {
1841 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1842 InstructionMark im(this);
1843 simd_prefix(dst, src, VEX_SIMD_F3);
1844 emit_byte(0x11);
1845 emit_operand(src, dst);
1846 }
1847
1848 void Assembler::movswl(Register dst, Address src) { // movsxw
1849 InstructionMark im(this);
1850 prefix(src, dst);
1851 emit_byte(0x0F);
1852 emit_byte(0xBF);
1853 emit_operand(dst, src);
1854 }
1855
1856 void Assembler::movswl(Register dst, Register src) { // movsxw
1857 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1858 emit_byte(0x0F);
1859 emit_byte(0xBF);
1860 emit_byte(0xC0 | encode);
1861 }
1862
1863 void Assembler::movw(Address dst, int imm16) {
1916 emit_byte(0xB7);
1917 emit_byte(0xC0 | encode);
1918 }
1919
1920 void Assembler::mull(Address src) {
1921 InstructionMark im(this);
1922 prefix(src);
1923 emit_byte(0xF7);
1924 emit_operand(rsp, src);
1925 }
1926
1927 void Assembler::mull(Register src) {
1928 int encode = prefix_and_encode(src->encoding());
1929 emit_byte(0xF7);
1930 emit_byte(0xE0 | encode);
1931 }
1932
1933 void Assembler::mulsd(XMMRegister dst, Address src) {
1934 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1935 InstructionMark im(this);
1936 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1937 emit_byte(0x59);
1938 emit_operand(dst, src);
1939 }
1940
1941 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1942 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1943 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1944 emit_byte(0x59);
1945 emit_byte(0xC0 | encode);
1946 }
1947
1948 void Assembler::mulss(XMMRegister dst, Address src) {
1949 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1950 InstructionMark im(this);
1951 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1952 emit_byte(0x59);
1953 emit_operand(dst, src);
1954 }
1955
1956 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1957 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1958 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1959 emit_byte(0x59);
1960 emit_byte(0xC0 | encode);
1961 }
1962
1963 void Assembler::negl(Register dst) {
1964 int encode = prefix_and_encode(dst->encoding());
1965 emit_byte(0xF7);
1966 emit_byte(0xD8 | encode);
1967 }
1968
1969 void Assembler::nop(int i) {
1970 #ifdef ASSERT
1971 assert(i > 0, " ");
1972 // The fancy nops aren't currently recognized by debuggers making it a
1973 // pain to disassemble code while debugging. If asserts are on clearly
1974 // speed is not an issue so simply use the single byte traditional nop
1975 // to do alignment.
1976
1977 for (; i > 0 ; i--) emit_byte(0x90);
1978 return;
2226 emit_arith_operand(0x81, rcx, dst, imm32);
2227 }
2228
2229 void Assembler::orl(Register dst, int32_t imm32) {
2230 prefix(dst);
2231 emit_arith(0x81, 0xC8, dst, imm32);
2232 }
2233
2234 void Assembler::orl(Register dst, Address src) {
2235 InstructionMark im(this);
2236 prefix(src, dst);
2237 emit_byte(0x0B);
2238 emit_operand(dst, src);
2239 }
2240
2241 void Assembler::orl(Register dst, Register src) {
2242 (void) prefix_and_encode(dst->encoding(), src->encoding());
2243 emit_arith(0x0B, 0xC0, dst, src);
2244 }
2245
2246 void Assembler::packuswb(XMMRegister dst, Address src) {
2247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2248 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2249 InstructionMark im(this);
2250 simd_prefix(dst, dst, src, VEX_SIMD_66);
2251 emit_byte(0x67);
2252 emit_operand(dst, src);
2253 }
2254
2255 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2257 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2258 emit_byte(0x67);
2259 emit_byte(0xC0 | encode);
2260 }
2261
2262 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2263 assert(VM_Version::supports_sse4_2(), "");
2264 InstructionMark im(this);
2265 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2266 emit_byte(0x61);
2267 emit_operand(dst, src);
2268 emit_byte(imm8);
2269 }
2270
2271 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2272 assert(VM_Version::supports_sse4_2(), "");
2273 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2274 emit_byte(0x61);
2275 emit_byte(0xC0 | encode);
2276 emit_byte(imm8);
2277 }
2278
2279 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2280 assert(VM_Version::supports_sse4_1(), "");
2281 InstructionMark im(this);
2282 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2283 emit_byte(0x30);
2284 emit_operand(dst, src);
2285 }
2286
2287 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2288 assert(VM_Version::supports_sse4_1(), "");
2289 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2290 emit_byte(0x30);
2291 emit_byte(0xC0 | encode);
2292 }
2293
2294 // generic
2295 void Assembler::pop(Register dst) {
2296 int encode = prefix_and_encode(dst->encoding());
2297 emit_byte(0x58 | encode);
2298 }
2299
2300 void Assembler::popcntl(Register dst, Address src) {
2301 assert(VM_Version::supports_popcnt(), "must support");
2302 InstructionMark im(this);
2303 emit_byte(0xF3);
2304 prefix(src, dst);
2305 emit_byte(0x0F);
2306 emit_byte(0xB8);
2307 emit_operand(dst, src);
2308 }
2309
2310 void Assembler::popcntl(Register dst, Register src) {
2311 assert(VM_Version::supports_popcnt(), "must support");
2312 emit_byte(0xF3);
2313 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2372 InstructionMark im(this);
2373 prefetch_prefix(src);
2374 emit_byte(0x18);
2375 emit_operand(rbx, src); // 3, src
2376 }
2377
2378 void Assembler::prefetchw(Address src) {
2379 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2380 InstructionMark im(this);
2381 prefetch_prefix(src);
2382 emit_byte(0x0D);
2383 emit_operand(rcx, src); // 1, src
2384 }
2385
2386 void Assembler::prefix(Prefix p) {
2387 a_byte(p);
2388 }
2389
2390 void Assembler::por(XMMRegister dst, XMMRegister src) {
2391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2392 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2393 emit_byte(0xEB);
2394 emit_byte(0xC0 | encode);
2395 }
2396
2397 void Assembler::por(XMMRegister dst, Address src) {
2398 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2399 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2400 InstructionMark im(this);
2401 simd_prefix(dst, dst, src, VEX_SIMD_66);
2402 emit_byte(0xEB);
2403 emit_operand(dst, src);
2404 }
2405
2406 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2407 assert(isByte(mode), "invalid value");
2408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2409 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2410 emit_byte(0x70);
2411 emit_byte(0xC0 | encode);
2412 emit_byte(mode & 0xFF);
2413
2414 }
2415
2416 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2417 assert(isByte(mode), "invalid value");
2418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2419 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2420 InstructionMark im(this);
2421 simd_prefix(dst, src, VEX_SIMD_66);
2422 emit_byte(0x70);
2423 emit_operand(dst, src);
2424 emit_byte(mode & 0xFF);
2425 }
2426
2427 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2428 assert(isByte(mode), "invalid value");
2429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2430 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
2431 emit_byte(0x70);
2432 emit_byte(0xC0 | encode);
2433 emit_byte(mode & 0xFF);
2434 }
2435
2436 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2437 assert(isByte(mode), "invalid value");
2438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2439 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2440 InstructionMark im(this);
2441 simd_prefix(dst, src, VEX_SIMD_F2);
2442 emit_byte(0x70);
2443 emit_operand(dst, src);
2444 emit_byte(mode & 0xFF);
2445 }
2446
2447 void Assembler::psrlq(XMMRegister dst, int shift) {
2448 // Shift 64 bit value logically right by specified number of bits.
2449 // HMM Table D-1 says sse2 or mmx.
2450 // Do not confuse it with psrldq SSE2 instruction which
2451 // shifts 128 bit value in xmm register by number of bytes.
2452 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2453 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
2454 emit_byte(0x73);
2455 emit_byte(0xC0 | encode);
2456 emit_byte(shift);
2457 }
2458
2459 void Assembler::psrldq(XMMRegister dst, int shift) {
2460 // Shift 128 bit value in xmm register by number of bytes.
2461 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2462 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2463 emit_byte(0x73);
2464 emit_byte(0xC0 | encode);
2465 emit_byte(shift);
2466 }
2467
2468 void Assembler::ptest(XMMRegister dst, Address src) {
2469 assert(VM_Version::supports_sse4_1(), "");
2470 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2471 InstructionMark im(this);
2472 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2473 emit_byte(0x17);
2474 emit_operand(dst, src);
2475 }
2476
2477 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2478 assert(VM_Version::supports_sse4_1(), "");
2479 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2480 emit_byte(0x17);
2481 emit_byte(0xC0 | encode);
2482 }
2483
2484 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2485 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2486 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2487 InstructionMark im(this);
2488 simd_prefix(dst, dst, src, VEX_SIMD_66);
2489 emit_byte(0x60);
2490 emit_operand(dst, src);
2491 }
2492
2493 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2496 emit_byte(0x60);
2497 emit_byte(0xC0 | encode);
2498 }
2499
2500 void Assembler::punpckldq(XMMRegister dst, Address src) {
2501 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2502 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2503 InstructionMark im(this);
2504 simd_prefix(dst, dst, src, VEX_SIMD_66);
2505 emit_byte(0x62);
2506 emit_operand(dst, src);
2507 }
2508
2509 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2510 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2511 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2512 emit_byte(0x62);
2513 emit_byte(0xC0 | encode);
2514 }
2515
2516 void Assembler::push(int32_t imm32) {
2517 // in 64bits we push 64bits onto the stack but only
2518 // take a 32bit immediate
2519 emit_byte(0x68);
2520 emit_long(imm32);
2521 }
2522
2523 void Assembler::push(Register src) {
2524 int encode = prefix_and_encode(src->encoding());
2525
2526 emit_byte(0x50 | encode);
2527 }
2528
2529 void Assembler::pushf() {
2530 emit_byte(0x9C);
2531 }
2532
2533 #ifndef _LP64 // no 32bit push/pop on amd64
2534 void Assembler::pushl(Address src) {
2535 // Note this will push 64bit on 64bit
2536 InstructionMark im(this);
2537 prefix(src);
2538 emit_byte(0xFF);
2539 emit_operand(rsi, src);
2540 }
2541 #endif
2542
2543 void Assembler::pxor(XMMRegister dst, Address src) {
2544 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2545 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2546 InstructionMark im(this);
2547 simd_prefix(dst, dst, src, VEX_SIMD_66);
2548 emit_byte(0xEF);
2549 emit_operand(dst, src);
2550 }
2551
2552 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2554 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2555 emit_byte(0xEF);
2556 emit_byte(0xC0 | encode);
2557 }
2558
2559 void Assembler::rcll(Register dst, int imm8) {
2560 assert(isShiftCount(imm8), "illegal shift count");
2561 int encode = prefix_and_encode(dst->encoding());
2562 if (imm8 == 1) {
2563 emit_byte(0xD1);
2564 emit_byte(0xD0 | encode);
2565 } else {
2566 emit_byte(0xC1);
2567 emit_byte(0xD0 | encode);
2568 emit_byte(imm8);
2569 }
2570 }
2571
2572 // copies data from [esi] to [edi] using rcx pointer sized words
2573 // generic
2574 void Assembler::rep_mov() {
2696 void Assembler::shrl(Register dst, int imm8) {
2697 assert(isShiftCount(imm8), "illegal shift count");
2698 int encode = prefix_and_encode(dst->encoding());
2699 emit_byte(0xC1);
2700 emit_byte(0xE8 | encode);
2701 emit_byte(imm8);
2702 }
2703
2704 void Assembler::shrl(Register dst) {
2705 int encode = prefix_and_encode(dst->encoding());
2706 emit_byte(0xD3);
2707 emit_byte(0xE8 | encode);
2708 }
2709
2710 // copies a single word from [esi] to [edi]
2711 void Assembler::smovl() {
2712 emit_byte(0xA5);
2713 }
2714
2715 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2717 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2718 emit_byte(0x51);
2719 emit_byte(0xC0 | encode);
2720 }
2721
2722 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2724 InstructionMark im(this);
2725 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2726 emit_byte(0x51);
2727 emit_operand(dst, src);
2728 }
2729
2730 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2731 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2733 emit_byte(0x51);
2734 emit_byte(0xC0 | encode);
2735 }
2736
2737 void Assembler::sqrtss(XMMRegister dst, Address src) {
2738 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2739 InstructionMark im(this);
2740 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2741 emit_byte(0x51);
2742 emit_operand(dst, src);
2743 }
2744
2745 void Assembler::stmxcsr( Address dst) {
2746 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2747 InstructionMark im(this);
2748 prefix(dst);
2749 emit_byte(0x0F);
2750 emit_byte(0xAE);
2751 emit_operand(as_Register(3), dst);
2752 }
2753
2754 void Assembler::subl(Address dst, int32_t imm32) {
2755 InstructionMark im(this);
2756 prefix(dst);
2757 emit_arith_operand(0x81, rbp, dst, imm32);
2758 }
2759
2760 void Assembler::subl(Address dst, Register src) {
2766
2767 void Assembler::subl(Register dst, int32_t imm32) {
2768 prefix(dst);
2769 emit_arith(0x81, 0xE8, dst, imm32);
2770 }
2771
2772 void Assembler::subl(Register dst, Address src) {
2773 InstructionMark im(this);
2774 prefix(src, dst);
2775 emit_byte(0x2B);
2776 emit_operand(dst, src);
2777 }
2778
2779 void Assembler::subl(Register dst, Register src) {
2780 (void) prefix_and_encode(dst->encoding(), src->encoding());
2781 emit_arith(0x2B, 0xC0, dst, src);
2782 }
2783
2784 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2787 emit_byte(0x5C);
2788 emit_byte(0xC0 | encode);
2789 }
2790
2791 void Assembler::subsd(XMMRegister dst, Address src) {
2792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2793 InstructionMark im(this);
2794 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2795 emit_byte(0x5C);
2796 emit_operand(dst, src);
2797 }
2798
2799 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2800 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2801 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2802 emit_byte(0x5C);
2803 emit_byte(0xC0 | encode);
2804 }
2805
2806 void Assembler::subss(XMMRegister dst, Address src) {
2807 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2808 InstructionMark im(this);
2809 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2810 emit_byte(0x5C);
2811 emit_operand(dst, src);
2812 }
2813
2814 void Assembler::testb(Register dst, int imm8) {
2815 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2816 (void) prefix_and_encode(dst->encoding(), true);
2817 emit_arith_b(0xF6, 0xC0, dst, imm8);
2818 }
2819
2820 void Assembler::testl(Register dst, int32_t imm32) {
2821 // not using emit_arith because test
2822 // doesn't support sign-extension of
2823 // 8bit operands
2824 int encode = dst->encoding();
2825 if (encode == 0) {
2826 emit_byte(0xA9);
2827 } else {
2828 encode = prefix_and_encode(encode);
2829 emit_byte(0xF7);
2830 emit_byte(0xC0 | encode);
2831 }
2832 emit_long(imm32);
2833 }
2834
2835 void Assembler::testl(Register dst, Register src) {
2836 (void) prefix_and_encode(dst->encoding(), src->encoding());
2837 emit_arith(0x85, 0xC0, dst, src);
2838 }
2839
2840 void Assembler::testl(Register dst, Address src) {
2841 InstructionMark im(this);
2842 prefix(src, dst);
2843 emit_byte(0x85);
2844 emit_operand(dst, src);
2845 }
2846
2847 void Assembler::ucomisd(XMMRegister dst, Address src) {
2848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2849 InstructionMark im(this);
2850 simd_prefix(dst, src, VEX_SIMD_66);
2851 emit_byte(0x2E);
2852 emit_operand(dst, src);
2853 }
2854
2855 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2856 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2857 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2858 emit_byte(0x2E);
2859 emit_byte(0xC0 | encode);
2860 }
2861
2862 void Assembler::ucomiss(XMMRegister dst, Address src) {
2863 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2864 InstructionMark im(this);
2865 simd_prefix(dst, src, VEX_SIMD_NONE);
2866 emit_byte(0x2E);
2867 emit_operand(dst, src);
2868 }
2869
2870 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2871 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2872 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
2873 emit_byte(0x2E);
2874 emit_byte(0xC0 | encode);
2875 }
2876
2877
2878 void Assembler::xaddl(Address dst, Register src) {
2879 InstructionMark im(this);
2880 prefix(dst, src);
2881 emit_byte(0x0F);
2882 emit_byte(0xC1);
2883 emit_operand(src, dst);
2884 }
2885
2886 void Assembler::xchgl(Register dst, Address src) { // xchg
2887 InstructionMark im(this);
2888 prefix(src, dst);
2889 emit_byte(0x87);
2890 emit_operand(dst, src);
2891 }
2892
2898
2899 void Assembler::xorl(Register dst, int32_t imm32) {
2900 prefix(dst);
2901 emit_arith(0x81, 0xF0, dst, imm32);
2902 }
2903
2904 void Assembler::xorl(Register dst, Address src) {
2905 InstructionMark im(this);
2906 prefix(src, dst);
2907 emit_byte(0x33);
2908 emit_operand(dst, src);
2909 }
2910
2911 void Assembler::xorl(Register dst, Register src) {
2912 (void) prefix_and_encode(dst->encoding(), src->encoding());
2913 emit_arith(0x33, 0xC0, dst, src);
2914 }
2915
2916 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2917 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2918 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2919 emit_byte(0x57);
2920 emit_byte(0xC0 | encode);
2921 }
2922
2923 void Assembler::xorpd(XMMRegister dst, Address src) {
2924 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2925 InstructionMark im(this);
2926 simd_prefix(dst, dst, src, VEX_SIMD_66);
2927 emit_byte(0x57);
2928 emit_operand(dst, src);
2929 }
2930
2931
2932 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2933 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2934 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
2935 emit_byte(0x57);
2936 emit_byte(0xC0 | encode);
2937 }
2938
2939 void Assembler::xorps(XMMRegister dst, Address src) {
2940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2941 InstructionMark im(this);
2942 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
2943 emit_byte(0x57);
2944 emit_operand(dst, src);
2945 }
2946
2947 #ifndef _LP64
2948 // 32bit only pieces of the assembler
2949
2950 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2951 // NO PREFIX AS NEVER 64BIT
2952 InstructionMark im(this);
2953 emit_byte(0x81);
2954 emit_byte(0xF8 | src1->encoding());
2955 emit_data(imm32, rspec, 0);
2956 }
2957
2958 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2959 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2960 InstructionMark im(this);
2961 emit_byte(0x81);
2962 emit_operand(rdi, src1);
3384
3385 void Assembler::fucomip(int i) {
3386 // make sure the instruction is supported (introduced for P6, together with cmov)
3387 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3388 emit_farith(0xDF, 0xE8, i);
3389 }
3390
3391 void Assembler::fwait() {
3392 emit_byte(0x9B);
3393 }
3394
3395 void Assembler::fxch(int i) {
3396 emit_farith(0xD9, 0xC8, i);
3397 }
3398
3399 void Assembler::fyl2x() {
3400 emit_byte(0xD9);
3401 emit_byte(0xF1);
3402 }
3403
3404 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
3405 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
3406
3407 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3408 if (pre > 0) {
3409 emit_byte(simd_pre[pre]);
3410 }
3411 if (rex_w) {
3412 prefixq(adr, xreg);
3413 } else {
3414 prefix(adr, xreg);
3415 }
3416 if (opc > 0) {
3417 emit_byte(0x0F);
3418 int opc2 = simd_opc[opc];
3419 if (opc2 > 0) {
3420 emit_byte(opc2);
3421 }
3422 }
3423 }
3424
3425 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3426 if (pre > 0) {
3427 emit_byte(simd_pre[pre]);
3428 }
3429 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
3430 prefix_and_encode(dst_enc, src_enc);
3431 if (opc > 0) {
3432 emit_byte(0x0F);
3433 int opc2 = simd_opc[opc];
3434 if (opc2 > 0) {
3435 emit_byte(opc2);
3436 }
3437 }
3438 return encode;
3439 }
3440
3441
3442 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
3443 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
3444 prefix(VEX_3bytes);
3445
3446 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
3447 byte1 = (~byte1) & 0xE0;
3448 byte1 |= opc;
3449 a_byte(byte1);
3450
3451 int byte2 = ((~nds_enc) & 0xf) << 3;
3452 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
3453 emit_byte(byte2);
3454 } else {
3455 prefix(VEX_2bytes);
3456
3457 int byte1 = vex_r ? VEX_R : 0;
3458 byte1 = (~byte1) & 0x80;
3459 byte1 |= ((~nds_enc) & 0xf) << 3;
3460 byte1 |= (vector256 ? 4 : 0) | pre;
3461 emit_byte(byte1);
3462 }
3463 }
3464
3465 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
3466 bool vex_r = (xreg_enc >= 8);
3467 bool vex_b = adr.base_needs_rex();
3468 bool vex_x = adr.index_needs_rex();
3469 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3470 }
3471
3472 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
3473 bool vex_r = (dst_enc >= 8);
3474 bool vex_b = (src_enc >= 8);
3475 bool vex_x = false;
3476 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3477 return (((dst_enc & 7) << 3) | (src_enc & 7));
3478 }
3479
3480
3481 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3482 if (UseAVX > 0) {
3483 int xreg_enc = xreg->encoding();
3484 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3485 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
3486 } else {
3487 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
3488 rex_prefix(adr, xreg, pre, opc, rex_w);
3489 }
3490 }
3491
3492 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3493 int dst_enc = dst->encoding();
3494 int src_enc = src->encoding();
3495 if (UseAVX > 0) {
3496 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3497 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
3498 } else {
3499 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
3500 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
3501 }
3502 }
3503
3504 #ifndef _LP64
3505
3506 void Assembler::incl(Register dst) {
3507 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3508 emit_byte(0x40 | dst->encoding());
3509 }
3510
3511 void Assembler::lea(Register dst, Address src) {
3512 leal(dst, src);
3513 }
3514
3515 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3516 InstructionMark im(this);
3517 emit_byte(0xC7);
3518 emit_operand(rax, dst);
3519 emit_data((int)imm32, rspec, 0);
3520 }
3521
3522 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3523 InstructionMark im(this);
3845 prefix(REX_X);
3846 }
3847 }
3848 } else {
3849 if (adr.base_needs_rex()) {
3850 if (adr.index_needs_rex()) {
3851 prefix(REX_RXB);
3852 } else {
3853 prefix(REX_RB);
3854 }
3855 } else {
3856 if (adr.index_needs_rex()) {
3857 prefix(REX_RX);
3858 } else {
3859 prefix(REX_R);
3860 }
3861 }
3862 }
3863 }
3864
3865 void Assembler::prefixq(Address adr, XMMRegister src) {
3866 if (src->encoding() < 8) {
3867 if (adr.base_needs_rex()) {
3868 if (adr.index_needs_rex()) {
3869 prefix(REX_WXB);
3870 } else {
3871 prefix(REX_WB);
3872 }
3873 } else {
3874 if (adr.index_needs_rex()) {
3875 prefix(REX_WX);
3876 } else {
3877 prefix(REX_W);
3878 }
3879 }
3880 } else {
3881 if (adr.base_needs_rex()) {
3882 if (adr.index_needs_rex()) {
3883 prefix(REX_WRXB);
3884 } else {
3885 prefix(REX_WRB);
3886 }
3887 } else {
3888 if (adr.index_needs_rex()) {
3889 prefix(REX_WRX);
3890 } else {
3891 prefix(REX_WR);
3892 }
3893 }
3894 }
3895 }
3896
3897 void Assembler::adcq(Register dst, int32_t imm32) {
3898 (void) prefixq_and_encode(dst->encoding());
3899 emit_arith(0x81, 0xD0, dst, imm32);
3900 }
3901
3902 void Assembler::adcq(Register dst, Address src) {
3903 InstructionMark im(this);
3904 prefixq(src, dst);
3905 emit_byte(0x13);
3906 emit_operand(dst, src);
3907 }
3908
3909 void Assembler::adcq(Register dst, Register src) {
3910 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3911 emit_arith(0x13, 0xC0, dst, src);
3912 }
3913
3914 void Assembler::addq(Address dst, int32_t imm32) {
3915 InstructionMark im(this);
3916 prefixq(dst);
4039 emit_arith(0x3B, 0xC0, dst, src);
4040 }
4041
4042 void Assembler::cmpq(Register dst, Address src) {
4043 InstructionMark im(this);
4044 prefixq(src, dst);
4045 emit_byte(0x3B);
4046 emit_operand(dst, src);
4047 }
4048
4049 void Assembler::cmpxchgq(Register reg, Address adr) {
4050 InstructionMark im(this);
4051 prefixq(adr, reg);
4052 emit_byte(0x0F);
4053 emit_byte(0xB1);
4054 emit_operand(reg, adr);
4055 }
4056
4057 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
4058 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4059 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
4060 emit_byte(0x2A);
4061 emit_byte(0xC0 | encode);
4062 }
4063
4064 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
4065 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4066 InstructionMark im(this);
4067 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
4068 emit_byte(0x2A);
4069 emit_operand(dst, src);
4070 }
4071
4072 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
4073 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4074 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
4075 emit_byte(0x2A);
4076 emit_byte(0xC0 | encode);
4077 }
4078
4079 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
4080 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4081 InstructionMark im(this);
4082 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
4083 emit_byte(0x2A);
4084 emit_operand(dst, src);
4085 }
4086
4087 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
4088 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4089 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
4090 emit_byte(0x2C);
4091 emit_byte(0xC0 | encode);
4092 }
4093
4094 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
4095 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4096 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
4097 emit_byte(0x2C);
4098 emit_byte(0xC0 | encode);
4099 }
4100
4101 void Assembler::decl(Register dst) {
4102 // Don't use it directly. Use MacroAssembler::decrementl() instead.
4103 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
4104 int encode = prefix_and_encode(dst->encoding());
4105 emit_byte(0xFF);
4106 emit_byte(0xC8 | encode);
4107 }
4108
4109 void Assembler::decq(Register dst) {
4110 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4111 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4112 int encode = prefixq_and_encode(dst->encoding());
4113 emit_byte(0xFF);
4114 emit_byte(0xC8 | encode);
4115 }
4116
4236
4237 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4238 InstructionMark im(this);
4239 prefix(src1);
4240 emit_byte(0x81);
4241 emit_operand(rax, src1, 4);
4242 emit_data((int)imm32, rspec, narrow_oop_operand);
4243 }
4244
4245 void Assembler::lzcntq(Register dst, Register src) {
4246 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4247 emit_byte(0xF3);
4248 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4249 emit_byte(0x0F);
4250 emit_byte(0xBD);
4251 emit_byte(0xC0 | encode);
4252 }
4253
4254 void Assembler::movdq(XMMRegister dst, Register src) {
4255 // table D-1 says MMX/SSE2
4256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4257 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
4258 emit_byte(0x6E);
4259 emit_byte(0xC0 | encode);
4260 }
4261
4262 void Assembler::movdq(Register dst, XMMRegister src) {
4263 // table D-1 says MMX/SSE2
4264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4265 // swap src/dst to get correct prefix
4266 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
4267 emit_byte(0x7E);
4268 emit_byte(0xC0 | encode);
4269 }
4270
4271 void Assembler::movq(Register dst, Register src) {
4272 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4273 emit_byte(0x8B);
4274 emit_byte(0xC0 | encode);
4275 }
4276
4277 void Assembler::movq(Register dst, Address src) {
4278 InstructionMark im(this);
4279 prefixq(src, dst);
4280 emit_byte(0x8B);
4281 emit_operand(dst, src);
4282 }
4283
4284 void Assembler::movq(Address dst, Register src) {
4285 InstructionMark im(this);
4286 prefixq(dst, src);
5805 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5806 }
5807 }
5808
5809 #endif // _LP64
5810
5811 // Now versions that are common to 32/64 bit
5812
5813 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5814 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5815 }
5816
5817 void MacroAssembler::addptr(Register dst, Register src) {
5818 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5819 }
5820
5821 void MacroAssembler::addptr(Address dst, Register src) {
5822 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5823 }
5824
5825 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
5826 if (reachable(src)) {
5827 Assembler::addsd(dst, as_Address(src));
5828 } else {
5829 lea(rscratch1, src);
5830 Assembler::addsd(dst, Address(rscratch1, 0));
5831 }
5832 }
5833
5834 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
5835 if (reachable(src)) {
5836 addss(dst, as_Address(src));
5837 } else {
5838 lea(rscratch1, src);
5839 addss(dst, Address(rscratch1, 0));
5840 }
5841 }
5842
5843 void MacroAssembler::align(int modulus) {
5844 if (offset() % modulus != 0) {
5845 nop(modulus - (offset() % modulus));
5846 }
5847 }
5848
5849 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5850 // Used in sign-masking with aligned address.
5851 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
5852 if (reachable(src)) {
5853 Assembler::andpd(dst, as_Address(src));
5854 } else {
5855 lea(rscratch1, src);
5856 Assembler::andpd(dst, Address(rscratch1, 0));
5857 }
5858 }
5859
5860 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
5861 // Used in sign-masking with aligned address.
5862 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
5863 if (reachable(src)) {
5864 Assembler::andps(dst, as_Address(src));
5865 } else {
5866 lea(rscratch1, src);
5867 Assembler::andps(dst, Address(rscratch1, 0));
5868 }
5869 }
5870
5871 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5872 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5873 }
5874
5875 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5876 pushf();
5877 if (os::is_MP())
5878 lock();
5879 incrementl(counter_addr);
5880 popf();
5881 }
5882
5883 // Writes to stack successive pages until offset reached to check for
5884 // stack overflow + shadow pages. This clobbers tmp.
5885 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5886 movptr(tmp, rsp);
5887 // Bang stack for total size given plus shadow page size.
5888 // Bang one page at a time because large size can bang beyond yellow and
5889 // red zones.
5890 Label loop;
6424
6425 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6426 if (reachable(adr)) {
6427 if (os::is_MP())
6428 lock();
6429 cmpxchgptr(reg, as_Address(adr));
6430 } else {
6431 lea(rscratch1, adr);
6432 if (os::is_MP())
6433 lock();
6434 cmpxchgptr(reg, Address(rscratch1, 0));
6435 }
6436 }
6437
6438 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6439 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6440 }
6441
6442 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6443 if (reachable(src)) {
6444 Assembler::comisd(dst, as_Address(src));
6445 } else {
6446 lea(rscratch1, src);
6447 Assembler::comisd(dst, Address(rscratch1, 0));
6448 }
6449 }
6450
6451 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6452 if (reachable(src)) {
6453 Assembler::comiss(dst, as_Address(src));
6454 } else {
6455 lea(rscratch1, src);
6456 Assembler::comiss(dst, Address(rscratch1, 0));
6457 }
6458 }
6459
6460
6461 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6462 Condition negated_cond = negate_condition(cond);
6463 Label L;
6464 jcc(negated_cond, L);
6465 atomic_incl(counter_addr);
6466 bind(L);
6467 }
6468
6469 int MacroAssembler::corrected_idivl(Register reg) {
6470 // Full implementation of Java idiv and irem; checks for
6471 // special case as described in JVM spec., p.243 & p.271.
6472 // The function returns the (pc) offset of the idivl
6473 // instruction - may be needed for implicit exceptions.
6474 //
6475 // normal case special case
6476 //
6520 /* else */ { subl(dst, value) ; return; }
6521 }
6522
6523 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6524 assert (shift_value > 0, "illegal shift value");
6525 Label _is_positive;
6526 testl (reg, reg);
6527 jcc (Assembler::positive, _is_positive);
6528 int offset = (1 << shift_value) - 1 ;
6529
6530 if (offset == 1) {
6531 incrementl(reg);
6532 } else {
6533 addl(reg, offset);
6534 }
6535
6536 bind (_is_positive);
6537 sarl(reg, shift_value);
6538 }
6539
6540 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
6541 if (reachable(src)) {
6542 Assembler::divsd(dst, as_Address(src));
6543 } else {
6544 lea(rscratch1, src);
6545 Assembler::divsd(dst, Address(rscratch1, 0));
6546 }
6547 }
6548
6549 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
6550 if (reachable(src)) {
6551 Assembler::divss(dst, as_Address(src));
6552 } else {
6553 lea(rscratch1, src);
6554 Assembler::divss(dst, Address(rscratch1, 0));
6555 }
6556 }
6557
6558 // !defined(COMPILER2) is because of stupid core builds
6559 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6560 void MacroAssembler::empty_FPU_stack() {
6561 if (VM_Version::supports_mmx()) {
6562 emms();
6563 } else {
6564 for (int i = 8; i-- > 0; ) ffree(i);
6565 }
6566 }
6567 #endif // !LP64 || C1 || !C2
6568
6569
6570 // Defines obj, preserves var_size_in_bytes
6571 void MacroAssembler::eden_allocate(Register obj,
6572 Register var_size_in_bytes,
6573 int con_size_in_bytes,
6574 Register t1,
6575 Label& slow_case) {
6576 assert(obj == rax, "obj must be in rax, for cmpxchg");
6577 assert_different_registers(obj, var_size_in_bytes, t1);
6977 }
6978 }
6979
6980 void MacroAssembler::movptr(Register dst, Register src) {
6981 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6982 }
6983
6984 void MacroAssembler::movptr(Register dst, Address src) {
6985 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6986 }
6987
6988 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6989 void MacroAssembler::movptr(Register dst, intptr_t src) {
6990 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6991 }
6992
6993 void MacroAssembler::movptr(Address dst, Register src) {
6994 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6995 }
6996
6997 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
6998 if (reachable(src)) {
6999 Assembler::movsd(dst, as_Address(src));
7000 } else {
7001 lea(rscratch1, src);
7002 Assembler::movsd(dst, Address(rscratch1, 0));
7003 }
7004 }
7005
7006 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
7007 if (reachable(src)) {
7008 Assembler::movss(dst, as_Address(src));
7009 } else {
7010 lea(rscratch1, src);
7011 Assembler::movss(dst, Address(rscratch1, 0));
7012 }
7013 }
7014
7015 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
7016 if (reachable(src)) {
7017 Assembler::mulsd(dst, as_Address(src));
7018 } else {
7019 lea(rscratch1, src);
7020 Assembler::mulsd(dst, Address(rscratch1, 0));
7021 }
7022 }
7023
7024 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
7025 if (reachable(src)) {
7026 Assembler::mulss(dst, as_Address(src));
7027 } else {
7028 lea(rscratch1, src);
7029 Assembler::mulss(dst, Address(rscratch1, 0));
7030 }
7031 }
7032
7033 void MacroAssembler::null_check(Register reg, int offset) {
7034 if (needs_explicit_null_check(offset)) {
7035 // provoke OS NULL exception if reg = NULL by
7036 // accessing M[reg] w/o changing any (non-CC) registers
7037 // NOTE: cmpl is plenty here to provoke a segv
7038 cmpptr(rax, Address(reg, 0));
7039 // Note: should probably use testl(rax, Address(reg, 0));
7040 // may be shorter code (however, this version of
7041 // testl needs to be implemented first)
7042 } else {
7043 // nothing to do, (later) access of M[reg + offset]
7044 // will provoke OS NULL exception if reg = NULL
7045 }
7046 }
7047
7048 void MacroAssembler::os_breakpoint() {
7049 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
7050 // (e.g., MSVC can't call ps() otherwise)
7051 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
7052 }
7191 } else {
7192 shll(reg, 24);
7193 sarl(reg, 24);
7194 }
7195 }
7196
7197 void MacroAssembler::sign_extend_short(Register reg) {
7198 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
7199 movswl(reg, reg); // movsxw
7200 } else {
7201 shll(reg, 16);
7202 sarl(reg, 16);
7203 }
7204 }
7205
7206 void MacroAssembler::testl(Register dst, AddressLiteral src) {
7207 assert(reachable(src), "Address should be reachable");
7208 testl(dst, as_Address(src));
7209 }
7210
7211 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
7212 if (reachable(src)) {
7213 Assembler::sqrtsd(dst, as_Address(src));
7214 } else {
7215 lea(rscratch1, src);
7216 Assembler::sqrtsd(dst, Address(rscratch1, 0));
7217 }
7218 }
7219
7220 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
7221 if (reachable(src)) {
7222 Assembler::sqrtss(dst, as_Address(src));
7223 } else {
7224 lea(rscratch1, src);
7225 Assembler::sqrtss(dst, Address(rscratch1, 0));
7226 }
7227 }
7228
7229 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
7230 if (reachable(src)) {
7231 Assembler::subsd(dst, as_Address(src));
7232 } else {
7233 lea(rscratch1, src);
7234 Assembler::subsd(dst, Address(rscratch1, 0));
7235 }
7236 }
7237
7238 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
7239 if (reachable(src)) {
7240 Assembler::subss(dst, as_Address(src));
7241 } else {
7242 lea(rscratch1, src);
7243 Assembler::subss(dst, Address(rscratch1, 0));
7244 }
7245 }
7246
7247 //////////////////////////////////////////////////////////////////////////////////
7248 #ifndef SERIALGC
7249
7250 void MacroAssembler::g1_write_barrier_pre(Register obj,
7251 Register pre_val,
7252 Register thread,
7253 Register tmp,
7254 bool tosca_live,
7255 bool expand_call) {
7256
7257 // If expand_call is true then we expand the call_VM_leaf macro
7258 // directly to skip generating the check by
7259 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
7260
7261 #ifdef _LP64
7262 assert(thread == r15_thread, "must be");
7263 #endif // _LP64
7264
7265 Label done;
7266 Label runtime;
8112 }
8113
8114 if (L_failure == &L_fallthrough)
8115 jccb(Assembler::notEqual, *L_failure);
8116 else jcc(Assembler::notEqual, *L_failure);
8117
8118 // Success. Cache the super we found and proceed in triumph.
8119 movptr(super_cache_addr, super_klass);
8120
8121 if (L_success != &L_fallthrough) {
8122 jmp(*L_success);
8123 }
8124
8125 #undef IS_A_TEMP
8126
8127 bind(L_fallthrough);
8128 }
8129
8130
8131 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
8132 if (reachable(src)) {
8133 Assembler::ucomisd(dst, as_Address(src));
8134 } else {
8135 lea(rscratch1, src);
8136 Assembler::ucomisd(dst, Address(rscratch1, 0));
8137 }
8138 }
8139
8140 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
8141 if (reachable(src)) {
8142 Assembler::ucomiss(dst, as_Address(src));
8143 } else {
8144 lea(rscratch1, src);
8145 Assembler::ucomiss(dst, Address(rscratch1, 0));
8146 }
8147 }
8148
8149 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
8150 // Used in sign-bit flipping with aligned address.
8151 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
8152 if (reachable(src)) {
8153 Assembler::xorpd(dst, as_Address(src));
8154 } else {
8155 lea(rscratch1, src);
8156 Assembler::xorpd(dst, Address(rscratch1, 0));
8157 }
8158 }
8159
8160 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
8161 // Used in sign-bit flipping with aligned address.
8162 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
8163 if (reachable(src)) {
8164 Assembler::xorps(dst, as_Address(src));
8165 } else {
8166 lea(rscratch1, src);
8167 Assembler::xorps(dst, Address(rscratch1, 0));
8168 }
8169 }
8170
8171 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
8172 if (VM_Version::supports_cmov()) {
8173 cmovl(cc, dst, src);
8174 } else {
8175 Label L;
8176 jccb(negate_condition(cc), L);
8177 movl(dst, src);
8178 bind(L);
8179 }
8180 }
8181
8182 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
8183 if (VM_Version::supports_cmov()) {
8184 cmovl(cc, dst, src);
8185 } else {
8186 Label L;
8187 jccb(negate_condition(cc), L);
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