1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 class BiasedLockingCounters;
29
30 // Contains all the definitions needed for x86 assembly code generation.
31
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
51
52
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
56
57 #ifdef _WIN64
58
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
63
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
68
69 #else
70
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
77
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
86
87 #endif // _WIN64
88
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
104
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
117
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
126
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
129
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
132
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
139
140 #endif // _LP64
141
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
144
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
150
151 class ArrayAddress;
152
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
178
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
185
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
191
192 public:
193
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
202
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
205
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
212
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
221
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
231
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
238 Address a = (*this);
239 a._disp += disp.constant_or_zero() * scale_size(scale);
240 if (disp.is_register()) {
241 assert(!a.index()->is_valid(), "competing indexes");
242 a._index = disp.as_register();
243 a._scale = scale;
244 }
245 return a;
246 }
247 bool is_same_address(Address a) const {
248 // disregard _rspec
249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
250 }
251
252 // The following two overloads are used in connection with the
253 // ByteSize type (see sizes.hpp). They simplify the use of
254 // ByteSize'd arguments in assembly code. Note that their equivalent
255 // for the optimized build are the member functions with int disp
256 // argument since ByteSize is mapped to an int type in that case.
257 //
258 // Note: DO NOT introduce similar overloaded functions for WordSize
259 // arguments as in the optimized mode, both ByteSize and WordSize
260 // are mapped to the same type and thus the compiler cannot make a
261 // distinction anymore (=> compiler errors).
262
263 #ifdef ASSERT
264 Address(Register base, ByteSize disp)
265 : _base(base),
266 _index(noreg),
267 _scale(no_scale),
268 _disp(in_bytes(disp)) {
269 }
270
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
272 : _base(base),
273 _index(index),
274 _scale(scale),
275 _disp(in_bytes(disp)) {
276 assert(!index->is_valid() == (scale == Address::no_scale),
277 "inconsistent address");
278 }
279
280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
281 : _base (base),
282 _index(index.register_or_noreg()),
283 _scale(scale),
284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
285 if (!index.is_register()) scale = Address::no_scale;
286 assert(!_index->is_valid() == (scale == Address::no_scale),
287 "inconsistent address");
288 }
289
290 #endif // ASSERT
291
292 // accessors
293 bool uses(Register reg) const { return _base == reg || _index == reg; }
294 Register base() const { return _base; }
295 Register index() const { return _index; }
296 ScaleFactor scale() const { return _scale; }
297 int disp() const { return _disp; }
298
299 // Convert the raw encoding form into the form expected by the constructor for
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert
301 // that to noreg for the Address constructor.
302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
303
304 static Address make_array(ArrayAddress);
305
306 private:
307 bool base_needs_rex() const {
308 return _base != noreg && _base->encoding() >= 8;
309 }
310
311 bool index_needs_rex() const {
312 return _index != noreg &&_index->encoding() >= 8;
313 }
314
315 relocInfo::relocType reloc() const { return _rspec.type(); }
316
317 friend class Assembler;
318 friend class MacroAssembler;
319 friend class LIR_Assembler; // base/index/scale/disp
320 };
321
322 //
323 // AddressLiteral has been split out from Address because operands of this type
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
325 // the few instructions that need to deal with address literals are unique and the
326 // MacroAssembler does not have to implement every instruction in the Assembler
327 // in order to search for address literals that may need special handling depending
328 // on the instruction and the platform. As small step on the way to merging i486/amd64
329 // directories.
330 //
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
332 friend class ArrayAddress;
333 RelocationHolder _rspec;
334 // Typically we use AddressLiterals we want to use their rval
335 // However in some situations we want the lval (effect address) of the item.
336 // We provide a special factory for making those lvals.
337 bool _is_lval;
338
339 // If the target is far we'll need to load the ea of this to
340 // a register to reach it. Otherwise if near we can do rip
341 // relative addressing.
342
343 address _target;
344
345 protected:
346 // creation
347 AddressLiteral()
348 : _is_lval(false),
349 _target(NULL)
350 {}
351
352 public:
353
354
355 AddressLiteral(address target, relocInfo::relocType rtype);
356
357 AddressLiteral(address target, RelocationHolder const& rspec)
358 : _rspec(rspec),
359 _is_lval(false),
360 _target(target)
361 {}
362
363 AddressLiteral addr() {
364 AddressLiteral ret = *this;
365 ret._is_lval = true;
366 return ret;
367 }
368
369
370 private:
371
372 address target() { return _target; }
373 bool is_lval() { return _is_lval; }
374
375 relocInfo::relocType reloc() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
377
378 friend class Assembler;
379 friend class MacroAssembler;
380 friend class Address;
381 friend class LIR_Assembler;
382 };
383
384 // Convience classes
385 class RuntimeAddress: public AddressLiteral {
386
387 public:
388
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
390
391 };
392
393 class OopAddress: public AddressLiteral {
394
395 public:
396
397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
398
399 };
400
401 class ExternalAddress: public AddressLiteral {
402 private:
403 static relocInfo::relocType reloc_for_target(address target) {
404 // Sometimes ExternalAddress is used for values which aren't
405 // exactly addresses, like the card table base.
406 // external_word_type can't be used for values in the first page
407 // so just skip the reloc in that case.
408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
409 }
410
411 public:
412
413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
414
415 };
416
417 class InternalAddress: public AddressLiteral {
418
419 public:
420
421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
422
423 };
424
425 // x86 can do array addressing as a single operation since disp can be an absolute
426 // address amd64 can't. We create a class that expresses the concept but does extra
427 // magic on amd64 to get the final result
428
429 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
430 private:
431
432 AddressLiteral _base;
433 Address _index;
434
435 public:
436
437 ArrayAddress() {};
438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
439 AddressLiteral base() { return _base; }
440 Address index() { return _index; }
441
442 };
443
444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
445
446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
448 // is what you get. The Assembler is generating code into a CodeBuffer.
449
450 class Assembler : public AbstractAssembler {
451 friend class AbstractAssembler; // for the non-virtual hack
452 friend class LIR_Assembler; // as_Address()
453 friend class StubGenerator;
454
455 public:
456 enum Condition { // The x86 condition codes used for conditional jumps/moves.
457 zero = 0x4,
458 notZero = 0x5,
459 equal = 0x4,
460 notEqual = 0x5,
461 less = 0xc,
462 lessEqual = 0xe,
463 greater = 0xf,
464 greaterEqual = 0xd,
465 below = 0x2,
466 belowEqual = 0x6,
467 above = 0x7,
468 aboveEqual = 0x3,
469 overflow = 0x0,
470 noOverflow = 0x1,
471 carrySet = 0x2,
472 carryClear = 0x3,
473 negative = 0x8,
474 positive = 0x9,
475 parity = 0xa,
476 noParity = 0xb
477 };
478
479 enum Prefix {
480 // segment overrides
481 CS_segment = 0x2e,
482 SS_segment = 0x36,
483 DS_segment = 0x3e,
484 ES_segment = 0x26,
485 FS_segment = 0x64,
486 GS_segment = 0x65,
487
488 REX = 0x40,
489
490 REX_B = 0x41,
491 REX_X = 0x42,
492 REX_XB = 0x43,
493 REX_R = 0x44,
494 REX_RB = 0x45,
495 REX_RX = 0x46,
496 REX_RXB = 0x47,
497
498 REX_W = 0x48,
499
500 REX_WB = 0x49,
501 REX_WX = 0x4A,
502 REX_WXB = 0x4B,
503 REX_WR = 0x4C,
504 REX_WRB = 0x4D,
505 REX_WRX = 0x4E,
506 REX_WRXB = 0x4F,
507
508 VEX_3bytes = 0xC4,
509 VEX_2bytes = 0xC5
510 };
511
512 enum VexPrefix {
513 VEX_B = 0x20,
514 VEX_X = 0x40,
515 VEX_R = 0x80,
516 VEX_W = 0x80
517 };
518
519 enum VexSimdPrefix {
520 VEX_SIMD_NONE = 0x0,
521 VEX_SIMD_66 = 0x1,
522 VEX_SIMD_F3 = 0x2,
523 VEX_SIMD_F2 = 0x3
524 };
525
526 enum VexOpcode {
527 VEX_OPCODE_NONE = 0x0,
528 VEX_OPCODE_0F = 0x1,
529 VEX_OPCODE_0F_38 = 0x2,
530 VEX_OPCODE_0F_3A = 0x3
531 };
532
533 enum WhichOperand {
534 // input to locate_operand, and format code for relocations
535 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
536 disp32_operand = 1, // embedded 32-bit displacement or address
537 call32_operand = 2, // embedded 32-bit self-relative displacement
538 #ifndef _LP64
539 _WhichOperand_limit = 3
540 #else
541 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
542 _WhichOperand_limit = 4
543 #endif
544 };
545
546
547
548 // NOTE: The general philopsophy of the declarations here is that 64bit versions
549 // of instructions are freely declared without the need for wrapping them an ifdef.
550 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
551 // In the .cpp file the implementations are wrapped so that they are dropped out
552 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
553 // to the size it was prior to merging up the 32bit and 64bit assemblers.
554 //
555 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
556 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
557
558 private:
559
560
561 // 64bit prefixes
562 int prefix_and_encode(int reg_enc, bool byteinst = false);
563 int prefixq_and_encode(int reg_enc);
564
565 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
566 int prefixq_and_encode(int dst_enc, int src_enc);
567
568 void prefix(Register reg);
569 void prefix(Address adr);
570 void prefixq(Address adr);
571
572 void prefix(Address adr, Register reg, bool byteinst = false);
573 void prefix(Address adr, XMMRegister reg);
574 void prefixq(Address adr, Register reg);
575 void prefixq(Address adr, XMMRegister reg);
576
577 void prefetch_prefix(Address src);
578
579 void rex_prefix(Address adr, XMMRegister xreg,
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
581 int rex_prefix_and_encode(int dst_enc, int src_enc,
582 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
583
584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
585 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
586 bool vector256);
587
588 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
589 VexSimdPrefix pre, VexOpcode opc,
590 bool vex_w, bool vector256);
591
592 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
593 VexSimdPrefix pre, VexOpcode opc,
594 bool vex_w, bool vector256);
595
596
597 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
598 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
599 bool rex_w = false, bool vector256 = false);
600
601 void simd_prefix(XMMRegister dst, Address src,
602 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
603 simd_prefix(dst, xnoreg, src, pre, opc);
604 }
605 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
606 simd_prefix(src, dst, pre);
607 }
608 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
609 VexSimdPrefix pre) {
610 bool rex_w = true;
611 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
612 }
613
614
615 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
616 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
617 bool rex_w = false, bool vector256 = false);
618
619 int simd_prefix_and_encode(XMMRegister dst, XMMRegister src,
620 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
621 return simd_prefix_and_encode(dst, xnoreg, src, pre, opc);
622 }
623
624 // Move/convert 32-bit integer value.
625 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
626 VexSimdPrefix pre) {
627 // It is OK to cast from Register to XMMRegister to pass argument here
628 // since only encoding is used in simd_prefix_and_encode() and number of
629 // Gen and Xmm registers are the same.
630 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
631 }
632 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
633 return simd_prefix_and_encode(dst, xnoreg, src, pre);
634 }
635 int simd_prefix_and_encode(Register dst, XMMRegister src, VexSimdPrefix pre) {
636 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre);
637 }
638
639 // Move/convert 64-bit integer value.
640 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
641 VexSimdPrefix pre) {
642 bool rex_w = true;
643 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
644 }
645 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
646 return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
647 }
648 int simd_prefix_and_encode_q(Register dst, XMMRegister src, VexSimdPrefix pre) {
649 bool rex_w = true;
650 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, VEX_OPCODE_0F, rex_w);
651 }
652
653 // Helper functions for groups of instructions
654 void emit_arith_b(int op1, int op2, Register dst, int imm8);
655
656 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
657 // only 32bit??
658 void emit_arith(int op1, int op2, Register dst, jobject obj);
659 void emit_arith(int op1, int op2, Register dst, Register src);
660
661 void emit_operand(Register reg,
662 Register base, Register index, Address::ScaleFactor scale,
663 int disp,
664 RelocationHolder const& rspec,
665 int rip_relative_correction = 0);
666
667 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
668
669 // operands that only take the original 32bit registers
670 void emit_operand32(Register reg, Address adr);
671
672 void emit_operand(XMMRegister reg,
673 Register base, Register index, Address::ScaleFactor scale,
674 int disp,
675 RelocationHolder const& rspec);
676
677 void emit_operand(XMMRegister reg, Address adr);
678
679 void emit_operand(MMXRegister reg, Address adr);
680
681 // workaround gcc (3.2.1-7) bug
682 void emit_operand(Address adr, MMXRegister reg);
683
684
685 // Immediate-to-memory forms
686 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
687
688 void emit_farith(int b1, int b2, int i);
689
690
691 protected:
692 #ifdef ASSERT
693 void check_relocation(RelocationHolder const& rspec, int format);
694 #endif
695
696 inline void emit_long64(jlong x);
697
698 void emit_data(jint data, relocInfo::relocType rtype, int format);
699 void emit_data(jint data, RelocationHolder const& rspec, int format);
700 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
701 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
702
703 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
704
705 // These are all easily abused and hence protected
706
707 // 32BIT ONLY SECTION
708 #ifndef _LP64
709 // Make these disappear in 64bit mode since they would never be correct
710 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
711 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
712
713 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
714 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
715
716 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
717 #else
718 // 64BIT ONLY SECTION
719 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
720
721 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
722 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
723
724 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
725 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
726 #endif // _LP64
727
728 // These are unique in that we are ensured by the caller that the 32bit
729 // relative in these instructions will always be able to reach the potentially
730 // 64bit address described by entry. Since they can take a 64bit address they
731 // don't have the 32 suffix like the other instructions in this class.
732
733 void call_literal(address entry, RelocationHolder const& rspec);
734 void jmp_literal(address entry, RelocationHolder const& rspec);
735
736 // Avoid using directly section
737 // Instructions in this section are actually usable by anyone without danger
738 // of failure but have performance issues that are addressed my enhanced
739 // instructions which will do the proper thing base on the particular cpu.
740 // We protect them because we don't trust you...
741
742 // Don't use next inc() and dec() methods directly. INC & DEC instructions
743 // could cause a partial flag stall since they don't set CF flag.
744 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
745 // which call inc() & dec() or add() & sub() in accordance with
746 // the product flag UseIncDec value.
747
748 void decl(Register dst);
749 void decl(Address dst);
750 void decq(Register dst);
751 void decq(Address dst);
752
753 void incl(Register dst);
754 void incl(Address dst);
755 void incq(Register dst);
756 void incq(Address dst);
757
758 // New cpus require use of movsd and movss to avoid partial register stall
759 // when loading from memory. But for old Opteron use movlpd instead of movsd.
760 // The selection is done in MacroAssembler::movdbl() and movflt().
761
762 // Move Scalar Single-Precision Floating-Point Values
763 void movss(XMMRegister dst, Address src);
764 void movss(XMMRegister dst, XMMRegister src);
765 void movss(Address dst, XMMRegister src);
766
767 // Move Scalar Double-Precision Floating-Point Values
768 void movsd(XMMRegister dst, Address src);
769 void movsd(XMMRegister dst, XMMRegister src);
770 void movsd(Address dst, XMMRegister src);
771 void movlpd(XMMRegister dst, Address src);
772
773 // New cpus require use of movaps and movapd to avoid partial register stall
774 // when moving between registers.
775 void movaps(XMMRegister dst, XMMRegister src);
776 void movapd(XMMRegister dst, XMMRegister src);
777
778 // End avoid using directly
779
780
781 // Instruction prefixes
782 void prefix(Prefix p);
783
784 public:
785
786 // Creation
787 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
788
789 // Decoding
790 static address locate_operand(address inst, WhichOperand which);
791 static address locate_next_instruction(address inst);
792
793 // Utilities
794 static bool is_polling_page_far() NOT_LP64({ return false;});
795
796 // Generic instructions
797 // Does 32bit or 64bit as needed for the platform. In some sense these
798 // belong in macro assembler but there is no need for both varieties to exist
799
800 void lea(Register dst, Address src);
801
802 void mov(Register dst, Register src);
803
804 void pusha();
805 void popa();
806
807 void pushf();
808 void popf();
809
810 void push(int32_t imm32);
811
812 void push(Register src);
813
814 void pop(Register dst);
815
816 // These are dummies to prevent surprise implicit conversions to Register
817 void push(void* v);
818 void pop(void* v);
819
820 // These do register sized moves/scans
821 void rep_mov();
822 void rep_set();
823 void repne_scan();
824 #ifdef _LP64
825 void repne_scanl();
826 #endif
827
828 // Vanilla instructions in lexical order
829
830 void adcl(Address dst, int32_t imm32);
831 void adcl(Address dst, Register src);
832 void adcl(Register dst, int32_t imm32);
833 void adcl(Register dst, Address src);
834 void adcl(Register dst, Register src);
835
836 void adcq(Register dst, int32_t imm32);
837 void adcq(Register dst, Address src);
838 void adcq(Register dst, Register src);
839
840 void addl(Address dst, int32_t imm32);
841 void addl(Address dst, Register src);
842 void addl(Register dst, int32_t imm32);
843 void addl(Register dst, Address src);
844 void addl(Register dst, Register src);
845
846 void addq(Address dst, int32_t imm32);
847 void addq(Address dst, Register src);
848 void addq(Register dst, int32_t imm32);
849 void addq(Register dst, Address src);
850 void addq(Register dst, Register src);
851
852 void addr_nop_4();
853 void addr_nop_5();
854 void addr_nop_7();
855 void addr_nop_8();
856
857 // Add Scalar Double-Precision Floating-Point Values
858 void addsd(XMMRegister dst, Address src);
859 void addsd(XMMRegister dst, XMMRegister src);
860
861 // Add Scalar Single-Precision Floating-Point Values
862 void addss(XMMRegister dst, Address src);
863 void addss(XMMRegister dst, XMMRegister src);
864
865 void andl(Address dst, int32_t imm32);
866 void andl(Register dst, int32_t imm32);
867 void andl(Register dst, Address src);
868 void andl(Register dst, Register src);
869
870 void andq(Address dst, int32_t imm32);
871 void andq(Register dst, int32_t imm32);
872 void andq(Register dst, Address src);
873 void andq(Register dst, Register src);
874
875 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
876 void andpd(XMMRegister dst, XMMRegister src);
877
878 // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
879 void andps(XMMRegister dst, XMMRegister src);
880
881 void bsfl(Register dst, Register src);
882 void bsrl(Register dst, Register src);
883
884 #ifdef _LP64
885 void bsfq(Register dst, Register src);
886 void bsrq(Register dst, Register src);
887 #endif
888
889 void bswapl(Register reg);
890
891 void bswapq(Register reg);
892
893 void call(Label& L, relocInfo::relocType rtype);
894 void call(Register reg); // push pc; pc <- reg
895 void call(Address adr); // push pc; pc <- adr
896
897 void cdql();
898
899 void cdqq();
900
901 void cld() { emit_byte(0xfc); }
902
903 void clflush(Address adr);
904
905 void cmovl(Condition cc, Register dst, Register src);
906 void cmovl(Condition cc, Register dst, Address src);
907
908 void cmovq(Condition cc, Register dst, Register src);
909 void cmovq(Condition cc, Register dst, Address src);
910
911
912 void cmpb(Address dst, int imm8);
913
914 void cmpl(Address dst, int32_t imm32);
915
916 void cmpl(Register dst, int32_t imm32);
917 void cmpl(Register dst, Register src);
918 void cmpl(Register dst, Address src);
919
920 void cmpq(Address dst, int32_t imm32);
921 void cmpq(Address dst, Register src);
922
923 void cmpq(Register dst, int32_t imm32);
924 void cmpq(Register dst, Register src);
925 void cmpq(Register dst, Address src);
926
927 // these are dummies used to catch attempting to convert NULL to Register
928 void cmpl(Register dst, void* junk); // dummy
929 void cmpq(Register dst, void* junk); // dummy
930
931 void cmpw(Address dst, int imm16);
932
933 void cmpxchg8 (Address adr);
934
935 void cmpxchgl(Register reg, Address adr);
936
937 void cmpxchgq(Register reg, Address adr);
938
939 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
940 void comisd(XMMRegister dst, Address src);
941 void comisd(XMMRegister dst, XMMRegister src);
942
943 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
944 void comiss(XMMRegister dst, Address src);
945 void comiss(XMMRegister dst, XMMRegister src);
946
947 // Identify processor type and features
948 void cpuid() {
949 emit_byte(0x0F);
950 emit_byte(0xA2);
951 }
952
953 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
954 void cvtsd2ss(XMMRegister dst, XMMRegister src);
955 void cvtsd2ss(XMMRegister dst, Address src);
956
957 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
958 void cvtsi2sdl(XMMRegister dst, Register src);
959 void cvtsi2sdl(XMMRegister dst, Address src);
960 void cvtsi2sdq(XMMRegister dst, Register src);
961 void cvtsi2sdq(XMMRegister dst, Address src);
962
963 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
964 void cvtsi2ssl(XMMRegister dst, Register src);
965 void cvtsi2ssl(XMMRegister dst, Address src);
966 void cvtsi2ssq(XMMRegister dst, Register src);
967 void cvtsi2ssq(XMMRegister dst, Address src);
968
969 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
970 void cvtdq2pd(XMMRegister dst, XMMRegister src);
971
972 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
973 void cvtdq2ps(XMMRegister dst, XMMRegister src);
974
975 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
976 void cvtss2sd(XMMRegister dst, XMMRegister src);
977 void cvtss2sd(XMMRegister dst, Address src);
978
979 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
980 void cvttsd2sil(Register dst, Address src);
981 void cvttsd2sil(Register dst, XMMRegister src);
982 void cvttsd2siq(Register dst, XMMRegister src);
983
984 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
985 void cvttss2sil(Register dst, XMMRegister src);
986 void cvttss2siq(Register dst, XMMRegister src);
987
988 // Divide Scalar Double-Precision Floating-Point Values
989 void divsd(XMMRegister dst, Address src);
990 void divsd(XMMRegister dst, XMMRegister src);
991
992 // Divide Scalar Single-Precision Floating-Point Values
993 void divss(XMMRegister dst, Address src);
994 void divss(XMMRegister dst, XMMRegister src);
995
996 void emms();
997
998 void fabs();
999
1000 void fadd(int i);
1001
1002 void fadd_d(Address src);
1003 void fadd_s(Address src);
1004
1005 // "Alternate" versions of x87 instructions place result down in FPU
1006 // stack instead of on TOS
1007
1008 void fadda(int i); // "alternate" fadd
1009 void faddp(int i = 1);
1010
1011 void fchs();
1012
1013 void fcom(int i);
1014
1015 void fcomp(int i = 1);
1016 void fcomp_d(Address src);
1017 void fcomp_s(Address src);
1018
1019 void fcompp();
1020
1021 void fcos();
1022
1023 void fdecstp();
1024
1025 void fdiv(int i);
1026 void fdiv_d(Address src);
1027 void fdivr_s(Address src);
1028 void fdiva(int i); // "alternate" fdiv
1029 void fdivp(int i = 1);
1030
1031 void fdivr(int i);
1032 void fdivr_d(Address src);
1033 void fdiv_s(Address src);
1034
1035 void fdivra(int i); // "alternate" reversed fdiv
1036
1037 void fdivrp(int i = 1);
1038
1039 void ffree(int i = 0);
1040
1041 void fild_d(Address adr);
1042 void fild_s(Address adr);
1043
1044 void fincstp();
1045
1046 void finit();
1047
1048 void fist_s (Address adr);
1049 void fistp_d(Address adr);
1050 void fistp_s(Address adr);
1051
1052 void fld1();
1053
1054 void fld_d(Address adr);
1055 void fld_s(Address adr);
1056 void fld_s(int index);
1057 void fld_x(Address adr); // extended-precision (80-bit) format
1058
1059 void fldcw(Address src);
1060
1061 void fldenv(Address src);
1062
1063 void fldlg2();
1064
1065 void fldln2();
1066
1067 void fldz();
1068
1069 void flog();
1070 void flog10();
1071
1072 void fmul(int i);
1073
1074 void fmul_d(Address src);
1075 void fmul_s(Address src);
1076
1077 void fmula(int i); // "alternate" fmul
1078
1079 void fmulp(int i = 1);
1080
1081 void fnsave(Address dst);
1082
1083 void fnstcw(Address src);
1084
1085 void fnstsw_ax();
1086
1087 void fprem();
1088 void fprem1();
1089
1090 void frstor(Address src);
1091
1092 void fsin();
1093
1094 void fsqrt();
1095
1096 void fst_d(Address adr);
1097 void fst_s(Address adr);
1098
1099 void fstp_d(Address adr);
1100 void fstp_d(int index);
1101 void fstp_s(Address adr);
1102 void fstp_x(Address adr); // extended-precision (80-bit) format
1103
1104 void fsub(int i);
1105 void fsub_d(Address src);
1106 void fsub_s(Address src);
1107
1108 void fsuba(int i); // "alternate" fsub
1109
1110 void fsubp(int i = 1);
1111
1112 void fsubr(int i);
1113 void fsubr_d(Address src);
1114 void fsubr_s(Address src);
1115
1116 void fsubra(int i); // "alternate" reversed fsub
1117
1118 void fsubrp(int i = 1);
1119
1120 void ftan();
1121
1122 void ftst();
1123
1124 void fucomi(int i = 1);
1125 void fucomip(int i = 1);
1126
1127 void fwait();
1128
1129 void fxch(int i = 1);
1130
1131 void fxrstor(Address src);
1132
1133 void fxsave(Address dst);
1134
1135 void fyl2x();
1136
1137 void hlt();
1138
1139 void idivl(Register src);
1140 void divl(Register src); // Unsigned division
1141
1142 void idivq(Register src);
1143
1144 void imull(Register dst, Register src);
1145 void imull(Register dst, Register src, int value);
1146
1147 void imulq(Register dst, Register src);
1148 void imulq(Register dst, Register src, int value);
1149
1150
1151 // jcc is the generic conditional branch generator to run-
1152 // time routines, jcc is used for branches to labels. jcc
1153 // takes a branch opcode (cc) and a label (L) and generates
1154 // either a backward branch or a forward branch and links it
1155 // to the label fixup chain. Usage:
1156 //
1157 // Label L; // unbound label
1158 // jcc(cc, L); // forward branch to unbound label
1159 // bind(L); // bind label to the current pc
1160 // jcc(cc, L); // backward branch to bound label
1161 // bind(L); // illegal: a label may be bound only once
1162 //
1163 // Note: The same Label can be used for forward and backward branches
1164 // but it may be bound only once.
1165
1166 void jcc(Condition cc, Label& L, bool maybe_short = true);
1167
1168 // Conditional jump to a 8-bit offset to L.
1169 // WARNING: be very careful using this for forward jumps. If the label is
1170 // not bound within an 8-bit offset of this instruction, a run-time error
1171 // will occur.
1172 void jccb(Condition cc, Label& L);
1173
1174 void jmp(Address entry); // pc <- entry
1175
1176 // Label operations & relative jumps (PPUM Appendix D)
1177 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1178
1179 void jmp(Register entry); // pc <- entry
1180
1181 // Unconditional 8-bit offset jump to L.
1182 // WARNING: be very careful using this for forward jumps. If the label is
1183 // not bound within an 8-bit offset of this instruction, a run-time error
1184 // will occur.
1185 void jmpb(Label& L);
1186
1187 void ldmxcsr( Address src );
1188
1189 void leal(Register dst, Address src);
1190
1191 void leaq(Register dst, Address src);
1192
1193 void lfence() {
1194 emit_byte(0x0F);
1195 emit_byte(0xAE);
1196 emit_byte(0xE8);
1197 }
1198
1199 void lock();
1200
1201 void lzcntl(Register dst, Register src);
1202
1203 #ifdef _LP64
1204 void lzcntq(Register dst, Register src);
1205 #endif
1206
1207 enum Membar_mask_bits {
1208 StoreStore = 1 << 3,
1209 LoadStore = 1 << 2,
1210 StoreLoad = 1 << 1,
1211 LoadLoad = 1 << 0
1212 };
1213
1214 // Serializes memory and blows flags
1215 void membar(Membar_mask_bits order_constraint) {
1216 if (os::is_MP()) {
1217 // We only have to handle StoreLoad
1218 if (order_constraint & StoreLoad) {
1219 // All usable chips support "locked" instructions which suffice
1220 // as barriers, and are much faster than the alternative of
1221 // using cpuid instruction. We use here a locked add [esp],0.
1222 // This is conveniently otherwise a no-op except for blowing
1223 // flags.
1224 // Any change to this code may need to revisit other places in
1225 // the code where this idiom is used, in particular the
1226 // orderAccess code.
1227 lock();
1228 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1229 }
1230 }
1231 }
1232
1233 void mfence();
1234
1235 // Moves
1236
1237 void mov64(Register dst, int64_t imm64);
1238
1239 void movb(Address dst, Register src);
1240 void movb(Address dst, int imm8);
1241 void movb(Register dst, Address src);
1242
1243 void movdl(XMMRegister dst, Register src);
1244 void movdl(Register dst, XMMRegister src);
1245 void movdl(XMMRegister dst, Address src);
1246
1247 // Move Double Quadword
1248 void movdq(XMMRegister dst, Register src);
1249 void movdq(Register dst, XMMRegister src);
1250
1251 // Move Aligned Double Quadword
1252 void movdqa(XMMRegister dst, XMMRegister src);
1253
1254 // Move Unaligned Double Quadword
1255 void movdqu(Address dst, XMMRegister src);
1256 void movdqu(XMMRegister dst, Address src);
1257 void movdqu(XMMRegister dst, XMMRegister src);
1258
1259 void movl(Register dst, int32_t imm32);
1260 void movl(Address dst, int32_t imm32);
1261 void movl(Register dst, Register src);
1262 void movl(Register dst, Address src);
1263 void movl(Address dst, Register src);
1264
1265 // These dummies prevent using movl from converting a zero (like NULL) into Register
1266 // by giving the compiler two choices it can't resolve
1267
1268 void movl(Address dst, void* junk);
1269 void movl(Register dst, void* junk);
1270
1271 #ifdef _LP64
1272 void movq(Register dst, Register src);
1273 void movq(Register dst, Address src);
1274 void movq(Address dst, Register src);
1275 #endif
1276
1277 void movq(Address dst, MMXRegister src );
1278 void movq(MMXRegister dst, Address src );
1279
1280 #ifdef _LP64
1281 // These dummies prevent using movq from converting a zero (like NULL) into Register
1282 // by giving the compiler two choices it can't resolve
1283
1284 void movq(Address dst, void* dummy);
1285 void movq(Register dst, void* dummy);
1286 #endif
1287
1288 // Move Quadword
1289 void movq(Address dst, XMMRegister src);
1290 void movq(XMMRegister dst, Address src);
1291
1292 void movsbl(Register dst, Address src);
1293 void movsbl(Register dst, Register src);
1294
1295 #ifdef _LP64
1296 void movsbq(Register dst, Address src);
1297 void movsbq(Register dst, Register src);
1298
1299 // Move signed 32bit immediate to 64bit extending sign
1300 void movslq(Address dst, int32_t imm64);
1301 void movslq(Register dst, int32_t imm64);
1302
1303 void movslq(Register dst, Address src);
1304 void movslq(Register dst, Register src);
1305 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1306 #endif
1307
1308 void movswl(Register dst, Address src);
1309 void movswl(Register dst, Register src);
1310
1311 #ifdef _LP64
1312 void movswq(Register dst, Address src);
1313 void movswq(Register dst, Register src);
1314 #endif
1315
1316 void movw(Address dst, int imm16);
1317 void movw(Register dst, Address src);
1318 void movw(Address dst, Register src);
1319
1320 void movzbl(Register dst, Address src);
1321 void movzbl(Register dst, Register src);
1322
1323 #ifdef _LP64
1324 void movzbq(Register dst, Address src);
1325 void movzbq(Register dst, Register src);
1326 #endif
1327
1328 void movzwl(Register dst, Address src);
1329 void movzwl(Register dst, Register src);
1330
1331 #ifdef _LP64
1332 void movzwq(Register dst, Address src);
1333 void movzwq(Register dst, Register src);
1334 #endif
1335
1336 void mull(Address src);
1337 void mull(Register src);
1338
1339 // Multiply Scalar Double-Precision Floating-Point Values
1340 void mulsd(XMMRegister dst, Address src);
1341 void mulsd(XMMRegister dst, XMMRegister src);
1342
1343 // Multiply Scalar Single-Precision Floating-Point Values
1344 void mulss(XMMRegister dst, Address src);
1345 void mulss(XMMRegister dst, XMMRegister src);
1346
1347 void negl(Register dst);
1348
1349 #ifdef _LP64
1350 void negq(Register dst);
1351 #endif
1352
1353 void nop(int i = 1);
1354
1355 void notl(Register dst);
1356
1357 #ifdef _LP64
1358 void notq(Register dst);
1359 #endif
1360
1361 void orl(Address dst, int32_t imm32);
1362 void orl(Register dst, int32_t imm32);
1363 void orl(Register dst, Address src);
1364 void orl(Register dst, Register src);
1365
1366 void orq(Address dst, int32_t imm32);
1367 void orq(Register dst, int32_t imm32);
1368 void orq(Register dst, Address src);
1369 void orq(Register dst, Register src);
1370
1371 // Pack with unsigned saturation
1372 void packuswb(XMMRegister dst, XMMRegister src);
1373 void packuswb(XMMRegister dst, Address src);
1374
1375 // SSE4.2 string instructions
1376 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1377 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1378
1379 // SSE4.1 packed move
1380 void pmovzxbw(XMMRegister dst, XMMRegister src);
1381 void pmovzxbw(XMMRegister dst, Address src);
1382
1383 #ifndef _LP64 // no 32bit push/pop on amd64
1384 void popl(Address dst);
1385 #endif
1386
1387 #ifdef _LP64
1388 void popq(Address dst);
1389 #endif
1390
1391 void popcntl(Register dst, Address src);
1392 void popcntl(Register dst, Register src);
1393
1394 #ifdef _LP64
1395 void popcntq(Register dst, Address src);
1396 void popcntq(Register dst, Register src);
1397 #endif
1398
1399 // Prefetches (SSE, SSE2, 3DNOW only)
1400
1401 void prefetchnta(Address src);
1402 void prefetchr(Address src);
1403 void prefetcht0(Address src);
1404 void prefetcht1(Address src);
1405 void prefetcht2(Address src);
1406 void prefetchw(Address src);
1407
1408 // POR - Bitwise logical OR
1409 void por(XMMRegister dst, XMMRegister src);
1410 void por(XMMRegister dst, Address src);
1411
1412 // Shuffle Packed Doublewords
1413 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1414 void pshufd(XMMRegister dst, Address src, int mode);
1415
1416 // Shuffle Packed Low Words
1417 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1418 void pshuflw(XMMRegister dst, Address src, int mode);
1419
1420 // Shift Right by bits Logical Quadword Immediate
1421 void psrlq(XMMRegister dst, int shift);
1422
1423 // Shift Right by bytes Logical DoubleQuadword Immediate
1424 void psrldq(XMMRegister dst, int shift);
1425
1426 // Logical Compare Double Quadword
1427 void ptest(XMMRegister dst, XMMRegister src);
1428 void ptest(XMMRegister dst, Address src);
1429
1430 // Interleave Low Bytes
1431 void punpcklbw(XMMRegister dst, XMMRegister src);
1432 void punpcklbw(XMMRegister dst, Address src);
1433
1434 // Interleave Low Doublewords
1435 void punpckldq(XMMRegister dst, XMMRegister src);
1436 void punpckldq(XMMRegister dst, Address src);
1437
1438 #ifndef _LP64 // no 32bit push/pop on amd64
1439 void pushl(Address src);
1440 #endif
1441
1442 void pushq(Address src);
1443
1444 // Xor Packed Byte Integer Values
1445 void pxor(XMMRegister dst, Address src);
1446 void pxor(XMMRegister dst, XMMRegister src);
1447
1448 void rcll(Register dst, int imm8);
1449
1450 void rclq(Register dst, int imm8);
1451
1452 void ret(int imm16);
1453
1454 void sahf();
1455
1456 void sarl(Register dst, int imm8);
1457 void sarl(Register dst);
1458
1459 void sarq(Register dst, int imm8);
1460 void sarq(Register dst);
1461
1462 void sbbl(Address dst, int32_t imm32);
1463 void sbbl(Register dst, int32_t imm32);
1464 void sbbl(Register dst, Address src);
1465 void sbbl(Register dst, Register src);
1466
1467 void sbbq(Address dst, int32_t imm32);
1468 void sbbq(Register dst, int32_t imm32);
1469 void sbbq(Register dst, Address src);
1470 void sbbq(Register dst, Register src);
1471
1472 void setb(Condition cc, Register dst);
1473
1474 void shldl(Register dst, Register src);
1475
1476 void shll(Register dst, int imm8);
1477 void shll(Register dst);
1478
1479 void shlq(Register dst, int imm8);
1480 void shlq(Register dst);
1481
1482 void shrdl(Register dst, Register src);
1483
1484 void shrl(Register dst, int imm8);
1485 void shrl(Register dst);
1486
1487 void shrq(Register dst, int imm8);
1488 void shrq(Register dst);
1489
1490 void smovl(); // QQQ generic?
1491
1492 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1493 void sqrtsd(XMMRegister dst, Address src);
1494 void sqrtsd(XMMRegister dst, XMMRegister src);
1495
1496 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1497 void sqrtss(XMMRegister dst, Address src);
1498 void sqrtss(XMMRegister dst, XMMRegister src);
1499
1500 void std() { emit_byte(0xfd); }
1501
1502 void stmxcsr( Address dst );
1503
1504 void subl(Address dst, int32_t imm32);
1505 void subl(Address dst, Register src);
1506 void subl(Register dst, int32_t imm32);
1507 void subl(Register dst, Address src);
1508 void subl(Register dst, Register src);
1509
1510 void subq(Address dst, int32_t imm32);
1511 void subq(Address dst, Register src);
1512 void subq(Register dst, int32_t imm32);
1513 void subq(Register dst, Address src);
1514 void subq(Register dst, Register src);
1515
1516
1517 // Subtract Scalar Double-Precision Floating-Point Values
1518 void subsd(XMMRegister dst, Address src);
1519 void subsd(XMMRegister dst, XMMRegister src);
1520
1521 // Subtract Scalar Single-Precision Floating-Point Values
1522 void subss(XMMRegister dst, Address src);
1523 void subss(XMMRegister dst, XMMRegister src);
1524
1525 void testb(Register dst, int imm8);
1526
1527 void testl(Register dst, int32_t imm32);
1528 void testl(Register dst, Register src);
1529 void testl(Register dst, Address src);
1530
1531 void testq(Register dst, int32_t imm32);
1532 void testq(Register dst, Register src);
1533
1534
1535 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1536 void ucomisd(XMMRegister dst, Address src);
1537 void ucomisd(XMMRegister dst, XMMRegister src);
1538
1539 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1540 void ucomiss(XMMRegister dst, Address src);
1541 void ucomiss(XMMRegister dst, XMMRegister src);
1542
1543 void xaddl(Address dst, Register src);
1544
1545 void xaddq(Address dst, Register src);
1546
1547 void xchgl(Register reg, Address adr);
1548 void xchgl(Register dst, Register src);
1549
1550 void xchgq(Register reg, Address adr);
1551 void xchgq(Register dst, Register src);
1552
1553 // Get Value of Extended Control Register
1554 void xgetbv() {
1555 emit_byte(0x0F);
1556 emit_byte(0x01);
1557 emit_byte(0xD0);
1558 }
1559
1560 void xorl(Register dst, int32_t imm32);
1561 void xorl(Register dst, Address src);
1562 void xorl(Register dst, Register src);
1563
1564 void xorq(Register dst, Address src);
1565 void xorq(Register dst, Register src);
1566
1567 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1568 void xorpd(XMMRegister dst, XMMRegister src);
1569
1570 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1571 void xorps(XMMRegister dst, XMMRegister src);
1572
1573 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1574
1575 protected:
1576 // Next instructions require address alignment 16 bytes SSE mode.
1577 // They should be called only from corresponding MacroAssembler instructions.
1578 void andpd(XMMRegister dst, Address src);
1579 void andps(XMMRegister dst, Address src);
1580 void xorpd(XMMRegister dst, Address src);
1581 void xorps(XMMRegister dst, Address src);
1582
1583 };
1584
1585
1586 // MacroAssembler extends Assembler by frequently used macros.
1587 //
1588 // Instructions for which a 'better' code sequence exists depending
1589 // on arguments should also go in here.
1590
1591 class MacroAssembler: public Assembler {
1592 friend class LIR_Assembler;
1593 friend class Runtime1; // as_Address()
1594
1595 protected:
1596
1597 Address as_Address(AddressLiteral adr);
1598 Address as_Address(ArrayAddress adr);
1599
1600 // Support for VM calls
1601 //
1602 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1603 // may customize this version by overriding it for its purposes (e.g., to save/restore
1604 // additional registers when doing a VM call).
1605 #ifdef CC_INTERP
1606 // c++ interpreter never wants to use interp_masm version of call_VM
1607 #define VIRTUAL
1608 #else
1609 #define VIRTUAL virtual
1610 #endif
1611
1612 VIRTUAL void call_VM_leaf_base(
1613 address entry_point, // the entry point
1614 int number_of_arguments // the number of arguments to pop after the call
1615 );
1616
1617 // This is the base routine called by the different versions of call_VM. The interpreter
1618 // may customize this version by overriding it for its purposes (e.g., to save/restore
1619 // additional registers when doing a VM call).
1620 //
1621 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1622 // returns the register which contains the thread upon return. If a thread register has been
1623 // specified, the return value will correspond to that register. If no last_java_sp is specified
1624 // (noreg) than rsp will be used instead.
1625 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1626 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1627 Register java_thread, // the thread if computed before ; use noreg otherwise
1628 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1629 address entry_point, // the entry point
1630 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1631 bool check_exceptions // whether to check for pending exceptions after return
1632 );
1633
1634 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1635 // The implementation is only non-empty for the InterpreterMacroAssembler,
1636 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1637 virtual void check_and_handle_popframe(Register java_thread);
1638 virtual void check_and_handle_earlyret(Register java_thread);
1639
1640 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1641
1642 // helpers for FPU flag access
1643 // tmp is a temporary register, if none is available use noreg
1644 void save_rax (Register tmp);
1645 void restore_rax(Register tmp);
1646
1647 public:
1648 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1649
1650 // Support for NULL-checks
1651 //
1652 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1653 // If the accessed location is M[reg + offset] and the offset is known, provide the
1654 // offset. No explicit code generation is needed if the offset is within a certain
1655 // range (0 <= offset <= page_size).
1656
1657 void null_check(Register reg, int offset = -1);
1658 static bool needs_explicit_null_check(intptr_t offset);
1659
1660 // Required platform-specific helpers for Label::patch_instructions.
1661 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1662 void pd_patch_instruction(address branch, address target);
1663 #ifndef PRODUCT
1664 static void pd_print_patched_instruction(address branch);
1665 #endif
1666
1667 // The following 4 methods return the offset of the appropriate move instruction
1668
1669 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1670 int load_unsigned_byte(Register dst, Address src);
1671 int load_unsigned_short(Register dst, Address src);
1672
1673 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1674 int load_signed_byte(Register dst, Address src);
1675 int load_signed_short(Register dst, Address src);
1676
1677 // Support for sign-extension (hi:lo = extend_sign(lo))
1678 void extend_sign(Register hi, Register lo);
1679
1680 // Load and store values by size and signed-ness
1681 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1682 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1683
1684 // Support for inc/dec with optimal instruction selection depending on value
1685
1686 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1687 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1688
1689 void decrementl(Address dst, int value = 1);
1690 void decrementl(Register reg, int value = 1);
1691
1692 void decrementq(Register reg, int value = 1);
1693 void decrementq(Address dst, int value = 1);
1694
1695 void incrementl(Address dst, int value = 1);
1696 void incrementl(Register reg, int value = 1);
1697
1698 void incrementq(Register reg, int value = 1);
1699 void incrementq(Address dst, int value = 1);
1700
1701
1702 // Support optimal SSE move instructions.
1703 void movflt(XMMRegister dst, XMMRegister src) {
1704 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1705 else { movss (dst, src); return; }
1706 }
1707 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1708 void movflt(XMMRegister dst, AddressLiteral src);
1709 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1710
1711 void movdbl(XMMRegister dst, XMMRegister src) {
1712 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1713 else { movsd (dst, src); return; }
1714 }
1715
1716 void movdbl(XMMRegister dst, AddressLiteral src);
1717
1718 void movdbl(XMMRegister dst, Address src) {
1719 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1720 else { movlpd(dst, src); return; }
1721 }
1722 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1723
1724 void incrementl(AddressLiteral dst);
1725 void incrementl(ArrayAddress dst);
1726
1727 // Alignment
1728 void align(int modulus);
1729
1730 // Misc
1731 void fat_nop(); // 5 byte nop
1732
1733 // Stack frame creation/removal
1734 void enter();
1735 void leave();
1736
1737 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1738 // The pointer will be loaded into the thread register.
1739 void get_thread(Register thread);
1740
1741
1742 // Support for VM calls
1743 //
1744 // It is imperative that all calls into the VM are handled via the call_VM macros.
1745 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1746 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1747
1748
1749 void call_VM(Register oop_result,
1750 address entry_point,
1751 bool check_exceptions = true);
1752 void call_VM(Register oop_result,
1753 address entry_point,
1754 Register arg_1,
1755 bool check_exceptions = true);
1756 void call_VM(Register oop_result,
1757 address entry_point,
1758 Register arg_1, Register arg_2,
1759 bool check_exceptions = true);
1760 void call_VM(Register oop_result,
1761 address entry_point,
1762 Register arg_1, Register arg_2, Register arg_3,
1763 bool check_exceptions = true);
1764
1765 // Overloadings with last_Java_sp
1766 void call_VM(Register oop_result,
1767 Register last_java_sp,
1768 address entry_point,
1769 int number_of_arguments = 0,
1770 bool check_exceptions = true);
1771 void call_VM(Register oop_result,
1772 Register last_java_sp,
1773 address entry_point,
1774 Register arg_1, bool
1775 check_exceptions = true);
1776 void call_VM(Register oop_result,
1777 Register last_java_sp,
1778 address entry_point,
1779 Register arg_1, Register arg_2,
1780 bool check_exceptions = true);
1781 void call_VM(Register oop_result,
1782 Register last_java_sp,
1783 address entry_point,
1784 Register arg_1, Register arg_2, Register arg_3,
1785 bool check_exceptions = true);
1786
1787 // These always tightly bind to MacroAssembler::call_VM_base
1788 // bypassing the virtual implementation
1789 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1790 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1791 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1792 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1793 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1794
1795 void call_VM_leaf(address entry_point,
1796 int number_of_arguments = 0);
1797 void call_VM_leaf(address entry_point,
1798 Register arg_1);
1799 void call_VM_leaf(address entry_point,
1800 Register arg_1, Register arg_2);
1801 void call_VM_leaf(address entry_point,
1802 Register arg_1, Register arg_2, Register arg_3);
1803
1804 // These always tightly bind to MacroAssembler::call_VM_leaf_base
1805 // bypassing the virtual implementation
1806 void super_call_VM_leaf(address entry_point);
1807 void super_call_VM_leaf(address entry_point, Register arg_1);
1808 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1809 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1810 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
1811
1812 // last Java Frame (fills frame anchor)
1813 void set_last_Java_frame(Register thread,
1814 Register last_java_sp,
1815 Register last_java_fp,
1816 address last_java_pc);
1817
1818 // thread in the default location (r15_thread on 64bit)
1819 void set_last_Java_frame(Register last_java_sp,
1820 Register last_java_fp,
1821 address last_java_pc);
1822
1823 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1824
1825 // thread in the default location (r15_thread on 64bit)
1826 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1827
1828 // Stores
1829 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1830 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1831
1832 #ifndef SERIALGC
1833
1834 void g1_write_barrier_pre(Register obj,
1835 Register pre_val,
1836 Register thread,
1837 Register tmp,
1838 bool tosca_live,
1839 bool expand_call);
1840
1841 void g1_write_barrier_post(Register store_addr,
1842 Register new_val,
1843 Register thread,
1844 Register tmp,
1845 Register tmp2);
1846
1847 #endif // SERIALGC
1848
1849 // split store_check(Register obj) to enhance instruction interleaving
1850 void store_check_part_1(Register obj);
1851 void store_check_part_2(Register obj);
1852
1853 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1854 void c2bool(Register x);
1855
1856 // C++ bool manipulation
1857
1858 void movbool(Register dst, Address src);
1859 void movbool(Address dst, bool boolconst);
1860 void movbool(Address dst, Register src);
1861 void testbool(Register dst);
1862
1863 // oop manipulations
1864 void load_klass(Register dst, Register src);
1865 void store_klass(Register dst, Register src);
1866
1867 void load_heap_oop(Register dst, Address src);
1868 void load_heap_oop_not_null(Register dst, Address src);
1869 void store_heap_oop(Address dst, Register src);
1870
1871 // Used for storing NULL. All other oop constants should be
1872 // stored using routines that take a jobject.
1873 void store_heap_oop_null(Address dst);
1874
1875 void load_prototype_header(Register dst, Register src);
1876
1877 #ifdef _LP64
1878 void store_klass_gap(Register dst, Register src);
1879
1880 // This dummy is to prevent a call to store_heap_oop from
1881 // converting a zero (like NULL) into a Register by giving
1882 // the compiler two choices it can't resolve
1883
1884 void store_heap_oop(Address dst, void* dummy);
1885
1886 void encode_heap_oop(Register r);
1887 void decode_heap_oop(Register r);
1888 void encode_heap_oop_not_null(Register r);
1889 void decode_heap_oop_not_null(Register r);
1890 void encode_heap_oop_not_null(Register dst, Register src);
1891 void decode_heap_oop_not_null(Register dst, Register src);
1892
1893 void set_narrow_oop(Register dst, jobject obj);
1894 void set_narrow_oop(Address dst, jobject obj);
1895 void cmp_narrow_oop(Register dst, jobject obj);
1896 void cmp_narrow_oop(Address dst, jobject obj);
1897
1898 // if heap base register is used - reinit it with the correct value
1899 void reinit_heapbase();
1900
1901 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1902
1903 #endif // _LP64
1904
1905 // Int division/remainder for Java
1906 // (as idivl, but checks for special case as described in JVM spec.)
1907 // returns idivl instruction offset for implicit exception handling
1908 int corrected_idivl(Register reg);
1909
1910 // Long division/remainder for Java
1911 // (as idivq, but checks for special case as described in JVM spec.)
1912 // returns idivq instruction offset for implicit exception handling
1913 int corrected_idivq(Register reg);
1914
1915 void int3();
1916
1917 // Long operation macros for a 32bit cpu
1918 // Long negation for Java
1919 void lneg(Register hi, Register lo);
1920
1921 // Long multiplication for Java
1922 // (destroys contents of eax, ebx, ecx and edx)
1923 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1924
1925 // Long shifts for Java
1926 // (semantics as described in JVM spec.)
1927 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1928 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1929
1930 // Long compare for Java
1931 // (semantics as described in JVM spec.)
1932 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1933
1934
1935 // misc
1936
1937 // Sign extension
1938 void sign_extend_short(Register reg);
1939 void sign_extend_byte(Register reg);
1940
1941 // Division by power of 2, rounding towards 0
1942 void division_with_shift(Register reg, int shift_value);
1943
1944 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1945 //
1946 // CF (corresponds to C0) if x < y
1947 // PF (corresponds to C2) if unordered
1948 // ZF (corresponds to C3) if x = y
1949 //
1950 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1951 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1952 void fcmp(Register tmp);
1953 // Variant of the above which allows y to be further down the stack
1954 // and which only pops x and y if specified. If pop_right is
1955 // specified then pop_left must also be specified.
1956 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1957
1958 // Floating-point comparison for Java
1959 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1960 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1961 // (semantics as described in JVM spec.)
1962 void fcmp2int(Register dst, bool unordered_is_less);
1963 // Variant of the above which allows y to be further down the stack
1964 // and which only pops x and y if specified. If pop_right is
1965 // specified then pop_left must also be specified.
1966 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1967
1968 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1969 // tmp is a temporary register, if none is available use noreg
1970 void fremr(Register tmp);
1971
1972
1973 // same as fcmp2int, but using SSE2
1974 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1975 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1976
1977 // Inlined sin/cos generator for Java; must not use CPU instruction
1978 // directly on Intel as it does not have high enough precision
1979 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1980 // number of FPU stack slots in use; all but the topmost will
1981 // require saving if a slow case is necessary. Assumes argument is
1982 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1983 // this code.
1984 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1985
1986 // branch to L if FPU flag C2 is set/not set
1987 // tmp is a temporary register, if none is available use noreg
1988 void jC2 (Register tmp, Label& L);
1989 void jnC2(Register tmp, Label& L);
1990
1991 // Pop ST (ffree & fincstp combined)
1992 void fpop();
1993
1994 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1995 void push_fTOS();
1996
1997 // pops double TOS element from CPU stack and pushes on FPU stack
1998 void pop_fTOS();
1999
2000 void empty_FPU_stack();
2001
2002 void push_IU_state();
2003 void pop_IU_state();
2004
2005 void push_FPU_state();
2006 void pop_FPU_state();
2007
2008 void push_CPU_state();
2009 void pop_CPU_state();
2010
2011 // Round up to a power of two
2012 void round_to(Register reg, int modulus);
2013
2014 // Callee saved registers handling
2015 void push_callee_saved_registers();
2016 void pop_callee_saved_registers();
2017
2018 // allocation
2019 void eden_allocate(
2020 Register obj, // result: pointer to object after successful allocation
2021 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2022 int con_size_in_bytes, // object size in bytes if known at compile time
2023 Register t1, // temp register
2024 Label& slow_case // continuation point if fast allocation fails
2025 );
2026 void tlab_allocate(
2027 Register obj, // result: pointer to object after successful allocation
2028 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2029 int con_size_in_bytes, // object size in bytes if known at compile time
2030 Register t1, // temp register
2031 Register t2, // temp register
2032 Label& slow_case // continuation point if fast allocation fails
2033 );
2034 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2035 void incr_allocated_bytes(Register thread,
2036 Register var_size_in_bytes, int con_size_in_bytes,
2037 Register t1 = noreg);
2038
2039 // interface method calling
2040 void lookup_interface_method(Register recv_klass,
2041 Register intf_klass,
2042 RegisterOrConstant itable_index,
2043 Register method_result,
2044 Register scan_temp,
2045 Label& no_such_interface);
2046
2047 // Test sub_klass against super_klass, with fast and slow paths.
2048
2049 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2050 // One of the three labels can be NULL, meaning take the fall-through.
2051 // If super_check_offset is -1, the value is loaded up from super_klass.
2052 // No registers are killed, except temp_reg.
2053 void check_klass_subtype_fast_path(Register sub_klass,
2054 Register super_klass,
2055 Register temp_reg,
2056 Label* L_success,
2057 Label* L_failure,
2058 Label* L_slow_path,
2059 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2060
2061 // The rest of the type check; must be wired to a corresponding fast path.
2062 // It does not repeat the fast path logic, so don't use it standalone.
2063 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2064 // Updates the sub's secondary super cache as necessary.
2065 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2066 void check_klass_subtype_slow_path(Register sub_klass,
2067 Register super_klass,
2068 Register temp_reg,
2069 Register temp2_reg,
2070 Label* L_success,
2071 Label* L_failure,
2072 bool set_cond_codes = false);
2073
2074 // Simplified, combined version, good for typical uses.
2075 // Falls through on failure.
2076 void check_klass_subtype(Register sub_klass,
2077 Register super_klass,
2078 Register temp_reg,
2079 Label& L_success);
2080
2081 // method handles (JSR 292)
2082 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2083 Register temp_reg,
2084 Label& wrong_method_type);
2085 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2086 Register temp_reg);
2087 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2088 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2089
2090
2091 //----
2092 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2093
2094 // Debugging
2095
2096 // only if +VerifyOops
2097 void verify_oop(Register reg, const char* s = "broken oop");
2098 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2099
2100 // only if +VerifyFPU
2101 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2102
2103 // prints msg, dumps registers and stops execution
2104 void stop(const char* msg);
2105
2106 // prints msg and continues
2107 void warn(const char* msg);
2108
2109 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2110 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2111
2112 void os_breakpoint();
2113
2114 void untested() { stop("untested"); }
2115
2116 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
2117
2118 void should_not_reach_here() { stop("should not reach here"); }
2119
2120 void print_CPU_state();
2121
2122 // Stack overflow checking
2123 void bang_stack_with_offset(int offset) {
2124 // stack grows down, caller passes positive offset
2125 assert(offset > 0, "must bang with negative offset");
2126 movl(Address(rsp, (-offset)), rax);
2127 }
2128
2129 // Writes to stack successive pages until offset reached to check for
2130 // stack overflow + shadow pages. Also, clobbers tmp
2131 void bang_stack_size(Register size, Register tmp);
2132
2133 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2134 Register tmp,
2135 int offset);
2136
2137 // Support for serializing memory accesses between threads
2138 void serialize_memory(Register thread, Register tmp);
2139
2140 void verify_tlab();
2141
2142 // Biased locking support
2143 // lock_reg and obj_reg must be loaded up with the appropriate values.
2144 // swap_reg must be rax, and is killed.
2145 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2146 // be killed; if not supplied, push/pop will be used internally to
2147 // allocate a temporary (inefficient, avoid if possible).
2148 // Optional slow case is for implementations (interpreter and C1) which branch to
2149 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2150 // Returns offset of first potentially-faulting instruction for null
2151 // check info (currently consumed only by C1). If
2152 // swap_reg_contains_mark is true then returns -1 as it is assumed
2153 // the calling code has already passed any potential faults.
2154 int biased_locking_enter(Register lock_reg, Register obj_reg,
2155 Register swap_reg, Register tmp_reg,
2156 bool swap_reg_contains_mark,
2157 Label& done, Label* slow_case = NULL,
2158 BiasedLockingCounters* counters = NULL);
2159 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2160
2161
2162 Condition negate_condition(Condition cond);
2163
2164 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2165 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2166 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2167 // here in MacroAssembler. The major exception to this rule is call
2168
2169 // Arithmetics
2170
2171
2172 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2173 void addptr(Address dst, Register src);
2174
2175 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2176 void addptr(Register dst, int32_t src);
2177 void addptr(Register dst, Register src);
2178 void addptr(Register dst, RegisterOrConstant src) {
2179 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2180 else addptr(dst, src.as_register());
2181 }
2182
2183 void andptr(Register dst, int32_t src);
2184 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2185
2186 void cmp8(AddressLiteral src1, int imm);
2187
2188 // renamed to drag out the casting of address to int32_t/intptr_t
2189 void cmp32(Register src1, int32_t imm);
2190
2191 void cmp32(AddressLiteral src1, int32_t imm);
2192 // compare reg - mem, or reg - &mem
2193 void cmp32(Register src1, AddressLiteral src2);
2194
2195 void cmp32(Register src1, Address src2);
2196
2197 #ifndef _LP64
2198 void cmpoop(Address dst, jobject obj);
2199 void cmpoop(Register dst, jobject obj);
2200 #endif // _LP64
2201
2202 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2203 void cmpptr(Address src1, AddressLiteral src2);
2204
2205 void cmpptr(Register src1, AddressLiteral src2);
2206
2207 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2208 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2209 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2210
2211 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2212 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2213
2214 // cmp64 to avoild hiding cmpq
2215 void cmp64(Register src1, AddressLiteral src);
2216
2217 void cmpxchgptr(Register reg, Address adr);
2218
2219 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2220
2221
2222 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2223
2224
2225 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2226
2227 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2228
2229 void shlptr(Register dst, int32_t shift);
2230 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2231
2232 void shrptr(Register dst, int32_t shift);
2233 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2234
2235 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2236 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2237
2238 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2239
2240 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2241 void subptr(Register dst, int32_t src);
2242 void subptr(Register dst, Register src);
2243 void subptr(Register dst, RegisterOrConstant src) {
2244 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2245 else subptr(dst, src.as_register());
2246 }
2247
2248 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2249 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2250
2251 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2252 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2253
2254 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2255
2256
2257
2258 // Helper functions for statistics gathering.
2259 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2260 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2261 // Unconditional atomic increment.
2262 void atomic_incl(AddressLiteral counter_addr);
2263
2264 void lea(Register dst, AddressLiteral adr);
2265 void lea(Address dst, AddressLiteral adr);
2266 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2267
2268 void leal32(Register dst, Address src) { leal(dst, src); }
2269
2270 // Import other testl() methods from the parent class or else
2271 // they will be hidden by the following overriding declaration.
2272 using Assembler::testl;
2273 void testl(Register dst, AddressLiteral src);
2274
2275 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2276 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2277 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2278
2279 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2280 void testptr(Register src1, Register src2);
2281
2282 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2283 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2284
2285 // Calls
2286
2287 void call(Label& L, relocInfo::relocType rtype);
2288 void call(Register entry);
2289
2290 // NOTE: this call tranfers to the effective address of entry NOT
2291 // the address contained by entry. This is because this is more natural
2292 // for jumps/calls.
2293 void call(AddressLiteral entry);
2294
2295 // Jumps
2296
2297 // NOTE: these jumps tranfer to the effective address of dst NOT
2298 // the address contained by dst. This is because this is more natural
2299 // for jumps/calls.
2300 void jump(AddressLiteral dst);
2301 void jump_cc(Condition cc, AddressLiteral dst);
2302
2303 // 32bit can do a case table jump in one instruction but we no longer allow the base
2304 // to be installed in the Address class. This jump will tranfers to the address
2305 // contained in the location described by entry (not the address of entry)
2306 void jump(ArrayAddress entry);
2307
2308 // Floating
2309
2310 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2311 void andpd(XMMRegister dst, AddressLiteral src);
2312
2313 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2314 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2315 void andps(XMMRegister dst, AddressLiteral src);
2316
2317 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2318 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2319 void comiss(XMMRegister dst, AddressLiteral src);
2320
2321 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2322 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2323 void comisd(XMMRegister dst, AddressLiteral src);
2324
2325 void fadd_s(Address src) { Assembler::fadd_s(src); }
2326 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2327
2328 void fldcw(Address src) { Assembler::fldcw(src); }
2329 void fldcw(AddressLiteral src);
2330
2331 void fld_s(int index) { Assembler::fld_s(index); }
2332 void fld_s(Address src) { Assembler::fld_s(src); }
2333 void fld_s(AddressLiteral src);
2334
2335 void fld_d(Address src) { Assembler::fld_d(src); }
2336 void fld_d(AddressLiteral src);
2337
2338 void fld_x(Address src) { Assembler::fld_x(src); }
2339 void fld_x(AddressLiteral src);
2340
2341 void fmul_s(Address src) { Assembler::fmul_s(src); }
2342 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2343
2344 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2345 void ldmxcsr(AddressLiteral src);
2346
2347 private:
2348 // these are private because users should be doing movflt/movdbl
2349
2350 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2351 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2352 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2353 void movss(XMMRegister dst, AddressLiteral src);
2354
2355 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2356 void movlpd(XMMRegister dst, AddressLiteral src);
2357
2358 public:
2359
2360 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2361 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2362 void addsd(XMMRegister dst, AddressLiteral src);
2363
2364 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2365 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2366 void addss(XMMRegister dst, AddressLiteral src);
2367
2368 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2369 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2370 void divsd(XMMRegister dst, AddressLiteral src);
2371
2372 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2373 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2374 void divss(XMMRegister dst, AddressLiteral src);
2375
2376 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2377 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2378 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2379 void movsd(XMMRegister dst, AddressLiteral src);
2380
2381 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2382 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2383 void mulsd(XMMRegister dst, AddressLiteral src);
2384
2385 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2386 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2387 void mulss(XMMRegister dst, AddressLiteral src);
2388
2389 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2390 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2391 void sqrtsd(XMMRegister dst, AddressLiteral src);
2392
2393 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2394 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2395 void sqrtss(XMMRegister dst, AddressLiteral src);
2396
2397 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2398 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2399 void subsd(XMMRegister dst, AddressLiteral src);
2400
2401 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2402 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2403 void subss(XMMRegister dst, AddressLiteral src);
2404
2405 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2406 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2407 void ucomiss(XMMRegister dst, AddressLiteral src);
2408
2409 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2410 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2411 void ucomisd(XMMRegister dst, AddressLiteral src);
2412
2413 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2414 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2415 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2416 void xorpd(XMMRegister dst, AddressLiteral src);
2417
2418 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2419 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2420 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2421 void xorps(XMMRegister dst, AddressLiteral src);
2422
2423 // Data
2424
2425 void cmov32( Condition cc, Register dst, Address src);
2426 void cmov32( Condition cc, Register dst, Register src);
2427
2428 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2429
2430 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2431 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2432
2433 void movoop(Register dst, jobject obj);
2434 void movoop(Address dst, jobject obj);
2435
2436 void movptr(ArrayAddress dst, Register src);
2437 // can this do an lea?
2438 void movptr(Register dst, ArrayAddress src);
2439
2440 void movptr(Register dst, Address src);
2441
2442 void movptr(Register dst, AddressLiteral src);
2443
2444 void movptr(Register dst, intptr_t src);
2445 void movptr(Register dst, Register src);
2446 void movptr(Address dst, intptr_t src);
2447
2448 void movptr(Address dst, Register src);
2449
2450 void movptr(Register dst, RegisterOrConstant src) {
2451 if (src.is_constant()) movptr(dst, src.as_constant());
2452 else movptr(dst, src.as_register());
2453 }
2454
2455 #ifdef _LP64
2456 // Generally the next two are only used for moving NULL
2457 // Although there are situations in initializing the mark word where
2458 // they could be used. They are dangerous.
2459
2460 // They only exist on LP64 so that int32_t and intptr_t are not the same
2461 // and we have ambiguous declarations.
2462
2463 void movptr(Address dst, int32_t imm32);
2464 void movptr(Register dst, int32_t imm32);
2465 #endif // _LP64
2466
2467 // to avoid hiding movl
2468 void mov32(AddressLiteral dst, Register src);
2469 void mov32(Register dst, AddressLiteral src);
2470
2471 // to avoid hiding movb
2472 void movbyte(ArrayAddress dst, int src);
2473
2474 // Can push value or effective address
2475 void pushptr(AddressLiteral src);
2476
2477 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2478 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2479
2480 void pushoop(jobject obj);
2481
2482 // sign extend as need a l to ptr sized element
2483 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2484 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2485
2486 // IndexOf strings.
2487 // Small strings are loaded through stack if they cross page boundary.
2488 void string_indexof(Register str1, Register str2,
2489 Register cnt1, Register cnt2,
2490 int int_cnt2, Register result,
2491 XMMRegister vec, Register tmp);
2492
2493 // IndexOf for constant substrings with size >= 8 elements
2494 // which don't need to be loaded through stack.
2495 void string_indexofC8(Register str1, Register str2,
2496 Register cnt1, Register cnt2,
2497 int int_cnt2, Register result,
2498 XMMRegister vec, Register tmp);
2499
2500 // Smallest code: we don't need to load through stack,
2501 // check string tail.
2502
2503 // Compare strings.
2504 void string_compare(Register str1, Register str2,
2505 Register cnt1, Register cnt2, Register result,
2506 XMMRegister vec1);
2507
2508 // Compare char[] arrays.
2509 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2510 Register limit, Register result, Register chr,
2511 XMMRegister vec1, XMMRegister vec2);
2512
2513 // Fill primitive arrays
2514 void generate_fill(BasicType t, bool aligned,
2515 Register to, Register value, Register count,
2516 Register rtmp, XMMRegister xtmp);
2517
2518 #undef VIRTUAL
2519
2520 };
2521
2522 /**
2523 * class SkipIfEqual:
2524 *
2525 * Instantiating this class will result in assembly code being output that will
2526 * jump around any code emitted between the creation of the instance and it's
2527 * automatic destruction at the end of a scope block, depending on the value of
2528 * the flag passed to the constructor, which will be checked at run-time.
2529 */
2530 class SkipIfEqual {
2531 private:
2532 MacroAssembler* _masm;
2533 Label _label;
2534
2535 public:
2536 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2537 ~SkipIfEqual();
2538 };
2539
2540 #ifdef ASSERT
2541 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2542 #endif
2543
2544 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP