220 #else
221 // make sure code pattern is actually a mov reg, imm32 instruction
222 u_char test_byte = *(u_char*)instruction_address();
223 u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
224 if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
225 #endif // AMD64
226 }
227
228
229 void NativeMovConstReg::print() {
230 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
231 instruction_address(), data());
232 }
233
234 //-------------------------------------------------------------------
235
236 int NativeMovRegMem::instruction_start() const {
237 int off = 0;
238 u_char instr_0 = ubyte_at(off);
239
240 // First check to see if we have a (prefixed or not) xor
241 if ( instr_0 >= instruction_prefix_wide_lo && // 0x40
242 instr_0 <= instruction_prefix_wide_hi) { // 0x4f
243 off++;
244 instr_0 = ubyte_at(off);
245 }
246
247 if (instr_0 == instruction_code_xor) {
248 off += 2;
249 instr_0 = ubyte_at(off);
250 }
251
252 // Now look for the real instruction and the many prefix/size specifiers.
253
254 if (instr_0 == instruction_operandsize_prefix ) { // 0x66
255 off++; // Not SSE instructions
256 instr_0 = ubyte_at(off);
257 }
258
259 if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3
260 instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
261 off++;
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220 #else
221 // make sure code pattern is actually a mov reg, imm32 instruction
222 u_char test_byte = *(u_char*)instruction_address();
223 u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
224 if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
225 #endif // AMD64
226 }
227
228
229 void NativeMovConstReg::print() {
230 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
231 instruction_address(), data());
232 }
233
234 //-------------------------------------------------------------------
235
236 int NativeMovRegMem::instruction_start() const {
237 int off = 0;
238 u_char instr_0 = ubyte_at(off);
239
240 // See comment in Assembler::locate_operand() about VEX prefixes.
241 if (instr_0 == instruction_VEX_prefix_2bytes) {
242 assert((UseAVX > 0), "shouldn't have VEX prefix");
243 NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
244 return 2;
245 }
246 if (instr_0 == instruction_VEX_prefix_3bytes) {
247 assert((UseAVX > 0), "shouldn't have VEX prefix");
248 NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
249 return 3;
250 }
251
252 // First check to see if we have a (prefixed or not) xor
253 if (instr_0 >= instruction_prefix_wide_lo && // 0x40
254 instr_0 <= instruction_prefix_wide_hi) { // 0x4f
255 off++;
256 instr_0 = ubyte_at(off);
257 }
258
259 if (instr_0 == instruction_code_xor) {
260 off += 2;
261 instr_0 = ubyte_at(off);
262 }
263
264 // Now look for the real instruction and the many prefix/size specifiers.
265
266 if (instr_0 == instruction_operandsize_prefix ) { // 0x66
267 off++; // Not SSE instructions
268 instr_0 = ubyte_at(off);
269 }
270
271 if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3
272 instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
273 off++;
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