1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
35
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
49
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
59
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 : 2,
65 monitor : 1,
66 : 1,
67 vmx : 1,
68 : 1,
69 est : 1,
70 : 1,
71 ssse3 : 1,
72 cid : 1,
73 : 2,
74 cmpxchg16: 1,
75 : 4,
76 dca : 1,
77 sse4_1 : 1,
78 sse4_2 : 1,
79 : 2,
80 popcnt : 1,
81 : 8;
82 } bits;
83 };
84
85 union StdCpuid1Edx {
86 uint32_t value;
87 struct {
88 uint32_t : 4,
89 tsc : 1,
90 : 3,
91 cmpxchg8 : 1,
92 : 6,
93 cmov : 1,
94 : 3,
95 clflush : 1,
96 : 3,
97 mmx : 1,
98 fxsr : 1,
99 sse : 1,
100 sse2 : 1,
101 : 1,
102 ht : 1,
103 : 3;
104 } bits;
105 };
106
107 union DcpCpuid4Eax {
108 uint32_t value;
109 struct {
110 uint32_t cache_type : 5,
111 : 21,
112 cores_per_cpu : 6;
113 } bits;
114 };
115
116 union DcpCpuid4Ebx {
117 uint32_t value;
118 struct {
119 uint32_t L1_line_size : 12,
120 partitions : 10,
121 associativity : 10;
122 } bits;
123 };
124
125 union TplCpuidBEbx {
126 uint32_t value;
127 struct {
128 uint32_t logical_cpus : 16,
129 : 16;
130 } bits;
131 };
132
133 union ExtCpuid1Ecx {
134 uint32_t value;
135 struct {
136 uint32_t LahfSahf : 1,
137 CmpLegacy : 1,
138 : 4,
139 lzcnt : 1,
140 sse4a : 1,
141 misalignsse : 1,
142 prefetchw : 1,
143 : 22;
144 } bits;
145 };
146
147 union ExtCpuid1Edx {
148 uint32_t value;
149 struct {
150 uint32_t : 22,
151 mmx_amd : 1,
152 mmx : 1,
153 fxsr : 1,
154 : 4,
155 long_mode : 1,
156 tdnow2 : 1,
157 tdnow : 1;
158 } bits;
159 };
160
161 union ExtCpuid5Ex {
162 uint32_t value;
163 struct {
164 uint32_t L1_line_size : 8,
165 L1_tag_lines : 8,
166 L1_assoc : 8,
167 L1_size : 8;
168 } bits;
169 };
170
171 union ExtCpuid8Ecx {
172 uint32_t value;
173 struct {
174 uint32_t cores_per_cpu : 8,
175 : 24;
176 } bits;
177 };
178
179 protected:
180 static int _cpu;
181 static int _model;
182 static int _stepping;
183 static int _cpuFeatures; // features returned by the "cpuid" instruction
184 // 0 if this instruction is not available
185 static const char* _features_str;
186
187 enum {
188 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
189 CPU_CMOV = (1 << 1),
190 CPU_FXSR = (1 << 2),
191 CPU_HT = (1 << 3),
192 CPU_MMX = (1 << 4),
193 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
194 // may not necessarily support other 3dnow instructions
195 CPU_SSE = (1 << 6),
196 CPU_SSE2 = (1 << 7),
197 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
198 CPU_SSSE3 = (1 << 9),
199 CPU_SSE4A = (1 << 10),
200 CPU_SSE4_1 = (1 << 11),
201 CPU_SSE4_2 = (1 << 12),
202 CPU_POPCNT = (1 << 13),
203 CPU_LZCNT = (1 << 14)
204 } cpuFeatureFlags;
205
206 // cpuid information block. All info derived from executing cpuid with
207 // various function numbers is stored here. Intel and AMD info is
208 // merged in this block: accessor methods disentangle it.
209 //
210 // The info block is laid out in subblocks of 4 dwords corresponding to
211 // eax, ebx, ecx and edx, whether or not they contain anything useful.
212 struct CpuidInfo {
213 // cpuid function 0
214 uint32_t std_max_function;
215 uint32_t std_vendor_name_0;
216 uint32_t std_vendor_name_1;
217 uint32_t std_vendor_name_2;
218
219 // cpuid function 1
220 StdCpuid1Eax std_cpuid1_eax;
221 StdCpuid1Ebx std_cpuid1_ebx;
222 StdCpuid1Ecx std_cpuid1_ecx;
223 StdCpuid1Edx std_cpuid1_edx;
224
225 // cpuid function 4 (deterministic cache parameters)
226 DcpCpuid4Eax dcp_cpuid4_eax;
227 DcpCpuid4Ebx dcp_cpuid4_ebx;
228 uint32_t dcp_cpuid4_ecx; // unused currently
229 uint32_t dcp_cpuid4_edx; // unused currently
230
231 // cpuid function 0xB (processor topology)
232 // ecx = 0
233 uint32_t tpl_cpuidB0_eax;
234 TplCpuidBEbx tpl_cpuidB0_ebx;
235 uint32_t tpl_cpuidB0_ecx; // unused currently
236 uint32_t tpl_cpuidB0_edx; // unused currently
237
238 // ecx = 1
239 uint32_t tpl_cpuidB1_eax;
240 TplCpuidBEbx tpl_cpuidB1_ebx;
241 uint32_t tpl_cpuidB1_ecx; // unused currently
242 uint32_t tpl_cpuidB1_edx; // unused currently
243
244 // ecx = 2
245 uint32_t tpl_cpuidB2_eax;
246 TplCpuidBEbx tpl_cpuidB2_ebx;
247 uint32_t tpl_cpuidB2_ecx; // unused currently
248 uint32_t tpl_cpuidB2_edx; // unused currently
249
250 // cpuid function 0x80000000 // example, unused
251 uint32_t ext_max_function;
252 uint32_t ext_vendor_name_0;
253 uint32_t ext_vendor_name_1;
254 uint32_t ext_vendor_name_2;
255
256 // cpuid function 0x80000001
257 uint32_t ext_cpuid1_eax; // reserved
258 uint32_t ext_cpuid1_ebx; // reserved
259 ExtCpuid1Ecx ext_cpuid1_ecx;
260 ExtCpuid1Edx ext_cpuid1_edx;
261
262 // cpuid functions 0x80000002 thru 0x80000004: example, unused
263 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
264 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
265 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
266
267 // cpuid function 0x80000005 //AMD L1, Intel reserved
268 uint32_t ext_cpuid5_eax; // unused currently
269 uint32_t ext_cpuid5_ebx; // reserved
270 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
271 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
272
273 // cpuid function 0x80000008
274 uint32_t ext_cpuid8_eax; // unused currently
275 uint32_t ext_cpuid8_ebx; // reserved
276 ExtCpuid8Ecx ext_cpuid8_ecx;
277 uint32_t ext_cpuid8_edx; // reserved
278 };
279
280 // The actual cpuid info block
281 static CpuidInfo _cpuid_info;
282
283 // Extractors and predicates
284 static uint32_t extended_cpu_family() {
285 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
286 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
287 return result;
288 }
289 static uint32_t extended_cpu_model() {
290 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
291 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
292 return result;
293 }
294 static uint32_t cpu_stepping() {
295 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
296 return result;
297 }
298 static uint logical_processor_count() {
299 uint result = threads_per_core();
300 return result;
301 }
302 static uint32_t feature_flags() {
303 uint32_t result = 0;
304 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
305 result |= CPU_CX8;
306 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
307 result |= CPU_CMOV;
308 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
309 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
310 result |= CPU_FXSR;
311 // HT flag is set for multi-core processors also.
312 if (threads_per_core() > 1)
313 result |= CPU_HT;
314 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
315 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
316 result |= CPU_MMX;
317 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
318 result |= CPU_SSE;
319 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
320 result |= CPU_SSE2;
321 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
322 result |= CPU_SSE3;
323 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
324 result |= CPU_SSSE3;
325 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
326 result |= CPU_SSE4_1;
327 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
328 result |= CPU_SSE4_2;
329 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
330 result |= CPU_POPCNT;
331
332 // AMD features.
333 if (is_amd()) {
334 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
335 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
336 result |= CPU_3DNOW_PREFETCH;
337 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
338 result |= CPU_LZCNT;
339 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
340 result |= CPU_SSE4A;
341 }
342
343 return result;
344 }
345
346 static void get_processor_features();
347
348 public:
349 // Offsets for cpuid asm stub
350 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
351 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
352 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
353 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
354 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
355 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
356 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
357 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
358 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
359
360 // Initialization
361 static void initialize();
362
363 // Asserts
364 static void assert_is_initialized() {
365 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
366 }
367
368 //
369 // Processor family:
370 // 3 - 386
371 // 4 - 486
372 // 5 - Pentium
373 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
374 // Pentium M, Core Solo, Core Duo, Core2 Duo
375 // family 6 model: 9, 13, 14, 15
376 // 0x0f - Pentium 4, Opteron
377 //
378 // Note: The cpu family should be used to select between
379 // instruction sequences which are valid on all Intel
380 // processors. Use the feature test functions below to
381 // determine whether a particular instruction is supported.
382 //
383 static int cpu_family() { return _cpu;}
384 static bool is_P6() { return cpu_family() >= 6; }
385
386 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
387 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
388
389 static bool supports_processor_topology() {
390 return (_cpuid_info.std_max_function >= 0xB) &&
391 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
392 // Some cpus have max cpuid >= 0xB but do not support processor topology.
393 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
394 }
395
396 static uint cores_per_cpu() {
397 uint result = 1;
398 if (is_intel()) {
399 if (supports_processor_topology()) {
400 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
401 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
402 } else {
403 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
404 }
405 } else if (is_amd()) {
406 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
407 }
408 return result;
409 }
410
411 static uint threads_per_core() {
412 uint result = 1;
413 if (is_intel() && supports_processor_topology()) {
414 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
415 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
416 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
417 cores_per_cpu();
418 }
419 return result;
420 }
421
422 static intx prefetch_data_size() {
423 intx result = 0;
424 if (is_intel()) {
425 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
426 } else if (is_amd()) {
427 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
428 }
429 if (result < 32) // not defined ?
430 result = 32; // 32 bytes by default on x86 and other x64
431 return result;
432 }
433
434 //
435 // Feature identification
436 //
437 static bool supports_cpuid() { return _cpuFeatures != 0; }
438 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
439 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
440 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
441 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
442 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
443 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
444 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
445 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
446 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
447 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
448 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
449 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
450 //
451 // AMD features
452 //
453 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
454 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
455 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
456 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
457
458 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
459 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
460 supports_sse3() && _model != 0x1C; }
461
462 static bool supports_compare_and_exchange() { return true; }
463
464 static const char* cpu_features() { return _features_str; }
465
466 static intx allocate_prefetch_distance() {
467 // This method should be called before allocate_prefetch_style().
468 //
469 // Hardware prefetching (distance/size in bytes):
470 // Pentium 3 - 64 / 32
471 // Pentium 4 - 256 / 128
472 // Athlon - 64 / 32 ????
473 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
474 // Core - 128 / 64
475 //
476 // Software prefetching (distance in bytes / instruction with best score):
477 // Pentium 3 - 128 / prefetchnta
478 // Pentium 4 - 512 / prefetchnta
479 // Athlon - 128 / prefetchnta
480 // Opteron - 256 / prefetchnta
481 // Core - 256 / prefetchnta
482 // It will be used only when AllocatePrefetchStyle > 0
483
484 intx count = AllocatePrefetchDistance;
485 if (count < 0) { // default ?
486 if (is_amd()) { // AMD
487 if (supports_sse2())
488 count = 256; // Opteron
489 else
490 count = 128; // Athlon
491 } else { // Intel
492 if (supports_sse2())
493 if (cpu_family() == 6) {
494 count = 256; // Pentium M, Core, Core2
495 } else {
496 count = 512; // Pentium 4
497 }
498 else
499 count = 128; // Pentium 3 (and all other old CPUs)
500 }
501 }
502 return count;
503 }
504 static intx allocate_prefetch_style() {
505 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
506 // Return 0 if AllocatePrefetchDistance was not defined.
507 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
508 }
509
510 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
511 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
512 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
513 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
514
515 // gc copy/scan is disabled if prefetchw isn't supported, because
516 // Prefetch::write emits an inlined prefetchw on Linux.
517 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
518 // The used prefetcht0 instruction works for both amd64 and em64t.
519 static intx prefetch_copy_interval_in_bytes() {
520 intx interval = PrefetchCopyIntervalInBytes;
521 return interval >= 0 ? interval : 576;
522 }
523 static intx prefetch_scan_interval_in_bytes() {
524 intx interval = PrefetchScanIntervalInBytes;
525 return interval >= 0 ? interval : 576;
526 }
527 static intx prefetch_fields_ahead() {
528 intx count = PrefetchFieldsAhead;
529 return count >= 0 ? count : 1;
530 }
531 };
532
533 #endif // CPU_X86_VM_VM_VERSION_X86_HPP