1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedOops) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_oop_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 int bit_width = width * 8;
682 jlong elt_val = con;
683 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
684 jlong val = elt_val;
685 for (int i = 0; i < count - 1; i++) {
686 val <<= bit_width;
687 val |= elt_val;
688 }
689 jdouble dval = *((jdouble*) &val); // coerce to double type
690 return dval;
691 }
692
693 // Standard Sparc opcode form2 field breakdown
694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
695 f0 &= (1<<19)-1; // Mask displacement to 19 bits
696 int op = (f30 << 30) |
697 (f29 << 29) |
698 (f25 << 25) |
699 (f22 << 22) |
700 (f20 << 20) |
701 (f19 << 19) |
702 (f0 << 0);
703 cbuf.insts()->emit_int32(op);
704 }
705
706 // Standard Sparc opcode form2 field breakdown
707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
708 f0 >>= 10; // Drop 10 bits
709 f0 &= (1<<22)-1; // Mask displacement to 22 bits
710 int op = (f30 << 30) |
711 (f25 << 25) |
712 (f22 << 22) |
713 (f0 << 0);
714 cbuf.insts()->emit_int32(op);
715 }
716
717 // Standard Sparc opcode form3 field breakdown
718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
719 int op = (f30 << 30) |
720 (f25 << 25) |
721 (f19 << 19) |
722 (f14 << 14) |
723 (f5 << 5) |
724 (f0 << 0);
725 cbuf.insts()->emit_int32(op);
726 }
727
728 // Standard Sparc opcode form3 field breakdown
729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
730 simm13 &= (1<<13)-1; // Mask to 13 bits
731 int op = (f30 << 30) |
732 (f25 << 25) |
733 (f19 << 19) |
734 (f14 << 14) |
735 (1 << 13) | // bit to indicate immediate-mode
736 (simm13<<0);
737 cbuf.insts()->emit_int32(op);
738 }
739
740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
741 simm10 &= (1<<10)-1; // Mask to 10 bits
742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
743 }
744
745 #ifdef ASSERT
746 // Helper function for VerifyOops in emit_form3_mem_reg
747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
748 warning("VerifyOops encountered unexpected instruction:");
749 n->dump(2);
750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
751 }
752 #endif
753
754
755 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
756 int src1_enc, int disp32, int src2_enc, int dst_enc) {
757
758 #ifdef ASSERT
759 // The following code implements the +VerifyOops feature.
760 // It verifies oop values which are loaded into or stored out of
761 // the current method activation. +VerifyOops complements techniques
762 // like ScavengeALot, because it eagerly inspects oops in transit,
763 // as they enter or leave the stack, as opposed to ScavengeALot,
764 // which inspects oops "at rest", in the stack or heap, at safepoints.
765 // For this reason, +VerifyOops can sometimes detect bugs very close
766 // to their point of creation. It can also serve as a cross-check
767 // on the validity of oop maps, when used toegether with ScavengeALot.
768
769 // It would be good to verify oops at other points, especially
770 // when an oop is used as a base pointer for a load or store.
771 // This is presently difficult, because it is hard to know when
772 // a base address is biased or not. (If we had such information,
773 // it would be easy and useful to make a two-argument version of
774 // verify_oop which unbiases the base, and performs verification.)
775
776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
777 bool is_verified_oop_base = false;
778 bool is_verified_oop_load = false;
779 bool is_verified_oop_store = false;
780 int tmp_enc = -1;
781 if (VerifyOops && src1_enc != R_SP_enc) {
782 // classify the op, mainly for an assert check
783 int st_op = 0, ld_op = 0;
784 switch (primary) {
785 case Assembler::stb_op3: st_op = Op_StoreB; break;
786 case Assembler::sth_op3: st_op = Op_StoreC; break;
787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
788 case Assembler::stw_op3: st_op = Op_StoreI; break;
789 case Assembler::std_op3: st_op = Op_StoreL; break;
790 case Assembler::stf_op3: st_op = Op_StoreF; break;
791 case Assembler::stdf_op3: st_op = Op_StoreD; break;
792
793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
794 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
795 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
796 case Assembler::ldx_op3: // may become LoadP or stay LoadI
797 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
798 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
799 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
800 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
801 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
804
805 default: ShouldNotReachHere();
806 }
807 if (tertiary == REGP_OP) {
808 if (st_op == Op_StoreI) st_op = Op_StoreP;
809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
810 else ShouldNotReachHere();
811 if (st_op) {
812 // a store
813 // inputs are (0:control, 1:memory, 2:address, 3:value)
814 Node* n2 = n->in(3);
815 if (n2 != NULL) {
816 const Type* t = n2->bottom_type();
817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 } else {
820 // a load
821 const Type* t = n->bottom_type();
822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 }
825
826 if (ld_op) {
827 // a Load
828 // inputs are (0:control, 1:memory, 2:address)
829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
830 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
843 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
845 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
846 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
847 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
848 !(n->rule() == loadUB_rule)) {
849 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
850 }
851 } else if (st_op) {
852 // a Store
853 // inputs are (0:control, 1:memory, 2:address, 3:value)
854 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
855 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
856 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
857 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
858 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
860 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
862 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
863 verify_oops_warning(n, n->ideal_Opcode(), st_op);
864 }
865 }
866
867 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
868 Node* addr = n->in(2);
869 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
870 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
871 if (atype != NULL) {
872 intptr_t offset = get_offset_from_base(n, atype, disp32);
873 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
874 if (offset != offset_2) {
875 get_offset_from_base(n, atype, disp32);
876 get_offset_from_base_2(n, atype, disp32);
877 }
878 assert(offset == offset_2, "different offsets");
879 if (offset == disp32) {
880 // we now know that src1 is a true oop pointer
881 is_verified_oop_base = true;
882 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
883 if( primary == Assembler::ldd_op3 ) {
884 is_verified_oop_base = false; // Cannot 'ldd' into O7
885 } else {
886 tmp_enc = dst_enc;
887 dst_enc = R_O7_enc; // Load into O7; preserve source oop
888 assert(src1_enc != dst_enc, "");
889 }
890 }
891 }
892 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
893 || offset == oopDesc::mark_offset_in_bytes())) {
894 // loading the mark should not be allowed either, but
895 // we don't check this since it conflicts with InlineObjectHash
896 // usage of LoadINode to get the mark. We could keep the
897 // check if we create a new LoadMarkNode
898 // but do not verify the object before its header is initialized
899 ShouldNotReachHere();
900 }
901 }
902 }
903 }
904 }
905 #endif
906
907 uint instr;
908 instr = (Assembler::ldst_op << 30)
909 | (dst_enc << 25)
910 | (primary << 19)
911 | (src1_enc << 14);
912
913 uint index = src2_enc;
914 int disp = disp32;
915
916 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
917 disp += STACK_BIAS;
918
919 // We should have a compiler bailout here rather than a guarantee.
920 // Better yet would be some mechanism to handle variable-size matches correctly.
921 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
922
923 if( disp == 0 ) {
924 // use reg-reg form
925 // bit 13 is already zero
926 instr |= index;
927 } else {
928 // use reg-imm form
929 instr |= 0x00002000; // set bit 13 to one
930 instr |= disp & 0x1FFF;
931 }
932
933 cbuf.insts()->emit_int32(instr);
934
935 #ifdef ASSERT
936 {
937 MacroAssembler _masm(&cbuf);
938 if (is_verified_oop_base) {
939 __ verify_oop(reg_to_register_object(src1_enc));
940 }
941 if (is_verified_oop_store) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 if (tmp_enc != -1) {
945 __ mov(O7, reg_to_register_object(tmp_enc));
946 }
947 if (is_verified_oop_load) {
948 __ verify_oop(reg_to_register_object(dst_enc));
949 }
950 }
951 #endif
952 }
953
954 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
955 // The method which records debug information at every safepoint
956 // expects the call to be the first instruction in the snippet as
957 // it creates a PcDesc structure which tracks the offset of a call
958 // from the start of the codeBlob. This offset is computed as
959 // code_end() - code_begin() of the code which has been emitted
960 // so far.
961 // In this particular case we have skirted around the problem by
962 // putting the "mov" instruction in the delay slot but the problem
963 // may bite us again at some other point and a cleaner/generic
964 // solution using relocations would be needed.
965 MacroAssembler _masm(&cbuf);
966 __ set_inst_mark();
967
968 // We flush the current window just so that there is a valid stack copy
969 // the fact that the current window becomes active again instantly is
970 // not a problem there is nothing live in it.
971
972 #ifdef ASSERT
973 int startpos = __ offset();
974 #endif /* ASSERT */
975
976 __ call((address)entry_point, rtype);
977
978 if (preserve_g2) __ delayed()->mov(G2, L7);
979 else __ delayed()->nop();
980
981 if (preserve_g2) __ mov(L7, G2);
982
983 #ifdef ASSERT
984 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
985 #ifdef _LP64
986 // Trash argument dump slots.
987 __ set(0xb0b8ac0db0b8ac0d, G1);
988 __ mov(G1, G5);
989 __ stx(G1, SP, STACK_BIAS + 0x80);
990 __ stx(G1, SP, STACK_BIAS + 0x88);
991 __ stx(G1, SP, STACK_BIAS + 0x90);
992 __ stx(G1, SP, STACK_BIAS + 0x98);
993 __ stx(G1, SP, STACK_BIAS + 0xA0);
994 __ stx(G1, SP, STACK_BIAS + 0xA8);
995 #else // _LP64
996 // this is also a native call, so smash the first 7 stack locations,
997 // and the various registers
998
999 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1000 // while [SP+0x44..0x58] are the argument dump slots.
1001 __ set((intptr_t)0xbaadf00d, G1);
1002 __ mov(G1, G5);
1003 __ sllx(G1, 32, G1);
1004 __ or3(G1, G5, G1);
1005 __ mov(G1, G5);
1006 __ stx(G1, SP, 0x40);
1007 __ stx(G1, SP, 0x48);
1008 __ stx(G1, SP, 0x50);
1009 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1010 #endif // _LP64
1011 }
1012 #endif /*ASSERT*/
1013 }
1014
1015 //=============================================================================
1016 // REQUIRED FUNCTIONALITY for encoding
1017 void emit_lo(CodeBuffer &cbuf, int val) { }
1018 void emit_hi(CodeBuffer &cbuf, int val) { }
1019
1020
1021 //=============================================================================
1022 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1023
1024 int Compile::ConstantTable::calculate_table_base_offset() const {
1025 if (UseRDPCForConstantTableBase) {
1026 // The table base offset might be less but then it fits into
1027 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1028 return Assembler::min_simm13();
1029 } else {
1030 int offset = -(size() / 2);
1031 if (!Assembler::is_simm13(offset)) {
1032 offset = Assembler::min_simm13();
1033 }
1034 return offset;
1035 }
1036 }
1037
1038 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1039 Compile* C = ra_->C;
1040 Compile::ConstantTable& constant_table = C->constant_table();
1041 MacroAssembler _masm(&cbuf);
1042
1043 Register r = as_Register(ra_->get_encode(this));
1044 CodeSection* consts_section = __ code()->consts();
1045 int consts_size = consts_section->align_at_start(consts_section->size());
1046 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1047
1048 if (UseRDPCForConstantTableBase) {
1049 // For the following RDPC logic to work correctly the consts
1050 // section must be allocated right before the insts section. This
1051 // assert checks for that. The layout and the SECT_* constants
1052 // are defined in src/share/vm/asm/codeBuffer.hpp.
1053 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1054 int insts_offset = __ offset();
1055
1056 // Layout:
1057 //
1058 // |----------- consts section ------------|----------- insts section -----------...
1059 // |------ constant table -----|- padding -|------------------x----
1060 // \ current PC (RDPC instruction)
1061 // |<------------- consts_size ----------->|<- insts_offset ->|
1062 // \ table base
1063 // The table base offset is later added to the load displacement
1064 // so it has to be negative.
1065 int table_base_offset = -(consts_size + insts_offset);
1066 int disp;
1067
1068 // If the displacement from the current PC to the constant table
1069 // base fits into simm13 we set the constant table base to the
1070 // current PC.
1071 if (Assembler::is_simm13(table_base_offset)) {
1072 constant_table.set_table_base_offset(table_base_offset);
1073 disp = 0;
1074 } else {
1075 // Otherwise we set the constant table base offset to the
1076 // maximum negative displacement of load instructions to keep
1077 // the disp as small as possible:
1078 //
1079 // |<------------- consts_size ----------->|<- insts_offset ->|
1080 // |<--------- min_simm13 --------->|<-------- disp --------->|
1081 // \ table base
1082 table_base_offset = Assembler::min_simm13();
1083 constant_table.set_table_base_offset(table_base_offset);
1084 disp = (consts_size + insts_offset) + table_base_offset;
1085 }
1086
1087 __ rdpc(r);
1088
1089 if (disp != 0) {
1090 assert(r != O7, "need temporary");
1091 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1092 }
1093 }
1094 else {
1095 // Materialize the constant table base.
1096 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1097 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1098 AddressLiteral base(baseaddr, rspec);
1099 __ set(base, r);
1100 }
1101 }
1102
1103 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1104 if (UseRDPCForConstantTableBase) {
1105 // This is really the worst case but generally it's only 1 instruction.
1106 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1107 } else {
1108 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1109 }
1110 }
1111
1112 #ifndef PRODUCT
1113 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1114 char reg[128];
1115 ra_->dump_register(this, reg);
1116 if (UseRDPCForConstantTableBase) {
1117 st->print("RDPC %s\t! constant table base", reg);
1118 } else {
1119 st->print("SET &constanttable,%s\t! constant table base", reg);
1120 }
1121 }
1122 #endif
1123
1124
1125 //=============================================================================
1126
1127 #ifndef PRODUCT
1128 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1129 Compile* C = ra_->C;
1130
1131 for (int i = 0; i < OptoPrologueNops; i++) {
1132 st->print_cr("NOP"); st->print("\t");
1133 }
1134
1135 if( VerifyThread ) {
1136 st->print_cr("Verify_Thread"); st->print("\t");
1137 }
1138
1139 size_t framesize = C->frame_slots() << LogBytesPerInt;
1140
1141 // Calls to C2R adapters often do not accept exceptional returns.
1142 // We require that their callers must bang for them. But be careful, because
1143 // some VM calls (such as call site linkage) can use several kilobytes of
1144 // stack. But the stack safety zone should account for that.
1145 // See bugs 4446381, 4468289, 4497237.
1146 if (C->need_stack_bang(framesize)) {
1147 st->print_cr("! stack bang"); st->print("\t");
1148 }
1149
1150 if (Assembler::is_simm13(-framesize)) {
1151 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1152 } else {
1153 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1154 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1155 st->print ("SAVE R_SP,R_G3,R_SP");
1156 }
1157
1158 }
1159 #endif
1160
1161 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1162 Compile* C = ra_->C;
1163 MacroAssembler _masm(&cbuf);
1164
1165 for (int i = 0; i < OptoPrologueNops; i++) {
1166 __ nop();
1167 }
1168
1169 __ verify_thread();
1170
1171 size_t framesize = C->frame_slots() << LogBytesPerInt;
1172 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1173 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1174
1175 // Calls to C2R adapters often do not accept exceptional returns.
1176 // We require that their callers must bang for them. But be careful, because
1177 // some VM calls (such as call site linkage) can use several kilobytes of
1178 // stack. But the stack safety zone should account for that.
1179 // See bugs 4446381, 4468289, 4497237.
1180 if (C->need_stack_bang(framesize)) {
1181 __ generate_stack_overflow_check(framesize);
1182 }
1183
1184 if (Assembler::is_simm13(-framesize)) {
1185 __ save(SP, -framesize, SP);
1186 } else {
1187 __ sethi(-framesize & ~0x3ff, G3);
1188 __ add(G3, -framesize & 0x3ff, G3);
1189 __ save(SP, G3, SP);
1190 }
1191 C->set_frame_complete( __ offset() );
1192
1193 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1194 // NOTE: We set the table base offset here because users might be
1195 // emitted before MachConstantBaseNode.
1196 Compile::ConstantTable& constant_table = C->constant_table();
1197 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1198 }
1199 }
1200
1201 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1202 return MachNode::size(ra_);
1203 }
1204
1205 int MachPrologNode::reloc() const {
1206 return 10; // a large enough number
1207 }
1208
1209 //=============================================================================
1210 #ifndef PRODUCT
1211 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1212 Compile* C = ra_->C;
1213
1214 if( do_polling() && ra_->C->is_method_compilation() ) {
1215 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1216 #ifdef _LP64
1217 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1218 #else
1219 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1220 #endif
1221 }
1222
1223 if( do_polling() )
1224 st->print("RET\n\t");
1225
1226 st->print("RESTORE");
1227 }
1228 #endif
1229
1230 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1231 MacroAssembler _masm(&cbuf);
1232 Compile* C = ra_->C;
1233
1234 __ verify_thread();
1235
1236 // If this does safepoint polling, then do it here
1237 if( do_polling() && ra_->C->is_method_compilation() ) {
1238 AddressLiteral polling_page(os::get_polling_page());
1239 __ sethi(polling_page, L0);
1240 __ relocate(relocInfo::poll_return_type);
1241 __ ld_ptr( L0, 0, G0 );
1242 }
1243
1244 // If this is a return, then stuff the restore in the delay slot
1245 if( do_polling() ) {
1246 __ ret();
1247 __ delayed()->restore();
1248 } else {
1249 __ restore();
1250 }
1251 }
1252
1253 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1254 return MachNode::size(ra_);
1255 }
1256
1257 int MachEpilogNode::reloc() const {
1258 return 16; // a large enough number
1259 }
1260
1261 const Pipeline * MachEpilogNode::pipeline() const {
1262 return MachNode::pipeline_class();
1263 }
1264
1265 int MachEpilogNode::safepoint_offset() const {
1266 assert( do_polling(), "no return for this epilog node");
1267 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1268 }
1269
1270 //=============================================================================
1271
1272 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1273 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1274 static enum RC rc_class( OptoReg::Name reg ) {
1275 if( !OptoReg::is_valid(reg) ) return rc_bad;
1276 if (OptoReg::is_stack(reg)) return rc_stack;
1277 VMReg r = OptoReg::as_VMReg(reg);
1278 if (r->is_Register()) return rc_int;
1279 assert(r->is_FloatRegister(), "must be");
1280 return rc_float;
1281 }
1282
1283 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1284 if( cbuf ) {
1285 // Better yet would be some mechanism to handle variable-size matches correctly
1286 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1287 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1288 } else {
1289 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1290 }
1291 }
1292 #ifndef PRODUCT
1293 else if( !do_size ) {
1294 if( size != 0 ) st->print("\n\t");
1295 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1296 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1297 }
1298 #endif
1299 return size+4;
1300 }
1301
1302 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1303 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1304 #ifndef PRODUCT
1305 else if( !do_size ) {
1306 if( size != 0 ) st->print("\n\t");
1307 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1308 }
1309 #endif
1310 return size+4;
1311 }
1312
1313 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1314 PhaseRegAlloc *ra_,
1315 bool do_size,
1316 outputStream* st ) const {
1317 // Get registers to move
1318 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1319 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1320 OptoReg::Name dst_second = ra_->get_reg_second(this );
1321 OptoReg::Name dst_first = ra_->get_reg_first(this );
1322
1323 enum RC src_second_rc = rc_class(src_second);
1324 enum RC src_first_rc = rc_class(src_first);
1325 enum RC dst_second_rc = rc_class(dst_second);
1326 enum RC dst_first_rc = rc_class(dst_first);
1327
1328 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1329
1330 // Generate spill code!
1331 int size = 0;
1332
1333 if( src_first == dst_first && src_second == dst_second )
1334 return size; // Self copy, no move
1335
1336 // --------------------------------------
1337 // Check for mem-mem move. Load into unused float registers and fall into
1338 // the float-store case.
1339 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1340 int offset = ra_->reg2offset(src_first);
1341 // Further check for aligned-adjacent pair, so we can use a double load
1342 if( (src_first&1)==0 && src_first+1 == src_second ) {
1343 src_second = OptoReg::Name(R_F31_num);
1344 src_second_rc = rc_float;
1345 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1346 } else {
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1348 }
1349 src_first = OptoReg::Name(R_F30_num);
1350 src_first_rc = rc_float;
1351 }
1352
1353 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1354 int offset = ra_->reg2offset(src_second);
1355 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1356 src_second = OptoReg::Name(R_F31_num);
1357 src_second_rc = rc_float;
1358 }
1359
1360 // --------------------------------------
1361 // Check for float->int copy; requires a trip through memory
1362 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1363 int offset = frame::register_save_words*wordSize;
1364 if (cbuf) {
1365 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1366 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1367 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1368 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1369 }
1370 #ifndef PRODUCT
1371 else if (!do_size) {
1372 if (size != 0) st->print("\n\t");
1373 st->print( "SUB R_SP,16,R_SP\n");
1374 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1375 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1376 st->print("\tADD R_SP,16,R_SP\n");
1377 }
1378 #endif
1379 size += 16;
1380 }
1381
1382 // Check for float->int copy on T4
1383 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1384 // Further check for aligned-adjacent pair, so we can use a double move
1385 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1386 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1387 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1388 }
1389 // Check for int->float copy on T4
1390 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1395 }
1396
1397 // --------------------------------------
1398 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1399 // In such cases, I have to do the big-endian swap. For aligned targets, the
1400 // hardware does the flop for me. Doubles are always aligned, so no problem
1401 // there. Misaligned sources only come from native-long-returns (handled
1402 // special below).
1403 #ifndef _LP64
1404 if( src_first_rc == rc_int && // source is already big-endian
1405 src_second_rc != rc_bad && // 64-bit move
1406 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1407 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1408 // Do the big-endian flop.
1409 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1410 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1411 }
1412 #endif
1413
1414 // --------------------------------------
1415 // Check for integer reg-reg copy
1416 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1417 #ifndef _LP64
1418 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1419 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1420 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1421 // operand contains the least significant word of the 64-bit value and vice versa.
1422 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1423 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1424 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1425 if( cbuf ) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1427 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1428 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1429 #ifndef PRODUCT
1430 } else if( !do_size ) {
1431 if( size != 0 ) st->print("\n\t");
1432 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1433 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1434 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1435 #endif
1436 }
1437 return size+12;
1438 }
1439 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1440 // returning a long value in I0/I1
1441 // a SpillCopy must be able to target a return instruction's reg_class
1442 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1443 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1444 // operand contains the least significant word of the 64-bit value and vice versa.
1445 OptoReg::Name tdest = dst_first;
1446
1447 if (src_first == dst_first) {
1448 tdest = OptoReg::Name(R_O7_num);
1449 size += 4;
1450 }
1451
1452 if( cbuf ) {
1453 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1454 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1455 // ShrL_reg_imm6
1456 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1457 // ShrR_reg_imm6 src, 0, dst
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1459 if (tdest != dst_first) {
1460 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1461 }
1462 }
1463 #ifndef PRODUCT
1464 else if( !do_size ) {
1465 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1466 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1467 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1468 if (tdest != dst_first) {
1469 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1470 }
1471 }
1472 #endif // PRODUCT
1473 return size+8;
1474 }
1475 #endif // !_LP64
1476 // Else normal reg-reg copy
1477 assert( src_second != dst_first, "smashed second before evacuating it" );
1478 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1479 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1480 // This moves an aligned adjacent pair.
1481 // See if we are done.
1482 if( src_first+1 == src_second && dst_first+1 == dst_second )
1483 return size;
1484 }
1485
1486 // Check for integer store
1487 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1488 int offset = ra_->reg2offset(dst_first);
1489 // Further check for aligned-adjacent pair, so we can use a double store
1490 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1491 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1492 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1493 }
1494
1495 // Check for integer load
1496 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1497 int offset = ra_->reg2offset(src_first);
1498 // Further check for aligned-adjacent pair, so we can use a double load
1499 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1500 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1501 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1502 }
1503
1504 // Check for float reg-reg copy
1505 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1506 // Further check for aligned-adjacent pair, so we can use a double move
1507 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1508 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1509 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1510 }
1511
1512 // Check for float store
1513 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1514 int offset = ra_->reg2offset(dst_first);
1515 // Further check for aligned-adjacent pair, so we can use a double store
1516 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1517 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1518 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1519 }
1520
1521 // Check for float load
1522 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1523 int offset = ra_->reg2offset(src_first);
1524 // Further check for aligned-adjacent pair, so we can use a double load
1525 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1526 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1527 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1528 }
1529
1530 // --------------------------------------------------------------------
1531 // Check for hi bits still needing moving. Only happens for misaligned
1532 // arguments to native calls.
1533 if( src_second == dst_second )
1534 return size; // Self copy; no move
1535 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1536
1537 #ifndef _LP64
1538 // In the LP64 build, all registers can be moved as aligned/adjacent
1539 // pairs, so there's never any need to move the high bits separately.
1540 // The 32-bit builds have to deal with the 32-bit ABI which can force
1541 // all sorts of silly alignment problems.
1542
1543 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1544 // 32-bits of a 64-bit register, but are needed in low bits of another
1545 // register (else it's a hi-bits-to-hi-bits copy which should have
1546 // happened already as part of a 64-bit move)
1547 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1548 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1549 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1550 // Shift src_second down to dst_second's low bits.
1551 if( cbuf ) {
1552 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1553 #ifndef PRODUCT
1554 } else if( !do_size ) {
1555 if( size != 0 ) st->print("\n\t");
1556 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1557 #endif
1558 }
1559 return size+4;
1560 }
1561
1562 // Check for high word integer store. Must down-shift the hi bits
1563 // into a temp register, then fall into the case of storing int bits.
1564 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1565 // Shift src_second down to dst_second's low bits.
1566 if( cbuf ) {
1567 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1568 #ifndef PRODUCT
1569 } else if( !do_size ) {
1570 if( size != 0 ) st->print("\n\t");
1571 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1572 #endif
1573 }
1574 size+=4;
1575 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1576 }
1577
1578 // Check for high word integer load
1579 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1580 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1581
1582 // Check for high word integer store
1583 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1584 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1585
1586 // Check for high word float store
1587 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1588 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1589
1590 #endif // !_LP64
1591
1592 Unimplemented();
1593 }
1594
1595 #ifndef PRODUCT
1596 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1597 implementation( NULL, ra_, false, st );
1598 }
1599 #endif
1600
1601 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1602 implementation( &cbuf, ra_, false, NULL );
1603 }
1604
1605 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1606 return implementation( NULL, ra_, true, NULL );
1607 }
1608
1609 //=============================================================================
1610 #ifndef PRODUCT
1611 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1612 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1613 }
1614 #endif
1615
1616 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1617 MacroAssembler _masm(&cbuf);
1618 for(int i = 0; i < _count; i += 1) {
1619 __ nop();
1620 }
1621 }
1622
1623 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1624 return 4 * _count;
1625 }
1626
1627
1628 //=============================================================================
1629 #ifndef PRODUCT
1630 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1631 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1632 int reg = ra_->get_reg_first(this);
1633 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1634 }
1635 #endif
1636
1637 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1638 MacroAssembler _masm(&cbuf);
1639 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1640 int reg = ra_->get_encode(this);
1641
1642 if (Assembler::is_simm13(offset)) {
1643 __ add(SP, offset, reg_to_register_object(reg));
1644 } else {
1645 __ set(offset, O7);
1646 __ add(SP, O7, reg_to_register_object(reg));
1647 }
1648 }
1649
1650 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1651 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1652 assert(ra_ == ra_->C->regalloc(), "sanity");
1653 return ra_->C->scratch_emit_size(this);
1654 }
1655
1656 //=============================================================================
1657
1658 // emit call stub, compiled java to interpretor
1659 void emit_java_to_interp(CodeBuffer &cbuf ) {
1660
1661 // Stub is fixed up when the corresponding call is converted from calling
1662 // compiled code to calling interpreted code.
1663 // set (empty), G5
1664 // jmp -1
1665
1666 address mark = cbuf.insts_mark(); // get mark within main instrs section
1667
1668 MacroAssembler _masm(&cbuf);
1669
1670 address base =
1671 __ start_a_stub(Compile::MAX_stubs_size);
1672 if (base == NULL) return; // CodeBuffer::expand failed
1673
1674 // static stub relocation stores the instruction address of the call
1675 __ relocate(static_stub_Relocation::spec(mark));
1676
1677 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1678
1679 __ set_inst_mark();
1680 AddressLiteral addrlit(-1);
1681 __ JUMP(addrlit, G3, 0);
1682
1683 __ delayed()->nop();
1684
1685 // Update current stubs pointer and restore code_end.
1686 __ end_a_stub();
1687 }
1688
1689 // size of call stub, compiled java to interpretor
1690 uint size_java_to_interp() {
1691 // This doesn't need to be accurate but it must be larger or equal to
1692 // the real size of the stub.
1693 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1694 NativeJump::instruction_size + // sethi; jmp; nop
1695 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1696 }
1697 // relocation entries for call stub, compiled java to interpretor
1698 uint reloc_java_to_interp() {
1699 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1700 }
1701
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1706 st->print_cr("\nUEP:");
1707 #ifdef _LP64
1708 if (UseCompressedOops) {
1709 assert(Universe::heap() != NULL, "java heap should be initialized");
1710 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1711 st->print_cr("\tSLL R_G5,3,R_G5");
1712 if (Universe::narrow_oop_base() != NULL)
1713 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1714 } else {
1715 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1716 }
1717 st->print_cr("\tCMP R_G5,R_G3" );
1718 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1719 #else // _LP64
1720 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1721 st->print_cr("\tCMP R_G5,R_G3" );
1722 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1723 #endif // _LP64
1724 }
1725 #endif
1726
1727 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1728 MacroAssembler _masm(&cbuf);
1729 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1730 Register temp_reg = G3;
1731 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1732
1733 // Load klass from receiver
1734 __ load_klass(O0, temp_reg);
1735 // Compare against expected klass
1736 __ cmp(temp_reg, G5_ic_reg);
1737 // Branch to miss code, checks xcc or icc depending
1738 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1739 }
1740
1741 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1742 return MachNode::size(ra_);
1743 }
1744
1745
1746 //=============================================================================
1747
1748 uint size_exception_handler() {
1749 if (TraceJumps) {
1750 return (400); // just a guess
1751 }
1752 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1753 }
1754
1755 uint size_deopt_handler() {
1756 if (TraceJumps) {
1757 return (400); // just a guess
1758 }
1759 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1760 }
1761
1762 // Emit exception handler code.
1763 int emit_exception_handler(CodeBuffer& cbuf) {
1764 Register temp_reg = G3;
1765 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1766 MacroAssembler _masm(&cbuf);
1767
1768 address base =
1769 __ start_a_stub(size_exception_handler());
1770 if (base == NULL) return 0; // CodeBuffer::expand failed
1771
1772 int offset = __ offset();
1773
1774 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1775 __ delayed()->nop();
1776
1777 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1778
1779 __ end_a_stub();
1780
1781 return offset;
1782 }
1783
1784 int emit_deopt_handler(CodeBuffer& cbuf) {
1785 // Can't use any of the current frame's registers as we may have deopted
1786 // at a poll and everything (including G3) can be live.
1787 Register temp_reg = L0;
1788 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1789 MacroAssembler _masm(&cbuf);
1790
1791 address base =
1792 __ start_a_stub(size_deopt_handler());
1793 if (base == NULL) return 0; // CodeBuffer::expand failed
1794
1795 int offset = __ offset();
1796 __ save_frame(0);
1797 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1798 __ delayed()->restore();
1799
1800 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1801
1802 __ end_a_stub();
1803 return offset;
1804
1805 }
1806
1807 // Given a register encoding, produce a Integer Register object
1808 static Register reg_to_register_object(int register_encoding) {
1809 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1810 return as_Register(register_encoding);
1811 }
1812
1813 // Given a register encoding, produce a single-precision Float Register object
1814 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1815 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1816 return as_SingleFloatRegister(register_encoding);
1817 }
1818
1819 // Given a register encoding, produce a double-precision Float Register object
1820 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1821 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1822 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1823 return as_DoubleFloatRegister(register_encoding);
1824 }
1825
1826 const bool Matcher::match_rule_supported(int opcode) {
1827 if (!has_match_rule(opcode))
1828 return false;
1829
1830 switch (opcode) {
1831 case Op_CountLeadingZerosI:
1832 case Op_CountLeadingZerosL:
1833 case Op_CountTrailingZerosI:
1834 case Op_CountTrailingZerosL:
1835 case Op_PopCountI:
1836 case Op_PopCountL:
1837 if (!UsePopCountInstruction)
1838 return false;
1839 break;
1840 }
1841
1842 return true; // Per default match rules are supported.
1843 }
1844
1845 int Matcher::regnum_to_fpu_offset(int regnum) {
1846 return regnum - 32; // The FP registers are in the second chunk
1847 }
1848
1849 #ifdef ASSERT
1850 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1851 #endif
1852
1853 // Vector width in bytes
1854 const uint Matcher::vector_width_in_bytes(void) {
1855 return 8;
1856 }
1857
1858 // Vector ideal reg
1859 const uint Matcher::vector_ideal_reg(void) {
1860 return Op_RegD;
1861 }
1862
1863 // USII supports fxtof through the whole range of number, USIII doesn't
1864 const bool Matcher::convL2FSupported(void) {
1865 return VM_Version::has_fast_fxtof();
1866 }
1867
1868 // Is this branch offset short enough that a short branch can be used?
1869 //
1870 // NOTE: If the platform does not provide any short branch variants, then
1871 // this method should return false for offset 0.
1872 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1873 // The passed offset is relative to address of the branch.
1874 // Don't need to adjust the offset.
1875 return UseCBCond && Assembler::is_simm12(offset);
1876 }
1877
1878 const bool Matcher::isSimpleConstant64(jlong value) {
1879 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1880 // Depends on optimizations in MacroAssembler::setx.
1881 int hi = (int)(value >> 32);
1882 int lo = (int)(value & ~0);
1883 return (hi == 0) || (hi == -1) || (lo == 0);
1884 }
1885
1886 // No scaling for the parameter the ClearArray node.
1887 const bool Matcher::init_array_count_is_in_bytes = true;
1888
1889 // Threshold size for cleararray.
1890 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1891
1892 // No additional cost for CMOVL.
1893 const int Matcher::long_cmove_cost() { return 0; }
1894
1895 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1896 const int Matcher::float_cmove_cost() {
1897 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1898 }
1899
1900 // Should the Matcher clone shifts on addressing modes, expecting them to
1901 // be subsumed into complex addressing expressions or compute them into
1902 // registers? True for Intel but false for most RISCs
1903 const bool Matcher::clone_shift_expressions = false;
1904
1905 // Do we need to mask the count passed to shift instructions or does
1906 // the cpu only look at the lower 5/6 bits anyway?
1907 const bool Matcher::need_masked_shift_count = false;
1908
1909 bool Matcher::narrow_oop_use_complex_address() {
1910 NOT_LP64(ShouldNotCallThis());
1911 assert(UseCompressedOops, "only for compressed oops code");
1912 return false;
1913 }
1914
1915 // Is it better to copy float constants, or load them directly from memory?
1916 // Intel can load a float constant from a direct address, requiring no
1917 // extra registers. Most RISCs will have to materialize an address into a
1918 // register first, so they would do better to copy the constant from stack.
1919 const bool Matcher::rematerialize_float_constants = false;
1920
1921 // If CPU can load and store mis-aligned doubles directly then no fixup is
1922 // needed. Else we split the double into 2 integer pieces and move it
1923 // piece-by-piece. Only happens when passing doubles into C code as the
1924 // Java calling convention forces doubles to be aligned.
1925 #ifdef _LP64
1926 const bool Matcher::misaligned_doubles_ok = true;
1927 #else
1928 const bool Matcher::misaligned_doubles_ok = false;
1929 #endif
1930
1931 // No-op on SPARC.
1932 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1933 }
1934
1935 // Advertise here if the CPU requires explicit rounding operations
1936 // to implement the UseStrictFP mode.
1937 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1938
1939 // Are floats conerted to double when stored to stack during deoptimization?
1940 // Sparc does not handle callee-save floats.
1941 bool Matcher::float_in_double() { return false; }
1942
1943 // Do ints take an entire long register or just half?
1944 // Note that we if-def off of _LP64.
1945 // The relevant question is how the int is callee-saved. In _LP64
1946 // the whole long is written but de-opt'ing will have to extract
1947 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1948 #ifdef _LP64
1949 const bool Matcher::int_in_long = true;
1950 #else
1951 const bool Matcher::int_in_long = false;
1952 #endif
1953
1954 // Return whether or not this register is ever used as an argument. This
1955 // function is used on startup to build the trampoline stubs in generateOptoStub.
1956 // Registers not mentioned will be killed by the VM call in the trampoline, and
1957 // arguments in those registers not be available to the callee.
1958 bool Matcher::can_be_java_arg( int reg ) {
1959 // Standard sparc 6 args in registers
1960 if( reg == R_I0_num ||
1961 reg == R_I1_num ||
1962 reg == R_I2_num ||
1963 reg == R_I3_num ||
1964 reg == R_I4_num ||
1965 reg == R_I5_num ) return true;
1966 #ifdef _LP64
1967 // 64-bit builds can pass 64-bit pointers and longs in
1968 // the high I registers
1969 if( reg == R_I0H_num ||
1970 reg == R_I1H_num ||
1971 reg == R_I2H_num ||
1972 reg == R_I3H_num ||
1973 reg == R_I4H_num ||
1974 reg == R_I5H_num ) return true;
1975
1976 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1977 return true;
1978 }
1979
1980 #else
1981 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1982 // Longs cannot be passed in O regs, because O regs become I regs
1983 // after a 'save' and I regs get their high bits chopped off on
1984 // interrupt.
1985 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1986 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1987 #endif
1988 // A few float args in registers
1989 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1990
1991 return false;
1992 }
1993
1994 bool Matcher::is_spillable_arg( int reg ) {
1995 return can_be_java_arg(reg);
1996 }
1997
1998 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1999 // Use hardware SDIVX instruction when it is
2000 // faster than a code which use multiply.
2001 return VM_Version::has_fast_idiv();
2002 }
2003
2004 // Register for DIVI projection of divmodI
2005 RegMask Matcher::divI_proj_mask() {
2006 ShouldNotReachHere();
2007 return RegMask();
2008 }
2009
2010 // Register for MODI projection of divmodI
2011 RegMask Matcher::modI_proj_mask() {
2012 ShouldNotReachHere();
2013 return RegMask();
2014 }
2015
2016 // Register for DIVL projection of divmodL
2017 RegMask Matcher::divL_proj_mask() {
2018 ShouldNotReachHere();
2019 return RegMask();
2020 }
2021
2022 // Register for MODL projection of divmodL
2023 RegMask Matcher::modL_proj_mask() {
2024 ShouldNotReachHere();
2025 return RegMask();
2026 }
2027
2028 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2029 return L7_REGP_mask();
2030 }
2031
2032 %}
2033
2034
2035 // The intptr_t operand types, defined by textual substitution.
2036 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2037 #ifdef _LP64
2038 #define immX immL
2039 #define immX13 immL13
2040 #define immX13m7 immL13m7
2041 #define iRegX iRegL
2042 #define g1RegX g1RegL
2043 #else
2044 #define immX immI
2045 #define immX13 immI13
2046 #define immX13m7 immI13m7
2047 #define iRegX iRegI
2048 #define g1RegX g1RegI
2049 #endif
2050
2051 //----------ENCODING BLOCK-----------------------------------------------------
2052 // This block specifies the encoding classes used by the compiler to output
2053 // byte streams. Encoding classes are parameterized macros used by
2054 // Machine Instruction Nodes in order to generate the bit encoding of the
2055 // instruction. Operands specify their base encoding interface with the
2056 // interface keyword. There are currently supported four interfaces,
2057 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2058 // operand to generate a function which returns its register number when
2059 // queried. CONST_INTER causes an operand to generate a function which
2060 // returns the value of the constant when queried. MEMORY_INTER causes an
2061 // operand to generate four functions which return the Base Register, the
2062 // Index Register, the Scale Value, and the Offset Value of the operand when
2063 // queried. COND_INTER causes an operand to generate six functions which
2064 // return the encoding code (ie - encoding bits for the instruction)
2065 // associated with each basic boolean condition for a conditional instruction.
2066 //
2067 // Instructions specify two basic values for encoding. Again, a function
2068 // is available to check if the constant displacement is an oop. They use the
2069 // ins_encode keyword to specify their encoding classes (which must be
2070 // a sequence of enc_class names, and their parameters, specified in
2071 // the encoding block), and they use the
2072 // opcode keyword to specify, in order, their primary, secondary, and
2073 // tertiary opcode. Only the opcode sections which a particular instruction
2074 // needs for encoding need to be specified.
2075 encode %{
2076 enc_class enc_untested %{
2077 #ifdef ASSERT
2078 MacroAssembler _masm(&cbuf);
2079 __ untested("encoding");
2080 #endif
2081 %}
2082
2083 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2084 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2085 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2086 %}
2087
2088 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2089 emit_form3_mem_reg(cbuf, this, $primary, -1,
2090 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2091 %}
2092
2093 enc_class form3_mem_prefetch_read( memory mem ) %{
2094 emit_form3_mem_reg(cbuf, this, $primary, -1,
2095 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2096 %}
2097
2098 enc_class form3_mem_prefetch_write( memory mem ) %{
2099 emit_form3_mem_reg(cbuf, this, $primary, -1,
2100 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2101 %}
2102
2103 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2104 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2105 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2106 guarantee($mem$$index == R_G0_enc, "double index?");
2107 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2108 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2109 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2110 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2111 %}
2112
2113 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2114 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2115 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2116 guarantee($mem$$index == R_G0_enc, "double index?");
2117 // Load long with 2 instructions
2118 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2119 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2120 %}
2121
2122 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2123 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2124 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2125 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2126 %}
2127
2128 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2129 // Encode a reg-reg copy. If it is useless, then empty encoding.
2130 if( $rs2$$reg != $rd$$reg )
2131 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2132 %}
2133
2134 // Target lo half of long
2135 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2136 // Encode a reg-reg copy. If it is useless, then empty encoding.
2137 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2138 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2139 %}
2140
2141 // Source lo half of long
2142 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2143 // Encode a reg-reg copy. If it is useless, then empty encoding.
2144 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2145 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2146 %}
2147
2148 // Target hi half of long
2149 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2150 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2151 %}
2152
2153 // Source lo half of long, and leave it sign extended.
2154 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2155 // Sign extend low half
2156 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2157 %}
2158
2159 // Source hi half of long, and leave it sign extended.
2160 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2161 // Shift high half to low half
2162 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2163 %}
2164
2165 // Source hi half of long
2166 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2167 // Encode a reg-reg copy. If it is useless, then empty encoding.
2168 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2169 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2170 %}
2171
2172 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2173 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2174 %}
2175
2176 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2177 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2178 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2179 %}
2180
2181 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2182 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2183 // clear if nothing else is happening
2184 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2185 // blt,a,pn done
2186 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2187 // mov dst,-1 in delay slot
2188 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2189 %}
2190
2191 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2192 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2193 %}
2194
2195 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2196 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2197 %}
2198
2199 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2200 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2201 %}
2202
2203 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2204 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2205 %}
2206
2207 enc_class move_return_pc_to_o1() %{
2208 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2209 %}
2210
2211 #ifdef _LP64
2212 /* %%% merge with enc_to_bool */
2213 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2214 MacroAssembler _masm(&cbuf);
2215
2216 Register src_reg = reg_to_register_object($src$$reg);
2217 Register dst_reg = reg_to_register_object($dst$$reg);
2218 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2219 %}
2220 #endif
2221
2222 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2223 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2224 MacroAssembler _masm(&cbuf);
2225
2226 Register p_reg = reg_to_register_object($p$$reg);
2227 Register q_reg = reg_to_register_object($q$$reg);
2228 Register y_reg = reg_to_register_object($y$$reg);
2229 Register tmp_reg = reg_to_register_object($tmp$$reg);
2230
2231 __ subcc( p_reg, q_reg, p_reg );
2232 __ add ( p_reg, y_reg, tmp_reg );
2233 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2234 %}
2235
2236 enc_class form_d2i_helper(regD src, regF dst) %{
2237 // fcmp %fcc0,$src,$src
2238 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2239 // branch %fcc0 not-nan, predict taken
2240 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2241 // fdtoi $src,$dst
2242 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2243 // fitos $dst,$dst (if nan)
2244 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2245 // clear $dst (if nan)
2246 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2247 // carry on here...
2248 %}
2249
2250 enc_class form_d2l_helper(regD src, regD dst) %{
2251 // fcmp %fcc0,$src,$src check for NAN
2252 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2253 // branch %fcc0 not-nan, predict taken
2254 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2255 // fdtox $src,$dst convert in delay slot
2256 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2257 // fxtod $dst,$dst (if nan)
2258 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2259 // clear $dst (if nan)
2260 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2261 // carry on here...
2262 %}
2263
2264 enc_class form_f2i_helper(regF src, regF dst) %{
2265 // fcmps %fcc0,$src,$src
2266 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2267 // branch %fcc0 not-nan, predict taken
2268 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2269 // fstoi $src,$dst
2270 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2271 // fitos $dst,$dst (if nan)
2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2273 // clear $dst (if nan)
2274 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2275 // carry on here...
2276 %}
2277
2278 enc_class form_f2l_helper(regF src, regD dst) %{
2279 // fcmps %fcc0,$src,$src
2280 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2281 // branch %fcc0 not-nan, predict taken
2282 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2283 // fstox $src,$dst
2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2285 // fxtod $dst,$dst (if nan)
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2287 // clear $dst (if nan)
2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2289 // carry on here...
2290 %}
2291
2292 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2293 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2294 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2295 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2296
2297 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2298
2299 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2300 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2301
2302 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2303 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2304 %}
2305
2306 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2307 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2308 %}
2309
2310 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2311 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2312 %}
2313
2314 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2315 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2316 %}
2317
2318 enc_class form3_convI2F(regF rs2, regF rd) %{
2319 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2320 %}
2321
2322 // Encloding class for traceable jumps
2323 enc_class form_jmpl(g3RegP dest) %{
2324 emit_jmpl(cbuf, $dest$$reg);
2325 %}
2326
2327 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2328 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2329 %}
2330
2331 enc_class form2_nop() %{
2332 emit_nop(cbuf);
2333 %}
2334
2335 enc_class form2_illtrap() %{
2336 emit_illtrap(cbuf);
2337 %}
2338
2339
2340 // Compare longs and convert into -1, 0, 1.
2341 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2342 // CMP $src1,$src2
2343 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2344 // blt,a,pn done
2345 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2346 // mov dst,-1 in delay slot
2347 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2348 // bgt,a,pn done
2349 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2350 // mov dst,1 in delay slot
2351 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2352 // CLR $dst
2353 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2354 %}
2355
2356 enc_class enc_PartialSubtypeCheck() %{
2357 MacroAssembler _masm(&cbuf);
2358 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2359 __ delayed()->nop();
2360 %}
2361
2362 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2363 MacroAssembler _masm(&cbuf);
2364 Label* L = $labl$$label;
2365 Assembler::Predict predict_taken =
2366 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2367
2368 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2369 __ delayed()->nop();
2370 %}
2371
2372 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2373 MacroAssembler _masm(&cbuf);
2374 Label* L = $labl$$label;
2375 Assembler::Predict predict_taken =
2376 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2377
2378 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2379 __ delayed()->nop();
2380 %}
2381
2382 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2383 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) |
2385 (Assembler::movcc_op3 << 19) |
2386 (1 << 18) | // cc2 bit for 'icc'
2387 ($cmp$$cmpcode << 14) |
2388 (0 << 13) | // select register move
2389 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2390 ($src$$reg << 0);
2391 cbuf.insts()->emit_int32(op);
2392 %}
2393
2394 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2395 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2396 int op = (Assembler::arith_op << 30) |
2397 ($dst$$reg << 25) |
2398 (Assembler::movcc_op3 << 19) |
2399 (1 << 18) | // cc2 bit for 'icc'
2400 ($cmp$$cmpcode << 14) |
2401 (1 << 13) | // select immediate move
2402 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2403 (simm11 << 0);
2404 cbuf.insts()->emit_int32(op);
2405 %}
2406
2407 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2408 int op = (Assembler::arith_op << 30) |
2409 ($dst$$reg << 25) |
2410 (Assembler::movcc_op3 << 19) |
2411 (0 << 18) | // cc2 bit for 'fccX'
2412 ($cmp$$cmpcode << 14) |
2413 (0 << 13) | // select register move
2414 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2415 ($src$$reg << 0);
2416 cbuf.insts()->emit_int32(op);
2417 %}
2418
2419 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2420 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2421 int op = (Assembler::arith_op << 30) |
2422 ($dst$$reg << 25) |
2423 (Assembler::movcc_op3 << 19) |
2424 (0 << 18) | // cc2 bit for 'fccX'
2425 ($cmp$$cmpcode << 14) |
2426 (1 << 13) | // select immediate move
2427 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2428 (simm11 << 0);
2429 cbuf.insts()->emit_int32(op);
2430 %}
2431
2432 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2433 int op = (Assembler::arith_op << 30) |
2434 ($dst$$reg << 25) |
2435 (Assembler::fpop2_op3 << 19) |
2436 (0 << 18) |
2437 ($cmp$$cmpcode << 14) |
2438 (1 << 13) | // select register move
2439 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2440 ($primary << 5) | // select single, double or quad
2441 ($src$$reg << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2444
2445 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2446 int op = (Assembler::arith_op << 30) |
2447 ($dst$$reg << 25) |
2448 (Assembler::fpop2_op3 << 19) |
2449 (0 << 18) |
2450 ($cmp$$cmpcode << 14) |
2451 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2452 ($primary << 5) | // select single, double or quad
2453 ($src$$reg << 0);
2454 cbuf.insts()->emit_int32(op);
2455 %}
2456
2457 // Used by the MIN/MAX encodings. Same as a CMOV, but
2458 // the condition comes from opcode-field instead of an argument.
2459 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2460 int op = (Assembler::arith_op << 30) |
2461 ($dst$$reg << 25) |
2462 (Assembler::movcc_op3 << 19) |
2463 (1 << 18) | // cc2 bit for 'icc'
2464 ($primary << 14) |
2465 (0 << 13) | // select register move
2466 (0 << 11) | // cc1, cc0 bits for 'icc'
2467 ($src$$reg << 0);
2468 cbuf.insts()->emit_int32(op);
2469 %}
2470
2471 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2472 int op = (Assembler::arith_op << 30) |
2473 ($dst$$reg << 25) |
2474 (Assembler::movcc_op3 << 19) |
2475 (6 << 16) | // cc2 bit for 'xcc'
2476 ($primary << 14) |
2477 (0 << 13) | // select register move
2478 (0 << 11) | // cc1, cc0 bits for 'icc'
2479 ($src$$reg << 0);
2480 cbuf.insts()->emit_int32(op);
2481 %}
2482
2483 enc_class Set13( immI13 src, iRegI rd ) %{
2484 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2485 %}
2486
2487 enc_class SetHi22( immI src, iRegI rd ) %{
2488 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2489 %}
2490
2491 enc_class Set32( immI src, iRegI rd ) %{
2492 MacroAssembler _masm(&cbuf);
2493 __ set($src$$constant, reg_to_register_object($rd$$reg));
2494 %}
2495
2496 enc_class call_epilog %{
2497 if( VerifyStackAtCalls ) {
2498 MacroAssembler _masm(&cbuf);
2499 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2500 Register temp_reg = G3;
2501 __ add(SP, framesize, temp_reg);
2502 __ cmp(temp_reg, FP);
2503 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2504 }
2505 %}
2506
2507 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2508 // to G1 so the register allocator will not have to deal with the misaligned register
2509 // pair.
2510 enc_class adjust_long_from_native_call %{
2511 #ifndef _LP64
2512 if (returns_long()) {
2513 // sllx O0,32,O0
2514 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2515 // srl O1,0,O1
2516 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2517 // or O0,O1,G1
2518 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2519 }
2520 #endif
2521 %}
2522
2523 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2524 // CALL directly to the runtime
2525 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2526 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2527 /*preserve_g2=*/true);
2528 %}
2529
2530 enc_class preserve_SP %{
2531 MacroAssembler _masm(&cbuf);
2532 __ mov(SP, L7_mh_SP_save);
2533 %}
2534
2535 enc_class restore_SP %{
2536 MacroAssembler _masm(&cbuf);
2537 __ mov(L7_mh_SP_save, SP);
2538 %}
2539
2540 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2541 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2542 // who we intended to call.
2543 if ( !_method ) {
2544 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2545 } else if (_optimized_virtual) {
2546 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2547 } else {
2548 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2549 }
2550 if( _method ) { // Emit stub for static call
2551 emit_java_to_interp(cbuf);
2552 }
2553 %}
2554
2555 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2556 MacroAssembler _masm(&cbuf);
2557 __ set_inst_mark();
2558 int vtable_index = this->_vtable_index;
2559 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2560 if (vtable_index < 0) {
2561 // must be invalid_vtable_index, not nonvirtual_vtable_index
2562 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2563 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2564 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2565 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2566 // !!!!!
2567 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2568 // emit_call_dynamic_prologue( cbuf );
2569 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2570
2571 address virtual_call_oop_addr = __ inst_mark();
2572 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2573 // who we intended to call.
2574 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2575 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2576 } else {
2577 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2578 // Just go thru the vtable
2579 // get receiver klass (receiver already checked for non-null)
2580 // If we end up going thru a c2i adapter interpreter expects method in G5
2581 int off = __ offset();
2582 __ load_klass(O0, G3_scratch);
2583 int klass_load_size;
2584 if (UseCompressedOops) {
2585 assert(Universe::heap() != NULL, "java heap should be initialized");
2586 if (Universe::narrow_oop_base() == NULL)
2587 klass_load_size = 2*BytesPerInstWord;
2588 else
2589 klass_load_size = 3*BytesPerInstWord;
2590 } else {
2591 klass_load_size = 1*BytesPerInstWord;
2592 }
2593 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2594 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2595 if (Assembler::is_simm13(v_off)) {
2596 __ ld_ptr(G3, v_off, G5_method);
2597 } else {
2598 // Generate 2 instructions
2599 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2600 __ or3(G5_method, v_off & 0x3ff, G5_method);
2601 // ld_ptr, set_hi, set
2602 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2603 "Unexpected instruction size(s)");
2604 __ ld_ptr(G3, G5_method, G5_method);
2605 }
2606 // NOTE: for vtable dispatches, the vtable entry will never be null.
2607 // However it may very well end up in handle_wrong_method if the
2608 // method is abstract for the particular class.
2609 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2610 // jump to target (either compiled code or c2iadapter)
2611 __ jmpl(G3_scratch, G0, O7);
2612 __ delayed()->nop();
2613 }
2614 %}
2615
2616 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2617 MacroAssembler _masm(&cbuf);
2618
2619 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2620 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2621 // we might be calling a C2I adapter which needs it.
2622
2623 assert(temp_reg != G5_ic_reg, "conflicting registers");
2624 // Load nmethod
2625 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2626
2627 // CALL to compiled java, indirect the contents of G3
2628 __ set_inst_mark();
2629 __ callr(temp_reg, G0);
2630 __ delayed()->nop();
2631 %}
2632
2633 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2634 MacroAssembler _masm(&cbuf);
2635 Register Rdividend = reg_to_register_object($src1$$reg);
2636 Register Rdivisor = reg_to_register_object($src2$$reg);
2637 Register Rresult = reg_to_register_object($dst$$reg);
2638
2639 __ sra(Rdivisor, 0, Rdivisor);
2640 __ sra(Rdividend, 0, Rdividend);
2641 __ sdivx(Rdividend, Rdivisor, Rresult);
2642 %}
2643
2644 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2645 MacroAssembler _masm(&cbuf);
2646
2647 Register Rdividend = reg_to_register_object($src1$$reg);
2648 int divisor = $imm$$constant;
2649 Register Rresult = reg_to_register_object($dst$$reg);
2650
2651 __ sra(Rdividend, 0, Rdividend);
2652 __ sdivx(Rdividend, divisor, Rresult);
2653 %}
2654
2655 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2656 MacroAssembler _masm(&cbuf);
2657 Register Rsrc1 = reg_to_register_object($src1$$reg);
2658 Register Rsrc2 = reg_to_register_object($src2$$reg);
2659 Register Rdst = reg_to_register_object($dst$$reg);
2660
2661 __ sra( Rsrc1, 0, Rsrc1 );
2662 __ sra( Rsrc2, 0, Rsrc2 );
2663 __ mulx( Rsrc1, Rsrc2, Rdst );
2664 __ srlx( Rdst, 32, Rdst );
2665 %}
2666
2667 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2668 MacroAssembler _masm(&cbuf);
2669 Register Rdividend = reg_to_register_object($src1$$reg);
2670 Register Rdivisor = reg_to_register_object($src2$$reg);
2671 Register Rresult = reg_to_register_object($dst$$reg);
2672 Register Rscratch = reg_to_register_object($scratch$$reg);
2673
2674 assert(Rdividend != Rscratch, "");
2675 assert(Rdivisor != Rscratch, "");
2676
2677 __ sra(Rdividend, 0, Rdividend);
2678 __ sra(Rdivisor, 0, Rdivisor);
2679 __ sdivx(Rdividend, Rdivisor, Rscratch);
2680 __ mulx(Rscratch, Rdivisor, Rscratch);
2681 __ sub(Rdividend, Rscratch, Rresult);
2682 %}
2683
2684 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2685 MacroAssembler _masm(&cbuf);
2686
2687 Register Rdividend = reg_to_register_object($src1$$reg);
2688 int divisor = $imm$$constant;
2689 Register Rresult = reg_to_register_object($dst$$reg);
2690 Register Rscratch = reg_to_register_object($scratch$$reg);
2691
2692 assert(Rdividend != Rscratch, "");
2693
2694 __ sra(Rdividend, 0, Rdividend);
2695 __ sdivx(Rdividend, divisor, Rscratch);
2696 __ mulx(Rscratch, divisor, Rscratch);
2697 __ sub(Rdividend, Rscratch, Rresult);
2698 %}
2699
2700 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2701 MacroAssembler _masm(&cbuf);
2702
2703 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2704 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2705
2706 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2707 %}
2708
2709 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2710 MacroAssembler _masm(&cbuf);
2711
2712 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2713 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2714
2715 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2716 %}
2717
2718 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2719 MacroAssembler _masm(&cbuf);
2720
2721 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2722 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2723
2724 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2725 %}
2726
2727 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2728 MacroAssembler _masm(&cbuf);
2729
2730 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2731 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2732
2733 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2734 %}
2735
2736 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2737 MacroAssembler _masm(&cbuf);
2738
2739 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2740 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2741
2742 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2743 %}
2744
2745 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2746 MacroAssembler _masm(&cbuf);
2747
2748 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2749 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2750
2751 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2752 %}
2753
2754 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2755 MacroAssembler _masm(&cbuf);
2756
2757 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2758 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2759
2760 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2761 %}
2762
2763 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2764 MacroAssembler _masm(&cbuf);
2765
2766 Register Roop = reg_to_register_object($oop$$reg);
2767 Register Rbox = reg_to_register_object($box$$reg);
2768 Register Rscratch = reg_to_register_object($scratch$$reg);
2769 Register Rmark = reg_to_register_object($scratch2$$reg);
2770
2771 assert(Roop != Rscratch, "");
2772 assert(Roop != Rmark, "");
2773 assert(Rbox != Rscratch, "");
2774 assert(Rbox != Rmark, "");
2775
2776 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2777 %}
2778
2779 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2780 MacroAssembler _masm(&cbuf);
2781
2782 Register Roop = reg_to_register_object($oop$$reg);
2783 Register Rbox = reg_to_register_object($box$$reg);
2784 Register Rscratch = reg_to_register_object($scratch$$reg);
2785 Register Rmark = reg_to_register_object($scratch2$$reg);
2786
2787 assert(Roop != Rscratch, "");
2788 assert(Roop != Rmark, "");
2789 assert(Rbox != Rscratch, "");
2790 assert(Rbox != Rmark, "");
2791
2792 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2793 %}
2794
2795 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2796 MacroAssembler _masm(&cbuf);
2797 Register Rmem = reg_to_register_object($mem$$reg);
2798 Register Rold = reg_to_register_object($old$$reg);
2799 Register Rnew = reg_to_register_object($new$$reg);
2800
2801 // casx_under_lock picks 1 of 3 encodings:
2802 // For 32-bit pointers you get a 32-bit CAS
2803 // For 64-bit pointers you get a 64-bit CASX
2804 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2805 __ cmp( Rold, Rnew );
2806 %}
2807
2808 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2809 Register Rmem = reg_to_register_object($mem$$reg);
2810 Register Rold = reg_to_register_object($old$$reg);
2811 Register Rnew = reg_to_register_object($new$$reg);
2812
2813 MacroAssembler _masm(&cbuf);
2814 __ mov(Rnew, O7);
2815 __ casx(Rmem, Rold, O7);
2816 __ cmp( Rold, O7 );
2817 %}
2818
2819 // raw int cas, used for compareAndSwap
2820 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2821 Register Rmem = reg_to_register_object($mem$$reg);
2822 Register Rold = reg_to_register_object($old$$reg);
2823 Register Rnew = reg_to_register_object($new$$reg);
2824
2825 MacroAssembler _masm(&cbuf);
2826 __ mov(Rnew, O7);
2827 __ cas(Rmem, Rold, O7);
2828 __ cmp( Rold, O7 );
2829 %}
2830
2831 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2832 Register Rres = reg_to_register_object($res$$reg);
2833
2834 MacroAssembler _masm(&cbuf);
2835 __ mov(1, Rres);
2836 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2837 %}
2838
2839 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2840 Register Rres = reg_to_register_object($res$$reg);
2841
2842 MacroAssembler _masm(&cbuf);
2843 __ mov(1, Rres);
2844 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2845 %}
2846
2847 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2848 MacroAssembler _masm(&cbuf);
2849 Register Rdst = reg_to_register_object($dst$$reg);
2850 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2851 : reg_to_DoubleFloatRegister_object($src1$$reg);
2852 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2853 : reg_to_DoubleFloatRegister_object($src2$$reg);
2854
2855 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2856 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2857 %}
2858
2859
2860 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2861 Label Ldone, Lloop;
2862 MacroAssembler _masm(&cbuf);
2863
2864 Register str1_reg = reg_to_register_object($str1$$reg);
2865 Register str2_reg = reg_to_register_object($str2$$reg);
2866 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2867 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2868 Register result_reg = reg_to_register_object($result$$reg);
2869
2870 assert(result_reg != str1_reg &&
2871 result_reg != str2_reg &&
2872 result_reg != cnt1_reg &&
2873 result_reg != cnt2_reg ,
2874 "need different registers");
2875
2876 // Compute the minimum of the string lengths(str1_reg) and the
2877 // difference of the string lengths (stack)
2878
2879 // See if the lengths are different, and calculate min in str1_reg.
2880 // Stash diff in O7 in case we need it for a tie-breaker.
2881 Label Lskip;
2882 __ subcc(cnt1_reg, cnt2_reg, O7);
2883 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2884 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2885 // cnt2 is shorter, so use its count:
2886 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2887 __ bind(Lskip);
2888
2889 // reallocate cnt1_reg, cnt2_reg, result_reg
2890 // Note: limit_reg holds the string length pre-scaled by 2
2891 Register limit_reg = cnt1_reg;
2892 Register chr2_reg = cnt2_reg;
2893 Register chr1_reg = result_reg;
2894 // str{12} are the base pointers
2895
2896 // Is the minimum length zero?
2897 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2898 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2899 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2900
2901 // Load first characters
2902 __ lduh(str1_reg, 0, chr1_reg);
2903 __ lduh(str2_reg, 0, chr2_reg);
2904
2905 // Compare first characters
2906 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2907 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2908 assert(chr1_reg == result_reg, "result must be pre-placed");
2909 __ delayed()->nop();
2910
2911 {
2912 // Check after comparing first character to see if strings are equivalent
2913 Label LSkip2;
2914 // Check if the strings start at same location
2915 __ cmp(str1_reg, str2_reg);
2916 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2917 __ delayed()->nop();
2918
2919 // Check if the length difference is zero (in O7)
2920 __ cmp(G0, O7);
2921 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2922 __ delayed()->mov(G0, result_reg); // result is zero
2923
2924 // Strings might not be equal
2925 __ bind(LSkip2);
2926 }
2927
2928 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2929 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2930 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2931
2932 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2933 __ add(str1_reg, limit_reg, str1_reg);
2934 __ add(str2_reg, limit_reg, str2_reg);
2935 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2936
2937 // Compare the rest of the characters
2938 __ lduh(str1_reg, limit_reg, chr1_reg);
2939 __ bind(Lloop);
2940 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2941 __ lduh(str2_reg, limit_reg, chr2_reg);
2942 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2943 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2944 assert(chr1_reg == result_reg, "result must be pre-placed");
2945 __ delayed()->inccc(limit_reg, sizeof(jchar));
2946 // annul LDUH if branch is not taken to prevent access past end of string
2947 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2948 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2949
2950 // If strings are equal up to min length, return the length difference.
2951 __ mov(O7, result_reg);
2952
2953 // Otherwise, return the difference between the first mismatched chars.
2954 __ bind(Ldone);
2955 %}
2956
2957 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2958 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2959 MacroAssembler _masm(&cbuf);
2960
2961 Register str1_reg = reg_to_register_object($str1$$reg);
2962 Register str2_reg = reg_to_register_object($str2$$reg);
2963 Register cnt_reg = reg_to_register_object($cnt$$reg);
2964 Register tmp1_reg = O7;
2965 Register result_reg = reg_to_register_object($result$$reg);
2966
2967 assert(result_reg != str1_reg &&
2968 result_reg != str2_reg &&
2969 result_reg != cnt_reg &&
2970 result_reg != tmp1_reg ,
2971 "need different registers");
2972
2973 __ cmp(str1_reg, str2_reg); //same char[] ?
2974 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2975 __ delayed()->add(G0, 1, result_reg);
2976
2977 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2978 __ delayed()->add(G0, 1, result_reg); // count == 0
2979
2980 //rename registers
2981 Register limit_reg = cnt_reg;
2982 Register chr1_reg = result_reg;
2983 Register chr2_reg = tmp1_reg;
2984
2985 //check for alignment and position the pointers to the ends
2986 __ or3(str1_reg, str2_reg, chr1_reg);
2987 __ andcc(chr1_reg, 0x3, chr1_reg);
2988 // notZero means at least one not 4-byte aligned.
2989 // We could optimize the case when both arrays are not aligned
2990 // but it is not frequent case and it requires additional checks.
2991 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2992 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2993
2994 // Compare char[] arrays aligned to 4 bytes.
2995 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2996 chr1_reg, chr2_reg, Ldone);
2997 __ ba(Ldone);
2998 __ delayed()->add(G0, 1, result_reg);
2999
3000 // char by char compare
3001 __ bind(Lchar);
3002 __ add(str1_reg, limit_reg, str1_reg);
3003 __ add(str2_reg, limit_reg, str2_reg);
3004 __ neg(limit_reg); //negate count
3005
3006 __ lduh(str1_reg, limit_reg, chr1_reg);
3007 // Lchar_loop
3008 __ bind(Lchar_loop);
3009 __ lduh(str2_reg, limit_reg, chr2_reg);
3010 __ cmp(chr1_reg, chr2_reg);
3011 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3012 __ delayed()->mov(G0, result_reg); //not equal
3013 __ inccc(limit_reg, sizeof(jchar));
3014 // annul LDUH if branch is not taken to prevent access past end of string
3015 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3016 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3017
3018 __ add(G0, 1, result_reg); //equal
3019
3020 __ bind(Ldone);
3021 %}
3022
3023 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3024 Label Lvector, Ldone, Lloop;
3025 MacroAssembler _masm(&cbuf);
3026
3027 Register ary1_reg = reg_to_register_object($ary1$$reg);
3028 Register ary2_reg = reg_to_register_object($ary2$$reg);
3029 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3030 Register tmp2_reg = O7;
3031 Register result_reg = reg_to_register_object($result$$reg);
3032
3033 int length_offset = arrayOopDesc::length_offset_in_bytes();
3034 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3035
3036 // return true if the same array
3037 __ cmp(ary1_reg, ary2_reg);
3038 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3039 __ delayed()->add(G0, 1, result_reg); // equal
3040
3041 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3042 __ delayed()->mov(G0, result_reg); // not equal
3043
3044 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3045 __ delayed()->mov(G0, result_reg); // not equal
3046
3047 //load the lengths of arrays
3048 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3049 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3050
3051 // return false if the two arrays are not equal length
3052 __ cmp(tmp1_reg, tmp2_reg);
3053 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3054 __ delayed()->mov(G0, result_reg); // not equal
3055
3056 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3057 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3058
3059 // load array addresses
3060 __ add(ary1_reg, base_offset, ary1_reg);
3061 __ add(ary2_reg, base_offset, ary2_reg);
3062
3063 // renaming registers
3064 Register chr1_reg = result_reg; // for characters in ary1
3065 Register chr2_reg = tmp2_reg; // for characters in ary2
3066 Register limit_reg = tmp1_reg; // length
3067
3068 // set byte count
3069 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3070
3071 // Compare char[] arrays aligned to 4 bytes.
3072 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3073 chr1_reg, chr2_reg, Ldone);
3074 __ add(G0, 1, result_reg); // equals
3075
3076 __ bind(Ldone);
3077 %}
3078
3079 enc_class enc_rethrow() %{
3080 cbuf.set_insts_mark();
3081 Register temp_reg = G3;
3082 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3083 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3084 MacroAssembler _masm(&cbuf);
3085 #ifdef ASSERT
3086 __ save_frame(0);
3087 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3088 __ sethi(last_rethrow_addrlit, L1);
3089 Address addr(L1, last_rethrow_addrlit.low10());
3090 __ get_pc(L2);
3091 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3092 __ st_ptr(L2, addr);
3093 __ restore();
3094 #endif
3095 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3096 __ delayed()->nop();
3097 %}
3098
3099 enc_class emit_mem_nop() %{
3100 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3101 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3102 %}
3103
3104 enc_class emit_fadd_nop() %{
3105 // Generates the instruction FMOVS f31,f31
3106 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3107 %}
3108
3109 enc_class emit_br_nop() %{
3110 // Generates the instruction BPN,PN .
3111 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3112 %}
3113
3114 enc_class enc_membar_acquire %{
3115 MacroAssembler _masm(&cbuf);
3116 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3117 %}
3118
3119 enc_class enc_membar_release %{
3120 MacroAssembler _masm(&cbuf);
3121 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3122 %}
3123
3124 enc_class enc_membar_volatile %{
3125 MacroAssembler _masm(&cbuf);
3126 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3127 %}
3128
3129 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3130 MacroAssembler _masm(&cbuf);
3131 Register src_reg = reg_to_register_object($src$$reg);
3132 Register dst_reg = reg_to_register_object($dst$$reg);
3133 __ sllx(src_reg, 56, dst_reg);
3134 __ srlx(dst_reg, 8, O7);
3135 __ or3 (dst_reg, O7, dst_reg);
3136 __ srlx(dst_reg, 16, O7);
3137 __ or3 (dst_reg, O7, dst_reg);
3138 __ srlx(dst_reg, 32, O7);
3139 __ or3 (dst_reg, O7, dst_reg);
3140 %}
3141
3142 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3143 MacroAssembler _masm(&cbuf);
3144 Register src_reg = reg_to_register_object($src$$reg);
3145 Register dst_reg = reg_to_register_object($dst$$reg);
3146 __ sll(src_reg, 24, dst_reg);
3147 __ srl(dst_reg, 8, O7);
3148 __ or3(dst_reg, O7, dst_reg);
3149 __ srl(dst_reg, 16, O7);
3150 __ or3(dst_reg, O7, dst_reg);
3151 %}
3152
3153 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3154 MacroAssembler _masm(&cbuf);
3155 Register src_reg = reg_to_register_object($src$$reg);
3156 Register dst_reg = reg_to_register_object($dst$$reg);
3157 __ sllx(src_reg, 48, dst_reg);
3158 __ srlx(dst_reg, 16, O7);
3159 __ or3 (dst_reg, O7, dst_reg);
3160 __ srlx(dst_reg, 32, O7);
3161 __ or3 (dst_reg, O7, dst_reg);
3162 %}
3163
3164 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3165 MacroAssembler _masm(&cbuf);
3166 Register src_reg = reg_to_register_object($src$$reg);
3167 Register dst_reg = reg_to_register_object($dst$$reg);
3168 __ sllx(src_reg, 32, dst_reg);
3169 __ srlx(dst_reg, 32, O7);
3170 __ or3 (dst_reg, O7, dst_reg);
3171 %}
3172
3173 %}
3174
3175 //----------FRAME--------------------------------------------------------------
3176 // Definition of frame structure and management information.
3177 //
3178 // S T A C K L A Y O U T Allocators stack-slot number
3179 // | (to get allocators register number
3180 // G Owned by | | v add VMRegImpl::stack0)
3181 // r CALLER | |
3182 // o | +--------+ pad to even-align allocators stack-slot
3183 // w V | pad0 | numbers; owned by CALLER
3184 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3185 // h ^ | in | 5
3186 // | | args | 4 Holes in incoming args owned by SELF
3187 // | | | | 3
3188 // | | +--------+
3189 // V | | old out| Empty on Intel, window on Sparc
3190 // | old |preserve| Must be even aligned.
3191 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3192 // | | in | 3 area for Intel ret address
3193 // Owned by |preserve| Empty on Sparc.
3194 // SELF +--------+
3195 // | | pad2 | 2 pad to align old SP
3196 // | +--------+ 1
3197 // | | locks | 0
3198 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3199 // | | pad1 | 11 pad to align new SP
3200 // | +--------+
3201 // | | | 10
3202 // | | spills | 9 spills
3203 // V | | 8 (pad0 slot for callee)
3204 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3205 // ^ | out | 7
3206 // | | args | 6 Holes in outgoing args owned by CALLEE
3207 // Owned by +--------+
3208 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3209 // | new |preserve| Must be even-aligned.
3210 // | SP-+--------+----> Matcher::_new_SP, even aligned
3211 // | | |
3212 //
3213 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3214 // known from SELF's arguments and the Java calling convention.
3215 // Region 6-7 is determined per call site.
3216 // Note 2: If the calling convention leaves holes in the incoming argument
3217 // area, those holes are owned by SELF. Holes in the outgoing area
3218 // are owned by the CALLEE. Holes should not be nessecary in the
3219 // incoming area, as the Java calling convention is completely under
3220 // the control of the AD file. Doubles can be sorted and packed to
3221 // avoid holes. Holes in the outgoing arguments may be nessecary for
3222 // varargs C calling conventions.
3223 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3224 // even aligned with pad0 as needed.
3225 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3226 // region 6-11 is even aligned; it may be padded out more so that
3227 // the region from SP to FP meets the minimum stack alignment.
3228
3229 frame %{
3230 // What direction does stack grow in (assumed to be same for native & Java)
3231 stack_direction(TOWARDS_LOW);
3232
3233 // These two registers define part of the calling convention
3234 // between compiled code and the interpreter.
3235 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3236 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3237
3238 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3239 cisc_spilling_operand_name(indOffset);
3240
3241 // Number of stack slots consumed by a Monitor enter
3242 #ifdef _LP64
3243 sync_stack_slots(2);
3244 #else
3245 sync_stack_slots(1);
3246 #endif
3247
3248 // Compiled code's Frame Pointer
3249 frame_pointer(R_SP);
3250
3251 // Stack alignment requirement
3252 stack_alignment(StackAlignmentInBytes);
3253 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3254 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3255
3256 // Number of stack slots between incoming argument block and the start of
3257 // a new frame. The PROLOG must add this many slots to the stack. The
3258 // EPILOG must remove this many slots.
3259 in_preserve_stack_slots(0);
3260
3261 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3262 // for calls to C. Supports the var-args backing area for register parms.
3263 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3264 #ifdef _LP64
3265 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3266 varargs_C_out_slots_killed(12);
3267 #else
3268 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3269 varargs_C_out_slots_killed( 7);
3270 #endif
3271
3272 // The after-PROLOG location of the return address. Location of
3273 // return address specifies a type (REG or STACK) and a number
3274 // representing the register number (i.e. - use a register name) or
3275 // stack slot.
3276 return_addr(REG R_I7); // Ret Addr is in register I7
3277
3278 // Body of function which returns an OptoRegs array locating
3279 // arguments either in registers or in stack slots for calling
3280 // java
3281 calling_convention %{
3282 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3283
3284 %}
3285
3286 // Body of function which returns an OptoRegs array locating
3287 // arguments either in registers or in stack slots for callin
3288 // C.
3289 c_calling_convention %{
3290 // This is obviously always outgoing
3291 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3292 %}
3293
3294 // Location of native (C/C++) and interpreter return values. This is specified to
3295 // be the same as Java. In the 32-bit VM, long values are actually returned from
3296 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3297 // to and from the register pairs is done by the appropriate call and epilog
3298 // opcodes. This simplifies the register allocator.
3299 c_return_value %{
3300 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3301 #ifdef _LP64
3302 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3303 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3304 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3305 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3306 #else // !_LP64
3307 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3308 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3309 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3310 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3311 #endif
3312 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3313 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3314 %}
3315
3316 // Location of compiled Java return values. Same as C
3317 return_value %{
3318 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3319 #ifdef _LP64
3320 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3321 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3322 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3323 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3324 #else // !_LP64
3325 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3326 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3327 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3328 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3329 #endif
3330 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3331 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3332 %}
3333
3334 %}
3335
3336
3337 //----------ATTRIBUTES---------------------------------------------------------
3338 //----------Operand Attributes-------------------------------------------------
3339 op_attrib op_cost(1); // Required cost attribute
3340
3341 //----------Instruction Attributes---------------------------------------------
3342 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3343 ins_attrib ins_size(32); // Required size attribute (in bits)
3344 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3345 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3346 // non-matching short branch variant of some
3347 // long branch?
3348
3349 //----------OPERANDS-----------------------------------------------------------
3350 // Operand definitions must precede instruction definitions for correct parsing
3351 // in the ADLC because operands constitute user defined types which are used in
3352 // instruction definitions.
3353
3354 //----------Simple Operands----------------------------------------------------
3355 // Immediate Operands
3356 // Integer Immediate: 32-bit
3357 operand immI() %{
3358 match(ConI);
3359
3360 op_cost(0);
3361 // formats are generated automatically for constants and base registers
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3365
3366 // Integer Immediate: 8-bit
3367 operand immI8() %{
3368 predicate(Assembler::is_simm8(n->get_int()));
3369 match(ConI);
3370 op_cost(0);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // Integer Immediate: 13-bit
3376 operand immI13() %{
3377 predicate(Assembler::is_simm13(n->get_int()));
3378 match(ConI);
3379 op_cost(0);
3380
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3384
3385 // Integer Immediate: 13-bit minus 7
3386 operand immI13m7() %{
3387 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3388 match(ConI);
3389 op_cost(0);
3390
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3394
3395 // Integer Immediate: 16-bit
3396 operand immI16() %{
3397 predicate(Assembler::is_simm16(n->get_int()));
3398 match(ConI);
3399 op_cost(0);
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Unsigned (positive) Integer Immediate: 13-bit
3405 operand immU13() %{
3406 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3407 match(ConI);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Integer Immediate: 6-bit
3415 operand immU6() %{
3416 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3417 match(ConI);
3418 op_cost(0);
3419 format %{ %}
3420 interface(CONST_INTER);
3421 %}
3422
3423 // Integer Immediate: 11-bit
3424 operand immI11() %{
3425 predicate(Assembler::is_simm11(n->get_int()));
3426 match(ConI);
3427 op_cost(0);
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
3432 // Integer Immediate: 5-bit
3433 operand immI5() %{
3434 predicate(Assembler::is_simm5(n->get_int()));
3435 match(ConI);
3436 op_cost(0);
3437 format %{ %}
3438 interface(CONST_INTER);
3439 %}
3440
3441 // Integer Immediate: 0-bit
3442 operand immI0() %{
3443 predicate(n->get_int() == 0);
3444 match(ConI);
3445 op_cost(0);
3446
3447 format %{ %}
3448 interface(CONST_INTER);
3449 %}
3450
3451 // Integer Immediate: the value 10
3452 operand immI10() %{
3453 predicate(n->get_int() == 10);
3454 match(ConI);
3455 op_cost(0);
3456
3457 format %{ %}
3458 interface(CONST_INTER);
3459 %}
3460
3461 // Integer Immediate: the values 0-31
3462 operand immU5() %{
3463 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3464 match(ConI);
3465 op_cost(0);
3466
3467 format %{ %}
3468 interface(CONST_INTER);
3469 %}
3470
3471 // Integer Immediate: the values 1-31
3472 operand immI_1_31() %{
3473 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3474 match(ConI);
3475 op_cost(0);
3476
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 // Integer Immediate: the values 32-63
3482 operand immI_32_63() %{
3483 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3484 match(ConI);
3485 op_cost(0);
3486
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3490
3491 // Immediates for special shifts (sign extend)
3492
3493 // Integer Immediate: the value 16
3494 operand immI_16() %{
3495 predicate(n->get_int() == 16);
3496 match(ConI);
3497 op_cost(0);
3498
3499 format %{ %}
3500 interface(CONST_INTER);
3501 %}
3502
3503 // Integer Immediate: the value 24
3504 operand immI_24() %{
3505 predicate(n->get_int() == 24);
3506 match(ConI);
3507 op_cost(0);
3508
3509 format %{ %}
3510 interface(CONST_INTER);
3511 %}
3512
3513 // Integer Immediate: the value 255
3514 operand immI_255() %{
3515 predicate( n->get_int() == 255 );
3516 match(ConI);
3517 op_cost(0);
3518
3519 format %{ %}
3520 interface(CONST_INTER);
3521 %}
3522
3523 // Integer Immediate: the value 65535
3524 operand immI_65535() %{
3525 predicate(n->get_int() == 65535);
3526 match(ConI);
3527 op_cost(0);
3528
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 // Long Immediate: the value FF
3534 operand immL_FF() %{
3535 predicate( n->get_long() == 0xFFL );
3536 match(ConL);
3537 op_cost(0);
3538
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Long Immediate: the value FFFF
3544 operand immL_FFFF() %{
3545 predicate( n->get_long() == 0xFFFFL );
3546 match(ConL);
3547 op_cost(0);
3548
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3552
3553 // Pointer Immediate: 32 or 64-bit
3554 operand immP() %{
3555 match(ConP);
3556
3557 op_cost(5);
3558 // formats are generated automatically for constants and base registers
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 #ifdef _LP64
3564 // Pointer Immediate: 64-bit
3565 operand immP_set() %{
3566 predicate(!VM_Version::is_niagara_plus());
3567 match(ConP);
3568
3569 op_cost(5);
3570 // formats are generated automatically for constants and base registers
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574
3575 // Pointer Immediate: 64-bit
3576 // From Niagara2 processors on a load should be better than materializing.
3577 operand immP_load() %{
3578 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3579 match(ConP);
3580
3581 op_cost(5);
3582 // formats are generated automatically for constants and base registers
3583 format %{ %}
3584 interface(CONST_INTER);
3585 %}
3586
3587 // Pointer Immediate: 64-bit
3588 operand immP_no_oop_cheap() %{
3589 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3590 match(ConP);
3591
3592 op_cost(5);
3593 // formats are generated automatically for constants and base registers
3594 format %{ %}
3595 interface(CONST_INTER);
3596 %}
3597 #endif
3598
3599 operand immP13() %{
3600 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3601 match(ConP);
3602 op_cost(0);
3603
3604 format %{ %}
3605 interface(CONST_INTER);
3606 %}
3607
3608 operand immP0() %{
3609 predicate(n->get_ptr() == 0);
3610 match(ConP);
3611 op_cost(0);
3612
3613 format %{ %}
3614 interface(CONST_INTER);
3615 %}
3616
3617 operand immP_poll() %{
3618 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3619 match(ConP);
3620
3621 // formats are generated automatically for constants and base registers
3622 format %{ %}
3623 interface(CONST_INTER);
3624 %}
3625
3626 // Pointer Immediate
3627 operand immN()
3628 %{
3629 match(ConN);
3630
3631 op_cost(10);
3632 format %{ %}
3633 interface(CONST_INTER);
3634 %}
3635
3636 // NULL Pointer Immediate
3637 operand immN0()
3638 %{
3639 predicate(n->get_narrowcon() == 0);
3640 match(ConN);
3641
3642 op_cost(0);
3643 format %{ %}
3644 interface(CONST_INTER);
3645 %}
3646
3647 operand immL() %{
3648 match(ConL);
3649 op_cost(40);
3650 // formats are generated automatically for constants and base registers
3651 format %{ %}
3652 interface(CONST_INTER);
3653 %}
3654
3655 operand immL0() %{
3656 predicate(n->get_long() == 0L);
3657 match(ConL);
3658 op_cost(0);
3659 // formats are generated automatically for constants and base registers
3660 format %{ %}
3661 interface(CONST_INTER);
3662 %}
3663
3664 // Integer Immediate: 5-bit
3665 operand immL5() %{
3666 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3667 match(ConL);
3668 op_cost(0);
3669 format %{ %}
3670 interface(CONST_INTER);
3671 %}
3672
3673 // Long Immediate: 13-bit
3674 operand immL13() %{
3675 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3676 match(ConL);
3677 op_cost(0);
3678
3679 format %{ %}
3680 interface(CONST_INTER);
3681 %}
3682
3683 // Long Immediate: 13-bit minus 7
3684 operand immL13m7() %{
3685 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3686 match(ConL);
3687 op_cost(0);
3688
3689 format %{ %}
3690 interface(CONST_INTER);
3691 %}
3692
3693 // Long Immediate: low 32-bit mask
3694 operand immL_32bits() %{
3695 predicate(n->get_long() == 0xFFFFFFFFL);
3696 match(ConL);
3697 op_cost(0);
3698
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3702
3703 // Long Immediate: cheap (materialize in <= 3 instructions)
3704 operand immL_cheap() %{
3705 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3706 match(ConL);
3707 op_cost(0);
3708
3709 format %{ %}
3710 interface(CONST_INTER);
3711 %}
3712
3713 // Long Immediate: expensive (materialize in > 3 instructions)
3714 operand immL_expensive() %{
3715 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3716 match(ConL);
3717 op_cost(0);
3718
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 // Double Immediate
3724 operand immD() %{
3725 match(ConD);
3726
3727 op_cost(40);
3728 format %{ %}
3729 interface(CONST_INTER);
3730 %}
3731
3732 operand immD0() %{
3733 #ifdef _LP64
3734 // on 64-bit architectures this comparision is faster
3735 predicate(jlong_cast(n->getd()) == 0);
3736 #else
3737 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3738 #endif
3739 match(ConD);
3740
3741 op_cost(0);
3742 format %{ %}
3743 interface(CONST_INTER);
3744 %}
3745
3746 // Float Immediate
3747 operand immF() %{
3748 match(ConF);
3749
3750 op_cost(20);
3751 format %{ %}
3752 interface(CONST_INTER);
3753 %}
3754
3755 // Float Immediate: 0
3756 operand immF0() %{
3757 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3758 match(ConF);
3759
3760 op_cost(0);
3761 format %{ %}
3762 interface(CONST_INTER);
3763 %}
3764
3765 // Integer Register Operands
3766 // Integer Register
3767 operand iRegI() %{
3768 constraint(ALLOC_IN_RC(int_reg));
3769 match(RegI);
3770
3771 match(notemp_iRegI);
3772 match(g1RegI);
3773 match(o0RegI);
3774 match(iRegIsafe);
3775
3776 format %{ %}
3777 interface(REG_INTER);
3778 %}
3779
3780 operand notemp_iRegI() %{
3781 constraint(ALLOC_IN_RC(notemp_int_reg));
3782 match(RegI);
3783
3784 match(o0RegI);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 operand o0RegI() %{
3791 constraint(ALLOC_IN_RC(o0_regI));
3792 match(iRegI);
3793
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3797
3798 // Pointer Register
3799 operand iRegP() %{
3800 constraint(ALLOC_IN_RC(ptr_reg));
3801 match(RegP);
3802
3803 match(lock_ptr_RegP);
3804 match(g1RegP);
3805 match(g2RegP);
3806 match(g3RegP);
3807 match(g4RegP);
3808 match(i0RegP);
3809 match(o0RegP);
3810 match(o1RegP);
3811 match(l7RegP);
3812
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3816
3817 operand sp_ptr_RegP() %{
3818 constraint(ALLOC_IN_RC(sp_ptr_reg));
3819 match(RegP);
3820 match(iRegP);
3821
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand lock_ptr_RegP() %{
3827 constraint(ALLOC_IN_RC(lock_ptr_reg));
3828 match(RegP);
3829 match(i0RegP);
3830 match(o0RegP);
3831 match(o1RegP);
3832 match(l7RegP);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand g1RegP() %{
3839 constraint(ALLOC_IN_RC(g1_regP));
3840 match(iRegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand g2RegP() %{
3847 constraint(ALLOC_IN_RC(g2_regP));
3848 match(iRegP);
3849
3850 format %{ %}
3851 interface(REG_INTER);
3852 %}
3853
3854 operand g3RegP() %{
3855 constraint(ALLOC_IN_RC(g3_regP));
3856 match(iRegP);
3857
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand g1RegI() %{
3863 constraint(ALLOC_IN_RC(g1_regI));
3864 match(iRegI);
3865
3866 format %{ %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand g3RegI() %{
3871 constraint(ALLOC_IN_RC(g3_regI));
3872 match(iRegI);
3873
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3877
3878 operand g4RegI() %{
3879 constraint(ALLOC_IN_RC(g4_regI));
3880 match(iRegI);
3881
3882 format %{ %}
3883 interface(REG_INTER);
3884 %}
3885
3886 operand g4RegP() %{
3887 constraint(ALLOC_IN_RC(g4_regP));
3888 match(iRegP);
3889
3890 format %{ %}
3891 interface(REG_INTER);
3892 %}
3893
3894 operand i0RegP() %{
3895 constraint(ALLOC_IN_RC(i0_regP));
3896 match(iRegP);
3897
3898 format %{ %}
3899 interface(REG_INTER);
3900 %}
3901
3902 operand o0RegP() %{
3903 constraint(ALLOC_IN_RC(o0_regP));
3904 match(iRegP);
3905
3906 format %{ %}
3907 interface(REG_INTER);
3908 %}
3909
3910 operand o1RegP() %{
3911 constraint(ALLOC_IN_RC(o1_regP));
3912 match(iRegP);
3913
3914 format %{ %}
3915 interface(REG_INTER);
3916 %}
3917
3918 operand o2RegP() %{
3919 constraint(ALLOC_IN_RC(o2_regP));
3920 match(iRegP);
3921
3922 format %{ %}
3923 interface(REG_INTER);
3924 %}
3925
3926 operand o7RegP() %{
3927 constraint(ALLOC_IN_RC(o7_regP));
3928 match(iRegP);
3929
3930 format %{ %}
3931 interface(REG_INTER);
3932 %}
3933
3934 operand l7RegP() %{
3935 constraint(ALLOC_IN_RC(l7_regP));
3936 match(iRegP);
3937
3938 format %{ %}
3939 interface(REG_INTER);
3940 %}
3941
3942 operand o7RegI() %{
3943 constraint(ALLOC_IN_RC(o7_regI));
3944 match(iRegI);
3945
3946 format %{ %}
3947 interface(REG_INTER);
3948 %}
3949
3950 operand iRegN() %{
3951 constraint(ALLOC_IN_RC(int_reg));
3952 match(RegN);
3953
3954 format %{ %}
3955 interface(REG_INTER);
3956 %}
3957
3958 // Long Register
3959 operand iRegL() %{
3960 constraint(ALLOC_IN_RC(long_reg));
3961 match(RegL);
3962
3963 format %{ %}
3964 interface(REG_INTER);
3965 %}
3966
3967 operand o2RegL() %{
3968 constraint(ALLOC_IN_RC(o2_regL));
3969 match(iRegL);
3970
3971 format %{ %}
3972 interface(REG_INTER);
3973 %}
3974
3975 operand o7RegL() %{
3976 constraint(ALLOC_IN_RC(o7_regL));
3977 match(iRegL);
3978
3979 format %{ %}
3980 interface(REG_INTER);
3981 %}
3982
3983 operand g1RegL() %{
3984 constraint(ALLOC_IN_RC(g1_regL));
3985 match(iRegL);
3986
3987 format %{ %}
3988 interface(REG_INTER);
3989 %}
3990
3991 operand g3RegL() %{
3992 constraint(ALLOC_IN_RC(g3_regL));
3993 match(iRegL);
3994
3995 format %{ %}
3996 interface(REG_INTER);
3997 %}
3998
3999 // Int Register safe
4000 // This is 64bit safe
4001 operand iRegIsafe() %{
4002 constraint(ALLOC_IN_RC(long_reg));
4003
4004 match(iRegI);
4005
4006 format %{ %}
4007 interface(REG_INTER);
4008 %}
4009
4010 // Condition Code Flag Register
4011 operand flagsReg() %{
4012 constraint(ALLOC_IN_RC(int_flags));
4013 match(RegFlags);
4014
4015 format %{ "ccr" %} // both ICC and XCC
4016 interface(REG_INTER);
4017 %}
4018
4019 // Condition Code Register, unsigned comparisons.
4020 operand flagsRegU() %{
4021 constraint(ALLOC_IN_RC(int_flags));
4022 match(RegFlags);
4023
4024 format %{ "icc_U" %}
4025 interface(REG_INTER);
4026 %}
4027
4028 // Condition Code Register, pointer comparisons.
4029 operand flagsRegP() %{
4030 constraint(ALLOC_IN_RC(int_flags));
4031 match(RegFlags);
4032
4033 #ifdef _LP64
4034 format %{ "xcc_P" %}
4035 #else
4036 format %{ "icc_P" %}
4037 #endif
4038 interface(REG_INTER);
4039 %}
4040
4041 // Condition Code Register, long comparisons.
4042 operand flagsRegL() %{
4043 constraint(ALLOC_IN_RC(int_flags));
4044 match(RegFlags);
4045
4046 format %{ "xcc_L" %}
4047 interface(REG_INTER);
4048 %}
4049
4050 // Condition Code Register, floating comparisons, unordered same as "less".
4051 operand flagsRegF() %{
4052 constraint(ALLOC_IN_RC(float_flags));
4053 match(RegFlags);
4054 match(flagsRegF0);
4055
4056 format %{ %}
4057 interface(REG_INTER);
4058 %}
4059
4060 operand flagsRegF0() %{
4061 constraint(ALLOC_IN_RC(float_flag0));
4062 match(RegFlags);
4063
4064 format %{ %}
4065 interface(REG_INTER);
4066 %}
4067
4068
4069 // Condition Code Flag Register used by long compare
4070 operand flagsReg_long_LTGE() %{
4071 constraint(ALLOC_IN_RC(int_flags));
4072 match(RegFlags);
4073 format %{ "icc_LTGE" %}
4074 interface(REG_INTER);
4075 %}
4076 operand flagsReg_long_EQNE() %{
4077 constraint(ALLOC_IN_RC(int_flags));
4078 match(RegFlags);
4079 format %{ "icc_EQNE" %}
4080 interface(REG_INTER);
4081 %}
4082 operand flagsReg_long_LEGT() %{
4083 constraint(ALLOC_IN_RC(int_flags));
4084 match(RegFlags);
4085 format %{ "icc_LEGT" %}
4086 interface(REG_INTER);
4087 %}
4088
4089
4090 operand regD() %{
4091 constraint(ALLOC_IN_RC(dflt_reg));
4092 match(RegD);
4093
4094 match(regD_low);
4095
4096 format %{ %}
4097 interface(REG_INTER);
4098 %}
4099
4100 operand regF() %{
4101 constraint(ALLOC_IN_RC(sflt_reg));
4102 match(RegF);
4103
4104 format %{ %}
4105 interface(REG_INTER);
4106 %}
4107
4108 operand regD_low() %{
4109 constraint(ALLOC_IN_RC(dflt_low_reg));
4110 match(regD);
4111
4112 format %{ %}
4113 interface(REG_INTER);
4114 %}
4115
4116 // Special Registers
4117
4118 // Method Register
4119 operand inline_cache_regP(iRegP reg) %{
4120 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4121 match(reg);
4122 format %{ %}
4123 interface(REG_INTER);
4124 %}
4125
4126 operand interpreter_method_oop_regP(iRegP reg) %{
4127 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4128 match(reg);
4129 format %{ %}
4130 interface(REG_INTER);
4131 %}
4132
4133
4134 //----------Complex Operands---------------------------------------------------
4135 // Indirect Memory Reference
4136 operand indirect(sp_ptr_RegP reg) %{
4137 constraint(ALLOC_IN_RC(sp_ptr_reg));
4138 match(reg);
4139
4140 op_cost(100);
4141 format %{ "[$reg]" %}
4142 interface(MEMORY_INTER) %{
4143 base($reg);
4144 index(0x0);
4145 scale(0x0);
4146 disp(0x0);
4147 %}
4148 %}
4149
4150 // Indirect with simm13 Offset
4151 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4152 constraint(ALLOC_IN_RC(sp_ptr_reg));
4153 match(AddP reg offset);
4154
4155 op_cost(100);
4156 format %{ "[$reg + $offset]" %}
4157 interface(MEMORY_INTER) %{
4158 base($reg);
4159 index(0x0);
4160 scale(0x0);
4161 disp($offset);
4162 %}
4163 %}
4164
4165 // Indirect with simm13 Offset minus 7
4166 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4167 constraint(ALLOC_IN_RC(sp_ptr_reg));
4168 match(AddP reg offset);
4169
4170 op_cost(100);
4171 format %{ "[$reg + $offset]" %}
4172 interface(MEMORY_INTER) %{
4173 base($reg);
4174 index(0x0);
4175 scale(0x0);
4176 disp($offset);
4177 %}
4178 %}
4179
4180 // Note: Intel has a swapped version also, like this:
4181 //operand indOffsetX(iRegI reg, immP offset) %{
4182 // constraint(ALLOC_IN_RC(int_reg));
4183 // match(AddP offset reg);
4184 //
4185 // op_cost(100);
4186 // format %{ "[$reg + $offset]" %}
4187 // interface(MEMORY_INTER) %{
4188 // base($reg);
4189 // index(0x0);
4190 // scale(0x0);
4191 // disp($offset);
4192 // %}
4193 //%}
4194 //// However, it doesn't make sense for SPARC, since
4195 // we have no particularly good way to embed oops in
4196 // single instructions.
4197
4198 // Indirect with Register Index
4199 operand indIndex(iRegP addr, iRegX index) %{
4200 constraint(ALLOC_IN_RC(ptr_reg));
4201 match(AddP addr index);
4202
4203 op_cost(100);
4204 format %{ "[$addr + $index]" %}
4205 interface(MEMORY_INTER) %{
4206 base($addr);
4207 index($index);
4208 scale(0x0);
4209 disp(0x0);
4210 %}
4211 %}
4212
4213 //----------Special Memory Operands--------------------------------------------
4214 // Stack Slot Operand - This operand is used for loading and storing temporary
4215 // values on the stack where a match requires a value to
4216 // flow through memory.
4217 operand stackSlotI(sRegI reg) %{
4218 constraint(ALLOC_IN_RC(stack_slots));
4219 op_cost(100);
4220 //match(RegI);
4221 format %{ "[$reg]" %}
4222 interface(MEMORY_INTER) %{
4223 base(0xE); // R_SP
4224 index(0x0);
4225 scale(0x0);
4226 disp($reg); // Stack Offset
4227 %}
4228 %}
4229
4230 operand stackSlotP(sRegP reg) %{
4231 constraint(ALLOC_IN_RC(stack_slots));
4232 op_cost(100);
4233 //match(RegP);
4234 format %{ "[$reg]" %}
4235 interface(MEMORY_INTER) %{
4236 base(0xE); // R_SP
4237 index(0x0);
4238 scale(0x0);
4239 disp($reg); // Stack Offset
4240 %}
4241 %}
4242
4243 operand stackSlotF(sRegF reg) %{
4244 constraint(ALLOC_IN_RC(stack_slots));
4245 op_cost(100);
4246 //match(RegF);
4247 format %{ "[$reg]" %}
4248 interface(MEMORY_INTER) %{
4249 base(0xE); // R_SP
4250 index(0x0);
4251 scale(0x0);
4252 disp($reg); // Stack Offset
4253 %}
4254 %}
4255 operand stackSlotD(sRegD reg) %{
4256 constraint(ALLOC_IN_RC(stack_slots));
4257 op_cost(100);
4258 //match(RegD);
4259 format %{ "[$reg]" %}
4260 interface(MEMORY_INTER) %{
4261 base(0xE); // R_SP
4262 index(0x0);
4263 scale(0x0);
4264 disp($reg); // Stack Offset
4265 %}
4266 %}
4267 operand stackSlotL(sRegL reg) %{
4268 constraint(ALLOC_IN_RC(stack_slots));
4269 op_cost(100);
4270 //match(RegL);
4271 format %{ "[$reg]" %}
4272 interface(MEMORY_INTER) %{
4273 base(0xE); // R_SP
4274 index(0x0);
4275 scale(0x0);
4276 disp($reg); // Stack Offset
4277 %}
4278 %}
4279
4280 // Operands for expressing Control Flow
4281 // NOTE: Label is a predefined operand which should not be redefined in
4282 // the AD file. It is generically handled within the ADLC.
4283
4284 //----------Conditional Branch Operands----------------------------------------
4285 // Comparison Op - This is the operation of the comparison, and is limited to
4286 // the following set of codes:
4287 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4288 //
4289 // Other attributes of the comparison, such as unsignedness, are specified
4290 // by the comparison instruction that sets a condition code flags register.
4291 // That result is represented by a flags operand whose subtype is appropriate
4292 // to the unsignedness (etc.) of the comparison.
4293 //
4294 // Later, the instruction which matches both the Comparison Op (a Bool) and
4295 // the flags (produced by the Cmp) specifies the coding of the comparison op
4296 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4297
4298 operand cmpOp() %{
4299 match(Bool);
4300
4301 format %{ "" %}
4302 interface(COND_INTER) %{
4303 equal(0x1);
4304 not_equal(0x9);
4305 less(0x3);
4306 greater_equal(0xB);
4307 less_equal(0x2);
4308 greater(0xA);
4309 %}
4310 %}
4311
4312 // Comparison Op, unsigned
4313 operand cmpOpU() %{
4314 match(Bool);
4315
4316 format %{ "u" %}
4317 interface(COND_INTER) %{
4318 equal(0x1);
4319 not_equal(0x9);
4320 less(0x5);
4321 greater_equal(0xD);
4322 less_equal(0x4);
4323 greater(0xC);
4324 %}
4325 %}
4326
4327 // Comparison Op, pointer (same as unsigned)
4328 operand cmpOpP() %{
4329 match(Bool);
4330
4331 format %{ "p" %}
4332 interface(COND_INTER) %{
4333 equal(0x1);
4334 not_equal(0x9);
4335 less(0x5);
4336 greater_equal(0xD);
4337 less_equal(0x4);
4338 greater(0xC);
4339 %}
4340 %}
4341
4342 // Comparison Op, branch-register encoding
4343 operand cmpOp_reg() %{
4344 match(Bool);
4345
4346 format %{ "" %}
4347 interface(COND_INTER) %{
4348 equal (0x1);
4349 not_equal (0x5);
4350 less (0x3);
4351 greater_equal(0x7);
4352 less_equal (0x2);
4353 greater (0x6);
4354 %}
4355 %}
4356
4357 // Comparison Code, floating, unordered same as less
4358 operand cmpOpF() %{
4359 match(Bool);
4360
4361 format %{ "fl" %}
4362 interface(COND_INTER) %{
4363 equal(0x9);
4364 not_equal(0x1);
4365 less(0x3);
4366 greater_equal(0xB);
4367 less_equal(0xE);
4368 greater(0x6);
4369 %}
4370 %}
4371
4372 // Used by long compare
4373 operand cmpOp_commute() %{
4374 match(Bool);
4375
4376 format %{ "" %}
4377 interface(COND_INTER) %{
4378 equal(0x1);
4379 not_equal(0x9);
4380 less(0xA);
4381 greater_equal(0x2);
4382 less_equal(0xB);
4383 greater(0x3);
4384 %}
4385 %}
4386
4387 //----------OPERAND CLASSES----------------------------------------------------
4388 // Operand Classes are groups of operands that are used to simplify
4389 // instruction definitions by not requiring the AD writer to specify separate
4390 // instructions for every form of operand when the instruction accepts
4391 // multiple operand types with the same basic encoding and format. The classic
4392 // case of this is memory operands.
4393 opclass memory( indirect, indOffset13, indIndex );
4394 opclass indIndexMemory( indIndex );
4395
4396 //----------PIPELINE-----------------------------------------------------------
4397 pipeline %{
4398
4399 //----------ATTRIBUTES---------------------------------------------------------
4400 attributes %{
4401 fixed_size_instructions; // Fixed size instructions
4402 branch_has_delay_slot; // Branch has delay slot following
4403 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4404 instruction_unit_size = 4; // An instruction is 4 bytes long
4405 instruction_fetch_unit_size = 16; // The processor fetches one line
4406 instruction_fetch_units = 1; // of 16 bytes
4407
4408 // List of nop instructions
4409 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4410 %}
4411
4412 //----------RESOURCES----------------------------------------------------------
4413 // Resources are the functional units available to the machine
4414 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4415
4416 //----------PIPELINE DESCRIPTION-----------------------------------------------
4417 // Pipeline Description specifies the stages in the machine's pipeline
4418
4419 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4420
4421 //----------PIPELINE CLASSES---------------------------------------------------
4422 // Pipeline Classes describe the stages in which input and output are
4423 // referenced by the hardware pipeline.
4424
4425 // Integer ALU reg-reg operation
4426 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4427 single_instruction;
4428 dst : E(write);
4429 src1 : R(read);
4430 src2 : R(read);
4431 IALU : R;
4432 %}
4433
4434 // Integer ALU reg-reg long operation
4435 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4436 instruction_count(2);
4437 dst : E(write);
4438 src1 : R(read);
4439 src2 : R(read);
4440 IALU : R;
4441 IALU : R;
4442 %}
4443
4444 // Integer ALU reg-reg long dependent operation
4445 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4446 instruction_count(1); multiple_bundles;
4447 dst : E(write);
4448 src1 : R(read);
4449 src2 : R(read);
4450 cr : E(write);
4451 IALU : R(2);
4452 %}
4453
4454 // Integer ALU reg-imm operaion
4455 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4456 single_instruction;
4457 dst : E(write);
4458 src1 : R(read);
4459 IALU : R;
4460 %}
4461
4462 // Integer ALU reg-reg operation with condition code
4463 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4464 single_instruction;
4465 dst : E(write);
4466 cr : E(write);
4467 src1 : R(read);
4468 src2 : R(read);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU reg-imm operation with condition code
4473 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4474 single_instruction;
4475 dst : E(write);
4476 cr : E(write);
4477 src1 : R(read);
4478 IALU : R;
4479 %}
4480
4481 // Integer ALU zero-reg operation
4482 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4483 single_instruction;
4484 dst : E(write);
4485 src2 : R(read);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU zero-reg operation with condition code only
4490 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4491 single_instruction;
4492 cr : E(write);
4493 src : R(read);
4494 IALU : R;
4495 %}
4496
4497 // Integer ALU reg-reg operation with condition code only
4498 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4499 single_instruction;
4500 cr : E(write);
4501 src1 : R(read);
4502 src2 : R(read);
4503 IALU : R;
4504 %}
4505
4506 // Integer ALU reg-imm operation with condition code only
4507 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4508 single_instruction;
4509 cr : E(write);
4510 src1 : R(read);
4511 IALU : R;
4512 %}
4513
4514 // Integer ALU reg-reg-zero operation with condition code only
4515 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4516 single_instruction;
4517 cr : E(write);
4518 src1 : R(read);
4519 src2 : R(read);
4520 IALU : R;
4521 %}
4522
4523 // Integer ALU reg-imm-zero operation with condition code only
4524 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4525 single_instruction;
4526 cr : E(write);
4527 src1 : R(read);
4528 IALU : R;
4529 %}
4530
4531 // Integer ALU reg-reg operation with condition code, src1 modified
4532 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4533 single_instruction;
4534 cr : E(write);
4535 src1 : E(write);
4536 src1 : R(read);
4537 src2 : R(read);
4538 IALU : R;
4539 %}
4540
4541 // Integer ALU reg-imm operation with condition code, src1 modified
4542 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4543 single_instruction;
4544 cr : E(write);
4545 src1 : E(write);
4546 src1 : R(read);
4547 IALU : R;
4548 %}
4549
4550 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4551 multiple_bundles;
4552 dst : E(write)+4;
4553 cr : E(write);
4554 src1 : R(read);
4555 src2 : R(read);
4556 IALU : R(3);
4557 BR : R(2);
4558 %}
4559
4560 // Integer ALU operation
4561 pipe_class ialu_none(iRegI dst) %{
4562 single_instruction;
4563 dst : E(write);
4564 IALU : R;
4565 %}
4566
4567 // Integer ALU reg operation
4568 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4569 single_instruction; may_have_no_code;
4570 dst : E(write);
4571 src : R(read);
4572 IALU : R;
4573 %}
4574
4575 // Integer ALU reg conditional operation
4576 // This instruction has a 1 cycle stall, and cannot execute
4577 // in the same cycle as the instruction setting the condition
4578 // code. We kludge this by pretending to read the condition code
4579 // 1 cycle earlier, and by marking the functional units as busy
4580 // for 2 cycles with the result available 1 cycle later than
4581 // is really the case.
4582 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4583 single_instruction;
4584 op2_out : C(write);
4585 op1 : R(read);
4586 cr : R(read); // This is really E, with a 1 cycle stall
4587 BR : R(2);
4588 MS : R(2);
4589 %}
4590
4591 #ifdef _LP64
4592 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4593 instruction_count(1); multiple_bundles;
4594 dst : C(write)+1;
4595 src : R(read)+1;
4596 IALU : R(1);
4597 BR : E(2);
4598 MS : E(2);
4599 %}
4600 #endif
4601
4602 // Integer ALU reg operation
4603 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4604 single_instruction; may_have_no_code;
4605 dst : E(write);
4606 src : R(read);
4607 IALU : R;
4608 %}
4609 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4610 single_instruction; may_have_no_code;
4611 dst : E(write);
4612 src : R(read);
4613 IALU : R;
4614 %}
4615
4616 // Two integer ALU reg operations
4617 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4618 instruction_count(2);
4619 dst : E(write);
4620 src : R(read);
4621 A0 : R;
4622 A1 : R;
4623 %}
4624
4625 // Two integer ALU reg operations
4626 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4627 instruction_count(2); may_have_no_code;
4628 dst : E(write);
4629 src : R(read);
4630 A0 : R;
4631 A1 : R;
4632 %}
4633
4634 // Integer ALU imm operation
4635 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4636 single_instruction;
4637 dst : E(write);
4638 IALU : R;
4639 %}
4640
4641 // Integer ALU reg-reg with carry operation
4642 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4643 single_instruction;
4644 dst : E(write);
4645 src1 : R(read);
4646 src2 : R(read);
4647 IALU : R;
4648 %}
4649
4650 // Integer ALU cc operation
4651 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4652 single_instruction;
4653 dst : E(write);
4654 cc : R(read);
4655 IALU : R;
4656 %}
4657
4658 // Integer ALU cc / second IALU operation
4659 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4660 instruction_count(1); multiple_bundles;
4661 dst : E(write)+1;
4662 src : R(read);
4663 IALU : R;
4664 %}
4665
4666 // Integer ALU cc / second IALU operation
4667 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4668 instruction_count(1); multiple_bundles;
4669 dst : E(write)+1;
4670 p : R(read);
4671 q : R(read);
4672 IALU : R;
4673 %}
4674
4675 // Integer ALU hi-lo-reg operation
4676 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4677 instruction_count(1); multiple_bundles;
4678 dst : E(write)+1;
4679 IALU : R(2);
4680 %}
4681
4682 // Float ALU hi-lo-reg operation (with temp)
4683 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4684 instruction_count(1); multiple_bundles;
4685 dst : E(write)+1;
4686 IALU : R(2);
4687 %}
4688
4689 // Long Constant
4690 pipe_class loadConL( iRegL dst, immL src ) %{
4691 instruction_count(2); multiple_bundles;
4692 dst : E(write)+1;
4693 IALU : R(2);
4694 IALU : R(2);
4695 %}
4696
4697 // Pointer Constant
4698 pipe_class loadConP( iRegP dst, immP src ) %{
4699 instruction_count(0); multiple_bundles;
4700 fixed_latency(6);
4701 %}
4702
4703 // Polling Address
4704 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4705 #ifdef _LP64
4706 instruction_count(0); multiple_bundles;
4707 fixed_latency(6);
4708 #else
4709 dst : E(write);
4710 IALU : R;
4711 #endif
4712 %}
4713
4714 // Long Constant small
4715 pipe_class loadConLlo( iRegL dst, immL src ) %{
4716 instruction_count(2);
4717 dst : E(write);
4718 IALU : R;
4719 IALU : R;
4720 %}
4721
4722 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4723 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4724 instruction_count(1); multiple_bundles;
4725 src : R(read);
4726 dst : M(write)+1;
4727 IALU : R;
4728 MS : E;
4729 %}
4730
4731 // Integer ALU nop operation
4732 pipe_class ialu_nop() %{
4733 single_instruction;
4734 IALU : R;
4735 %}
4736
4737 // Integer ALU nop operation
4738 pipe_class ialu_nop_A0() %{
4739 single_instruction;
4740 A0 : R;
4741 %}
4742
4743 // Integer ALU nop operation
4744 pipe_class ialu_nop_A1() %{
4745 single_instruction;
4746 A1 : R;
4747 %}
4748
4749 // Integer Multiply reg-reg operation
4750 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4751 single_instruction;
4752 dst : E(write);
4753 src1 : R(read);
4754 src2 : R(read);
4755 MS : R(5);
4756 %}
4757
4758 // Integer Multiply reg-imm operation
4759 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4760 single_instruction;
4761 dst : E(write);
4762 src1 : R(read);
4763 MS : R(5);
4764 %}
4765
4766 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4767 single_instruction;
4768 dst : E(write)+4;
4769 src1 : R(read);
4770 src2 : R(read);
4771 MS : R(6);
4772 %}
4773
4774 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4775 single_instruction;
4776 dst : E(write)+4;
4777 src1 : R(read);
4778 MS : R(6);
4779 %}
4780
4781 // Integer Divide reg-reg
4782 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4783 instruction_count(1); multiple_bundles;
4784 dst : E(write);
4785 temp : E(write);
4786 src1 : R(read);
4787 src2 : R(read);
4788 temp : R(read);
4789 MS : R(38);
4790 %}
4791
4792 // Integer Divide reg-imm
4793 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4794 instruction_count(1); multiple_bundles;
4795 dst : E(write);
4796 temp : E(write);
4797 src1 : R(read);
4798 temp : R(read);
4799 MS : R(38);
4800 %}
4801
4802 // Long Divide
4803 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4804 dst : E(write)+71;
4805 src1 : R(read);
4806 src2 : R(read)+1;
4807 MS : R(70);
4808 %}
4809
4810 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4811 dst : E(write)+71;
4812 src1 : R(read);
4813 MS : R(70);
4814 %}
4815
4816 // Floating Point Add Float
4817 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4818 single_instruction;
4819 dst : X(write);
4820 src1 : E(read);
4821 src2 : E(read);
4822 FA : R;
4823 %}
4824
4825 // Floating Point Add Double
4826 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4827 single_instruction;
4828 dst : X(write);
4829 src1 : E(read);
4830 src2 : E(read);
4831 FA : R;
4832 %}
4833
4834 // Floating Point Conditional Move based on integer flags
4835 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4836 single_instruction;
4837 dst : X(write);
4838 src : E(read);
4839 cr : R(read);
4840 FA : R(2);
4841 BR : R(2);
4842 %}
4843
4844 // Floating Point Conditional Move based on integer flags
4845 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4846 single_instruction;
4847 dst : X(write);
4848 src : E(read);
4849 cr : R(read);
4850 FA : R(2);
4851 BR : R(2);
4852 %}
4853
4854 // Floating Point Multiply Float
4855 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4856 single_instruction;
4857 dst : X(write);
4858 src1 : E(read);
4859 src2 : E(read);
4860 FM : R;
4861 %}
4862
4863 // Floating Point Multiply Double
4864 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4865 single_instruction;
4866 dst : X(write);
4867 src1 : E(read);
4868 src2 : E(read);
4869 FM : R;
4870 %}
4871
4872 // Floating Point Divide Float
4873 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4874 single_instruction;
4875 dst : X(write);
4876 src1 : E(read);
4877 src2 : E(read);
4878 FM : R;
4879 FDIV : C(14);
4880 %}
4881
4882 // Floating Point Divide Double
4883 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4884 single_instruction;
4885 dst : X(write);
4886 src1 : E(read);
4887 src2 : E(read);
4888 FM : R;
4889 FDIV : C(17);
4890 %}
4891
4892 // Floating Point Move/Negate/Abs Float
4893 pipe_class faddF_reg(regF dst, regF src) %{
4894 single_instruction;
4895 dst : W(write);
4896 src : E(read);
4897 FA : R(1);
4898 %}
4899
4900 // Floating Point Move/Negate/Abs Double
4901 pipe_class faddD_reg(regD dst, regD src) %{
4902 single_instruction;
4903 dst : W(write);
4904 src : E(read);
4905 FA : R;
4906 %}
4907
4908 // Floating Point Convert F->D
4909 pipe_class fcvtF2D(regD dst, regF src) %{
4910 single_instruction;
4911 dst : X(write);
4912 src : E(read);
4913 FA : R;
4914 %}
4915
4916 // Floating Point Convert I->D
4917 pipe_class fcvtI2D(regD dst, regF src) %{
4918 single_instruction;
4919 dst : X(write);
4920 src : E(read);
4921 FA : R;
4922 %}
4923
4924 // Floating Point Convert LHi->D
4925 pipe_class fcvtLHi2D(regD dst, regD src) %{
4926 single_instruction;
4927 dst : X(write);
4928 src : E(read);
4929 FA : R;
4930 %}
4931
4932 // Floating Point Convert L->D
4933 pipe_class fcvtL2D(regD dst, regF src) %{
4934 single_instruction;
4935 dst : X(write);
4936 src : E(read);
4937 FA : R;
4938 %}
4939
4940 // Floating Point Convert L->F
4941 pipe_class fcvtL2F(regD dst, regF src) %{
4942 single_instruction;
4943 dst : X(write);
4944 src : E(read);
4945 FA : R;
4946 %}
4947
4948 // Floating Point Convert D->F
4949 pipe_class fcvtD2F(regD dst, regF src) %{
4950 single_instruction;
4951 dst : X(write);
4952 src : E(read);
4953 FA : R;
4954 %}
4955
4956 // Floating Point Convert I->L
4957 pipe_class fcvtI2L(regD dst, regF src) %{
4958 single_instruction;
4959 dst : X(write);
4960 src : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Point Convert D->F
4965 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4966 instruction_count(1); multiple_bundles;
4967 dst : X(write)+6;
4968 src : E(read);
4969 FA : R;
4970 %}
4971
4972 // Floating Point Convert D->L
4973 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4974 instruction_count(1); multiple_bundles;
4975 dst : X(write)+6;
4976 src : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Point Convert F->I
4981 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4982 instruction_count(1); multiple_bundles;
4983 dst : X(write)+6;
4984 src : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Convert F->L
4989 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4990 instruction_count(1); multiple_bundles;
4991 dst : X(write)+6;
4992 src : E(read);
4993 FA : R;
4994 %}
4995
4996 // Floating Point Convert I->F
4997 pipe_class fcvtI2F(regF dst, regF src) %{
4998 single_instruction;
4999 dst : X(write);
5000 src : E(read);
5001 FA : R;
5002 %}
5003
5004 // Floating Point Compare
5005 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5006 single_instruction;
5007 cr : X(write);
5008 src1 : E(read);
5009 src2 : E(read);
5010 FA : R;
5011 %}
5012
5013 // Floating Point Compare
5014 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5015 single_instruction;
5016 cr : X(write);
5017 src1 : E(read);
5018 src2 : E(read);
5019 FA : R;
5020 %}
5021
5022 // Floating Add Nop
5023 pipe_class fadd_nop() %{
5024 single_instruction;
5025 FA : R;
5026 %}
5027
5028 // Integer Store to Memory
5029 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5030 single_instruction;
5031 mem : R(read);
5032 src : C(read);
5033 MS : R;
5034 %}
5035
5036 // Integer Store to Memory
5037 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5038 single_instruction;
5039 mem : R(read);
5040 src : C(read);
5041 MS : R;
5042 %}
5043
5044 // Integer Store Zero to Memory
5045 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5046 single_instruction;
5047 mem : R(read);
5048 MS : R;
5049 %}
5050
5051 // Special Stack Slot Store
5052 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5053 single_instruction;
5054 stkSlot : R(read);
5055 src : C(read);
5056 MS : R;
5057 %}
5058
5059 // Special Stack Slot Store
5060 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5061 instruction_count(2); multiple_bundles;
5062 stkSlot : R(read);
5063 src : C(read);
5064 MS : R(2);
5065 %}
5066
5067 // Float Store
5068 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5069 single_instruction;
5070 mem : R(read);
5071 src : C(read);
5072 MS : R;
5073 %}
5074
5075 // Float Store
5076 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5077 single_instruction;
5078 mem : R(read);
5079 MS : R;
5080 %}
5081
5082 // Double Store
5083 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5084 instruction_count(1);
5085 mem : R(read);
5086 src : C(read);
5087 MS : R;
5088 %}
5089
5090 // Double Store
5091 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5092 single_instruction;
5093 mem : R(read);
5094 MS : R;
5095 %}
5096
5097 // Special Stack Slot Float Store
5098 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5099 single_instruction;
5100 stkSlot : R(read);
5101 src : C(read);
5102 MS : R;
5103 %}
5104
5105 // Special Stack Slot Double Store
5106 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5107 single_instruction;
5108 stkSlot : R(read);
5109 src : C(read);
5110 MS : R;
5111 %}
5112
5113 // Integer Load (when sign bit propagation not needed)
5114 pipe_class iload_mem(iRegI dst, memory mem) %{
5115 single_instruction;
5116 mem : R(read);
5117 dst : C(write);
5118 MS : R;
5119 %}
5120
5121 // Integer Load from stack operand
5122 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5123 single_instruction;
5124 mem : R(read);
5125 dst : C(write);
5126 MS : R;
5127 %}
5128
5129 // Integer Load (when sign bit propagation or masking is needed)
5130 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5131 single_instruction;
5132 mem : R(read);
5133 dst : M(write);
5134 MS : R;
5135 %}
5136
5137 // Float Load
5138 pipe_class floadF_mem(regF dst, memory mem) %{
5139 single_instruction;
5140 mem : R(read);
5141 dst : M(write);
5142 MS : R;
5143 %}
5144
5145 // Float Load
5146 pipe_class floadD_mem(regD dst, memory mem) %{
5147 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5148 mem : R(read);
5149 dst : M(write);
5150 MS : R;
5151 %}
5152
5153 // Float Load
5154 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5155 single_instruction;
5156 stkSlot : R(read);
5157 dst : M(write);
5158 MS : R;
5159 %}
5160
5161 // Float Load
5162 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5163 single_instruction;
5164 stkSlot : R(read);
5165 dst : M(write);
5166 MS : R;
5167 %}
5168
5169 // Memory Nop
5170 pipe_class mem_nop() %{
5171 single_instruction;
5172 MS : R;
5173 %}
5174
5175 pipe_class sethi(iRegP dst, immI src) %{
5176 single_instruction;
5177 dst : E(write);
5178 IALU : R;
5179 %}
5180
5181 pipe_class loadPollP(iRegP poll) %{
5182 single_instruction;
5183 poll : R(read);
5184 MS : R;
5185 %}
5186
5187 pipe_class br(Universe br, label labl) %{
5188 single_instruction_with_delay_slot;
5189 BR : R;
5190 %}
5191
5192 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5193 single_instruction_with_delay_slot;
5194 cr : E(read);
5195 BR : R;
5196 %}
5197
5198 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5199 single_instruction_with_delay_slot;
5200 op1 : E(read);
5201 BR : R;
5202 MS : R;
5203 %}
5204
5205 // Compare and branch
5206 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5207 instruction_count(2); has_delay_slot;
5208 cr : E(write);
5209 src1 : R(read);
5210 src2 : R(read);
5211 IALU : R;
5212 BR : R;
5213 %}
5214
5215 // Compare and branch
5216 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5217 instruction_count(2); has_delay_slot;
5218 cr : E(write);
5219 src1 : R(read);
5220 IALU : R;
5221 BR : R;
5222 %}
5223
5224 // Compare and branch using cbcond
5225 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5226 single_instruction;
5227 src1 : E(read);
5228 src2 : E(read);
5229 IALU : R;
5230 BR : R;
5231 %}
5232
5233 // Compare and branch using cbcond
5234 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5235 single_instruction;
5236 src1 : E(read);
5237 IALU : R;
5238 BR : R;
5239 %}
5240
5241 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5242 single_instruction_with_delay_slot;
5243 cr : E(read);
5244 BR : R;
5245 %}
5246
5247 pipe_class br_nop() %{
5248 single_instruction;
5249 BR : R;
5250 %}
5251
5252 pipe_class simple_call(method meth) %{
5253 instruction_count(2); multiple_bundles; force_serialization;
5254 fixed_latency(100);
5255 BR : R(1);
5256 MS : R(1);
5257 A0 : R(1);
5258 %}
5259
5260 pipe_class compiled_call(method meth) %{
5261 instruction_count(1); multiple_bundles; force_serialization;
5262 fixed_latency(100);
5263 MS : R(1);
5264 %}
5265
5266 pipe_class call(method meth) %{
5267 instruction_count(0); multiple_bundles; force_serialization;
5268 fixed_latency(100);
5269 %}
5270
5271 pipe_class tail_call(Universe ignore, label labl) %{
5272 single_instruction; has_delay_slot;
5273 fixed_latency(100);
5274 BR : R(1);
5275 MS : R(1);
5276 %}
5277
5278 pipe_class ret(Universe ignore) %{
5279 single_instruction; has_delay_slot;
5280 BR : R(1);
5281 MS : R(1);
5282 %}
5283
5284 pipe_class ret_poll(g3RegP poll) %{
5285 instruction_count(3); has_delay_slot;
5286 poll : E(read);
5287 MS : R;
5288 %}
5289
5290 // The real do-nothing guy
5291 pipe_class empty( ) %{
5292 instruction_count(0);
5293 %}
5294
5295 pipe_class long_memory_op() %{
5296 instruction_count(0); multiple_bundles; force_serialization;
5297 fixed_latency(25);
5298 MS : R(1);
5299 %}
5300
5301 // Check-cast
5302 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5303 array : R(read);
5304 match : R(read);
5305 IALU : R(2);
5306 BR : R(2);
5307 MS : R;
5308 %}
5309
5310 // Convert FPU flags into +1,0,-1
5311 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5312 src1 : E(read);
5313 src2 : E(read);
5314 dst : E(write);
5315 FA : R;
5316 MS : R(2);
5317 BR : R(2);
5318 %}
5319
5320 // Compare for p < q, and conditionally add y
5321 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5322 p : E(read);
5323 q : E(read);
5324 y : E(read);
5325 IALU : R(3)
5326 %}
5327
5328 // Perform a compare, then move conditionally in a branch delay slot.
5329 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5330 src2 : E(read);
5331 srcdst : E(read);
5332 IALU : R;
5333 BR : R;
5334 %}
5335
5336 // Define the class for the Nop node
5337 define %{
5338 MachNop = ialu_nop;
5339 %}
5340
5341 %}
5342
5343 //----------INSTRUCTIONS-------------------------------------------------------
5344
5345 //------------Special Stack Slot instructions - no match rules-----------------
5346 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5347 // No match rule to avoid chain rule match.
5348 effect(DEF dst, USE src);
5349 ins_cost(MEMORY_REF_COST);
5350 size(4);
5351 format %{ "LDF $src,$dst\t! stkI to regF" %}
5352 opcode(Assembler::ldf_op3);
5353 ins_encode(simple_form3_mem_reg(src, dst));
5354 ins_pipe(floadF_stk);
5355 %}
5356
5357 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5358 // No match rule to avoid chain rule match.
5359 effect(DEF dst, USE src);
5360 ins_cost(MEMORY_REF_COST);
5361 size(4);
5362 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5363 opcode(Assembler::lddf_op3);
5364 ins_encode(simple_form3_mem_reg(src, dst));
5365 ins_pipe(floadD_stk);
5366 %}
5367
5368 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5369 // No match rule to avoid chain rule match.
5370 effect(DEF dst, USE src);
5371 ins_cost(MEMORY_REF_COST);
5372 size(4);
5373 format %{ "STF $src,$dst\t! regF to stkI" %}
5374 opcode(Assembler::stf_op3);
5375 ins_encode(simple_form3_mem_reg(dst, src));
5376 ins_pipe(fstoreF_stk_reg);
5377 %}
5378
5379 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5380 // No match rule to avoid chain rule match.
5381 effect(DEF dst, USE src);
5382 ins_cost(MEMORY_REF_COST);
5383 size(4);
5384 format %{ "STDF $src,$dst\t! regD to stkL" %}
5385 opcode(Assembler::stdf_op3);
5386 ins_encode(simple_form3_mem_reg(dst, src));
5387 ins_pipe(fstoreD_stk_reg);
5388 %}
5389
5390 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5391 effect(DEF dst, USE src);
5392 ins_cost(MEMORY_REF_COST*2);
5393 size(8);
5394 format %{ "STW $src,$dst.hi\t! long\n\t"
5395 "STW R_G0,$dst.lo" %}
5396 opcode(Assembler::stw_op3);
5397 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5398 ins_pipe(lstoreI_stk_reg);
5399 %}
5400
5401 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5402 // No match rule to avoid chain rule match.
5403 effect(DEF dst, USE src);
5404 ins_cost(MEMORY_REF_COST);
5405 size(4);
5406 format %{ "STX $src,$dst\t! regL to stkD" %}
5407 opcode(Assembler::stx_op3);
5408 ins_encode(simple_form3_mem_reg( dst, src ) );
5409 ins_pipe(istore_stk_reg);
5410 %}
5411
5412 //---------- Chain stack slots between similar types --------
5413
5414 // Load integer from stack slot
5415 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5416 match(Set dst src);
5417 ins_cost(MEMORY_REF_COST);
5418
5419 size(4);
5420 format %{ "LDUW $src,$dst\t!stk" %}
5421 opcode(Assembler::lduw_op3);
5422 ins_encode(simple_form3_mem_reg( src, dst ) );
5423 ins_pipe(iload_mem);
5424 %}
5425
5426 // Store integer to stack slot
5427 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5428 match(Set dst src);
5429 ins_cost(MEMORY_REF_COST);
5430
5431 size(4);
5432 format %{ "STW $src,$dst\t!stk" %}
5433 opcode(Assembler::stw_op3);
5434 ins_encode(simple_form3_mem_reg( dst, src ) );
5435 ins_pipe(istore_mem_reg);
5436 %}
5437
5438 // Load long from stack slot
5439 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5440 match(Set dst src);
5441
5442 ins_cost(MEMORY_REF_COST);
5443 size(4);
5444 format %{ "LDX $src,$dst\t! long" %}
5445 opcode(Assembler::ldx_op3);
5446 ins_encode(simple_form3_mem_reg( src, dst ) );
5447 ins_pipe(iload_mem);
5448 %}
5449
5450 // Store long to stack slot
5451 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5452 match(Set dst src);
5453
5454 ins_cost(MEMORY_REF_COST);
5455 size(4);
5456 format %{ "STX $src,$dst\t! long" %}
5457 opcode(Assembler::stx_op3);
5458 ins_encode(simple_form3_mem_reg( dst, src ) );
5459 ins_pipe(istore_mem_reg);
5460 %}
5461
5462 #ifdef _LP64
5463 // Load pointer from stack slot, 64-bit encoding
5464 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5465 match(Set dst src);
5466 ins_cost(MEMORY_REF_COST);
5467 size(4);
5468 format %{ "LDX $src,$dst\t!ptr" %}
5469 opcode(Assembler::ldx_op3);
5470 ins_encode(simple_form3_mem_reg( src, dst ) );
5471 ins_pipe(iload_mem);
5472 %}
5473
5474 // Store pointer to stack slot
5475 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5476 match(Set dst src);
5477 ins_cost(MEMORY_REF_COST);
5478 size(4);
5479 format %{ "STX $src,$dst\t!ptr" %}
5480 opcode(Assembler::stx_op3);
5481 ins_encode(simple_form3_mem_reg( dst, src ) );
5482 ins_pipe(istore_mem_reg);
5483 %}
5484 #else // _LP64
5485 // Load pointer from stack slot, 32-bit encoding
5486 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5487 match(Set dst src);
5488 ins_cost(MEMORY_REF_COST);
5489 format %{ "LDUW $src,$dst\t!ptr" %}
5490 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5491 ins_encode(simple_form3_mem_reg( src, dst ) );
5492 ins_pipe(iload_mem);
5493 %}
5494
5495 // Store pointer to stack slot
5496 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5497 match(Set dst src);
5498 ins_cost(MEMORY_REF_COST);
5499 format %{ "STW $src,$dst\t!ptr" %}
5500 opcode(Assembler::stw_op3, Assembler::ldst_op);
5501 ins_encode(simple_form3_mem_reg( dst, src ) );
5502 ins_pipe(istore_mem_reg);
5503 %}
5504 #endif // _LP64
5505
5506 //------------Special Nop instructions for bundling - no match rules-----------
5507 // Nop using the A0 functional unit
5508 instruct Nop_A0() %{
5509 ins_cost(0);
5510
5511 format %{ "NOP ! Alu Pipeline" %}
5512 opcode(Assembler::or_op3, Assembler::arith_op);
5513 ins_encode( form2_nop() );
5514 ins_pipe(ialu_nop_A0);
5515 %}
5516
5517 // Nop using the A1 functional unit
5518 instruct Nop_A1( ) %{
5519 ins_cost(0);
5520
5521 format %{ "NOP ! Alu Pipeline" %}
5522 opcode(Assembler::or_op3, Assembler::arith_op);
5523 ins_encode( form2_nop() );
5524 ins_pipe(ialu_nop_A1);
5525 %}
5526
5527 // Nop using the memory functional unit
5528 instruct Nop_MS( ) %{
5529 ins_cost(0);
5530
5531 format %{ "NOP ! Memory Pipeline" %}
5532 ins_encode( emit_mem_nop );
5533 ins_pipe(mem_nop);
5534 %}
5535
5536 // Nop using the floating add functional unit
5537 instruct Nop_FA( ) %{
5538 ins_cost(0);
5539
5540 format %{ "NOP ! Floating Add Pipeline" %}
5541 ins_encode( emit_fadd_nop );
5542 ins_pipe(fadd_nop);
5543 %}
5544
5545 // Nop using the branch functional unit
5546 instruct Nop_BR( ) %{
5547 ins_cost(0);
5548
5549 format %{ "NOP ! Branch Pipeline" %}
5550 ins_encode( emit_br_nop );
5551 ins_pipe(br_nop);
5552 %}
5553
5554 //----------Load/Store/Move Instructions---------------------------------------
5555 //----------Load Instructions--------------------------------------------------
5556 // Load Byte (8bit signed)
5557 instruct loadB(iRegI dst, memory mem) %{
5558 match(Set dst (LoadB mem));
5559 ins_cost(MEMORY_REF_COST);
5560
5561 size(4);
5562 format %{ "LDSB $mem,$dst\t! byte" %}
5563 ins_encode %{
5564 __ ldsb($mem$$Address, $dst$$Register);
5565 %}
5566 ins_pipe(iload_mask_mem);
5567 %}
5568
5569 // Load Byte (8bit signed) into a Long Register
5570 instruct loadB2L(iRegL dst, memory mem) %{
5571 match(Set dst (ConvI2L (LoadB mem)));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 size(4);
5575 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5576 ins_encode %{
5577 __ ldsb($mem$$Address, $dst$$Register);
5578 %}
5579 ins_pipe(iload_mask_mem);
5580 %}
5581
5582 // Load Unsigned Byte (8bit UNsigned) into an int reg
5583 instruct loadUB(iRegI dst, memory mem) %{
5584 match(Set dst (LoadUB mem));
5585 ins_cost(MEMORY_REF_COST);
5586
5587 size(4);
5588 format %{ "LDUB $mem,$dst\t! ubyte" %}
5589 ins_encode %{
5590 __ ldub($mem$$Address, $dst$$Register);
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5596 instruct loadUB2L(iRegL dst, memory mem) %{
5597 match(Set dst (ConvI2L (LoadUB mem)));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 size(4);
5601 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5602 ins_encode %{
5603 __ ldub($mem$$Address, $dst$$Register);
5604 %}
5605 ins_pipe(iload_mem);
5606 %}
5607
5608 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5609 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5610 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5611 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5612
5613 size(2*4);
5614 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5615 "AND $dst,$mask,$dst" %}
5616 ins_encode %{
5617 __ ldub($mem$$Address, $dst$$Register);
5618 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5619 %}
5620 ins_pipe(iload_mem);
5621 %}
5622
5623 // Load Short (16bit signed)
5624 instruct loadS(iRegI dst, memory mem) %{
5625 match(Set dst (LoadS mem));
5626 ins_cost(MEMORY_REF_COST);
5627
5628 size(4);
5629 format %{ "LDSH $mem,$dst\t! short" %}
5630 ins_encode %{
5631 __ ldsh($mem$$Address, $dst$$Register);
5632 %}
5633 ins_pipe(iload_mask_mem);
5634 %}
5635
5636 // Load Short (16 bit signed) to Byte (8 bit signed)
5637 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5638 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5639 ins_cost(MEMORY_REF_COST);
5640
5641 size(4);
5642
5643 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5644 ins_encode %{
5645 __ ldsb($mem$$Address, $dst$$Register, 1);
5646 %}
5647 ins_pipe(iload_mask_mem);
5648 %}
5649
5650 // Load Short (16bit signed) into a Long Register
5651 instruct loadS2L(iRegL dst, memory mem) %{
5652 match(Set dst (ConvI2L (LoadS mem)));
5653 ins_cost(MEMORY_REF_COST);
5654
5655 size(4);
5656 format %{ "LDSH $mem,$dst\t! short -> long" %}
5657 ins_encode %{
5658 __ ldsh($mem$$Address, $dst$$Register);
5659 %}
5660 ins_pipe(iload_mask_mem);
5661 %}
5662
5663 // Load Unsigned Short/Char (16bit UNsigned)
5664 instruct loadUS(iRegI dst, memory mem) %{
5665 match(Set dst (LoadUS mem));
5666 ins_cost(MEMORY_REF_COST);
5667
5668 size(4);
5669 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5670 ins_encode %{
5671 __ lduh($mem$$Address, $dst$$Register);
5672 %}
5673 ins_pipe(iload_mem);
5674 %}
5675
5676 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5677 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5678 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5679 ins_cost(MEMORY_REF_COST);
5680
5681 size(4);
5682 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5683 ins_encode %{
5684 __ ldsb($mem$$Address, $dst$$Register, 1);
5685 %}
5686 ins_pipe(iload_mask_mem);
5687 %}
5688
5689 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5690 instruct loadUS2L(iRegL dst, memory mem) %{
5691 match(Set dst (ConvI2L (LoadUS mem)));
5692 ins_cost(MEMORY_REF_COST);
5693
5694 size(4);
5695 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5696 ins_encode %{
5697 __ lduh($mem$$Address, $dst$$Register);
5698 %}
5699 ins_pipe(iload_mem);
5700 %}
5701
5702 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5703 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5704 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5705 ins_cost(MEMORY_REF_COST);
5706
5707 size(4);
5708 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5709 ins_encode %{
5710 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5711 %}
5712 ins_pipe(iload_mem);
5713 %}
5714
5715 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5716 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5717 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5718 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5719
5720 size(2*4);
5721 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5722 "AND $dst,$mask,$dst" %}
5723 ins_encode %{
5724 Register Rdst = $dst$$Register;
5725 __ lduh($mem$$Address, Rdst);
5726 __ and3(Rdst, $mask$$constant, Rdst);
5727 %}
5728 ins_pipe(iload_mem);
5729 %}
5730
5731 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5732 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5733 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5734 effect(TEMP dst, TEMP tmp);
5735 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5736
5737 size((3+1)*4); // set may use two instructions.
5738 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5739 "SET $mask,$tmp\n\t"
5740 "AND $dst,$tmp,$dst" %}
5741 ins_encode %{
5742 Register Rdst = $dst$$Register;
5743 Register Rtmp = $tmp$$Register;
5744 __ lduh($mem$$Address, Rdst);
5745 __ set($mask$$constant, Rtmp);
5746 __ and3(Rdst, Rtmp, Rdst);
5747 %}
5748 ins_pipe(iload_mem);
5749 %}
5750
5751 // Load Integer
5752 instruct loadI(iRegI dst, memory mem) %{
5753 match(Set dst (LoadI mem));
5754 ins_cost(MEMORY_REF_COST);
5755
5756 size(4);
5757 format %{ "LDUW $mem,$dst\t! int" %}
5758 ins_encode %{
5759 __ lduw($mem$$Address, $dst$$Register);
5760 %}
5761 ins_pipe(iload_mem);
5762 %}
5763
5764 // Load Integer to Byte (8 bit signed)
5765 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5766 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5767 ins_cost(MEMORY_REF_COST);
5768
5769 size(4);
5770
5771 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5772 ins_encode %{
5773 __ ldsb($mem$$Address, $dst$$Register, 3);
5774 %}
5775 ins_pipe(iload_mask_mem);
5776 %}
5777
5778 // Load Integer to Unsigned Byte (8 bit UNsigned)
5779 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5780 match(Set dst (AndI (LoadI mem) mask));
5781 ins_cost(MEMORY_REF_COST);
5782
5783 size(4);
5784
5785 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5786 ins_encode %{
5787 __ ldub($mem$$Address, $dst$$Register, 3);
5788 %}
5789 ins_pipe(iload_mask_mem);
5790 %}
5791
5792 // Load Integer to Short (16 bit signed)
5793 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5794 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5795 ins_cost(MEMORY_REF_COST);
5796
5797 size(4);
5798
5799 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5800 ins_encode %{
5801 __ ldsh($mem$$Address, $dst$$Register, 2);
5802 %}
5803 ins_pipe(iload_mask_mem);
5804 %}
5805
5806 // Load Integer to Unsigned Short (16 bit UNsigned)
5807 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5808 match(Set dst (AndI (LoadI mem) mask));
5809 ins_cost(MEMORY_REF_COST);
5810
5811 size(4);
5812
5813 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5814 ins_encode %{
5815 __ lduh($mem$$Address, $dst$$Register, 2);
5816 %}
5817 ins_pipe(iload_mask_mem);
5818 %}
5819
5820 // Load Integer into a Long Register
5821 instruct loadI2L(iRegL dst, memory mem) %{
5822 match(Set dst (ConvI2L (LoadI mem)));
5823 ins_cost(MEMORY_REF_COST);
5824
5825 size(4);
5826 format %{ "LDSW $mem,$dst\t! int -> long" %}
5827 ins_encode %{
5828 __ ldsw($mem$$Address, $dst$$Register);
5829 %}
5830 ins_pipe(iload_mask_mem);
5831 %}
5832
5833 // Load Integer with mask 0xFF into a Long Register
5834 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5835 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5836 ins_cost(MEMORY_REF_COST);
5837
5838 size(4);
5839 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5840 ins_encode %{
5841 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5842 %}
5843 ins_pipe(iload_mem);
5844 %}
5845
5846 // Load Integer with mask 0xFFFF into a Long Register
5847 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5848 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5849 ins_cost(MEMORY_REF_COST);
5850
5851 size(4);
5852 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5853 ins_encode %{
5854 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5855 %}
5856 ins_pipe(iload_mem);
5857 %}
5858
5859 // Load Integer with a 13-bit mask into a Long Register
5860 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5861 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5862 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5863
5864 size(2*4);
5865 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5866 "AND $dst,$mask,$dst" %}
5867 ins_encode %{
5868 Register Rdst = $dst$$Register;
5869 __ lduw($mem$$Address, Rdst);
5870 __ and3(Rdst, $mask$$constant, Rdst);
5871 %}
5872 ins_pipe(iload_mem);
5873 %}
5874
5875 // Load Integer with a 32-bit mask into a Long Register
5876 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5877 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5878 effect(TEMP dst, TEMP tmp);
5879 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5880
5881 size((3+1)*4); // set may use two instructions.
5882 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5883 "SET $mask,$tmp\n\t"
5884 "AND $dst,$tmp,$dst" %}
5885 ins_encode %{
5886 Register Rdst = $dst$$Register;
5887 Register Rtmp = $tmp$$Register;
5888 __ lduw($mem$$Address, Rdst);
5889 __ set($mask$$constant, Rtmp);
5890 __ and3(Rdst, Rtmp, Rdst);
5891 %}
5892 ins_pipe(iload_mem);
5893 %}
5894
5895 // Load Unsigned Integer into a Long Register
5896 instruct loadUI2L(iRegL dst, memory mem) %{
5897 match(Set dst (LoadUI2L mem));
5898 ins_cost(MEMORY_REF_COST);
5899
5900 size(4);
5901 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5902 ins_encode %{
5903 __ lduw($mem$$Address, $dst$$Register);
5904 %}
5905 ins_pipe(iload_mem);
5906 %}
5907
5908 // Load Long - aligned
5909 instruct loadL(iRegL dst, memory mem ) %{
5910 match(Set dst (LoadL mem));
5911 ins_cost(MEMORY_REF_COST);
5912
5913 size(4);
5914 format %{ "LDX $mem,$dst\t! long" %}
5915 ins_encode %{
5916 __ ldx($mem$$Address, $dst$$Register);
5917 %}
5918 ins_pipe(iload_mem);
5919 %}
5920
5921 // Load Long - UNaligned
5922 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5923 match(Set dst (LoadL_unaligned mem));
5924 effect(KILL tmp);
5925 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5926 size(16);
5927 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5928 "\tLDUW $mem ,$dst\n"
5929 "\tSLLX #32, $dst, $dst\n"
5930 "\tOR $dst, R_O7, $dst" %}
5931 opcode(Assembler::lduw_op3);
5932 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5933 ins_pipe(iload_mem);
5934 %}
5935
5936 // Load Aligned Packed Byte into a Double Register
5937 instruct loadA8B(regD dst, memory mem) %{
5938 match(Set dst (Load8B mem));
5939 ins_cost(MEMORY_REF_COST);
5940 size(4);
5941 format %{ "LDDF $mem,$dst\t! packed8B" %}
5942 opcode(Assembler::lddf_op3);
5943 ins_encode(simple_form3_mem_reg( mem, dst ) );
5944 ins_pipe(floadD_mem);
5945 %}
5946
5947 // Load Aligned Packed Char into a Double Register
5948 instruct loadA4C(regD dst, memory mem) %{
5949 match(Set dst (Load4C mem));
5950 ins_cost(MEMORY_REF_COST);
5951 size(4);
5952 format %{ "LDDF $mem,$dst\t! packed4C" %}
5953 opcode(Assembler::lddf_op3);
5954 ins_encode(simple_form3_mem_reg( mem, dst ) );
5955 ins_pipe(floadD_mem);
5956 %}
5957
5958 // Load Aligned Packed Short into a Double Register
5959 instruct loadA4S(regD dst, memory mem) %{
5960 match(Set dst (Load4S mem));
5961 ins_cost(MEMORY_REF_COST);
5962 size(4);
5963 format %{ "LDDF $mem,$dst\t! packed4S" %}
5964 opcode(Assembler::lddf_op3);
5965 ins_encode(simple_form3_mem_reg( mem, dst ) );
5966 ins_pipe(floadD_mem);
5967 %}
5968
5969 // Load Aligned Packed Int into a Double Register
5970 instruct loadA2I(regD dst, memory mem) %{
5971 match(Set dst (Load2I mem));
5972 ins_cost(MEMORY_REF_COST);
5973 size(4);
5974 format %{ "LDDF $mem,$dst\t! packed2I" %}
5975 opcode(Assembler::lddf_op3);
5976 ins_encode(simple_form3_mem_reg( mem, dst ) );
5977 ins_pipe(floadD_mem);
5978 %}
5979
5980 // Load Range
5981 instruct loadRange(iRegI dst, memory mem) %{
5982 match(Set dst (LoadRange mem));
5983 ins_cost(MEMORY_REF_COST);
5984
5985 size(4);
5986 format %{ "LDUW $mem,$dst\t! range" %}
5987 opcode(Assembler::lduw_op3);
5988 ins_encode(simple_form3_mem_reg( mem, dst ) );
5989 ins_pipe(iload_mem);
5990 %}
5991
5992 // Load Integer into %f register (for fitos/fitod)
5993 instruct loadI_freg(regF dst, memory mem) %{
5994 match(Set dst (LoadI mem));
5995 ins_cost(MEMORY_REF_COST);
5996 size(4);
5997
5998 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5999 opcode(Assembler::ldf_op3);
6000 ins_encode(simple_form3_mem_reg( mem, dst ) );
6001 ins_pipe(floadF_mem);
6002 %}
6003
6004 // Load Pointer
6005 instruct loadP(iRegP dst, memory mem) %{
6006 match(Set dst (LoadP mem));
6007 ins_cost(MEMORY_REF_COST);
6008 size(4);
6009
6010 #ifndef _LP64
6011 format %{ "LDUW $mem,$dst\t! ptr" %}
6012 ins_encode %{
6013 __ lduw($mem$$Address, $dst$$Register);
6014 %}
6015 #else
6016 format %{ "LDX $mem,$dst\t! ptr" %}
6017 ins_encode %{
6018 __ ldx($mem$$Address, $dst$$Register);
6019 %}
6020 #endif
6021 ins_pipe(iload_mem);
6022 %}
6023
6024 // Load Compressed Pointer
6025 instruct loadN(iRegN dst, memory mem) %{
6026 match(Set dst (LoadN mem));
6027 ins_cost(MEMORY_REF_COST);
6028 size(4);
6029
6030 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6031 ins_encode %{
6032 __ lduw($mem$$Address, $dst$$Register);
6033 %}
6034 ins_pipe(iload_mem);
6035 %}
6036
6037 // Load Klass Pointer
6038 instruct loadKlass(iRegP dst, memory mem) %{
6039 match(Set dst (LoadKlass mem));
6040 ins_cost(MEMORY_REF_COST);
6041 size(4);
6042
6043 #ifndef _LP64
6044 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6045 ins_encode %{
6046 __ lduw($mem$$Address, $dst$$Register);
6047 %}
6048 #else
6049 format %{ "LDX $mem,$dst\t! klass ptr" %}
6050 ins_encode %{
6051 __ ldx($mem$$Address, $dst$$Register);
6052 %}
6053 #endif
6054 ins_pipe(iload_mem);
6055 %}
6056
6057 // Load narrow Klass Pointer
6058 instruct loadNKlass(iRegN dst, memory mem) %{
6059 match(Set dst (LoadNKlass mem));
6060 ins_cost(MEMORY_REF_COST);
6061 size(4);
6062
6063 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6064 ins_encode %{
6065 __ lduw($mem$$Address, $dst$$Register);
6066 %}
6067 ins_pipe(iload_mem);
6068 %}
6069
6070 // Load Double
6071 instruct loadD(regD dst, memory mem) %{
6072 match(Set dst (LoadD mem));
6073 ins_cost(MEMORY_REF_COST);
6074
6075 size(4);
6076 format %{ "LDDF $mem,$dst" %}
6077 opcode(Assembler::lddf_op3);
6078 ins_encode(simple_form3_mem_reg( mem, dst ) );
6079 ins_pipe(floadD_mem);
6080 %}
6081
6082 // Load Double - UNaligned
6083 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6084 match(Set dst (LoadD_unaligned mem));
6085 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6086 size(8);
6087 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6088 "\tLDF $mem+4,$dst.lo\t!" %}
6089 opcode(Assembler::ldf_op3);
6090 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6091 ins_pipe(iload_mem);
6092 %}
6093
6094 // Load Float
6095 instruct loadF(regF dst, memory mem) %{
6096 match(Set dst (LoadF mem));
6097 ins_cost(MEMORY_REF_COST);
6098
6099 size(4);
6100 format %{ "LDF $mem,$dst" %}
6101 opcode(Assembler::ldf_op3);
6102 ins_encode(simple_form3_mem_reg( mem, dst ) );
6103 ins_pipe(floadF_mem);
6104 %}
6105
6106 // Load Constant
6107 instruct loadConI( iRegI dst, immI src ) %{
6108 match(Set dst src);
6109 ins_cost(DEFAULT_COST * 3/2);
6110 format %{ "SET $src,$dst" %}
6111 ins_encode( Set32(src, dst) );
6112 ins_pipe(ialu_hi_lo_reg);
6113 %}
6114
6115 instruct loadConI13( iRegI dst, immI13 src ) %{
6116 match(Set dst src);
6117
6118 size(4);
6119 format %{ "MOV $src,$dst" %}
6120 ins_encode( Set13( src, dst ) );
6121 ins_pipe(ialu_imm);
6122 %}
6123
6124 #ifndef _LP64
6125 instruct loadConP(iRegP dst, immP con) %{
6126 match(Set dst con);
6127 ins_cost(DEFAULT_COST * 3/2);
6128 format %{ "SET $con,$dst\t!ptr" %}
6129 ins_encode %{
6130 // [RGV] This next line should be generated from ADLC
6131 if (_opnds[1]->constant_is_oop()) {
6132 intptr_t val = $con$$constant;
6133 __ set_oop_constant((jobject) val, $dst$$Register);
6134 } else { // non-oop pointers, e.g. card mark base, heap top
6135 __ set($con$$constant, $dst$$Register);
6136 }
6137 %}
6138 ins_pipe(loadConP);
6139 %}
6140 #else
6141 instruct loadConP_set(iRegP dst, immP_set con) %{
6142 match(Set dst con);
6143 ins_cost(DEFAULT_COST * 3/2);
6144 format %{ "SET $con,$dst\t! ptr" %}
6145 ins_encode %{
6146 // [RGV] This next line should be generated from ADLC
6147 if (_opnds[1]->constant_is_oop()) {
6148 intptr_t val = $con$$constant;
6149 __ set_oop_constant((jobject) val, $dst$$Register);
6150 } else { // non-oop pointers, e.g. card mark base, heap top
6151 __ set($con$$constant, $dst$$Register);
6152 }
6153 %}
6154 ins_pipe(loadConP);
6155 %}
6156
6157 instruct loadConP_load(iRegP dst, immP_load con) %{
6158 match(Set dst con);
6159 ins_cost(MEMORY_REF_COST);
6160 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6161 ins_encode %{
6162 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6163 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6164 %}
6165 ins_pipe(loadConP);
6166 %}
6167
6168 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6169 match(Set dst con);
6170 ins_cost(DEFAULT_COST * 3/2);
6171 format %{ "SET $con,$dst\t! non-oop ptr" %}
6172 ins_encode %{
6173 __ set($con$$constant, $dst$$Register);
6174 %}
6175 ins_pipe(loadConP);
6176 %}
6177 #endif // _LP64
6178
6179 instruct loadConP0(iRegP dst, immP0 src) %{
6180 match(Set dst src);
6181
6182 size(4);
6183 format %{ "CLR $dst\t!ptr" %}
6184 ins_encode %{
6185 __ clr($dst$$Register);
6186 %}
6187 ins_pipe(ialu_imm);
6188 %}
6189
6190 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6191 match(Set dst src);
6192 ins_cost(DEFAULT_COST);
6193 format %{ "SET $src,$dst\t!ptr" %}
6194 ins_encode %{
6195 AddressLiteral polling_page(os::get_polling_page());
6196 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6197 %}
6198 ins_pipe(loadConP_poll);
6199 %}
6200
6201 instruct loadConN0(iRegN dst, immN0 src) %{
6202 match(Set dst src);
6203
6204 size(4);
6205 format %{ "CLR $dst\t! compressed NULL ptr" %}
6206 ins_encode %{
6207 __ clr($dst$$Register);
6208 %}
6209 ins_pipe(ialu_imm);
6210 %}
6211
6212 instruct loadConN(iRegN dst, immN src) %{
6213 match(Set dst src);
6214 ins_cost(DEFAULT_COST * 3/2);
6215 format %{ "SET $src,$dst\t! compressed ptr" %}
6216 ins_encode %{
6217 Register dst = $dst$$Register;
6218 __ set_narrow_oop((jobject)$src$$constant, dst);
6219 %}
6220 ins_pipe(ialu_hi_lo_reg);
6221 %}
6222
6223 // Materialize long value (predicated by immL_cheap).
6224 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6225 match(Set dst con);
6226 effect(KILL tmp);
6227 ins_cost(DEFAULT_COST * 3);
6228 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6229 ins_encode %{
6230 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6231 %}
6232 ins_pipe(loadConL);
6233 %}
6234
6235 // Load long value from constant table (predicated by immL_expensive).
6236 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6237 match(Set dst con);
6238 ins_cost(MEMORY_REF_COST);
6239 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6240 ins_encode %{
6241 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6242 __ ldx($constanttablebase, con_offset, $dst$$Register);
6243 %}
6244 ins_pipe(loadConL);
6245 %}
6246
6247 instruct loadConL0( iRegL dst, immL0 src ) %{
6248 match(Set dst src);
6249 ins_cost(DEFAULT_COST);
6250 size(4);
6251 format %{ "CLR $dst\t! long" %}
6252 ins_encode( Set13( src, dst ) );
6253 ins_pipe(ialu_imm);
6254 %}
6255
6256 instruct loadConL13( iRegL dst, immL13 src ) %{
6257 match(Set dst src);
6258 ins_cost(DEFAULT_COST * 2);
6259
6260 size(4);
6261 format %{ "MOV $src,$dst\t! long" %}
6262 ins_encode( Set13( src, dst ) );
6263 ins_pipe(ialu_imm);
6264 %}
6265
6266 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6267 match(Set dst con);
6268 effect(KILL tmp);
6269 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6270 ins_encode %{
6271 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6272 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6273 %}
6274 ins_pipe(loadConFD);
6275 %}
6276
6277 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6278 match(Set dst con);
6279 effect(KILL tmp);
6280 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6281 ins_encode %{
6282 // XXX This is a quick fix for 6833573.
6283 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6284 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6285 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6286 %}
6287 ins_pipe(loadConFD);
6288 %}
6289
6290 // Prefetch instructions.
6291 // Must be safe to execute with invalid address (cannot fault).
6292
6293 instruct prefetchr( memory mem ) %{
6294 match( PrefetchRead mem );
6295 ins_cost(MEMORY_REF_COST);
6296 size(4);
6297
6298 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6299 opcode(Assembler::prefetch_op3);
6300 ins_encode( form3_mem_prefetch_read( mem ) );
6301 ins_pipe(iload_mem);
6302 %}
6303
6304 instruct prefetchw( memory mem ) %{
6305 match( PrefetchWrite mem );
6306 ins_cost(MEMORY_REF_COST);
6307 size(4);
6308
6309 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6310 opcode(Assembler::prefetch_op3);
6311 ins_encode( form3_mem_prefetch_write( mem ) );
6312 ins_pipe(iload_mem);
6313 %}
6314
6315 // Prefetch instructions for allocation.
6316
6317 instruct prefetchAlloc( memory mem ) %{
6318 predicate(AllocatePrefetchInstr == 0);
6319 match( PrefetchAllocation mem );
6320 ins_cost(MEMORY_REF_COST);
6321 size(4);
6322
6323 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6324 opcode(Assembler::prefetch_op3);
6325 ins_encode( form3_mem_prefetch_write( mem ) );
6326 ins_pipe(iload_mem);
6327 %}
6328
6329 // Use BIS instruction to prefetch for allocation.
6330 // Could fault, need space at the end of TLAB.
6331 instruct prefetchAlloc_bis( iRegP dst ) %{
6332 predicate(AllocatePrefetchInstr == 1);
6333 match( PrefetchAllocation dst );
6334 ins_cost(MEMORY_REF_COST);
6335 size(4);
6336
6337 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6338 ins_encode %{
6339 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6340 %}
6341 ins_pipe(istore_mem_reg);
6342 %}
6343
6344 // Next code is used for finding next cache line address to prefetch.
6345 #ifndef _LP64
6346 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6347 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6348 ins_cost(DEFAULT_COST);
6349 size(4);
6350
6351 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6352 ins_encode %{
6353 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6354 %}
6355 ins_pipe(ialu_reg_imm);
6356 %}
6357 #else
6358 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6359 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6360 ins_cost(DEFAULT_COST);
6361 size(4);
6362
6363 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6364 ins_encode %{
6365 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6366 %}
6367 ins_pipe(ialu_reg_imm);
6368 %}
6369 #endif
6370
6371 //----------Store Instructions-------------------------------------------------
6372 // Store Byte
6373 instruct storeB(memory mem, iRegI src) %{
6374 match(Set mem (StoreB mem src));
6375 ins_cost(MEMORY_REF_COST);
6376
6377 size(4);
6378 format %{ "STB $src,$mem\t! byte" %}
6379 opcode(Assembler::stb_op3);
6380 ins_encode(simple_form3_mem_reg( mem, src ) );
6381 ins_pipe(istore_mem_reg);
6382 %}
6383
6384 instruct storeB0(memory mem, immI0 src) %{
6385 match(Set mem (StoreB mem src));
6386 ins_cost(MEMORY_REF_COST);
6387
6388 size(4);
6389 format %{ "STB $src,$mem\t! byte" %}
6390 opcode(Assembler::stb_op3);
6391 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6392 ins_pipe(istore_mem_zero);
6393 %}
6394
6395 instruct storeCM0(memory mem, immI0 src) %{
6396 match(Set mem (StoreCM mem src));
6397 ins_cost(MEMORY_REF_COST);
6398
6399 size(4);
6400 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6401 opcode(Assembler::stb_op3);
6402 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6403 ins_pipe(istore_mem_zero);
6404 %}
6405
6406 // Store Char/Short
6407 instruct storeC(memory mem, iRegI src) %{
6408 match(Set mem (StoreC mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 size(4);
6412 format %{ "STH $src,$mem\t! short" %}
6413 opcode(Assembler::sth_op3);
6414 ins_encode(simple_form3_mem_reg( mem, src ) );
6415 ins_pipe(istore_mem_reg);
6416 %}
6417
6418 instruct storeC0(memory mem, immI0 src) %{
6419 match(Set mem (StoreC mem src));
6420 ins_cost(MEMORY_REF_COST);
6421
6422 size(4);
6423 format %{ "STH $src,$mem\t! short" %}
6424 opcode(Assembler::sth_op3);
6425 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6426 ins_pipe(istore_mem_zero);
6427 %}
6428
6429 // Store Integer
6430 instruct storeI(memory mem, iRegI src) %{
6431 match(Set mem (StoreI mem src));
6432 ins_cost(MEMORY_REF_COST);
6433
6434 size(4);
6435 format %{ "STW $src,$mem" %}
6436 opcode(Assembler::stw_op3);
6437 ins_encode(simple_form3_mem_reg( mem, src ) );
6438 ins_pipe(istore_mem_reg);
6439 %}
6440
6441 // Store Long
6442 instruct storeL(memory mem, iRegL src) %{
6443 match(Set mem (StoreL mem src));
6444 ins_cost(MEMORY_REF_COST);
6445 size(4);
6446 format %{ "STX $src,$mem\t! long" %}
6447 opcode(Assembler::stx_op3);
6448 ins_encode(simple_form3_mem_reg( mem, src ) );
6449 ins_pipe(istore_mem_reg);
6450 %}
6451
6452 instruct storeI0(memory mem, immI0 src) %{
6453 match(Set mem (StoreI mem src));
6454 ins_cost(MEMORY_REF_COST);
6455
6456 size(4);
6457 format %{ "STW $src,$mem" %}
6458 opcode(Assembler::stw_op3);
6459 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6460 ins_pipe(istore_mem_zero);
6461 %}
6462
6463 instruct storeL0(memory mem, immL0 src) %{
6464 match(Set mem (StoreL mem src));
6465 ins_cost(MEMORY_REF_COST);
6466
6467 size(4);
6468 format %{ "STX $src,$mem" %}
6469 opcode(Assembler::stx_op3);
6470 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6471 ins_pipe(istore_mem_zero);
6472 %}
6473
6474 // Store Integer from float register (used after fstoi)
6475 instruct storeI_Freg(memory mem, regF src) %{
6476 match(Set mem (StoreI mem src));
6477 ins_cost(MEMORY_REF_COST);
6478
6479 size(4);
6480 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6481 opcode(Assembler::stf_op3);
6482 ins_encode(simple_form3_mem_reg( mem, src ) );
6483 ins_pipe(fstoreF_mem_reg);
6484 %}
6485
6486 // Store Pointer
6487 instruct storeP(memory dst, sp_ptr_RegP src) %{
6488 match(Set dst (StoreP dst src));
6489 ins_cost(MEMORY_REF_COST);
6490 size(4);
6491
6492 #ifndef _LP64
6493 format %{ "STW $src,$dst\t! ptr" %}
6494 opcode(Assembler::stw_op3, 0, REGP_OP);
6495 #else
6496 format %{ "STX $src,$dst\t! ptr" %}
6497 opcode(Assembler::stx_op3, 0, REGP_OP);
6498 #endif
6499 ins_encode( form3_mem_reg( dst, src ) );
6500 ins_pipe(istore_mem_spORreg);
6501 %}
6502
6503 instruct storeP0(memory dst, immP0 src) %{
6504 match(Set dst (StoreP dst src));
6505 ins_cost(MEMORY_REF_COST);
6506 size(4);
6507
6508 #ifndef _LP64
6509 format %{ "STW $src,$dst\t! ptr" %}
6510 opcode(Assembler::stw_op3, 0, REGP_OP);
6511 #else
6512 format %{ "STX $src,$dst\t! ptr" %}
6513 opcode(Assembler::stx_op3, 0, REGP_OP);
6514 #endif
6515 ins_encode( form3_mem_reg( dst, R_G0 ) );
6516 ins_pipe(istore_mem_zero);
6517 %}
6518
6519 // Store Compressed Pointer
6520 instruct storeN(memory dst, iRegN src) %{
6521 match(Set dst (StoreN dst src));
6522 ins_cost(MEMORY_REF_COST);
6523 size(4);
6524
6525 format %{ "STW $src,$dst\t! compressed ptr" %}
6526 ins_encode %{
6527 Register base = as_Register($dst$$base);
6528 Register index = as_Register($dst$$index);
6529 Register src = $src$$Register;
6530 if (index != G0) {
6531 __ stw(src, base, index);
6532 } else {
6533 __ stw(src, base, $dst$$disp);
6534 }
6535 %}
6536 ins_pipe(istore_mem_spORreg);
6537 %}
6538
6539 instruct storeN0(memory dst, immN0 src) %{
6540 match(Set dst (StoreN dst src));
6541 ins_cost(MEMORY_REF_COST);
6542 size(4);
6543
6544 format %{ "STW $src,$dst\t! compressed ptr" %}
6545 ins_encode %{
6546 Register base = as_Register($dst$$base);
6547 Register index = as_Register($dst$$index);
6548 if (index != G0) {
6549 __ stw(0, base, index);
6550 } else {
6551 __ stw(0, base, $dst$$disp);
6552 }
6553 %}
6554 ins_pipe(istore_mem_zero);
6555 %}
6556
6557 // Store Double
6558 instruct storeD( memory mem, regD src) %{
6559 match(Set mem (StoreD mem src));
6560 ins_cost(MEMORY_REF_COST);
6561
6562 size(4);
6563 format %{ "STDF $src,$mem" %}
6564 opcode(Assembler::stdf_op3);
6565 ins_encode(simple_form3_mem_reg( mem, src ) );
6566 ins_pipe(fstoreD_mem_reg);
6567 %}
6568
6569 instruct storeD0( memory mem, immD0 src) %{
6570 match(Set mem (StoreD mem src));
6571 ins_cost(MEMORY_REF_COST);
6572
6573 size(4);
6574 format %{ "STX $src,$mem" %}
6575 opcode(Assembler::stx_op3);
6576 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6577 ins_pipe(fstoreD_mem_zero);
6578 %}
6579
6580 // Store Float
6581 instruct storeF( memory mem, regF src) %{
6582 match(Set mem (StoreF mem src));
6583 ins_cost(MEMORY_REF_COST);
6584
6585 size(4);
6586 format %{ "STF $src,$mem" %}
6587 opcode(Assembler::stf_op3);
6588 ins_encode(simple_form3_mem_reg( mem, src ) );
6589 ins_pipe(fstoreF_mem_reg);
6590 %}
6591
6592 instruct storeF0( memory mem, immF0 src) %{
6593 match(Set mem (StoreF mem src));
6594 ins_cost(MEMORY_REF_COST);
6595
6596 size(4);
6597 format %{ "STW $src,$mem\t! storeF0" %}
6598 opcode(Assembler::stw_op3);
6599 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6600 ins_pipe(fstoreF_mem_zero);
6601 %}
6602
6603 // Store Aligned Packed Bytes in Double register to memory
6604 instruct storeA8B(memory mem, regD src) %{
6605 match(Set mem (Store8B mem src));
6606 ins_cost(MEMORY_REF_COST);
6607 size(4);
6608 format %{ "STDF $src,$mem\t! packed8B" %}
6609 opcode(Assembler::stdf_op3);
6610 ins_encode(simple_form3_mem_reg( mem, src ) );
6611 ins_pipe(fstoreD_mem_reg);
6612 %}
6613
6614 // Convert oop pointer into compressed form
6615 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6616 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6617 match(Set dst (EncodeP src));
6618 format %{ "encode_heap_oop $src, $dst" %}
6619 ins_encode %{
6620 __ encode_heap_oop($src$$Register, $dst$$Register);
6621 %}
6622 ins_pipe(ialu_reg);
6623 %}
6624
6625 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6626 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6627 match(Set dst (EncodeP src));
6628 format %{ "encode_heap_oop_not_null $src, $dst" %}
6629 ins_encode %{
6630 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6631 %}
6632 ins_pipe(ialu_reg);
6633 %}
6634
6635 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6636 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6637 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6638 match(Set dst (DecodeN src));
6639 format %{ "decode_heap_oop $src, $dst" %}
6640 ins_encode %{
6641 __ decode_heap_oop($src$$Register, $dst$$Register);
6642 %}
6643 ins_pipe(ialu_reg);
6644 %}
6645
6646 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6647 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6648 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6649 match(Set dst (DecodeN src));
6650 format %{ "decode_heap_oop_not_null $src, $dst" %}
6651 ins_encode %{
6652 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6653 %}
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657
6658 // Store Zero into Aligned Packed Bytes
6659 instruct storeA8B0(memory mem, immI0 zero) %{
6660 match(Set mem (Store8B mem zero));
6661 ins_cost(MEMORY_REF_COST);
6662 size(4);
6663 format %{ "STX $zero,$mem\t! packed8B" %}
6664 opcode(Assembler::stx_op3);
6665 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6666 ins_pipe(fstoreD_mem_zero);
6667 %}
6668
6669 // Store Aligned Packed Chars/Shorts in Double register to memory
6670 instruct storeA4C(memory mem, regD src) %{
6671 match(Set mem (Store4C mem src));
6672 ins_cost(MEMORY_REF_COST);
6673 size(4);
6674 format %{ "STDF $src,$mem\t! packed4C" %}
6675 opcode(Assembler::stdf_op3);
6676 ins_encode(simple_form3_mem_reg( mem, src ) );
6677 ins_pipe(fstoreD_mem_reg);
6678 %}
6679
6680 // Store Zero into Aligned Packed Chars/Shorts
6681 instruct storeA4C0(memory mem, immI0 zero) %{
6682 match(Set mem (Store4C mem (Replicate4C zero)));
6683 ins_cost(MEMORY_REF_COST);
6684 size(4);
6685 format %{ "STX $zero,$mem\t! packed4C" %}
6686 opcode(Assembler::stx_op3);
6687 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6688 ins_pipe(fstoreD_mem_zero);
6689 %}
6690
6691 // Store Aligned Packed Ints in Double register to memory
6692 instruct storeA2I(memory mem, regD src) %{
6693 match(Set mem (Store2I mem src));
6694 ins_cost(MEMORY_REF_COST);
6695 size(4);
6696 format %{ "STDF $src,$mem\t! packed2I" %}
6697 opcode(Assembler::stdf_op3);
6698 ins_encode(simple_form3_mem_reg( mem, src ) );
6699 ins_pipe(fstoreD_mem_reg);
6700 %}
6701
6702 // Store Zero into Aligned Packed Ints
6703 instruct storeA2I0(memory mem, immI0 zero) %{
6704 match(Set mem (Store2I mem zero));
6705 ins_cost(MEMORY_REF_COST);
6706 size(4);
6707 format %{ "STX $zero,$mem\t! packed2I" %}
6708 opcode(Assembler::stx_op3);
6709 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6710 ins_pipe(fstoreD_mem_zero);
6711 %}
6712
6713
6714 //----------MemBar Instructions-----------------------------------------------
6715 // Memory barrier flavors
6716
6717 instruct membar_acquire() %{
6718 match(MemBarAcquire);
6719 ins_cost(4*MEMORY_REF_COST);
6720
6721 size(0);
6722 format %{ "MEMBAR-acquire" %}
6723 ins_encode( enc_membar_acquire );
6724 ins_pipe(long_memory_op);
6725 %}
6726
6727 instruct membar_acquire_lock() %{
6728 match(MemBarAcquireLock);
6729 ins_cost(0);
6730
6731 size(0);
6732 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6733 ins_encode( );
6734 ins_pipe(empty);
6735 %}
6736
6737 instruct membar_release() %{
6738 match(MemBarRelease);
6739 ins_cost(4*MEMORY_REF_COST);
6740
6741 size(0);
6742 format %{ "MEMBAR-release" %}
6743 ins_encode( enc_membar_release );
6744 ins_pipe(long_memory_op);
6745 %}
6746
6747 instruct membar_release_lock() %{
6748 match(MemBarReleaseLock);
6749 ins_cost(0);
6750
6751 size(0);
6752 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6753 ins_encode( );
6754 ins_pipe(empty);
6755 %}
6756
6757 instruct membar_volatile() %{
6758 match(MemBarVolatile);
6759 ins_cost(4*MEMORY_REF_COST);
6760
6761 size(4);
6762 format %{ "MEMBAR-volatile" %}
6763 ins_encode( enc_membar_volatile );
6764 ins_pipe(long_memory_op);
6765 %}
6766
6767 instruct unnecessary_membar_volatile() %{
6768 match(MemBarVolatile);
6769 predicate(Matcher::post_store_load_barrier(n));
6770 ins_cost(0);
6771
6772 size(0);
6773 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6774 ins_encode( );
6775 ins_pipe(empty);
6776 %}
6777
6778 instruct membar_storestore() %{
6779 match(MemBarStoreStore);
6780 ins_cost(0);
6781
6782 size(0);
6783 format %{ "!MEMBAR-storestore (empty encoding)" %}
6784 ins_encode( );
6785 ins_pipe(empty);
6786 %}
6787
6788 //----------Register Move Instructions-----------------------------------------
6789 instruct roundDouble_nop(regD dst) %{
6790 match(Set dst (RoundDouble dst));
6791 ins_cost(0);
6792 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6793 ins_encode( );
6794 ins_pipe(empty);
6795 %}
6796
6797
6798 instruct roundFloat_nop(regF dst) %{
6799 match(Set dst (RoundFloat dst));
6800 ins_cost(0);
6801 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6802 ins_encode( );
6803 ins_pipe(empty);
6804 %}
6805
6806
6807 // Cast Index to Pointer for unsafe natives
6808 instruct castX2P(iRegX src, iRegP dst) %{
6809 match(Set dst (CastX2P src));
6810
6811 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6812 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6813 ins_pipe(ialu_reg);
6814 %}
6815
6816 // Cast Pointer to Index for unsafe natives
6817 instruct castP2X(iRegP src, iRegX dst) %{
6818 match(Set dst (CastP2X src));
6819
6820 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6821 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6822 ins_pipe(ialu_reg);
6823 %}
6824
6825 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6826 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6827 match(Set stkSlot src); // chain rule
6828 ins_cost(MEMORY_REF_COST);
6829 format %{ "STDF $src,$stkSlot\t!stk" %}
6830 opcode(Assembler::stdf_op3);
6831 ins_encode(simple_form3_mem_reg(stkSlot, src));
6832 ins_pipe(fstoreD_stk_reg);
6833 %}
6834
6835 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6836 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6837 match(Set dst stkSlot); // chain rule
6838 ins_cost(MEMORY_REF_COST);
6839 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6840 opcode(Assembler::lddf_op3);
6841 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6842 ins_pipe(floadD_stk);
6843 %}
6844
6845 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6846 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6847 match(Set stkSlot src); // chain rule
6848 ins_cost(MEMORY_REF_COST);
6849 format %{ "STF $src,$stkSlot\t!stk" %}
6850 opcode(Assembler::stf_op3);
6851 ins_encode(simple_form3_mem_reg(stkSlot, src));
6852 ins_pipe(fstoreF_stk_reg);
6853 %}
6854
6855 //----------Conditional Move---------------------------------------------------
6856 // Conditional move
6857 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6858 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6859 ins_cost(150);
6860 format %{ "MOV$cmp $pcc,$src,$dst" %}
6861 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6862 ins_pipe(ialu_reg);
6863 %}
6864
6865 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6866 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6867 ins_cost(140);
6868 format %{ "MOV$cmp $pcc,$src,$dst" %}
6869 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6870 ins_pipe(ialu_imm);
6871 %}
6872
6873 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6874 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6875 ins_cost(150);
6876 size(4);
6877 format %{ "MOV$cmp $icc,$src,$dst" %}
6878 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6879 ins_pipe(ialu_reg);
6880 %}
6881
6882 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6883 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6884 ins_cost(140);
6885 size(4);
6886 format %{ "MOV$cmp $icc,$src,$dst" %}
6887 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6888 ins_pipe(ialu_imm);
6889 %}
6890
6891 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6892 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6893 ins_cost(150);
6894 size(4);
6895 format %{ "MOV$cmp $icc,$src,$dst" %}
6896 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6897 ins_pipe(ialu_reg);
6898 %}
6899
6900 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6901 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6902 ins_cost(140);
6903 size(4);
6904 format %{ "MOV$cmp $icc,$src,$dst" %}
6905 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6906 ins_pipe(ialu_imm);
6907 %}
6908
6909 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6910 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6911 ins_cost(150);
6912 size(4);
6913 format %{ "MOV$cmp $fcc,$src,$dst" %}
6914 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6915 ins_pipe(ialu_reg);
6916 %}
6917
6918 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6919 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6920 ins_cost(140);
6921 size(4);
6922 format %{ "MOV$cmp $fcc,$src,$dst" %}
6923 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6924 ins_pipe(ialu_imm);
6925 %}
6926
6927 // Conditional move for RegN. Only cmov(reg,reg).
6928 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6929 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6930 ins_cost(150);
6931 format %{ "MOV$cmp $pcc,$src,$dst" %}
6932 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6933 ins_pipe(ialu_reg);
6934 %}
6935
6936 // This instruction also works with CmpN so we don't need cmovNN_reg.
6937 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6938 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6939 ins_cost(150);
6940 size(4);
6941 format %{ "MOV$cmp $icc,$src,$dst" %}
6942 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(ialu_reg);
6944 %}
6945
6946 // This instruction also works with CmpN so we don't need cmovNN_reg.
6947 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6948 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6949 ins_cost(150);
6950 size(4);
6951 format %{ "MOV$cmp $icc,$src,$dst" %}
6952 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6953 ins_pipe(ialu_reg);
6954 %}
6955
6956 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6957 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6958 ins_cost(150);
6959 size(4);
6960 format %{ "MOV$cmp $fcc,$src,$dst" %}
6961 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6962 ins_pipe(ialu_reg);
6963 %}
6964
6965 // Conditional move
6966 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6967 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6968 ins_cost(150);
6969 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6970 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6971 ins_pipe(ialu_reg);
6972 %}
6973
6974 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6975 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6976 ins_cost(140);
6977 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6978 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6979 ins_pipe(ialu_imm);
6980 %}
6981
6982 // This instruction also works with CmpN so we don't need cmovPN_reg.
6983 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6984 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6985 ins_cost(150);
6986
6987 size(4);
6988 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6989 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6990 ins_pipe(ialu_reg);
6991 %}
6992
6993 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6994 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6995 ins_cost(150);
6996
6997 size(4);
6998 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6999 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7000 ins_pipe(ialu_reg);
7001 %}
7002
7003 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
7004 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7005 ins_cost(140);
7006
7007 size(4);
7008 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
7009 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7010 ins_pipe(ialu_imm);
7011 %}
7012
7013 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
7014 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7015 ins_cost(140);
7016
7017 size(4);
7018 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
7019 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7020 ins_pipe(ialu_imm);
7021 %}
7022
7023 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
7024 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7025 ins_cost(150);
7026 size(4);
7027 format %{ "MOV$cmp $fcc,$src,$dst" %}
7028 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7029 ins_pipe(ialu_imm);
7030 %}
7031
7032 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
7033 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7034 ins_cost(140);
7035 size(4);
7036 format %{ "MOV$cmp $fcc,$src,$dst" %}
7037 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
7038 ins_pipe(ialu_imm);
7039 %}
7040
7041 // Conditional move
7042 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7043 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7044 ins_cost(150);
7045 opcode(0x101);
7046 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7047 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7048 ins_pipe(int_conditional_float_move);
7049 %}
7050
7051 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7052 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7053 ins_cost(150);
7054
7055 size(4);
7056 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7057 opcode(0x101);
7058 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7059 ins_pipe(int_conditional_float_move);
7060 %}
7061
7062 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7063 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7064 ins_cost(150);
7065
7066 size(4);
7067 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7068 opcode(0x101);
7069 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7070 ins_pipe(int_conditional_float_move);
7071 %}
7072
7073 // Conditional move,
7074 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7075 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7076 ins_cost(150);
7077 size(4);
7078 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7079 opcode(0x1);
7080 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7081 ins_pipe(int_conditional_double_move);
7082 %}
7083
7084 // Conditional move
7085 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7086 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7087 ins_cost(150);
7088 size(4);
7089 opcode(0x102);
7090 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7091 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7092 ins_pipe(int_conditional_double_move);
7093 %}
7094
7095 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7096 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7097 ins_cost(150);
7098
7099 size(4);
7100 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7101 opcode(0x102);
7102 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7103 ins_pipe(int_conditional_double_move);
7104 %}
7105
7106 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7107 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7108 ins_cost(150);
7109
7110 size(4);
7111 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7112 opcode(0x102);
7113 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7114 ins_pipe(int_conditional_double_move);
7115 %}
7116
7117 // Conditional move,
7118 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7119 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7120 ins_cost(150);
7121 size(4);
7122 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7123 opcode(0x2);
7124 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7125 ins_pipe(int_conditional_double_move);
7126 %}
7127
7128 // Conditional move
7129 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7130 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7131 ins_cost(150);
7132 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7133 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7134 ins_pipe(ialu_reg);
7135 %}
7136
7137 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7138 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7139 ins_cost(140);
7140 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7141 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7142 ins_pipe(ialu_imm);
7143 %}
7144
7145 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7146 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7147 ins_cost(150);
7148
7149 size(4);
7150 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7151 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7152 ins_pipe(ialu_reg);
7153 %}
7154
7155
7156 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7157 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7158 ins_cost(150);
7159
7160 size(4);
7161 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7162 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7163 ins_pipe(ialu_reg);
7164 %}
7165
7166
7167 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7168 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7169 ins_cost(150);
7170
7171 size(4);
7172 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7173 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7174 ins_pipe(ialu_reg);
7175 %}
7176
7177
7178
7179 //----------OS and Locking Instructions----------------------------------------
7180
7181 // This name is KNOWN by the ADLC and cannot be changed.
7182 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7183 // for this guy.
7184 instruct tlsLoadP(g2RegP dst) %{
7185 match(Set dst (ThreadLocal));
7186
7187 size(0);
7188 ins_cost(0);
7189 format %{ "# TLS is in G2" %}
7190 ins_encode( /*empty encoding*/ );
7191 ins_pipe(ialu_none);
7192 %}
7193
7194 instruct checkCastPP( iRegP dst ) %{
7195 match(Set dst (CheckCastPP dst));
7196
7197 size(0);
7198 format %{ "# checkcastPP of $dst" %}
7199 ins_encode( /*empty encoding*/ );
7200 ins_pipe(empty);
7201 %}
7202
7203
7204 instruct castPP( iRegP dst ) %{
7205 match(Set dst (CastPP dst));
7206 format %{ "# castPP of $dst" %}
7207 ins_encode( /*empty encoding*/ );
7208 ins_pipe(empty);
7209 %}
7210
7211 instruct castII( iRegI dst ) %{
7212 match(Set dst (CastII dst));
7213 format %{ "# castII of $dst" %}
7214 ins_encode( /*empty encoding*/ );
7215 ins_cost(0);
7216 ins_pipe(empty);
7217 %}
7218
7219 //----------Arithmetic Instructions--------------------------------------------
7220 // Addition Instructions
7221 // Register Addition
7222 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7223 match(Set dst (AddI src1 src2));
7224
7225 size(4);
7226 format %{ "ADD $src1,$src2,$dst" %}
7227 ins_encode %{
7228 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7229 %}
7230 ins_pipe(ialu_reg_reg);
7231 %}
7232
7233 // Immediate Addition
7234 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7235 match(Set dst (AddI src1 src2));
7236
7237 size(4);
7238 format %{ "ADD $src1,$src2,$dst" %}
7239 opcode(Assembler::add_op3, Assembler::arith_op);
7240 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7241 ins_pipe(ialu_reg_imm);
7242 %}
7243
7244 // Pointer Register Addition
7245 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7246 match(Set dst (AddP src1 src2));
7247
7248 size(4);
7249 format %{ "ADD $src1,$src2,$dst" %}
7250 opcode(Assembler::add_op3, Assembler::arith_op);
7251 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7252 ins_pipe(ialu_reg_reg);
7253 %}
7254
7255 // Pointer Immediate Addition
7256 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7257 match(Set dst (AddP src1 src2));
7258
7259 size(4);
7260 format %{ "ADD $src1,$src2,$dst" %}
7261 opcode(Assembler::add_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7263 ins_pipe(ialu_reg_imm);
7264 %}
7265
7266 // Long Addition
7267 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7268 match(Set dst (AddL src1 src2));
7269
7270 size(4);
7271 format %{ "ADD $src1,$src2,$dst\t! long" %}
7272 opcode(Assembler::add_op3, Assembler::arith_op);
7273 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7274 ins_pipe(ialu_reg_reg);
7275 %}
7276
7277 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7278 match(Set dst (AddL src1 con));
7279
7280 size(4);
7281 format %{ "ADD $src1,$con,$dst" %}
7282 opcode(Assembler::add_op3, Assembler::arith_op);
7283 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7284 ins_pipe(ialu_reg_imm);
7285 %}
7286
7287 //----------Conditional_store--------------------------------------------------
7288 // Conditional-store of the updated heap-top.
7289 // Used during allocation of the shared heap.
7290 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7291
7292 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7293 instruct loadPLocked(iRegP dst, memory mem) %{
7294 match(Set dst (LoadPLocked mem));
7295 ins_cost(MEMORY_REF_COST);
7296
7297 #ifndef _LP64
7298 size(4);
7299 format %{ "LDUW $mem,$dst\t! ptr" %}
7300 opcode(Assembler::lduw_op3, 0, REGP_OP);
7301 #else
7302 format %{ "LDX $mem,$dst\t! ptr" %}
7303 opcode(Assembler::ldx_op3, 0, REGP_OP);
7304 #endif
7305 ins_encode( form3_mem_reg( mem, dst ) );
7306 ins_pipe(iload_mem);
7307 %}
7308
7309 // LoadL-locked. Same as a regular long load when used with a compare-swap
7310 instruct loadLLocked(iRegL dst, memory mem) %{
7311 match(Set dst (LoadLLocked mem));
7312 ins_cost(MEMORY_REF_COST);
7313 size(4);
7314 format %{ "LDX $mem,$dst\t! long" %}
7315 opcode(Assembler::ldx_op3);
7316 ins_encode(simple_form3_mem_reg( mem, dst ) );
7317 ins_pipe(iload_mem);
7318 %}
7319
7320 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7321 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7322 effect( KILL newval );
7323 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7324 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7325 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7326 ins_pipe( long_memory_op );
7327 %}
7328
7329 // Conditional-store of an int value.
7330 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7331 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7332 effect( KILL newval );
7333 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7334 "CMP $oldval,$newval\t\t! See if we made progress" %}
7335 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7336 ins_pipe( long_memory_op );
7337 %}
7338
7339 // Conditional-store of a long value.
7340 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7341 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7342 effect( KILL newval );
7343 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7344 "CMP $oldval,$newval\t\t! See if we made progress" %}
7345 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7346 ins_pipe( long_memory_op );
7347 %}
7348
7349 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7350
7351 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7352 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7353 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7354 format %{
7355 "MOV $newval,O7\n\t"
7356 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7357 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7358 "MOV 1,$res\n\t"
7359 "MOVne xcc,R_G0,$res"
7360 %}
7361 ins_encode( enc_casx(mem_ptr, oldval, newval),
7362 enc_lflags_ne_to_boolean(res) );
7363 ins_pipe( long_memory_op );
7364 %}
7365
7366
7367 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7368 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7369 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7370 format %{
7371 "MOV $newval,O7\n\t"
7372 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7373 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7374 "MOV 1,$res\n\t"
7375 "MOVne icc,R_G0,$res"
7376 %}
7377 ins_encode( enc_casi(mem_ptr, oldval, newval),
7378 enc_iflags_ne_to_boolean(res) );
7379 ins_pipe( long_memory_op );
7380 %}
7381
7382 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7383 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7384 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7385 format %{
7386 "MOV $newval,O7\n\t"
7387 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7388 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7389 "MOV 1,$res\n\t"
7390 "MOVne xcc,R_G0,$res"
7391 %}
7392 #ifdef _LP64
7393 ins_encode( enc_casx(mem_ptr, oldval, newval),
7394 enc_lflags_ne_to_boolean(res) );
7395 #else
7396 ins_encode( enc_casi(mem_ptr, oldval, newval),
7397 enc_iflags_ne_to_boolean(res) );
7398 #endif
7399 ins_pipe( long_memory_op );
7400 %}
7401
7402 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7403 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7404 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7405 format %{
7406 "MOV $newval,O7\n\t"
7407 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7408 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7409 "MOV 1,$res\n\t"
7410 "MOVne icc,R_G0,$res"
7411 %}
7412 ins_encode( enc_casi(mem_ptr, oldval, newval),
7413 enc_iflags_ne_to_boolean(res) );
7414 ins_pipe( long_memory_op );
7415 %}
7416
7417 //---------------------
7418 // Subtraction Instructions
7419 // Register Subtraction
7420 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7421 match(Set dst (SubI src1 src2));
7422
7423 size(4);
7424 format %{ "SUB $src1,$src2,$dst" %}
7425 opcode(Assembler::sub_op3, Assembler::arith_op);
7426 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7427 ins_pipe(ialu_reg_reg);
7428 %}
7429
7430 // Immediate Subtraction
7431 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7432 match(Set dst (SubI src1 src2));
7433
7434 size(4);
7435 format %{ "SUB $src1,$src2,$dst" %}
7436 opcode(Assembler::sub_op3, Assembler::arith_op);
7437 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7438 ins_pipe(ialu_reg_imm);
7439 %}
7440
7441 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7442 match(Set dst (SubI zero src2));
7443
7444 size(4);
7445 format %{ "NEG $src2,$dst" %}
7446 opcode(Assembler::sub_op3, Assembler::arith_op);
7447 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7448 ins_pipe(ialu_zero_reg);
7449 %}
7450
7451 // Long subtraction
7452 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7453 match(Set dst (SubL src1 src2));
7454
7455 size(4);
7456 format %{ "SUB $src1,$src2,$dst\t! long" %}
7457 opcode(Assembler::sub_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7459 ins_pipe(ialu_reg_reg);
7460 %}
7461
7462 // Immediate Subtraction
7463 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7464 match(Set dst (SubL src1 con));
7465
7466 size(4);
7467 format %{ "SUB $src1,$con,$dst\t! long" %}
7468 opcode(Assembler::sub_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7470 ins_pipe(ialu_reg_imm);
7471 %}
7472
7473 // Long negation
7474 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7475 match(Set dst (SubL zero src2));
7476
7477 size(4);
7478 format %{ "NEG $src2,$dst\t! long" %}
7479 opcode(Assembler::sub_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7481 ins_pipe(ialu_zero_reg);
7482 %}
7483
7484 // Multiplication Instructions
7485 // Integer Multiplication
7486 // Register Multiplication
7487 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7488 match(Set dst (MulI src1 src2));
7489
7490 size(4);
7491 format %{ "MULX $src1,$src2,$dst" %}
7492 opcode(Assembler::mulx_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7494 ins_pipe(imul_reg_reg);
7495 %}
7496
7497 // Immediate Multiplication
7498 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7499 match(Set dst (MulI src1 src2));
7500
7501 size(4);
7502 format %{ "MULX $src1,$src2,$dst" %}
7503 opcode(Assembler::mulx_op3, Assembler::arith_op);
7504 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7505 ins_pipe(imul_reg_imm);
7506 %}
7507
7508 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7509 match(Set dst (MulL src1 src2));
7510 ins_cost(DEFAULT_COST * 5);
7511 size(4);
7512 format %{ "MULX $src1,$src2,$dst\t! long" %}
7513 opcode(Assembler::mulx_op3, Assembler::arith_op);
7514 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7515 ins_pipe(mulL_reg_reg);
7516 %}
7517
7518 // Immediate Multiplication
7519 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7520 match(Set dst (MulL src1 src2));
7521 ins_cost(DEFAULT_COST * 5);
7522 size(4);
7523 format %{ "MULX $src1,$src2,$dst" %}
7524 opcode(Assembler::mulx_op3, Assembler::arith_op);
7525 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7526 ins_pipe(mulL_reg_imm);
7527 %}
7528
7529 // Integer Division
7530 // Register Division
7531 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7532 match(Set dst (DivI src1 src2));
7533 ins_cost((2+71)*DEFAULT_COST);
7534
7535 format %{ "SRA $src2,0,$src2\n\t"
7536 "SRA $src1,0,$src1\n\t"
7537 "SDIVX $src1,$src2,$dst" %}
7538 ins_encode( idiv_reg( src1, src2, dst ) );
7539 ins_pipe(sdiv_reg_reg);
7540 %}
7541
7542 // Immediate Division
7543 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7544 match(Set dst (DivI src1 src2));
7545 ins_cost((2+71)*DEFAULT_COST);
7546
7547 format %{ "SRA $src1,0,$src1\n\t"
7548 "SDIVX $src1,$src2,$dst" %}
7549 ins_encode( idiv_imm( src1, src2, dst ) );
7550 ins_pipe(sdiv_reg_imm);
7551 %}
7552
7553 //----------Div-By-10-Expansion------------------------------------------------
7554 // Extract hi bits of a 32x32->64 bit multiply.
7555 // Expand rule only, not matched
7556 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7557 effect( DEF dst, USE src1, USE src2 );
7558 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7559 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7560 ins_encode( enc_mul_hi(dst,src1,src2));
7561 ins_pipe(sdiv_reg_reg);
7562 %}
7563
7564 // Magic constant, reciprocal of 10
7565 instruct loadConI_x66666667(iRegIsafe dst) %{
7566 effect( DEF dst );
7567
7568 size(8);
7569 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7570 ins_encode( Set32(0x66666667, dst) );
7571 ins_pipe(ialu_hi_lo_reg);
7572 %}
7573
7574 // Register Shift Right Arithmetic Long by 32-63
7575 instruct sra_31( iRegI dst, iRegI src ) %{
7576 effect( DEF dst, USE src );
7577 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7578 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7579 ins_pipe(ialu_reg_reg);
7580 %}
7581
7582 // Arithmetic Shift Right by 8-bit immediate
7583 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7584 effect( DEF dst, USE src );
7585 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7586 opcode(Assembler::sra_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7588 ins_pipe(ialu_reg_imm);
7589 %}
7590
7591 // Integer DIV with 10
7592 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7593 match(Set dst (DivI src div));
7594 ins_cost((6+6)*DEFAULT_COST);
7595 expand %{
7596 iRegIsafe tmp1; // Killed temps;
7597 iRegIsafe tmp2; // Killed temps;
7598 iRegI tmp3; // Killed temps;
7599 iRegI tmp4; // Killed temps;
7600 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7601 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7602 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7603 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7604 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7605 %}
7606 %}
7607
7608 // Register Long Division
7609 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7610 match(Set dst (DivL src1 src2));
7611 ins_cost(DEFAULT_COST*71);
7612 size(4);
7613 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7614 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7615 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7616 ins_pipe(divL_reg_reg);
7617 %}
7618
7619 // Register Long Division
7620 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7621 match(Set dst (DivL src1 src2));
7622 ins_cost(DEFAULT_COST*71);
7623 size(4);
7624 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7625 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7626 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7627 ins_pipe(divL_reg_imm);
7628 %}
7629
7630 // Integer Remainder
7631 // Register Remainder
7632 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7633 match(Set dst (ModI src1 src2));
7634 effect( KILL ccr, KILL temp);
7635
7636 format %{ "SREM $src1,$src2,$dst" %}
7637 ins_encode( irem_reg(src1, src2, dst, temp) );
7638 ins_pipe(sdiv_reg_reg);
7639 %}
7640
7641 // Immediate Remainder
7642 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7643 match(Set dst (ModI src1 src2));
7644 effect( KILL ccr, KILL temp);
7645
7646 format %{ "SREM $src1,$src2,$dst" %}
7647 ins_encode( irem_imm(src1, src2, dst, temp) );
7648 ins_pipe(sdiv_reg_imm);
7649 %}
7650
7651 // Register Long Remainder
7652 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7653 effect(DEF dst, USE src1, USE src2);
7654 size(4);
7655 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7656 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7657 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7658 ins_pipe(divL_reg_reg);
7659 %}
7660
7661 // Register Long Division
7662 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7663 effect(DEF dst, USE src1, USE src2);
7664 size(4);
7665 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7666 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7667 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7668 ins_pipe(divL_reg_imm);
7669 %}
7670
7671 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7672 effect(DEF dst, USE src1, USE src2);
7673 size(4);
7674 format %{ "MULX $src1,$src2,$dst\t! long" %}
7675 opcode(Assembler::mulx_op3, Assembler::arith_op);
7676 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7677 ins_pipe(mulL_reg_reg);
7678 %}
7679
7680 // Immediate Multiplication
7681 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7682 effect(DEF dst, USE src1, USE src2);
7683 size(4);
7684 format %{ "MULX $src1,$src2,$dst" %}
7685 opcode(Assembler::mulx_op3, Assembler::arith_op);
7686 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7687 ins_pipe(mulL_reg_imm);
7688 %}
7689
7690 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7691 effect(DEF dst, USE src1, USE src2);
7692 size(4);
7693 format %{ "SUB $src1,$src2,$dst\t! long" %}
7694 opcode(Assembler::sub_op3, Assembler::arith_op);
7695 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7696 ins_pipe(ialu_reg_reg);
7697 %}
7698
7699 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7700 effect(DEF dst, USE src1, USE src2);
7701 size(4);
7702 format %{ "SUB $src1,$src2,$dst\t! long" %}
7703 opcode(Assembler::sub_op3, Assembler::arith_op);
7704 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7705 ins_pipe(ialu_reg_reg);
7706 %}
7707
7708 // Register Long Remainder
7709 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7710 match(Set dst (ModL src1 src2));
7711 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7712 expand %{
7713 iRegL tmp1;
7714 iRegL tmp2;
7715 divL_reg_reg_1(tmp1, src1, src2);
7716 mulL_reg_reg_1(tmp2, tmp1, src2);
7717 subL_reg_reg_1(dst, src1, tmp2);
7718 %}
7719 %}
7720
7721 // Register Long Remainder
7722 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7723 match(Set dst (ModL src1 src2));
7724 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7725 expand %{
7726 iRegL tmp1;
7727 iRegL tmp2;
7728 divL_reg_imm13_1(tmp1, src1, src2);
7729 mulL_reg_imm13_1(tmp2, tmp1, src2);
7730 subL_reg_reg_2 (dst, src1, tmp2);
7731 %}
7732 %}
7733
7734 // Integer Shift Instructions
7735 // Register Shift Left
7736 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7737 match(Set dst (LShiftI src1 src2));
7738
7739 size(4);
7740 format %{ "SLL $src1,$src2,$dst" %}
7741 opcode(Assembler::sll_op3, Assembler::arith_op);
7742 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7743 ins_pipe(ialu_reg_reg);
7744 %}
7745
7746 // Register Shift Left Immediate
7747 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7748 match(Set dst (LShiftI src1 src2));
7749
7750 size(4);
7751 format %{ "SLL $src1,$src2,$dst" %}
7752 opcode(Assembler::sll_op3, Assembler::arith_op);
7753 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7754 ins_pipe(ialu_reg_imm);
7755 %}
7756
7757 // Register Shift Left
7758 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7759 match(Set dst (LShiftL src1 src2));
7760
7761 size(4);
7762 format %{ "SLLX $src1,$src2,$dst" %}
7763 opcode(Assembler::sllx_op3, Assembler::arith_op);
7764 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7765 ins_pipe(ialu_reg_reg);
7766 %}
7767
7768 // Register Shift Left Immediate
7769 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7770 match(Set dst (LShiftL src1 src2));
7771
7772 size(4);
7773 format %{ "SLLX $src1,$src2,$dst" %}
7774 opcode(Assembler::sllx_op3, Assembler::arith_op);
7775 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7776 ins_pipe(ialu_reg_imm);
7777 %}
7778
7779 // Register Arithmetic Shift Right
7780 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7781 match(Set dst (RShiftI src1 src2));
7782 size(4);
7783 format %{ "SRA $src1,$src2,$dst" %}
7784 opcode(Assembler::sra_op3, Assembler::arith_op);
7785 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7786 ins_pipe(ialu_reg_reg);
7787 %}
7788
7789 // Register Arithmetic Shift Right Immediate
7790 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7791 match(Set dst (RShiftI src1 src2));
7792
7793 size(4);
7794 format %{ "SRA $src1,$src2,$dst" %}
7795 opcode(Assembler::sra_op3, Assembler::arith_op);
7796 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7797 ins_pipe(ialu_reg_imm);
7798 %}
7799
7800 // Register Shift Right Arithmatic Long
7801 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7802 match(Set dst (RShiftL src1 src2));
7803
7804 size(4);
7805 format %{ "SRAX $src1,$src2,$dst" %}
7806 opcode(Assembler::srax_op3, Assembler::arith_op);
7807 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7808 ins_pipe(ialu_reg_reg);
7809 %}
7810
7811 // Register Shift Left Immediate
7812 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7813 match(Set dst (RShiftL src1 src2));
7814
7815 size(4);
7816 format %{ "SRAX $src1,$src2,$dst" %}
7817 opcode(Assembler::srax_op3, Assembler::arith_op);
7818 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7819 ins_pipe(ialu_reg_imm);
7820 %}
7821
7822 // Register Shift Right
7823 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7824 match(Set dst (URShiftI src1 src2));
7825
7826 size(4);
7827 format %{ "SRL $src1,$src2,$dst" %}
7828 opcode(Assembler::srl_op3, Assembler::arith_op);
7829 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7830 ins_pipe(ialu_reg_reg);
7831 %}
7832
7833 // Register Shift Right Immediate
7834 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7835 match(Set dst (URShiftI src1 src2));
7836
7837 size(4);
7838 format %{ "SRL $src1,$src2,$dst" %}
7839 opcode(Assembler::srl_op3, Assembler::arith_op);
7840 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7841 ins_pipe(ialu_reg_imm);
7842 %}
7843
7844 // Register Shift Right
7845 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7846 match(Set dst (URShiftL src1 src2));
7847
7848 size(4);
7849 format %{ "SRLX $src1,$src2,$dst" %}
7850 opcode(Assembler::srlx_op3, Assembler::arith_op);
7851 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7852 ins_pipe(ialu_reg_reg);
7853 %}
7854
7855 // Register Shift Right Immediate
7856 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7857 match(Set dst (URShiftL src1 src2));
7858
7859 size(4);
7860 format %{ "SRLX $src1,$src2,$dst" %}
7861 opcode(Assembler::srlx_op3, Assembler::arith_op);
7862 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7863 ins_pipe(ialu_reg_imm);
7864 %}
7865
7866 // Register Shift Right Immediate with a CastP2X
7867 #ifdef _LP64
7868 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7869 match(Set dst (URShiftL (CastP2X src1) src2));
7870 size(4);
7871 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7872 opcode(Assembler::srlx_op3, Assembler::arith_op);
7873 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7874 ins_pipe(ialu_reg_imm);
7875 %}
7876 #else
7877 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7878 match(Set dst (URShiftI (CastP2X src1) src2));
7879 size(4);
7880 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7881 opcode(Assembler::srl_op3, Assembler::arith_op);
7882 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7883 ins_pipe(ialu_reg_imm);
7884 %}
7885 #endif
7886
7887
7888 //----------Floating Point Arithmetic Instructions-----------------------------
7889
7890 // Add float single precision
7891 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7892 match(Set dst (AddF src1 src2));
7893
7894 size(4);
7895 format %{ "FADDS $src1,$src2,$dst" %}
7896 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7897 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7898 ins_pipe(faddF_reg_reg);
7899 %}
7900
7901 // Add float double precision
7902 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7903 match(Set dst (AddD src1 src2));
7904
7905 size(4);
7906 format %{ "FADDD $src1,$src2,$dst" %}
7907 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7908 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7909 ins_pipe(faddD_reg_reg);
7910 %}
7911
7912 // Sub float single precision
7913 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7914 match(Set dst (SubF src1 src2));
7915
7916 size(4);
7917 format %{ "FSUBS $src1,$src2,$dst" %}
7918 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7919 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7920 ins_pipe(faddF_reg_reg);
7921 %}
7922
7923 // Sub float double precision
7924 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7925 match(Set dst (SubD src1 src2));
7926
7927 size(4);
7928 format %{ "FSUBD $src1,$src2,$dst" %}
7929 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7930 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7931 ins_pipe(faddD_reg_reg);
7932 %}
7933
7934 // Mul float single precision
7935 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7936 match(Set dst (MulF src1 src2));
7937
7938 size(4);
7939 format %{ "FMULS $src1,$src2,$dst" %}
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7941 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7942 ins_pipe(fmulF_reg_reg);
7943 %}
7944
7945 // Mul float double precision
7946 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7947 match(Set dst (MulD src1 src2));
7948
7949 size(4);
7950 format %{ "FMULD $src1,$src2,$dst" %}
7951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7952 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7953 ins_pipe(fmulD_reg_reg);
7954 %}
7955
7956 // Div float single precision
7957 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7958 match(Set dst (DivF src1 src2));
7959
7960 size(4);
7961 format %{ "FDIVS $src1,$src2,$dst" %}
7962 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7963 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7964 ins_pipe(fdivF_reg_reg);
7965 %}
7966
7967 // Div float double precision
7968 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7969 match(Set dst (DivD src1 src2));
7970
7971 size(4);
7972 format %{ "FDIVD $src1,$src2,$dst" %}
7973 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7974 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7975 ins_pipe(fdivD_reg_reg);
7976 %}
7977
7978 // Absolute float double precision
7979 instruct absD_reg(regD dst, regD src) %{
7980 match(Set dst (AbsD src));
7981
7982 format %{ "FABSd $src,$dst" %}
7983 ins_encode(fabsd(dst, src));
7984 ins_pipe(faddD_reg);
7985 %}
7986
7987 // Absolute float single precision
7988 instruct absF_reg(regF dst, regF src) %{
7989 match(Set dst (AbsF src));
7990
7991 format %{ "FABSs $src,$dst" %}
7992 ins_encode(fabss(dst, src));
7993 ins_pipe(faddF_reg);
7994 %}
7995
7996 instruct negF_reg(regF dst, regF src) %{
7997 match(Set dst (NegF src));
7998
7999 size(4);
8000 format %{ "FNEGs $src,$dst" %}
8001 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
8002 ins_encode(form3_opf_rs2F_rdF(src, dst));
8003 ins_pipe(faddF_reg);
8004 %}
8005
8006 instruct negD_reg(regD dst, regD src) %{
8007 match(Set dst (NegD src));
8008
8009 format %{ "FNEGd $src,$dst" %}
8010 ins_encode(fnegd(dst, src));
8011 ins_pipe(faddD_reg);
8012 %}
8013
8014 // Sqrt float double precision
8015 instruct sqrtF_reg_reg(regF dst, regF src) %{
8016 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8017
8018 size(4);
8019 format %{ "FSQRTS $src,$dst" %}
8020 ins_encode(fsqrts(dst, src));
8021 ins_pipe(fdivF_reg_reg);
8022 %}
8023
8024 // Sqrt float double precision
8025 instruct sqrtD_reg_reg(regD dst, regD src) %{
8026 match(Set dst (SqrtD src));
8027
8028 size(4);
8029 format %{ "FSQRTD $src,$dst" %}
8030 ins_encode(fsqrtd(dst, src));
8031 ins_pipe(fdivD_reg_reg);
8032 %}
8033
8034 //----------Logical Instructions-----------------------------------------------
8035 // And Instructions
8036 // Register And
8037 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8038 match(Set dst (AndI src1 src2));
8039
8040 size(4);
8041 format %{ "AND $src1,$src2,$dst" %}
8042 opcode(Assembler::and_op3, Assembler::arith_op);
8043 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8044 ins_pipe(ialu_reg_reg);
8045 %}
8046
8047 // Immediate And
8048 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8049 match(Set dst (AndI src1 src2));
8050
8051 size(4);
8052 format %{ "AND $src1,$src2,$dst" %}
8053 opcode(Assembler::and_op3, Assembler::arith_op);
8054 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8055 ins_pipe(ialu_reg_imm);
8056 %}
8057
8058 // Register And Long
8059 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8060 match(Set dst (AndL src1 src2));
8061
8062 ins_cost(DEFAULT_COST);
8063 size(4);
8064 format %{ "AND $src1,$src2,$dst\t! long" %}
8065 opcode(Assembler::and_op3, Assembler::arith_op);
8066 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8067 ins_pipe(ialu_reg_reg);
8068 %}
8069
8070 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8071 match(Set dst (AndL src1 con));
8072
8073 ins_cost(DEFAULT_COST);
8074 size(4);
8075 format %{ "AND $src1,$con,$dst\t! long" %}
8076 opcode(Assembler::and_op3, Assembler::arith_op);
8077 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8078 ins_pipe(ialu_reg_imm);
8079 %}
8080
8081 // Or Instructions
8082 // Register Or
8083 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8084 match(Set dst (OrI src1 src2));
8085
8086 size(4);
8087 format %{ "OR $src1,$src2,$dst" %}
8088 opcode(Assembler::or_op3, Assembler::arith_op);
8089 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8090 ins_pipe(ialu_reg_reg);
8091 %}
8092
8093 // Immediate Or
8094 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8095 match(Set dst (OrI src1 src2));
8096
8097 size(4);
8098 format %{ "OR $src1,$src2,$dst" %}
8099 opcode(Assembler::or_op3, Assembler::arith_op);
8100 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8101 ins_pipe(ialu_reg_imm);
8102 %}
8103
8104 // Register Or Long
8105 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8106 match(Set dst (OrL src1 src2));
8107
8108 ins_cost(DEFAULT_COST);
8109 size(4);
8110 format %{ "OR $src1,$src2,$dst\t! long" %}
8111 opcode(Assembler::or_op3, Assembler::arith_op);
8112 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8113 ins_pipe(ialu_reg_reg);
8114 %}
8115
8116 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8117 match(Set dst (OrL src1 con));
8118 ins_cost(DEFAULT_COST*2);
8119
8120 ins_cost(DEFAULT_COST);
8121 size(4);
8122 format %{ "OR $src1,$con,$dst\t! long" %}
8123 opcode(Assembler::or_op3, Assembler::arith_op);
8124 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8125 ins_pipe(ialu_reg_imm);
8126 %}
8127
8128 #ifndef _LP64
8129
8130 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8131 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8132 match(Set dst (OrI src1 (CastP2X src2)));
8133
8134 size(4);
8135 format %{ "OR $src1,$src2,$dst" %}
8136 opcode(Assembler::or_op3, Assembler::arith_op);
8137 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8138 ins_pipe(ialu_reg_reg);
8139 %}
8140
8141 #else
8142
8143 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8144 match(Set dst (OrL src1 (CastP2X src2)));
8145
8146 ins_cost(DEFAULT_COST);
8147 size(4);
8148 format %{ "OR $src1,$src2,$dst\t! long" %}
8149 opcode(Assembler::or_op3, Assembler::arith_op);
8150 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8151 ins_pipe(ialu_reg_reg);
8152 %}
8153
8154 #endif
8155
8156 // Xor Instructions
8157 // Register Xor
8158 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8159 match(Set dst (XorI src1 src2));
8160
8161 size(4);
8162 format %{ "XOR $src1,$src2,$dst" %}
8163 opcode(Assembler::xor_op3, Assembler::arith_op);
8164 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8165 ins_pipe(ialu_reg_reg);
8166 %}
8167
8168 // Immediate Xor
8169 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8170 match(Set dst (XorI src1 src2));
8171
8172 size(4);
8173 format %{ "XOR $src1,$src2,$dst" %}
8174 opcode(Assembler::xor_op3, Assembler::arith_op);
8175 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8176 ins_pipe(ialu_reg_imm);
8177 %}
8178
8179 // Register Xor Long
8180 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8181 match(Set dst (XorL src1 src2));
8182
8183 ins_cost(DEFAULT_COST);
8184 size(4);
8185 format %{ "XOR $src1,$src2,$dst\t! long" %}
8186 opcode(Assembler::xor_op3, Assembler::arith_op);
8187 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8188 ins_pipe(ialu_reg_reg);
8189 %}
8190
8191 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8192 match(Set dst (XorL src1 con));
8193
8194 ins_cost(DEFAULT_COST);
8195 size(4);
8196 format %{ "XOR $src1,$con,$dst\t! long" %}
8197 opcode(Assembler::xor_op3, Assembler::arith_op);
8198 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8199 ins_pipe(ialu_reg_imm);
8200 %}
8201
8202 //----------Convert to Boolean-------------------------------------------------
8203 // Nice hack for 32-bit tests but doesn't work for
8204 // 64-bit pointers.
8205 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8206 match(Set dst (Conv2B src));
8207 effect( KILL ccr );
8208 ins_cost(DEFAULT_COST*2);
8209 format %{ "CMP R_G0,$src\n\t"
8210 "ADDX R_G0,0,$dst" %}
8211 ins_encode( enc_to_bool( src, dst ) );
8212 ins_pipe(ialu_reg_ialu);
8213 %}
8214
8215 #ifndef _LP64
8216 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8217 match(Set dst (Conv2B src));
8218 effect( KILL ccr );
8219 ins_cost(DEFAULT_COST*2);
8220 format %{ "CMP R_G0,$src\n\t"
8221 "ADDX R_G0,0,$dst" %}
8222 ins_encode( enc_to_bool( src, dst ) );
8223 ins_pipe(ialu_reg_ialu);
8224 %}
8225 #else
8226 instruct convP2B( iRegI dst, iRegP src ) %{
8227 match(Set dst (Conv2B src));
8228 ins_cost(DEFAULT_COST*2);
8229 format %{ "MOV $src,$dst\n\t"
8230 "MOVRNZ $src,1,$dst" %}
8231 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8232 ins_pipe(ialu_clr_and_mover);
8233 %}
8234 #endif
8235
8236 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8237 match(Set dst (CmpLTMask src zero));
8238 effect(KILL ccr);
8239 size(4);
8240 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8241 ins_encode %{
8242 __ sra($src$$Register, 31, $dst$$Register);
8243 %}
8244 ins_pipe(ialu_reg_imm);
8245 %}
8246
8247 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8248 match(Set dst (CmpLTMask p q));
8249 effect( KILL ccr );
8250 ins_cost(DEFAULT_COST*4);
8251 format %{ "CMP $p,$q\n\t"
8252 "MOV #0,$dst\n\t"
8253 "BLT,a .+8\n\t"
8254 "MOV #-1,$dst" %}
8255 ins_encode( enc_ltmask(p,q,dst) );
8256 ins_pipe(ialu_reg_reg_ialu);
8257 %}
8258
8259 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8260 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8261 effect(KILL ccr, TEMP tmp);
8262 ins_cost(DEFAULT_COST*3);
8263
8264 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8265 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8266 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8267 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8268 ins_pipe( cadd_cmpltmask );
8269 %}
8270
8271
8272 //-----------------------------------------------------------------
8273 // Direct raw moves between float and general registers using VIS3.
8274
8275 // ins_pipe(faddF_reg);
8276 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8277 predicate(UseVIS >= 3);
8278 match(Set dst (MoveF2I src));
8279
8280 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8281 ins_encode %{
8282 __ movstouw($src$$FloatRegister, $dst$$Register);
8283 %}
8284 ins_pipe(ialu_reg_reg);
8285 %}
8286
8287 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8288 predicate(UseVIS >= 3);
8289 match(Set dst (MoveI2F src));
8290
8291 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8292 ins_encode %{
8293 __ movwtos($src$$Register, $dst$$FloatRegister);
8294 %}
8295 ins_pipe(ialu_reg_reg);
8296 %}
8297
8298 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8299 predicate(UseVIS >= 3);
8300 match(Set dst (MoveD2L src));
8301
8302 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8303 ins_encode %{
8304 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8305 %}
8306 ins_pipe(ialu_reg_reg);
8307 %}
8308
8309 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8310 predicate(UseVIS >= 3);
8311 match(Set dst (MoveL2D src));
8312
8313 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8314 ins_encode %{
8315 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8316 %}
8317 ins_pipe(ialu_reg_reg);
8318 %}
8319
8320
8321 // Raw moves between float and general registers using stack.
8322
8323 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8324 match(Set dst (MoveF2I src));
8325 effect(DEF dst, USE src);
8326 ins_cost(MEMORY_REF_COST);
8327
8328 size(4);
8329 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8330 opcode(Assembler::lduw_op3);
8331 ins_encode(simple_form3_mem_reg( src, dst ) );
8332 ins_pipe(iload_mem);
8333 %}
8334
8335 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8336 match(Set dst (MoveI2F src));
8337 effect(DEF dst, USE src);
8338 ins_cost(MEMORY_REF_COST);
8339
8340 size(4);
8341 format %{ "LDF $src,$dst\t! MoveI2F" %}
8342 opcode(Assembler::ldf_op3);
8343 ins_encode(simple_form3_mem_reg(src, dst));
8344 ins_pipe(floadF_stk);
8345 %}
8346
8347 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8348 match(Set dst (MoveD2L src));
8349 effect(DEF dst, USE src);
8350 ins_cost(MEMORY_REF_COST);
8351
8352 size(4);
8353 format %{ "LDX $src,$dst\t! MoveD2L" %}
8354 opcode(Assembler::ldx_op3);
8355 ins_encode(simple_form3_mem_reg( src, dst ) );
8356 ins_pipe(iload_mem);
8357 %}
8358
8359 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8360 match(Set dst (MoveL2D src));
8361 effect(DEF dst, USE src);
8362 ins_cost(MEMORY_REF_COST);
8363
8364 size(4);
8365 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8366 opcode(Assembler::lddf_op3);
8367 ins_encode(simple_form3_mem_reg(src, dst));
8368 ins_pipe(floadD_stk);
8369 %}
8370
8371 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8372 match(Set dst (MoveF2I src));
8373 effect(DEF dst, USE src);
8374 ins_cost(MEMORY_REF_COST);
8375
8376 size(4);
8377 format %{ "STF $src,$dst\t! MoveF2I" %}
8378 opcode(Assembler::stf_op3);
8379 ins_encode(simple_form3_mem_reg(dst, src));
8380 ins_pipe(fstoreF_stk_reg);
8381 %}
8382
8383 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8384 match(Set dst (MoveI2F src));
8385 effect(DEF dst, USE src);
8386 ins_cost(MEMORY_REF_COST);
8387
8388 size(4);
8389 format %{ "STW $src,$dst\t! MoveI2F" %}
8390 opcode(Assembler::stw_op3);
8391 ins_encode(simple_form3_mem_reg( dst, src ) );
8392 ins_pipe(istore_mem_reg);
8393 %}
8394
8395 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8396 match(Set dst (MoveD2L src));
8397 effect(DEF dst, USE src);
8398 ins_cost(MEMORY_REF_COST);
8399
8400 size(4);
8401 format %{ "STDF $src,$dst\t! MoveD2L" %}
8402 opcode(Assembler::stdf_op3);
8403 ins_encode(simple_form3_mem_reg(dst, src));
8404 ins_pipe(fstoreD_stk_reg);
8405 %}
8406
8407 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8408 match(Set dst (MoveL2D src));
8409 effect(DEF dst, USE src);
8410 ins_cost(MEMORY_REF_COST);
8411
8412 size(4);
8413 format %{ "STX $src,$dst\t! MoveL2D" %}
8414 opcode(Assembler::stx_op3);
8415 ins_encode(simple_form3_mem_reg( dst, src ) );
8416 ins_pipe(istore_mem_reg);
8417 %}
8418
8419
8420 //----------Arithmetic Conversion Instructions---------------------------------
8421 // The conversions operations are all Alpha sorted. Please keep it that way!
8422
8423 instruct convD2F_reg(regF dst, regD src) %{
8424 match(Set dst (ConvD2F src));
8425 size(4);
8426 format %{ "FDTOS $src,$dst" %}
8427 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8428 ins_encode(form3_opf_rs2D_rdF(src, dst));
8429 ins_pipe(fcvtD2F);
8430 %}
8431
8432
8433 // Convert a double to an int in a float register.
8434 // If the double is a NAN, stuff a zero in instead.
8435 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8436 effect(DEF dst, USE src, KILL fcc0);
8437 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8438 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8439 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8440 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8441 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8442 "skip:" %}
8443 ins_encode(form_d2i_helper(src,dst));
8444 ins_pipe(fcvtD2I);
8445 %}
8446
8447 instruct convD2I_stk(stackSlotI dst, regD src) %{
8448 match(Set dst (ConvD2I src));
8449 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8450 expand %{
8451 regF tmp;
8452 convD2I_helper(tmp, src);
8453 regF_to_stkI(dst, tmp);
8454 %}
8455 %}
8456
8457 instruct convD2I_reg(iRegI dst, regD src) %{
8458 predicate(UseVIS >= 3);
8459 match(Set dst (ConvD2I src));
8460 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8461 expand %{
8462 regF tmp;
8463 convD2I_helper(tmp, src);
8464 MoveF2I_reg_reg(dst, tmp);
8465 %}
8466 %}
8467
8468
8469 // Convert a double to a long in a double register.
8470 // If the double is a NAN, stuff a zero in instead.
8471 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8472 effect(DEF dst, USE src, KILL fcc0);
8473 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8474 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8475 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8476 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8477 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8478 "skip:" %}
8479 ins_encode(form_d2l_helper(src,dst));
8480 ins_pipe(fcvtD2L);
8481 %}
8482
8483 instruct convD2L_stk(stackSlotL dst, regD src) %{
8484 match(Set dst (ConvD2L src));
8485 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8486 expand %{
8487 regD tmp;
8488 convD2L_helper(tmp, src);
8489 regD_to_stkL(dst, tmp);
8490 %}
8491 %}
8492
8493 instruct convD2L_reg(iRegL dst, regD src) %{
8494 predicate(UseVIS >= 3);
8495 match(Set dst (ConvD2L src));
8496 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8497 expand %{
8498 regD tmp;
8499 convD2L_helper(tmp, src);
8500 MoveD2L_reg_reg(dst, tmp);
8501 %}
8502 %}
8503
8504
8505 instruct convF2D_reg(regD dst, regF src) %{
8506 match(Set dst (ConvF2D src));
8507 format %{ "FSTOD $src,$dst" %}
8508 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8509 ins_encode(form3_opf_rs2F_rdD(src, dst));
8510 ins_pipe(fcvtF2D);
8511 %}
8512
8513
8514 // Convert a float to an int in a float register.
8515 // If the float is a NAN, stuff a zero in instead.
8516 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8517 effect(DEF dst, USE src, KILL fcc0);
8518 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8519 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8520 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8521 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8522 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8523 "skip:" %}
8524 ins_encode(form_f2i_helper(src,dst));
8525 ins_pipe(fcvtF2I);
8526 %}
8527
8528 instruct convF2I_stk(stackSlotI dst, regF src) %{
8529 match(Set dst (ConvF2I src));
8530 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8531 expand %{
8532 regF tmp;
8533 convF2I_helper(tmp, src);
8534 regF_to_stkI(dst, tmp);
8535 %}
8536 %}
8537
8538 instruct convF2I_reg(iRegI dst, regF src) %{
8539 predicate(UseVIS >= 3);
8540 match(Set dst (ConvF2I src));
8541 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8542 expand %{
8543 regF tmp;
8544 convF2I_helper(tmp, src);
8545 MoveF2I_reg_reg(dst, tmp);
8546 %}
8547 %}
8548
8549
8550 // Convert a float to a long in a float register.
8551 // If the float is a NAN, stuff a zero in instead.
8552 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8553 effect(DEF dst, USE src, KILL fcc0);
8554 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8555 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8556 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8557 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8558 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8559 "skip:" %}
8560 ins_encode(form_f2l_helper(src,dst));
8561 ins_pipe(fcvtF2L);
8562 %}
8563
8564 instruct convF2L_stk(stackSlotL dst, regF src) %{
8565 match(Set dst (ConvF2L src));
8566 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8567 expand %{
8568 regD tmp;
8569 convF2L_helper(tmp, src);
8570 regD_to_stkL(dst, tmp);
8571 %}
8572 %}
8573
8574 instruct convF2L_reg(iRegL dst, regF src) %{
8575 predicate(UseVIS >= 3);
8576 match(Set dst (ConvF2L src));
8577 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8578 expand %{
8579 regD tmp;
8580 convF2L_helper(tmp, src);
8581 MoveD2L_reg_reg(dst, tmp);
8582 %}
8583 %}
8584
8585
8586 instruct convI2D_helper(regD dst, regF tmp) %{
8587 effect(USE tmp, DEF dst);
8588 format %{ "FITOD $tmp,$dst" %}
8589 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8590 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8591 ins_pipe(fcvtI2D);
8592 %}
8593
8594 instruct convI2D_stk(stackSlotI src, regD dst) %{
8595 match(Set dst (ConvI2D src));
8596 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8597 expand %{
8598 regF tmp;
8599 stkI_to_regF(tmp, src);
8600 convI2D_helper(dst, tmp);
8601 %}
8602 %}
8603
8604 instruct convI2D_reg(regD_low dst, iRegI src) %{
8605 predicate(UseVIS >= 3);
8606 match(Set dst (ConvI2D src));
8607 expand %{
8608 regF tmp;
8609 MoveI2F_reg_reg(tmp, src);
8610 convI2D_helper(dst, tmp);
8611 %}
8612 %}
8613
8614 instruct convI2D_mem(regD_low dst, memory mem) %{
8615 match(Set dst (ConvI2D (LoadI mem)));
8616 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8617 size(8);
8618 format %{ "LDF $mem,$dst\n\t"
8619 "FITOD $dst,$dst" %}
8620 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8621 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8622 ins_pipe(floadF_mem);
8623 %}
8624
8625
8626 instruct convI2F_helper(regF dst, regF tmp) %{
8627 effect(DEF dst, USE tmp);
8628 format %{ "FITOS $tmp,$dst" %}
8629 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8630 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8631 ins_pipe(fcvtI2F);
8632 %}
8633
8634 instruct convI2F_stk(regF dst, stackSlotI src) %{
8635 match(Set dst (ConvI2F src));
8636 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8637 expand %{
8638 regF tmp;
8639 stkI_to_regF(tmp,src);
8640 convI2F_helper(dst, tmp);
8641 %}
8642 %}
8643
8644 instruct convI2F_reg(regF dst, iRegI src) %{
8645 predicate(UseVIS >= 3);
8646 match(Set dst (ConvI2F src));
8647 ins_cost(DEFAULT_COST);
8648 expand %{
8649 regF tmp;
8650 MoveI2F_reg_reg(tmp, src);
8651 convI2F_helper(dst, tmp);
8652 %}
8653 %}
8654
8655 instruct convI2F_mem( regF dst, memory mem ) %{
8656 match(Set dst (ConvI2F (LoadI mem)));
8657 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8658 size(8);
8659 format %{ "LDF $mem,$dst\n\t"
8660 "FITOS $dst,$dst" %}
8661 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8662 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8663 ins_pipe(floadF_mem);
8664 %}
8665
8666
8667 instruct convI2L_reg(iRegL dst, iRegI src) %{
8668 match(Set dst (ConvI2L src));
8669 size(4);
8670 format %{ "SRA $src,0,$dst\t! int->long" %}
8671 opcode(Assembler::sra_op3, Assembler::arith_op);
8672 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8673 ins_pipe(ialu_reg_reg);
8674 %}
8675
8676 // Zero-extend convert int to long
8677 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8678 match(Set dst (AndL (ConvI2L src) mask) );
8679 size(4);
8680 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8681 opcode(Assembler::srl_op3, Assembler::arith_op);
8682 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8683 ins_pipe(ialu_reg_reg);
8684 %}
8685
8686 // Zero-extend long
8687 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8688 match(Set dst (AndL src mask) );
8689 size(4);
8690 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8691 opcode(Assembler::srl_op3, Assembler::arith_op);
8692 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8693 ins_pipe(ialu_reg_reg);
8694 %}
8695
8696
8697 //-----------
8698 // Long to Double conversion using V8 opcodes.
8699 // Still useful because cheetah traps and becomes
8700 // amazingly slow for some common numbers.
8701
8702 // Magic constant, 0x43300000
8703 instruct loadConI_x43300000(iRegI dst) %{
8704 effect(DEF dst);
8705 size(4);
8706 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8707 ins_encode(SetHi22(0x43300000, dst));
8708 ins_pipe(ialu_none);
8709 %}
8710
8711 // Magic constant, 0x41f00000
8712 instruct loadConI_x41f00000(iRegI dst) %{
8713 effect(DEF dst);
8714 size(4);
8715 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8716 ins_encode(SetHi22(0x41f00000, dst));
8717 ins_pipe(ialu_none);
8718 %}
8719
8720 // Construct a double from two float halves
8721 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8722 effect(DEF dst, USE src1, USE src2);
8723 size(8);
8724 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8725 "FMOVS $src2.lo,$dst.lo" %}
8726 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8727 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8728 ins_pipe(faddD_reg_reg);
8729 %}
8730
8731 // Convert integer in high half of a double register (in the lower half of
8732 // the double register file) to double
8733 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8734 effect(DEF dst, USE src);
8735 size(4);
8736 format %{ "FITOD $src,$dst" %}
8737 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8738 ins_encode(form3_opf_rs2D_rdD(src, dst));
8739 ins_pipe(fcvtLHi2D);
8740 %}
8741
8742 // Add float double precision
8743 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8744 effect(DEF dst, USE src1, USE src2);
8745 size(4);
8746 format %{ "FADDD $src1,$src2,$dst" %}
8747 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8748 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8749 ins_pipe(faddD_reg_reg);
8750 %}
8751
8752 // Sub float double precision
8753 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8754 effect(DEF dst, USE src1, USE src2);
8755 size(4);
8756 format %{ "FSUBD $src1,$src2,$dst" %}
8757 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8758 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8759 ins_pipe(faddD_reg_reg);
8760 %}
8761
8762 // Mul float double precision
8763 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8764 effect(DEF dst, USE src1, USE src2);
8765 size(4);
8766 format %{ "FMULD $src1,$src2,$dst" %}
8767 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8768 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8769 ins_pipe(fmulD_reg_reg);
8770 %}
8771
8772 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8773 match(Set dst (ConvL2D src));
8774 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8775
8776 expand %{
8777 regD_low tmpsrc;
8778 iRegI ix43300000;
8779 iRegI ix41f00000;
8780 stackSlotL lx43300000;
8781 stackSlotL lx41f00000;
8782 regD_low dx43300000;
8783 regD dx41f00000;
8784 regD tmp1;
8785 regD_low tmp2;
8786 regD tmp3;
8787 regD tmp4;
8788
8789 stkL_to_regD(tmpsrc, src);
8790
8791 loadConI_x43300000(ix43300000);
8792 loadConI_x41f00000(ix41f00000);
8793 regI_to_stkLHi(lx43300000, ix43300000);
8794 regI_to_stkLHi(lx41f00000, ix41f00000);
8795 stkL_to_regD(dx43300000, lx43300000);
8796 stkL_to_regD(dx41f00000, lx41f00000);
8797
8798 convI2D_regDHi_regD(tmp1, tmpsrc);
8799 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8800 subD_regD_regD(tmp3, tmp2, dx43300000);
8801 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8802 addD_regD_regD(dst, tmp3, tmp4);
8803 %}
8804 %}
8805
8806 // Long to Double conversion using fast fxtof
8807 instruct convL2D_helper(regD dst, regD tmp) %{
8808 effect(DEF dst, USE tmp);
8809 size(4);
8810 format %{ "FXTOD $tmp,$dst" %}
8811 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8812 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8813 ins_pipe(fcvtL2D);
8814 %}
8815
8816 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8817 predicate(VM_Version::has_fast_fxtof());
8818 match(Set dst (ConvL2D src));
8819 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8820 expand %{
8821 regD tmp;
8822 stkL_to_regD(tmp, src);
8823 convL2D_helper(dst, tmp);
8824 %}
8825 %}
8826
8827 instruct convL2D_reg(regD dst, iRegL src) %{
8828 predicate(UseVIS >= 3);
8829 match(Set dst (ConvL2D src));
8830 expand %{
8831 regD tmp;
8832 MoveL2D_reg_reg(tmp, src);
8833 convL2D_helper(dst, tmp);
8834 %}
8835 %}
8836
8837 // Long to Float conversion using fast fxtof
8838 instruct convL2F_helper(regF dst, regD tmp) %{
8839 effect(DEF dst, USE tmp);
8840 size(4);
8841 format %{ "FXTOS $tmp,$dst" %}
8842 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8843 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8844 ins_pipe(fcvtL2F);
8845 %}
8846
8847 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8848 match(Set dst (ConvL2F src));
8849 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8850 expand %{
8851 regD tmp;
8852 stkL_to_regD(tmp, src);
8853 convL2F_helper(dst, tmp);
8854 %}
8855 %}
8856
8857 instruct convL2F_reg(regF dst, iRegL src) %{
8858 predicate(UseVIS >= 3);
8859 match(Set dst (ConvL2F src));
8860 ins_cost(DEFAULT_COST);
8861 expand %{
8862 regD tmp;
8863 MoveL2D_reg_reg(tmp, src);
8864 convL2F_helper(dst, tmp);
8865 %}
8866 %}
8867
8868 //-----------
8869
8870 instruct convL2I_reg(iRegI dst, iRegL src) %{
8871 match(Set dst (ConvL2I src));
8872 #ifndef _LP64
8873 format %{ "MOV $src.lo,$dst\t! long->int" %}
8874 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8875 ins_pipe(ialu_move_reg_I_to_L);
8876 #else
8877 size(4);
8878 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8879 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8880 ins_pipe(ialu_reg);
8881 #endif
8882 %}
8883
8884 // Register Shift Right Immediate
8885 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8886 match(Set dst (ConvL2I (RShiftL src cnt)));
8887
8888 size(4);
8889 format %{ "SRAX $src,$cnt,$dst" %}
8890 opcode(Assembler::srax_op3, Assembler::arith_op);
8891 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8892 ins_pipe(ialu_reg_imm);
8893 %}
8894
8895 // Replicate scalar to packed byte values in Double register
8896 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8897 effect(DEF dst, USE src);
8898 format %{ "SLLX $src,56,$dst\n\t"
8899 "SRLX $dst, 8,O7\n\t"
8900 "OR $dst,O7,$dst\n\t"
8901 "SRLX $dst,16,O7\n\t"
8902 "OR $dst,O7,$dst\n\t"
8903 "SRLX $dst,32,O7\n\t"
8904 "OR $dst,O7,$dst\t! replicate8B" %}
8905 ins_encode( enc_repl8b(src, dst));
8906 ins_pipe(ialu_reg);
8907 %}
8908
8909 // Replicate scalar to packed byte values in Double register
8910 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8911 match(Set dst (Replicate8B src));
8912 expand %{
8913 iRegL tmp;
8914 Repl8B_reg_helper(tmp, src);
8915 regL_to_stkD(dst, tmp);
8916 %}
8917 %}
8918
8919 // Replicate scalar constant to packed byte values in Double register
8920 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8921 match(Set dst (Replicate8B con));
8922 effect(KILL tmp);
8923 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8924 ins_encode %{
8925 // XXX This is a quick fix for 6833573.
8926 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8927 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8928 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8929 %}
8930 ins_pipe(loadConFD);
8931 %}
8932
8933 // Replicate scalar to packed char values into stack slot
8934 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8935 effect(DEF dst, USE src);
8936 format %{ "SLLX $src,48,$dst\n\t"
8937 "SRLX $dst,16,O7\n\t"
8938 "OR $dst,O7,$dst\n\t"
8939 "SRLX $dst,32,O7\n\t"
8940 "OR $dst,O7,$dst\t! replicate4C" %}
8941 ins_encode( enc_repl4s(src, dst) );
8942 ins_pipe(ialu_reg);
8943 %}
8944
8945 // Replicate scalar to packed char values into stack slot
8946 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8947 match(Set dst (Replicate4C src));
8948 expand %{
8949 iRegL tmp;
8950 Repl4C_reg_helper(tmp, src);
8951 regL_to_stkD(dst, tmp);
8952 %}
8953 %}
8954
8955 // Replicate scalar constant to packed char values in Double register
8956 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8957 match(Set dst (Replicate4C con));
8958 effect(KILL tmp);
8959 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8960 ins_encode %{
8961 // XXX This is a quick fix for 6833573.
8962 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8963 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8964 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8965 %}
8966 ins_pipe(loadConFD);
8967 %}
8968
8969 // Replicate scalar to packed short values into stack slot
8970 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8971 effect(DEF dst, USE src);
8972 format %{ "SLLX $src,48,$dst\n\t"
8973 "SRLX $dst,16,O7\n\t"
8974 "OR $dst,O7,$dst\n\t"
8975 "SRLX $dst,32,O7\n\t"
8976 "OR $dst,O7,$dst\t! replicate4S" %}
8977 ins_encode( enc_repl4s(src, dst) );
8978 ins_pipe(ialu_reg);
8979 %}
8980
8981 // Replicate scalar to packed short values into stack slot
8982 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8983 match(Set dst (Replicate4S src));
8984 expand %{
8985 iRegL tmp;
8986 Repl4S_reg_helper(tmp, src);
8987 regL_to_stkD(dst, tmp);
8988 %}
8989 %}
8990
8991 // Replicate scalar constant to packed short values in Double register
8992 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8993 match(Set dst (Replicate4S con));
8994 effect(KILL tmp);
8995 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8996 ins_encode %{
8997 // XXX This is a quick fix for 6833573.
8998 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8999 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
9000 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
9001 %}
9002 ins_pipe(loadConFD);
9003 %}
9004
9005 // Replicate scalar to packed int values in Double register
9006 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
9007 effect(DEF dst, USE src);
9008 format %{ "SLLX $src,32,$dst\n\t"
9009 "SRLX $dst,32,O7\n\t"
9010 "OR $dst,O7,$dst\t! replicate2I" %}
9011 ins_encode( enc_repl2i(src, dst));
9012 ins_pipe(ialu_reg);
9013 %}
9014
9015 // Replicate scalar to packed int values in Double register
9016 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
9017 match(Set dst (Replicate2I src));
9018 expand %{
9019 iRegL tmp;
9020 Repl2I_reg_helper(tmp, src);
9021 regL_to_stkD(dst, tmp);
9022 %}
9023 %}
9024
9025 // Replicate scalar zero constant to packed int values in Double register
9026 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
9027 match(Set dst (Replicate2I con));
9028 effect(KILL tmp);
9029 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
9030 ins_encode %{
9031 // XXX This is a quick fix for 6833573.
9032 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
9033 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
9034 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
9035 %}
9036 ins_pipe(loadConFD);
9037 %}
9038
9039 //----------Control Flow Instructions------------------------------------------
9040 // Compare Instructions
9041 // Compare Integers
9042 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
9043 match(Set icc (CmpI op1 op2));
9044 effect( DEF icc, USE op1, USE op2 );
9045
9046 size(4);
9047 format %{ "CMP $op1,$op2" %}
9048 opcode(Assembler::subcc_op3, Assembler::arith_op);
9049 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9050 ins_pipe(ialu_cconly_reg_reg);
9051 %}
9052
9053 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
9054 match(Set icc (CmpU op1 op2));
9055
9056 size(4);
9057 format %{ "CMP $op1,$op2\t! unsigned" %}
9058 opcode(Assembler::subcc_op3, Assembler::arith_op);
9059 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9060 ins_pipe(ialu_cconly_reg_reg);
9061 %}
9062
9063 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
9064 match(Set icc (CmpI op1 op2));
9065 effect( DEF icc, USE op1 );
9066
9067 size(4);
9068 format %{ "CMP $op1,$op2" %}
9069 opcode(Assembler::subcc_op3, Assembler::arith_op);
9070 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9071 ins_pipe(ialu_cconly_reg_imm);
9072 %}
9073
9074 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
9075 match(Set icc (CmpI (AndI op1 op2) zero));
9076
9077 size(4);
9078 format %{ "BTST $op2,$op1" %}
9079 opcode(Assembler::andcc_op3, Assembler::arith_op);
9080 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9081 ins_pipe(ialu_cconly_reg_reg_zero);
9082 %}
9083
9084 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
9085 match(Set icc (CmpI (AndI op1 op2) zero));
9086
9087 size(4);
9088 format %{ "BTST $op2,$op1" %}
9089 opcode(Assembler::andcc_op3, Assembler::arith_op);
9090 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9091 ins_pipe(ialu_cconly_reg_imm_zero);
9092 %}
9093
9094 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
9095 match(Set xcc (CmpL op1 op2));
9096 effect( DEF xcc, USE op1, USE op2 );
9097
9098 size(4);
9099 format %{ "CMP $op1,$op2\t\t! long" %}
9100 opcode(Assembler::subcc_op3, Assembler::arith_op);
9101 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9102 ins_pipe(ialu_cconly_reg_reg);
9103 %}
9104
9105 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
9106 match(Set xcc (CmpL op1 con));
9107 effect( DEF xcc, USE op1, USE con );
9108
9109 size(4);
9110 format %{ "CMP $op1,$con\t\t! long" %}
9111 opcode(Assembler::subcc_op3, Assembler::arith_op);
9112 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9113 ins_pipe(ialu_cconly_reg_reg);
9114 %}
9115
9116 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
9117 match(Set xcc (CmpL (AndL op1 op2) zero));
9118 effect( DEF xcc, USE op1, USE op2 );
9119
9120 size(4);
9121 format %{ "BTST $op1,$op2\t\t! long" %}
9122 opcode(Assembler::andcc_op3, Assembler::arith_op);
9123 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9124 ins_pipe(ialu_cconly_reg_reg);
9125 %}
9126
9127 // useful for checking the alignment of a pointer:
9128 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9129 match(Set xcc (CmpL (AndL op1 con) zero));
9130 effect( DEF xcc, USE op1, USE con );
9131
9132 size(4);
9133 format %{ "BTST $op1,$con\t\t! long" %}
9134 opcode(Assembler::andcc_op3, Assembler::arith_op);
9135 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9136 ins_pipe(ialu_cconly_reg_reg);
9137 %}
9138
9139 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9140 match(Set icc (CmpU op1 op2));
9141
9142 size(4);
9143 format %{ "CMP $op1,$op2\t! unsigned" %}
9144 opcode(Assembler::subcc_op3, Assembler::arith_op);
9145 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9146 ins_pipe(ialu_cconly_reg_imm);
9147 %}
9148
9149 // Compare Pointers
9150 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9151 match(Set pcc (CmpP op1 op2));
9152
9153 size(4);
9154 format %{ "CMP $op1,$op2\t! ptr" %}
9155 opcode(Assembler::subcc_op3, Assembler::arith_op);
9156 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9157 ins_pipe(ialu_cconly_reg_reg);
9158 %}
9159
9160 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9161 match(Set pcc (CmpP op1 op2));
9162
9163 size(4);
9164 format %{ "CMP $op1,$op2\t! ptr" %}
9165 opcode(Assembler::subcc_op3, Assembler::arith_op);
9166 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9167 ins_pipe(ialu_cconly_reg_imm);
9168 %}
9169
9170 // Compare Narrow oops
9171 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9172 match(Set icc (CmpN op1 op2));
9173
9174 size(4);
9175 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9176 opcode(Assembler::subcc_op3, Assembler::arith_op);
9177 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9178 ins_pipe(ialu_cconly_reg_reg);
9179 %}
9180
9181 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9182 match(Set icc (CmpN op1 op2));
9183
9184 size(4);
9185 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9186 opcode(Assembler::subcc_op3, Assembler::arith_op);
9187 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9188 ins_pipe(ialu_cconly_reg_imm);
9189 %}
9190
9191 //----------Max and Min--------------------------------------------------------
9192 // Min Instructions
9193 // Conditional move for min
9194 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9195 effect( USE_DEF op2, USE op1, USE icc );
9196
9197 size(4);
9198 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9199 opcode(Assembler::less);
9200 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9201 ins_pipe(ialu_reg_flags);
9202 %}
9203
9204 // Min Register with Register.
9205 instruct minI_eReg(iRegI op1, iRegI op2) %{
9206 match(Set op2 (MinI op1 op2));
9207 ins_cost(DEFAULT_COST*2);
9208 expand %{
9209 flagsReg icc;
9210 compI_iReg(icc,op1,op2);
9211 cmovI_reg_lt(op2,op1,icc);
9212 %}
9213 %}
9214
9215 // Max Instructions
9216 // Conditional move for max
9217 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9218 effect( USE_DEF op2, USE op1, USE icc );
9219 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9220 opcode(Assembler::greater);
9221 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9222 ins_pipe(ialu_reg_flags);
9223 %}
9224
9225 // Max Register with Register
9226 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9227 match(Set op2 (MaxI op1 op2));
9228 ins_cost(DEFAULT_COST*2);
9229 expand %{
9230 flagsReg icc;
9231 compI_iReg(icc,op1,op2);
9232 cmovI_reg_gt(op2,op1,icc);
9233 %}
9234 %}
9235
9236
9237 //----------Float Compares----------------------------------------------------
9238 // Compare floating, generate condition code
9239 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9240 match(Set fcc (CmpF src1 src2));
9241
9242 size(4);
9243 format %{ "FCMPs $fcc,$src1,$src2" %}
9244 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9245 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9246 ins_pipe(faddF_fcc_reg_reg_zero);
9247 %}
9248
9249 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9250 match(Set fcc (CmpD src1 src2));
9251
9252 size(4);
9253 format %{ "FCMPd $fcc,$src1,$src2" %}
9254 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9255 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9256 ins_pipe(faddD_fcc_reg_reg_zero);
9257 %}
9258
9259
9260 // Compare floating, generate -1,0,1
9261 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9262 match(Set dst (CmpF3 src1 src2));
9263 effect(KILL fcc0);
9264 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9265 format %{ "fcmpl $dst,$src1,$src2" %}
9266 // Primary = float
9267 opcode( true );
9268 ins_encode( floating_cmp( dst, src1, src2 ) );
9269 ins_pipe( floating_cmp );
9270 %}
9271
9272 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9273 match(Set dst (CmpD3 src1 src2));
9274 effect(KILL fcc0);
9275 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9276 format %{ "dcmpl $dst,$src1,$src2" %}
9277 // Primary = double (not float)
9278 opcode( false );
9279 ins_encode( floating_cmp( dst, src1, src2 ) );
9280 ins_pipe( floating_cmp );
9281 %}
9282
9283 //----------Branches---------------------------------------------------------
9284 // Jump
9285 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9286 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9287 match(Jump switch_val);
9288 effect(TEMP table);
9289
9290 ins_cost(350);
9291
9292 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9293 "LD [O7 + $switch_val], O7\n\t"
9294 "JUMP O7" %}
9295 ins_encode %{
9296 // Calculate table address into a register.
9297 Register table_reg;
9298 Register label_reg = O7;
9299 // If we are calculating the size of this instruction don't trust
9300 // zero offsets because they might change when
9301 // MachConstantBaseNode decides to optimize the constant table
9302 // base.
9303 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9304 table_reg = $constanttablebase;
9305 } else {
9306 table_reg = O7;
9307 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9308 __ add($constanttablebase, con_offset, table_reg);
9309 }
9310
9311 // Jump to base address + switch value
9312 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9313 __ jmp(label_reg, G0);
9314 __ delayed()->nop();
9315 %}
9316 ins_pipe(ialu_reg_reg);
9317 %}
9318
9319 // Direct Branch. Use V8 version with longer range.
9320 instruct branch(label labl) %{
9321 match(Goto);
9322 effect(USE labl);
9323
9324 size(8);
9325 ins_cost(BRANCH_COST);
9326 format %{ "BA $labl" %}
9327 ins_encode %{
9328 Label* L = $labl$$label;
9329 __ ba(*L);
9330 __ delayed()->nop();
9331 %}
9332 ins_pipe(br);
9333 %}
9334
9335 // Direct Branch, short with no delay slot
9336 instruct branch_short(label labl) %{
9337 match(Goto);
9338 predicate(UseCBCond);
9339 effect(USE labl);
9340
9341 size(4);
9342 ins_cost(BRANCH_COST);
9343 format %{ "BA $labl\t! short branch" %}
9344 ins_encode %{
9345 Label* L = $labl$$label;
9346 assert(__ use_cbcond(*L), "back to back cbcond");
9347 __ ba_short(*L);
9348 %}
9349 ins_short_branch(1);
9350 ins_avoid_back_to_back(1);
9351 ins_pipe(cbcond_reg_imm);
9352 %}
9353
9354 // Conditional Direct Branch
9355 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9356 match(If cmp icc);
9357 effect(USE labl);
9358
9359 size(8);
9360 ins_cost(BRANCH_COST);
9361 format %{ "BP$cmp $icc,$labl" %}
9362 // Prim = bits 24-22, Secnd = bits 31-30
9363 ins_encode( enc_bp( labl, cmp, icc ) );
9364 ins_pipe(br_cc);
9365 %}
9366
9367 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9368 match(If cmp icc);
9369 effect(USE labl);
9370
9371 ins_cost(BRANCH_COST);
9372 format %{ "BP$cmp $icc,$labl" %}
9373 // Prim = bits 24-22, Secnd = bits 31-30
9374 ins_encode( enc_bp( labl, cmp, icc ) );
9375 ins_pipe(br_cc);
9376 %}
9377
9378 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9379 match(If cmp pcc);
9380 effect(USE labl);
9381
9382 size(8);
9383 ins_cost(BRANCH_COST);
9384 format %{ "BP$cmp $pcc,$labl" %}
9385 ins_encode %{
9386 Label* L = $labl$$label;
9387 Assembler::Predict predict_taken =
9388 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9389
9390 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9391 __ delayed()->nop();
9392 %}
9393 ins_pipe(br_cc);
9394 %}
9395
9396 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9397 match(If cmp fcc);
9398 effect(USE labl);
9399
9400 size(8);
9401 ins_cost(BRANCH_COST);
9402 format %{ "FBP$cmp $fcc,$labl" %}
9403 ins_encode %{
9404 Label* L = $labl$$label;
9405 Assembler::Predict predict_taken =
9406 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9407
9408 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9409 __ delayed()->nop();
9410 %}
9411 ins_pipe(br_fcc);
9412 %}
9413
9414 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9415 match(CountedLoopEnd cmp icc);
9416 effect(USE labl);
9417
9418 size(8);
9419 ins_cost(BRANCH_COST);
9420 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9421 // Prim = bits 24-22, Secnd = bits 31-30
9422 ins_encode( enc_bp( labl, cmp, icc ) );
9423 ins_pipe(br_cc);
9424 %}
9425
9426 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9427 match(CountedLoopEnd cmp icc);
9428 effect(USE labl);
9429
9430 size(8);
9431 ins_cost(BRANCH_COST);
9432 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9433 // Prim = bits 24-22, Secnd = bits 31-30
9434 ins_encode( enc_bp( labl, cmp, icc ) );
9435 ins_pipe(br_cc);
9436 %}
9437
9438 // Compare and branch instructions
9439 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9440 match(If cmp (CmpI op1 op2));
9441 effect(USE labl, KILL icc);
9442
9443 size(12);
9444 ins_cost(BRANCH_COST);
9445 format %{ "CMP $op1,$op2\t! int\n\t"
9446 "BP$cmp $labl" %}
9447 ins_encode %{
9448 Label* L = $labl$$label;
9449 Assembler::Predict predict_taken =
9450 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9451 __ cmp($op1$$Register, $op2$$Register);
9452 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9453 __ delayed()->nop();
9454 %}
9455 ins_pipe(cmp_br_reg_reg);
9456 %}
9457
9458 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9459 match(If cmp (CmpI op1 op2));
9460 effect(USE labl, KILL icc);
9461
9462 size(12);
9463 ins_cost(BRANCH_COST);
9464 format %{ "CMP $op1,$op2\t! int\n\t"
9465 "BP$cmp $labl" %}
9466 ins_encode %{
9467 Label* L = $labl$$label;
9468 Assembler::Predict predict_taken =
9469 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9470 __ cmp($op1$$Register, $op2$$constant);
9471 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9472 __ delayed()->nop();
9473 %}
9474 ins_pipe(cmp_br_reg_imm);
9475 %}
9476
9477 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9478 match(If cmp (CmpU op1 op2));
9479 effect(USE labl, KILL icc);
9480
9481 size(12);
9482 ins_cost(BRANCH_COST);
9483 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9484 "BP$cmp $labl" %}
9485 ins_encode %{
9486 Label* L = $labl$$label;
9487 Assembler::Predict predict_taken =
9488 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9489 __ cmp($op1$$Register, $op2$$Register);
9490 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9491 __ delayed()->nop();
9492 %}
9493 ins_pipe(cmp_br_reg_reg);
9494 %}
9495
9496 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9497 match(If cmp (CmpU op1 op2));
9498 effect(USE labl, KILL icc);
9499
9500 size(12);
9501 ins_cost(BRANCH_COST);
9502 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9503 "BP$cmp $labl" %}
9504 ins_encode %{
9505 Label* L = $labl$$label;
9506 Assembler::Predict predict_taken =
9507 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9508 __ cmp($op1$$Register, $op2$$constant);
9509 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9510 __ delayed()->nop();
9511 %}
9512 ins_pipe(cmp_br_reg_imm);
9513 %}
9514
9515 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9516 match(If cmp (CmpL op1 op2));
9517 effect(USE labl, KILL xcc);
9518
9519 size(12);
9520 ins_cost(BRANCH_COST);
9521 format %{ "CMP $op1,$op2\t! long\n\t"
9522 "BP$cmp $labl" %}
9523 ins_encode %{
9524 Label* L = $labl$$label;
9525 Assembler::Predict predict_taken =
9526 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9527 __ cmp($op1$$Register, $op2$$Register);
9528 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9529 __ delayed()->nop();
9530 %}
9531 ins_pipe(cmp_br_reg_reg);
9532 %}
9533
9534 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9535 match(If cmp (CmpL op1 op2));
9536 effect(USE labl, KILL xcc);
9537
9538 size(12);
9539 ins_cost(BRANCH_COST);
9540 format %{ "CMP $op1,$op2\t! long\n\t"
9541 "BP$cmp $labl" %}
9542 ins_encode %{
9543 Label* L = $labl$$label;
9544 Assembler::Predict predict_taken =
9545 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9546 __ cmp($op1$$Register, $op2$$constant);
9547 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9548 __ delayed()->nop();
9549 %}
9550 ins_pipe(cmp_br_reg_imm);
9551 %}
9552
9553 // Compare Pointers and branch
9554 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9555 match(If cmp (CmpP op1 op2));
9556 effect(USE labl, KILL pcc);
9557
9558 size(12);
9559 ins_cost(BRANCH_COST);
9560 format %{ "CMP $op1,$op2\t! ptr\n\t"
9561 "B$cmp $labl" %}
9562 ins_encode %{
9563 Label* L = $labl$$label;
9564 Assembler::Predict predict_taken =
9565 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9566 __ cmp($op1$$Register, $op2$$Register);
9567 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9568 __ delayed()->nop();
9569 %}
9570 ins_pipe(cmp_br_reg_reg);
9571 %}
9572
9573 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9574 match(If cmp (CmpP op1 null));
9575 effect(USE labl, KILL pcc);
9576
9577 size(12);
9578 ins_cost(BRANCH_COST);
9579 format %{ "CMP $op1,0\t! ptr\n\t"
9580 "B$cmp $labl" %}
9581 ins_encode %{
9582 Label* L = $labl$$label;
9583 Assembler::Predict predict_taken =
9584 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9585 __ cmp($op1$$Register, G0);
9586 // bpr() is not used here since it has shorter distance.
9587 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9588 __ delayed()->nop();
9589 %}
9590 ins_pipe(cmp_br_reg_reg);
9591 %}
9592
9593 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9594 match(If cmp (CmpN op1 op2));
9595 effect(USE labl, KILL icc);
9596
9597 size(12);
9598 ins_cost(BRANCH_COST);
9599 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9600 "BP$cmp $labl" %}
9601 ins_encode %{
9602 Label* L = $labl$$label;
9603 Assembler::Predict predict_taken =
9604 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9605 __ cmp($op1$$Register, $op2$$Register);
9606 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9607 __ delayed()->nop();
9608 %}
9609 ins_pipe(cmp_br_reg_reg);
9610 %}
9611
9612 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9613 match(If cmp (CmpN op1 null));
9614 effect(USE labl, KILL icc);
9615
9616 size(12);
9617 ins_cost(BRANCH_COST);
9618 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9619 "BP$cmp $labl" %}
9620 ins_encode %{
9621 Label* L = $labl$$label;
9622 Assembler::Predict predict_taken =
9623 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9624 __ cmp($op1$$Register, G0);
9625 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9626 __ delayed()->nop();
9627 %}
9628 ins_pipe(cmp_br_reg_reg);
9629 %}
9630
9631 // Loop back branch
9632 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9633 match(CountedLoopEnd cmp (CmpI op1 op2));
9634 effect(USE labl, KILL icc);
9635
9636 size(12);
9637 ins_cost(BRANCH_COST);
9638 format %{ "CMP $op1,$op2\t! int\n\t"
9639 "BP$cmp $labl\t! Loop end" %}
9640 ins_encode %{
9641 Label* L = $labl$$label;
9642 Assembler::Predict predict_taken =
9643 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9644 __ cmp($op1$$Register, $op2$$Register);
9645 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9646 __ delayed()->nop();
9647 %}
9648 ins_pipe(cmp_br_reg_reg);
9649 %}
9650
9651 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9652 match(CountedLoopEnd cmp (CmpI op1 op2));
9653 effect(USE labl, KILL icc);
9654
9655 size(12);
9656 ins_cost(BRANCH_COST);
9657 format %{ "CMP $op1,$op2\t! int\n\t"
9658 "BP$cmp $labl\t! Loop end" %}
9659 ins_encode %{
9660 Label* L = $labl$$label;
9661 Assembler::Predict predict_taken =
9662 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9663 __ cmp($op1$$Register, $op2$$constant);
9664 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9665 __ delayed()->nop();
9666 %}
9667 ins_pipe(cmp_br_reg_imm);
9668 %}
9669
9670 // Short compare and branch instructions
9671 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9672 match(If cmp (CmpI op1 op2));
9673 predicate(UseCBCond);
9674 effect(USE labl, KILL icc);
9675
9676 size(4);
9677 ins_cost(BRANCH_COST);
9678 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9679 ins_encode %{
9680 Label* L = $labl$$label;
9681 assert(__ use_cbcond(*L), "back to back cbcond");
9682 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9683 %}
9684 ins_short_branch(1);
9685 ins_avoid_back_to_back(1);
9686 ins_pipe(cbcond_reg_reg);
9687 %}
9688
9689 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9690 match(If cmp (CmpI op1 op2));
9691 predicate(UseCBCond);
9692 effect(USE labl, KILL icc);
9693
9694 size(4);
9695 ins_cost(BRANCH_COST);
9696 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9697 ins_encode %{
9698 Label* L = $labl$$label;
9699 assert(__ use_cbcond(*L), "back to back cbcond");
9700 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9701 %}
9702 ins_short_branch(1);
9703 ins_avoid_back_to_back(1);
9704 ins_pipe(cbcond_reg_imm);
9705 %}
9706
9707 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9708 match(If cmp (CmpU op1 op2));
9709 predicate(UseCBCond);
9710 effect(USE labl, KILL icc);
9711
9712 size(4);
9713 ins_cost(BRANCH_COST);
9714 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9715 ins_encode %{
9716 Label* L = $labl$$label;
9717 assert(__ use_cbcond(*L), "back to back cbcond");
9718 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9719 %}
9720 ins_short_branch(1);
9721 ins_avoid_back_to_back(1);
9722 ins_pipe(cbcond_reg_reg);
9723 %}
9724
9725 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9726 match(If cmp (CmpU op1 op2));
9727 predicate(UseCBCond);
9728 effect(USE labl, KILL icc);
9729
9730 size(4);
9731 ins_cost(BRANCH_COST);
9732 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9733 ins_encode %{
9734 Label* L = $labl$$label;
9735 assert(__ use_cbcond(*L), "back to back cbcond");
9736 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9737 %}
9738 ins_short_branch(1);
9739 ins_avoid_back_to_back(1);
9740 ins_pipe(cbcond_reg_imm);
9741 %}
9742
9743 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9744 match(If cmp (CmpL op1 op2));
9745 predicate(UseCBCond);
9746 effect(USE labl, KILL xcc);
9747
9748 size(4);
9749 ins_cost(BRANCH_COST);
9750 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9751 ins_encode %{
9752 Label* L = $labl$$label;
9753 assert(__ use_cbcond(*L), "back to back cbcond");
9754 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9755 %}
9756 ins_short_branch(1);
9757 ins_avoid_back_to_back(1);
9758 ins_pipe(cbcond_reg_reg);
9759 %}
9760
9761 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9762 match(If cmp (CmpL op1 op2));
9763 predicate(UseCBCond);
9764 effect(USE labl, KILL xcc);
9765
9766 size(4);
9767 ins_cost(BRANCH_COST);
9768 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9769 ins_encode %{
9770 Label* L = $labl$$label;
9771 assert(__ use_cbcond(*L), "back to back cbcond");
9772 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9773 %}
9774 ins_short_branch(1);
9775 ins_avoid_back_to_back(1);
9776 ins_pipe(cbcond_reg_imm);
9777 %}
9778
9779 // Compare Pointers and branch
9780 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9781 match(If cmp (CmpP op1 op2));
9782 predicate(UseCBCond);
9783 effect(USE labl, KILL pcc);
9784
9785 size(4);
9786 ins_cost(BRANCH_COST);
9787 #ifdef _LP64
9788 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9789 #else
9790 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9791 #endif
9792 ins_encode %{
9793 Label* L = $labl$$label;
9794 assert(__ use_cbcond(*L), "back to back cbcond");
9795 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9796 %}
9797 ins_short_branch(1);
9798 ins_avoid_back_to_back(1);
9799 ins_pipe(cbcond_reg_reg);
9800 %}
9801
9802 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9803 match(If cmp (CmpP op1 null));
9804 predicate(UseCBCond);
9805 effect(USE labl, KILL pcc);
9806
9807 size(4);
9808 ins_cost(BRANCH_COST);
9809 #ifdef _LP64
9810 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9811 #else
9812 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9813 #endif
9814 ins_encode %{
9815 Label* L = $labl$$label;
9816 assert(__ use_cbcond(*L), "back to back cbcond");
9817 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9818 %}
9819 ins_short_branch(1);
9820 ins_avoid_back_to_back(1);
9821 ins_pipe(cbcond_reg_reg);
9822 %}
9823
9824 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9825 match(If cmp (CmpN op1 op2));
9826 predicate(UseCBCond);
9827 effect(USE labl, KILL icc);
9828
9829 size(4);
9830 ins_cost(BRANCH_COST);
9831 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9832 ins_encode %{
9833 Label* L = $labl$$label;
9834 assert(__ use_cbcond(*L), "back to back cbcond");
9835 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9836 %}
9837 ins_short_branch(1);
9838 ins_avoid_back_to_back(1);
9839 ins_pipe(cbcond_reg_reg);
9840 %}
9841
9842 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9843 match(If cmp (CmpN op1 null));
9844 predicate(UseCBCond);
9845 effect(USE labl, KILL icc);
9846
9847 size(4);
9848 ins_cost(BRANCH_COST);
9849 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9850 ins_encode %{
9851 Label* L = $labl$$label;
9852 assert(__ use_cbcond(*L), "back to back cbcond");
9853 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9854 %}
9855 ins_short_branch(1);
9856 ins_avoid_back_to_back(1);
9857 ins_pipe(cbcond_reg_reg);
9858 %}
9859
9860 // Loop back branch
9861 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9862 match(CountedLoopEnd cmp (CmpI op1 op2));
9863 predicate(UseCBCond);
9864 effect(USE labl, KILL icc);
9865
9866 size(4);
9867 ins_cost(BRANCH_COST);
9868 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9869 ins_encode %{
9870 Label* L = $labl$$label;
9871 assert(__ use_cbcond(*L), "back to back cbcond");
9872 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9873 %}
9874 ins_short_branch(1);
9875 ins_avoid_back_to_back(1);
9876 ins_pipe(cbcond_reg_reg);
9877 %}
9878
9879 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9880 match(CountedLoopEnd cmp (CmpI op1 op2));
9881 predicate(UseCBCond);
9882 effect(USE labl, KILL icc);
9883
9884 size(4);
9885 ins_cost(BRANCH_COST);
9886 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9887 ins_encode %{
9888 Label* L = $labl$$label;
9889 assert(__ use_cbcond(*L), "back to back cbcond");
9890 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9891 %}
9892 ins_short_branch(1);
9893 ins_avoid_back_to_back(1);
9894 ins_pipe(cbcond_reg_imm);
9895 %}
9896
9897 // Branch-on-register tests all 64 bits. We assume that values
9898 // in 64-bit registers always remains zero or sign extended
9899 // unless our code munges the high bits. Interrupts can chop
9900 // the high order bits to zero or sign at any time.
9901 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9902 match(If cmp (CmpI op1 zero));
9903 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9904 effect(USE labl);
9905
9906 size(8);
9907 ins_cost(BRANCH_COST);
9908 format %{ "BR$cmp $op1,$labl" %}
9909 ins_encode( enc_bpr( labl, cmp, op1 ) );
9910 ins_pipe(br_reg);
9911 %}
9912
9913 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9914 match(If cmp (CmpP op1 null));
9915 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9916 effect(USE labl);
9917
9918 size(8);
9919 ins_cost(BRANCH_COST);
9920 format %{ "BR$cmp $op1,$labl" %}
9921 ins_encode( enc_bpr( labl, cmp, op1 ) );
9922 ins_pipe(br_reg);
9923 %}
9924
9925 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9926 match(If cmp (CmpL op1 zero));
9927 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9928 effect(USE labl);
9929
9930 size(8);
9931 ins_cost(BRANCH_COST);
9932 format %{ "BR$cmp $op1,$labl" %}
9933 ins_encode( enc_bpr( labl, cmp, op1 ) );
9934 ins_pipe(br_reg);
9935 %}
9936
9937
9938 // ============================================================================
9939 // Long Compare
9940 //
9941 // Currently we hold longs in 2 registers. Comparing such values efficiently
9942 // is tricky. The flavor of compare used depends on whether we are testing
9943 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9944 // The GE test is the negated LT test. The LE test can be had by commuting
9945 // the operands (yielding a GE test) and then negating; negate again for the
9946 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9947 // NE test is negated from that.
9948
9949 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9950 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9951 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9952 // are collapsed internally in the ADLC's dfa-gen code. The match for
9953 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9954 // foo match ends up with the wrong leaf. One fix is to not match both
9955 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9956 // both forms beat the trinary form of long-compare and both are very useful
9957 // on Intel which has so few registers.
9958
9959 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9960 match(If cmp xcc);
9961 effect(USE labl);
9962
9963 size(8);
9964 ins_cost(BRANCH_COST);
9965 format %{ "BP$cmp $xcc,$labl" %}
9966 ins_encode %{
9967 Label* L = $labl$$label;
9968 Assembler::Predict predict_taken =
9969 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9970
9971 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9972 __ delayed()->nop();
9973 %}
9974 ins_pipe(br_cc);
9975 %}
9976
9977 // Manifest a CmpL3 result in an integer register. Very painful.
9978 // This is the test to avoid.
9979 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9980 match(Set dst (CmpL3 src1 src2) );
9981 effect( KILL ccr );
9982 ins_cost(6*DEFAULT_COST);
9983 size(24);
9984 format %{ "CMP $src1,$src2\t\t! long\n"
9985 "\tBLT,a,pn done\n"
9986 "\tMOV -1,$dst\t! delay slot\n"
9987 "\tBGT,a,pn done\n"
9988 "\tMOV 1,$dst\t! delay slot\n"
9989 "\tCLR $dst\n"
9990 "done:" %}
9991 ins_encode( cmpl_flag(src1,src2,dst) );
9992 ins_pipe(cmpL_reg);
9993 %}
9994
9995 // Conditional move
9996 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9997 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9998 ins_cost(150);
9999 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
10000 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
10001 ins_pipe(ialu_reg);
10002 %}
10003
10004 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
10005 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
10006 ins_cost(140);
10007 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
10008 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
10009 ins_pipe(ialu_imm);
10010 %}
10011
10012 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
10013 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
10014 ins_cost(150);
10015 format %{ "MOV$cmp $xcc,$src,$dst" %}
10016 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
10017 ins_pipe(ialu_reg);
10018 %}
10019
10020 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
10021 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
10022 ins_cost(140);
10023 format %{ "MOV$cmp $xcc,$src,$dst" %}
10024 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
10025 ins_pipe(ialu_imm);
10026 %}
10027
10028 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
10029 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
10030 ins_cost(150);
10031 format %{ "MOV$cmp $xcc,$src,$dst" %}
10032 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
10033 ins_pipe(ialu_reg);
10034 %}
10035
10036 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
10037 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
10038 ins_cost(150);
10039 format %{ "MOV$cmp $xcc,$src,$dst" %}
10040 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
10041 ins_pipe(ialu_reg);
10042 %}
10043
10044 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
10045 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
10046 ins_cost(140);
10047 format %{ "MOV$cmp $xcc,$src,$dst" %}
10048 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
10049 ins_pipe(ialu_imm);
10050 %}
10051
10052 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
10053 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
10054 ins_cost(150);
10055 opcode(0x101);
10056 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
10057 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10058 ins_pipe(int_conditional_float_move);
10059 %}
10060
10061 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
10062 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
10063 ins_cost(150);
10064 opcode(0x102);
10065 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
10066 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10067 ins_pipe(int_conditional_float_move);
10068 %}
10069
10070 // ============================================================================
10071 // Safepoint Instruction
10072 instruct safePoint_poll(iRegP poll) %{
10073 match(SafePoint poll);
10074 effect(USE poll);
10075
10076 size(4);
10077 #ifdef _LP64
10078 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
10079 #else
10080 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
10081 #endif
10082 ins_encode %{
10083 __ relocate(relocInfo::poll_type);
10084 __ ld_ptr($poll$$Register, 0, G0);
10085 %}
10086 ins_pipe(loadPollP);
10087 %}
10088
10089 // ============================================================================
10090 // Call Instructions
10091 // Call Java Static Instruction
10092 instruct CallStaticJavaDirect( method meth ) %{
10093 match(CallStaticJava);
10094 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
10095 effect(USE meth);
10096
10097 size(8);
10098 ins_cost(CALL_COST);
10099 format %{ "CALL,static ; NOP ==> " %}
10100 ins_encode( Java_Static_Call( meth ), call_epilog );
10101 ins_pipe(simple_call);
10102 %}
10103
10104 // Call Java Static Instruction (method handle version)
10105 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
10106 match(CallStaticJava);
10107 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
10108 effect(USE meth, KILL l7_mh_SP_save);
10109
10110 size(16);
10111 ins_cost(CALL_COST);
10112 format %{ "CALL,static/MethodHandle" %}
10113 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10114 ins_pipe(simple_call);
10115 %}
10116
10117 // Call Java Dynamic Instruction
10118 instruct CallDynamicJavaDirect( method meth ) %{
10119 match(CallDynamicJava);
10120 effect(USE meth);
10121
10122 ins_cost(CALL_COST);
10123 format %{ "SET (empty),R_G5\n\t"
10124 "CALL,dynamic ; NOP ==> " %}
10125 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10126 ins_pipe(call);
10127 %}
10128
10129 // Call Runtime Instruction
10130 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10131 match(CallRuntime);
10132 effect(USE meth, KILL l7);
10133 ins_cost(CALL_COST);
10134 format %{ "CALL,runtime" %}
10135 ins_encode( Java_To_Runtime( meth ),
10136 call_epilog, adjust_long_from_native_call );
10137 ins_pipe(simple_call);
10138 %}
10139
10140 // Call runtime without safepoint - same as CallRuntime
10141 instruct CallLeafDirect(method meth, l7RegP l7) %{
10142 match(CallLeaf);
10143 effect(USE meth, KILL l7);
10144 ins_cost(CALL_COST);
10145 format %{ "CALL,runtime leaf" %}
10146 ins_encode( Java_To_Runtime( meth ),
10147 call_epilog,
10148 adjust_long_from_native_call );
10149 ins_pipe(simple_call);
10150 %}
10151
10152 // Call runtime without safepoint - same as CallLeaf
10153 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10154 match(CallLeafNoFP);
10155 effect(USE meth, KILL l7);
10156 ins_cost(CALL_COST);
10157 format %{ "CALL,runtime leaf nofp" %}
10158 ins_encode( Java_To_Runtime( meth ),
10159 call_epilog,
10160 adjust_long_from_native_call );
10161 ins_pipe(simple_call);
10162 %}
10163
10164 // Tail Call; Jump from runtime stub to Java code.
10165 // Also known as an 'interprocedural jump'.
10166 // Target of jump will eventually return to caller.
10167 // TailJump below removes the return address.
10168 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10169 match(TailCall jump_target method_oop );
10170
10171 ins_cost(CALL_COST);
10172 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10173 ins_encode(form_jmpl(jump_target));
10174 ins_pipe(tail_call);
10175 %}
10176
10177
10178 // Return Instruction
10179 instruct Ret() %{
10180 match(Return);
10181
10182 // The epilogue node did the ret already.
10183 size(0);
10184 format %{ "! return" %}
10185 ins_encode();
10186 ins_pipe(empty);
10187 %}
10188
10189
10190 // Tail Jump; remove the return address; jump to target.
10191 // TailCall above leaves the return address around.
10192 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10193 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10194 // "restore" before this instruction (in Epilogue), we need to materialize it
10195 // in %i0.
10196 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10197 match( TailJump jump_target ex_oop );
10198 ins_cost(CALL_COST);
10199 format %{ "! discard R_O7\n\t"
10200 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10201 ins_encode(form_jmpl_set_exception_pc(jump_target));
10202 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10203 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10204 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10205 ins_pipe(tail_call);
10206 %}
10207
10208 // Create exception oop: created by stack-crawling runtime code.
10209 // Created exception is now available to this handler, and is setup
10210 // just prior to jumping to this handler. No code emitted.
10211 instruct CreateException( o0RegP ex_oop )
10212 %{
10213 match(Set ex_oop (CreateEx));
10214 ins_cost(0);
10215
10216 size(0);
10217 // use the following format syntax
10218 format %{ "! exception oop is in R_O0; no code emitted" %}
10219 ins_encode();
10220 ins_pipe(empty);
10221 %}
10222
10223
10224 // Rethrow exception:
10225 // The exception oop will come in the first argument position.
10226 // Then JUMP (not call) to the rethrow stub code.
10227 instruct RethrowException()
10228 %{
10229 match(Rethrow);
10230 ins_cost(CALL_COST);
10231
10232 // use the following format syntax
10233 format %{ "Jmp rethrow_stub" %}
10234 ins_encode(enc_rethrow);
10235 ins_pipe(tail_call);
10236 %}
10237
10238
10239 // Die now
10240 instruct ShouldNotReachHere( )
10241 %{
10242 match(Halt);
10243 ins_cost(CALL_COST);
10244
10245 size(4);
10246 // Use the following format syntax
10247 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10248 ins_encode( form2_illtrap() );
10249 ins_pipe(tail_call);
10250 %}
10251
10252 // ============================================================================
10253 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10254 // array for an instance of the superklass. Set a hidden internal cache on a
10255 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10256 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10257 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10258 match(Set index (PartialSubtypeCheck sub super));
10259 effect( KILL pcc, KILL o7 );
10260 ins_cost(DEFAULT_COST*10);
10261 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10262 ins_encode( enc_PartialSubtypeCheck() );
10263 ins_pipe(partial_subtype_check_pipe);
10264 %}
10265
10266 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10267 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10268 effect( KILL idx, KILL o7 );
10269 ins_cost(DEFAULT_COST*10);
10270 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10271 ins_encode( enc_PartialSubtypeCheck() );
10272 ins_pipe(partial_subtype_check_pipe);
10273 %}
10274
10275
10276 // ============================================================================
10277 // inlined locking and unlocking
10278
10279 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10280 match(Set pcc (FastLock object box));
10281
10282 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10283 ins_cost(100);
10284
10285 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10286 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10287 ins_pipe(long_memory_op);
10288 %}
10289
10290
10291 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10292 match(Set pcc (FastUnlock object box));
10293 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10294 ins_cost(100);
10295
10296 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10297 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10298 ins_pipe(long_memory_op);
10299 %}
10300
10301 // The encodings are generic.
10302 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10303 predicate(!use_block_zeroing(n->in(2)) );
10304 match(Set dummy (ClearArray cnt base));
10305 effect(TEMP temp, KILL ccr);
10306 ins_cost(300);
10307 format %{ "MOV $cnt,$temp\n"
10308 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10309 " BRge loop\t\t! Clearing loop\n"
10310 " STX G0,[$base+$temp]\t! delay slot" %}
10311
10312 ins_encode %{
10313 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10314 Register nof_bytes_arg = $cnt$$Register;
10315 Register nof_bytes_tmp = $temp$$Register;
10316 Register base_pointer_arg = $base$$Register;
10317
10318 Label loop;
10319 __ mov(nof_bytes_arg, nof_bytes_tmp);
10320
10321 // Loop and clear, walking backwards through the array.
10322 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10323 __ bind(loop);
10324 __ deccc(nof_bytes_tmp, 8);
10325 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10326 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10327 // %%%% this mini-loop must not cross a cache boundary!
10328 %}
10329 ins_pipe(long_memory_op);
10330 %}
10331
10332 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10333 predicate(use_block_zeroing(n->in(2)));
10334 match(Set dummy (ClearArray cnt base));
10335 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10336 ins_cost(300);
10337 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10338
10339 ins_encode %{
10340
10341 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10342 Register to = $base$$Register;
10343 Register count = $cnt$$Register;
10344
10345 Label Ldone;
10346 __ nop(); // Separate short branches
10347 // Use BIS for zeroing (temp is not used).
10348 __ bis_zeroing(to, count, G0, Ldone);
10349 __ bind(Ldone);
10350
10351 %}
10352 ins_pipe(long_memory_op);
10353 %}
10354
10355 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10356 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10357 match(Set dummy (ClearArray cnt base));
10358 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10359 ins_cost(300);
10360 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10361
10362 ins_encode %{
10363
10364 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10365 Register to = $base$$Register;
10366 Register count = $cnt$$Register;
10367 Register temp = $tmp$$Register;
10368
10369 Label Ldone;
10370 __ nop(); // Separate short branches
10371 // Use BIS for zeroing
10372 __ bis_zeroing(to, count, temp, Ldone);
10373 __ bind(Ldone);
10374
10375 %}
10376 ins_pipe(long_memory_op);
10377 %}
10378
10379 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10380 o7RegI tmp, flagsReg ccr) %{
10381 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10382 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10383 ins_cost(300);
10384 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10385 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10386 ins_pipe(long_memory_op);
10387 %}
10388
10389 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10390 o7RegI tmp, flagsReg ccr) %{
10391 match(Set result (StrEquals (Binary str1 str2) cnt));
10392 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10393 ins_cost(300);
10394 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10395 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10396 ins_pipe(long_memory_op);
10397 %}
10398
10399 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10400 o7RegI tmp2, flagsReg ccr) %{
10401 match(Set result (AryEq ary1 ary2));
10402 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10403 ins_cost(300);
10404 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10405 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10406 ins_pipe(long_memory_op);
10407 %}
10408
10409
10410 //---------- Zeros Count Instructions ------------------------------------------
10411
10412 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10413 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10414 match(Set dst (CountLeadingZerosI src));
10415 effect(TEMP dst, TEMP tmp, KILL cr);
10416
10417 // x |= (x >> 1);
10418 // x |= (x >> 2);
10419 // x |= (x >> 4);
10420 // x |= (x >> 8);
10421 // x |= (x >> 16);
10422 // return (WORDBITS - popc(x));
10423 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10424 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10425 "OR $dst,$tmp,$dst\n\t"
10426 "SRL $dst,2,$tmp\n\t"
10427 "OR $dst,$tmp,$dst\n\t"
10428 "SRL $dst,4,$tmp\n\t"
10429 "OR $dst,$tmp,$dst\n\t"
10430 "SRL $dst,8,$tmp\n\t"
10431 "OR $dst,$tmp,$dst\n\t"
10432 "SRL $dst,16,$tmp\n\t"
10433 "OR $dst,$tmp,$dst\n\t"
10434 "POPC $dst,$dst\n\t"
10435 "MOV 32,$tmp\n\t"
10436 "SUB $tmp,$dst,$dst" %}
10437 ins_encode %{
10438 Register Rdst = $dst$$Register;
10439 Register Rsrc = $src$$Register;
10440 Register Rtmp = $tmp$$Register;
10441 __ srl(Rsrc, 1, Rtmp);
10442 __ srl(Rsrc, 0, Rdst);
10443 __ or3(Rdst, Rtmp, Rdst);
10444 __ srl(Rdst, 2, Rtmp);
10445 __ or3(Rdst, Rtmp, Rdst);
10446 __ srl(Rdst, 4, Rtmp);
10447 __ or3(Rdst, Rtmp, Rdst);
10448 __ srl(Rdst, 8, Rtmp);
10449 __ or3(Rdst, Rtmp, Rdst);
10450 __ srl(Rdst, 16, Rtmp);
10451 __ or3(Rdst, Rtmp, Rdst);
10452 __ popc(Rdst, Rdst);
10453 __ mov(BitsPerInt, Rtmp);
10454 __ sub(Rtmp, Rdst, Rdst);
10455 %}
10456 ins_pipe(ialu_reg);
10457 %}
10458
10459 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10460 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10461 match(Set dst (CountLeadingZerosL src));
10462 effect(TEMP dst, TEMP tmp, KILL cr);
10463
10464 // x |= (x >> 1);
10465 // x |= (x >> 2);
10466 // x |= (x >> 4);
10467 // x |= (x >> 8);
10468 // x |= (x >> 16);
10469 // x |= (x >> 32);
10470 // return (WORDBITS - popc(x));
10471 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10472 "OR $src,$tmp,$dst\n\t"
10473 "SRLX $dst,2,$tmp\n\t"
10474 "OR $dst,$tmp,$dst\n\t"
10475 "SRLX $dst,4,$tmp\n\t"
10476 "OR $dst,$tmp,$dst\n\t"
10477 "SRLX $dst,8,$tmp\n\t"
10478 "OR $dst,$tmp,$dst\n\t"
10479 "SRLX $dst,16,$tmp\n\t"
10480 "OR $dst,$tmp,$dst\n\t"
10481 "SRLX $dst,32,$tmp\n\t"
10482 "OR $dst,$tmp,$dst\n\t"
10483 "POPC $dst,$dst\n\t"
10484 "MOV 64,$tmp\n\t"
10485 "SUB $tmp,$dst,$dst" %}
10486 ins_encode %{
10487 Register Rdst = $dst$$Register;
10488 Register Rsrc = $src$$Register;
10489 Register Rtmp = $tmp$$Register;
10490 __ srlx(Rsrc, 1, Rtmp);
10491 __ or3( Rsrc, Rtmp, Rdst);
10492 __ srlx(Rdst, 2, Rtmp);
10493 __ or3( Rdst, Rtmp, Rdst);
10494 __ srlx(Rdst, 4, Rtmp);
10495 __ or3( Rdst, Rtmp, Rdst);
10496 __ srlx(Rdst, 8, Rtmp);
10497 __ or3( Rdst, Rtmp, Rdst);
10498 __ srlx(Rdst, 16, Rtmp);
10499 __ or3( Rdst, Rtmp, Rdst);
10500 __ srlx(Rdst, 32, Rtmp);
10501 __ or3( Rdst, Rtmp, Rdst);
10502 __ popc(Rdst, Rdst);
10503 __ mov(BitsPerLong, Rtmp);
10504 __ sub(Rtmp, Rdst, Rdst);
10505 %}
10506 ins_pipe(ialu_reg);
10507 %}
10508
10509 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10510 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10511 match(Set dst (CountTrailingZerosI src));
10512 effect(TEMP dst, KILL cr);
10513
10514 // return popc(~x & (x - 1));
10515 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10516 "ANDN $dst,$src,$dst\n\t"
10517 "SRL $dst,R_G0,$dst\n\t"
10518 "POPC $dst,$dst" %}
10519 ins_encode %{
10520 Register Rdst = $dst$$Register;
10521 Register Rsrc = $src$$Register;
10522 __ sub(Rsrc, 1, Rdst);
10523 __ andn(Rdst, Rsrc, Rdst);
10524 __ srl(Rdst, G0, Rdst);
10525 __ popc(Rdst, Rdst);
10526 %}
10527 ins_pipe(ialu_reg);
10528 %}
10529
10530 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10531 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10532 match(Set dst (CountTrailingZerosL src));
10533 effect(TEMP dst, KILL cr);
10534
10535 // return popc(~x & (x - 1));
10536 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10537 "ANDN $dst,$src,$dst\n\t"
10538 "POPC $dst,$dst" %}
10539 ins_encode %{
10540 Register Rdst = $dst$$Register;
10541 Register Rsrc = $src$$Register;
10542 __ sub(Rsrc, 1, Rdst);
10543 __ andn(Rdst, Rsrc, Rdst);
10544 __ popc(Rdst, Rdst);
10545 %}
10546 ins_pipe(ialu_reg);
10547 %}
10548
10549
10550 //---------- Population Count Instructions -------------------------------------
10551
10552 instruct popCountI(iRegI dst, iRegI src) %{
10553 predicate(UsePopCountInstruction);
10554 match(Set dst (PopCountI src));
10555
10556 format %{ "POPC $src, $dst" %}
10557 ins_encode %{
10558 __ popc($src$$Register, $dst$$Register);
10559 %}
10560 ins_pipe(ialu_reg);
10561 %}
10562
10563 // Note: Long.bitCount(long) returns an int.
10564 instruct popCountL(iRegI dst, iRegL src) %{
10565 predicate(UsePopCountInstruction);
10566 match(Set dst (PopCountL src));
10567
10568 format %{ "POPC $src, $dst" %}
10569 ins_encode %{
10570 __ popc($src$$Register, $dst$$Register);
10571 %}
10572 ins_pipe(ialu_reg);
10573 %}
10574
10575
10576 // ============================================================================
10577 //------------Bytes reverse--------------------------------------------------
10578
10579 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10580 match(Set dst (ReverseBytesI src));
10581
10582 // Op cost is artificially doubled to make sure that load or store
10583 // instructions are preferred over this one which requires a spill
10584 // onto a stack slot.
10585 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10586 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10587
10588 ins_encode %{
10589 __ set($src$$disp + STACK_BIAS, O7);
10590 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10591 %}
10592 ins_pipe( iload_mem );
10593 %}
10594
10595 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10596 match(Set dst (ReverseBytesL src));
10597
10598 // Op cost is artificially doubled to make sure that load or store
10599 // instructions are preferred over this one which requires a spill
10600 // onto a stack slot.
10601 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10602 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10603
10604 ins_encode %{
10605 __ set($src$$disp + STACK_BIAS, O7);
10606 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10607 %}
10608 ins_pipe( iload_mem );
10609 %}
10610
10611 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10612 match(Set dst (ReverseBytesUS src));
10613
10614 // Op cost is artificially doubled to make sure that load or store
10615 // instructions are preferred over this one which requires a spill
10616 // onto a stack slot.
10617 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10618 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10619
10620 ins_encode %{
10621 // the value was spilled as an int so bias the load
10622 __ set($src$$disp + STACK_BIAS + 2, O7);
10623 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10624 %}
10625 ins_pipe( iload_mem );
10626 %}
10627
10628 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10629 match(Set dst (ReverseBytesS src));
10630
10631 // Op cost is artificially doubled to make sure that load or store
10632 // instructions are preferred over this one which requires a spill
10633 // onto a stack slot.
10634 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10635 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10636
10637 ins_encode %{
10638 // the value was spilled as an int so bias the load
10639 __ set($src$$disp + STACK_BIAS + 2, O7);
10640 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10641 %}
10642 ins_pipe( iload_mem );
10643 %}
10644
10645 // Load Integer reversed byte order
10646 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10647 match(Set dst (ReverseBytesI (LoadI src)));
10648
10649 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10650 size(4);
10651 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10652
10653 ins_encode %{
10654 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10655 %}
10656 ins_pipe(iload_mem);
10657 %}
10658
10659 // Load Long - aligned and reversed
10660 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10661 match(Set dst (ReverseBytesL (LoadL src)));
10662
10663 ins_cost(MEMORY_REF_COST);
10664 size(4);
10665 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10666
10667 ins_encode %{
10668 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10669 %}
10670 ins_pipe(iload_mem);
10671 %}
10672
10673 // Load unsigned short / char reversed byte order
10674 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10675 match(Set dst (ReverseBytesUS (LoadUS src)));
10676
10677 ins_cost(MEMORY_REF_COST);
10678 size(4);
10679 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10680
10681 ins_encode %{
10682 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10683 %}
10684 ins_pipe(iload_mem);
10685 %}
10686
10687 // Load short reversed byte order
10688 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10689 match(Set dst (ReverseBytesS (LoadS src)));
10690
10691 ins_cost(MEMORY_REF_COST);
10692 size(4);
10693 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10694
10695 ins_encode %{
10696 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10697 %}
10698 ins_pipe(iload_mem);
10699 %}
10700
10701 // Store Integer reversed byte order
10702 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10703 match(Set dst (StoreI dst (ReverseBytesI src)));
10704
10705 ins_cost(MEMORY_REF_COST);
10706 size(4);
10707 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10708
10709 ins_encode %{
10710 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10711 %}
10712 ins_pipe(istore_mem_reg);
10713 %}
10714
10715 // Store Long reversed byte order
10716 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10717 match(Set dst (StoreL dst (ReverseBytesL src)));
10718
10719 ins_cost(MEMORY_REF_COST);
10720 size(4);
10721 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10722
10723 ins_encode %{
10724 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10725 %}
10726 ins_pipe(istore_mem_reg);
10727 %}
10728
10729 // Store unsighed short/char reversed byte order
10730 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10731 match(Set dst (StoreC dst (ReverseBytesUS src)));
10732
10733 ins_cost(MEMORY_REF_COST);
10734 size(4);
10735 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10736
10737 ins_encode %{
10738 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10739 %}
10740 ins_pipe(istore_mem_reg);
10741 %}
10742
10743 // Store short reversed byte order
10744 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10745 match(Set dst (StoreC dst (ReverseBytesS src)));
10746
10747 ins_cost(MEMORY_REF_COST);
10748 size(4);
10749 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10750
10751 ins_encode %{
10752 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10753 %}
10754 ins_pipe(istore_mem_reg);
10755 %}
10756
10757 //----------PEEPHOLE RULES-----------------------------------------------------
10758 // These must follow all instruction definitions as they use the names
10759 // defined in the instructions definitions.
10760 //
10761 // peepmatch ( root_instr_name [preceding_instruction]* );
10762 //
10763 // peepconstraint %{
10764 // (instruction_number.operand_name relational_op instruction_number.operand_name
10765 // [, ...] );
10766 // // instruction numbers are zero-based using left to right order in peepmatch
10767 //
10768 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10769 // // provide an instruction_number.operand_name for each operand that appears
10770 // // in the replacement instruction's match rule
10771 //
10772 // ---------VM FLAGS---------------------------------------------------------
10773 //
10774 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10775 //
10776 // Each peephole rule is given an identifying number starting with zero and
10777 // increasing by one in the order seen by the parser. An individual peephole
10778 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10779 // on the command-line.
10780 //
10781 // ---------CURRENT LIMITATIONS----------------------------------------------
10782 //
10783 // Only match adjacent instructions in same basic block
10784 // Only equality constraints
10785 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10786 // Only one replacement instruction
10787 //
10788 // ---------EXAMPLE----------------------------------------------------------
10789 //
10790 // // pertinent parts of existing instructions in architecture description
10791 // instruct movI(eRegI dst, eRegI src) %{
10792 // match(Set dst (CopyI src));
10793 // %}
10794 //
10795 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10796 // match(Set dst (AddI dst src));
10797 // effect(KILL cr);
10798 // %}
10799 //
10800 // // Change (inc mov) to lea
10801 // peephole %{
10802 // // increment preceeded by register-register move
10803 // peepmatch ( incI_eReg movI );
10804 // // require that the destination register of the increment
10805 // // match the destination register of the move
10806 // peepconstraint ( 0.dst == 1.dst );
10807 // // construct a replacement instruction that sets
10808 // // the destination to ( move's source register + one )
10809 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10810 // %}
10811 //
10812
10813 // // Change load of spilled value to only a spill
10814 // instruct storeI(memory mem, eRegI src) %{
10815 // match(Set mem (StoreI mem src));
10816 // %}
10817 //
10818 // instruct loadI(eRegI dst, memory mem) %{
10819 // match(Set dst (LoadI mem));
10820 // %}
10821 //
10822 // peephole %{
10823 // peepmatch ( loadI storeI );
10824 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10825 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10826 // %}
10827
10828 //----------SMARTSPILL RULES---------------------------------------------------
10829 // These must follow all instruction definitions as they use the names
10830 // defined in the instructions definitions.
10831 //
10832 // SPARC will probably not have any of these rules due to RISC instruction set.
10833
10834 //----------PIPELINE-----------------------------------------------------------
10835 // Rules which define the behavior of the target architectures pipeline.