1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 int bit_width = width * 8;
682 jlong elt_val = con;
683 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
684 jlong val = elt_val;
685 for (int i = 0; i < count - 1; i++) {
686 val <<= bit_width;
687 val |= elt_val;
688 }
689 jdouble dval = *((jdouble*) &val); // coerce to double type
690 return dval;
691 }
692
693 // Standard Sparc opcode form2 field breakdown
694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
695 f0 &= (1<<19)-1; // Mask displacement to 19 bits
696 int op = (f30 << 30) |
697 (f29 << 29) |
698 (f25 << 25) |
699 (f22 << 22) |
700 (f20 << 20) |
701 (f19 << 19) |
702 (f0 << 0);
703 cbuf.insts()->emit_int32(op);
704 }
705
706 // Standard Sparc opcode form2 field breakdown
707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
708 f0 >>= 10; // Drop 10 bits
709 f0 &= (1<<22)-1; // Mask displacement to 22 bits
710 int op = (f30 << 30) |
711 (f25 << 25) |
712 (f22 << 22) |
824 }
825
826 if (ld_op) {
827 // a Load
828 // inputs are (0:control, 1:memory, 2:address)
829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
830 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
843 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
845 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
846 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
847 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
848 !(n->rule() == loadUB_rule)) {
849 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
850 }
851 } else if (st_op) {
852 // a Store
853 // inputs are (0:control, 1:memory, 2:address, 3:value)
854 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
855 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
856 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
857 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
858 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
860 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
862 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
863 verify_oops_warning(n, n->ideal_Opcode(), st_op);
864 }
865 }
866
867 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
868 Node* addr = n->in(2);
869 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
870 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
871 if (atype != NULL) {
872 intptr_t offset = get_offset_from_base(n, atype, disp32);
873 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
874 if (offset != offset_2) {
875 get_offset_from_base(n, atype, disp32);
876 get_offset_from_base_2(n, atype, disp32);
877 }
878 assert(offset == offset_2, "different offsets");
879 if (offset == disp32) {
880 // we now know that src1 is a true oop pointer
881 is_verified_oop_base = true;
1833 case Op_CountTrailingZerosI:
1834 case Op_CountTrailingZerosL:
1835 case Op_PopCountI:
1836 case Op_PopCountL:
1837 if (!UsePopCountInstruction)
1838 return false;
1839 break;
1840 }
1841
1842 return true; // Per default match rules are supported.
1843 }
1844
1845 int Matcher::regnum_to_fpu_offset(int regnum) {
1846 return regnum - 32; // The FP registers are in the second chunk
1847 }
1848
1849 #ifdef ASSERT
1850 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1851 #endif
1852
1853 // Vector width in bytes
1854 const uint Matcher::vector_width_in_bytes(void) {
1855 return 8;
1856 }
1857
1858 // Vector ideal reg
1859 const uint Matcher::vector_ideal_reg(void) {
1860 return Op_RegD;
1861 }
1862
1863 // USII supports fxtof through the whole range of number, USIII doesn't
1864 const bool Matcher::convL2FSupported(void) {
1865 return VM_Version::has_fast_fxtof();
1866 }
1867
1868 // Is this branch offset short enough that a short branch can be used?
1869 //
1870 // NOTE: If the platform does not provide any short branch variants, then
1871 // this method should return false for offset 0.
1872 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1873 // The passed offset is relative to address of the branch.
1874 // Don't need to adjust the offset.
1875 return UseCBCond && Assembler::is_simm12(offset);
1876 }
1877
1878 const bool Matcher::isSimpleConstant64(jlong value) {
1879 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1880 // Depends on optimizations in MacroAssembler::setx.
1881 int hi = (int)(value >> 32);
1882 int lo = (int)(value & ~0);
5916 __ ldx($mem$$Address, $dst$$Register);
5917 %}
5918 ins_pipe(iload_mem);
5919 %}
5920
5921 // Load Long - UNaligned
5922 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5923 match(Set dst (LoadL_unaligned mem));
5924 effect(KILL tmp);
5925 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5926 size(16);
5927 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5928 "\tLDUW $mem ,$dst\n"
5929 "\tSLLX #32, $dst, $dst\n"
5930 "\tOR $dst, R_O7, $dst" %}
5931 opcode(Assembler::lduw_op3);
5932 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5933 ins_pipe(iload_mem);
5934 %}
5935
5936 // Load Aligned Packed Byte into a Double Register
5937 instruct loadA8B(regD dst, memory mem) %{
5938 match(Set dst (Load8B mem));
5939 ins_cost(MEMORY_REF_COST);
5940 size(4);
5941 format %{ "LDDF $mem,$dst\t! packed8B" %}
5942 opcode(Assembler::lddf_op3);
5943 ins_encode(simple_form3_mem_reg( mem, dst ) );
5944 ins_pipe(floadD_mem);
5945 %}
5946
5947 // Load Aligned Packed Char into a Double Register
5948 instruct loadA4C(regD dst, memory mem) %{
5949 match(Set dst (Load4C mem));
5950 ins_cost(MEMORY_REF_COST);
5951 size(4);
5952 format %{ "LDDF $mem,$dst\t! packed4C" %}
5953 opcode(Assembler::lddf_op3);
5954 ins_encode(simple_form3_mem_reg( mem, dst ) );
5955 ins_pipe(floadD_mem);
5956 %}
5957
5958 // Load Aligned Packed Short into a Double Register
5959 instruct loadA4S(regD dst, memory mem) %{
5960 match(Set dst (Load4S mem));
5961 ins_cost(MEMORY_REF_COST);
5962 size(4);
5963 format %{ "LDDF $mem,$dst\t! packed4S" %}
5964 opcode(Assembler::lddf_op3);
5965 ins_encode(simple_form3_mem_reg( mem, dst ) );
5966 ins_pipe(floadD_mem);
5967 %}
5968
5969 // Load Aligned Packed Int into a Double Register
5970 instruct loadA2I(regD dst, memory mem) %{
5971 match(Set dst (Load2I mem));
5972 ins_cost(MEMORY_REF_COST);
5973 size(4);
5974 format %{ "LDDF $mem,$dst\t! packed2I" %}
5975 opcode(Assembler::lddf_op3);
5976 ins_encode(simple_form3_mem_reg( mem, dst ) );
5977 ins_pipe(floadD_mem);
5978 %}
5979
5980 // Load Range
5981 instruct loadRange(iRegI dst, memory mem) %{
5982 match(Set dst (LoadRange mem));
5983 ins_cost(MEMORY_REF_COST);
5984
5985 size(4);
5986 format %{ "LDUW $mem,$dst\t! range" %}
5987 opcode(Assembler::lduw_op3);
5988 ins_encode(simple_form3_mem_reg( mem, dst ) );
5989 ins_pipe(iload_mem);
5990 %}
5991
5992 // Load Integer into %f register (for fitos/fitod)
5993 instruct loadI_freg(regF dst, memory mem) %{
5994 match(Set dst (LoadI mem));
5995 ins_cost(MEMORY_REF_COST);
5996 size(4);
5997
5998 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5999 opcode(Assembler::ldf_op3);
6583 ins_cost(MEMORY_REF_COST);
6584
6585 size(4);
6586 format %{ "STF $src,$mem" %}
6587 opcode(Assembler::stf_op3);
6588 ins_encode(simple_form3_mem_reg( mem, src ) );
6589 ins_pipe(fstoreF_mem_reg);
6590 %}
6591
6592 instruct storeF0( memory mem, immF0 src) %{
6593 match(Set mem (StoreF mem src));
6594 ins_cost(MEMORY_REF_COST);
6595
6596 size(4);
6597 format %{ "STW $src,$mem\t! storeF0" %}
6598 opcode(Assembler::stw_op3);
6599 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6600 ins_pipe(fstoreF_mem_zero);
6601 %}
6602
6603 // Store Aligned Packed Bytes in Double register to memory
6604 instruct storeA8B(memory mem, regD src) %{
6605 match(Set mem (Store8B mem src));
6606 ins_cost(MEMORY_REF_COST);
6607 size(4);
6608 format %{ "STDF $src,$mem\t! packed8B" %}
6609 opcode(Assembler::stdf_op3);
6610 ins_encode(simple_form3_mem_reg( mem, src ) );
6611 ins_pipe(fstoreD_mem_reg);
6612 %}
6613
6614 // Convert oop pointer into compressed form
6615 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6616 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6617 match(Set dst (EncodeP src));
6618 format %{ "encode_heap_oop $src, $dst" %}
6619 ins_encode %{
6620 __ encode_heap_oop($src$$Register, $dst$$Register);
6621 %}
6622 ins_pipe(ialu_reg);
6623 %}
6624
6625 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6626 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6627 match(Set dst (EncodeP src));
6628 format %{ "encode_heap_oop_not_null $src, $dst" %}
6629 ins_encode %{
6630 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6631 %}
6632 ins_pipe(ialu_reg);
6633 %}
6638 match(Set dst (DecodeN src));
6639 format %{ "decode_heap_oop $src, $dst" %}
6640 ins_encode %{
6641 __ decode_heap_oop($src$$Register, $dst$$Register);
6642 %}
6643 ins_pipe(ialu_reg);
6644 %}
6645
6646 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6647 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6648 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6649 match(Set dst (DecodeN src));
6650 format %{ "decode_heap_oop_not_null $src, $dst" %}
6651 ins_encode %{
6652 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6653 %}
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657
6658 // Store Zero into Aligned Packed Bytes
6659 instruct storeA8B0(memory mem, immI0 zero) %{
6660 match(Set mem (Store8B mem zero));
6661 ins_cost(MEMORY_REF_COST);
6662 size(4);
6663 format %{ "STX $zero,$mem\t! packed8B" %}
6664 opcode(Assembler::stx_op3);
6665 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6666 ins_pipe(fstoreD_mem_zero);
6667 %}
6668
6669 // Store Aligned Packed Chars/Shorts in Double register to memory
6670 instruct storeA4C(memory mem, regD src) %{
6671 match(Set mem (Store4C mem src));
6672 ins_cost(MEMORY_REF_COST);
6673 size(4);
6674 format %{ "STDF $src,$mem\t! packed4C" %}
6675 opcode(Assembler::stdf_op3);
6676 ins_encode(simple_form3_mem_reg( mem, src ) );
6677 ins_pipe(fstoreD_mem_reg);
6678 %}
6679
6680 // Store Zero into Aligned Packed Chars/Shorts
6681 instruct storeA4C0(memory mem, immI0 zero) %{
6682 match(Set mem (Store4C mem (Replicate4C zero)));
6683 ins_cost(MEMORY_REF_COST);
6684 size(4);
6685 format %{ "STX $zero,$mem\t! packed4C" %}
6686 opcode(Assembler::stx_op3);
6687 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6688 ins_pipe(fstoreD_mem_zero);
6689 %}
6690
6691 // Store Aligned Packed Ints in Double register to memory
6692 instruct storeA2I(memory mem, regD src) %{
6693 match(Set mem (Store2I mem src));
6694 ins_cost(MEMORY_REF_COST);
6695 size(4);
6696 format %{ "STDF $src,$mem\t! packed2I" %}
6697 opcode(Assembler::stdf_op3);
6698 ins_encode(simple_form3_mem_reg( mem, src ) );
6699 ins_pipe(fstoreD_mem_reg);
6700 %}
6701
6702 // Store Zero into Aligned Packed Ints
6703 instruct storeA2I0(memory mem, immI0 zero) %{
6704 match(Set mem (Store2I mem zero));
6705 ins_cost(MEMORY_REF_COST);
6706 size(4);
6707 format %{ "STX $zero,$mem\t! packed2I" %}
6708 opcode(Assembler::stx_op3);
6709 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6710 ins_pipe(fstoreD_mem_zero);
6711 %}
6712
6713
6714 //----------MemBar Instructions-----------------------------------------------
6715 // Memory barrier flavors
6716
6717 instruct membar_acquire() %{
6718 match(MemBarAcquire);
6719 ins_cost(4*MEMORY_REF_COST);
6720
6721 size(0);
6722 format %{ "MEMBAR-acquire" %}
6723 ins_encode( enc_membar_acquire );
6724 ins_pipe(long_memory_op);
6725 %}
6726
6727 instruct membar_acquire_lock() %{
6728 match(MemBarAcquireLock);
6729 ins_cost(0);
6730
6731 size(0);
6732 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6733 ins_encode( );
8875 ins_pipe(ialu_move_reg_I_to_L);
8876 #else
8877 size(4);
8878 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8879 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8880 ins_pipe(ialu_reg);
8881 #endif
8882 %}
8883
8884 // Register Shift Right Immediate
8885 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8886 match(Set dst (ConvL2I (RShiftL src cnt)));
8887
8888 size(4);
8889 format %{ "SRAX $src,$cnt,$dst" %}
8890 opcode(Assembler::srax_op3, Assembler::arith_op);
8891 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8892 ins_pipe(ialu_reg_imm);
8893 %}
8894
8895 // Replicate scalar to packed byte values in Double register
8896 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8897 effect(DEF dst, USE src);
8898 format %{ "SLLX $src,56,$dst\n\t"
8899 "SRLX $dst, 8,O7\n\t"
8900 "OR $dst,O7,$dst\n\t"
8901 "SRLX $dst,16,O7\n\t"
8902 "OR $dst,O7,$dst\n\t"
8903 "SRLX $dst,32,O7\n\t"
8904 "OR $dst,O7,$dst\t! replicate8B" %}
8905 ins_encode( enc_repl8b(src, dst));
8906 ins_pipe(ialu_reg);
8907 %}
8908
8909 // Replicate scalar to packed byte values in Double register
8910 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8911 match(Set dst (Replicate8B src));
8912 expand %{
8913 iRegL tmp;
8914 Repl8B_reg_helper(tmp, src);
8915 regL_to_stkD(dst, tmp);
8916 %}
8917 %}
8918
8919 // Replicate scalar constant to packed byte values in Double register
8920 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8921 match(Set dst (Replicate8B con));
8922 effect(KILL tmp);
8923 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8924 ins_encode %{
8925 // XXX This is a quick fix for 6833573.
8926 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8927 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8928 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8929 %}
8930 ins_pipe(loadConFD);
8931 %}
8932
8933 // Replicate scalar to packed char values into stack slot
8934 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8935 effect(DEF dst, USE src);
8936 format %{ "SLLX $src,48,$dst\n\t"
8937 "SRLX $dst,16,O7\n\t"
8938 "OR $dst,O7,$dst\n\t"
8939 "SRLX $dst,32,O7\n\t"
8940 "OR $dst,O7,$dst\t! replicate4C" %}
8941 ins_encode( enc_repl4s(src, dst) );
8942 ins_pipe(ialu_reg);
8943 %}
8944
8945 // Replicate scalar to packed char values into stack slot
8946 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8947 match(Set dst (Replicate4C src));
8948 expand %{
8949 iRegL tmp;
8950 Repl4C_reg_helper(tmp, src);
8951 regL_to_stkD(dst, tmp);
8952 %}
8953 %}
8954
8955 // Replicate scalar constant to packed char values in Double register
8956 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8957 match(Set dst (Replicate4C con));
8958 effect(KILL tmp);
8959 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8960 ins_encode %{
8961 // XXX This is a quick fix for 6833573.
8962 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8963 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8964 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8965 %}
8966 ins_pipe(loadConFD);
8967 %}
8968
8969 // Replicate scalar to packed short values into stack slot
8970 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8971 effect(DEF dst, USE src);
8972 format %{ "SLLX $src,48,$dst\n\t"
8973 "SRLX $dst,16,O7\n\t"
8974 "OR $dst,O7,$dst\n\t"
8975 "SRLX $dst,32,O7\n\t"
8976 "OR $dst,O7,$dst\t! replicate4S" %}
8977 ins_encode( enc_repl4s(src, dst) );
8978 ins_pipe(ialu_reg);
8979 %}
8980
8981 // Replicate scalar to packed short values into stack slot
8982 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8983 match(Set dst (Replicate4S src));
8984 expand %{
8985 iRegL tmp;
8986 Repl4S_reg_helper(tmp, src);
8987 regL_to_stkD(dst, tmp);
8988 %}
8989 %}
8990
8991 // Replicate scalar constant to packed short values in Double register
8992 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8993 match(Set dst (Replicate4S con));
8994 effect(KILL tmp);
8995 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8996 ins_encode %{
8997 // XXX This is a quick fix for 6833573.
8998 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8999 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
9000 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
9001 %}
9002 ins_pipe(loadConFD);
9003 %}
9004
9005 // Replicate scalar to packed int values in Double register
9006 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
9007 effect(DEF dst, USE src);
9008 format %{ "SLLX $src,32,$dst\n\t"
9009 "SRLX $dst,32,O7\n\t"
9010 "OR $dst,O7,$dst\t! replicate2I" %}
9011 ins_encode( enc_repl2i(src, dst));
9012 ins_pipe(ialu_reg);
9013 %}
9014
9015 // Replicate scalar to packed int values in Double register
9016 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
9017 match(Set dst (Replicate2I src));
9018 expand %{
9019 iRegL tmp;
9020 Repl2I_reg_helper(tmp, src);
9021 regL_to_stkD(dst, tmp);
9022 %}
9023 %}
9024
9025 // Replicate scalar zero constant to packed int values in Double register
9026 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
9027 match(Set dst (Replicate2I con));
9028 effect(KILL tmp);
9029 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
9030 ins_encode %{
9031 // XXX This is a quick fix for 6833573.
9032 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
9033 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
9034 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
9035 %}
9036 ins_pipe(loadConFD);
9037 %}
9038
9039 //----------Control Flow Instructions------------------------------------------
9040 // Compare Instructions
9041 // Compare Integers
9042 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
9043 match(Set icc (CmpI op1 op2));
9044 effect( DEF icc, USE op1, USE op2 );
9045
9046 size(4);
9047 format %{ "CMP $op1,$op2" %}
9048 opcode(Assembler::subcc_op3, Assembler::arith_op);
9049 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9050 ins_pipe(ialu_cconly_reg_reg);
9051 %}
9052
9053 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
9054 match(Set icc (CmpU op1 op2));
9055
9056 size(4);
9057 format %{ "CMP $op1,$op2\t! unsigned" %}
9058 opcode(Assembler::subcc_op3, Assembler::arith_op);
10737 ins_encode %{
10738 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10739 %}
10740 ins_pipe(istore_mem_reg);
10741 %}
10742
10743 // Store short reversed byte order
10744 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10745 match(Set dst (StoreC dst (ReverseBytesS src)));
10746
10747 ins_cost(MEMORY_REF_COST);
10748 size(4);
10749 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10750
10751 ins_encode %{
10752 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10753 %}
10754 ins_pipe(istore_mem_reg);
10755 %}
10756
10757 //----------PEEPHOLE RULES-----------------------------------------------------
10758 // These must follow all instruction definitions as they use the names
10759 // defined in the instructions definitions.
10760 //
10761 // peepmatch ( root_instr_name [preceding_instruction]* );
10762 //
10763 // peepconstraint %{
10764 // (instruction_number.operand_name relational_op instruction_number.operand_name
10765 // [, ...] );
10766 // // instruction numbers are zero-based using left to right order in peepmatch
10767 //
10768 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10769 // // provide an instruction_number.operand_name for each operand that appears
10770 // // in the replacement instruction's match rule
10771 //
10772 // ---------VM FLAGS---------------------------------------------------------
10773 //
10774 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10775 //
10776 // Each peephole rule is given an identifying number starting with zero and
|
1 //
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
843 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
844 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
849 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
852 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
853 !(n->rule() == loadUB_rule)) {
854 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
855 }
856 } else if (st_op) {
857 // a Store
858 // inputs are (0:control, 1:memory, 2:address, 3:value)
859 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
860 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
861 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
862 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
864 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
865 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
866 verify_oops_warning(n, n->ideal_Opcode(), st_op);
867 }
868 }
869
870 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
871 Node* addr = n->in(2);
872 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
873 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
874 if (atype != NULL) {
875 intptr_t offset = get_offset_from_base(n, atype, disp32);
876 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
877 if (offset != offset_2) {
878 get_offset_from_base(n, atype, disp32);
879 get_offset_from_base_2(n, atype, disp32);
880 }
881 assert(offset == offset_2, "different offsets");
882 if (offset == disp32) {
883 // we now know that src1 is a true oop pointer
884 is_verified_oop_base = true;
1836 case Op_CountTrailingZerosI:
1837 case Op_CountTrailingZerosL:
1838 case Op_PopCountI:
1839 case Op_PopCountL:
1840 if (!UsePopCountInstruction)
1841 return false;
1842 break;
1843 }
1844
1845 return true; // Per default match rules are supported.
1846 }
1847
1848 int Matcher::regnum_to_fpu_offset(int regnum) {
1849 return regnum - 32; // The FP registers are in the second chunk
1850 }
1851
1852 #ifdef ASSERT
1853 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1854 #endif
1855
1856 // Map Types to machine register types
1857 const int Matcher::base2reg[Type::lastype] = {
1858 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
1859 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
1860 0, Op_RegD, 0, 0, /* Vectors */
1861 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
1862 0, 0/*abio*/,
1863 Op_RegP /* Return address */, 0, /* the memories */
1864 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
1865 0 /*bottom*/
1866 };
1867
1868 // Vector width in bytes
1869 const int Matcher::vector_width_in_bytes(BasicType bt) {
1870 assert(MaxVectorSize == 8, "");
1871 return 8;
1872 }
1873
1874 // Vector ideal reg
1875 const int Matcher::vector_ideal_reg(int size) {
1876 assert(MaxVectorSize == 8, "");
1877 return Op_RegD;
1878 }
1879
1880 // Limits on vector size (number of elements) loaded into vector.
1881 const int Matcher::max_vector_size(const BasicType bt) {
1882 assert(is_java_primitive(bt), "only primitive type vectors");
1883 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1884 }
1885
1886 const int Matcher::min_vector_size(const BasicType bt) {
1887 return max_vector_size(bt); // Same as max.
1888 }
1889
1890 // SPARC doesn't support misaligned vectors store/load.
1891 const bool Matcher::misaligned_vectors_ok() {
1892 return false;
1893 }
1894
1895 // USII supports fxtof through the whole range of number, USIII doesn't
1896 const bool Matcher::convL2FSupported(void) {
1897 return VM_Version::has_fast_fxtof();
1898 }
1899
1900 // Is this branch offset short enough that a short branch can be used?
1901 //
1902 // NOTE: If the platform does not provide any short branch variants, then
1903 // this method should return false for offset 0.
1904 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1905 // The passed offset is relative to address of the branch.
1906 // Don't need to adjust the offset.
1907 return UseCBCond && Assembler::is_simm12(offset);
1908 }
1909
1910 const bool Matcher::isSimpleConstant64(jlong value) {
1911 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1912 // Depends on optimizations in MacroAssembler::setx.
1913 int hi = (int)(value >> 32);
1914 int lo = (int)(value & ~0);
5948 __ ldx($mem$$Address, $dst$$Register);
5949 %}
5950 ins_pipe(iload_mem);
5951 %}
5952
5953 // Load Long - UNaligned
5954 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5955 match(Set dst (LoadL_unaligned mem));
5956 effect(KILL tmp);
5957 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5958 size(16);
5959 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5960 "\tLDUW $mem ,$dst\n"
5961 "\tSLLX #32, $dst, $dst\n"
5962 "\tOR $dst, R_O7, $dst" %}
5963 opcode(Assembler::lduw_op3);
5964 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5965 ins_pipe(iload_mem);
5966 %}
5967
5968 // Load Range
5969 instruct loadRange(iRegI dst, memory mem) %{
5970 match(Set dst (LoadRange mem));
5971 ins_cost(MEMORY_REF_COST);
5972
5973 size(4);
5974 format %{ "LDUW $mem,$dst\t! range" %}
5975 opcode(Assembler::lduw_op3);
5976 ins_encode(simple_form3_mem_reg( mem, dst ) );
5977 ins_pipe(iload_mem);
5978 %}
5979
5980 // Load Integer into %f register (for fitos/fitod)
5981 instruct loadI_freg(regF dst, memory mem) %{
5982 match(Set dst (LoadI mem));
5983 ins_cost(MEMORY_REF_COST);
5984 size(4);
5985
5986 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5987 opcode(Assembler::ldf_op3);
6571 ins_cost(MEMORY_REF_COST);
6572
6573 size(4);
6574 format %{ "STF $src,$mem" %}
6575 opcode(Assembler::stf_op3);
6576 ins_encode(simple_form3_mem_reg( mem, src ) );
6577 ins_pipe(fstoreF_mem_reg);
6578 %}
6579
6580 instruct storeF0( memory mem, immF0 src) %{
6581 match(Set mem (StoreF mem src));
6582 ins_cost(MEMORY_REF_COST);
6583
6584 size(4);
6585 format %{ "STW $src,$mem\t! storeF0" %}
6586 opcode(Assembler::stw_op3);
6587 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6588 ins_pipe(fstoreF_mem_zero);
6589 %}
6590
6591 // Convert oop pointer into compressed form
6592 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6593 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6594 match(Set dst (EncodeP src));
6595 format %{ "encode_heap_oop $src, $dst" %}
6596 ins_encode %{
6597 __ encode_heap_oop($src$$Register, $dst$$Register);
6598 %}
6599 ins_pipe(ialu_reg);
6600 %}
6601
6602 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6603 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6604 match(Set dst (EncodeP src));
6605 format %{ "encode_heap_oop_not_null $src, $dst" %}
6606 ins_encode %{
6607 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6608 %}
6609 ins_pipe(ialu_reg);
6610 %}
6615 match(Set dst (DecodeN src));
6616 format %{ "decode_heap_oop $src, $dst" %}
6617 ins_encode %{
6618 __ decode_heap_oop($src$$Register, $dst$$Register);
6619 %}
6620 ins_pipe(ialu_reg);
6621 %}
6622
6623 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6624 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6625 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6626 match(Set dst (DecodeN src));
6627 format %{ "decode_heap_oop_not_null $src, $dst" %}
6628 ins_encode %{
6629 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6630 %}
6631 ins_pipe(ialu_reg);
6632 %}
6633
6634
6635 //----------MemBar Instructions-----------------------------------------------
6636 // Memory barrier flavors
6637
6638 instruct membar_acquire() %{
6639 match(MemBarAcquire);
6640 ins_cost(4*MEMORY_REF_COST);
6641
6642 size(0);
6643 format %{ "MEMBAR-acquire" %}
6644 ins_encode( enc_membar_acquire );
6645 ins_pipe(long_memory_op);
6646 %}
6647
6648 instruct membar_acquire_lock() %{
6649 match(MemBarAcquireLock);
6650 ins_cost(0);
6651
6652 size(0);
6653 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6654 ins_encode( );
8796 ins_pipe(ialu_move_reg_I_to_L);
8797 #else
8798 size(4);
8799 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8800 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8801 ins_pipe(ialu_reg);
8802 #endif
8803 %}
8804
8805 // Register Shift Right Immediate
8806 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8807 match(Set dst (ConvL2I (RShiftL src cnt)));
8808
8809 size(4);
8810 format %{ "SRAX $src,$cnt,$dst" %}
8811 opcode(Assembler::srax_op3, Assembler::arith_op);
8812 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8813 ins_pipe(ialu_reg_imm);
8814 %}
8815
8816 //----------Control Flow Instructions------------------------------------------
8817 // Compare Instructions
8818 // Compare Integers
8819 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8820 match(Set icc (CmpI op1 op2));
8821 effect( DEF icc, USE op1, USE op2 );
8822
8823 size(4);
8824 format %{ "CMP $op1,$op2" %}
8825 opcode(Assembler::subcc_op3, Assembler::arith_op);
8826 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8827 ins_pipe(ialu_cconly_reg_reg);
8828 %}
8829
8830 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8831 match(Set icc (CmpU op1 op2));
8832
8833 size(4);
8834 format %{ "CMP $op1,$op2\t! unsigned" %}
8835 opcode(Assembler::subcc_op3, Assembler::arith_op);
10514 ins_encode %{
10515 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10516 %}
10517 ins_pipe(istore_mem_reg);
10518 %}
10519
10520 // Store short reversed byte order
10521 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10522 match(Set dst (StoreC dst (ReverseBytesS src)));
10523
10524 ins_cost(MEMORY_REF_COST);
10525 size(4);
10526 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10527
10528 ins_encode %{
10529 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10530 %}
10531 ins_pipe(istore_mem_reg);
10532 %}
10533
10534 // ====================VECTOR INSTRUCTIONS=====================================
10535
10536 // Load Aligned Packed values into a Double Register
10537 instruct loadV8(regD dst, memory mem) %{
10538 predicate(n->as_LoadVector()->memory_size() == 8);
10539 match(Set dst (LoadVector mem));
10540 ins_cost(MEMORY_REF_COST);
10541 size(4);
10542 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10543 opcode(Assembler::lddf_op3);
10544 ins_encode(simple_form3_mem_reg( mem, dst ) );
10545 ins_pipe(floadD_mem);
10546 %}
10547
10548 // Store Vector in Double register to memory
10549 instruct storeV8(memory mem, regD src) %{
10550 predicate(n->as_StoreVector()->memory_size() == 8);
10551 match(Set mem (StoreVector mem src));
10552 ins_cost(MEMORY_REF_COST);
10553 size(4);
10554 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10555 opcode(Assembler::stdf_op3);
10556 ins_encode(simple_form3_mem_reg( mem, src ) );
10557 ins_pipe(fstoreD_mem_reg);
10558 %}
10559
10560 // Store Zero into vector in memory
10561 instruct storeV8B_zero(memory mem, immI0 zero) %{
10562 predicate(n->as_StoreVector()->memory_size() == 8);
10563 match(Set mem (StoreVector mem (ReplicateB zero)));
10564 ins_cost(MEMORY_REF_COST);
10565 size(4);
10566 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10567 opcode(Assembler::stx_op3);
10568 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
10569 ins_pipe(fstoreD_mem_zero);
10570 %}
10571
10572 instruct storeV4C_zero(memory mem, immI0 zero) %{
10573 predicate(n->as_StoreVector()->memory_size() == 8);
10574 match(Set mem (StoreVector mem (ReplicateC zero)));
10575 ins_cost(MEMORY_REF_COST);
10576 size(4);
10577 format %{ "STX $zero,$mem\t! store zero vector (4 chars)" %}
10578 opcode(Assembler::stx_op3);
10579 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
10580 ins_pipe(fstoreD_mem_zero);
10581 %}
10582
10583 instruct storeV4S_zero(memory mem, immI0 zero) %{
10584 predicate(n->as_StoreVector()->memory_size() == 8);
10585 match(Set mem (StoreVector mem (ReplicateS zero)));
10586 ins_cost(MEMORY_REF_COST);
10587 size(4);
10588 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10589 opcode(Assembler::stx_op3);
10590 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
10591 ins_pipe(fstoreD_mem_zero);
10592 %}
10593
10594 instruct storeV2I_zero(memory mem, immI0 zero) %{
10595 predicate(n->as_StoreVector()->memory_size() == 8);
10596 match(Set mem (StoreVector mem (ReplicateI zero)));
10597 ins_cost(MEMORY_REF_COST);
10598 size(4);
10599 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10600 opcode(Assembler::stx_op3);
10601 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
10602 ins_pipe(fstoreD_mem_zero);
10603 %}
10604
10605 instruct storeV2F_zero(memory mem, immF0 zero) %{
10606 predicate(n->as_StoreVector()->memory_size() == 8);
10607 match(Set mem (StoreVector mem (ReplicateF zero)));
10608 ins_cost(MEMORY_REF_COST);
10609 size(4);
10610 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10611 opcode(Assembler::stx_op3);
10612 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
10613 ins_pipe(fstoreD_mem_zero);
10614 %}
10615
10616 // Replicate scalar to packed byte values in Double register
10617 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
10618 effect(DEF dst, USE src);
10619 format %{ "SLLX $src,56,$dst\n\t"
10620 "SRLX $dst, 8,O7\n\t"
10621 "OR $dst,O7,$dst\n\t"
10622 "SRLX $dst,16,O7\n\t"
10623 "OR $dst,O7,$dst\n\t"
10624 "SRLX $dst,32,O7\n\t"
10625 "OR $dst,O7,$dst\t! replicate8B" %}
10626 ins_encode( enc_repl8b(src, dst));
10627 ins_pipe(ialu_reg);
10628 %}
10629
10630 // Replicate scalar to packed byte values in Double register
10631 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
10632 predicate(n->as_Vector()->length() == 8);
10633 match(Set dst (ReplicateB src));
10634 expand %{
10635 iRegL tmp;
10636 Repl8B_reg_helper(tmp, src);
10637 regL_to_stkD(dst, tmp);
10638 %}
10639 %}
10640
10641 // Replicate scalar constant to packed byte values in Double register
10642 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10643 predicate(n->as_Vector()->length() == 8);
10644 match(Set dst (ReplicateB con));
10645 effect(KILL tmp);
10646 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10647 ins_encode %{
10648 // XXX This is a quick fix for 6833573.
10649 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10650 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10651 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10652 %}
10653 ins_pipe(loadConFD);
10654 %}
10655
10656 // Replicate scalar to packed char values into stack slot
10657 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
10658 effect(DEF dst, USE src);
10659 format %{ "SLLX $src,48,$dst\n\t"
10660 "SRLX $dst,16,O7\n\t"
10661 "OR $dst,O7,$dst\n\t"
10662 "SRLX $dst,32,O7\n\t"
10663 "OR $dst,O7,$dst\t! replicate4C" %}
10664 ins_encode( enc_repl4s(src, dst) );
10665 ins_pipe(ialu_reg);
10666 %}
10667
10668 // Replicate scalar to packed char values into stack slot
10669 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
10670 predicate(n->as_Vector()->length() == 4);
10671 match(Set dst (ReplicateC src));
10672 expand %{
10673 iRegL tmp;
10674 Repl4C_reg_helper(tmp, src);
10675 regL_to_stkD(dst, tmp);
10676 %}
10677 %}
10678
10679 // Replicate scalar constant to packed char values in Double register
10680 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
10681 predicate(n->as_Vector()->length() == 4);
10682 match(Set dst (ReplicateC con));
10683 effect(KILL tmp);
10684 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
10685 ins_encode %{
10686 // XXX This is a quick fix for 6833573.
10687 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10688 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10689 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10690 %}
10691 ins_pipe(loadConFD);
10692 %}
10693
10694 // Replicate scalar to packed short values into stack slot
10695 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
10696 effect(DEF dst, USE src);
10697 format %{ "SLLX $src,48,$dst\n\t"
10698 "SRLX $dst,16,O7\n\t"
10699 "OR $dst,O7,$dst\n\t"
10700 "SRLX $dst,32,O7\n\t"
10701 "OR $dst,O7,$dst\t! replicate4S" %}
10702 ins_encode( enc_repl4s(src, dst) );
10703 ins_pipe(ialu_reg);
10704 %}
10705
10706 // Replicate scalar to packed short values into stack slot
10707 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
10708 predicate(n->as_Vector()->length() == 4);
10709 match(Set dst (ReplicateS src));
10710 expand %{
10711 iRegL tmp;
10712 Repl4S_reg_helper(tmp, src);
10713 regL_to_stkD(dst, tmp);
10714 %}
10715 %}
10716
10717 // Replicate scalar constant to packed short values in Double register
10718 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10719 predicate(n->as_Vector()->length() == 4);
10720 match(Set dst (ReplicateS con));
10721 effect(KILL tmp);
10722 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10723 ins_encode %{
10724 // XXX This is a quick fix for 6833573.
10725 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10726 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10727 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10728 %}
10729 ins_pipe(loadConFD);
10730 %}
10731
10732 // Replicate scalar to packed int values in Double register
10733 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
10734 effect(DEF dst, USE src);
10735 format %{ "SLLX $src,32,$dst\n\t"
10736 "SRLX $dst,32,O7\n\t"
10737 "OR $dst,O7,$dst\t! replicate2I" %}
10738 ins_encode( enc_repl2i(src, dst));
10739 ins_pipe(ialu_reg);
10740 %}
10741
10742 // Replicate scalar to packed int values in Double register
10743 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
10744 predicate(n->as_Vector()->length() == 2);
10745 match(Set dst (ReplicateI src));
10746 expand %{
10747 iRegL tmp;
10748 Repl2I_reg_helper(tmp, src);
10749 regL_to_stkD(dst, tmp);
10750 %}
10751 %}
10752
10753 // Replicate scalar zero constant to packed int values in Double register
10754 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10755 predicate(n->as_Vector()->length() == 2);
10756 match(Set dst (ReplicateI con));
10757 effect(KILL tmp);
10758 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10759 ins_encode %{
10760 // XXX This is a quick fix for 6833573.
10761 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10762 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10763 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10764 %}
10765 ins_pipe(loadConFD);
10766 %}
10767
10768 // Replicate scalar to packed float values in Double register
10769 instruct Repl2F_reg(stackSlotD dst, regF src) %{
10770 predicate(n->as_Vector()->length() == 2);
10771 match(Set dst (ReplicateF src));
10772 ins_cost(MEMORY_REF_COST*2);
10773 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10774 "STF $src,$dst.lo" %}
10775 opcode(Assembler::stf_op3);
10776 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10777 ins_pipe(fstoreF_stk_reg);
10778 %}
10779
10780 // Replicate scalar zero constant to packed float values in Double register
10781 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10782 predicate(n->as_Vector()->length() == 2);
10783 match(Set dst (ReplicateF con));
10784 effect(KILL tmp);
10785 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10786 ins_encode %{
10787 // XXX This is a quick fix for 6833573.
10788 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10789 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10790 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10791 %}
10792 ins_pipe(loadConFD);
10793 %}
10794
10795 //----------PEEPHOLE RULES-----------------------------------------------------
10796 // These must follow all instruction definitions as they use the names
10797 // defined in the instructions definitions.
10798 //
10799 // peepmatch ( root_instr_name [preceding_instruction]* );
10800 //
10801 // peepconstraint %{
10802 // (instruction_number.operand_name relational_op instruction_number.operand_name
10803 // [, ...] );
10804 // // instruction numbers are zero-based using left to right order in peepmatch
10805 //
10806 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10807 // // provide an instruction_number.operand_name for each operand that appears
10808 // // in the replacement instruction's match rule
10809 //
10810 // ---------VM FLAGS---------------------------------------------------------
10811 //
10812 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10813 //
10814 // Each peephole rule is given an identifying number starting with zero and
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