1 /* 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_REGISTER_X86_HPP 26 #define CPU_X86_VM_REGISTER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "vm_version_x86.hpp" 30 31 class VMRegImpl; 32 typedef VMRegImpl* VMReg; 33 34 // Use Register as shortcut 35 class RegisterImpl; 36 typedef RegisterImpl* Register; 37 38 39 // The implementation of integer registers for the ia32 architecture 40 inline Register as_Register(int encoding) { 41 return (Register)(intptr_t) encoding; 42 } 43 44 class RegisterImpl: public AbstractRegisterImpl { 45 public: 46 enum { 47 #ifndef AMD64 48 number_of_registers = 8, 49 number_of_byte_registers = 4 50 #else 51 number_of_registers = 16, 52 number_of_byte_registers = 16 53 #endif // AMD64 54 }; 55 56 // derived registers, offsets, and addresses 57 Register successor() const { return as_Register(encoding() + 1); } 58 59 // construction 60 inline friend Register as_Register(int encoding); 61 62 VMReg as_VMReg(); 63 64 // accessors 65 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 66 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 67 bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; } 68 const char* name() const; 69 }; 70 71 // The integer registers of the ia32/amd64 architecture 72 73 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); 74 75 76 CONSTANT_REGISTER_DECLARATION(Register, rax, (0)); 77 CONSTANT_REGISTER_DECLARATION(Register, rcx, (1)); 78 CONSTANT_REGISTER_DECLARATION(Register, rdx, (2)); 79 CONSTANT_REGISTER_DECLARATION(Register, rbx, (3)); 80 CONSTANT_REGISTER_DECLARATION(Register, rsp, (4)); 81 CONSTANT_REGISTER_DECLARATION(Register, rbp, (5)); 82 CONSTANT_REGISTER_DECLARATION(Register, rsi, (6)); 83 CONSTANT_REGISTER_DECLARATION(Register, rdi, (7)); 84 #ifdef AMD64 85 CONSTANT_REGISTER_DECLARATION(Register, r8, (8)); 86 CONSTANT_REGISTER_DECLARATION(Register, r9, (9)); 87 CONSTANT_REGISTER_DECLARATION(Register, r10, (10)); 88 CONSTANT_REGISTER_DECLARATION(Register, r11, (11)); 89 CONSTANT_REGISTER_DECLARATION(Register, r12, (12)); 90 CONSTANT_REGISTER_DECLARATION(Register, r13, (13)); 91 CONSTANT_REGISTER_DECLARATION(Register, r14, (14)); 92 CONSTANT_REGISTER_DECLARATION(Register, r15, (15)); 93 #endif // AMD64 94 95 // Use FloatRegister as shortcut 96 class FloatRegisterImpl; 97 typedef FloatRegisterImpl* FloatRegister; 98 99 inline FloatRegister as_FloatRegister(int encoding) { 100 return (FloatRegister)(intptr_t) encoding; 101 } 102 103 // The implementation of floating point registers for the ia32 architecture 104 class FloatRegisterImpl: public AbstractRegisterImpl { 105 public: 106 enum { 107 number_of_registers = 8 108 }; 109 110 // construction 111 inline friend FloatRegister as_FloatRegister(int encoding); 112 113 VMReg as_VMReg(); 114 115 // derived registers, offsets, and addresses 116 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } 117 118 // accessors 119 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 120 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 121 const char* name() const; 122 123 }; 124 125 // Use XMMRegister as shortcut 126 class XMMRegisterImpl; 127 typedef XMMRegisterImpl* XMMRegister; 128 129 // Use MMXRegister as shortcut 130 class MMXRegisterImpl; 131 typedef MMXRegisterImpl* MMXRegister; 132 133 inline XMMRegister as_XMMRegister(int encoding) { 134 return (XMMRegister)(intptr_t)encoding; 135 } 136 137 inline MMXRegister as_MMXRegister(int encoding) { 138 return (MMXRegister)(intptr_t)encoding; 139 } 140 141 // The implementation of XMM registers for the IA32 architecture 142 class XMMRegisterImpl: public AbstractRegisterImpl { 143 public: 144 enum { 145 #ifndef AMD64 146 number_of_registers = 8 147 #else 148 number_of_registers = 16 149 #endif // AMD64 150 }; 151 152 // construction 153 friend XMMRegister as_XMMRegister(int encoding); 154 155 VMReg as_VMReg(); 156 157 // derived registers, offsets, and addresses 158 XMMRegister successor() const { return as_XMMRegister(encoding() + 1); } 159 160 // accessors 161 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 162 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 163 const char* name() const; 164 }; 165 166 167 // The XMM registers, for P3 and up chips 168 CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1)); 169 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0)); 170 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1)); 171 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2)); 172 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3)); 173 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4)); 174 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5)); 175 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6)); 176 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7)); 177 #ifdef AMD64 178 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8)); 179 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9)); 180 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10)); 181 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11)); 182 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12)); 183 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13)); 184 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14)); 185 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15)); 186 #endif // AMD64 187 188 // Only used by the 32bit stubGenerator. These can't be described by vmreg and hence 189 // can't be described in oopMaps and therefore can't be used by the compilers (at least 190 // were deopt might wan't to see them). 191 192 // The MMX registers, for P3 and up chips 193 CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1)); 194 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0)); 195 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1)); 196 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2)); 197 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3)); 198 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4)); 199 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5)); 200 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6)); 201 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7)); 202 203 204 // Need to know the total number of registers of all sorts for SharedInfo. 205 // Define a class that exports it. 206 class ConcreteRegisterImpl : public AbstractRegisterImpl { 207 public: 208 enum { 209 // A big enough number for C2: all the registers plus flags 210 // This number must be large enough to cover REG_COUNT (defined by c2) registers. 211 // There is no requirement that any ordering here matches any ordering c2 gives 212 // it's optoregs. 213 214 number_of_registers = RegisterImpl::number_of_registers + 215 #ifdef AMD64 216 RegisterImpl::number_of_registers + // "H" half of a 64bit register 217 #endif // AMD64 218 2 * FloatRegisterImpl::number_of_registers + 219 2 * XMMRegisterImpl::number_of_registers + 220 1 // eflags 221 }; 222 223 static const int max_gpr; 224 static const int max_fpr; 225 static const int max_xmm; 226 227 }; 228 229 #endif // CPU_X86_VM_REGISTER_X86_HPP