1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
141 // The implementation of XMM registers for the IA32 architecture
142 class XMMRegisterImpl: public AbstractRegisterImpl {
143 public:
144 enum {
145 #ifndef AMD64
146 number_of_registers = 8
147 #else
148 number_of_registers = 16
149 #endif // AMD64
150 };
151
152 // construction
153 friend XMMRegister as_XMMRegister(int encoding);
154
155 VMReg as_VMReg();
156
157 // derived registers, offsets, and addresses
158 XMMRegister successor() const { return as_XMMRegister(encoding() + 1); }
159
160 // accessors
161 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
162 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
163 const char* name() const;
164 };
165
166
167 // The XMM registers, for P3 and up chips
168 CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
169 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
170 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
171 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
172 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
173 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
174 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
175 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
176 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
177 #ifdef AMD64
178 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8));
179 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9));
180 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10));
181 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11));
199 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
200 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
201 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
202
203
204 // Need to know the total number of registers of all sorts for SharedInfo.
205 // Define a class that exports it.
206 class ConcreteRegisterImpl : public AbstractRegisterImpl {
207 public:
208 enum {
209 // A big enough number for C2: all the registers plus flags
210 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
211 // There is no requirement that any ordering here matches any ordering c2 gives
212 // it's optoregs.
213
214 number_of_registers = RegisterImpl::number_of_registers +
215 #ifdef AMD64
216 RegisterImpl::number_of_registers + // "H" half of a 64bit register
217 #endif // AMD64
218 2 * FloatRegisterImpl::number_of_registers +
219 2 * XMMRegisterImpl::number_of_registers +
220 1 // eflags
221 };
222
223 static const int max_gpr;
224 static const int max_fpr;
225 static const int max_xmm;
226
227 };
228
229 #endif // CPU_X86_VM_REGISTER_X86_HPP
|
1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
141 // The implementation of XMM registers for the IA32 architecture
142 class XMMRegisterImpl: public AbstractRegisterImpl {
143 public:
144 enum {
145 #ifndef AMD64
146 number_of_registers = 8
147 #else
148 number_of_registers = 16
149 #endif // AMD64
150 };
151
152 // construction
153 friend XMMRegister as_XMMRegister(int encoding);
154
155 VMReg as_VMReg();
156
157 // derived registers, offsets, and addresses
158 XMMRegister successor() const { return as_XMMRegister(encoding() + 1); }
159
160 // accessors
161 int encoding() const { assert(is_valid(), err_msg("invalid register (%d)", (int)(intptr_t)this )); return (intptr_t)this; }
162 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
163 const char* name() const;
164 };
165
166
167 // The XMM registers, for P3 and up chips
168 CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
169 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
170 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
171 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
172 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
173 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
174 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
175 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
176 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
177 #ifdef AMD64
178 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8));
179 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9));
180 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10));
181 CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11));
199 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
200 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
201 CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
202
203
204 // Need to know the total number of registers of all sorts for SharedInfo.
205 // Define a class that exports it.
206 class ConcreteRegisterImpl : public AbstractRegisterImpl {
207 public:
208 enum {
209 // A big enough number for C2: all the registers plus flags
210 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
211 // There is no requirement that any ordering here matches any ordering c2 gives
212 // it's optoregs.
213
214 number_of_registers = RegisterImpl::number_of_registers +
215 #ifdef AMD64
216 RegisterImpl::number_of_registers + // "H" half of a 64bit register
217 #endif // AMD64
218 2 * FloatRegisterImpl::number_of_registers +
219 8 * XMMRegisterImpl::number_of_registers +
220 1 // eflags
221 };
222
223 static const int max_gpr;
224 static const int max_fpr;
225 static const int max_xmm;
226
227 };
228
229 #endif // CPU_X86_VM_REGISTER_X86_HPP
|