src/cpu/x86/vm/vm_version_x86.cpp

*** 465,474 ****
--- 465,500 ----
    if (!supports_avx2()) // Drop to 1 if no AVX2 support
      UseAVX = MIN2((intx)1,UseAVX);
    if (!supports_avx ()) // Drop to 0 if no AVX  support
      UseAVX = 0;
  
+ #ifdef COMPILER2
+   if (UseFPUForSpilling) {
+     if (UseSSE < 2) {
+       // Only supported with SSE2+
+       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
+     }
+   }
+   if (MaxVectorSize > 0) {
+     if (!is_power_of_2(MaxVectorSize)) {
+       warning("MaxVectorSize must be a power of 2");
+       FLAG_SET_DEFAULT(MaxVectorSize, 32);
+     }
+     if (MaxVectorSize > 32) {
+       FLAG_SET_DEFAULT(MaxVectorSize, 32);
+     }
+     if (MaxVectorSize > 16 && UseAVX == 0) {
+       // Only supported with AVX+
+       FLAG_SET_DEFAULT(MaxVectorSize, 16);
+     }
+     if (UseSSE < 2) {
+       // Only supported with SSE2+
+       FLAG_SET_DEFAULT(MaxVectorSize, 0);
+     }
+   }
+ #endif
+ 
    // On new cpus instructions which update whole XMM register should be used
    // to prevent partial register stall due to dependencies on high half.
    //
    // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
    // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
*** 542,552 ****
--- 568,584 ----
        if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
          UseUnalignedLoadStores = true;
        }
      }
  
+ #ifdef COMPILER2
+     if (MaxVectorSize > 16) {
+       // Limit vectors size to 16 bytes on current AMD cpus.
+       FLAG_SET_DEFAULT(MaxVectorSize, 16);
      }
+ #endif // COMPILER2
+   }
  
    if( is_intel() ) { // Intel cpus specific settings
      if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
        UseStoreImmI16 = false; // don't use it on Intel cpus
      }
*** 604,622 ****
    } else if (UsePopCountInstruction) {
      warning("POPCNT instruction is not available on this CPU");
      FLAG_SET_DEFAULT(UsePopCountInstruction, false);
    }
  
- #ifdef COMPILER2
-   if (UseFPUForSpilling) {
-     if (UseSSE < 2) {
-       // Only supported with SSE2+
-       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
-     }
-   }
- #endif
- 
    assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
    assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
  
    // set valid Prefetch instruction
    if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
--- 636,645 ----