1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
242
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
246
247 #define __ _masm.
248
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
251
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
255
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
266
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
269
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
275
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
282
283 static int preserve_SP_size() {
284 return 2; // op, rm(reg/reg)
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
296
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
300
301 static int sizeof_FFree_Float_Stack_All = -1;
302
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
307
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
313
314 //
315 // Compute padding required for nodes which need alignment
316 //
317
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
325
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
334
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
343
344 // EMIT_RM()
345 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
346 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
347 cbuf.insts()->emit_int8(c);
348 }
349
350 // EMIT_CC()
351 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
352 unsigned char c = (unsigned char)( f1 | f2 );
353 cbuf.insts()->emit_int8(c);
354 }
355
356 // EMIT_OPCODE()
357 void emit_opcode(CodeBuffer &cbuf, int code) {
358 cbuf.insts()->emit_int8((unsigned char) code);
359 }
360
361 // EMIT_OPCODE() w/ relocation information
362 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
363 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
364 emit_opcode(cbuf, code);
365 }
366
367 // EMIT_D8()
368 void emit_d8(CodeBuffer &cbuf, int d8) {
369 cbuf.insts()->emit_int8((unsigned char) d8);
370 }
371
372 // EMIT_D16()
373 void emit_d16(CodeBuffer &cbuf, int d16) {
374 cbuf.insts()->emit_int16(d16);
375 }
376
377 // EMIT_D32()
378 void emit_d32(CodeBuffer &cbuf, int d32) {
379 cbuf.insts()->emit_int32(d32);
380 }
381
382 // emit 32 bit value and construct relocation entry from relocInfo::relocType
383 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
384 int format) {
385 cbuf.relocate(cbuf.insts_mark(), reloc, format);
386 cbuf.insts()->emit_int32(d32);
387 }
388
389 // emit 32 bit value and construct relocation entry from RelocationHolder
390 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
391 int format) {
392 #ifdef ASSERT
393 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
394 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
395 }
396 #endif
397 cbuf.relocate(cbuf.insts_mark(), rspec, format);
398 cbuf.insts()->emit_int32(d32);
399 }
400
401 // Access stack slot for load or store
402 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
403 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
404 if( -128 <= disp && disp <= 127 ) {
405 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
406 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
407 emit_d8 (cbuf, disp); // Displacement // R/M byte
408 } else {
409 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
410 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
411 emit_d32(cbuf, disp); // Displacement // R/M byte
412 }
413 }
414
415 // eRegI ereg, memory mem) %{ // emit_reg_mem
416 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
417 // There is no index & no scale, use form without SIB byte
418 if ((index == 0x4) &&
419 (scale == 0) && (base != ESP_enc)) {
420 // If no displacement, mode is 0x0; unless base is [EBP]
421 if ( (displace == 0) && (base != EBP_enc) ) {
422 emit_rm(cbuf, 0x0, reg_encoding, base);
423 }
424 else { // If 8-bit displacement, mode 0x1
425 if ((displace >= -128) && (displace <= 127)
426 && !(displace_is_oop) ) {
427 emit_rm(cbuf, 0x1, reg_encoding, base);
428 emit_d8(cbuf, displace);
429 }
430 else { // If 32-bit displacement
431 if (base == -1) { // Special flag for absolute address
432 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
433 // (manual lies; no SIB needed here)
434 if ( displace_is_oop ) {
435 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
436 } else {
437 emit_d32 (cbuf, displace);
438 }
439 }
440 else { // Normal base + offset
441 emit_rm(cbuf, 0x2, reg_encoding, base);
442 if ( displace_is_oop ) {
443 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
444 } else {
445 emit_d32 (cbuf, displace);
446 }
447 }
448 }
449 }
450 }
451 else { // Else, encode with the SIB byte
452 // If no displacement, mode is 0x0; unless base is [EBP]
453 if (displace == 0 && (base != EBP_enc)) { // If no displacement
454 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
455 emit_rm(cbuf, scale, index, base);
456 }
457 else { // If 8-bit displacement, mode 0x1
458 if ((displace >= -128) && (displace <= 127)
459 && !(displace_is_oop) ) {
460 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 emit_d8(cbuf, displace);
463 }
464 else { // If 32-bit displacement
465 if (base == 0x04 ) {
466 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, 0x04);
468 } else {
469 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
470 emit_rm(cbuf, scale, index, base);
471 }
472 if ( displace_is_oop ) {
473 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
474 } else {
475 emit_d32 (cbuf, displace);
476 }
477 }
478 }
479 }
480 }
481
482
483 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
484 if( dst_encoding == src_encoding ) {
485 // reg-reg copy, use an empty encoding
486 } else {
487 emit_opcode( cbuf, 0x8B );
488 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
489 }
490 }
491
492 void emit_cmpfp_fixup(MacroAssembler& _masm) {
493 Label exit;
494 __ jccb(Assembler::noParity, exit);
495 __ pushf();
496 //
497 // comiss/ucomiss instructions set ZF,PF,CF flags and
498 // zero OF,AF,SF for NaN values.
499 // Fixup flags by zeroing ZF,PF so that compare of NaN
500 // values returns 'less than' result (CF is set).
501 // Leave the rest of flags unchanged.
502 //
503 // 7 6 5 4 3 2 1 0
504 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
505 // 0 0 1 0 1 0 1 1 (0x2B)
506 //
507 __ andl(Address(rsp, 0), 0xffffff2b);
508 __ popf();
509 __ bind(exit);
510 }
511
512 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
513 Label done;
514 __ movl(dst, -1);
515 __ jcc(Assembler::parity, done);
516 __ jcc(Assembler::below, done);
517 __ setb(Assembler::notEqual, dst);
518 __ movzbl(dst, dst);
519 __ bind(done);
520 }
521
522
523 //=============================================================================
524 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
525
526 int Compile::ConstantTable::calculate_table_base_offset() const {
527 return 0; // absolute addressing, no offset
528 }
529
530 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
531 // Empty encoding
532 }
533
534 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
535 return 0;
536 }
537
538 #ifndef PRODUCT
539 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
540 st->print("# MachConstantBaseNode (empty encoding)");
541 }
542 #endif
543
544
545 //=============================================================================
546 #ifndef PRODUCT
547 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
548 Compile* C = ra_->C;
549
550 int framesize = C->frame_slots() << LogBytesPerInt;
551 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
552 // Remove wordSize for return addr which is already pushed.
553 framesize -= wordSize;
554
555 if (C->need_stack_bang(framesize)) {
556 framesize -= wordSize;
557 st->print("# stack bang");
558 st->print("\n\t");
559 st->print("PUSH EBP\t# Save EBP");
560 if (framesize) {
561 st->print("\n\t");
562 st->print("SUB ESP, #%d\t# Create frame",framesize);
563 }
564 } else {
565 st->print("SUB ESP, #%d\t# Create frame",framesize);
566 st->print("\n\t");
567 framesize -= wordSize;
568 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
569 }
570
571 if (VerifyStackAtCalls) {
572 st->print("\n\t");
573 framesize -= wordSize;
574 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
575 }
576
577 if( C->in_24_bit_fp_mode() ) {
578 st->print("\n\t");
579 st->print("FLDCW \t# load 24 bit fpu control word");
580 }
581 if (UseSSE >= 2 && VerifyFPU) {
582 st->print("\n\t");
583 st->print("# verify FPU stack (must be clean on entry)");
584 }
585
586 #ifdef ASSERT
587 if (VerifyStackAtCalls) {
588 st->print("\n\t");
589 st->print("# stack alignment check");
590 }
591 #endif
592 st->cr();
593 }
594 #endif
595
596
597 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
598 Compile* C = ra_->C;
599 MacroAssembler _masm(&cbuf);
600
601 int framesize = C->frame_slots() << LogBytesPerInt;
602
603 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
604
605 C->set_frame_complete(cbuf.insts_size());
606
607 if (C->has_mach_constant_base_node()) {
608 // NOTE: We set the table base offset here because users might be
609 // emitted before MachConstantBaseNode.
610 Compile::ConstantTable& constant_table = C->constant_table();
611 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
612 }
613 }
614
615 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_); // too many variables; just compute it the hard way
617 }
618
619 int MachPrologNode::reloc() const {
620 return 0; // a large enough number
621 }
622
623 //=============================================================================
624 #ifndef PRODUCT
625 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
626 Compile *C = ra_->C;
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
631
632 if( C->in_24_bit_fp_mode() ) {
633 st->print("FLDCW standard control word");
634 st->cr(); st->print("\t");
635 }
636 if( framesize ) {
637 st->print("ADD ESP,%d\t# Destroy frame",framesize);
638 st->cr(); st->print("\t");
639 }
640 st->print_cr("POPL EBP"); st->print("\t");
641 if( do_polling() && C->is_method_compilation() ) {
642 st->print("TEST PollPage,EAX\t! Poll Safepoint");
643 st->cr(); st->print("\t");
644 }
645 }
646 #endif
647
648 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
649 Compile *C = ra_->C;
650
651 // If method set FPU control word, restore to standard control word
652 if( C->in_24_bit_fp_mode() ) {
653 MacroAssembler masm(&cbuf);
654 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
655 }
656
657 int framesize = C->frame_slots() << LogBytesPerInt;
658 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
659 // Remove two words for return addr and rbp,
660 framesize -= 2*wordSize;
661
662 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
663
664 if( framesize >= 128 ) {
665 emit_opcode(cbuf, 0x81); // add SP, #framesize
666 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
667 emit_d32(cbuf, framesize);
668 }
669 else if( framesize ) {
670 emit_opcode(cbuf, 0x83); // add SP, #framesize
671 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
672 emit_d8(cbuf, framesize);
673 }
674
675 emit_opcode(cbuf, 0x58 | EBP_enc);
676
677 if( do_polling() && C->is_method_compilation() ) {
678 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
679 emit_opcode(cbuf,0x85);
680 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
681 emit_d32(cbuf, (intptr_t)os::get_polling_page());
682 }
683 }
684
685 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
686 Compile *C = ra_->C;
687 // If method set FPU control word, restore to standard control word
688 int size = C->in_24_bit_fp_mode() ? 6 : 0;
689 if( do_polling() && C->is_method_compilation() ) size += 6;
690
691 int framesize = C->frame_slots() << LogBytesPerInt;
692 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
693 // Remove two words for return addr and rbp,
694 framesize -= 2*wordSize;
695
696 size++; // popl rbp,
697
698 if( framesize >= 128 ) {
699 size += 6;
700 } else {
701 size += framesize ? 3 : 0;
702 }
703 return size;
704 }
705
706 int MachEpilogNode::reloc() const {
707 return 0; // a large enough number
708 }
709
710 const Pipeline * MachEpilogNode::pipeline() const {
711 return MachNode::pipeline_class();
712 }
713
714 int MachEpilogNode::safepoint_offset() const { return 0; }
715
716 //=============================================================================
717
718 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
719 static enum RC rc_class( OptoReg::Name reg ) {
720
721 if( !OptoReg::is_valid(reg) ) return rc_bad;
722 if (OptoReg::is_stack(reg)) return rc_stack;
723
724 VMReg r = OptoReg::as_VMReg(reg);
725 if (r->is_Register()) return rc_int;
726 if (r->is_FloatRegister()) {
727 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
728 return rc_float;
729 }
730 assert(r->is_XMMRegister(), "must be");
731 return rc_xmm;
732 }
733
734 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
735 int opcode, const char *op_str, int size, outputStream* st ) {
736 if( cbuf ) {
737 emit_opcode (*cbuf, opcode );
738 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
739 #ifndef PRODUCT
740 } else if( !do_size ) {
741 if( size != 0 ) st->print("\n\t");
742 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
743 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
744 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
745 } else { // FLD, FST, PUSH, POP
746 st->print("%s [ESP + #%d]",op_str,offset);
747 }
748 #endif
749 }
750 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
751 return size+3+offset_size;
752 }
753
754 // Helper for XMM registers. Extra opcode bits, limited syntax.
755 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
756 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
757 if (cbuf) {
758 MacroAssembler _masm(cbuf);
759 if (reg_lo+1 == reg_hi) { // double move?
760 if (is_load) {
761 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
762 } else {
763 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
764 }
765 } else {
766 if (is_load) {
767 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
768 } else {
769 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
770 }
771 }
772 #ifndef PRODUCT
773 } else if (!do_size) {
774 if (size != 0) st->print("\n\t");
775 if (reg_lo+1 == reg_hi) { // double move?
776 if (is_load) st->print("%s %s,[ESP + #%d]",
777 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
778 Matcher::regName[reg_lo], offset);
779 else st->print("MOVSD [ESP + #%d],%s",
780 offset, Matcher::regName[reg_lo]);
781 } else {
782 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
783 Matcher::regName[reg_lo], offset);
784 else st->print("MOVSS [ESP + #%d],%s",
785 offset, Matcher::regName[reg_lo]);
786 }
787 #endif
788 }
789 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
790 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
791 return size+5+offset_size;
792 }
793
794
795 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
796 int src_hi, int dst_hi, int size, outputStream* st ) {
797 if (cbuf) {
798 MacroAssembler _masm(cbuf);
799 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
800 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
801 as_XMMRegister(Matcher::_regEncode[src_lo]));
802 } else {
803 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
804 as_XMMRegister(Matcher::_regEncode[src_lo]));
805 }
806 #ifndef PRODUCT
807 } else if (!do_size) {
808 if (size != 0) st->print("\n\t");
809 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
810 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
811 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
812 } else {
813 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
814 }
815 } else {
816 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
817 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
818 } else {
819 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 }
821 }
822 #endif
823 }
824 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
825 // Only MOVAPS SSE prefix uses 1 byte.
826 int sz = 4;
827 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
828 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
829 return size + sz;
830 }
831
832 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
833 int src_hi, int dst_hi, int size, outputStream* st ) {
834 // 32-bit
835 if (cbuf) {
836 MacroAssembler _masm(cbuf);
837 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
838 as_Register(Matcher::_regEncode[src_lo]));
839 #ifndef PRODUCT
840 } else if (!do_size) {
841 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
842 #endif
843 }
844 return 4;
845 }
846
847
848 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
849 int src_hi, int dst_hi, int size, outputStream* st ) {
850 // 32-bit
851 if (cbuf) {
852 MacroAssembler _masm(cbuf);
853 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
854 as_XMMRegister(Matcher::_regEncode[src_lo]));
855 #ifndef PRODUCT
856 } else if (!do_size) {
857 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
858 #endif
859 }
860 return 4;
861 }
862
863 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
864 if( cbuf ) {
865 emit_opcode(*cbuf, 0x8B );
866 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
867 #ifndef PRODUCT
868 } else if( !do_size ) {
869 if( size != 0 ) st->print("\n\t");
870 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
871 #endif
872 }
873 return size+2;
874 }
875
876 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
877 int offset, int size, outputStream* st ) {
878 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
879 if( cbuf ) {
880 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
881 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
882 #ifndef PRODUCT
883 } else if( !do_size ) {
884 if( size != 0 ) st->print("\n\t");
885 st->print("FLD %s",Matcher::regName[src_lo]);
886 #endif
887 }
888 size += 2;
889 }
890
891 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
892 const char *op_str;
893 int op;
894 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
895 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
896 op = 0xDD;
897 } else { // 32-bit store
898 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
899 op = 0xD9;
900 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
901 }
902
903 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
904 }
905
906 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
907 // Get registers to move
908 OptoReg::Name src_second = ra_->get_reg_second(in(1));
909 OptoReg::Name src_first = ra_->get_reg_first(in(1));
910 OptoReg::Name dst_second = ra_->get_reg_second(this );
911 OptoReg::Name dst_first = ra_->get_reg_first(this );
912
913 enum RC src_second_rc = rc_class(src_second);
914 enum RC src_first_rc = rc_class(src_first);
915 enum RC dst_second_rc = rc_class(dst_second);
916 enum RC dst_first_rc = rc_class(dst_first);
917
918 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
919
920 // Generate spill code!
921 int size = 0;
922
923 if( src_first == dst_first && src_second == dst_second )
924 return size; // Self copy, no move
925
926 // --------------------------------------
927 // Check for mem-mem move. push/pop to move.
928 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
929 if( src_second == dst_first ) { // overlapping stack copy ranges
930 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
933 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
934 }
935 // move low bits
936 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
937 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
938 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
939 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
940 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
941 }
942 return size;
943 }
944
945 // --------------------------------------
946 // Check for integer reg-reg copy
947 if( src_first_rc == rc_int && dst_first_rc == rc_int )
948 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
949
950 // Check for integer store
951 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
952 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
953
954 // Check for integer load
955 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
956 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
957
958 // Check for integer reg-xmm reg copy
959 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
960 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
961 "no 64 bit integer-float reg moves" );
962 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
963 }
964 // --------------------------------------
965 // Check for float reg-reg copy
966 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
967 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
968 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
969 if( cbuf ) {
970
971 // Note the mucking with the register encode to compensate for the 0/1
972 // indexing issue mentioned in a comment in the reg_def sections
973 // for FPR registers many lines above here.
974
975 if( src_first != FPR1L_num ) {
976 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
977 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
978 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
979 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
980 } else {
981 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
982 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
983 }
984 #ifndef PRODUCT
985 } else if( !do_size ) {
986 if( size != 0 ) st->print("\n\t");
987 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
988 else st->print( "FST %s", Matcher::regName[dst_first]);
989 #endif
990 }
991 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
992 }
993
994 // Check for float store
995 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
996 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
997 }
998
999 // Check for float load
1000 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1001 int offset = ra_->reg2offset(src_first);
1002 const char *op_str;
1003 int op;
1004 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1005 op_str = "FLD_D";
1006 op = 0xDD;
1007 } else { // 32-bit load
1008 op_str = "FLD_S";
1009 op = 0xD9;
1010 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1011 }
1012 if( cbuf ) {
1013 emit_opcode (*cbuf, op );
1014 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1015 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1016 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1017 #ifndef PRODUCT
1018 } else if( !do_size ) {
1019 if( size != 0 ) st->print("\n\t");
1020 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1021 #endif
1022 }
1023 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1024 return size + 3+offset_size+2;
1025 }
1026
1027 // Check for xmm reg-reg copy
1028 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1029 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1030 (src_first+1 == src_second && dst_first+1 == dst_second),
1031 "no non-adjacent float-moves" );
1032 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1033 }
1034
1035 // Check for xmm reg-integer reg copy
1036 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1037 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1038 "no 64 bit float-integer reg moves" );
1039 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1040 }
1041
1042 // Check for xmm store
1043 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1044 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1045 }
1046
1047 // Check for float xmm load
1048 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1049 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1050 }
1051
1052 // Copy from float reg to xmm reg
1053 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1054 // copy to the top of stack from floating point reg
1055 // and use LEA to preserve flags
1056 if( cbuf ) {
1057 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1058 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1059 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1060 emit_d8(*cbuf,0xF8);
1061 #ifndef PRODUCT
1062 } else if( !do_size ) {
1063 if( size != 0 ) st->print("\n\t");
1064 st->print("LEA ESP,[ESP-8]");
1065 #endif
1066 }
1067 size += 4;
1068
1069 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1070
1071 // Copy from the temp memory to the xmm reg.
1072 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1073
1074 if( cbuf ) {
1075 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1076 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1077 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1078 emit_d8(*cbuf,0x08);
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 st->print("LEA ESP,[ESP+8]");
1083 #endif
1084 }
1085 size += 4;
1086 return size;
1087 }
1088
1089 assert( size > 0, "missed a case" );
1090
1091 // --------------------------------------------------------------------
1092 // Check for second bits still needing moving.
1093 if( src_second == dst_second )
1094 return size; // Self copy; no move
1095 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1096
1097 // Check for second word int-int move
1098 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1099 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1100
1101 // Check for second word integer store
1102 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1103 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1104
1105 // Check for second word integer load
1106 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1107 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1108
1109
1110 Unimplemented();
1111 }
1112
1113 #ifndef PRODUCT
1114 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1115 implementation( NULL, ra_, false, st );
1116 }
1117 #endif
1118
1119 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1120 implementation( &cbuf, ra_, false, NULL );
1121 }
1122
1123 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1124 return implementation( NULL, ra_, true, NULL );
1125 }
1126
1127
1128 //=============================================================================
1129 #ifndef PRODUCT
1130 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1131 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1132 int reg = ra_->get_reg_first(this);
1133 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1134 }
1135 #endif
1136
1137 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1138 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1139 int reg = ra_->get_encode(this);
1140 if( offset >= 128 ) {
1141 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1142 emit_rm(cbuf, 0x2, reg, 0x04);
1143 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1144 emit_d32(cbuf, offset);
1145 }
1146 else {
1147 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1148 emit_rm(cbuf, 0x1, reg, 0x04);
1149 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1150 emit_d8(cbuf, offset);
1151 }
1152 }
1153
1154 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1155 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1156 if( offset >= 128 ) {
1157 return 7;
1158 }
1159 else {
1160 return 4;
1161 }
1162 }
1163
1164 //=============================================================================
1165
1166 // emit call stub, compiled java to interpreter
1167 void emit_java_to_interp(CodeBuffer &cbuf ) {
1168 // Stub is fixed up when the corresponding call is converted from calling
1169 // compiled code to calling interpreted code.
1170 // mov rbx,0
1171 // jmp -1
1172
1173 address mark = cbuf.insts_mark(); // get mark within main instrs section
1174
1175 // Note that the code buffer's insts_mark is always relative to insts.
1176 // That's why we must use the macroassembler to generate a stub.
1177 MacroAssembler _masm(&cbuf);
1178
1179 address base =
1180 __ start_a_stub(Compile::MAX_stubs_size);
1181 if (base == NULL) return; // CodeBuffer::expand failed
1182 // static stub relocation stores the instruction address of the call
1183 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1184 // static stub relocation also tags the methodOop in the code-stream.
1185 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1186 // This is recognized as unresolved by relocs/nativeInst/ic code
1187 __ jump(RuntimeAddress(__ pc()));
1188
1189 __ end_a_stub();
1190 // Update current stubs pointer and restore insts_end.
1191 }
1192 // size of call stub, compiled java to interpretor
1193 uint size_java_to_interp() {
1194 return 10; // movl; jmp
1195 }
1196 // relocation entries for call stub, compiled java to interpretor
1197 uint reloc_java_to_interp() {
1198 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1199 }
1200
1201 //=============================================================================
1202 #ifndef PRODUCT
1203 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1204 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1205 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1206 st->print_cr("\tNOP");
1207 st->print_cr("\tNOP");
1208 if( !OptoBreakpoint )
1209 st->print_cr("\tNOP");
1210 }
1211 #endif
1212
1213 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1214 MacroAssembler masm(&cbuf);
1215 #ifdef ASSERT
1216 uint insts_size = cbuf.insts_size();
1217 #endif
1218 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1219 masm.jump_cc(Assembler::notEqual,
1220 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1221 /* WARNING these NOPs are critical so that verified entry point is properly
1222 aligned for patching by NativeJump::patch_verified_entry() */
1223 int nops_cnt = 2;
1224 if( !OptoBreakpoint ) // Leave space for int3
1225 nops_cnt += 1;
1226 masm.nop(nops_cnt);
1227
1228 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1229 }
1230
1231 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1232 return OptoBreakpoint ? 11 : 12;
1233 }
1234
1235
1236 //=============================================================================
1237 uint size_exception_handler() {
1238 // NativeCall instruction size is the same as NativeJump.
1239 // exception handler starts out as jump and can be patched to
1240 // a call be deoptimization. (4932387)
1241 // Note that this value is also credited (in output.cpp) to
1242 // the size of the code section.
1243 return NativeJump::instruction_size;
1244 }
1245
1246 // Emit exception handler code. Stuff framesize into a register
1247 // and call a VM stub routine.
1248 int emit_exception_handler(CodeBuffer& cbuf) {
1249
1250 // Note that the code buffer's insts_mark is always relative to insts.
1251 // That's why we must use the macroassembler to generate a handler.
1252 MacroAssembler _masm(&cbuf);
1253 address base =
1254 __ start_a_stub(size_exception_handler());
1255 if (base == NULL) return 0; // CodeBuffer::expand failed
1256 int offset = __ offset();
1257 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1258 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1259 __ end_a_stub();
1260 return offset;
1261 }
1262
1263 uint size_deopt_handler() {
1264 // NativeCall instruction size is the same as NativeJump.
1265 // exception handler starts out as jump and can be patched to
1266 // a call be deoptimization. (4932387)
1267 // Note that this value is also credited (in output.cpp) to
1268 // the size of the code section.
1269 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1270 }
1271
1272 // Emit deopt handler code.
1273 int emit_deopt_handler(CodeBuffer& cbuf) {
1274
1275 // Note that the code buffer's insts_mark is always relative to insts.
1276 // That's why we must use the macroassembler to generate a handler.
1277 MacroAssembler _masm(&cbuf);
1278 address base =
1279 __ start_a_stub(size_exception_handler());
1280 if (base == NULL) return 0; // CodeBuffer::expand failed
1281 int offset = __ offset();
1282 InternalAddress here(__ pc());
1283 __ pushptr(here.addr());
1284
1285 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1286 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1287 __ end_a_stub();
1288 return offset;
1289 }
1290
1291
1292 const bool Matcher::match_rule_supported(int opcode) {
1293 if (!has_match_rule(opcode))
1294 return false;
1295
1296 switch (opcode) {
1297 case Op_PopCountI:
1298 case Op_PopCountL:
1299 if (!UsePopCountInstruction)
1300 return false;
1301 break;
1302 }
1303
1304 return true; // Per default match rules are supported.
1305 }
1306
1307 int Matcher::regnum_to_fpu_offset(int regnum) {
1308 return regnum - 32; // The FP registers are in the second chunk
1309 }
1310
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1315
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1320
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1325
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1331 // The passed offset is relative to address of the branch.
1332 // On 86 a branch displacement is calculated relative to address
1333 // of a next instruction.
1334 offset -= br_size;
1335
1336 // the short version of jmpConUCF2 contains multiple branches,
1337 // making the reach slightly less
1338 if (rule == jmpConUCF2_rule)
1339 return (-126 <= offset && offset <= 125);
1340 return (-128 <= offset && offset <= 127);
1341 }
1342
1343 const bool Matcher::isSimpleConstant64(jlong value) {
1344 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1345 return false;
1346 }
1347
1348 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1349 const bool Matcher::init_array_count_is_in_bytes = false;
1350
1351 // Threshold size for cleararray.
1352 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1353
1354 // Needs 2 CMOV's for longs.
1355 const int Matcher::long_cmove_cost() { return 1; }
1356
1357 // No CMOVF/CMOVD with SSE/SSE2
1358 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1359
1360 // Should the Matcher clone shifts on addressing modes, expecting them to
1361 // be subsumed into complex addressing expressions or compute them into
1362 // registers? True for Intel but false for most RISCs
1363 const bool Matcher::clone_shift_expressions = true;
1364
1365 // Do we need to mask the count passed to shift instructions or does
1366 // the cpu only look at the lower 5/6 bits anyway?
1367 const bool Matcher::need_masked_shift_count = false;
1368
1369 bool Matcher::narrow_oop_use_complex_address() {
1370 ShouldNotCallThis();
1371 return true;
1372 }
1373
1374
1375 // Is it better to copy float constants, or load them directly from memory?
1376 // Intel can load a float constant from a direct address, requiring no
1377 // extra registers. Most RISCs will have to materialize an address into a
1378 // register first, so they would do better to copy the constant from stack.
1379 const bool Matcher::rematerialize_float_constants = true;
1380
1381 // If CPU can load and store mis-aligned doubles directly then no fixup is
1382 // needed. Else we split the double into 2 integer pieces and move it
1383 // piece-by-piece. Only happens when passing doubles into C code as the
1384 // Java calling convention forces doubles to be aligned.
1385 const bool Matcher::misaligned_doubles_ok = true;
1386
1387
1388 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1389 // Get the memory operand from the node
1390 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1391 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1392 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1393 uint opcnt = 1; // First operand
1394 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1395 while( idx >= skipped+num_edges ) {
1396 skipped += num_edges;
1397 opcnt++; // Bump operand count
1398 assert( opcnt < numopnds, "Accessing non-existent operand" );
1399 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1400 }
1401
1402 MachOper *memory = node->_opnds[opcnt];
1403 MachOper *new_memory = NULL;
1404 switch (memory->opcode()) {
1405 case DIRECT:
1406 case INDOFFSET32X:
1407 // No transformation necessary.
1408 return;
1409 case INDIRECT:
1410 new_memory = new (C) indirect_win95_safeOper( );
1411 break;
1412 case INDOFFSET8:
1413 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1414 break;
1415 case INDOFFSET32:
1416 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1417 break;
1418 case INDINDEXOFFSET:
1419 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1420 break;
1421 case INDINDEXSCALE:
1422 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1423 break;
1424 case INDINDEXSCALEOFFSET:
1425 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1426 break;
1427 case LOAD_LONG_INDIRECT:
1428 case LOAD_LONG_INDOFFSET32:
1429 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1430 return;
1431 default:
1432 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1433 return;
1434 }
1435 node->_opnds[opcnt] = new_memory;
1436 }
1437
1438 // Advertise here if the CPU requires explicit rounding operations
1439 // to implement the UseStrictFP mode.
1440 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1441
1442 // Are floats conerted to double when stored to stack during deoptimization?
1443 // On x32 it is stored with convertion only when FPU is used for floats.
1444 bool Matcher::float_in_double() { return (UseSSE == 0); }
1445
1446 // Do ints take an entire long register or just half?
1447 const bool Matcher::int_in_long = false;
1448
1449 // Return whether or not this register is ever used as an argument. This
1450 // function is used on startup to build the trampoline stubs in generateOptoStub.
1451 // Registers not mentioned will be killed by the VM call in the trampoline, and
1452 // arguments in those registers not be available to the callee.
1453 bool Matcher::can_be_java_arg( int reg ) {
1454 if( reg == ECX_num || reg == EDX_num ) return true;
1455 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1456 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1457 return false;
1458 }
1459
1460 bool Matcher::is_spillable_arg( int reg ) {
1461 return can_be_java_arg(reg);
1462 }
1463
1464 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1465 // Use hardware integer DIV instruction when
1466 // it is faster than a code which use multiply.
1467 // Only when constant divisor fits into 32 bit
1468 // (min_jint is excluded to get only correct
1469 // positive 32 bit values from negative).
1470 return VM_Version::has_fast_idiv() &&
1471 (divisor == (int)divisor && divisor != min_jint);
1472 }
1473
1474 // Register for DIVI projection of divmodI
1475 RegMask Matcher::divI_proj_mask() {
1476 return EAX_REG_mask();
1477 }
1478
1479 // Register for MODI projection of divmodI
1480 RegMask Matcher::modI_proj_mask() {
1481 return EDX_REG_mask();
1482 }
1483
1484 // Register for DIVL projection of divmodL
1485 RegMask Matcher::divL_proj_mask() {
1486 ShouldNotReachHere();
1487 return RegMask();
1488 }
1489
1490 // Register for MODL projection of divmodL
1491 RegMask Matcher::modL_proj_mask() {
1492 ShouldNotReachHere();
1493 return RegMask();
1494 }
1495
1496 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1497 return EBP_REG_mask();
1498 }
1499
1500 // Returns true if the high 32 bits of the value is known to be zero.
1501 bool is_operand_hi32_zero(Node* n) {
1502 int opc = n->Opcode();
1503 if (opc == Op_LoadUI2L) {
1504 return true;
1505 }
1506 if (opc == Op_AndL) {
1507 Node* o2 = n->in(2);
1508 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1509 return true;
1510 }
1511 }
1512 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1513 return true;
1514 }
1515 return false;
1516 }
1517
1518 %}
1519
1520 //----------ENCODING BLOCK-----------------------------------------------------
1521 // This block specifies the encoding classes used by the compiler to output
1522 // byte streams. Encoding classes generate functions which are called by
1523 // Machine Instruction Nodes in order to generate the bit encoding of the
1524 // instruction. Operands specify their base encoding interface with the
1525 // interface keyword. There are currently supported four interfaces,
1526 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1527 // operand to generate a function which returns its register number when
1528 // queried. CONST_INTER causes an operand to generate a function which
1529 // returns the value of the constant when queried. MEMORY_INTER causes an
1530 // operand to generate four functions which return the Base Register, the
1531 // Index Register, the Scale Value, and the Offset Value of the operand when
1532 // queried. COND_INTER causes an operand to generate six functions which
1533 // return the encoding code (ie - encoding bits for the instruction)
1534 // associated with each basic boolean condition for a conditional instruction.
1535 // Instructions specify two basic values for encoding. They use the
1536 // ins_encode keyword to specify their encoding class (which must be one of
1537 // the class names specified in the encoding block), and they use the
1538 // opcode keyword to specify, in order, their primary, secondary, and
1539 // tertiary opcode. Only the opcode sections which a particular instruction
1540 // needs for encoding need to be specified.
1541 encode %{
1542 // Build emit functions for each basic byte or larger field in the intel
1543 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1544 // code in the enc_class source block. Emit functions will live in the
1545 // main source block for now. In future, we can generalize this by
1546 // adding a syntax that specifies the sizes of fields in an order,
1547 // so that the adlc can build the emit functions automagically
1548
1549 // Emit primary opcode
1550 enc_class OpcP %{
1551 emit_opcode(cbuf, $primary);
1552 %}
1553
1554 // Emit secondary opcode
1555 enc_class OpcS %{
1556 emit_opcode(cbuf, $secondary);
1557 %}
1558
1559 // Emit opcode directly
1560 enc_class Opcode(immI d8) %{
1561 emit_opcode(cbuf, $d8$$constant);
1562 %}
1563
1564 enc_class SizePrefix %{
1565 emit_opcode(cbuf,0x66);
1566 %}
1567
1568 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1569 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1570 %}
1571
1572 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1573 emit_opcode(cbuf,$opcode$$constant);
1574 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1575 %}
1576
1577 enc_class mov_r32_imm0( eRegI dst ) %{
1578 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1579 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1580 %}
1581
1582 enc_class cdq_enc %{
1583 // Full implementation of Java idiv and irem; checks for
1584 // special case as described in JVM spec., p.243 & p.271.
1585 //
1586 // normal case special case
1587 //
1588 // input : rax,: dividend min_int
1589 // reg: divisor -1
1590 //
1591 // output: rax,: quotient (= rax, idiv reg) min_int
1592 // rdx: remainder (= rax, irem reg) 0
1593 //
1594 // Code sequnce:
1595 //
1596 // 81 F8 00 00 00 80 cmp rax,80000000h
1597 // 0F 85 0B 00 00 00 jne normal_case
1598 // 33 D2 xor rdx,edx
1599 // 83 F9 FF cmp rcx,0FFh
1600 // 0F 84 03 00 00 00 je done
1601 // normal_case:
1602 // 99 cdq
1603 // F7 F9 idiv rax,ecx
1604 // done:
1605 //
1606 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1609 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1610 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1611 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1612 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1613 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1614 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1615 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1616 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1617 // normal_case:
1618 emit_opcode(cbuf,0x99); // cdq
1619 // idiv (note: must be emitted by the user of this rule)
1620 // normal:
1621 %}
1622
1623 // Dense encoding for older common ops
1624 enc_class Opc_plus(immI opcode, eRegI reg) %{
1625 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1626 %}
1627
1628
1629 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1630 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1631 // Check for 8-bit immediate, and set sign extend bit in opcode
1632 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1633 emit_opcode(cbuf, $primary | 0x02);
1634 }
1635 else { // If 32-bit immediate
1636 emit_opcode(cbuf, $primary);
1637 }
1638 %}
1639
1640 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1641 // Emit primary opcode and set sign-extend bit
1642 // Check for 8-bit immediate, and set sign extend bit in opcode
1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1644 emit_opcode(cbuf, $primary | 0x02); }
1645 else { // If 32-bit immediate
1646 emit_opcode(cbuf, $primary);
1647 }
1648 // Emit r/m byte with secondary opcode, after primary opcode.
1649 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1650 %}
1651
1652 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1653 // Check for 8-bit immediate, and set sign extend bit in opcode
1654 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1655 $$$emit8$imm$$constant;
1656 }
1657 else { // If 32-bit immediate
1658 // Output immediate
1659 $$$emit32$imm$$constant;
1660 }
1661 %}
1662
1663 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1664 // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 int con = (int)$imm$$constant; // Throw away top bits
1667 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1668 // Emit r/m byte with secondary opcode, after primary opcode.
1669 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1670 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1671 else emit_d32(cbuf,con);
1672 %}
1673
1674 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1675 // Emit primary opcode and set sign-extend bit
1676 // Check for 8-bit immediate, and set sign extend bit in opcode
1677 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1678 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1679 // Emit r/m byte with tertiary opcode, after primary opcode.
1680 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1681 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1682 else emit_d32(cbuf,con);
1683 %}
1684
1685 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1686 emit_cc(cbuf, $secondary, $dst$$reg );
1687 %}
1688
1689 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1690 int destlo = $dst$$reg;
1691 int desthi = HIGH_FROM_LOW(destlo);
1692 // bswap lo
1693 emit_opcode(cbuf, 0x0F);
1694 emit_cc(cbuf, 0xC8, destlo);
1695 // bswap hi
1696 emit_opcode(cbuf, 0x0F);
1697 emit_cc(cbuf, 0xC8, desthi);
1698 // xchg lo and hi
1699 emit_opcode(cbuf, 0x87);
1700 emit_rm(cbuf, 0x3, destlo, desthi);
1701 %}
1702
1703 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1704 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1705 %}
1706
1707 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1708 $$$emit8$primary;
1709 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1710 %}
1711
1712 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1713 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1714 emit_d8(cbuf, op >> 8 );
1715 emit_d8(cbuf, op & 255);
1716 %}
1717
1718 // emulate a CMOV with a conditional branch around a MOV
1719 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1720 // Invert sense of branch from sense of CMOV
1721 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1722 emit_d8( cbuf, $brOffs$$constant );
1723 %}
1724
1725 enc_class enc_PartialSubtypeCheck( ) %{
1726 Register Redi = as_Register(EDI_enc); // result register
1727 Register Reax = as_Register(EAX_enc); // super class
1728 Register Recx = as_Register(ECX_enc); // killed
1729 Register Resi = as_Register(ESI_enc); // sub class
1730 Label miss;
1731
1732 MacroAssembler _masm(&cbuf);
1733 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1734 NULL, &miss,
1735 /*set_cond_codes:*/ true);
1736 if ($primary) {
1737 __ xorptr(Redi, Redi);
1738 }
1739 __ bind(miss);
1740 %}
1741
1742 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1743 MacroAssembler masm(&cbuf);
1744 int start = masm.offset();
1745 if (UseSSE >= 2) {
1746 if (VerifyFPU) {
1747 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1748 }
1749 } else {
1750 // External c_calling_convention expects the FPU stack to be 'clean'.
1751 // Compiled code leaves it dirty. Do cleanup now.
1752 masm.empty_FPU_stack();
1753 }
1754 if (sizeof_FFree_Float_Stack_All == -1) {
1755 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1756 } else {
1757 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1758 }
1759 %}
1760
1761 enc_class Verify_FPU_For_Leaf %{
1762 if( VerifyFPU ) {
1763 MacroAssembler masm(&cbuf);
1764 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1765 }
1766 %}
1767
1768 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1769 // This is the instruction starting address for relocation info.
1770 cbuf.set_insts_mark();
1771 $$$emit8$primary;
1772 // CALL directly to the runtime
1773 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1774 runtime_call_Relocation::spec(), RELOC_IMM32 );
1775
1776 if (UseSSE >= 2) {
1777 MacroAssembler _masm(&cbuf);
1778 BasicType rt = tf()->return_type();
1779
1780 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1781 // A C runtime call where the return value is unused. In SSE2+
1782 // mode the result needs to be removed from the FPU stack. It's
1783 // likely that this function call could be removed by the
1784 // optimizer if the C function is a pure function.
1785 __ ffree(0);
1786 } else if (rt == T_FLOAT) {
1787 __ lea(rsp, Address(rsp, -4));
1788 __ fstp_s(Address(rsp, 0));
1789 __ movflt(xmm0, Address(rsp, 0));
1790 __ lea(rsp, Address(rsp, 4));
1791 } else if (rt == T_DOUBLE) {
1792 __ lea(rsp, Address(rsp, -8));
1793 __ fstp_d(Address(rsp, 0));
1794 __ movdbl(xmm0, Address(rsp, 0));
1795 __ lea(rsp, Address(rsp, 8));
1796 }
1797 }
1798 %}
1799
1800
1801 enc_class pre_call_FPU %{
1802 // If method sets FPU control word restore it here
1803 debug_only(int off0 = cbuf.insts_size());
1804 if( Compile::current()->in_24_bit_fp_mode() ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1807 }
1808 debug_only(int off1 = cbuf.insts_size());
1809 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1810 %}
1811
1812 enc_class post_call_FPU %{
1813 // If method sets FPU control word do it here also
1814 if( Compile::current()->in_24_bit_fp_mode() ) {
1815 MacroAssembler masm(&cbuf);
1816 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1817 }
1818 %}
1819
1820 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1821 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1822 // who we intended to call.
1823 cbuf.set_insts_mark();
1824 $$$emit8$primary;
1825 if ( !_method ) {
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 runtime_call_Relocation::spec(), RELOC_IMM32 );
1828 } else if(_optimized_virtual) {
1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1830 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1831 } else {
1832 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1833 static_call_Relocation::spec(), RELOC_IMM32 );
1834 }
1835 if( _method ) { // Emit stub for static call
1836 emit_java_to_interp(cbuf);
1837 }
1838 %}
1839
1840 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1841 // !!!!!
1842 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1843 // emit_call_dynamic_prologue( cbuf );
1844 cbuf.set_insts_mark();
1845 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1846 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1847 address virtual_call_oop_addr = cbuf.insts_mark();
1848 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1849 // who we intended to call.
1850 cbuf.set_insts_mark();
1851 $$$emit8$primary;
1852 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1853 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1854 %}
1855
1856 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1857 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1858 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1859
1860 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1861 cbuf.set_insts_mark();
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1864 emit_d8(cbuf, disp); // Displacement
1865
1866 %}
1867
1868 // Following encoding is no longer used, but may be restored if calling
1869 // convention changes significantly.
1870 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1871 //
1872 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1873 // // int ic_reg = Matcher::inline_cache_reg();
1874 // // int ic_encode = Matcher::_regEncode[ic_reg];
1875 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1876 // // int imo_encode = Matcher::_regEncode[imo_reg];
1877 //
1878 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1879 // // // so we load it immediately before the call
1880 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1881 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1882 //
1883 // // xor rbp,ebp
1884 // emit_opcode(cbuf, 0x33);
1885 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1886 //
1887 // // CALL to interpreter.
1888 // cbuf.set_insts_mark();
1889 // $$$emit8$primary;
1890 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1891 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1892 // %}
1893
1894 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1895 $$$emit8$primary;
1896 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1897 $$$emit8$shift$$constant;
1898 %}
1899
1900 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1901 // Load immediate does not have a zero or sign extended version
1902 // for 8-bit immediates
1903 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1904 $$$emit32$src$$constant;
1905 %}
1906
1907 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1908 // Load immediate does not have a zero or sign extended version
1909 // for 8-bit immediates
1910 emit_opcode(cbuf, $primary + $dst$$reg);
1911 $$$emit32$src$$constant;
1912 %}
1913
1914 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1915 // Load immediate does not have a zero or sign extended version
1916 // for 8-bit immediates
1917 int dst_enc = $dst$$reg;
1918 int src_con = $src$$constant & 0x0FFFFFFFFL;
1919 if (src_con == 0) {
1920 // xor dst, dst
1921 emit_opcode(cbuf, 0x33);
1922 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1923 } else {
1924 emit_opcode(cbuf, $primary + dst_enc);
1925 emit_d32(cbuf, src_con);
1926 }
1927 %}
1928
1929 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 int dst_enc = $dst$$reg + 2;
1933 int src_con = ((julong)($src$$constant)) >> 32;
1934 if (src_con == 0) {
1935 // xor dst, dst
1936 emit_opcode(cbuf, 0x33);
1937 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1938 } else {
1939 emit_opcode(cbuf, $primary + dst_enc);
1940 emit_d32(cbuf, src_con);
1941 }
1942 %}
1943
1944
1945 // Encode a reg-reg copy. If it is useless, then empty encoding.
1946 enc_class enc_Copy( eRegI dst, eRegI src ) %{
1947 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1948 %}
1949
1950 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
1951 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1952 %}
1953
1954 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1956 %}
1957
1958 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1959 $$$emit8$primary;
1960 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1961 %}
1962
1963 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1964 $$$emit8$secondary;
1965 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1966 %}
1967
1968 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1969 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1970 %}
1971
1972 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1974 %}
1975
1976 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
1977 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1978 %}
1979
1980 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1981 // Output immediate
1982 $$$emit32$src$$constant;
1983 %}
1984
1985 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1986 // Output Float immediate bits
1987 jfloat jf = $src$$constant;
1988 int jf_as_bits = jint_cast( jf );
1989 emit_d32(cbuf, jf_as_bits);
1990 %}
1991
1992 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1993 // Output Float immediate bits
1994 jfloat jf = $src$$constant;
1995 int jf_as_bits = jint_cast( jf );
1996 emit_d32(cbuf, jf_as_bits);
1997 %}
1998
1999 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2000 // Output immediate
2001 $$$emit16$src$$constant;
2002 %}
2003
2004 enc_class Con_d32(immI src) %{
2005 emit_d32(cbuf,$src$$constant);
2006 %}
2007
2008 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2009 // Output immediate memory reference
2010 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2011 emit_d32(cbuf, 0x00);
2012 %}
2013
2014 enc_class lock_prefix( ) %{
2015 if( os::is_MP() )
2016 emit_opcode(cbuf,0xF0); // [Lock]
2017 %}
2018
2019 // Cmp-xchg long value.
2020 // Note: we need to swap rbx, and rcx before and after the
2021 // cmpxchg8 instruction because the instruction uses
2022 // rcx as the high order word of the new value to store but
2023 // our register encoding uses rbx,.
2024 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2025
2026 // XCHG rbx,ecx
2027 emit_opcode(cbuf,0x87);
2028 emit_opcode(cbuf,0xD9);
2029 // [Lock]
2030 if( os::is_MP() )
2031 emit_opcode(cbuf,0xF0);
2032 // CMPXCHG8 [Eptr]
2033 emit_opcode(cbuf,0x0F);
2034 emit_opcode(cbuf,0xC7);
2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2036 // XCHG rbx,ecx
2037 emit_opcode(cbuf,0x87);
2038 emit_opcode(cbuf,0xD9);
2039 %}
2040
2041 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2042 // [Lock]
2043 if( os::is_MP() )
2044 emit_opcode(cbuf,0xF0);
2045
2046 // CMPXCHG [Eptr]
2047 emit_opcode(cbuf,0x0F);
2048 emit_opcode(cbuf,0xB1);
2049 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2050 %}
2051
2052 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2053 int res_encoding = $res$$reg;
2054
2055 // MOV res,0
2056 emit_opcode( cbuf, 0xB8 + res_encoding);
2057 emit_d32( cbuf, 0 );
2058 // JNE,s fail
2059 emit_opcode(cbuf,0x75);
2060 emit_d8(cbuf, 5 );
2061 // MOV res,1
2062 emit_opcode( cbuf, 0xB8 + res_encoding);
2063 emit_d32( cbuf, 1 );
2064 // fail:
2065 %}
2066
2067 enc_class set_instruction_start( ) %{
2068 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2069 %}
2070
2071 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2072 int reg_encoding = $ereg$$reg;
2073 int base = $mem$$base;
2074 int index = $mem$$index;
2075 int scale = $mem$$scale;
2076 int displace = $mem$$disp;
2077 bool disp_is_oop = $mem->disp_is_oop();
2078 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2079 %}
2080
2081 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2082 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2083 int base = $mem$$base;
2084 int index = $mem$$index;
2085 int scale = $mem$$scale;
2086 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2087 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2088 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2089 %}
2090
2091 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2092 int r1, r2;
2093 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2094 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2095 emit_opcode(cbuf,0x0F);
2096 emit_opcode(cbuf,$tertiary);
2097 emit_rm(cbuf, 0x3, r1, r2);
2098 emit_d8(cbuf,$cnt$$constant);
2099 emit_d8(cbuf,$primary);
2100 emit_rm(cbuf, 0x3, $secondary, r1);
2101 emit_d8(cbuf,$cnt$$constant);
2102 %}
2103
2104 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2105 emit_opcode( cbuf, 0x8B ); // Move
2106 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2107 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2108 emit_d8(cbuf,$primary);
2109 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2110 emit_d8(cbuf,$cnt$$constant-32);
2111 }
2112 emit_d8(cbuf,$primary);
2113 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2114 emit_d8(cbuf,31);
2115 %}
2116
2117 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2118 int r1, r2;
2119 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2120 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2121
2122 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2123 emit_rm(cbuf, 0x3, r1, r2);
2124 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2125 emit_opcode(cbuf,$primary);
2126 emit_rm(cbuf, 0x3, $secondary, r1);
2127 emit_d8(cbuf,$cnt$$constant-32);
2128 }
2129 emit_opcode(cbuf,0x33); // XOR r2,r2
2130 emit_rm(cbuf, 0x3, r2, r2);
2131 %}
2132
2133 // Clone of RegMem but accepts an extra parameter to access each
2134 // half of a double in memory; it never needs relocation info.
2135 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2136 emit_opcode(cbuf,$opcode$$constant);
2137 int reg_encoding = $rm_reg$$reg;
2138 int base = $mem$$base;
2139 int index = $mem$$index;
2140 int scale = $mem$$scale;
2141 int displace = $mem$$disp + $disp_for_half$$constant;
2142 bool disp_is_oop = false;
2143 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2144 %}
2145
2146 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2147 //
2148 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2149 // and it never needs relocation information.
2150 // Frequently used to move data between FPU's Stack Top and memory.
2151 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2152 int rm_byte_opcode = $rm_opcode$$constant;
2153 int base = $mem$$base;
2154 int index = $mem$$index;
2155 int scale = $mem$$scale;
2156 int displace = $mem$$disp;
2157 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2158 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2159 %}
2160
2161 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2162 int rm_byte_opcode = $rm_opcode$$constant;
2163 int base = $mem$$base;
2164 int index = $mem$$index;
2165 int scale = $mem$$scale;
2166 int displace = $mem$$disp;
2167 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2168 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2169 %}
2170
2171 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2172 int reg_encoding = $dst$$reg;
2173 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2174 int index = 0x04; // 0x04 indicates no index
2175 int scale = 0x00; // 0x00 indicates no scale
2176 int displace = $src1$$constant; // 0x00 indicates no displacement
2177 bool disp_is_oop = false;
2178 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2179 %}
2180
2181 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2182 // Compare dst,src
2183 emit_opcode(cbuf,0x3B);
2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2185 // jmp dst < src around move
2186 emit_opcode(cbuf,0x7C);
2187 emit_d8(cbuf,2);
2188 // move dst,src
2189 emit_opcode(cbuf,0x8B);
2190 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2191 %}
2192
2193 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2194 // Compare dst,src
2195 emit_opcode(cbuf,0x3B);
2196 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2197 // jmp dst > src around move
2198 emit_opcode(cbuf,0x7F);
2199 emit_d8(cbuf,2);
2200 // move dst,src
2201 emit_opcode(cbuf,0x8B);
2202 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2203 %}
2204
2205 enc_class enc_FPR_store(memory mem, regDPR src) %{
2206 // If src is FPR1, we can just FST to store it.
2207 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2208 int reg_encoding = 0x2; // Just store
2209 int base = $mem$$base;
2210 int index = $mem$$index;
2211 int scale = $mem$$scale;
2212 int displace = $mem$$disp;
2213 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2214 if( $src$$reg != FPR1L_enc ) {
2215 reg_encoding = 0x3; // Store & pop
2216 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2217 emit_d8( cbuf, 0xC0-1+$src$$reg );
2218 }
2219 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2220 emit_opcode(cbuf,$primary);
2221 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2222 %}
2223
2224 enc_class neg_reg(eRegI dst) %{
2225 // NEG $dst
2226 emit_opcode(cbuf,0xF7);
2227 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2228 %}
2229
2230 enc_class setLT_reg(eCXRegI dst) %{
2231 // SETLT $dst
2232 emit_opcode(cbuf,0x0F);
2233 emit_opcode(cbuf,0x9C);
2234 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2235 %}
2236
2237 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2238 int tmpReg = $tmp$$reg;
2239
2240 // SUB $p,$q
2241 emit_opcode(cbuf,0x2B);
2242 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2243 // SBB $tmp,$tmp
2244 emit_opcode(cbuf,0x1B);
2245 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2246 // AND $tmp,$y
2247 emit_opcode(cbuf,0x23);
2248 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2249 // ADD $p,$tmp
2250 emit_opcode(cbuf,0x03);
2251 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2252 %}
2253
2254 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2255 int tmpReg = $tmp$$reg;
2256
2257 // SUB $p,$q
2258 emit_opcode(cbuf,0x2B);
2259 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2260 // SBB $tmp,$tmp
2261 emit_opcode(cbuf,0x1B);
2262 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2263 // AND $tmp,$y
2264 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2265 emit_opcode(cbuf,0x23);
2266 int reg_encoding = tmpReg;
2267 int base = $mem$$base;
2268 int index = $mem$$index;
2269 int scale = $mem$$scale;
2270 int displace = $mem$$disp;
2271 bool disp_is_oop = $mem->disp_is_oop();
2272 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2273 // ADD $p,$tmp
2274 emit_opcode(cbuf,0x03);
2275 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2276 %}
2277
2278 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2279 // TEST shift,32
2280 emit_opcode(cbuf,0xF7);
2281 emit_rm(cbuf, 0x3, 0, ECX_enc);
2282 emit_d32(cbuf,0x20);
2283 // JEQ,s small
2284 emit_opcode(cbuf, 0x74);
2285 emit_d8(cbuf, 0x04);
2286 // MOV $dst.hi,$dst.lo
2287 emit_opcode( cbuf, 0x8B );
2288 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2289 // CLR $dst.lo
2290 emit_opcode(cbuf, 0x33);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2292 // small:
2293 // SHLD $dst.hi,$dst.lo,$shift
2294 emit_opcode(cbuf,0x0F);
2295 emit_opcode(cbuf,0xA5);
2296 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2297 // SHL $dst.lo,$shift"
2298 emit_opcode(cbuf,0xD3);
2299 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2300 %}
2301
2302 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2303 // TEST shift,32
2304 emit_opcode(cbuf,0xF7);
2305 emit_rm(cbuf, 0x3, 0, ECX_enc);
2306 emit_d32(cbuf,0x20);
2307 // JEQ,s small
2308 emit_opcode(cbuf, 0x74);
2309 emit_d8(cbuf, 0x04);
2310 // MOV $dst.lo,$dst.hi
2311 emit_opcode( cbuf, 0x8B );
2312 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2313 // CLR $dst.hi
2314 emit_opcode(cbuf, 0x33);
2315 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2316 // small:
2317 // SHRD $dst.lo,$dst.hi,$shift
2318 emit_opcode(cbuf,0x0F);
2319 emit_opcode(cbuf,0xAD);
2320 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2321 // SHR $dst.hi,$shift"
2322 emit_opcode(cbuf,0xD3);
2323 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2324 %}
2325
2326 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2327 // TEST shift,32
2328 emit_opcode(cbuf,0xF7);
2329 emit_rm(cbuf, 0x3, 0, ECX_enc);
2330 emit_d32(cbuf,0x20);
2331 // JEQ,s small
2332 emit_opcode(cbuf, 0x74);
2333 emit_d8(cbuf, 0x05);
2334 // MOV $dst.lo,$dst.hi
2335 emit_opcode( cbuf, 0x8B );
2336 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2337 // SAR $dst.hi,31
2338 emit_opcode(cbuf, 0xC1);
2339 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2340 emit_d8(cbuf, 0x1F );
2341 // small:
2342 // SHRD $dst.lo,$dst.hi,$shift
2343 emit_opcode(cbuf,0x0F);
2344 emit_opcode(cbuf,0xAD);
2345 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2346 // SAR $dst.hi,$shift"
2347 emit_opcode(cbuf,0xD3);
2348 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2349 %}
2350
2351
2352 // ----------------- Encodings for floating point unit -----------------
2353 // May leave result in FPU-TOS or FPU reg depending on opcodes
2354 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2355 $$$emit8$primary;
2356 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2357 %}
2358
2359 // Pop argument in FPR0 with FSTP ST(0)
2360 enc_class PopFPU() %{
2361 emit_opcode( cbuf, 0xDD );
2362 emit_d8( cbuf, 0xD8 );
2363 %}
2364
2365 // !!!!! equivalent to Pop_Reg_F
2366 enc_class Pop_Reg_DPR( regDPR dst ) %{
2367 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2368 emit_d8( cbuf, 0xD8+$dst$$reg );
2369 %}
2370
2371 enc_class Push_Reg_DPR( regDPR dst ) %{
2372 emit_opcode( cbuf, 0xD9 );
2373 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2374 %}
2375
2376 enc_class strictfp_bias1( regDPR dst ) %{
2377 emit_opcode( cbuf, 0xDB ); // FLD m80real
2378 emit_opcode( cbuf, 0x2D );
2379 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2380 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2381 emit_opcode( cbuf, 0xC8+$dst$$reg );
2382 %}
2383
2384 enc_class strictfp_bias2( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xDB ); // FLD m80real
2386 emit_opcode( cbuf, 0x2D );
2387 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2388 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2389 emit_opcode( cbuf, 0xC8+$dst$$reg );
2390 %}
2391
2392 // Special case for moving an integer register to a stack slot.
2393 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2394 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2395 %}
2396
2397 // Special case for moving a register to a stack slot.
2398 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2399 // Opcode already emitted
2400 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2401 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2402 emit_d32(cbuf, $dst$$disp); // Displacement
2403 %}
2404
2405 // Push the integer in stackSlot 'src' onto FP-stack
2406 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2407 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2408 %}
2409
2410 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2411 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2412 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2413 %}
2414
2415 // Same as Pop_Mem_F except for opcode
2416 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2417 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2418 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2419 %}
2420
2421 enc_class Pop_Reg_FPR( regFPR dst ) %{
2422 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2423 emit_d8( cbuf, 0xD8+$dst$$reg );
2424 %}
2425
2426 enc_class Push_Reg_FPR( regFPR dst ) %{
2427 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2428 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2429 %}
2430
2431 // Push FPU's float to a stack-slot, and pop FPU-stack
2432 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2433 int pop = 0x02;
2434 if ($src$$reg != FPR1L_enc) {
2435 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2436 emit_d8( cbuf, 0xC0-1+$src$$reg );
2437 pop = 0x03;
2438 }
2439 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2440 %}
2441
2442 // Push FPU's double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2444 int pop = 0x02;
2445 if ($src$$reg != FPR1L_enc) {
2446 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2447 emit_d8( cbuf, 0xC0-1+$src$$reg );
2448 pop = 0x03;
2449 }
2450 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2451 %}
2452
2453 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2454 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2455 int pop = 0xD0 - 1; // -1 since we skip FLD
2456 if ($src$$reg != FPR1L_enc) {
2457 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2458 emit_d8( cbuf, 0xC0-1+$src$$reg );
2459 pop = 0xD8;
2460 }
2461 emit_opcode( cbuf, 0xDD );
2462 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2463 %}
2464
2465
2466 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2467 // load dst in FPR0
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2470 if ($src$$reg != FPR1L_enc) {
2471 // fincstp
2472 emit_opcode (cbuf, 0xD9);
2473 emit_opcode (cbuf, 0xF7);
2474 // swap src with FPR1:
2475 // FXCH FPR1 with src
2476 emit_opcode(cbuf, 0xD9);
2477 emit_d8(cbuf, 0xC8-1+$src$$reg );
2478 // fdecstp
2479 emit_opcode (cbuf, 0xD9);
2480 emit_opcode (cbuf, 0xF6);
2481 }
2482 %}
2483
2484 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2485 MacroAssembler _masm(&cbuf);
2486 __ subptr(rsp, 8);
2487 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2488 __ fld_d(Address(rsp, 0));
2489 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2490 __ fld_d(Address(rsp, 0));
2491 %}
2492
2493 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2494 MacroAssembler _masm(&cbuf);
2495 __ subptr(rsp, 4);
2496 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2497 __ fld_s(Address(rsp, 0));
2498 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2499 __ fld_s(Address(rsp, 0));
2500 %}
2501
2502 enc_class Push_ResultD(regD dst) %{
2503 MacroAssembler _masm(&cbuf);
2504 __ fstp_d(Address(rsp, 0));
2505 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2506 __ addptr(rsp, 8);
2507 %}
2508
2509 enc_class Push_ResultF(regF dst, immI d8) %{
2510 MacroAssembler _masm(&cbuf);
2511 __ fstp_s(Address(rsp, 0));
2512 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2513 __ addptr(rsp, $d8$$constant);
2514 %}
2515
2516 enc_class Push_SrcD(regD src) %{
2517 MacroAssembler _masm(&cbuf);
2518 __ subptr(rsp, 8);
2519 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2520 __ fld_d(Address(rsp, 0));
2521 %}
2522
2523 enc_class push_stack_temp_qword() %{
2524 MacroAssembler _masm(&cbuf);
2525 __ subptr(rsp, 8);
2526 %}
2527
2528 enc_class pop_stack_temp_qword() %{
2529 MacroAssembler _masm(&cbuf);
2530 __ addptr(rsp, 8);
2531 %}
2532
2533 enc_class push_xmm_to_fpr1(regD src) %{
2534 MacroAssembler _masm(&cbuf);
2535 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2536 __ fld_d(Address(rsp, 0));
2537 %}
2538
2539 enc_class Push_Result_Mod_DPR( regDPR src) %{
2540 if ($src$$reg != FPR1L_enc) {
2541 // fincstp
2542 emit_opcode (cbuf, 0xD9);
2543 emit_opcode (cbuf, 0xF7);
2544 // FXCH FPR1 with src
2545 emit_opcode(cbuf, 0xD9);
2546 emit_d8(cbuf, 0xC8-1+$src$$reg );
2547 // fdecstp
2548 emit_opcode (cbuf, 0xD9);
2549 emit_opcode (cbuf, 0xF6);
2550 }
2551 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2552 // // FSTP FPR$dst$$reg
2553 // emit_opcode( cbuf, 0xDD );
2554 // emit_d8( cbuf, 0xD8+$dst$$reg );
2555 %}
2556
2557 enc_class fnstsw_sahf_skip_parity() %{
2558 // fnstsw ax
2559 emit_opcode( cbuf, 0xDF );
2560 emit_opcode( cbuf, 0xE0 );
2561 // sahf
2562 emit_opcode( cbuf, 0x9E );
2563 // jnp ::skip
2564 emit_opcode( cbuf, 0x7B );
2565 emit_opcode( cbuf, 0x05 );
2566 %}
2567
2568 enc_class emitModDPR() %{
2569 // fprem must be iterative
2570 // :: loop
2571 // fprem
2572 emit_opcode( cbuf, 0xD9 );
2573 emit_opcode( cbuf, 0xF8 );
2574 // wait
2575 emit_opcode( cbuf, 0x9b );
2576 // fnstsw ax
2577 emit_opcode( cbuf, 0xDF );
2578 emit_opcode( cbuf, 0xE0 );
2579 // sahf
2580 emit_opcode( cbuf, 0x9E );
2581 // jp ::loop
2582 emit_opcode( cbuf, 0x0F );
2583 emit_opcode( cbuf, 0x8A );
2584 emit_opcode( cbuf, 0xF4 );
2585 emit_opcode( cbuf, 0xFF );
2586 emit_opcode( cbuf, 0xFF );
2587 emit_opcode( cbuf, 0xFF );
2588 %}
2589
2590 enc_class fpu_flags() %{
2591 // fnstsw_ax
2592 emit_opcode( cbuf, 0xDF);
2593 emit_opcode( cbuf, 0xE0);
2594 // test ax,0x0400
2595 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2596 emit_opcode( cbuf, 0xA9 );
2597 emit_d16 ( cbuf, 0x0400 );
2598 // // // This sequence works, but stalls for 12-16 cycles on PPro
2599 // // test rax,0x0400
2600 // emit_opcode( cbuf, 0xA9 );
2601 // emit_d32 ( cbuf, 0x00000400 );
2602 //
2603 // jz exit (no unordered comparison)
2604 emit_opcode( cbuf, 0x74 );
2605 emit_d8 ( cbuf, 0x02 );
2606 // mov ah,1 - treat as LT case (set carry flag)
2607 emit_opcode( cbuf, 0xB4 );
2608 emit_d8 ( cbuf, 0x01 );
2609 // sahf
2610 emit_opcode( cbuf, 0x9E);
2611 %}
2612
2613 enc_class cmpF_P6_fixup() %{
2614 // Fixup the integer flags in case comparison involved a NaN
2615 //
2616 // JNP exit (no unordered comparison, P-flag is set by NaN)
2617 emit_opcode( cbuf, 0x7B );
2618 emit_d8 ( cbuf, 0x03 );
2619 // MOV AH,1 - treat as LT case (set carry flag)
2620 emit_opcode( cbuf, 0xB4 );
2621 emit_d8 ( cbuf, 0x01 );
2622 // SAHF
2623 emit_opcode( cbuf, 0x9E);
2624 // NOP // target for branch to avoid branch to branch
2625 emit_opcode( cbuf, 0x90);
2626 %}
2627
2628 // fnstsw_ax();
2629 // sahf();
2630 // movl(dst, nan_result);
2631 // jcc(Assembler::parity, exit);
2632 // movl(dst, less_result);
2633 // jcc(Assembler::below, exit);
2634 // movl(dst, equal_result);
2635 // jcc(Assembler::equal, exit);
2636 // movl(dst, greater_result);
2637
2638 // less_result = 1;
2639 // greater_result = -1;
2640 // equal_result = 0;
2641 // nan_result = -1;
2642
2643 enc_class CmpF_Result(eRegI dst) %{
2644 // fnstsw_ax();
2645 emit_opcode( cbuf, 0xDF);
2646 emit_opcode( cbuf, 0xE0);
2647 // sahf
2648 emit_opcode( cbuf, 0x9E);
2649 // movl(dst, nan_result);
2650 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2651 emit_d32( cbuf, -1 );
2652 // jcc(Assembler::parity, exit);
2653 emit_opcode( cbuf, 0x7A );
2654 emit_d8 ( cbuf, 0x13 );
2655 // movl(dst, less_result);
2656 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2657 emit_d32( cbuf, -1 );
2658 // jcc(Assembler::below, exit);
2659 emit_opcode( cbuf, 0x72 );
2660 emit_d8 ( cbuf, 0x0C );
2661 // movl(dst, equal_result);
2662 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2663 emit_d32( cbuf, 0 );
2664 // jcc(Assembler::equal, exit);
2665 emit_opcode( cbuf, 0x74 );
2666 emit_d8 ( cbuf, 0x05 );
2667 // movl(dst, greater_result);
2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2669 emit_d32( cbuf, 1 );
2670 %}
2671
2672
2673 // Compare the longs and set flags
2674 // BROKEN! Do Not use as-is
2675 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2676 // CMP $src1.hi,$src2.hi
2677 emit_opcode( cbuf, 0x3B );
2678 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2679 // JNE,s done
2680 emit_opcode(cbuf,0x75);
2681 emit_d8(cbuf, 2 );
2682 // CMP $src1.lo,$src2.lo
2683 emit_opcode( cbuf, 0x3B );
2684 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2685 // done:
2686 %}
2687
2688 enc_class convert_int_long( regL dst, eRegI src ) %{
2689 // mov $dst.lo,$src
2690 int dst_encoding = $dst$$reg;
2691 int src_encoding = $src$$reg;
2692 encode_Copy( cbuf, dst_encoding , src_encoding );
2693 // mov $dst.hi,$src
2694 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2695 // sar $dst.hi,31
2696 emit_opcode( cbuf, 0xC1 );
2697 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2698 emit_d8(cbuf, 0x1F );
2699 %}
2700
2701 enc_class convert_long_double( eRegL src ) %{
2702 // push $src.hi
2703 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2704 // push $src.lo
2705 emit_opcode(cbuf, 0x50+$src$$reg );
2706 // fild 64-bits at [SP]
2707 emit_opcode(cbuf,0xdf);
2708 emit_d8(cbuf, 0x6C);
2709 emit_d8(cbuf, 0x24);
2710 emit_d8(cbuf, 0x00);
2711 // pop stack
2712 emit_opcode(cbuf, 0x83); // add SP, #8
2713 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2714 emit_d8(cbuf, 0x8);
2715 %}
2716
2717 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2718 // IMUL EDX:EAX,$src1
2719 emit_opcode( cbuf, 0xF7 );
2720 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2721 // SAR EDX,$cnt-32
2722 int shift_count = ((int)$cnt$$constant) - 32;
2723 if (shift_count > 0) {
2724 emit_opcode(cbuf, 0xC1);
2725 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2726 emit_d8(cbuf, shift_count);
2727 }
2728 %}
2729
2730 // this version doesn't have add sp, 8
2731 enc_class convert_long_double2( eRegL src ) %{
2732 // push $src.hi
2733 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2734 // push $src.lo
2735 emit_opcode(cbuf, 0x50+$src$$reg );
2736 // fild 64-bits at [SP]
2737 emit_opcode(cbuf,0xdf);
2738 emit_d8(cbuf, 0x6C);
2739 emit_d8(cbuf, 0x24);
2740 emit_d8(cbuf, 0x00);
2741 %}
2742
2743 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2744 // Basic idea: long = (long)int * (long)int
2745 // IMUL EDX:EAX, src
2746 emit_opcode( cbuf, 0xF7 );
2747 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2748 %}
2749
2750 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2751 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2752 // MUL EDX:EAX, src
2753 emit_opcode( cbuf, 0xF7 );
2754 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2755 %}
2756
2757 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2758 // Basic idea: lo(result) = lo(x_lo * y_lo)
2759 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2760 // MOV $tmp,$src.lo
2761 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2762 // IMUL $tmp,EDX
2763 emit_opcode( cbuf, 0x0F );
2764 emit_opcode( cbuf, 0xAF );
2765 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2766 // MOV EDX,$src.hi
2767 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2768 // IMUL EDX,EAX
2769 emit_opcode( cbuf, 0x0F );
2770 emit_opcode( cbuf, 0xAF );
2771 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2772 // ADD $tmp,EDX
2773 emit_opcode( cbuf, 0x03 );
2774 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2775 // MUL EDX:EAX,$src.lo
2776 emit_opcode( cbuf, 0xF7 );
2777 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2778 // ADD EDX,ESI
2779 emit_opcode( cbuf, 0x03 );
2780 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2781 %}
2782
2783 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(src * y_lo)
2785 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2786 // IMUL $tmp,EDX,$src
2787 emit_opcode( cbuf, 0x6B );
2788 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2789 emit_d8( cbuf, (int)$src$$constant );
2790 // MOV EDX,$src
2791 emit_opcode(cbuf, 0xB8 + EDX_enc);
2792 emit_d32( cbuf, (int)$src$$constant );
2793 // MUL EDX:EAX,EDX
2794 emit_opcode( cbuf, 0xF7 );
2795 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2796 // ADD EDX,ESI
2797 emit_opcode( cbuf, 0x03 );
2798 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2799 %}
2800
2801 enc_class long_div( eRegL src1, eRegL src2 ) %{
2802 // PUSH src1.hi
2803 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2804 // PUSH src1.lo
2805 emit_opcode(cbuf, 0x50+$src1$$reg );
2806 // PUSH src2.hi
2807 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2808 // PUSH src2.lo
2809 emit_opcode(cbuf, 0x50+$src2$$reg );
2810 // CALL directly to the runtime
2811 cbuf.set_insts_mark();
2812 emit_opcode(cbuf,0xE8); // Call into runtime
2813 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2814 // Restore stack
2815 emit_opcode(cbuf, 0x83); // add SP, #framesize
2816 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2817 emit_d8(cbuf, 4*4);
2818 %}
2819
2820 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2821 // PUSH src1.hi
2822 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2823 // PUSH src1.lo
2824 emit_opcode(cbuf, 0x50+$src1$$reg );
2825 // PUSH src2.hi
2826 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2827 // PUSH src2.lo
2828 emit_opcode(cbuf, 0x50+$src2$$reg );
2829 // CALL directly to the runtime
2830 cbuf.set_insts_mark();
2831 emit_opcode(cbuf,0xE8); // Call into runtime
2832 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2833 // Restore stack
2834 emit_opcode(cbuf, 0x83); // add SP, #framesize
2835 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2836 emit_d8(cbuf, 4*4);
2837 %}
2838
2839 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
2840 // MOV $tmp,$src.lo
2841 emit_opcode(cbuf, 0x8B);
2842 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2843 // OR $tmp,$src.hi
2844 emit_opcode(cbuf, 0x0B);
2845 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2846 %}
2847
2848 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2849 // CMP $src1.lo,$src2.lo
2850 emit_opcode( cbuf, 0x3B );
2851 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2852 // JNE,s skip
2853 emit_cc(cbuf, 0x70, 0x5);
2854 emit_d8(cbuf,2);
2855 // CMP $src1.hi,$src2.hi
2856 emit_opcode( cbuf, 0x3B );
2857 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2858 %}
2859
2860 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
2861 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2862 emit_opcode( cbuf, 0x3B );
2863 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2864 // MOV $tmp,$src1.hi
2865 emit_opcode( cbuf, 0x8B );
2866 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2867 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2868 emit_opcode( cbuf, 0x1B );
2869 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2870 %}
2871
2872 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
2873 // XOR $tmp,$tmp
2874 emit_opcode(cbuf,0x33); // XOR
2875 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2876 // CMP $tmp,$src.lo
2877 emit_opcode( cbuf, 0x3B );
2878 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2879 // SBB $tmp,$src.hi
2880 emit_opcode( cbuf, 0x1B );
2881 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2882 %}
2883
2884 // Sniff, sniff... smells like Gnu Superoptimizer
2885 enc_class neg_long( eRegL dst ) %{
2886 emit_opcode(cbuf,0xF7); // NEG hi
2887 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2888 emit_opcode(cbuf,0xF7); // NEG lo
2889 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2890 emit_opcode(cbuf,0x83); // SBB hi,0
2891 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2892 emit_d8 (cbuf,0 );
2893 %}
2894
2895
2896 // Because the transitions from emitted code to the runtime
2897 // monitorenter/exit helper stubs are so slow it's critical that
2898 // we inline both the stack-locking fast-path and the inflated fast path.
2899 //
2900 // See also: cmpFastLock and cmpFastUnlock.
2901 //
2902 // What follows is a specialized inline transliteration of the code
2903 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2904 // another option would be to emit TrySlowEnter and TrySlowExit methods
2905 // at startup-time. These methods would accept arguments as
2906 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2907 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2908 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2909 // In practice, however, the # of lock sites is bounded and is usually small.
2910 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2911 // if the processor uses simple bimodal branch predictors keyed by EIP
2912 // Since the helper routines would be called from multiple synchronization
2913 // sites.
2914 //
2915 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2916 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2917 // to those specialized methods. That'd give us a mostly platform-independent
2918 // implementation that the JITs could optimize and inline at their pleasure.
2919 // Done correctly, the only time we'd need to cross to native could would be
2920 // to park() or unpark() threads. We'd also need a few more unsafe operators
2921 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2922 // (b) explicit barriers or fence operations.
2923 //
2924 // TODO:
2925 //
2926 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2927 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2928 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2929 // the lock operators would typically be faster than reifying Self.
2930 //
2931 // * Ideally I'd define the primitives as:
2932 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2933 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2934 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2935 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2936 // Furthermore the register assignments are overconstrained, possibly resulting in
2937 // sub-optimal code near the synchronization site.
2938 //
2939 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2940 // Alternately, use a better sp-proximity test.
2941 //
2942 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2943 // Either one is sufficient to uniquely identify a thread.
2944 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2945 //
2946 // * Intrinsify notify() and notifyAll() for the common cases where the
2947 // object is locked by the calling thread but the waitlist is empty.
2948 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2949 //
2950 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2951 // But beware of excessive branch density on AMD Opterons.
2952 //
2953 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2954 // or failure of the fast-path. If the fast-path fails then we pass
2955 // control to the slow-path, typically in C. In Fast_Lock and
2956 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2957 // will emit a conditional branch immediately after the node.
2958 // So we have branches to branches and lots of ICC.ZF games.
2959 // Instead, it might be better to have C2 pass a "FailureLabel"
2960 // into Fast_Lock and Fast_Unlock. In the case of success, control
2961 // will drop through the node. ICC.ZF is undefined at exit.
2962 // In the case of failure, the node will branch directly to the
2963 // FailureLabel
2964
2965
2966 // obj: object to lock
2967 // box: on-stack box address (displaced header location) - KILLED
2968 // rax,: tmp -- KILLED
2969 // scr: tmp -- KILLED
2970 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2971
2972 Register objReg = as_Register($obj$$reg);
2973 Register boxReg = as_Register($box$$reg);
2974 Register tmpReg = as_Register($tmp$$reg);
2975 Register scrReg = as_Register($scr$$reg);
2976
2977 // Ensure the register assignents are disjoint
2978 guarantee (objReg != boxReg, "") ;
2979 guarantee (objReg != tmpReg, "") ;
2980 guarantee (objReg != scrReg, "") ;
2981 guarantee (boxReg != tmpReg, "") ;
2982 guarantee (boxReg != scrReg, "") ;
2983 guarantee (tmpReg == as_Register(EAX_enc), "") ;
2984
2985 MacroAssembler masm(&cbuf);
2986
2987 if (_counters != NULL) {
2988 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2989 }
2990 if (EmitSync & 1) {
2991 // set box->dhw = unused_mark (3)
2992 // Force all sync thru slow-path: slow_enter() and slow_exit()
2993 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
2994 masm.cmpptr (rsp, (int32_t)0) ;
2995 } else
2996 if (EmitSync & 2) {
2997 Label DONE_LABEL ;
2998 if (UseBiasedLocking) {
2999 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3000 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3001 }
3002
3003 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3004 masm.orptr (tmpReg, 0x1);
3005 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3006 if (os::is_MP()) { masm.lock(); }
3007 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3008 masm.jcc(Assembler::equal, DONE_LABEL);
3009 // Recursive locking
3010 masm.subptr(tmpReg, rsp);
3011 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3012 masm.movptr(Address(boxReg, 0), tmpReg);
3013 masm.bind(DONE_LABEL) ;
3014 } else {
3015 // Possible cases that we'll encounter in fast_lock
3016 // ------------------------------------------------
3017 // * Inflated
3018 // -- unlocked
3019 // -- Locked
3020 // = by self
3021 // = by other
3022 // * biased
3023 // -- by Self
3024 // -- by other
3025 // * neutral
3026 // * stack-locked
3027 // -- by self
3028 // = sp-proximity test hits
3029 // = sp-proximity test generates false-negative
3030 // -- by other
3031 //
3032
3033 Label IsInflated, DONE_LABEL, PopDone ;
3034
3035 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3036 // order to reduce the number of conditional branches in the most common cases.
3037 // Beware -- there's a subtle invariant that fetch of the markword
3038 // at [FETCH], below, will never observe a biased encoding (*101b).
3039 // If this invariant is not held we risk exclusion (safety) failure.
3040 if (UseBiasedLocking && !UseOptoBiasInlining) {
3041 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3042 }
3043
3044 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3045 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3046 masm.jccb (Assembler::notZero, IsInflated) ;
3047
3048 // Attempt stack-locking ...
3049 masm.orptr (tmpReg, 0x1);
3050 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3051 if (os::is_MP()) { masm.lock(); }
3052 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3053 if (_counters != NULL) {
3054 masm.cond_inc32(Assembler::equal,
3055 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3056 }
3057 masm.jccb (Assembler::equal, DONE_LABEL);
3058
3059 // Recursive locking
3060 masm.subptr(tmpReg, rsp);
3061 masm.andptr(tmpReg, 0xFFFFF003 );
3062 masm.movptr(Address(boxReg, 0), tmpReg);
3063 if (_counters != NULL) {
3064 masm.cond_inc32(Assembler::equal,
3065 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3066 }
3067 masm.jmp (DONE_LABEL) ;
3068
3069 masm.bind (IsInflated) ;
3070
3071 // The object is inflated.
3072 //
3073 // TODO-FIXME: eliminate the ugly use of manifest constants:
3074 // Use markOopDesc::monitor_value instead of "2".
3075 // use markOop::unused_mark() instead of "3".
3076 // The tmpReg value is an objectMonitor reference ORed with
3077 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3078 // objectmonitor pointer by masking off the "2" bit or we can just
3079 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3080 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3081 //
3082 // I use the latter as it avoids AGI stalls.
3083 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3084 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3085 //
3086 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3087
3088 // boxReg refers to the on-stack BasicLock in the current frame.
3089 // We'd like to write:
3090 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3091 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3092 // additional latency as we have another ST in the store buffer that must drain.
3093
3094 if (EmitSync & 8192) {
3095 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3096 masm.get_thread (scrReg) ;
3097 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3098 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3099 if (os::is_MP()) { masm.lock(); }
3100 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3101 } else
3102 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3103 masm.movptr(scrReg, boxReg) ;
3104 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3105
3106 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3107 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3108 // prefetchw [eax + Offset(_owner)-2]
3109 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3110 }
3111
3112 if ((EmitSync & 64) == 0) {
3113 // Optimistic form: consider XORL tmpReg,tmpReg
3114 masm.movptr(tmpReg, NULL_WORD) ;
3115 } else {
3116 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3117 // Test-And-CAS instead of CAS
3118 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3119 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3120 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3121 }
3122
3123 // Appears unlocked - try to swing _owner from null to non-null.
3124 // Ideally, I'd manifest "Self" with get_thread and then attempt
3125 // to CAS the register containing Self into m->Owner.
3126 // But we don't have enough registers, so instead we can either try to CAS
3127 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3128 // we later store "Self" into m->Owner. Transiently storing a stack address
3129 // (rsp or the address of the box) into m->owner is harmless.
3130 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3131 if (os::is_MP()) { masm.lock(); }
3132 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3133 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3134 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3135 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3136 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3137 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3138
3139 // If the CAS fails we can either retry or pass control to the slow-path.
3140 // We use the latter tactic.
3141 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3142 // If the CAS was successful ...
3143 // Self has acquired the lock
3144 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3145 // Intentional fall-through into DONE_LABEL ...
3146 } else {
3147 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3148 masm.movptr(boxReg, tmpReg) ;
3149
3150 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3151 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3152 // prefetchw [eax + Offset(_owner)-2]
3153 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3154 }
3155
3156 if ((EmitSync & 64) == 0) {
3157 // Optimistic form
3158 masm.xorptr (tmpReg, tmpReg) ;
3159 } else {
3160 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3161 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3162 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3163 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3164 }
3165
3166 // Appears unlocked - try to swing _owner from null to non-null.
3167 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3168 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3169 masm.get_thread (scrReg) ;
3170 if (os::is_MP()) { masm.lock(); }
3171 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3172
3173 // If the CAS fails we can either retry or pass control to the slow-path.
3174 // We use the latter tactic.
3175 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3176 // If the CAS was successful ...
3177 // Self has acquired the lock
3178 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3179 // Intentional fall-through into DONE_LABEL ...
3180 }
3181
3182 // DONE_LABEL is a hot target - we'd really like to place it at the
3183 // start of cache line by padding with NOPs.
3184 // See the AMD and Intel software optimization manuals for the
3185 // most efficient "long" NOP encodings.
3186 // Unfortunately none of our alignment mechanisms suffice.
3187 masm.bind(DONE_LABEL);
3188
3189 // Avoid branch-to-branch on AMD processors
3190 // This appears to be superstition.
3191 if (EmitSync & 32) masm.nop() ;
3192
3193
3194 // At DONE_LABEL the icc ZFlag is set as follows ...
3195 // Fast_Unlock uses the same protocol.
3196 // ZFlag == 1 -> Success
3197 // ZFlag == 0 -> Failure - force control through the slow-path
3198 }
3199 %}
3200
3201 // obj: object to unlock
3202 // box: box address (displaced header location), killed. Must be EAX.
3203 // rbx,: killed tmp; cannot be obj nor box.
3204 //
3205 // Some commentary on balanced locking:
3206 //
3207 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3208 // Methods that don't have provably balanced locking are forced to run in the
3209 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3210 // The interpreter provides two properties:
3211 // I1: At return-time the interpreter automatically and quietly unlocks any
3212 // objects acquired the current activation (frame). Recall that the
3213 // interpreter maintains an on-stack list of locks currently held by
3214 // a frame.
3215 // I2: If a method attempts to unlock an object that is not held by the
3216 // the frame the interpreter throws IMSX.
3217 //
3218 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3219 // B() doesn't have provably balanced locking so it runs in the interpreter.
3220 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3221 // is still locked by A().
3222 //
3223 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3224 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3225 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3226 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3227
3228 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3229
3230 Register objReg = as_Register($obj$$reg);
3231 Register boxReg = as_Register($box$$reg);
3232 Register tmpReg = as_Register($tmp$$reg);
3233
3234 guarantee (objReg != boxReg, "") ;
3235 guarantee (objReg != tmpReg, "") ;
3236 guarantee (boxReg != tmpReg, "") ;
3237 guarantee (boxReg == as_Register(EAX_enc), "") ;
3238 MacroAssembler masm(&cbuf);
3239
3240 if (EmitSync & 4) {
3241 // Disable - inhibit all inlining. Force control through the slow-path
3242 masm.cmpptr (rsp, 0) ;
3243 } else
3244 if (EmitSync & 8) {
3245 Label DONE_LABEL ;
3246 if (UseBiasedLocking) {
3247 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3248 }
3249 // classic stack-locking code ...
3250 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3251 masm.testptr(tmpReg, tmpReg) ;
3252 masm.jcc (Assembler::zero, DONE_LABEL) ;
3253 if (os::is_MP()) { masm.lock(); }
3254 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3255 masm.bind(DONE_LABEL);
3256 } else {
3257 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3258
3259 // Critically, the biased locking test must have precedence over
3260 // and appear before the (box->dhw == 0) recursive stack-lock test.
3261 if (UseBiasedLocking && !UseOptoBiasInlining) {
3262 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3263 }
3264
3265 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3266 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3267 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3268
3269 masm.testptr(tmpReg, 0x02) ; // Inflated?
3270 masm.jccb (Assembler::zero, Stacked) ;
3271
3272 masm.bind (Inflated) ;
3273 // It's inflated.
3274 // Despite our balanced locking property we still check that m->_owner == Self
3275 // as java routines or native JNI code called by this thread might
3276 // have released the lock.
3277 // Refer to the comments in synchronizer.cpp for how we might encode extra
3278 // state in _succ so we can avoid fetching EntryList|cxq.
3279 //
3280 // I'd like to add more cases in fast_lock() and fast_unlock() --
3281 // such as recursive enter and exit -- but we have to be wary of
3282 // I$ bloat, T$ effects and BP$ effects.
3283 //
3284 // If there's no contention try a 1-0 exit. That is, exit without
3285 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3286 // we detect and recover from the race that the 1-0 exit admits.
3287 //
3288 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3289 // before it STs null into _owner, releasing the lock. Updates
3290 // to data protected by the critical section must be visible before
3291 // we drop the lock (and thus before any other thread could acquire
3292 // the lock and observe the fields protected by the lock).
3293 // IA32's memory-model is SPO, so STs are ordered with respect to
3294 // each other and there's no need for an explicit barrier (fence).
3295 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3296
3297 masm.get_thread (boxReg) ;
3298 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3299 // prefetchw [ebx + Offset(_owner)-2]
3300 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3301 }
3302
3303 // Note that we could employ various encoding schemes to reduce
3304 // the number of loads below (currently 4) to just 2 or 3.
3305 // Refer to the comments in synchronizer.cpp.
3306 // In practice the chain of fetches doesn't seem to impact performance, however.
3307 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3308 // Attempt to reduce branch density - AMD's branch predictor.
3309 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3310 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3311 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3312 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3313 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3314 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3315 masm.jmpb (DONE_LABEL) ;
3316 } else {
3317 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3318 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3319 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3320 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3321 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3322 masm.jccb (Assembler::notZero, CheckSucc) ;
3323 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3324 masm.jmpb (DONE_LABEL) ;
3325 }
3326
3327 // The Following code fragment (EmitSync & 65536) improves the performance of
3328 // contended applications and contended synchronization microbenchmarks.
3329 // Unfortunately the emission of the code - even though not executed - causes regressions
3330 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3331 // with an equal number of never-executed NOPs results in the same regression.
3332 // We leave it off by default.
3333
3334 if ((EmitSync & 65536) != 0) {
3335 Label LSuccess, LGoSlowPath ;
3336
3337 masm.bind (CheckSucc) ;
3338
3339 // Optional pre-test ... it's safe to elide this
3340 if ((EmitSync & 16) == 0) {
3341 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3342 masm.jccb (Assembler::zero, LGoSlowPath) ;
3343 }
3344
3345 // We have a classic Dekker-style idiom:
3346 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3347 // There are a number of ways to implement the barrier:
3348 // (1) lock:andl &m->_owner, 0
3349 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3350 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3351 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3352 // (2) If supported, an explicit MFENCE is appealing.
3353 // In older IA32 processors MFENCE is slower than lock:add or xchg
3354 // particularly if the write-buffer is full as might be the case if
3355 // if stores closely precede the fence or fence-equivalent instruction.
3356 // In more modern implementations MFENCE appears faster, however.
3357 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3358 // The $lines underlying the top-of-stack should be in M-state.
3359 // The locked add instruction is serializing, of course.
3360 // (4) Use xchg, which is serializing
3361 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3362 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3363 // The integer condition codes will tell us if succ was 0.
3364 // Since _succ and _owner should reside in the same $line and
3365 // we just stored into _owner, it's likely that the $line
3366 // remains in M-state for the lock:orl.
3367 //
3368 // We currently use (3), although it's likely that switching to (2)
3369 // is correct for the future.
3370
3371 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3372 if (os::is_MP()) {
3373 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3374 masm.mfence();
3375 } else {
3376 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3377 }
3378 }
3379 // Ratify _succ remains non-null
3380 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3381 masm.jccb (Assembler::notZero, LSuccess) ;
3382
3383 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3384 if (os::is_MP()) { masm.lock(); }
3385 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3386 masm.jccb (Assembler::notEqual, LSuccess) ;
3387 // Since we're low on registers we installed rsp as a placeholding in _owner.
3388 // Now install Self over rsp. This is safe as we're transitioning from
3389 // non-null to non=null
3390 masm.get_thread (boxReg) ;
3391 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3392 // Intentional fall-through into LGoSlowPath ...
3393
3394 masm.bind (LGoSlowPath) ;
3395 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3396 masm.jmpb (DONE_LABEL) ;
3397
3398 masm.bind (LSuccess) ;
3399 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3400 masm.jmpb (DONE_LABEL) ;
3401 }
3402
3403 masm.bind (Stacked) ;
3404 // It's not inflated and it's not recursively stack-locked and it's not biased.
3405 // It must be stack-locked.
3406 // Try to reset the header to displaced header.
3407 // The "box" value on the stack is stable, so we can reload
3408 // and be assured we observe the same value as above.
3409 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3410 if (os::is_MP()) { masm.lock(); }
3411 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3412 // Intention fall-thru into DONE_LABEL
3413
3414
3415 // DONE_LABEL is a hot target - we'd really like to place it at the
3416 // start of cache line by padding with NOPs.
3417 // See the AMD and Intel software optimization manuals for the
3418 // most efficient "long" NOP encodings.
3419 // Unfortunately none of our alignment mechanisms suffice.
3420 if ((EmitSync & 65536) == 0) {
3421 masm.bind (CheckSucc) ;
3422 }
3423 masm.bind(DONE_LABEL);
3424
3425 // Avoid branch to branch on AMD processors
3426 if (EmitSync & 32768) { masm.nop() ; }
3427 }
3428 %}
3429
3430
3431 enc_class enc_pop_rdx() %{
3432 emit_opcode(cbuf,0x5A);
3433 %}
3434
3435 enc_class enc_rethrow() %{
3436 cbuf.set_insts_mark();
3437 emit_opcode(cbuf, 0xE9); // jmp entry
3438 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3439 runtime_call_Relocation::spec(), RELOC_IMM32 );
3440 %}
3441
3442
3443 // Convert a double to an int. Java semantics require we do complex
3444 // manglelations in the corner cases. So we set the rounding mode to
3445 // 'zero', store the darned double down as an int, and reset the
3446 // rounding mode to 'nearest'. The hardware throws an exception which
3447 // patches up the correct value directly to the stack.
3448 enc_class DPR2I_encoding( regDPR src ) %{
3449 // Flip to round-to-zero mode. We attempted to allow invalid-op
3450 // exceptions here, so that a NAN or other corner-case value will
3451 // thrown an exception (but normal values get converted at full speed).
3452 // However, I2C adapters and other float-stack manglers leave pending
3453 // invalid-op exceptions hanging. We would have to clear them before
3454 // enabling them and that is more expensive than just testing for the
3455 // invalid value Intel stores down in the corner cases.
3456 emit_opcode(cbuf,0xD9); // FLDCW trunc
3457 emit_opcode(cbuf,0x2D);
3458 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3459 // Allocate a word
3460 emit_opcode(cbuf,0x83); // SUB ESP,4
3461 emit_opcode(cbuf,0xEC);
3462 emit_d8(cbuf,0x04);
3463 // Encoding assumes a double has been pushed into FPR0.
3464 // Store down the double as an int, popping the FPU stack
3465 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3466 emit_opcode(cbuf,0x1C);
3467 emit_d8(cbuf,0x24);
3468 // Restore the rounding mode; mask the exception
3469 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3470 emit_opcode(cbuf,0x2D);
3471 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3472 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3473 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3474
3475 // Load the converted int; adjust CPU stack
3476 emit_opcode(cbuf,0x58); // POP EAX
3477 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3478 emit_d32 (cbuf,0x80000000); // 0x80000000
3479 emit_opcode(cbuf,0x75); // JNE around_slow_call
3480 emit_d8 (cbuf,0x07); // Size of slow_call
3481 // Push src onto stack slow-path
3482 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3483 emit_d8 (cbuf,0xC0-1+$src$$reg );
3484 // CALL directly to the runtime
3485 cbuf.set_insts_mark();
3486 emit_opcode(cbuf,0xE8); // Call into runtime
3487 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3488 // Carry on here...
3489 %}
3490
3491 enc_class DPR2L_encoding( regDPR src ) %{
3492 emit_opcode(cbuf,0xD9); // FLDCW trunc
3493 emit_opcode(cbuf,0x2D);
3494 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3495 // Allocate a word
3496 emit_opcode(cbuf,0x83); // SUB ESP,8
3497 emit_opcode(cbuf,0xEC);
3498 emit_d8(cbuf,0x08);
3499 // Encoding assumes a double has been pushed into FPR0.
3500 // Store down the double as a long, popping the FPU stack
3501 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3502 emit_opcode(cbuf,0x3C);
3503 emit_d8(cbuf,0x24);
3504 // Restore the rounding mode; mask the exception
3505 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3506 emit_opcode(cbuf,0x2D);
3507 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3508 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3509 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3510
3511 // Load the converted int; adjust CPU stack
3512 emit_opcode(cbuf,0x58); // POP EAX
3513 emit_opcode(cbuf,0x5A); // POP EDX
3514 emit_opcode(cbuf,0x81); // CMP EDX,imm
3515 emit_d8 (cbuf,0xFA); // rdx
3516 emit_d32 (cbuf,0x80000000); // 0x80000000
3517 emit_opcode(cbuf,0x75); // JNE around_slow_call
3518 emit_d8 (cbuf,0x07+4); // Size of slow_call
3519 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3520 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3521 emit_opcode(cbuf,0x75); // JNE around_slow_call
3522 emit_d8 (cbuf,0x07); // Size of slow_call
3523 // Push src onto stack slow-path
3524 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3525 emit_d8 (cbuf,0xC0-1+$src$$reg );
3526 // CALL directly to the runtime
3527 cbuf.set_insts_mark();
3528 emit_opcode(cbuf,0xE8); // Call into runtime
3529 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3530 // Carry on here...
3531 %}
3532
3533 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3534 // Operand was loaded from memory into fp ST (stack top)
3535 // FMUL ST,$src /* D8 C8+i */
3536 emit_opcode(cbuf, 0xD8);
3537 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3538 %}
3539
3540 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3541 // FADDP ST,src2 /* D8 C0+i */
3542 emit_opcode(cbuf, 0xD8);
3543 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3544 //could use FADDP src2,fpST /* DE C0+i */
3545 %}
3546
3547 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3548 // FADDP src2,ST /* DE C0+i */
3549 emit_opcode(cbuf, 0xDE);
3550 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3551 %}
3552
3553 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3554 // Operand has been loaded into fp ST (stack top)
3555 // FSUB ST,$src1
3556 emit_opcode(cbuf, 0xD8);
3557 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3558
3559 // FDIV
3560 emit_opcode(cbuf, 0xD8);
3561 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3562 %}
3563
3564 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3565 // Operand was loaded from memory into fp ST (stack top)
3566 // FADD ST,$src /* D8 C0+i */
3567 emit_opcode(cbuf, 0xD8);
3568 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3569
3570 // FMUL ST,src2 /* D8 C*+i */
3571 emit_opcode(cbuf, 0xD8);
3572 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3573 %}
3574
3575
3576 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3577 // Operand was loaded from memory into fp ST (stack top)
3578 // FADD ST,$src /* D8 C0+i */
3579 emit_opcode(cbuf, 0xD8);
3580 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3581
3582 // FMULP src2,ST /* DE C8+i */
3583 emit_opcode(cbuf, 0xDE);
3584 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3585 %}
3586
3587 // Atomically load the volatile long
3588 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3589 emit_opcode(cbuf,0xDF);
3590 int rm_byte_opcode = 0x05;
3591 int base = $mem$$base;
3592 int index = $mem$$index;
3593 int scale = $mem$$scale;
3594 int displace = $mem$$disp;
3595 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3596 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3597 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3598 %}
3599
3600 // Volatile Store Long. Must be atomic, so move it into
3601 // the FP TOS and then do a 64-bit FIST. Has to probe the
3602 // target address before the store (for null-ptr checks)
3603 // so the memory operand is used twice in the encoding.
3604 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3605 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3606 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3607 emit_opcode(cbuf,0xDF);
3608 int rm_byte_opcode = 0x07;
3609 int base = $mem$$base;
3610 int index = $mem$$index;
3611 int scale = $mem$$scale;
3612 int displace = $mem$$disp;
3613 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3615 %}
3616
3617 // Safepoint Poll. This polls the safepoint page, and causes an
3618 // exception if it is not readable. Unfortunately, it kills the condition code
3619 // in the process
3620 // We current use TESTL [spp],EDI
3621 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3622
3623 enc_class Safepoint_Poll() %{
3624 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3625 emit_opcode(cbuf,0x85);
3626 emit_rm (cbuf, 0x0, 0x7, 0x5);
3627 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3628 %}
3629 %}
3630
3631
3632 //----------FRAME--------------------------------------------------------------
3633 // Definition of frame structure and management information.
3634 //
3635 // S T A C K L A Y O U T Allocators stack-slot number
3636 // | (to get allocators register number
3637 // G Owned by | | v add OptoReg::stack0())
3638 // r CALLER | |
3639 // o | +--------+ pad to even-align allocators stack-slot
3640 // w V | pad0 | numbers; owned by CALLER
3641 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3642 // h ^ | in | 5
3643 // | | args | 4 Holes in incoming args owned by SELF
3644 // | | | | 3
3645 // | | +--------+
3646 // V | | old out| Empty on Intel, window on Sparc
3647 // | old |preserve| Must be even aligned.
3648 // | SP-+--------+----> Matcher::_old_SP, even aligned
3649 // | | in | 3 area for Intel ret address
3650 // Owned by |preserve| Empty on Sparc.
3651 // SELF +--------+
3652 // | | pad2 | 2 pad to align old SP
3653 // | +--------+ 1
3654 // | | locks | 0
3655 // | +--------+----> OptoReg::stack0(), even aligned
3656 // | | pad1 | 11 pad to align new SP
3657 // | +--------+
3658 // | | | 10
3659 // | | spills | 9 spills
3660 // V | | 8 (pad0 slot for callee)
3661 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3662 // ^ | out | 7
3663 // | | args | 6 Holes in outgoing args owned by CALLEE
3664 // Owned by +--------+
3665 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3666 // | new |preserve| Must be even-aligned.
3667 // | SP-+--------+----> Matcher::_new_SP, even aligned
3668 // | | |
3669 //
3670 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3671 // known from SELF's arguments and the Java calling convention.
3672 // Region 6-7 is determined per call site.
3673 // Note 2: If the calling convention leaves holes in the incoming argument
3674 // area, those holes are owned by SELF. Holes in the outgoing area
3675 // are owned by the CALLEE. Holes should not be nessecary in the
3676 // incoming area, as the Java calling convention is completely under
3677 // the control of the AD file. Doubles can be sorted and packed to
3678 // avoid holes. Holes in the outgoing arguments may be nessecary for
3679 // varargs C calling conventions.
3680 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3681 // even aligned with pad0 as needed.
3682 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3683 // region 6-11 is even aligned; it may be padded out more so that
3684 // the region from SP to FP meets the minimum stack alignment.
3685
3686 frame %{
3687 // What direction does stack grow in (assumed to be same for C & Java)
3688 stack_direction(TOWARDS_LOW);
3689
3690 // These three registers define part of the calling convention
3691 // between compiled code and the interpreter.
3692 inline_cache_reg(EAX); // Inline Cache Register
3693 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3694
3695 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3696 cisc_spilling_operand_name(indOffset32);
3697
3698 // Number of stack slots consumed by locking an object
3699 sync_stack_slots(1);
3700
3701 // Compiled code's Frame Pointer
3702 frame_pointer(ESP);
3703 // Interpreter stores its frame pointer in a register which is
3704 // stored to the stack by I2CAdaptors.
3705 // I2CAdaptors convert from interpreted java to compiled java.
3706 interpreter_frame_pointer(EBP);
3707
3708 // Stack alignment requirement
3709 // Alignment size in bytes (128-bit -> 16 bytes)
3710 stack_alignment(StackAlignmentInBytes);
3711
3712 // Number of stack slots between incoming argument block and the start of
3713 // a new frame. The PROLOG must add this many slots to the stack. The
3714 // EPILOG must remove this many slots. Intel needs one slot for
3715 // return address and one for rbp, (must save rbp)
3716 in_preserve_stack_slots(2+VerifyStackAtCalls);
3717
3718 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3719 // for calls to C. Supports the var-args backing area for register parms.
3720 varargs_C_out_slots_killed(0);
3721
3722 // The after-PROLOG location of the return address. Location of
3723 // return address specifies a type (REG or STACK) and a number
3724 // representing the register number (i.e. - use a register name) or
3725 // stack slot.
3726 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3727 // Otherwise, it is above the locks and verification slot and alignment word
3728 return_addr(STACK - 1 +
3729 round_to((Compile::current()->in_preserve_stack_slots() +
3730 Compile::current()->fixed_slots()),
3731 stack_alignment_in_slots()));
3732
3733 // Body of function which returns an integer array locating
3734 // arguments either in registers or in stack slots. Passed an array
3735 // of ideal registers called "sig" and a "length" count. Stack-slot
3736 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3737 // arguments for a CALLEE. Incoming stack arguments are
3738 // automatically biased by the preserve_stack_slots field above.
3739 calling_convention %{
3740 // No difference between ingoing/outgoing just pass false
3741 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3742 %}
3743
3744
3745 // Body of function which returns an integer array locating
3746 // arguments either in registers or in stack slots. Passed an array
3747 // of ideal registers called "sig" and a "length" count. Stack-slot
3748 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3749 // arguments for a CALLEE. Incoming stack arguments are
3750 // automatically biased by the preserve_stack_slots field above.
3751 c_calling_convention %{
3752 // This is obviously always outgoing
3753 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3754 %}
3755
3756 // Location of C & interpreter return values
3757 c_return_value %{
3758 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3759 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3760 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3761
3762 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3763 // that C functions return float and double results in XMM0.
3764 if( ideal_reg == Op_RegD && UseSSE>=2 )
3765 return OptoRegPair(XMM0b_num,XMM0a_num);
3766 if( ideal_reg == Op_RegF && UseSSE>=2 )
3767 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3768
3769 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3770 %}
3771
3772 // Location of return values
3773 return_value %{
3774 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3775 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3776 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3777 if( ideal_reg == Op_RegD && UseSSE>=2 )
3778 return OptoRegPair(XMM0b_num,XMM0a_num);
3779 if( ideal_reg == Op_RegF && UseSSE>=1 )
3780 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3781 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3782 %}
3783
3784 %}
3785
3786 //----------ATTRIBUTES---------------------------------------------------------
3787 //----------Operand Attributes-------------------------------------------------
3788 op_attrib op_cost(0); // Required cost attribute
3789
3790 //----------Instruction Attributes---------------------------------------------
3791 ins_attrib ins_cost(100); // Required cost attribute
3792 ins_attrib ins_size(8); // Required size attribute (in bits)
3793 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3794 // non-matching short branch variant of some
3795 // long branch?
3796 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3797 // specifies the alignment that some part of the instruction (not
3798 // necessarily the start) requires. If > 1, a compute_padding()
3799 // function must be provided for the instruction
3800
3801 //----------OPERANDS-----------------------------------------------------------
3802 // Operand definitions must precede instruction definitions for correct parsing
3803 // in the ADLC because operands constitute user defined types which are used in
3804 // instruction definitions.
3805
3806 //----------Simple Operands----------------------------------------------------
3807 // Immediate Operands
3808 // Integer Immediate
3809 operand immI() %{
3810 match(ConI);
3811
3812 op_cost(10);
3813 format %{ %}
3814 interface(CONST_INTER);
3815 %}
3816
3817 // Constant for test vs zero
3818 operand immI0() %{
3819 predicate(n->get_int() == 0);
3820 match(ConI);
3821
3822 op_cost(0);
3823 format %{ %}
3824 interface(CONST_INTER);
3825 %}
3826
3827 // Constant for increment
3828 operand immI1() %{
3829 predicate(n->get_int() == 1);
3830 match(ConI);
3831
3832 op_cost(0);
3833 format %{ %}
3834 interface(CONST_INTER);
3835 %}
3836
3837 // Constant for decrement
3838 operand immI_M1() %{
3839 predicate(n->get_int() == -1);
3840 match(ConI);
3841
3842 op_cost(0);
3843 format %{ %}
3844 interface(CONST_INTER);
3845 %}
3846
3847 // Valid scale values for addressing modes
3848 operand immI2() %{
3849 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3850 match(ConI);
3851
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3855
3856 operand immI8() %{
3857 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3858 match(ConI);
3859
3860 op_cost(5);
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3864
3865 operand immI16() %{
3866 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3867 match(ConI);
3868
3869 op_cost(10);
3870 format %{ %}
3871 interface(CONST_INTER);
3872 %}
3873
3874 // Constant for long shifts
3875 operand immI_32() %{
3876 predicate( n->get_int() == 32 );
3877 match(ConI);
3878
3879 op_cost(0);
3880 format %{ %}
3881 interface(CONST_INTER);
3882 %}
3883
3884 operand immI_1_31() %{
3885 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3886 match(ConI);
3887
3888 op_cost(0);
3889 format %{ %}
3890 interface(CONST_INTER);
3891 %}
3892
3893 operand immI_32_63() %{
3894 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3895 match(ConI);
3896 op_cost(0);
3897
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3901
3902 operand immI_1() %{
3903 predicate( n->get_int() == 1 );
3904 match(ConI);
3905
3906 op_cost(0);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3910
3911 operand immI_2() %{
3912 predicate( n->get_int() == 2 );
3913 match(ConI);
3914
3915 op_cost(0);
3916 format %{ %}
3917 interface(CONST_INTER);
3918 %}
3919
3920 operand immI_3() %{
3921 predicate( n->get_int() == 3 );
3922 match(ConI);
3923
3924 op_cost(0);
3925 format %{ %}
3926 interface(CONST_INTER);
3927 %}
3928
3929 // Pointer Immediate
3930 operand immP() %{
3931 match(ConP);
3932
3933 op_cost(10);
3934 format %{ %}
3935 interface(CONST_INTER);
3936 %}
3937
3938 // NULL Pointer Immediate
3939 operand immP0() %{
3940 predicate( n->get_ptr() == 0 );
3941 match(ConP);
3942 op_cost(0);
3943
3944 format %{ %}
3945 interface(CONST_INTER);
3946 %}
3947
3948 // Long Immediate
3949 operand immL() %{
3950 match(ConL);
3951
3952 op_cost(20);
3953 format %{ %}
3954 interface(CONST_INTER);
3955 %}
3956
3957 // Long Immediate zero
3958 operand immL0() %{
3959 predicate( n->get_long() == 0L );
3960 match(ConL);
3961 op_cost(0);
3962
3963 format %{ %}
3964 interface(CONST_INTER);
3965 %}
3966
3967 // Long Immediate zero
3968 operand immL_M1() %{
3969 predicate( n->get_long() == -1L );
3970 match(ConL);
3971 op_cost(0);
3972
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3976
3977 // Long immediate from 0 to 127.
3978 // Used for a shorter form of long mul by 10.
3979 operand immL_127() %{
3980 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3981 match(ConL);
3982 op_cost(0);
3983
3984 format %{ %}
3985 interface(CONST_INTER);
3986 %}
3987
3988 // Long Immediate: low 32-bit mask
3989 operand immL_32bits() %{
3990 predicate(n->get_long() == 0xFFFFFFFFL);
3991 match(ConL);
3992 op_cost(0);
3993
3994 format %{ %}
3995 interface(CONST_INTER);
3996 %}
3997
3998 // Long Immediate: low 32-bit mask
3999 operand immL32() %{
4000 predicate(n->get_long() == (int)(n->get_long()));
4001 match(ConL);
4002 op_cost(20);
4003
4004 format %{ %}
4005 interface(CONST_INTER);
4006 %}
4007
4008 //Double Immediate zero
4009 operand immDPR0() %{
4010 // Do additional (and counter-intuitive) test against NaN to work around VC++
4011 // bug that generates code such that NaNs compare equal to 0.0
4012 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4013 match(ConD);
4014
4015 op_cost(5);
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4019
4020 // Double Immediate one
4021 operand immDPR1() %{
4022 predicate( UseSSE<=1 && n->getd() == 1.0 );
4023 match(ConD);
4024
4025 op_cost(5);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4029
4030 // Double Immediate
4031 operand immDPR() %{
4032 predicate(UseSSE<=1);
4033 match(ConD);
4034
4035 op_cost(5);
4036 format %{ %}
4037 interface(CONST_INTER);
4038 %}
4039
4040 operand immD() %{
4041 predicate(UseSSE>=2);
4042 match(ConD);
4043
4044 op_cost(5);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 // Double Immediate zero
4050 operand immD0() %{
4051 // Do additional (and counter-intuitive) test against NaN to work around VC++
4052 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4053 // compare equal to -0.0.
4054 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4055 match(ConD);
4056
4057 format %{ %}
4058 interface(CONST_INTER);
4059 %}
4060
4061 // Float Immediate zero
4062 operand immFPR0() %{
4063 predicate(UseSSE == 0 && n->getf() == 0.0F);
4064 match(ConF);
4065
4066 op_cost(5);
4067 format %{ %}
4068 interface(CONST_INTER);
4069 %}
4070
4071 // Float Immediate one
4072 operand immFPR1() %{
4073 predicate(UseSSE == 0 && n->getf() == 1.0F);
4074 match(ConF);
4075
4076 op_cost(5);
4077 format %{ %}
4078 interface(CONST_INTER);
4079 %}
4080
4081 // Float Immediate
4082 operand immFPR() %{
4083 predicate( UseSSE == 0 );
4084 match(ConF);
4085
4086 op_cost(5);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4090
4091 // Float Immediate
4092 operand immF() %{
4093 predicate(UseSSE >= 1);
4094 match(ConF);
4095
4096 op_cost(5);
4097 format %{ %}
4098 interface(CONST_INTER);
4099 %}
4100
4101 // Float Immediate zero. Zero and not -0.0
4102 operand immF0() %{
4103 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4104 match(ConF);
4105
4106 op_cost(5);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4110
4111 // Immediates for special shifts (sign extend)
4112
4113 // Constants for increment
4114 operand immI_16() %{
4115 predicate( n->get_int() == 16 );
4116 match(ConI);
4117
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4121
4122 operand immI_24() %{
4123 predicate( n->get_int() == 24 );
4124 match(ConI);
4125
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 // Constant for byte-wide masking
4131 operand immI_255() %{
4132 predicate( n->get_int() == 255 );
4133 match(ConI);
4134
4135 format %{ %}
4136 interface(CONST_INTER);
4137 %}
4138
4139 // Constant for short-wide masking
4140 operand immI_65535() %{
4141 predicate(n->get_int() == 65535);
4142 match(ConI);
4143
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4147
4148 // Register Operands
4149 // Integer Register
4150 operand eRegI() %{
4151 constraint(ALLOC_IN_RC(e_reg));
4152 match(RegI);
4153 match(xRegI);
4154 match(eAXRegI);
4155 match(eBXRegI);
4156 match(eCXRegI);
4157 match(eDXRegI);
4158 match(eDIRegI);
4159 match(eSIRegI);
4160
4161 format %{ %}
4162 interface(REG_INTER);
4163 %}
4164
4165 // Subset of Integer Register
4166 operand xRegI(eRegI reg) %{
4167 constraint(ALLOC_IN_RC(x_reg));
4168 match(reg);
4169 match(eAXRegI);
4170 match(eBXRegI);
4171 match(eCXRegI);
4172 match(eDXRegI);
4173
4174 format %{ %}
4175 interface(REG_INTER);
4176 %}
4177
4178 // Special Registers
4179 operand eAXRegI(xRegI reg) %{
4180 constraint(ALLOC_IN_RC(eax_reg));
4181 match(reg);
4182 match(eRegI);
4183
4184 format %{ "EAX" %}
4185 interface(REG_INTER);
4186 %}
4187
4188 // Special Registers
4189 operand eBXRegI(xRegI reg) %{
4190 constraint(ALLOC_IN_RC(ebx_reg));
4191 match(reg);
4192 match(eRegI);
4193
4194 format %{ "EBX" %}
4195 interface(REG_INTER);
4196 %}
4197
4198 operand eCXRegI(xRegI reg) %{
4199 constraint(ALLOC_IN_RC(ecx_reg));
4200 match(reg);
4201 match(eRegI);
4202
4203 format %{ "ECX" %}
4204 interface(REG_INTER);
4205 %}
4206
4207 operand eDXRegI(xRegI reg) %{
4208 constraint(ALLOC_IN_RC(edx_reg));
4209 match(reg);
4210 match(eRegI);
4211
4212 format %{ "EDX" %}
4213 interface(REG_INTER);
4214 %}
4215
4216 operand eDIRegI(xRegI reg) %{
4217 constraint(ALLOC_IN_RC(edi_reg));
4218 match(reg);
4219 match(eRegI);
4220
4221 format %{ "EDI" %}
4222 interface(REG_INTER);
4223 %}
4224
4225 operand naxRegI() %{
4226 constraint(ALLOC_IN_RC(nax_reg));
4227 match(RegI);
4228 match(eCXRegI);
4229 match(eDXRegI);
4230 match(eSIRegI);
4231 match(eDIRegI);
4232
4233 format %{ %}
4234 interface(REG_INTER);
4235 %}
4236
4237 operand nadxRegI() %{
4238 constraint(ALLOC_IN_RC(nadx_reg));
4239 match(RegI);
4240 match(eBXRegI);
4241 match(eCXRegI);
4242 match(eSIRegI);
4243 match(eDIRegI);
4244
4245 format %{ %}
4246 interface(REG_INTER);
4247 %}
4248
4249 operand ncxRegI() %{
4250 constraint(ALLOC_IN_RC(ncx_reg));
4251 match(RegI);
4252 match(eAXRegI);
4253 match(eDXRegI);
4254 match(eSIRegI);
4255 match(eDIRegI);
4256
4257 format %{ %}
4258 interface(REG_INTER);
4259 %}
4260
4261 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4262 // //
4263 operand eSIRegI(xRegI reg) %{
4264 constraint(ALLOC_IN_RC(esi_reg));
4265 match(reg);
4266 match(eRegI);
4267
4268 format %{ "ESI" %}
4269 interface(REG_INTER);
4270 %}
4271
4272 // Pointer Register
4273 operand anyRegP() %{
4274 constraint(ALLOC_IN_RC(any_reg));
4275 match(RegP);
4276 match(eAXRegP);
4277 match(eBXRegP);
4278 match(eCXRegP);
4279 match(eDIRegP);
4280 match(eRegP);
4281
4282 format %{ %}
4283 interface(REG_INTER);
4284 %}
4285
4286 operand eRegP() %{
4287 constraint(ALLOC_IN_RC(e_reg));
4288 match(RegP);
4289 match(eAXRegP);
4290 match(eBXRegP);
4291 match(eCXRegP);
4292 match(eDIRegP);
4293
4294 format %{ %}
4295 interface(REG_INTER);
4296 %}
4297
4298 // On windows95, EBP is not safe to use for implicit null tests.
4299 operand eRegP_no_EBP() %{
4300 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4301 match(RegP);
4302 match(eAXRegP);
4303 match(eBXRegP);
4304 match(eCXRegP);
4305 match(eDIRegP);
4306
4307 op_cost(100);
4308 format %{ %}
4309 interface(REG_INTER);
4310 %}
4311
4312 operand naxRegP() %{
4313 constraint(ALLOC_IN_RC(nax_reg));
4314 match(RegP);
4315 match(eBXRegP);
4316 match(eDXRegP);
4317 match(eCXRegP);
4318 match(eSIRegP);
4319 match(eDIRegP);
4320
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4324
4325 operand nabxRegP() %{
4326 constraint(ALLOC_IN_RC(nabx_reg));
4327 match(RegP);
4328 match(eCXRegP);
4329 match(eDXRegP);
4330 match(eSIRegP);
4331 match(eDIRegP);
4332
4333 format %{ %}
4334 interface(REG_INTER);
4335 %}
4336
4337 operand pRegP() %{
4338 constraint(ALLOC_IN_RC(p_reg));
4339 match(RegP);
4340 match(eBXRegP);
4341 match(eDXRegP);
4342 match(eSIRegP);
4343 match(eDIRegP);
4344
4345 format %{ %}
4346 interface(REG_INTER);
4347 %}
4348
4349 // Special Registers
4350 // Return a pointer value
4351 operand eAXRegP(eRegP reg) %{
4352 constraint(ALLOC_IN_RC(eax_reg));
4353 match(reg);
4354 format %{ "EAX" %}
4355 interface(REG_INTER);
4356 %}
4357
4358 // Used in AtomicAdd
4359 operand eBXRegP(eRegP reg) %{
4360 constraint(ALLOC_IN_RC(ebx_reg));
4361 match(reg);
4362 format %{ "EBX" %}
4363 interface(REG_INTER);
4364 %}
4365
4366 // Tail-call (interprocedural jump) to interpreter
4367 operand eCXRegP(eRegP reg) %{
4368 constraint(ALLOC_IN_RC(ecx_reg));
4369 match(reg);
4370 format %{ "ECX" %}
4371 interface(REG_INTER);
4372 %}
4373
4374 operand eSIRegP(eRegP reg) %{
4375 constraint(ALLOC_IN_RC(esi_reg));
4376 match(reg);
4377 format %{ "ESI" %}
4378 interface(REG_INTER);
4379 %}
4380
4381 // Used in rep stosw
4382 operand eDIRegP(eRegP reg) %{
4383 constraint(ALLOC_IN_RC(edi_reg));
4384 match(reg);
4385 format %{ "EDI" %}
4386 interface(REG_INTER);
4387 %}
4388
4389 operand eBPRegP() %{
4390 constraint(ALLOC_IN_RC(ebp_reg));
4391 match(RegP);
4392 format %{ "EBP" %}
4393 interface(REG_INTER);
4394 %}
4395
4396 operand eRegL() %{
4397 constraint(ALLOC_IN_RC(long_reg));
4398 match(RegL);
4399 match(eADXRegL);
4400
4401 format %{ %}
4402 interface(REG_INTER);
4403 %}
4404
4405 operand eADXRegL( eRegL reg ) %{
4406 constraint(ALLOC_IN_RC(eadx_reg));
4407 match(reg);
4408
4409 format %{ "EDX:EAX" %}
4410 interface(REG_INTER);
4411 %}
4412
4413 operand eBCXRegL( eRegL reg ) %{
4414 constraint(ALLOC_IN_RC(ebcx_reg));
4415 match(reg);
4416
4417 format %{ "EBX:ECX" %}
4418 interface(REG_INTER);
4419 %}
4420
4421 // Special case for integer high multiply
4422 operand eADXRegL_low_only() %{
4423 constraint(ALLOC_IN_RC(eadx_reg));
4424 match(RegL);
4425
4426 format %{ "EAX" %}
4427 interface(REG_INTER);
4428 %}
4429
4430 // Flags register, used as output of compare instructions
4431 operand eFlagsReg() %{
4432 constraint(ALLOC_IN_RC(int_flags));
4433 match(RegFlags);
4434
4435 format %{ "EFLAGS" %}
4436 interface(REG_INTER);
4437 %}
4438
4439 // Flags register, used as output of FLOATING POINT compare instructions
4440 operand eFlagsRegU() %{
4441 constraint(ALLOC_IN_RC(int_flags));
4442 match(RegFlags);
4443
4444 format %{ "EFLAGS_U" %}
4445 interface(REG_INTER);
4446 %}
4447
4448 operand eFlagsRegUCF() %{
4449 constraint(ALLOC_IN_RC(int_flags));
4450 match(RegFlags);
4451 predicate(false);
4452
4453 format %{ "EFLAGS_U_CF" %}
4454 interface(REG_INTER);
4455 %}
4456
4457 // Condition Code Register used by long compare
4458 operand flagsReg_long_LTGE() %{
4459 constraint(ALLOC_IN_RC(int_flags));
4460 match(RegFlags);
4461 format %{ "FLAGS_LTGE" %}
4462 interface(REG_INTER);
4463 %}
4464 operand flagsReg_long_EQNE() %{
4465 constraint(ALLOC_IN_RC(int_flags));
4466 match(RegFlags);
4467 format %{ "FLAGS_EQNE" %}
4468 interface(REG_INTER);
4469 %}
4470 operand flagsReg_long_LEGT() %{
4471 constraint(ALLOC_IN_RC(int_flags));
4472 match(RegFlags);
4473 format %{ "FLAGS_LEGT" %}
4474 interface(REG_INTER);
4475 %}
4476
4477 // Float register operands
4478 operand regDPR() %{
4479 predicate( UseSSE < 2 );
4480 constraint(ALLOC_IN_RC(dbl_reg));
4481 match(RegD);
4482 match(regDPR1);
4483 match(regDPR2);
4484 format %{ %}
4485 interface(REG_INTER);
4486 %}
4487
4488 operand regDPR1(regDPR reg) %{
4489 predicate( UseSSE < 2 );
4490 constraint(ALLOC_IN_RC(dbl_reg0));
4491 match(reg);
4492 format %{ "FPR1" %}
4493 interface(REG_INTER);
4494 %}
4495
4496 operand regDPR2(regDPR reg) %{
4497 predicate( UseSSE < 2 );
4498 constraint(ALLOC_IN_RC(dbl_reg1));
4499 match(reg);
4500 format %{ "FPR2" %}
4501 interface(REG_INTER);
4502 %}
4503
4504 operand regnotDPR1(regDPR reg) %{
4505 predicate( UseSSE < 2 );
4506 constraint(ALLOC_IN_RC(dbl_notreg0));
4507 match(reg);
4508 format %{ %}
4509 interface(REG_INTER);
4510 %}
4511
4512 // XMM Double register operands
4513 operand regD() %{
4514 predicate( UseSSE>=2 );
4515 constraint(ALLOC_IN_RC(xdb_reg));
4516 match(RegD);
4517 match(regD6);
4518 match(regD7);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4522
4523 // XMM6 double register operands
4524 operand regD6(regD reg) %{
4525 predicate( UseSSE>=2 );
4526 constraint(ALLOC_IN_RC(xdb_reg6));
4527 match(reg);
4528 format %{ "XMM6" %}
4529 interface(REG_INTER);
4530 %}
4531
4532 // XMM7 double register operands
4533 operand regD7(regD reg) %{
4534 predicate( UseSSE>=2 );
4535 constraint(ALLOC_IN_RC(xdb_reg7));
4536 match(reg);
4537 format %{ "XMM7" %}
4538 interface(REG_INTER);
4539 %}
4540
4541 // Float register operands
4542 operand regFPR() %{
4543 predicate( UseSSE < 2 );
4544 constraint(ALLOC_IN_RC(flt_reg));
4545 match(RegF);
4546 match(regFPR1);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4550
4551 // Float register operands
4552 operand regFPR1(regFPR reg) %{
4553 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(flt_reg0));
4555 match(reg);
4556 format %{ "FPR1" %}
4557 interface(REG_INTER);
4558 %}
4559
4560 // XMM register operands
4561 operand regF() %{
4562 predicate( UseSSE>=1 );
4563 constraint(ALLOC_IN_RC(xmm_reg));
4564 match(RegF);
4565 format %{ %}
4566 interface(REG_INTER);
4567 %}
4568
4569
4570 //----------Memory Operands----------------------------------------------------
4571 // Direct Memory Operand
4572 operand direct(immP addr) %{
4573 match(addr);
4574
4575 format %{ "[$addr]" %}
4576 interface(MEMORY_INTER) %{
4577 base(0xFFFFFFFF);
4578 index(0x4);
4579 scale(0x0);
4580 disp($addr);
4581 %}
4582 %}
4583
4584 // Indirect Memory Operand
4585 operand indirect(eRegP reg) %{
4586 constraint(ALLOC_IN_RC(e_reg));
4587 match(reg);
4588
4589 format %{ "[$reg]" %}
4590 interface(MEMORY_INTER) %{
4591 base($reg);
4592 index(0x4);
4593 scale(0x0);
4594 disp(0x0);
4595 %}
4596 %}
4597
4598 // Indirect Memory Plus Short Offset Operand
4599 operand indOffset8(eRegP reg, immI8 off) %{
4600 match(AddP reg off);
4601
4602 format %{ "[$reg + $off]" %}
4603 interface(MEMORY_INTER) %{
4604 base($reg);
4605 index(0x4);
4606 scale(0x0);
4607 disp($off);
4608 %}
4609 %}
4610
4611 // Indirect Memory Plus Long Offset Operand
4612 operand indOffset32(eRegP reg, immI off) %{
4613 match(AddP reg off);
4614
4615 format %{ "[$reg + $off]" %}
4616 interface(MEMORY_INTER) %{
4617 base($reg);
4618 index(0x4);
4619 scale(0x0);
4620 disp($off);
4621 %}
4622 %}
4623
4624 // Indirect Memory Plus Long Offset Operand
4625 operand indOffset32X(eRegI reg, immP off) %{
4626 match(AddP off reg);
4627
4628 format %{ "[$reg + $off]" %}
4629 interface(MEMORY_INTER) %{
4630 base($reg);
4631 index(0x4);
4632 scale(0x0);
4633 disp($off);
4634 %}
4635 %}
4636
4637 // Indirect Memory Plus Index Register Plus Offset Operand
4638 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
4639 match(AddP (AddP reg ireg) off);
4640
4641 op_cost(10);
4642 format %{"[$reg + $off + $ireg]" %}
4643 interface(MEMORY_INTER) %{
4644 base($reg);
4645 index($ireg);
4646 scale(0x0);
4647 disp($off);
4648 %}
4649 %}
4650
4651 // Indirect Memory Plus Index Register Plus Offset Operand
4652 operand indIndex(eRegP reg, eRegI ireg) %{
4653 match(AddP reg ireg);
4654
4655 op_cost(10);
4656 format %{"[$reg + $ireg]" %}
4657 interface(MEMORY_INTER) %{
4658 base($reg);
4659 index($ireg);
4660 scale(0x0);
4661 disp(0x0);
4662 %}
4663 %}
4664
4665 // // -------------------------------------------------------------------------
4666 // // 486 architecture doesn't support "scale * index + offset" with out a base
4667 // // -------------------------------------------------------------------------
4668 // // Scaled Memory Operands
4669 // // Indirect Memory Times Scale Plus Offset Operand
4670 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
4671 // match(AddP off (LShiftI ireg scale));
4672 //
4673 // op_cost(10);
4674 // format %{"[$off + $ireg << $scale]" %}
4675 // interface(MEMORY_INTER) %{
4676 // base(0x4);
4677 // index($ireg);
4678 // scale($scale);
4679 // disp($off);
4680 // %}
4681 // %}
4682
4683 // Indirect Memory Times Scale Plus Index Register
4684 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
4685 match(AddP reg (LShiftI ireg scale));
4686
4687 op_cost(10);
4688 format %{"[$reg + $ireg << $scale]" %}
4689 interface(MEMORY_INTER) %{
4690 base($reg);
4691 index($ireg);
4692 scale($scale);
4693 disp(0x0);
4694 %}
4695 %}
4696
4697 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4698 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
4699 match(AddP (AddP reg (LShiftI ireg scale)) off);
4700
4701 op_cost(10);
4702 format %{"[$reg + $off + $ireg << $scale]" %}
4703 interface(MEMORY_INTER) %{
4704 base($reg);
4705 index($ireg);
4706 scale($scale);
4707 disp($off);
4708 %}
4709 %}
4710
4711 //----------Load Long Memory Operands------------------------------------------
4712 // The load-long idiom will use it's address expression again after loading
4713 // the first word of the long. If the load-long destination overlaps with
4714 // registers used in the addressing expression, the 2nd half will be loaded
4715 // from a clobbered address. Fix this by requiring that load-long use
4716 // address registers that do not overlap with the load-long target.
4717
4718 // load-long support
4719 operand load_long_RegP() %{
4720 constraint(ALLOC_IN_RC(esi_reg));
4721 match(RegP);
4722 match(eSIRegP);
4723 op_cost(100);
4724 format %{ %}
4725 interface(REG_INTER);
4726 %}
4727
4728 // Indirect Memory Operand Long
4729 operand load_long_indirect(load_long_RegP reg) %{
4730 constraint(ALLOC_IN_RC(esi_reg));
4731 match(reg);
4732
4733 format %{ "[$reg]" %}
4734 interface(MEMORY_INTER) %{
4735 base($reg);
4736 index(0x4);
4737 scale(0x0);
4738 disp(0x0);
4739 %}
4740 %}
4741
4742 // Indirect Memory Plus Long Offset Operand
4743 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4744 match(AddP reg off);
4745
4746 format %{ "[$reg + $off]" %}
4747 interface(MEMORY_INTER) %{
4748 base($reg);
4749 index(0x4);
4750 scale(0x0);
4751 disp($off);
4752 %}
4753 %}
4754
4755 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4756
4757
4758 //----------Special Memory Operands--------------------------------------------
4759 // Stack Slot Operand - This operand is used for loading and storing temporary
4760 // values on the stack where a match requires a value to
4761 // flow through memory.
4762 operand stackSlotP(sRegP reg) %{
4763 constraint(ALLOC_IN_RC(stack_slots));
4764 // No match rule because this operand is only generated in matching
4765 format %{ "[$reg]" %}
4766 interface(MEMORY_INTER) %{
4767 base(0x4); // ESP
4768 index(0x4); // No Index
4769 scale(0x0); // No Scale
4770 disp($reg); // Stack Offset
4771 %}
4772 %}
4773
4774 operand stackSlotI(sRegI reg) %{
4775 constraint(ALLOC_IN_RC(stack_slots));
4776 // No match rule because this operand is only generated in matching
4777 format %{ "[$reg]" %}
4778 interface(MEMORY_INTER) %{
4779 base(0x4); // ESP
4780 index(0x4); // No Index
4781 scale(0x0); // No Scale
4782 disp($reg); // Stack Offset
4783 %}
4784 %}
4785
4786 operand stackSlotF(sRegF reg) %{
4787 constraint(ALLOC_IN_RC(stack_slots));
4788 // No match rule because this operand is only generated in matching
4789 format %{ "[$reg]" %}
4790 interface(MEMORY_INTER) %{
4791 base(0x4); // ESP
4792 index(0x4); // No Index
4793 scale(0x0); // No Scale
4794 disp($reg); // Stack Offset
4795 %}
4796 %}
4797
4798 operand stackSlotD(sRegD reg) %{
4799 constraint(ALLOC_IN_RC(stack_slots));
4800 // No match rule because this operand is only generated in matching
4801 format %{ "[$reg]" %}
4802 interface(MEMORY_INTER) %{
4803 base(0x4); // ESP
4804 index(0x4); // No Index
4805 scale(0x0); // No Scale
4806 disp($reg); // Stack Offset
4807 %}
4808 %}
4809
4810 operand stackSlotL(sRegL reg) %{
4811 constraint(ALLOC_IN_RC(stack_slots));
4812 // No match rule because this operand is only generated in matching
4813 format %{ "[$reg]" %}
4814 interface(MEMORY_INTER) %{
4815 base(0x4); // ESP
4816 index(0x4); // No Index
4817 scale(0x0); // No Scale
4818 disp($reg); // Stack Offset
4819 %}
4820 %}
4821
4822 //----------Memory Operands - Win95 Implicit Null Variants----------------
4823 // Indirect Memory Operand
4824 operand indirect_win95_safe(eRegP_no_EBP reg)
4825 %{
4826 constraint(ALLOC_IN_RC(e_reg));
4827 match(reg);
4828
4829 op_cost(100);
4830 format %{ "[$reg]" %}
4831 interface(MEMORY_INTER) %{
4832 base($reg);
4833 index(0x4);
4834 scale(0x0);
4835 disp(0x0);
4836 %}
4837 %}
4838
4839 // Indirect Memory Plus Short Offset Operand
4840 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4841 %{
4842 match(AddP reg off);
4843
4844 op_cost(100);
4845 format %{ "[$reg + $off]" %}
4846 interface(MEMORY_INTER) %{
4847 base($reg);
4848 index(0x4);
4849 scale(0x0);
4850 disp($off);
4851 %}
4852 %}
4853
4854 // Indirect Memory Plus Long Offset Operand
4855 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4856 %{
4857 match(AddP reg off);
4858
4859 op_cost(100);
4860 format %{ "[$reg + $off]" %}
4861 interface(MEMORY_INTER) %{
4862 base($reg);
4863 index(0x4);
4864 scale(0x0);
4865 disp($off);
4866 %}
4867 %}
4868
4869 // Indirect Memory Plus Index Register Plus Offset Operand
4870 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
4871 %{
4872 match(AddP (AddP reg ireg) off);
4873
4874 op_cost(100);
4875 format %{"[$reg + $off + $ireg]" %}
4876 interface(MEMORY_INTER) %{
4877 base($reg);
4878 index($ireg);
4879 scale(0x0);
4880 disp($off);
4881 %}
4882 %}
4883
4884 // Indirect Memory Times Scale Plus Index Register
4885 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
4886 %{
4887 match(AddP reg (LShiftI ireg scale));
4888
4889 op_cost(100);
4890 format %{"[$reg + $ireg << $scale]" %}
4891 interface(MEMORY_INTER) %{
4892 base($reg);
4893 index($ireg);
4894 scale($scale);
4895 disp(0x0);
4896 %}
4897 %}
4898
4899 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4900 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
4901 %{
4902 match(AddP (AddP reg (LShiftI ireg scale)) off);
4903
4904 op_cost(100);
4905 format %{"[$reg + $off + $ireg << $scale]" %}
4906 interface(MEMORY_INTER) %{
4907 base($reg);
4908 index($ireg);
4909 scale($scale);
4910 disp($off);
4911 %}
4912 %}
4913
4914 //----------Conditional Branch Operands----------------------------------------
4915 // Comparison Op - This is the operation of the comparison, and is limited to
4916 // the following set of codes:
4917 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4918 //
4919 // Other attributes of the comparison, such as unsignedness, are specified
4920 // by the comparison instruction that sets a condition code flags register.
4921 // That result is represented by a flags operand whose subtype is appropriate
4922 // to the unsignedness (etc.) of the comparison.
4923 //
4924 // Later, the instruction which matches both the Comparison Op (a Bool) and
4925 // the flags (produced by the Cmp) specifies the coding of the comparison op
4926 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4927
4928 // Comparision Code
4929 operand cmpOp() %{
4930 match(Bool);
4931
4932 format %{ "" %}
4933 interface(COND_INTER) %{
4934 equal(0x4, "e");
4935 not_equal(0x5, "ne");
4936 less(0xC, "l");
4937 greater_equal(0xD, "ge");
4938 less_equal(0xE, "le");
4939 greater(0xF, "g");
4940 %}
4941 %}
4942
4943 // Comparison Code, unsigned compare. Used by FP also, with
4944 // C2 (unordered) turned into GT or LT already. The other bits
4945 // C0 and C3 are turned into Carry & Zero flags.
4946 operand cmpOpU() %{
4947 match(Bool);
4948
4949 format %{ "" %}
4950 interface(COND_INTER) %{
4951 equal(0x4, "e");
4952 not_equal(0x5, "ne");
4953 less(0x2, "b");
4954 greater_equal(0x3, "nb");
4955 less_equal(0x6, "be");
4956 greater(0x7, "nbe");
4957 %}
4958 %}
4959
4960 // Floating comparisons that don't require any fixup for the unordered case
4961 operand cmpOpUCF() %{
4962 match(Bool);
4963 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4964 n->as_Bool()->_test._test == BoolTest::ge ||
4965 n->as_Bool()->_test._test == BoolTest::le ||
4966 n->as_Bool()->_test._test == BoolTest::gt);
4967 format %{ "" %}
4968 interface(COND_INTER) %{
4969 equal(0x4, "e");
4970 not_equal(0x5, "ne");
4971 less(0x2, "b");
4972 greater_equal(0x3, "nb");
4973 less_equal(0x6, "be");
4974 greater(0x7, "nbe");
4975 %}
4976 %}
4977
4978
4979 // Floating comparisons that can be fixed up with extra conditional jumps
4980 operand cmpOpUCF2() %{
4981 match(Bool);
4982 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4983 n->as_Bool()->_test._test == BoolTest::eq);
4984 format %{ "" %}
4985 interface(COND_INTER) %{
4986 equal(0x4, "e");
4987 not_equal(0x5, "ne");
4988 less(0x2, "b");
4989 greater_equal(0x3, "nb");
4990 less_equal(0x6, "be");
4991 greater(0x7, "nbe");
4992 %}
4993 %}
4994
4995 // Comparison Code for FP conditional move
4996 operand cmpOp_fcmov() %{
4997 match(Bool);
4998
4999 format %{ "" %}
5000 interface(COND_INTER) %{
5001 equal (0x0C8);
5002 not_equal (0x1C8);
5003 less (0x0C0);
5004 greater_equal(0x1C0);
5005 less_equal (0x0D0);
5006 greater (0x1D0);
5007 %}
5008 %}
5009
5010 // Comparision Code used in long compares
5011 operand cmpOp_commute() %{
5012 match(Bool);
5013
5014 format %{ "" %}
5015 interface(COND_INTER) %{
5016 equal(0x4, "e");
5017 not_equal(0x5, "ne");
5018 less(0xF, "g");
5019 greater_equal(0xE, "le");
5020 less_equal(0xD, "ge");
5021 greater(0xC, "l");
5022 %}
5023 %}
5024
5025 //----------OPERAND CLASSES----------------------------------------------------
5026 // Operand Classes are groups of operands that are used as to simplify
5027 // instruction definitions by not requiring the AD writer to specify separate
5028 // instructions for every form of operand when the instruction accepts
5029 // multiple operand types with the same basic encoding and format. The classic
5030 // case of this is memory operands.
5031
5032 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5033 indIndex, indIndexScale, indIndexScaleOffset);
5034
5035 // Long memory operations are encoded in 2 instructions and a +4 offset.
5036 // This means some kind of offset is always required and you cannot use
5037 // an oop as the offset (done when working on static globals).
5038 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5039 indIndex, indIndexScale, indIndexScaleOffset);
5040
5041
5042 //----------PIPELINE-----------------------------------------------------------
5043 // Rules which define the behavior of the target architectures pipeline.
5044 pipeline %{
5045
5046 //----------ATTRIBUTES---------------------------------------------------------
5047 attributes %{
5048 variable_size_instructions; // Fixed size instructions
5049 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5050 instruction_unit_size = 1; // An instruction is 1 bytes long
5051 instruction_fetch_unit_size = 16; // The processor fetches one line
5052 instruction_fetch_units = 1; // of 16 bytes
5053
5054 // List of nop instructions
5055 nops( MachNop );
5056 %}
5057
5058 //----------RESOURCES----------------------------------------------------------
5059 // Resources are the functional units available to the machine
5060
5061 // Generic P2/P3 pipeline
5062 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5063 // 3 instructions decoded per cycle.
5064 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5065 // 2 ALU op, only ALU0 handles mul/div instructions.
5066 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5067 MS0, MS1, MEM = MS0 | MS1,
5068 BR, FPU,
5069 ALU0, ALU1, ALU = ALU0 | ALU1 );
5070
5071 //----------PIPELINE DESCRIPTION-----------------------------------------------
5072 // Pipeline Description specifies the stages in the machine's pipeline
5073
5074 // Generic P2/P3 pipeline
5075 pipe_desc(S0, S1, S2, S3, S4, S5);
5076
5077 //----------PIPELINE CLASSES---------------------------------------------------
5078 // Pipeline Classes describe the stages in which input and output are
5079 // referenced by the hardware pipeline.
5080
5081 // Naming convention: ialu or fpu
5082 // Then: _reg
5083 // Then: _reg if there is a 2nd register
5084 // Then: _long if it's a pair of instructions implementing a long
5085 // Then: _fat if it requires the big decoder
5086 // Or: _mem if it requires the big decoder and a memory unit.
5087
5088 // Integer ALU reg operation
5089 pipe_class ialu_reg(eRegI dst) %{
5090 single_instruction;
5091 dst : S4(write);
5092 dst : S3(read);
5093 DECODE : S0; // any decoder
5094 ALU : S3; // any alu
5095 %}
5096
5097 // Long ALU reg operation
5098 pipe_class ialu_reg_long(eRegL dst) %{
5099 instruction_count(2);
5100 dst : S4(write);
5101 dst : S3(read);
5102 DECODE : S0(2); // any 2 decoders
5103 ALU : S3(2); // both alus
5104 %}
5105
5106 // Integer ALU reg operation using big decoder
5107 pipe_class ialu_reg_fat(eRegI dst) %{
5108 single_instruction;
5109 dst : S4(write);
5110 dst : S3(read);
5111 D0 : S0; // big decoder only
5112 ALU : S3; // any alu
5113 %}
5114
5115 // Long ALU reg operation using big decoder
5116 pipe_class ialu_reg_long_fat(eRegL dst) %{
5117 instruction_count(2);
5118 dst : S4(write);
5119 dst : S3(read);
5120 D0 : S0(2); // big decoder only; twice
5121 ALU : S3(2); // any 2 alus
5122 %}
5123
5124 // Integer ALU reg-reg operation
5125 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5126 single_instruction;
5127 dst : S4(write);
5128 src : S3(read);
5129 DECODE : S0; // any decoder
5130 ALU : S3; // any alu
5131 %}
5132
5133 // Long ALU reg-reg operation
5134 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5135 instruction_count(2);
5136 dst : S4(write);
5137 src : S3(read);
5138 DECODE : S0(2); // any 2 decoders
5139 ALU : S3(2); // both alus
5140 %}
5141
5142 // Integer ALU reg-reg operation
5143 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5144 single_instruction;
5145 dst : S4(write);
5146 src : S3(read);
5147 D0 : S0; // big decoder only
5148 ALU : S3; // any alu
5149 %}
5150
5151 // Long ALU reg-reg operation
5152 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5153 instruction_count(2);
5154 dst : S4(write);
5155 src : S3(read);
5156 D0 : S0(2); // big decoder only; twice
5157 ALU : S3(2); // both alus
5158 %}
5159
5160 // Integer ALU reg-mem operation
5161 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5162 single_instruction;
5163 dst : S5(write);
5164 mem : S3(read);
5165 D0 : S0; // big decoder only
5166 ALU : S4; // any alu
5167 MEM : S3; // any mem
5168 %}
5169
5170 // Long ALU reg-mem operation
5171 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5172 instruction_count(2);
5173 dst : S5(write);
5174 mem : S3(read);
5175 D0 : S0(2); // big decoder only; twice
5176 ALU : S4(2); // any 2 alus
5177 MEM : S3(2); // both mems
5178 %}
5179
5180 // Integer mem operation (prefetch)
5181 pipe_class ialu_mem(memory mem)
5182 %{
5183 single_instruction;
5184 mem : S3(read);
5185 D0 : S0; // big decoder only
5186 MEM : S3; // any mem
5187 %}
5188
5189 // Integer Store to Memory
5190 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5191 single_instruction;
5192 mem : S3(read);
5193 src : S5(read);
5194 D0 : S0; // big decoder only
5195 ALU : S4; // any alu
5196 MEM : S3;
5197 %}
5198
5199 // Long Store to Memory
5200 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5201 instruction_count(2);
5202 mem : S3(read);
5203 src : S5(read);
5204 D0 : S0(2); // big decoder only; twice
5205 ALU : S4(2); // any 2 alus
5206 MEM : S3(2); // Both mems
5207 %}
5208
5209 // Integer Store to Memory
5210 pipe_class ialu_mem_imm(memory mem) %{
5211 single_instruction;
5212 mem : S3(read);
5213 D0 : S0; // big decoder only
5214 ALU : S4; // any alu
5215 MEM : S3;
5216 %}
5217
5218 // Integer ALU0 reg-reg operation
5219 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5220 single_instruction;
5221 dst : S4(write);
5222 src : S3(read);
5223 D0 : S0; // Big decoder only
5224 ALU0 : S3; // only alu0
5225 %}
5226
5227 // Integer ALU0 reg-mem operation
5228 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5229 single_instruction;
5230 dst : S5(write);
5231 mem : S3(read);
5232 D0 : S0; // big decoder only
5233 ALU0 : S4; // ALU0 only
5234 MEM : S3; // any mem
5235 %}
5236
5237 // Integer ALU reg-reg operation
5238 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5239 single_instruction;
5240 cr : S4(write);
5241 src1 : S3(read);
5242 src2 : S3(read);
5243 DECODE : S0; // any decoder
5244 ALU : S3; // any alu
5245 %}
5246
5247 // Integer ALU reg-imm operation
5248 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5249 single_instruction;
5250 cr : S4(write);
5251 src1 : S3(read);
5252 DECODE : S0; // any decoder
5253 ALU : S3; // any alu
5254 %}
5255
5256 // Integer ALU reg-mem operation
5257 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5258 single_instruction;
5259 cr : S4(write);
5260 src1 : S3(read);
5261 src2 : S3(read);
5262 D0 : S0; // big decoder only
5263 ALU : S4; // any alu
5264 MEM : S3;
5265 %}
5266
5267 // Conditional move reg-reg
5268 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5269 instruction_count(4);
5270 y : S4(read);
5271 q : S3(read);
5272 p : S3(read);
5273 DECODE : S0(4); // any decoder
5274 %}
5275
5276 // Conditional move reg-reg
5277 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5278 single_instruction;
5279 dst : S4(write);
5280 src : S3(read);
5281 cr : S3(read);
5282 DECODE : S0; // any decoder
5283 %}
5284
5285 // Conditional move reg-mem
5286 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5287 single_instruction;
5288 dst : S4(write);
5289 src : S3(read);
5290 cr : S3(read);
5291 DECODE : S0; // any decoder
5292 MEM : S3;
5293 %}
5294
5295 // Conditional move reg-reg long
5296 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5297 single_instruction;
5298 dst : S4(write);
5299 src : S3(read);
5300 cr : S3(read);
5301 DECODE : S0(2); // any 2 decoders
5302 %}
5303
5304 // Conditional move double reg-reg
5305 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5306 single_instruction;
5307 dst : S4(write);
5308 src : S3(read);
5309 cr : S3(read);
5310 DECODE : S0; // any decoder
5311 %}
5312
5313 // Float reg-reg operation
5314 pipe_class fpu_reg(regDPR dst) %{
5315 instruction_count(2);
5316 dst : S3(read);
5317 DECODE : S0(2); // any 2 decoders
5318 FPU : S3;
5319 %}
5320
5321 // Float reg-reg operation
5322 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5323 instruction_count(2);
5324 dst : S4(write);
5325 src : S3(read);
5326 DECODE : S0(2); // any 2 decoders
5327 FPU : S3;
5328 %}
5329
5330 // Float reg-reg operation
5331 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5332 instruction_count(3);
5333 dst : S4(write);
5334 src1 : S3(read);
5335 src2 : S3(read);
5336 DECODE : S0(3); // any 3 decoders
5337 FPU : S3(2);
5338 %}
5339
5340 // Float reg-reg operation
5341 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5342 instruction_count(4);
5343 dst : S4(write);
5344 src1 : S3(read);
5345 src2 : S3(read);
5346 src3 : S3(read);
5347 DECODE : S0(4); // any 3 decoders
5348 FPU : S3(2);
5349 %}
5350
5351 // Float reg-reg operation
5352 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5353 instruction_count(4);
5354 dst : S4(write);
5355 src1 : S3(read);
5356 src2 : S3(read);
5357 src3 : S3(read);
5358 DECODE : S1(3); // any 3 decoders
5359 D0 : S0; // Big decoder only
5360 FPU : S3(2);
5361 MEM : S3;
5362 %}
5363
5364 // Float reg-mem operation
5365 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5366 instruction_count(2);
5367 dst : S5(write);
5368 mem : S3(read);
5369 D0 : S0; // big decoder only
5370 DECODE : S1; // any decoder for FPU POP
5371 FPU : S4;
5372 MEM : S3; // any mem
5373 %}
5374
5375 // Float reg-mem operation
5376 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5377 instruction_count(3);
5378 dst : S5(write);
5379 src1 : S3(read);
5380 mem : S3(read);
5381 D0 : S0; // big decoder only
5382 DECODE : S1(2); // any decoder for FPU POP
5383 FPU : S4;
5384 MEM : S3; // any mem
5385 %}
5386
5387 // Float mem-reg operation
5388 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5389 instruction_count(2);
5390 src : S5(read);
5391 mem : S3(read);
5392 DECODE : S0; // any decoder for FPU PUSH
5393 D0 : S1; // big decoder only
5394 FPU : S4;
5395 MEM : S3; // any mem
5396 %}
5397
5398 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5399 instruction_count(3);
5400 src1 : S3(read);
5401 src2 : S3(read);
5402 mem : S3(read);
5403 DECODE : S0(2); // any decoder for FPU PUSH
5404 D0 : S1; // big decoder only
5405 FPU : S4;
5406 MEM : S3; // any mem
5407 %}
5408
5409 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5410 instruction_count(3);
5411 src1 : S3(read);
5412 src2 : S3(read);
5413 mem : S4(read);
5414 DECODE : S0; // any decoder for FPU PUSH
5415 D0 : S0(2); // big decoder only
5416 FPU : S4;
5417 MEM : S3(2); // any mem
5418 %}
5419
5420 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5421 instruction_count(2);
5422 src1 : S3(read);
5423 dst : S4(read);
5424 D0 : S0(2); // big decoder only
5425 MEM : S3(2); // any mem
5426 %}
5427
5428 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5429 instruction_count(3);
5430 src1 : S3(read);
5431 src2 : S3(read);
5432 dst : S4(read);
5433 D0 : S0(3); // big decoder only
5434 FPU : S4;
5435 MEM : S3(3); // any mem
5436 %}
5437
5438 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5439 instruction_count(3);
5440 src1 : S4(read);
5441 mem : S4(read);
5442 DECODE : S0; // any decoder for FPU PUSH
5443 D0 : S0(2); // big decoder only
5444 FPU : S4;
5445 MEM : S3(2); // any mem
5446 %}
5447
5448 // Float load constant
5449 pipe_class fpu_reg_con(regDPR dst) %{
5450 instruction_count(2);
5451 dst : S5(write);
5452 D0 : S0; // big decoder only for the load
5453 DECODE : S1; // any decoder for FPU POP
5454 FPU : S4;
5455 MEM : S3; // any mem
5456 %}
5457
5458 // Float load constant
5459 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5460 instruction_count(3);
5461 dst : S5(write);
5462 src : S3(read);
5463 D0 : S0; // big decoder only for the load
5464 DECODE : S1(2); // any decoder for FPU POP
5465 FPU : S4;
5466 MEM : S3; // any mem
5467 %}
5468
5469 // UnConditional branch
5470 pipe_class pipe_jmp( label labl ) %{
5471 single_instruction;
5472 BR : S3;
5473 %}
5474
5475 // Conditional branch
5476 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5477 single_instruction;
5478 cr : S1(read);
5479 BR : S3;
5480 %}
5481
5482 // Allocation idiom
5483 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5484 instruction_count(1); force_serialization;
5485 fixed_latency(6);
5486 heap_ptr : S3(read);
5487 DECODE : S0(3);
5488 D0 : S2;
5489 MEM : S3;
5490 ALU : S3(2);
5491 dst : S5(write);
5492 BR : S5;
5493 %}
5494
5495 // Generic big/slow expanded idiom
5496 pipe_class pipe_slow( ) %{
5497 instruction_count(10); multiple_bundles; force_serialization;
5498 fixed_latency(100);
5499 D0 : S0(2);
5500 MEM : S3(2);
5501 %}
5502
5503 // The real do-nothing guy
5504 pipe_class empty( ) %{
5505 instruction_count(0);
5506 %}
5507
5508 // Define the class for the Nop node
5509 define %{
5510 MachNop = empty;
5511 %}
5512
5513 %}
5514
5515 //----------INSTRUCTIONS-------------------------------------------------------
5516 //
5517 // match -- States which machine-independent subtree may be replaced
5518 // by this instruction.
5519 // ins_cost -- The estimated cost of this instruction is used by instruction
5520 // selection to identify a minimum cost tree of machine
5521 // instructions that matches a tree of machine-independent
5522 // instructions.
5523 // format -- A string providing the disassembly for this instruction.
5524 // The value of an instruction's operand may be inserted
5525 // by referring to it with a '$' prefix.
5526 // opcode -- Three instruction opcodes may be provided. These are referred
5527 // to within an encode class as $primary, $secondary, and $tertiary
5528 // respectively. The primary opcode is commonly used to
5529 // indicate the type of machine instruction, while secondary
5530 // and tertiary are often used for prefix options or addressing
5531 // modes.
5532 // ins_encode -- A list of encode classes with parameters. The encode class
5533 // name must have been defined in an 'enc_class' specification
5534 // in the encode section of the architecture description.
5535
5536 //----------BSWAP-Instruction--------------------------------------------------
5537 instruct bytes_reverse_int(eRegI dst) %{
5538 match(Set dst (ReverseBytesI dst));
5539
5540 format %{ "BSWAP $dst" %}
5541 opcode(0x0F, 0xC8);
5542 ins_encode( OpcP, OpcSReg(dst) );
5543 ins_pipe( ialu_reg );
5544 %}
5545
5546 instruct bytes_reverse_long(eRegL dst) %{
5547 match(Set dst (ReverseBytesL dst));
5548
5549 format %{ "BSWAP $dst.lo\n\t"
5550 "BSWAP $dst.hi\n\t"
5551 "XCHG $dst.lo $dst.hi" %}
5552
5553 ins_cost(125);
5554 ins_encode( bswap_long_bytes(dst) );
5555 ins_pipe( ialu_reg_reg);
5556 %}
5557
5558 instruct bytes_reverse_unsigned_short(eRegI dst) %{
5559 match(Set dst (ReverseBytesUS dst));
5560
5561 format %{ "BSWAP $dst\n\t"
5562 "SHR $dst,16\n\t" %}
5563 ins_encode %{
5564 __ bswapl($dst$$Register);
5565 __ shrl($dst$$Register, 16);
5566 %}
5567 ins_pipe( ialu_reg );
5568 %}
5569
5570 instruct bytes_reverse_short(eRegI dst) %{
5571 match(Set dst (ReverseBytesS dst));
5572
5573 format %{ "BSWAP $dst\n\t"
5574 "SAR $dst,16\n\t" %}
5575 ins_encode %{
5576 __ bswapl($dst$$Register);
5577 __ sarl($dst$$Register, 16);
5578 %}
5579 ins_pipe( ialu_reg );
5580 %}
5581
5582
5583 //---------- Zeros Count Instructions ------------------------------------------
5584
5585 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5586 predicate(UseCountLeadingZerosInstruction);
5587 match(Set dst (CountLeadingZerosI src));
5588 effect(KILL cr);
5589
5590 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5591 ins_encode %{
5592 __ lzcntl($dst$$Register, $src$$Register);
5593 %}
5594 ins_pipe(ialu_reg);
5595 %}
5596
5597 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
5598 predicate(!UseCountLeadingZerosInstruction);
5599 match(Set dst (CountLeadingZerosI src));
5600 effect(KILL cr);
5601
5602 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5603 "JNZ skip\n\t"
5604 "MOV $dst, -1\n"
5605 "skip:\n\t"
5606 "NEG $dst\n\t"
5607 "ADD $dst, 31" %}
5608 ins_encode %{
5609 Register Rdst = $dst$$Register;
5610 Register Rsrc = $src$$Register;
5611 Label skip;
5612 __ bsrl(Rdst, Rsrc);
5613 __ jccb(Assembler::notZero, skip);
5614 __ movl(Rdst, -1);
5615 __ bind(skip);
5616 __ negl(Rdst);
5617 __ addl(Rdst, BitsPerInt - 1);
5618 %}
5619 ins_pipe(ialu_reg);
5620 %}
5621
5622 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5623 predicate(UseCountLeadingZerosInstruction);
5624 match(Set dst (CountLeadingZerosL src));
5625 effect(TEMP dst, KILL cr);
5626
5627 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5628 "JNC done\n\t"
5629 "LZCNT $dst, $src.lo\n\t"
5630 "ADD $dst, 32\n"
5631 "done:" %}
5632 ins_encode %{
5633 Register Rdst = $dst$$Register;
5634 Register Rsrc = $src$$Register;
5635 Label done;
5636 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5637 __ jccb(Assembler::carryClear, done);
5638 __ lzcntl(Rdst, Rsrc);
5639 __ addl(Rdst, BitsPerInt);
5640 __ bind(done);
5641 %}
5642 ins_pipe(ialu_reg);
5643 %}
5644
5645 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
5646 predicate(!UseCountLeadingZerosInstruction);
5647 match(Set dst (CountLeadingZerosL src));
5648 effect(TEMP dst, KILL cr);
5649
5650 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5651 "JZ msw_is_zero\n\t"
5652 "ADD $dst, 32\n\t"
5653 "JMP not_zero\n"
5654 "msw_is_zero:\n\t"
5655 "BSR $dst, $src.lo\n\t"
5656 "JNZ not_zero\n\t"
5657 "MOV $dst, -1\n"
5658 "not_zero:\n\t"
5659 "NEG $dst\n\t"
5660 "ADD $dst, 63\n" %}
5661 ins_encode %{
5662 Register Rdst = $dst$$Register;
5663 Register Rsrc = $src$$Register;
5664 Label msw_is_zero;
5665 Label not_zero;
5666 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5667 __ jccb(Assembler::zero, msw_is_zero);
5668 __ addl(Rdst, BitsPerInt);
5669 __ jmpb(not_zero);
5670 __ bind(msw_is_zero);
5671 __ bsrl(Rdst, Rsrc);
5672 __ jccb(Assembler::notZero, not_zero);
5673 __ movl(Rdst, -1);
5674 __ bind(not_zero);
5675 __ negl(Rdst);
5676 __ addl(Rdst, BitsPerLong - 1);
5677 %}
5678 ins_pipe(ialu_reg);
5679 %}
5680
5681 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5682 match(Set dst (CountTrailingZerosI src));
5683 effect(KILL cr);
5684
5685 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5686 "JNZ done\n\t"
5687 "MOV $dst, 32\n"
5688 "done:" %}
5689 ins_encode %{
5690 Register Rdst = $dst$$Register;
5691 Label done;
5692 __ bsfl(Rdst, $src$$Register);
5693 __ jccb(Assembler::notZero, done);
5694 __ movl(Rdst, BitsPerInt);
5695 __ bind(done);
5696 %}
5697 ins_pipe(ialu_reg);
5698 %}
5699
5700 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5701 match(Set dst (CountTrailingZerosL src));
5702 effect(TEMP dst, KILL cr);
5703
5704 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5705 "JNZ done\n\t"
5706 "BSF $dst, $src.hi\n\t"
5707 "JNZ msw_not_zero\n\t"
5708 "MOV $dst, 32\n"
5709 "msw_not_zero:\n\t"
5710 "ADD $dst, 32\n"
5711 "done:" %}
5712 ins_encode %{
5713 Register Rdst = $dst$$Register;
5714 Register Rsrc = $src$$Register;
5715 Label msw_not_zero;
5716 Label done;
5717 __ bsfl(Rdst, Rsrc);
5718 __ jccb(Assembler::notZero, done);
5719 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5720 __ jccb(Assembler::notZero, msw_not_zero);
5721 __ movl(Rdst, BitsPerInt);
5722 __ bind(msw_not_zero);
5723 __ addl(Rdst, BitsPerInt);
5724 __ bind(done);
5725 %}
5726 ins_pipe(ialu_reg);
5727 %}
5728
5729
5730 //---------- Population Count Instructions -------------------------------------
5731
5732 instruct popCountI(eRegI dst, eRegI src) %{
5733 predicate(UsePopCountInstruction);
5734 match(Set dst (PopCountI src));
5735
5736 format %{ "POPCNT $dst, $src" %}
5737 ins_encode %{
5738 __ popcntl($dst$$Register, $src$$Register);
5739 %}
5740 ins_pipe(ialu_reg);
5741 %}
5742
5743 instruct popCountI_mem(eRegI dst, memory mem) %{
5744 predicate(UsePopCountInstruction);
5745 match(Set dst (PopCountI (LoadI mem)));
5746
5747 format %{ "POPCNT $dst, $mem" %}
5748 ins_encode %{
5749 __ popcntl($dst$$Register, $mem$$Address);
5750 %}
5751 ins_pipe(ialu_reg);
5752 %}
5753
5754 // Note: Long.bitCount(long) returns an int.
5755 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
5756 predicate(UsePopCountInstruction);
5757 match(Set dst (PopCountL src));
5758 effect(KILL cr, TEMP tmp, TEMP dst);
5759
5760 format %{ "POPCNT $dst, $src.lo\n\t"
5761 "POPCNT $tmp, $src.hi\n\t"
5762 "ADD $dst, $tmp" %}
5763 ins_encode %{
5764 __ popcntl($dst$$Register, $src$$Register);
5765 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5766 __ addl($dst$$Register, $tmp$$Register);
5767 %}
5768 ins_pipe(ialu_reg);
5769 %}
5770
5771 // Note: Long.bitCount(long) returns an int.
5772 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
5773 predicate(UsePopCountInstruction);
5774 match(Set dst (PopCountL (LoadL mem)));
5775 effect(KILL cr, TEMP tmp, TEMP dst);
5776
5777 format %{ "POPCNT $dst, $mem\n\t"
5778 "POPCNT $tmp, $mem+4\n\t"
5779 "ADD $dst, $tmp" %}
5780 ins_encode %{
5781 //__ popcntl($dst$$Register, $mem$$Address$$first);
5782 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5783 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5784 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5785 __ addl($dst$$Register, $tmp$$Register);
5786 %}
5787 ins_pipe(ialu_reg);
5788 %}
5789
5790
5791 //----------Load/Store/Move Instructions---------------------------------------
5792 //----------Load Instructions--------------------------------------------------
5793 // Load Byte (8bit signed)
5794 instruct loadB(xRegI dst, memory mem) %{
5795 match(Set dst (LoadB mem));
5796
5797 ins_cost(125);
5798 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5799
5800 ins_encode %{
5801 __ movsbl($dst$$Register, $mem$$Address);
5802 %}
5803
5804 ins_pipe(ialu_reg_mem);
5805 %}
5806
5807 // Load Byte (8bit signed) into Long Register
5808 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5809 match(Set dst (ConvI2L (LoadB mem)));
5810 effect(KILL cr);
5811
5812 ins_cost(375);
5813 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5814 "MOV $dst.hi,$dst.lo\n\t"
5815 "SAR $dst.hi,7" %}
5816
5817 ins_encode %{
5818 __ movsbl($dst$$Register, $mem$$Address);
5819 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5820 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5821 %}
5822
5823 ins_pipe(ialu_reg_mem);
5824 %}
5825
5826 // Load Unsigned Byte (8bit UNsigned)
5827 instruct loadUB(xRegI dst, memory mem) %{
5828 match(Set dst (LoadUB mem));
5829
5830 ins_cost(125);
5831 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5832
5833 ins_encode %{
5834 __ movzbl($dst$$Register, $mem$$Address);
5835 %}
5836
5837 ins_pipe(ialu_reg_mem);
5838 %}
5839
5840 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5841 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5842 match(Set dst (ConvI2L (LoadUB mem)));
5843 effect(KILL cr);
5844
5845 ins_cost(250);
5846 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5847 "XOR $dst.hi,$dst.hi" %}
5848
5849 ins_encode %{
5850 Register Rdst = $dst$$Register;
5851 __ movzbl(Rdst, $mem$$Address);
5852 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5853 %}
5854
5855 ins_pipe(ialu_reg_mem);
5856 %}
5857
5858 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5859 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5860 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5861 effect(KILL cr);
5862
5863 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5864 "XOR $dst.hi,$dst.hi\n\t"
5865 "AND $dst.lo,$mask" %}
5866 ins_encode %{
5867 Register Rdst = $dst$$Register;
5868 __ movzbl(Rdst, $mem$$Address);
5869 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5870 __ andl(Rdst, $mask$$constant);
5871 %}
5872 ins_pipe(ialu_reg_mem);
5873 %}
5874
5875 // Load Short (16bit signed)
5876 instruct loadS(eRegI dst, memory mem) %{
5877 match(Set dst (LoadS mem));
5878
5879 ins_cost(125);
5880 format %{ "MOVSX $dst,$mem\t# short" %}
5881
5882 ins_encode %{
5883 __ movswl($dst$$Register, $mem$$Address);
5884 %}
5885
5886 ins_pipe(ialu_reg_mem);
5887 %}
5888
5889 // Load Short (16 bit signed) to Byte (8 bit signed)
5890 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5891 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5892
5893 ins_cost(125);
5894 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5895 ins_encode %{
5896 __ movsbl($dst$$Register, $mem$$Address);
5897 %}
5898 ins_pipe(ialu_reg_mem);
5899 %}
5900
5901 // Load Short (16bit signed) into Long Register
5902 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5903 match(Set dst (ConvI2L (LoadS mem)));
5904 effect(KILL cr);
5905
5906 ins_cost(375);
5907 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5908 "MOV $dst.hi,$dst.lo\n\t"
5909 "SAR $dst.hi,15" %}
5910
5911 ins_encode %{
5912 __ movswl($dst$$Register, $mem$$Address);
5913 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5914 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5915 %}
5916
5917 ins_pipe(ialu_reg_mem);
5918 %}
5919
5920 // Load Unsigned Short/Char (16bit unsigned)
5921 instruct loadUS(eRegI dst, memory mem) %{
5922 match(Set dst (LoadUS mem));
5923
5924 ins_cost(125);
5925 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5926
5927 ins_encode %{
5928 __ movzwl($dst$$Register, $mem$$Address);
5929 %}
5930
5931 ins_pipe(ialu_reg_mem);
5932 %}
5933
5934 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5935 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5936 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5937
5938 ins_cost(125);
5939 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5940 ins_encode %{
5941 __ movsbl($dst$$Register, $mem$$Address);
5942 %}
5943 ins_pipe(ialu_reg_mem);
5944 %}
5945
5946 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5947 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5948 match(Set dst (ConvI2L (LoadUS mem)));
5949 effect(KILL cr);
5950
5951 ins_cost(250);
5952 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5953 "XOR $dst.hi,$dst.hi" %}
5954
5955 ins_encode %{
5956 __ movzwl($dst$$Register, $mem$$Address);
5957 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5958 %}
5959
5960 ins_pipe(ialu_reg_mem);
5961 %}
5962
5963 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5964 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5965 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5966 effect(KILL cr);
5967
5968 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5969 "XOR $dst.hi,$dst.hi" %}
5970 ins_encode %{
5971 Register Rdst = $dst$$Register;
5972 __ movzbl(Rdst, $mem$$Address);
5973 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5974 %}
5975 ins_pipe(ialu_reg_mem);
5976 %}
5977
5978 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5979 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5980 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5981 effect(KILL cr);
5982
5983 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5984 "XOR $dst.hi,$dst.hi\n\t"
5985 "AND $dst.lo,$mask" %}
5986 ins_encode %{
5987 Register Rdst = $dst$$Register;
5988 __ movzwl(Rdst, $mem$$Address);
5989 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5990 __ andl(Rdst, $mask$$constant);
5991 %}
5992 ins_pipe(ialu_reg_mem);
5993 %}
5994
5995 // Load Integer
5996 instruct loadI(eRegI dst, memory mem) %{
5997 match(Set dst (LoadI mem));
5998
5999 ins_cost(125);
6000 format %{ "MOV $dst,$mem\t# int" %}
6001
6002 ins_encode %{
6003 __ movl($dst$$Register, $mem$$Address);
6004 %}
6005
6006 ins_pipe(ialu_reg_mem);
6007 %}
6008
6009 // Load Integer (32 bit signed) to Byte (8 bit signed)
6010 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6011 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6012
6013 ins_cost(125);
6014 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6015 ins_encode %{
6016 __ movsbl($dst$$Register, $mem$$Address);
6017 %}
6018 ins_pipe(ialu_reg_mem);
6019 %}
6020
6021 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6022 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6023 match(Set dst (AndI (LoadI mem) mask));
6024
6025 ins_cost(125);
6026 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6027 ins_encode %{
6028 __ movzbl($dst$$Register, $mem$$Address);
6029 %}
6030 ins_pipe(ialu_reg_mem);
6031 %}
6032
6033 // Load Integer (32 bit signed) to Short (16 bit signed)
6034 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6035 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6036
6037 ins_cost(125);
6038 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6039 ins_encode %{
6040 __ movswl($dst$$Register, $mem$$Address);
6041 %}
6042 ins_pipe(ialu_reg_mem);
6043 %}
6044
6045 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6046 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6047 match(Set dst (AndI (LoadI mem) mask));
6048
6049 ins_cost(125);
6050 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6051 ins_encode %{
6052 __ movzwl($dst$$Register, $mem$$Address);
6053 %}
6054 ins_pipe(ialu_reg_mem);
6055 %}
6056
6057 // Load Integer into Long Register
6058 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6059 match(Set dst (ConvI2L (LoadI mem)));
6060 effect(KILL cr);
6061
6062 ins_cost(375);
6063 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6064 "MOV $dst.hi,$dst.lo\n\t"
6065 "SAR $dst.hi,31" %}
6066
6067 ins_encode %{
6068 __ movl($dst$$Register, $mem$$Address);
6069 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6070 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6071 %}
6072
6073 ins_pipe(ialu_reg_mem);
6074 %}
6075
6076 // Load Integer with mask 0xFF into Long Register
6077 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6078 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6079 effect(KILL cr);
6080
6081 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6082 "XOR $dst.hi,$dst.hi" %}
6083 ins_encode %{
6084 Register Rdst = $dst$$Register;
6085 __ movzbl(Rdst, $mem$$Address);
6086 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6087 %}
6088 ins_pipe(ialu_reg_mem);
6089 %}
6090
6091 // Load Integer with mask 0xFFFF into Long Register
6092 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6093 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6094 effect(KILL cr);
6095
6096 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6097 "XOR $dst.hi,$dst.hi" %}
6098 ins_encode %{
6099 Register Rdst = $dst$$Register;
6100 __ movzwl(Rdst, $mem$$Address);
6101 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6102 %}
6103 ins_pipe(ialu_reg_mem);
6104 %}
6105
6106 // Load Integer with 32-bit mask into Long Register
6107 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6108 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6109 effect(KILL cr);
6110
6111 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6112 "XOR $dst.hi,$dst.hi\n\t"
6113 "AND $dst.lo,$mask" %}
6114 ins_encode %{
6115 Register Rdst = $dst$$Register;
6116 __ movl(Rdst, $mem$$Address);
6117 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6118 __ andl(Rdst, $mask$$constant);
6119 %}
6120 ins_pipe(ialu_reg_mem);
6121 %}
6122
6123 // Load Unsigned Integer into Long Register
6124 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6125 match(Set dst (LoadUI2L mem));
6126 effect(KILL cr);
6127
6128 ins_cost(250);
6129 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6130 "XOR $dst.hi,$dst.hi" %}
6131
6132 ins_encode %{
6133 __ movl($dst$$Register, $mem$$Address);
6134 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6135 %}
6136
6137 ins_pipe(ialu_reg_mem);
6138 %}
6139
6140 // Load Long. Cannot clobber address while loading, so restrict address
6141 // register to ESI
6142 instruct loadL(eRegL dst, load_long_memory mem) %{
6143 predicate(!((LoadLNode*)n)->require_atomic_access());
6144 match(Set dst (LoadL mem));
6145
6146 ins_cost(250);
6147 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6148 "MOV $dst.hi,$mem+4" %}
6149
6150 ins_encode %{
6151 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6152 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6153 __ movl($dst$$Register, Amemlo);
6154 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6155 %}
6156
6157 ins_pipe(ialu_reg_long_mem);
6158 %}
6159
6160 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6161 // then store it down to the stack and reload on the int
6162 // side.
6163 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6164 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6165 match(Set dst (LoadL mem));
6166
6167 ins_cost(200);
6168 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6169 "FISTp $dst" %}
6170 ins_encode(enc_loadL_volatile(mem,dst));
6171 ins_pipe( fpu_reg_mem );
6172 %}
6173
6174 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6175 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6176 match(Set dst (LoadL mem));
6177 effect(TEMP tmp);
6178 ins_cost(180);
6179 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6180 "MOVSD $dst,$tmp" %}
6181 ins_encode %{
6182 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6183 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6184 %}
6185 ins_pipe( pipe_slow );
6186 %}
6187
6188 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6189 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6190 match(Set dst (LoadL mem));
6191 effect(TEMP tmp);
6192 ins_cost(160);
6193 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6194 "MOVD $dst.lo,$tmp\n\t"
6195 "PSRLQ $tmp,32\n\t"
6196 "MOVD $dst.hi,$tmp" %}
6197 ins_encode %{
6198 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6199 __ movdl($dst$$Register, $tmp$$XMMRegister);
6200 __ psrlq($tmp$$XMMRegister, 32);
6201 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6202 %}
6203 ins_pipe( pipe_slow );
6204 %}
6205
6206 // Load Range
6207 instruct loadRange(eRegI dst, memory mem) %{
6208 match(Set dst (LoadRange mem));
6209
6210 ins_cost(125);
6211 format %{ "MOV $dst,$mem" %}
6212 opcode(0x8B);
6213 ins_encode( OpcP, RegMem(dst,mem));
6214 ins_pipe( ialu_reg_mem );
6215 %}
6216
6217
6218 // Load Pointer
6219 instruct loadP(eRegP dst, memory mem) %{
6220 match(Set dst (LoadP mem));
6221
6222 ins_cost(125);
6223 format %{ "MOV $dst,$mem" %}
6224 opcode(0x8B);
6225 ins_encode( OpcP, RegMem(dst,mem));
6226 ins_pipe( ialu_reg_mem );
6227 %}
6228
6229 // Load Klass Pointer
6230 instruct loadKlass(eRegP dst, memory mem) %{
6231 match(Set dst (LoadKlass mem));
6232
6233 ins_cost(125);
6234 format %{ "MOV $dst,$mem" %}
6235 opcode(0x8B);
6236 ins_encode( OpcP, RegMem(dst,mem));
6237 ins_pipe( ialu_reg_mem );
6238 %}
6239
6240 // Load Double
6241 instruct loadDPR(regDPR dst, memory mem) %{
6242 predicate(UseSSE<=1);
6243 match(Set dst (LoadD mem));
6244
6245 ins_cost(150);
6246 format %{ "FLD_D ST,$mem\n\t"
6247 "FSTP $dst" %}
6248 opcode(0xDD); /* DD /0 */
6249 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6250 Pop_Reg_DPR(dst) );
6251 ins_pipe( fpu_reg_mem );
6252 %}
6253
6254 // Load Double to XMM
6255 instruct loadD(regD dst, memory mem) %{
6256 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6257 match(Set dst (LoadD mem));
6258 ins_cost(145);
6259 format %{ "MOVSD $dst,$mem" %}
6260 ins_encode %{
6261 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6262 %}
6263 ins_pipe( pipe_slow );
6264 %}
6265
6266 instruct loadD_partial(regD dst, memory mem) %{
6267 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6268 match(Set dst (LoadD mem));
6269 ins_cost(145);
6270 format %{ "MOVLPD $dst,$mem" %}
6271 ins_encode %{
6272 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6273 %}
6274 ins_pipe( pipe_slow );
6275 %}
6276
6277 // Load to XMM register (single-precision floating point)
6278 // MOVSS instruction
6279 instruct loadF(regF dst, memory mem) %{
6280 predicate(UseSSE>=1);
6281 match(Set dst (LoadF mem));
6282 ins_cost(145);
6283 format %{ "MOVSS $dst,$mem" %}
6284 ins_encode %{
6285 __ movflt ($dst$$XMMRegister, $mem$$Address);
6286 %}
6287 ins_pipe( pipe_slow );
6288 %}
6289
6290 // Load Float
6291 instruct loadFPR(regFPR dst, memory mem) %{
6292 predicate(UseSSE==0);
6293 match(Set dst (LoadF mem));
6294
6295 ins_cost(150);
6296 format %{ "FLD_S ST,$mem\n\t"
6297 "FSTP $dst" %}
6298 opcode(0xD9); /* D9 /0 */
6299 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6300 Pop_Reg_FPR(dst) );
6301 ins_pipe( fpu_reg_mem );
6302 %}
6303
6304 // Load Aligned Packed Byte to XMM register
6305 instruct loadA8B(regD dst, memory mem) %{
6306 predicate(UseSSE>=1);
6307 match(Set dst (Load8B mem));
6308 ins_cost(125);
6309 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6310 ins_encode %{
6311 __ movq($dst$$XMMRegister, $mem$$Address);
6312 %}
6313 ins_pipe( pipe_slow );
6314 %}
6315
6316 // Load Aligned Packed Short to XMM register
6317 instruct loadA4S(regD dst, memory mem) %{
6318 predicate(UseSSE>=1);
6319 match(Set dst (Load4S mem));
6320 ins_cost(125);
6321 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6322 ins_encode %{
6323 __ movq($dst$$XMMRegister, $mem$$Address);
6324 %}
6325 ins_pipe( pipe_slow );
6326 %}
6327
6328 // Load Aligned Packed Char to XMM register
6329 instruct loadA4C(regD dst, memory mem) %{
6330 predicate(UseSSE>=1);
6331 match(Set dst (Load4C mem));
6332 ins_cost(125);
6333 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6334 ins_encode %{
6335 __ movq($dst$$XMMRegister, $mem$$Address);
6336 %}
6337 ins_pipe( pipe_slow );
6338 %}
6339
6340 // Load Aligned Packed Integer to XMM register
6341 instruct load2IU(regD dst, memory mem) %{
6342 predicate(UseSSE>=1);
6343 match(Set dst (Load2I mem));
6344 ins_cost(125);
6345 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6346 ins_encode %{
6347 __ movq($dst$$XMMRegister, $mem$$Address);
6348 %}
6349 ins_pipe( pipe_slow );
6350 %}
6351
6352 // Load Aligned Packed Single to XMM
6353 instruct loadA2F(regD dst, memory mem) %{
6354 predicate(UseSSE>=1);
6355 match(Set dst (Load2F mem));
6356 ins_cost(145);
6357 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6358 ins_encode %{
6359 __ movq($dst$$XMMRegister, $mem$$Address);
6360 %}
6361 ins_pipe( pipe_slow );
6362 %}
6363
6364 // Load Effective Address
6365 instruct leaP8(eRegP dst, indOffset8 mem) %{
6366 match(Set dst mem);
6367
6368 ins_cost(110);
6369 format %{ "LEA $dst,$mem" %}
6370 opcode(0x8D);
6371 ins_encode( OpcP, RegMem(dst,mem));
6372 ins_pipe( ialu_reg_reg_fat );
6373 %}
6374
6375 instruct leaP32(eRegP dst, indOffset32 mem) %{
6376 match(Set dst mem);
6377
6378 ins_cost(110);
6379 format %{ "LEA $dst,$mem" %}
6380 opcode(0x8D);
6381 ins_encode( OpcP, RegMem(dst,mem));
6382 ins_pipe( ialu_reg_reg_fat );
6383 %}
6384
6385 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6386 match(Set dst mem);
6387
6388 ins_cost(110);
6389 format %{ "LEA $dst,$mem" %}
6390 opcode(0x8D);
6391 ins_encode( OpcP, RegMem(dst,mem));
6392 ins_pipe( ialu_reg_reg_fat );
6393 %}
6394
6395 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6396 match(Set dst mem);
6397
6398 ins_cost(110);
6399 format %{ "LEA $dst,$mem" %}
6400 opcode(0x8D);
6401 ins_encode( OpcP, RegMem(dst,mem));
6402 ins_pipe( ialu_reg_reg_fat );
6403 %}
6404
6405 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6406 match(Set dst mem);
6407
6408 ins_cost(110);
6409 format %{ "LEA $dst,$mem" %}
6410 opcode(0x8D);
6411 ins_encode( OpcP, RegMem(dst,mem));
6412 ins_pipe( ialu_reg_reg_fat );
6413 %}
6414
6415 // Load Constant
6416 instruct loadConI(eRegI dst, immI src) %{
6417 match(Set dst src);
6418
6419 format %{ "MOV $dst,$src" %}
6420 ins_encode( LdImmI(dst, src) );
6421 ins_pipe( ialu_reg_fat );
6422 %}
6423
6424 // Load Constant zero
6425 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6426 match(Set dst src);
6427 effect(KILL cr);
6428
6429 ins_cost(50);
6430 format %{ "XOR $dst,$dst" %}
6431 opcode(0x33); /* + rd */
6432 ins_encode( OpcP, RegReg( dst, dst ) );
6433 ins_pipe( ialu_reg );
6434 %}
6435
6436 instruct loadConP(eRegP dst, immP src) %{
6437 match(Set dst src);
6438
6439 format %{ "MOV $dst,$src" %}
6440 opcode(0xB8); /* + rd */
6441 ins_encode( LdImmP(dst, src) );
6442 ins_pipe( ialu_reg_fat );
6443 %}
6444
6445 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6446 match(Set dst src);
6447 effect(KILL cr);
6448 ins_cost(200);
6449 format %{ "MOV $dst.lo,$src.lo\n\t"
6450 "MOV $dst.hi,$src.hi" %}
6451 opcode(0xB8);
6452 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6453 ins_pipe( ialu_reg_long_fat );
6454 %}
6455
6456 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6457 match(Set dst src);
6458 effect(KILL cr);
6459 ins_cost(150);
6460 format %{ "XOR $dst.lo,$dst.lo\n\t"
6461 "XOR $dst.hi,$dst.hi" %}
6462 opcode(0x33,0x33);
6463 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6464 ins_pipe( ialu_reg_long );
6465 %}
6466
6467 // The instruction usage is guarded by predicate in operand immFPR().
6468 instruct loadConFPR(regFPR dst, immFPR con) %{
6469 match(Set dst con);
6470 ins_cost(125);
6471 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6472 "FSTP $dst" %}
6473 ins_encode %{
6474 __ fld_s($constantaddress($con));
6475 __ fstp_d($dst$$reg);
6476 %}
6477 ins_pipe(fpu_reg_con);
6478 %}
6479
6480 // The instruction usage is guarded by predicate in operand immFPR0().
6481 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6482 match(Set dst con);
6483 ins_cost(125);
6484 format %{ "FLDZ ST\n\t"
6485 "FSTP $dst" %}
6486 ins_encode %{
6487 __ fldz();
6488 __ fstp_d($dst$$reg);
6489 %}
6490 ins_pipe(fpu_reg_con);
6491 %}
6492
6493 // The instruction usage is guarded by predicate in operand immFPR1().
6494 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6495 match(Set dst con);
6496 ins_cost(125);
6497 format %{ "FLD1 ST\n\t"
6498 "FSTP $dst" %}
6499 ins_encode %{
6500 __ fld1();
6501 __ fstp_d($dst$$reg);
6502 %}
6503 ins_pipe(fpu_reg_con);
6504 %}
6505
6506 // The instruction usage is guarded by predicate in operand immF().
6507 instruct loadConF(regF dst, immF con) %{
6508 match(Set dst con);
6509 ins_cost(125);
6510 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6511 ins_encode %{
6512 __ movflt($dst$$XMMRegister, $constantaddress($con));
6513 %}
6514 ins_pipe(pipe_slow);
6515 %}
6516
6517 // The instruction usage is guarded by predicate in operand immF0().
6518 instruct loadConF0(regF dst, immF0 src) %{
6519 match(Set dst src);
6520 ins_cost(100);
6521 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6522 ins_encode %{
6523 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6524 %}
6525 ins_pipe(pipe_slow);
6526 %}
6527
6528 // The instruction usage is guarded by predicate in operand immDPR().
6529 instruct loadConDPR(regDPR dst, immDPR con) %{
6530 match(Set dst con);
6531 ins_cost(125);
6532
6533 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6534 "FSTP $dst" %}
6535 ins_encode %{
6536 __ fld_d($constantaddress($con));
6537 __ fstp_d($dst$$reg);
6538 %}
6539 ins_pipe(fpu_reg_con);
6540 %}
6541
6542 // The instruction usage is guarded by predicate in operand immDPR0().
6543 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6544 match(Set dst con);
6545 ins_cost(125);
6546
6547 format %{ "FLDZ ST\n\t"
6548 "FSTP $dst" %}
6549 ins_encode %{
6550 __ fldz();
6551 __ fstp_d($dst$$reg);
6552 %}
6553 ins_pipe(fpu_reg_con);
6554 %}
6555
6556 // The instruction usage is guarded by predicate in operand immDPR1().
6557 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6558 match(Set dst con);
6559 ins_cost(125);
6560
6561 format %{ "FLD1 ST\n\t"
6562 "FSTP $dst" %}
6563 ins_encode %{
6564 __ fld1();
6565 __ fstp_d($dst$$reg);
6566 %}
6567 ins_pipe(fpu_reg_con);
6568 %}
6569
6570 // The instruction usage is guarded by predicate in operand immD().
6571 instruct loadConD(regD dst, immD con) %{
6572 match(Set dst con);
6573 ins_cost(125);
6574 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6575 ins_encode %{
6576 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6577 %}
6578 ins_pipe(pipe_slow);
6579 %}
6580
6581 // The instruction usage is guarded by predicate in operand immD0().
6582 instruct loadConD0(regD dst, immD0 src) %{
6583 match(Set dst src);
6584 ins_cost(100);
6585 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6586 ins_encode %{
6587 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6588 %}
6589 ins_pipe( pipe_slow );
6590 %}
6591
6592 // Load Stack Slot
6593 instruct loadSSI(eRegI dst, stackSlotI src) %{
6594 match(Set dst src);
6595 ins_cost(125);
6596
6597 format %{ "MOV $dst,$src" %}
6598 opcode(0x8B);
6599 ins_encode( OpcP, RegMem(dst,src));
6600 ins_pipe( ialu_reg_mem );
6601 %}
6602
6603 instruct loadSSL(eRegL dst, stackSlotL src) %{
6604 match(Set dst src);
6605
6606 ins_cost(200);
6607 format %{ "MOV $dst,$src.lo\n\t"
6608 "MOV $dst+4,$src.hi" %}
6609 opcode(0x8B, 0x8B);
6610 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6611 ins_pipe( ialu_mem_long_reg );
6612 %}
6613
6614 // Load Stack Slot
6615 instruct loadSSP(eRegP dst, stackSlotP src) %{
6616 match(Set dst src);
6617 ins_cost(125);
6618
6619 format %{ "MOV $dst,$src" %}
6620 opcode(0x8B);
6621 ins_encode( OpcP, RegMem(dst,src));
6622 ins_pipe( ialu_reg_mem );
6623 %}
6624
6625 // Load Stack Slot
6626 instruct loadSSF(regFPR dst, stackSlotF src) %{
6627 match(Set dst src);
6628 ins_cost(125);
6629
6630 format %{ "FLD_S $src\n\t"
6631 "FSTP $dst" %}
6632 opcode(0xD9); /* D9 /0, FLD m32real */
6633 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6634 Pop_Reg_FPR(dst) );
6635 ins_pipe( fpu_reg_mem );
6636 %}
6637
6638 // Load Stack Slot
6639 instruct loadSSD(regDPR dst, stackSlotD src) %{
6640 match(Set dst src);
6641 ins_cost(125);
6642
6643 format %{ "FLD_D $src\n\t"
6644 "FSTP $dst" %}
6645 opcode(0xDD); /* DD /0, FLD m64real */
6646 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6647 Pop_Reg_DPR(dst) );
6648 ins_pipe( fpu_reg_mem );
6649 %}
6650
6651 // Prefetch instructions.
6652 // Must be safe to execute with invalid address (cannot fault).
6653
6654 instruct prefetchr0( memory mem ) %{
6655 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6656 match(PrefetchRead mem);
6657 ins_cost(0);
6658 size(0);
6659 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6660 ins_encode();
6661 ins_pipe(empty);
6662 %}
6663
6664 instruct prefetchr( memory mem ) %{
6665 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6666 match(PrefetchRead mem);
6667 ins_cost(100);
6668
6669 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6670 ins_encode %{
6671 __ prefetchr($mem$$Address);
6672 %}
6673 ins_pipe(ialu_mem);
6674 %}
6675
6676 instruct prefetchrNTA( memory mem ) %{
6677 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6678 match(PrefetchRead mem);
6679 ins_cost(100);
6680
6681 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6682 ins_encode %{
6683 __ prefetchnta($mem$$Address);
6684 %}
6685 ins_pipe(ialu_mem);
6686 %}
6687
6688 instruct prefetchrT0( memory mem ) %{
6689 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6690 match(PrefetchRead mem);
6691 ins_cost(100);
6692
6693 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6694 ins_encode %{
6695 __ prefetcht0($mem$$Address);
6696 %}
6697 ins_pipe(ialu_mem);
6698 %}
6699
6700 instruct prefetchrT2( memory mem ) %{
6701 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6702 match(PrefetchRead mem);
6703 ins_cost(100);
6704
6705 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6706 ins_encode %{
6707 __ prefetcht2($mem$$Address);
6708 %}
6709 ins_pipe(ialu_mem);
6710 %}
6711
6712 instruct prefetchw0( memory mem ) %{
6713 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6714 match(PrefetchWrite mem);
6715 ins_cost(0);
6716 size(0);
6717 format %{ "Prefetch (non-SSE is empty encoding)" %}
6718 ins_encode();
6719 ins_pipe(empty);
6720 %}
6721
6722 instruct prefetchw( memory mem ) %{
6723 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6724 match( PrefetchWrite mem );
6725 ins_cost(100);
6726
6727 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6728 ins_encode %{
6729 __ prefetchw($mem$$Address);
6730 %}
6731 ins_pipe(ialu_mem);
6732 %}
6733
6734 instruct prefetchwNTA( memory mem ) %{
6735 predicate(UseSSE>=1);
6736 match(PrefetchWrite mem);
6737 ins_cost(100);
6738
6739 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6740 ins_encode %{
6741 __ prefetchnta($mem$$Address);
6742 %}
6743 ins_pipe(ialu_mem);
6744 %}
6745
6746 // Prefetch instructions for allocation.
6747
6748 instruct prefetchAlloc0( memory mem ) %{
6749 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6750 match(PrefetchAllocation mem);
6751 ins_cost(0);
6752 size(0);
6753 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6754 ins_encode();
6755 ins_pipe(empty);
6756 %}
6757
6758 instruct prefetchAlloc( memory mem ) %{
6759 predicate(AllocatePrefetchInstr==3);
6760 match( PrefetchAllocation mem );
6761 ins_cost(100);
6762
6763 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6764 ins_encode %{
6765 __ prefetchw($mem$$Address);
6766 %}
6767 ins_pipe(ialu_mem);
6768 %}
6769
6770 instruct prefetchAllocNTA( memory mem ) %{
6771 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6772 match(PrefetchAllocation mem);
6773 ins_cost(100);
6774
6775 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6776 ins_encode %{
6777 __ prefetchnta($mem$$Address);
6778 %}
6779 ins_pipe(ialu_mem);
6780 %}
6781
6782 instruct prefetchAllocT0( memory mem ) %{
6783 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6784 match(PrefetchAllocation mem);
6785 ins_cost(100);
6786
6787 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6788 ins_encode %{
6789 __ prefetcht0($mem$$Address);
6790 %}
6791 ins_pipe(ialu_mem);
6792 %}
6793
6794 instruct prefetchAllocT2( memory mem ) %{
6795 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6796 match(PrefetchAllocation mem);
6797 ins_cost(100);
6798
6799 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6800 ins_encode %{
6801 __ prefetcht2($mem$$Address);
6802 %}
6803 ins_pipe(ialu_mem);
6804 %}
6805
6806 //----------Store Instructions-------------------------------------------------
6807
6808 // Store Byte
6809 instruct storeB(memory mem, xRegI src) %{
6810 match(Set mem (StoreB mem src));
6811
6812 ins_cost(125);
6813 format %{ "MOV8 $mem,$src" %}
6814 opcode(0x88);
6815 ins_encode( OpcP, RegMem( src, mem ) );
6816 ins_pipe( ialu_mem_reg );
6817 %}
6818
6819 // Store Char/Short
6820 instruct storeC(memory mem, eRegI src) %{
6821 match(Set mem (StoreC mem src));
6822
6823 ins_cost(125);
6824 format %{ "MOV16 $mem,$src" %}
6825 opcode(0x89, 0x66);
6826 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6827 ins_pipe( ialu_mem_reg );
6828 %}
6829
6830 // Store Integer
6831 instruct storeI(memory mem, eRegI src) %{
6832 match(Set mem (StoreI mem src));
6833
6834 ins_cost(125);
6835 format %{ "MOV $mem,$src" %}
6836 opcode(0x89);
6837 ins_encode( OpcP, RegMem( src, mem ) );
6838 ins_pipe( ialu_mem_reg );
6839 %}
6840
6841 // Store Long
6842 instruct storeL(long_memory mem, eRegL src) %{
6843 predicate(!((StoreLNode*)n)->require_atomic_access());
6844 match(Set mem (StoreL mem src));
6845
6846 ins_cost(200);
6847 format %{ "MOV $mem,$src.lo\n\t"
6848 "MOV $mem+4,$src.hi" %}
6849 opcode(0x89, 0x89);
6850 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6851 ins_pipe( ialu_mem_long_reg );
6852 %}
6853
6854 // Store Long to Integer
6855 instruct storeL2I(memory mem, eRegL src) %{
6856 match(Set mem (StoreI mem (ConvL2I src)));
6857
6858 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6859 ins_encode %{
6860 __ movl($mem$$Address, $src$$Register);
6861 %}
6862 ins_pipe(ialu_mem_reg);
6863 %}
6864
6865 // Volatile Store Long. Must be atomic, so move it into
6866 // the FP TOS and then do a 64-bit FIST. Has to probe the
6867 // target address before the store (for null-ptr checks)
6868 // so the memory operand is used twice in the encoding.
6869 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6870 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6871 match(Set mem (StoreL mem src));
6872 effect( KILL cr );
6873 ins_cost(400);
6874 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6875 "FILD $src\n\t"
6876 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6877 opcode(0x3B);
6878 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6879 ins_pipe( fpu_reg_mem );
6880 %}
6881
6882 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6883 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6884 match(Set mem (StoreL mem src));
6885 effect( TEMP tmp, KILL cr );
6886 ins_cost(380);
6887 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6888 "MOVSD $tmp,$src\n\t"
6889 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6890 ins_encode %{
6891 __ cmpl(rax, $mem$$Address);
6892 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6893 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6894 %}
6895 ins_pipe( pipe_slow );
6896 %}
6897
6898 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6899 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6900 match(Set mem (StoreL mem src));
6901 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6902 ins_cost(360);
6903 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6904 "MOVD $tmp,$src.lo\n\t"
6905 "MOVD $tmp2,$src.hi\n\t"
6906 "PUNPCKLDQ $tmp,$tmp2\n\t"
6907 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6908 ins_encode %{
6909 __ cmpl(rax, $mem$$Address);
6910 __ movdl($tmp$$XMMRegister, $src$$Register);
6911 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6912 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6913 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6914 %}
6915 ins_pipe( pipe_slow );
6916 %}
6917
6918 // Store Pointer; for storing unknown oops and raw pointers
6919 instruct storeP(memory mem, anyRegP src) %{
6920 match(Set mem (StoreP mem src));
6921
6922 ins_cost(125);
6923 format %{ "MOV $mem,$src" %}
6924 opcode(0x89);
6925 ins_encode( OpcP, RegMem( src, mem ) );
6926 ins_pipe( ialu_mem_reg );
6927 %}
6928
6929 // Store Integer Immediate
6930 instruct storeImmI(memory mem, immI src) %{
6931 match(Set mem (StoreI mem src));
6932
6933 ins_cost(150);
6934 format %{ "MOV $mem,$src" %}
6935 opcode(0xC7); /* C7 /0 */
6936 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6937 ins_pipe( ialu_mem_imm );
6938 %}
6939
6940 // Store Short/Char Immediate
6941 instruct storeImmI16(memory mem, immI16 src) %{
6942 predicate(UseStoreImmI16);
6943 match(Set mem (StoreC mem src));
6944
6945 ins_cost(150);
6946 format %{ "MOV16 $mem,$src" %}
6947 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6948 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6949 ins_pipe( ialu_mem_imm );
6950 %}
6951
6952 // Store Pointer Immediate; null pointers or constant oops that do not
6953 // need card-mark barriers.
6954 instruct storeImmP(memory mem, immP src) %{
6955 match(Set mem (StoreP mem src));
6956
6957 ins_cost(150);
6958 format %{ "MOV $mem,$src" %}
6959 opcode(0xC7); /* C7 /0 */
6960 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6961 ins_pipe( ialu_mem_imm );
6962 %}
6963
6964 // Store Byte Immediate
6965 instruct storeImmB(memory mem, immI8 src) %{
6966 match(Set mem (StoreB mem src));
6967
6968 ins_cost(150);
6969 format %{ "MOV8 $mem,$src" %}
6970 opcode(0xC6); /* C6 /0 */
6971 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6972 ins_pipe( ialu_mem_imm );
6973 %}
6974
6975 // Store Aligned Packed Byte XMM register to memory
6976 instruct storeA8B(memory mem, regD src) %{
6977 predicate(UseSSE>=1);
6978 match(Set mem (Store8B mem src));
6979 ins_cost(145);
6980 format %{ "MOVQ $mem,$src\t! packed8B" %}
6981 ins_encode %{
6982 __ movq($mem$$Address, $src$$XMMRegister);
6983 %}
6984 ins_pipe( pipe_slow );
6985 %}
6986
6987 // Store Aligned Packed Char/Short XMM register to memory
6988 instruct storeA4C(memory mem, regD src) %{
6989 predicate(UseSSE>=1);
6990 match(Set mem (Store4C mem src));
6991 ins_cost(145);
6992 format %{ "MOVQ $mem,$src\t! packed4C" %}
6993 ins_encode %{
6994 __ movq($mem$$Address, $src$$XMMRegister);
6995 %}
6996 ins_pipe( pipe_slow );
6997 %}
6998
6999 // Store Aligned Packed Integer XMM register to memory
7000 instruct storeA2I(memory mem, regD src) %{
7001 predicate(UseSSE>=1);
7002 match(Set mem (Store2I mem src));
7003 ins_cost(145);
7004 format %{ "MOVQ $mem,$src\t! packed2I" %}
7005 ins_encode %{
7006 __ movq($mem$$Address, $src$$XMMRegister);
7007 %}
7008 ins_pipe( pipe_slow );
7009 %}
7010
7011 // Store CMS card-mark Immediate
7012 instruct storeImmCM(memory mem, immI8 src) %{
7013 match(Set mem (StoreCM mem src));
7014
7015 ins_cost(150);
7016 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7017 opcode(0xC6); /* C6 /0 */
7018 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7019 ins_pipe( ialu_mem_imm );
7020 %}
7021
7022 // Store Double
7023 instruct storeDPR( memory mem, regDPR1 src) %{
7024 predicate(UseSSE<=1);
7025 match(Set mem (StoreD mem src));
7026
7027 ins_cost(100);
7028 format %{ "FST_D $mem,$src" %}
7029 opcode(0xDD); /* DD /2 */
7030 ins_encode( enc_FPR_store(mem,src) );
7031 ins_pipe( fpu_mem_reg );
7032 %}
7033
7034 // Store double does rounding on x86
7035 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7036 predicate(UseSSE<=1);
7037 match(Set mem (StoreD mem (RoundDouble src)));
7038
7039 ins_cost(100);
7040 format %{ "FST_D $mem,$src\t# round" %}
7041 opcode(0xDD); /* DD /2 */
7042 ins_encode( enc_FPR_store(mem,src) );
7043 ins_pipe( fpu_mem_reg );
7044 %}
7045
7046 // Store XMM register to memory (double-precision floating points)
7047 // MOVSD instruction
7048 instruct storeD(memory mem, regD src) %{
7049 predicate(UseSSE>=2);
7050 match(Set mem (StoreD mem src));
7051 ins_cost(95);
7052 format %{ "MOVSD $mem,$src" %}
7053 ins_encode %{
7054 __ movdbl($mem$$Address, $src$$XMMRegister);
7055 %}
7056 ins_pipe( pipe_slow );
7057 %}
7058
7059 // Store XMM register to memory (single-precision floating point)
7060 // MOVSS instruction
7061 instruct storeF(memory mem, regF src) %{
7062 predicate(UseSSE>=1);
7063 match(Set mem (StoreF mem src));
7064 ins_cost(95);
7065 format %{ "MOVSS $mem,$src" %}
7066 ins_encode %{
7067 __ movflt($mem$$Address, $src$$XMMRegister);
7068 %}
7069 ins_pipe( pipe_slow );
7070 %}
7071
7072 // Store Aligned Packed Single Float XMM register to memory
7073 instruct storeA2F(memory mem, regD src) %{
7074 predicate(UseSSE>=1);
7075 match(Set mem (Store2F mem src));
7076 ins_cost(145);
7077 format %{ "MOVQ $mem,$src\t! packed2F" %}
7078 ins_encode %{
7079 __ movq($mem$$Address, $src$$XMMRegister);
7080 %}
7081 ins_pipe( pipe_slow );
7082 %}
7083
7084 // Store Float
7085 instruct storeFPR( memory mem, regFPR1 src) %{
7086 predicate(UseSSE==0);
7087 match(Set mem (StoreF mem src));
7088
7089 ins_cost(100);
7090 format %{ "FST_S $mem,$src" %}
7091 opcode(0xD9); /* D9 /2 */
7092 ins_encode( enc_FPR_store(mem,src) );
7093 ins_pipe( fpu_mem_reg );
7094 %}
7095
7096 // Store Float does rounding on x86
7097 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7098 predicate(UseSSE==0);
7099 match(Set mem (StoreF mem (RoundFloat src)));
7100
7101 ins_cost(100);
7102 format %{ "FST_S $mem,$src\t# round" %}
7103 opcode(0xD9); /* D9 /2 */
7104 ins_encode( enc_FPR_store(mem,src) );
7105 ins_pipe( fpu_mem_reg );
7106 %}
7107
7108 // Store Float does rounding on x86
7109 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7110 predicate(UseSSE<=1);
7111 match(Set mem (StoreF mem (ConvD2F src)));
7112
7113 ins_cost(100);
7114 format %{ "FST_S $mem,$src\t# D-round" %}
7115 opcode(0xD9); /* D9 /2 */
7116 ins_encode( enc_FPR_store(mem,src) );
7117 ins_pipe( fpu_mem_reg );
7118 %}
7119
7120 // Store immediate Float value (it is faster than store from FPU register)
7121 // The instruction usage is guarded by predicate in operand immFPR().
7122 instruct storeFPR_imm( memory mem, immFPR src) %{
7123 match(Set mem (StoreF mem src));
7124
7125 ins_cost(50);
7126 format %{ "MOV $mem,$src\t# store float" %}
7127 opcode(0xC7); /* C7 /0 */
7128 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7129 ins_pipe( ialu_mem_imm );
7130 %}
7131
7132 // Store immediate Float value (it is faster than store from XMM register)
7133 // The instruction usage is guarded by predicate in operand immF().
7134 instruct storeF_imm( memory mem, immF src) %{
7135 match(Set mem (StoreF mem src));
7136
7137 ins_cost(50);
7138 format %{ "MOV $mem,$src\t# store float" %}
7139 opcode(0xC7); /* C7 /0 */
7140 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7141 ins_pipe( ialu_mem_imm );
7142 %}
7143
7144 // Store Integer to stack slot
7145 instruct storeSSI(stackSlotI dst, eRegI src) %{
7146 match(Set dst src);
7147
7148 ins_cost(100);
7149 format %{ "MOV $dst,$src" %}
7150 opcode(0x89);
7151 ins_encode( OpcPRegSS( dst, src ) );
7152 ins_pipe( ialu_mem_reg );
7153 %}
7154
7155 // Store Integer to stack slot
7156 instruct storeSSP(stackSlotP dst, eRegP src) %{
7157 match(Set dst src);
7158
7159 ins_cost(100);
7160 format %{ "MOV $dst,$src" %}
7161 opcode(0x89);
7162 ins_encode( OpcPRegSS( dst, src ) );
7163 ins_pipe( ialu_mem_reg );
7164 %}
7165
7166 // Store Long to stack slot
7167 instruct storeSSL(stackSlotL dst, eRegL src) %{
7168 match(Set dst src);
7169
7170 ins_cost(200);
7171 format %{ "MOV $dst,$src.lo\n\t"
7172 "MOV $dst+4,$src.hi" %}
7173 opcode(0x89, 0x89);
7174 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7175 ins_pipe( ialu_mem_long_reg );
7176 %}
7177
7178 //----------MemBar Instructions-----------------------------------------------
7179 // Memory barrier flavors
7180
7181 instruct membar_acquire() %{
7182 match(MemBarAcquire);
7183 ins_cost(400);
7184
7185 size(0);
7186 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7187 ins_encode();
7188 ins_pipe(empty);
7189 %}
7190
7191 instruct membar_acquire_lock() %{
7192 match(MemBarAcquireLock);
7193 ins_cost(0);
7194
7195 size(0);
7196 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7197 ins_encode( );
7198 ins_pipe(empty);
7199 %}
7200
7201 instruct membar_release() %{
7202 match(MemBarRelease);
7203 ins_cost(400);
7204
7205 size(0);
7206 format %{ "MEMBAR-release ! (empty encoding)" %}
7207 ins_encode( );
7208 ins_pipe(empty);
7209 %}
7210
7211 instruct membar_release_lock() %{
7212 match(MemBarReleaseLock);
7213 ins_cost(0);
7214
7215 size(0);
7216 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7217 ins_encode( );
7218 ins_pipe(empty);
7219 %}
7220
7221 instruct membar_volatile(eFlagsReg cr) %{
7222 match(MemBarVolatile);
7223 effect(KILL cr);
7224 ins_cost(400);
7225
7226 format %{
7227 $$template
7228 if (os::is_MP()) {
7229 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7230 } else {
7231 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7232 }
7233 %}
7234 ins_encode %{
7235 __ membar(Assembler::StoreLoad);
7236 %}
7237 ins_pipe(pipe_slow);
7238 %}
7239
7240 instruct unnecessary_membar_volatile() %{
7241 match(MemBarVolatile);
7242 predicate(Matcher::post_store_load_barrier(n));
7243 ins_cost(0);
7244
7245 size(0);
7246 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7247 ins_encode( );
7248 ins_pipe(empty);
7249 %}
7250
7251 instruct membar_storestore() %{
7252 match(MemBarStoreStore);
7253 ins_cost(0);
7254
7255 size(0);
7256 format %{ "MEMBAR-storestore (empty encoding)" %}
7257 ins_encode( );
7258 ins_pipe(empty);
7259 %}
7260
7261 //----------Move Instructions--------------------------------------------------
7262 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7263 match(Set dst (CastX2P src));
7264 format %{ "# X2P $dst, $src" %}
7265 ins_encode( /*empty encoding*/ );
7266 ins_cost(0);
7267 ins_pipe(empty);
7268 %}
7269
7270 instruct castP2X(eRegI dst, eRegP src ) %{
7271 match(Set dst (CastP2X src));
7272 ins_cost(50);
7273 format %{ "MOV $dst, $src\t# CastP2X" %}
7274 ins_encode( enc_Copy( dst, src) );
7275 ins_pipe( ialu_reg_reg );
7276 %}
7277
7278 //----------Conditional Move---------------------------------------------------
7279 // Conditional move
7280 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7281 predicate(!VM_Version::supports_cmov() );
7282 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7283 ins_cost(200);
7284 format %{ "J$cop,us skip\t# signed cmove\n\t"
7285 "MOV $dst,$src\n"
7286 "skip:" %}
7287 ins_encode %{
7288 Label Lskip;
7289 // Invert sense of branch from sense of CMOV
7290 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7291 __ movl($dst$$Register, $src$$Register);
7292 __ bind(Lskip);
7293 %}
7294 ins_pipe( pipe_cmov_reg );
7295 %}
7296
7297 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7298 predicate(!VM_Version::supports_cmov() );
7299 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7300 ins_cost(200);
7301 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7302 "MOV $dst,$src\n"
7303 "skip:" %}
7304 ins_encode %{
7305 Label Lskip;
7306 // Invert sense of branch from sense of CMOV
7307 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7308 __ movl($dst$$Register, $src$$Register);
7309 __ bind(Lskip);
7310 %}
7311 ins_pipe( pipe_cmov_reg );
7312 %}
7313
7314 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7315 predicate(VM_Version::supports_cmov() );
7316 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7317 ins_cost(200);
7318 format %{ "CMOV$cop $dst,$src" %}
7319 opcode(0x0F,0x40);
7320 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7321 ins_pipe( pipe_cmov_reg );
7322 %}
7323
7324 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7325 predicate(VM_Version::supports_cmov() );
7326 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7327 ins_cost(200);
7328 format %{ "CMOV$cop $dst,$src" %}
7329 opcode(0x0F,0x40);
7330 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7331 ins_pipe( pipe_cmov_reg );
7332 %}
7333
7334 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7335 predicate(VM_Version::supports_cmov() );
7336 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7337 ins_cost(200);
7338 expand %{
7339 cmovI_regU(cop, cr, dst, src);
7340 %}
7341 %}
7342
7343 // Conditional move
7344 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7345 predicate(VM_Version::supports_cmov() );
7346 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7347 ins_cost(250);
7348 format %{ "CMOV$cop $dst,$src" %}
7349 opcode(0x0F,0x40);
7350 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7351 ins_pipe( pipe_cmov_mem );
7352 %}
7353
7354 // Conditional move
7355 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7356 predicate(VM_Version::supports_cmov() );
7357 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7358 ins_cost(250);
7359 format %{ "CMOV$cop $dst,$src" %}
7360 opcode(0x0F,0x40);
7361 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7362 ins_pipe( pipe_cmov_mem );
7363 %}
7364
7365 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7366 predicate(VM_Version::supports_cmov() );
7367 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7368 ins_cost(250);
7369 expand %{
7370 cmovI_memU(cop, cr, dst, src);
7371 %}
7372 %}
7373
7374 // Conditional move
7375 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7376 predicate(VM_Version::supports_cmov() );
7377 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7378 ins_cost(200);
7379 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7380 opcode(0x0F,0x40);
7381 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7382 ins_pipe( pipe_cmov_reg );
7383 %}
7384
7385 // Conditional move (non-P6 version)
7386 // Note: a CMoveP is generated for stubs and native wrappers
7387 // regardless of whether we are on a P6, so we
7388 // emulate a cmov here
7389 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7390 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7391 ins_cost(300);
7392 format %{ "Jn$cop skip\n\t"
7393 "MOV $dst,$src\t# pointer\n"
7394 "skip:" %}
7395 opcode(0x8b);
7396 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7397 ins_pipe( pipe_cmov_reg );
7398 %}
7399
7400 // Conditional move
7401 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7402 predicate(VM_Version::supports_cmov() );
7403 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7404 ins_cost(200);
7405 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7406 opcode(0x0F,0x40);
7407 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7408 ins_pipe( pipe_cmov_reg );
7409 %}
7410
7411 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7412 predicate(VM_Version::supports_cmov() );
7413 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7414 ins_cost(200);
7415 expand %{
7416 cmovP_regU(cop, cr, dst, src);
7417 %}
7418 %}
7419
7420 // DISABLED: Requires the ADLC to emit a bottom_type call that
7421 // correctly meets the two pointer arguments; one is an incoming
7422 // register but the other is a memory operand. ALSO appears to
7423 // be buggy with implicit null checks.
7424 //
7425 //// Conditional move
7426 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7427 // predicate(VM_Version::supports_cmov() );
7428 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7429 // ins_cost(250);
7430 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7431 // opcode(0x0F,0x40);
7432 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7433 // ins_pipe( pipe_cmov_mem );
7434 //%}
7435 //
7436 //// Conditional move
7437 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7438 // predicate(VM_Version::supports_cmov() );
7439 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7440 // ins_cost(250);
7441 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7442 // opcode(0x0F,0x40);
7443 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7444 // ins_pipe( pipe_cmov_mem );
7445 //%}
7446
7447 // Conditional move
7448 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7449 predicate(UseSSE<=1);
7450 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7451 ins_cost(200);
7452 format %{ "FCMOV$cop $dst,$src\t# double" %}
7453 opcode(0xDA);
7454 ins_encode( enc_cmov_dpr(cop,src) );
7455 ins_pipe( pipe_cmovDPR_reg );
7456 %}
7457
7458 // Conditional move
7459 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7460 predicate(UseSSE==0);
7461 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7462 ins_cost(200);
7463 format %{ "FCMOV$cop $dst,$src\t# float" %}
7464 opcode(0xDA);
7465 ins_encode( enc_cmov_dpr(cop,src) );
7466 ins_pipe( pipe_cmovDPR_reg );
7467 %}
7468
7469 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7470 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7471 predicate(UseSSE<=1);
7472 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7473 ins_cost(200);
7474 format %{ "Jn$cop skip\n\t"
7475 "MOV $dst,$src\t# double\n"
7476 "skip:" %}
7477 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7478 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7479 ins_pipe( pipe_cmovDPR_reg );
7480 %}
7481
7482 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7483 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7484 predicate(UseSSE==0);
7485 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7486 ins_cost(200);
7487 format %{ "Jn$cop skip\n\t"
7488 "MOV $dst,$src\t# float\n"
7489 "skip:" %}
7490 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7491 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7492 ins_pipe( pipe_cmovDPR_reg );
7493 %}
7494
7495 // No CMOVE with SSE/SSE2
7496 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7497 predicate (UseSSE>=1);
7498 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7499 ins_cost(200);
7500 format %{ "Jn$cop skip\n\t"
7501 "MOVSS $dst,$src\t# float\n"
7502 "skip:" %}
7503 ins_encode %{
7504 Label skip;
7505 // Invert sense of branch from sense of CMOV
7506 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7507 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7508 __ bind(skip);
7509 %}
7510 ins_pipe( pipe_slow );
7511 %}
7512
7513 // No CMOVE with SSE/SSE2
7514 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7515 predicate (UseSSE>=2);
7516 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7517 ins_cost(200);
7518 format %{ "Jn$cop skip\n\t"
7519 "MOVSD $dst,$src\t# float\n"
7520 "skip:" %}
7521 ins_encode %{
7522 Label skip;
7523 // Invert sense of branch from sense of CMOV
7524 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7525 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7526 __ bind(skip);
7527 %}
7528 ins_pipe( pipe_slow );
7529 %}
7530
7531 // unsigned version
7532 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7533 predicate (UseSSE>=1);
7534 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7535 ins_cost(200);
7536 format %{ "Jn$cop skip\n\t"
7537 "MOVSS $dst,$src\t# float\n"
7538 "skip:" %}
7539 ins_encode %{
7540 Label skip;
7541 // Invert sense of branch from sense of CMOV
7542 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7543 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7544 __ bind(skip);
7545 %}
7546 ins_pipe( pipe_slow );
7547 %}
7548
7549 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7550 predicate (UseSSE>=1);
7551 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7552 ins_cost(200);
7553 expand %{
7554 fcmovF_regU(cop, cr, dst, src);
7555 %}
7556 %}
7557
7558 // unsigned version
7559 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7560 predicate (UseSSE>=2);
7561 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7562 ins_cost(200);
7563 format %{ "Jn$cop skip\n\t"
7564 "MOVSD $dst,$src\t# float\n"
7565 "skip:" %}
7566 ins_encode %{
7567 Label skip;
7568 // Invert sense of branch from sense of CMOV
7569 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7570 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7571 __ bind(skip);
7572 %}
7573 ins_pipe( pipe_slow );
7574 %}
7575
7576 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7577 predicate (UseSSE>=2);
7578 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7579 ins_cost(200);
7580 expand %{
7581 fcmovD_regU(cop, cr, dst, src);
7582 %}
7583 %}
7584
7585 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7586 predicate(VM_Version::supports_cmov() );
7587 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7588 ins_cost(200);
7589 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7590 "CMOV$cop $dst.hi,$src.hi" %}
7591 opcode(0x0F,0x40);
7592 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7593 ins_pipe( pipe_cmov_reg_long );
7594 %}
7595
7596 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7597 predicate(VM_Version::supports_cmov() );
7598 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7599 ins_cost(200);
7600 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7601 "CMOV$cop $dst.hi,$src.hi" %}
7602 opcode(0x0F,0x40);
7603 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7604 ins_pipe( pipe_cmov_reg_long );
7605 %}
7606
7607 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7608 predicate(VM_Version::supports_cmov() );
7609 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7610 ins_cost(200);
7611 expand %{
7612 cmovL_regU(cop, cr, dst, src);
7613 %}
7614 %}
7615
7616 //----------Arithmetic Instructions--------------------------------------------
7617 //----------Addition Instructions----------------------------------------------
7618 // Integer Addition Instructions
7619 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7620 match(Set dst (AddI dst src));
7621 effect(KILL cr);
7622
7623 size(2);
7624 format %{ "ADD $dst,$src" %}
7625 opcode(0x03);
7626 ins_encode( OpcP, RegReg( dst, src) );
7627 ins_pipe( ialu_reg_reg );
7628 %}
7629
7630 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7631 match(Set dst (AddI dst src));
7632 effect(KILL cr);
7633
7634 format %{ "ADD $dst,$src" %}
7635 opcode(0x81, 0x00); /* /0 id */
7636 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7637 ins_pipe( ialu_reg );
7638 %}
7639
7640 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7641 predicate(UseIncDec);
7642 match(Set dst (AddI dst src));
7643 effect(KILL cr);
7644
7645 size(1);
7646 format %{ "INC $dst" %}
7647 opcode(0x40); /* */
7648 ins_encode( Opc_plus( primary, dst ) );
7649 ins_pipe( ialu_reg );
7650 %}
7651
7652 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7653 match(Set dst (AddI src0 src1));
7654 ins_cost(110);
7655
7656 format %{ "LEA $dst,[$src0 + $src1]" %}
7657 opcode(0x8D); /* 0x8D /r */
7658 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7659 ins_pipe( ialu_reg_reg );
7660 %}
7661
7662 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7663 match(Set dst (AddP src0 src1));
7664 ins_cost(110);
7665
7666 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7667 opcode(0x8D); /* 0x8D /r */
7668 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7669 ins_pipe( ialu_reg_reg );
7670 %}
7671
7672 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7673 predicate(UseIncDec);
7674 match(Set dst (AddI dst src));
7675 effect(KILL cr);
7676
7677 size(1);
7678 format %{ "DEC $dst" %}
7679 opcode(0x48); /* */
7680 ins_encode( Opc_plus( primary, dst ) );
7681 ins_pipe( ialu_reg );
7682 %}
7683
7684 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7685 match(Set dst (AddP dst src));
7686 effect(KILL cr);
7687
7688 size(2);
7689 format %{ "ADD $dst,$src" %}
7690 opcode(0x03);
7691 ins_encode( OpcP, RegReg( dst, src) );
7692 ins_pipe( ialu_reg_reg );
7693 %}
7694
7695 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7696 match(Set dst (AddP dst src));
7697 effect(KILL cr);
7698
7699 format %{ "ADD $dst,$src" %}
7700 opcode(0x81,0x00); /* Opcode 81 /0 id */
7701 // ins_encode( RegImm( dst, src) );
7702 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7703 ins_pipe( ialu_reg );
7704 %}
7705
7706 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7707 match(Set dst (AddI dst (LoadI src)));
7708 effect(KILL cr);
7709
7710 ins_cost(125);
7711 format %{ "ADD $dst,$src" %}
7712 opcode(0x03);
7713 ins_encode( OpcP, RegMem( dst, src) );
7714 ins_pipe( ialu_reg_mem );
7715 %}
7716
7717 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7718 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7719 effect(KILL cr);
7720
7721 ins_cost(150);
7722 format %{ "ADD $dst,$src" %}
7723 opcode(0x01); /* Opcode 01 /r */
7724 ins_encode( OpcP, RegMem( src, dst ) );
7725 ins_pipe( ialu_mem_reg );
7726 %}
7727
7728 // Add Memory with Immediate
7729 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7730 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7731 effect(KILL cr);
7732
7733 ins_cost(125);
7734 format %{ "ADD $dst,$src" %}
7735 opcode(0x81); /* Opcode 81 /0 id */
7736 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7737 ins_pipe( ialu_mem_imm );
7738 %}
7739
7740 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7741 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7742 effect(KILL cr);
7743
7744 ins_cost(125);
7745 format %{ "INC $dst" %}
7746 opcode(0xFF); /* Opcode FF /0 */
7747 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7748 ins_pipe( ialu_mem_imm );
7749 %}
7750
7751 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7752 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7753 effect(KILL cr);
7754
7755 ins_cost(125);
7756 format %{ "DEC $dst" %}
7757 opcode(0xFF); /* Opcode FF /1 */
7758 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7759 ins_pipe( ialu_mem_imm );
7760 %}
7761
7762
7763 instruct checkCastPP( eRegP dst ) %{
7764 match(Set dst (CheckCastPP dst));
7765
7766 size(0);
7767 format %{ "#checkcastPP of $dst" %}
7768 ins_encode( /*empty encoding*/ );
7769 ins_pipe( empty );
7770 %}
7771
7772 instruct castPP( eRegP dst ) %{
7773 match(Set dst (CastPP dst));
7774 format %{ "#castPP of $dst" %}
7775 ins_encode( /*empty encoding*/ );
7776 ins_pipe( empty );
7777 %}
7778
7779 instruct castII( eRegI dst ) %{
7780 match(Set dst (CastII dst));
7781 format %{ "#castII of $dst" %}
7782 ins_encode( /*empty encoding*/ );
7783 ins_cost(0);
7784 ins_pipe( empty );
7785 %}
7786
7787
7788 // Load-locked - same as a regular pointer load when used with compare-swap
7789 instruct loadPLocked(eRegP dst, memory mem) %{
7790 match(Set dst (LoadPLocked mem));
7791
7792 ins_cost(125);
7793 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7794 opcode(0x8B);
7795 ins_encode( OpcP, RegMem(dst,mem));
7796 ins_pipe( ialu_reg_mem );
7797 %}
7798
7799 // LoadLong-locked - same as a volatile long load when used with compare-swap
7800 instruct loadLLocked(stackSlotL dst, memory mem) %{
7801 predicate(UseSSE<=1);
7802 match(Set dst (LoadLLocked mem));
7803
7804 ins_cost(200);
7805 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7806 "FISTp $dst" %}
7807 ins_encode(enc_loadL_volatile(mem,dst));
7808 ins_pipe( fpu_reg_mem );
7809 %}
7810
7811 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{
7812 predicate(UseSSE>=2);
7813 match(Set dst (LoadLLocked mem));
7814 effect(TEMP tmp);
7815 ins_cost(180);
7816 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7817 "MOVSD $dst,$tmp" %}
7818 ins_encode %{
7819 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7820 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7821 %}
7822 ins_pipe( pipe_slow );
7823 %}
7824
7825 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{
7826 predicate(UseSSE>=2);
7827 match(Set dst (LoadLLocked mem));
7828 effect(TEMP tmp);
7829 ins_cost(160);
7830 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7831 "MOVD $dst.lo,$tmp\n\t"
7832 "PSRLQ $tmp,32\n\t"
7833 "MOVD $dst.hi,$tmp" %}
7834 ins_encode %{
7835 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7836 __ movdl($dst$$Register, $tmp$$XMMRegister);
7837 __ psrlq($tmp$$XMMRegister, 32);
7838 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7839 %}
7840 ins_pipe( pipe_slow );
7841 %}
7842
7843 // Conditional-store of the updated heap-top.
7844 // Used during allocation of the shared heap.
7845 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7846 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7847 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7848 // EAX is killed if there is contention, but then it's also unused.
7849 // In the common case of no contention, EAX holds the new oop address.
7850 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7851 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7852 ins_pipe( pipe_cmpxchg );
7853 %}
7854
7855 // Conditional-store of an int value.
7856 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7857 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
7858 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7859 effect(KILL oldval);
7860 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7861 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7862 ins_pipe( pipe_cmpxchg );
7863 %}
7864
7865 // Conditional-store of a long value.
7866 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7867 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7868 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7869 effect(KILL oldval);
7870 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7871 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7872 "XCHG EBX,ECX"
7873 %}
7874 ins_encode %{
7875 // Note: we need to swap rbx, and rcx before and after the
7876 // cmpxchg8 instruction because the instruction uses
7877 // rcx as the high order word of the new value to store but
7878 // our register encoding uses rbx.
7879 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7880 if( os::is_MP() )
7881 __ lock();
7882 __ cmpxchg8($mem$$Address);
7883 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7884 %}
7885 ins_pipe( pipe_cmpxchg );
7886 %}
7887
7888 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7889
7890 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7891 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7892 effect(KILL cr, KILL oldval);
7893 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7894 "MOV $res,0\n\t"
7895 "JNE,s fail\n\t"
7896 "MOV $res,1\n"
7897 "fail:" %}
7898 ins_encode( enc_cmpxchg8(mem_ptr),
7899 enc_flags_ne_to_boolean(res) );
7900 ins_pipe( pipe_cmpxchg );
7901 %}
7902
7903 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7904 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7905 effect(KILL cr, KILL oldval);
7906 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7907 "MOV $res,0\n\t"
7908 "JNE,s fail\n\t"
7909 "MOV $res,1\n"
7910 "fail:" %}
7911 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7912 ins_pipe( pipe_cmpxchg );
7913 %}
7914
7915 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7916 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7917 effect(KILL cr, KILL oldval);
7918 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7919 "MOV $res,0\n\t"
7920 "JNE,s fail\n\t"
7921 "MOV $res,1\n"
7922 "fail:" %}
7923 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7924 ins_pipe( pipe_cmpxchg );
7925 %}
7926
7927 //----------Subtraction Instructions-------------------------------------------
7928 // Integer Subtraction Instructions
7929 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7930 match(Set dst (SubI dst src));
7931 effect(KILL cr);
7932
7933 size(2);
7934 format %{ "SUB $dst,$src" %}
7935 opcode(0x2B);
7936 ins_encode( OpcP, RegReg( dst, src) );
7937 ins_pipe( ialu_reg_reg );
7938 %}
7939
7940 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7941 match(Set dst (SubI dst src));
7942 effect(KILL cr);
7943
7944 format %{ "SUB $dst,$src" %}
7945 opcode(0x81,0x05); /* Opcode 81 /5 */
7946 // ins_encode( RegImm( dst, src) );
7947 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7948 ins_pipe( ialu_reg );
7949 %}
7950
7951 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7952 match(Set dst (SubI dst (LoadI src)));
7953 effect(KILL cr);
7954
7955 ins_cost(125);
7956 format %{ "SUB $dst,$src" %}
7957 opcode(0x2B);
7958 ins_encode( OpcP, RegMem( dst, src) );
7959 ins_pipe( ialu_reg_mem );
7960 %}
7961
7962 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7963 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7964 effect(KILL cr);
7965
7966 ins_cost(150);
7967 format %{ "SUB $dst,$src" %}
7968 opcode(0x29); /* Opcode 29 /r */
7969 ins_encode( OpcP, RegMem( src, dst ) );
7970 ins_pipe( ialu_mem_reg );
7971 %}
7972
7973 // Subtract from a pointer
7974 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
7975 match(Set dst (AddP dst (SubI zero src)));
7976 effect(KILL cr);
7977
7978 size(2);
7979 format %{ "SUB $dst,$src" %}
7980 opcode(0x2B);
7981 ins_encode( OpcP, RegReg( dst, src) );
7982 ins_pipe( ialu_reg_reg );
7983 %}
7984
7985 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
7986 match(Set dst (SubI zero dst));
7987 effect(KILL cr);
7988
7989 size(2);
7990 format %{ "NEG $dst" %}
7991 opcode(0xF7,0x03); // Opcode F7 /3
7992 ins_encode( OpcP, RegOpc( dst ) );
7993 ins_pipe( ialu_reg );
7994 %}
7995
7996
7997 //----------Multiplication/Division Instructions-------------------------------
7998 // Integer Multiplication Instructions
7999 // Multiply Register
8000 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8001 match(Set dst (MulI dst src));
8002 effect(KILL cr);
8003
8004 size(3);
8005 ins_cost(300);
8006 format %{ "IMUL $dst,$src" %}
8007 opcode(0xAF, 0x0F);
8008 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8009 ins_pipe( ialu_reg_reg_alu0 );
8010 %}
8011
8012 // Multiply 32-bit Immediate
8013 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8014 match(Set dst (MulI src imm));
8015 effect(KILL cr);
8016
8017 ins_cost(300);
8018 format %{ "IMUL $dst,$src,$imm" %}
8019 opcode(0x69); /* 69 /r id */
8020 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8021 ins_pipe( ialu_reg_reg_alu0 );
8022 %}
8023
8024 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8025 match(Set dst src);
8026 effect(KILL cr);
8027
8028 // Note that this is artificially increased to make it more expensive than loadConL
8029 ins_cost(250);
8030 format %{ "MOV EAX,$src\t// low word only" %}
8031 opcode(0xB8);
8032 ins_encode( LdImmL_Lo(dst, src) );
8033 ins_pipe( ialu_reg_fat );
8034 %}
8035
8036 // Multiply by 32-bit Immediate, taking the shifted high order results
8037 // (special case for shift by 32)
8038 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8039 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8040 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8041 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8042 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8043 effect(USE src1, KILL cr);
8044
8045 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8046 ins_cost(0*100 + 1*400 - 150);
8047 format %{ "IMUL EDX:EAX,$src1" %}
8048 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8049 ins_pipe( pipe_slow );
8050 %}
8051
8052 // Multiply by 32-bit Immediate, taking the shifted high order results
8053 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8054 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8055 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8056 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8057 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8058 effect(USE src1, KILL cr);
8059
8060 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8061 ins_cost(1*100 + 1*400 - 150);
8062 format %{ "IMUL EDX:EAX,$src1\n\t"
8063 "SAR EDX,$cnt-32" %}
8064 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8065 ins_pipe( pipe_slow );
8066 %}
8067
8068 // Multiply Memory 32-bit Immediate
8069 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8070 match(Set dst (MulI (LoadI src) imm));
8071 effect(KILL cr);
8072
8073 ins_cost(300);
8074 format %{ "IMUL $dst,$src,$imm" %}
8075 opcode(0x69); /* 69 /r id */
8076 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8077 ins_pipe( ialu_reg_mem_alu0 );
8078 %}
8079
8080 // Multiply Memory
8081 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8082 match(Set dst (MulI dst (LoadI src)));
8083 effect(KILL cr);
8084
8085 ins_cost(350);
8086 format %{ "IMUL $dst,$src" %}
8087 opcode(0xAF, 0x0F);
8088 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8089 ins_pipe( ialu_reg_mem_alu0 );
8090 %}
8091
8092 // Multiply Register Int to Long
8093 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8094 // Basic Idea: long = (long)int * (long)int
8095 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8096 effect(DEF dst, USE src, USE src1, KILL flags);
8097
8098 ins_cost(300);
8099 format %{ "IMUL $dst,$src1" %}
8100
8101 ins_encode( long_int_multiply( dst, src1 ) );
8102 ins_pipe( ialu_reg_reg_alu0 );
8103 %}
8104
8105 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8106 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8107 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8108 effect(KILL flags);
8109
8110 ins_cost(300);
8111 format %{ "MUL $dst,$src1" %}
8112
8113 ins_encode( long_uint_multiply(dst, src1) );
8114 ins_pipe( ialu_reg_reg_alu0 );
8115 %}
8116
8117 // Multiply Register Long
8118 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8119 match(Set dst (MulL dst src));
8120 effect(KILL cr, TEMP tmp);
8121 ins_cost(4*100+3*400);
8122 // Basic idea: lo(result) = lo(x_lo * y_lo)
8123 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8124 format %{ "MOV $tmp,$src.lo\n\t"
8125 "IMUL $tmp,EDX\n\t"
8126 "MOV EDX,$src.hi\n\t"
8127 "IMUL EDX,EAX\n\t"
8128 "ADD $tmp,EDX\n\t"
8129 "MUL EDX:EAX,$src.lo\n\t"
8130 "ADD EDX,$tmp" %}
8131 ins_encode( long_multiply( dst, src, tmp ) );
8132 ins_pipe( pipe_slow );
8133 %}
8134
8135 // Multiply Register Long where the left operand's high 32 bits are zero
8136 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8137 predicate(is_operand_hi32_zero(n->in(1)));
8138 match(Set dst (MulL dst src));
8139 effect(KILL cr, TEMP tmp);
8140 ins_cost(2*100+2*400);
8141 // Basic idea: lo(result) = lo(x_lo * y_lo)
8142 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8143 format %{ "MOV $tmp,$src.hi\n\t"
8144 "IMUL $tmp,EAX\n\t"
8145 "MUL EDX:EAX,$src.lo\n\t"
8146 "ADD EDX,$tmp" %}
8147 ins_encode %{
8148 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8149 __ imull($tmp$$Register, rax);
8150 __ mull($src$$Register);
8151 __ addl(rdx, $tmp$$Register);
8152 %}
8153 ins_pipe( pipe_slow );
8154 %}
8155
8156 // Multiply Register Long where the right operand's high 32 bits are zero
8157 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8158 predicate(is_operand_hi32_zero(n->in(2)));
8159 match(Set dst (MulL dst src));
8160 effect(KILL cr, TEMP tmp);
8161 ins_cost(2*100+2*400);
8162 // Basic idea: lo(result) = lo(x_lo * y_lo)
8163 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8164 format %{ "MOV $tmp,$src.lo\n\t"
8165 "IMUL $tmp,EDX\n\t"
8166 "MUL EDX:EAX,$src.lo\n\t"
8167 "ADD EDX,$tmp" %}
8168 ins_encode %{
8169 __ movl($tmp$$Register, $src$$Register);
8170 __ imull($tmp$$Register, rdx);
8171 __ mull($src$$Register);
8172 __ addl(rdx, $tmp$$Register);
8173 %}
8174 ins_pipe( pipe_slow );
8175 %}
8176
8177 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8178 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8179 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8180 match(Set dst (MulL dst src));
8181 effect(KILL cr);
8182 ins_cost(1*400);
8183 // Basic idea: lo(result) = lo(x_lo * y_lo)
8184 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8185 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8186 ins_encode %{
8187 __ mull($src$$Register);
8188 %}
8189 ins_pipe( pipe_slow );
8190 %}
8191
8192 // Multiply Register Long by small constant
8193 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8194 match(Set dst (MulL dst src));
8195 effect(KILL cr, TEMP tmp);
8196 ins_cost(2*100+2*400);
8197 size(12);
8198 // Basic idea: lo(result) = lo(src * EAX)
8199 // hi(result) = hi(src * EAX) + lo(src * EDX)
8200 format %{ "IMUL $tmp,EDX,$src\n\t"
8201 "MOV EDX,$src\n\t"
8202 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8203 "ADD EDX,$tmp" %}
8204 ins_encode( long_multiply_con( dst, src, tmp ) );
8205 ins_pipe( pipe_slow );
8206 %}
8207
8208 // Integer DIV with Register
8209 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8210 match(Set rax (DivI rax div));
8211 effect(KILL rdx, KILL cr);
8212 size(26);
8213 ins_cost(30*100+10*100);
8214 format %{ "CMP EAX,0x80000000\n\t"
8215 "JNE,s normal\n\t"
8216 "XOR EDX,EDX\n\t"
8217 "CMP ECX,-1\n\t"
8218 "JE,s done\n"
8219 "normal: CDQ\n\t"
8220 "IDIV $div\n\t"
8221 "done:" %}
8222 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8223 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8224 ins_pipe( ialu_reg_reg_alu0 );
8225 %}
8226
8227 // Divide Register Long
8228 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8229 match(Set dst (DivL src1 src2));
8230 effect( KILL cr, KILL cx, KILL bx );
8231 ins_cost(10000);
8232 format %{ "PUSH $src1.hi\n\t"
8233 "PUSH $src1.lo\n\t"
8234 "PUSH $src2.hi\n\t"
8235 "PUSH $src2.lo\n\t"
8236 "CALL SharedRuntime::ldiv\n\t"
8237 "ADD ESP,16" %}
8238 ins_encode( long_div(src1,src2) );
8239 ins_pipe( pipe_slow );
8240 %}
8241
8242 // Integer DIVMOD with Register, both quotient and mod results
8243 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8244 match(DivModI rax div);
8245 effect(KILL cr);
8246 size(26);
8247 ins_cost(30*100+10*100);
8248 format %{ "CMP EAX,0x80000000\n\t"
8249 "JNE,s normal\n\t"
8250 "XOR EDX,EDX\n\t"
8251 "CMP ECX,-1\n\t"
8252 "JE,s done\n"
8253 "normal: CDQ\n\t"
8254 "IDIV $div\n\t"
8255 "done:" %}
8256 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8257 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8258 ins_pipe( pipe_slow );
8259 %}
8260
8261 // Integer MOD with Register
8262 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8263 match(Set rdx (ModI rax div));
8264 effect(KILL rax, KILL cr);
8265
8266 size(26);
8267 ins_cost(300);
8268 format %{ "CDQ\n\t"
8269 "IDIV $div" %}
8270 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8271 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8272 ins_pipe( ialu_reg_reg_alu0 );
8273 %}
8274
8275 // Remainder Register Long
8276 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8277 match(Set dst (ModL src1 src2));
8278 effect( KILL cr, KILL cx, KILL bx );
8279 ins_cost(10000);
8280 format %{ "PUSH $src1.hi\n\t"
8281 "PUSH $src1.lo\n\t"
8282 "PUSH $src2.hi\n\t"
8283 "PUSH $src2.lo\n\t"
8284 "CALL SharedRuntime::lrem\n\t"
8285 "ADD ESP,16" %}
8286 ins_encode( long_mod(src1,src2) );
8287 ins_pipe( pipe_slow );
8288 %}
8289
8290 // Divide Register Long (no special case since divisor != -1)
8291 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8292 match(Set dst (DivL dst imm));
8293 effect( TEMP tmp, TEMP tmp2, KILL cr );
8294 ins_cost(1000);
8295 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8296 "XOR $tmp2,$tmp2\n\t"
8297 "CMP $tmp,EDX\n\t"
8298 "JA,s fast\n\t"
8299 "MOV $tmp2,EAX\n\t"
8300 "MOV EAX,EDX\n\t"
8301 "MOV EDX,0\n\t"
8302 "JLE,s pos\n\t"
8303 "LNEG EAX : $tmp2\n\t"
8304 "DIV $tmp # unsigned division\n\t"
8305 "XCHG EAX,$tmp2\n\t"
8306 "DIV $tmp\n\t"
8307 "LNEG $tmp2 : EAX\n\t"
8308 "JMP,s done\n"
8309 "pos:\n\t"
8310 "DIV $tmp\n\t"
8311 "XCHG EAX,$tmp2\n"
8312 "fast:\n\t"
8313 "DIV $tmp\n"
8314 "done:\n\t"
8315 "MOV EDX,$tmp2\n\t"
8316 "NEG EDX:EAX # if $imm < 0" %}
8317 ins_encode %{
8318 int con = (int)$imm$$constant;
8319 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8320 int pcon = (con > 0) ? con : -con;
8321 Label Lfast, Lpos, Ldone;
8322
8323 __ movl($tmp$$Register, pcon);
8324 __ xorl($tmp2$$Register,$tmp2$$Register);
8325 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8326 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8327
8328 __ movl($tmp2$$Register, $dst$$Register); // save
8329 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8330 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8331 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8332
8333 // Negative dividend.
8334 // convert value to positive to use unsigned division
8335 __ lneg($dst$$Register, $tmp2$$Register);
8336 __ divl($tmp$$Register);
8337 __ xchgl($dst$$Register, $tmp2$$Register);
8338 __ divl($tmp$$Register);
8339 // revert result back to negative
8340 __ lneg($tmp2$$Register, $dst$$Register);
8341 __ jmpb(Ldone);
8342
8343 __ bind(Lpos);
8344 __ divl($tmp$$Register); // Use unsigned division
8345 __ xchgl($dst$$Register, $tmp2$$Register);
8346 // Fallthrow for final divide, tmp2 has 32 bit hi result
8347
8348 __ bind(Lfast);
8349 // fast path: src is positive
8350 __ divl($tmp$$Register); // Use unsigned division
8351
8352 __ bind(Ldone);
8353 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8354 if (con < 0) {
8355 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8356 }
8357 %}
8358 ins_pipe( pipe_slow );
8359 %}
8360
8361 // Remainder Register Long (remainder fit into 32 bits)
8362 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8363 match(Set dst (ModL dst imm));
8364 effect( TEMP tmp, TEMP tmp2, KILL cr );
8365 ins_cost(1000);
8366 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8367 "CMP $tmp,EDX\n\t"
8368 "JA,s fast\n\t"
8369 "MOV $tmp2,EAX\n\t"
8370 "MOV EAX,EDX\n\t"
8371 "MOV EDX,0\n\t"
8372 "JLE,s pos\n\t"
8373 "LNEG EAX : $tmp2\n\t"
8374 "DIV $tmp # unsigned division\n\t"
8375 "MOV EAX,$tmp2\n\t"
8376 "DIV $tmp\n\t"
8377 "NEG EDX\n\t"
8378 "JMP,s done\n"
8379 "pos:\n\t"
8380 "DIV $tmp\n\t"
8381 "MOV EAX,$tmp2\n"
8382 "fast:\n\t"
8383 "DIV $tmp\n"
8384 "done:\n\t"
8385 "MOV EAX,EDX\n\t"
8386 "SAR EDX,31\n\t" %}
8387 ins_encode %{
8388 int con = (int)$imm$$constant;
8389 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8390 int pcon = (con > 0) ? con : -con;
8391 Label Lfast, Lpos, Ldone;
8392
8393 __ movl($tmp$$Register, pcon);
8394 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8395 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8396
8397 __ movl($tmp2$$Register, $dst$$Register); // save
8398 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8399 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8400 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8401
8402 // Negative dividend.
8403 // convert value to positive to use unsigned division
8404 __ lneg($dst$$Register, $tmp2$$Register);
8405 __ divl($tmp$$Register);
8406 __ movl($dst$$Register, $tmp2$$Register);
8407 __ divl($tmp$$Register);
8408 // revert remainder back to negative
8409 __ negl(HIGH_FROM_LOW($dst$$Register));
8410 __ jmpb(Ldone);
8411
8412 __ bind(Lpos);
8413 __ divl($tmp$$Register);
8414 __ movl($dst$$Register, $tmp2$$Register);
8415
8416 __ bind(Lfast);
8417 // fast path: src is positive
8418 __ divl($tmp$$Register);
8419
8420 __ bind(Ldone);
8421 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8422 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8423
8424 %}
8425 ins_pipe( pipe_slow );
8426 %}
8427
8428 // Integer Shift Instructions
8429 // Shift Left by one
8430 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8431 match(Set dst (LShiftI dst shift));
8432 effect(KILL cr);
8433
8434 size(2);
8435 format %{ "SHL $dst,$shift" %}
8436 opcode(0xD1, 0x4); /* D1 /4 */
8437 ins_encode( OpcP, RegOpc( dst ) );
8438 ins_pipe( ialu_reg );
8439 %}
8440
8441 // Shift Left by 8-bit immediate
8442 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8443 match(Set dst (LShiftI dst shift));
8444 effect(KILL cr);
8445
8446 size(3);
8447 format %{ "SHL $dst,$shift" %}
8448 opcode(0xC1, 0x4); /* C1 /4 ib */
8449 ins_encode( RegOpcImm( dst, shift) );
8450 ins_pipe( ialu_reg );
8451 %}
8452
8453 // Shift Left by variable
8454 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8455 match(Set dst (LShiftI dst shift));
8456 effect(KILL cr);
8457
8458 size(2);
8459 format %{ "SHL $dst,$shift" %}
8460 opcode(0xD3, 0x4); /* D3 /4 */
8461 ins_encode( OpcP, RegOpc( dst ) );
8462 ins_pipe( ialu_reg_reg );
8463 %}
8464
8465 // Arithmetic shift right by one
8466 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8467 match(Set dst (RShiftI dst shift));
8468 effect(KILL cr);
8469
8470 size(2);
8471 format %{ "SAR $dst,$shift" %}
8472 opcode(0xD1, 0x7); /* D1 /7 */
8473 ins_encode( OpcP, RegOpc( dst ) );
8474 ins_pipe( ialu_reg );
8475 %}
8476
8477 // Arithmetic shift right by one
8478 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8479 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8480 effect(KILL cr);
8481 format %{ "SAR $dst,$shift" %}
8482 opcode(0xD1, 0x7); /* D1 /7 */
8483 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8484 ins_pipe( ialu_mem_imm );
8485 %}
8486
8487 // Arithmetic Shift Right by 8-bit immediate
8488 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8489 match(Set dst (RShiftI dst shift));
8490 effect(KILL cr);
8491
8492 size(3);
8493 format %{ "SAR $dst,$shift" %}
8494 opcode(0xC1, 0x7); /* C1 /7 ib */
8495 ins_encode( RegOpcImm( dst, shift ) );
8496 ins_pipe( ialu_mem_imm );
8497 %}
8498
8499 // Arithmetic Shift Right by 8-bit immediate
8500 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8501 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8502 effect(KILL cr);
8503
8504 format %{ "SAR $dst,$shift" %}
8505 opcode(0xC1, 0x7); /* C1 /7 ib */
8506 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8507 ins_pipe( ialu_mem_imm );
8508 %}
8509
8510 // Arithmetic Shift Right by variable
8511 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8512 match(Set dst (RShiftI dst shift));
8513 effect(KILL cr);
8514
8515 size(2);
8516 format %{ "SAR $dst,$shift" %}
8517 opcode(0xD3, 0x7); /* D3 /7 */
8518 ins_encode( OpcP, RegOpc( dst ) );
8519 ins_pipe( ialu_reg_reg );
8520 %}
8521
8522 // Logical shift right by one
8523 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8524 match(Set dst (URShiftI dst shift));
8525 effect(KILL cr);
8526
8527 size(2);
8528 format %{ "SHR $dst,$shift" %}
8529 opcode(0xD1, 0x5); /* D1 /5 */
8530 ins_encode( OpcP, RegOpc( dst ) );
8531 ins_pipe( ialu_reg );
8532 %}
8533
8534 // Logical Shift Right by 8-bit immediate
8535 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8536 match(Set dst (URShiftI dst shift));
8537 effect(KILL cr);
8538
8539 size(3);
8540 format %{ "SHR $dst,$shift" %}
8541 opcode(0xC1, 0x5); /* C1 /5 ib */
8542 ins_encode( RegOpcImm( dst, shift) );
8543 ins_pipe( ialu_reg );
8544 %}
8545
8546
8547 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8548 // This idiom is used by the compiler for the i2b bytecode.
8549 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8550 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8551
8552 size(3);
8553 format %{ "MOVSX $dst,$src :8" %}
8554 ins_encode %{
8555 __ movsbl($dst$$Register, $src$$Register);
8556 %}
8557 ins_pipe(ialu_reg_reg);
8558 %}
8559
8560 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8561 // This idiom is used by the compiler the i2s bytecode.
8562 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8563 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8564
8565 size(3);
8566 format %{ "MOVSX $dst,$src :16" %}
8567 ins_encode %{
8568 __ movswl($dst$$Register, $src$$Register);
8569 %}
8570 ins_pipe(ialu_reg_reg);
8571 %}
8572
8573
8574 // Logical Shift Right by variable
8575 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8576 match(Set dst (URShiftI dst shift));
8577 effect(KILL cr);
8578
8579 size(2);
8580 format %{ "SHR $dst,$shift" %}
8581 opcode(0xD3, 0x5); /* D3 /5 */
8582 ins_encode( OpcP, RegOpc( dst ) );
8583 ins_pipe( ialu_reg_reg );
8584 %}
8585
8586
8587 //----------Logical Instructions-----------------------------------------------
8588 //----------Integer Logical Instructions---------------------------------------
8589 // And Instructions
8590 // And Register with Register
8591 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8592 match(Set dst (AndI dst src));
8593 effect(KILL cr);
8594
8595 size(2);
8596 format %{ "AND $dst,$src" %}
8597 opcode(0x23);
8598 ins_encode( OpcP, RegReg( dst, src) );
8599 ins_pipe( ialu_reg_reg );
8600 %}
8601
8602 // And Register with Immediate
8603 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8604 match(Set dst (AndI dst src));
8605 effect(KILL cr);
8606
8607 format %{ "AND $dst,$src" %}
8608 opcode(0x81,0x04); /* Opcode 81 /4 */
8609 // ins_encode( RegImm( dst, src) );
8610 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8611 ins_pipe( ialu_reg );
8612 %}
8613
8614 // And Register with Memory
8615 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8616 match(Set dst (AndI dst (LoadI src)));
8617 effect(KILL cr);
8618
8619 ins_cost(125);
8620 format %{ "AND $dst,$src" %}
8621 opcode(0x23);
8622 ins_encode( OpcP, RegMem( dst, src) );
8623 ins_pipe( ialu_reg_mem );
8624 %}
8625
8626 // And Memory with Register
8627 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8628 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8629 effect(KILL cr);
8630
8631 ins_cost(150);
8632 format %{ "AND $dst,$src" %}
8633 opcode(0x21); /* Opcode 21 /r */
8634 ins_encode( OpcP, RegMem( src, dst ) );
8635 ins_pipe( ialu_mem_reg );
8636 %}
8637
8638 // And Memory with Immediate
8639 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8640 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8641 effect(KILL cr);
8642
8643 ins_cost(125);
8644 format %{ "AND $dst,$src" %}
8645 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8646 // ins_encode( MemImm( dst, src) );
8647 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8648 ins_pipe( ialu_mem_imm );
8649 %}
8650
8651 // Or Instructions
8652 // Or Register with Register
8653 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8654 match(Set dst (OrI dst src));
8655 effect(KILL cr);
8656
8657 size(2);
8658 format %{ "OR $dst,$src" %}
8659 opcode(0x0B);
8660 ins_encode( OpcP, RegReg( dst, src) );
8661 ins_pipe( ialu_reg_reg );
8662 %}
8663
8664 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8665 match(Set dst (OrI dst (CastP2X src)));
8666 effect(KILL cr);
8667
8668 size(2);
8669 format %{ "OR $dst,$src" %}
8670 opcode(0x0B);
8671 ins_encode( OpcP, RegReg( dst, src) );
8672 ins_pipe( ialu_reg_reg );
8673 %}
8674
8675
8676 // Or Register with Immediate
8677 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8678 match(Set dst (OrI dst src));
8679 effect(KILL cr);
8680
8681 format %{ "OR $dst,$src" %}
8682 opcode(0x81,0x01); /* Opcode 81 /1 id */
8683 // ins_encode( RegImm( dst, src) );
8684 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8685 ins_pipe( ialu_reg );
8686 %}
8687
8688 // Or Register with Memory
8689 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8690 match(Set dst (OrI dst (LoadI src)));
8691 effect(KILL cr);
8692
8693 ins_cost(125);
8694 format %{ "OR $dst,$src" %}
8695 opcode(0x0B);
8696 ins_encode( OpcP, RegMem( dst, src) );
8697 ins_pipe( ialu_reg_mem );
8698 %}
8699
8700 // Or Memory with Register
8701 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8702 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8703 effect(KILL cr);
8704
8705 ins_cost(150);
8706 format %{ "OR $dst,$src" %}
8707 opcode(0x09); /* Opcode 09 /r */
8708 ins_encode( OpcP, RegMem( src, dst ) );
8709 ins_pipe( ialu_mem_reg );
8710 %}
8711
8712 // Or Memory with Immediate
8713 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8714 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8715 effect(KILL cr);
8716
8717 ins_cost(125);
8718 format %{ "OR $dst,$src" %}
8719 opcode(0x81,0x1); /* Opcode 81 /1 id */
8720 // ins_encode( MemImm( dst, src) );
8721 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8722 ins_pipe( ialu_mem_imm );
8723 %}
8724
8725 // ROL/ROR
8726 // ROL expand
8727 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8728 effect(USE_DEF dst, USE shift, KILL cr);
8729
8730 format %{ "ROL $dst, $shift" %}
8731 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8732 ins_encode( OpcP, RegOpc( dst ));
8733 ins_pipe( ialu_reg );
8734 %}
8735
8736 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8737 effect(USE_DEF dst, USE shift, KILL cr);
8738
8739 format %{ "ROL $dst, $shift" %}
8740 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8741 ins_encode( RegOpcImm(dst, shift) );
8742 ins_pipe(ialu_reg);
8743 %}
8744
8745 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8746 effect(USE_DEF dst, USE shift, KILL cr);
8747
8748 format %{ "ROL $dst, $shift" %}
8749 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8750 ins_encode(OpcP, RegOpc(dst));
8751 ins_pipe( ialu_reg_reg );
8752 %}
8753 // end of ROL expand
8754
8755 // ROL 32bit by one once
8756 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8757 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8758
8759 expand %{
8760 rolI_eReg_imm1(dst, lshift, cr);
8761 %}
8762 %}
8763
8764 // ROL 32bit var by imm8 once
8765 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8766 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8767 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8768
8769 expand %{
8770 rolI_eReg_imm8(dst, lshift, cr);
8771 %}
8772 %}
8773
8774 // ROL 32bit var by var once
8775 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8776 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8777
8778 expand %{
8779 rolI_eReg_CL(dst, shift, cr);
8780 %}
8781 %}
8782
8783 // ROL 32bit var by var once
8784 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8785 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8786
8787 expand %{
8788 rolI_eReg_CL(dst, shift, cr);
8789 %}
8790 %}
8791
8792 // ROR expand
8793 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8794 effect(USE_DEF dst, USE shift, KILL cr);
8795
8796 format %{ "ROR $dst, $shift" %}
8797 opcode(0xD1,0x1); /* Opcode D1 /1 */
8798 ins_encode( OpcP, RegOpc( dst ) );
8799 ins_pipe( ialu_reg );
8800 %}
8801
8802 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8803 effect (USE_DEF dst, USE shift, KILL cr);
8804
8805 format %{ "ROR $dst, $shift" %}
8806 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8807 ins_encode( RegOpcImm(dst, shift) );
8808 ins_pipe( ialu_reg );
8809 %}
8810
8811 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8812 effect(USE_DEF dst, USE shift, KILL cr);
8813
8814 format %{ "ROR $dst, $shift" %}
8815 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8816 ins_encode(OpcP, RegOpc(dst));
8817 ins_pipe( ialu_reg_reg );
8818 %}
8819 // end of ROR expand
8820
8821 // ROR right once
8822 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8823 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8824
8825 expand %{
8826 rorI_eReg_imm1(dst, rshift, cr);
8827 %}
8828 %}
8829
8830 // ROR 32bit by immI8 once
8831 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8832 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8833 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8834
8835 expand %{
8836 rorI_eReg_imm8(dst, rshift, cr);
8837 %}
8838 %}
8839
8840 // ROR 32bit var by var once
8841 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8842 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8843
8844 expand %{
8845 rorI_eReg_CL(dst, shift, cr);
8846 %}
8847 %}
8848
8849 // ROR 32bit var by var once
8850 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8851 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8852
8853 expand %{
8854 rorI_eReg_CL(dst, shift, cr);
8855 %}
8856 %}
8857
8858 // Xor Instructions
8859 // Xor Register with Register
8860 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8861 match(Set dst (XorI dst src));
8862 effect(KILL cr);
8863
8864 size(2);
8865 format %{ "XOR $dst,$src" %}
8866 opcode(0x33);
8867 ins_encode( OpcP, RegReg( dst, src) );
8868 ins_pipe( ialu_reg_reg );
8869 %}
8870
8871 // Xor Register with Immediate -1
8872 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8873 match(Set dst (XorI dst imm));
8874
8875 size(2);
8876 format %{ "NOT $dst" %}
8877 ins_encode %{
8878 __ notl($dst$$Register);
8879 %}
8880 ins_pipe( ialu_reg );
8881 %}
8882
8883 // Xor Register with Immediate
8884 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8885 match(Set dst (XorI dst src));
8886 effect(KILL cr);
8887
8888 format %{ "XOR $dst,$src" %}
8889 opcode(0x81,0x06); /* Opcode 81 /6 id */
8890 // ins_encode( RegImm( dst, src) );
8891 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8892 ins_pipe( ialu_reg );
8893 %}
8894
8895 // Xor Register with Memory
8896 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8897 match(Set dst (XorI dst (LoadI src)));
8898 effect(KILL cr);
8899
8900 ins_cost(125);
8901 format %{ "XOR $dst,$src" %}
8902 opcode(0x33);
8903 ins_encode( OpcP, RegMem(dst, src) );
8904 ins_pipe( ialu_reg_mem );
8905 %}
8906
8907 // Xor Memory with Register
8908 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8909 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8910 effect(KILL cr);
8911
8912 ins_cost(150);
8913 format %{ "XOR $dst,$src" %}
8914 opcode(0x31); /* Opcode 31 /r */
8915 ins_encode( OpcP, RegMem( src, dst ) );
8916 ins_pipe( ialu_mem_reg );
8917 %}
8918
8919 // Xor Memory with Immediate
8920 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8921 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8922 effect(KILL cr);
8923
8924 ins_cost(125);
8925 format %{ "XOR $dst,$src" %}
8926 opcode(0x81,0x6); /* Opcode 81 /6 id */
8927 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8928 ins_pipe( ialu_mem_imm );
8929 %}
8930
8931 //----------Convert Int to Boolean---------------------------------------------
8932
8933 instruct movI_nocopy(eRegI dst, eRegI src) %{
8934 effect( DEF dst, USE src );
8935 format %{ "MOV $dst,$src" %}
8936 ins_encode( enc_Copy( dst, src) );
8937 ins_pipe( ialu_reg_reg );
8938 %}
8939
8940 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8941 effect( USE_DEF dst, USE src, KILL cr );
8942
8943 size(4);
8944 format %{ "NEG $dst\n\t"
8945 "ADC $dst,$src" %}
8946 ins_encode( neg_reg(dst),
8947 OpcRegReg(0x13,dst,src) );
8948 ins_pipe( ialu_reg_reg_long );
8949 %}
8950
8951 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8952 match(Set dst (Conv2B src));
8953
8954 expand %{
8955 movI_nocopy(dst,src);
8956 ci2b(dst,src,cr);
8957 %}
8958 %}
8959
8960 instruct movP_nocopy(eRegI dst, eRegP src) %{
8961 effect( DEF dst, USE src );
8962 format %{ "MOV $dst,$src" %}
8963 ins_encode( enc_Copy( dst, src) );
8964 ins_pipe( ialu_reg_reg );
8965 %}
8966
8967 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
8968 effect( USE_DEF dst, USE src, KILL cr );
8969 format %{ "NEG $dst\n\t"
8970 "ADC $dst,$src" %}
8971 ins_encode( neg_reg(dst),
8972 OpcRegReg(0x13,dst,src) );
8973 ins_pipe( ialu_reg_reg_long );
8974 %}
8975
8976 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
8977 match(Set dst (Conv2B src));
8978
8979 expand %{
8980 movP_nocopy(dst,src);
8981 cp2b(dst,src,cr);
8982 %}
8983 %}
8984
8985 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8986 match(Set dst (CmpLTMask p q));
8987 effect( KILL cr );
8988 ins_cost(400);
8989
8990 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8991 format %{ "XOR $dst,$dst\n\t"
8992 "CMP $p,$q\n\t"
8993 "SETlt $dst\n\t"
8994 "NEG $dst" %}
8995 ins_encode( OpcRegReg(0x33,dst,dst),
8996 OpcRegReg(0x3B,p,q),
8997 setLT_reg(dst), neg_reg(dst) );
8998 ins_pipe( pipe_slow );
8999 %}
9000
9001 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9002 match(Set dst (CmpLTMask dst zero));
9003 effect( DEF dst, KILL cr );
9004 ins_cost(100);
9005
9006 format %{ "SAR $dst,31" %}
9007 opcode(0xC1, 0x7); /* C1 /7 ib */
9008 ins_encode( RegOpcImm( dst, 0x1F ) );
9009 ins_pipe( ialu_reg );
9010 %}
9011
9012
9013 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9014 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9015 effect( KILL tmp, KILL cr );
9016 ins_cost(400);
9017 // annoyingly, $tmp has no edges so you cant ask for it in
9018 // any format or encoding
9019 format %{ "SUB $p,$q\n\t"
9020 "SBB ECX,ECX\n\t"
9021 "AND ECX,$y\n\t"
9022 "ADD $p,ECX" %}
9023 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9024 ins_pipe( pipe_cmplt );
9025 %}
9026
9027 /* If I enable this, I encourage spilling in the inner loop of compress.
9028 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9029 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9030 effect( USE_KILL tmp, KILL cr );
9031 ins_cost(400);
9032
9033 format %{ "SUB $p,$q\n\t"
9034 "SBB ECX,ECX\n\t"
9035 "AND ECX,$y\n\t"
9036 "ADD $p,ECX" %}
9037 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9038 %}
9039 */
9040
9041 //----------Long Instructions------------------------------------------------
9042 // Add Long Register with Register
9043 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9044 match(Set dst (AddL dst src));
9045 effect(KILL cr);
9046 ins_cost(200);
9047 format %{ "ADD $dst.lo,$src.lo\n\t"
9048 "ADC $dst.hi,$src.hi" %}
9049 opcode(0x03, 0x13);
9050 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9051 ins_pipe( ialu_reg_reg_long );
9052 %}
9053
9054 // Add Long Register with Immediate
9055 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9056 match(Set dst (AddL dst src));
9057 effect(KILL cr);
9058 format %{ "ADD $dst.lo,$src.lo\n\t"
9059 "ADC $dst.hi,$src.hi" %}
9060 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9061 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9062 ins_pipe( ialu_reg_long );
9063 %}
9064
9065 // Add Long Register with Memory
9066 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9067 match(Set dst (AddL dst (LoadL mem)));
9068 effect(KILL cr);
9069 ins_cost(125);
9070 format %{ "ADD $dst.lo,$mem\n\t"
9071 "ADC $dst.hi,$mem+4" %}
9072 opcode(0x03, 0x13);
9073 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9074 ins_pipe( ialu_reg_long_mem );
9075 %}
9076
9077 // Subtract Long Register with Register.
9078 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9079 match(Set dst (SubL dst src));
9080 effect(KILL cr);
9081 ins_cost(200);
9082 format %{ "SUB $dst.lo,$src.lo\n\t"
9083 "SBB $dst.hi,$src.hi" %}
9084 opcode(0x2B, 0x1B);
9085 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9086 ins_pipe( ialu_reg_reg_long );
9087 %}
9088
9089 // Subtract Long Register with Immediate
9090 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9091 match(Set dst (SubL dst src));
9092 effect(KILL cr);
9093 format %{ "SUB $dst.lo,$src.lo\n\t"
9094 "SBB $dst.hi,$src.hi" %}
9095 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9096 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9097 ins_pipe( ialu_reg_long );
9098 %}
9099
9100 // Subtract Long Register with Memory
9101 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9102 match(Set dst (SubL dst (LoadL mem)));
9103 effect(KILL cr);
9104 ins_cost(125);
9105 format %{ "SUB $dst.lo,$mem\n\t"
9106 "SBB $dst.hi,$mem+4" %}
9107 opcode(0x2B, 0x1B);
9108 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9109 ins_pipe( ialu_reg_long_mem );
9110 %}
9111
9112 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9113 match(Set dst (SubL zero dst));
9114 effect(KILL cr);
9115 ins_cost(300);
9116 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9117 ins_encode( neg_long(dst) );
9118 ins_pipe( ialu_reg_reg_long );
9119 %}
9120
9121 // And Long Register with Register
9122 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9123 match(Set dst (AndL dst src));
9124 effect(KILL cr);
9125 format %{ "AND $dst.lo,$src.lo\n\t"
9126 "AND $dst.hi,$src.hi" %}
9127 opcode(0x23,0x23);
9128 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9129 ins_pipe( ialu_reg_reg_long );
9130 %}
9131
9132 // And Long Register with Immediate
9133 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9134 match(Set dst (AndL dst src));
9135 effect(KILL cr);
9136 format %{ "AND $dst.lo,$src.lo\n\t"
9137 "AND $dst.hi,$src.hi" %}
9138 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9139 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9140 ins_pipe( ialu_reg_long );
9141 %}
9142
9143 // And Long Register with Memory
9144 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9145 match(Set dst (AndL dst (LoadL mem)));
9146 effect(KILL cr);
9147 ins_cost(125);
9148 format %{ "AND $dst.lo,$mem\n\t"
9149 "AND $dst.hi,$mem+4" %}
9150 opcode(0x23, 0x23);
9151 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9152 ins_pipe( ialu_reg_long_mem );
9153 %}
9154
9155 // Or Long Register with Register
9156 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9157 match(Set dst (OrL dst src));
9158 effect(KILL cr);
9159 format %{ "OR $dst.lo,$src.lo\n\t"
9160 "OR $dst.hi,$src.hi" %}
9161 opcode(0x0B,0x0B);
9162 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9163 ins_pipe( ialu_reg_reg_long );
9164 %}
9165
9166 // Or Long Register with Immediate
9167 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9168 match(Set dst (OrL dst src));
9169 effect(KILL cr);
9170 format %{ "OR $dst.lo,$src.lo\n\t"
9171 "OR $dst.hi,$src.hi" %}
9172 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9173 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9174 ins_pipe( ialu_reg_long );
9175 %}
9176
9177 // Or Long Register with Memory
9178 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9179 match(Set dst (OrL dst (LoadL mem)));
9180 effect(KILL cr);
9181 ins_cost(125);
9182 format %{ "OR $dst.lo,$mem\n\t"
9183 "OR $dst.hi,$mem+4" %}
9184 opcode(0x0B,0x0B);
9185 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9186 ins_pipe( ialu_reg_long_mem );
9187 %}
9188
9189 // Xor Long Register with Register
9190 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9191 match(Set dst (XorL dst src));
9192 effect(KILL cr);
9193 format %{ "XOR $dst.lo,$src.lo\n\t"
9194 "XOR $dst.hi,$src.hi" %}
9195 opcode(0x33,0x33);
9196 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9197 ins_pipe( ialu_reg_reg_long );
9198 %}
9199
9200 // Xor Long Register with Immediate -1
9201 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9202 match(Set dst (XorL dst imm));
9203 format %{ "NOT $dst.lo\n\t"
9204 "NOT $dst.hi" %}
9205 ins_encode %{
9206 __ notl($dst$$Register);
9207 __ notl(HIGH_FROM_LOW($dst$$Register));
9208 %}
9209 ins_pipe( ialu_reg_long );
9210 %}
9211
9212 // Xor Long Register with Immediate
9213 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9214 match(Set dst (XorL dst src));
9215 effect(KILL cr);
9216 format %{ "XOR $dst.lo,$src.lo\n\t"
9217 "XOR $dst.hi,$src.hi" %}
9218 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9219 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9220 ins_pipe( ialu_reg_long );
9221 %}
9222
9223 // Xor Long Register with Memory
9224 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9225 match(Set dst (XorL dst (LoadL mem)));
9226 effect(KILL cr);
9227 ins_cost(125);
9228 format %{ "XOR $dst.lo,$mem\n\t"
9229 "XOR $dst.hi,$mem+4" %}
9230 opcode(0x33,0x33);
9231 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9232 ins_pipe( ialu_reg_long_mem );
9233 %}
9234
9235 // Shift Left Long by 1
9236 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9237 predicate(UseNewLongLShift);
9238 match(Set dst (LShiftL dst cnt));
9239 effect(KILL cr);
9240 ins_cost(100);
9241 format %{ "ADD $dst.lo,$dst.lo\n\t"
9242 "ADC $dst.hi,$dst.hi" %}
9243 ins_encode %{
9244 __ addl($dst$$Register,$dst$$Register);
9245 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9246 %}
9247 ins_pipe( ialu_reg_long );
9248 %}
9249
9250 // Shift Left Long by 2
9251 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9252 predicate(UseNewLongLShift);
9253 match(Set dst (LShiftL dst cnt));
9254 effect(KILL cr);
9255 ins_cost(100);
9256 format %{ "ADD $dst.lo,$dst.lo\n\t"
9257 "ADC $dst.hi,$dst.hi\n\t"
9258 "ADD $dst.lo,$dst.lo\n\t"
9259 "ADC $dst.hi,$dst.hi" %}
9260 ins_encode %{
9261 __ addl($dst$$Register,$dst$$Register);
9262 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9263 __ addl($dst$$Register,$dst$$Register);
9264 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9265 %}
9266 ins_pipe( ialu_reg_long );
9267 %}
9268
9269 // Shift Left Long by 3
9270 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9271 predicate(UseNewLongLShift);
9272 match(Set dst (LShiftL dst cnt));
9273 effect(KILL cr);
9274 ins_cost(100);
9275 format %{ "ADD $dst.lo,$dst.lo\n\t"
9276 "ADC $dst.hi,$dst.hi\n\t"
9277 "ADD $dst.lo,$dst.lo\n\t"
9278 "ADC $dst.hi,$dst.hi\n\t"
9279 "ADD $dst.lo,$dst.lo\n\t"
9280 "ADC $dst.hi,$dst.hi" %}
9281 ins_encode %{
9282 __ addl($dst$$Register,$dst$$Register);
9283 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9284 __ addl($dst$$Register,$dst$$Register);
9285 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9286 __ addl($dst$$Register,$dst$$Register);
9287 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9288 %}
9289 ins_pipe( ialu_reg_long );
9290 %}
9291
9292 // Shift Left Long by 1-31
9293 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9294 match(Set dst (LShiftL dst cnt));
9295 effect(KILL cr);
9296 ins_cost(200);
9297 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9298 "SHL $dst.lo,$cnt" %}
9299 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9300 ins_encode( move_long_small_shift(dst,cnt) );
9301 ins_pipe( ialu_reg_long );
9302 %}
9303
9304 // Shift Left Long by 32-63
9305 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9306 match(Set dst (LShiftL dst cnt));
9307 effect(KILL cr);
9308 ins_cost(300);
9309 format %{ "MOV $dst.hi,$dst.lo\n"
9310 "\tSHL $dst.hi,$cnt-32\n"
9311 "\tXOR $dst.lo,$dst.lo" %}
9312 opcode(0xC1, 0x4); /* C1 /4 ib */
9313 ins_encode( move_long_big_shift_clr(dst,cnt) );
9314 ins_pipe( ialu_reg_long );
9315 %}
9316
9317 // Shift Left Long by variable
9318 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9319 match(Set dst (LShiftL dst shift));
9320 effect(KILL cr);
9321 ins_cost(500+200);
9322 size(17);
9323 format %{ "TEST $shift,32\n\t"
9324 "JEQ,s small\n\t"
9325 "MOV $dst.hi,$dst.lo\n\t"
9326 "XOR $dst.lo,$dst.lo\n"
9327 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9328 "SHL $dst.lo,$shift" %}
9329 ins_encode( shift_left_long( dst, shift ) );
9330 ins_pipe( pipe_slow );
9331 %}
9332
9333 // Shift Right Long by 1-31
9334 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9335 match(Set dst (URShiftL dst cnt));
9336 effect(KILL cr);
9337 ins_cost(200);
9338 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9339 "SHR $dst.hi,$cnt" %}
9340 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9341 ins_encode( move_long_small_shift(dst,cnt) );
9342 ins_pipe( ialu_reg_long );
9343 %}
9344
9345 // Shift Right Long by 32-63
9346 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9347 match(Set dst (URShiftL dst cnt));
9348 effect(KILL cr);
9349 ins_cost(300);
9350 format %{ "MOV $dst.lo,$dst.hi\n"
9351 "\tSHR $dst.lo,$cnt-32\n"
9352 "\tXOR $dst.hi,$dst.hi" %}
9353 opcode(0xC1, 0x5); /* C1 /5 ib */
9354 ins_encode( move_long_big_shift_clr(dst,cnt) );
9355 ins_pipe( ialu_reg_long );
9356 %}
9357
9358 // Shift Right Long by variable
9359 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9360 match(Set dst (URShiftL dst shift));
9361 effect(KILL cr);
9362 ins_cost(600);
9363 size(17);
9364 format %{ "TEST $shift,32\n\t"
9365 "JEQ,s small\n\t"
9366 "MOV $dst.lo,$dst.hi\n\t"
9367 "XOR $dst.hi,$dst.hi\n"
9368 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9369 "SHR $dst.hi,$shift" %}
9370 ins_encode( shift_right_long( dst, shift ) );
9371 ins_pipe( pipe_slow );
9372 %}
9373
9374 // Shift Right Long by 1-31
9375 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9376 match(Set dst (RShiftL dst cnt));
9377 effect(KILL cr);
9378 ins_cost(200);
9379 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9380 "SAR $dst.hi,$cnt" %}
9381 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9382 ins_encode( move_long_small_shift(dst,cnt) );
9383 ins_pipe( ialu_reg_long );
9384 %}
9385
9386 // Shift Right Long by 32-63
9387 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9388 match(Set dst (RShiftL dst cnt));
9389 effect(KILL cr);
9390 ins_cost(300);
9391 format %{ "MOV $dst.lo,$dst.hi\n"
9392 "\tSAR $dst.lo,$cnt-32\n"
9393 "\tSAR $dst.hi,31" %}
9394 opcode(0xC1, 0x7); /* C1 /7 ib */
9395 ins_encode( move_long_big_shift_sign(dst,cnt) );
9396 ins_pipe( ialu_reg_long );
9397 %}
9398
9399 // Shift Right arithmetic Long by variable
9400 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9401 match(Set dst (RShiftL dst shift));
9402 effect(KILL cr);
9403 ins_cost(600);
9404 size(18);
9405 format %{ "TEST $shift,32\n\t"
9406 "JEQ,s small\n\t"
9407 "MOV $dst.lo,$dst.hi\n\t"
9408 "SAR $dst.hi,31\n"
9409 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9410 "SAR $dst.hi,$shift" %}
9411 ins_encode( shift_right_arith_long( dst, shift ) );
9412 ins_pipe( pipe_slow );
9413 %}
9414
9415
9416 //----------Double Instructions------------------------------------------------
9417 // Double Math
9418
9419 // Compare & branch
9420
9421 // P6 version of float compare, sets condition codes in EFLAGS
9422 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9423 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9424 match(Set cr (CmpD src1 src2));
9425 effect(KILL rax);
9426 ins_cost(150);
9427 format %{ "FLD $src1\n\t"
9428 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9429 "JNP exit\n\t"
9430 "MOV ah,1 // saw a NaN, set CF\n\t"
9431 "SAHF\n"
9432 "exit:\tNOP // avoid branch to branch" %}
9433 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9434 ins_encode( Push_Reg_DPR(src1),
9435 OpcP, RegOpc(src2),
9436 cmpF_P6_fixup );
9437 ins_pipe( pipe_slow );
9438 %}
9439
9440 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9441 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9442 match(Set cr (CmpD src1 src2));
9443 ins_cost(150);
9444 format %{ "FLD $src1\n\t"
9445 "FUCOMIP ST,$src2 // P6 instruction" %}
9446 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9447 ins_encode( Push_Reg_DPR(src1),
9448 OpcP, RegOpc(src2));
9449 ins_pipe( pipe_slow );
9450 %}
9451
9452 // Compare & branch
9453 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9454 predicate(UseSSE<=1);
9455 match(Set cr (CmpD src1 src2));
9456 effect(KILL rax);
9457 ins_cost(200);
9458 format %{ "FLD $src1\n\t"
9459 "FCOMp $src2\n\t"
9460 "FNSTSW AX\n\t"
9461 "TEST AX,0x400\n\t"
9462 "JZ,s flags\n\t"
9463 "MOV AH,1\t# unordered treat as LT\n"
9464 "flags:\tSAHF" %}
9465 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9466 ins_encode( Push_Reg_DPR(src1),
9467 OpcP, RegOpc(src2),
9468 fpu_flags);
9469 ins_pipe( pipe_slow );
9470 %}
9471
9472 // Compare vs zero into -1,0,1
9473 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9474 predicate(UseSSE<=1);
9475 match(Set dst (CmpD3 src1 zero));
9476 effect(KILL cr, KILL rax);
9477 ins_cost(280);
9478 format %{ "FTSTD $dst,$src1" %}
9479 opcode(0xE4, 0xD9);
9480 ins_encode( Push_Reg_DPR(src1),
9481 OpcS, OpcP, PopFPU,
9482 CmpF_Result(dst));
9483 ins_pipe( pipe_slow );
9484 %}
9485
9486 // Compare into -1,0,1
9487 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9488 predicate(UseSSE<=1);
9489 match(Set dst (CmpD3 src1 src2));
9490 effect(KILL cr, KILL rax);
9491 ins_cost(300);
9492 format %{ "FCMPD $dst,$src1,$src2" %}
9493 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9494 ins_encode( Push_Reg_DPR(src1),
9495 OpcP, RegOpc(src2),
9496 CmpF_Result(dst));
9497 ins_pipe( pipe_slow );
9498 %}
9499
9500 // float compare and set condition codes in EFLAGS by XMM regs
9501 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9502 predicate(UseSSE>=2);
9503 match(Set cr (CmpD src1 src2));
9504 ins_cost(145);
9505 format %{ "UCOMISD $src1,$src2\n\t"
9506 "JNP,s exit\n\t"
9507 "PUSHF\t# saw NaN, set CF\n\t"
9508 "AND [rsp], #0xffffff2b\n\t"
9509 "POPF\n"
9510 "exit:" %}
9511 ins_encode %{
9512 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9513 emit_cmpfp_fixup(_masm);
9514 %}
9515 ins_pipe( pipe_slow );
9516 %}
9517
9518 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9519 predicate(UseSSE>=2);
9520 match(Set cr (CmpD src1 src2));
9521 ins_cost(100);
9522 format %{ "UCOMISD $src1,$src2" %}
9523 ins_encode %{
9524 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9525 %}
9526 ins_pipe( pipe_slow );
9527 %}
9528
9529 // float compare and set condition codes in EFLAGS by XMM regs
9530 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9531 predicate(UseSSE>=2);
9532 match(Set cr (CmpD src1 (LoadD src2)));
9533 ins_cost(145);
9534 format %{ "UCOMISD $src1,$src2\n\t"
9535 "JNP,s exit\n\t"
9536 "PUSHF\t# saw NaN, set CF\n\t"
9537 "AND [rsp], #0xffffff2b\n\t"
9538 "POPF\n"
9539 "exit:" %}
9540 ins_encode %{
9541 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9542 emit_cmpfp_fixup(_masm);
9543 %}
9544 ins_pipe( pipe_slow );
9545 %}
9546
9547 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9548 predicate(UseSSE>=2);
9549 match(Set cr (CmpD src1 (LoadD src2)));
9550 ins_cost(100);
9551 format %{ "UCOMISD $src1,$src2" %}
9552 ins_encode %{
9553 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9554 %}
9555 ins_pipe( pipe_slow );
9556 %}
9557
9558 // Compare into -1,0,1 in XMM
9559 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9560 predicate(UseSSE>=2);
9561 match(Set dst (CmpD3 src1 src2));
9562 effect(KILL cr);
9563 ins_cost(255);
9564 format %{ "UCOMISD $src1, $src2\n\t"
9565 "MOV $dst, #-1\n\t"
9566 "JP,s done\n\t"
9567 "JB,s done\n\t"
9568 "SETNE $dst\n\t"
9569 "MOVZB $dst, $dst\n"
9570 "done:" %}
9571 ins_encode %{
9572 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9573 emit_cmpfp3(_masm, $dst$$Register);
9574 %}
9575 ins_pipe( pipe_slow );
9576 %}
9577
9578 // Compare into -1,0,1 in XMM and memory
9579 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9580 predicate(UseSSE>=2);
9581 match(Set dst (CmpD3 src1 (LoadD src2)));
9582 effect(KILL cr);
9583 ins_cost(275);
9584 format %{ "UCOMISD $src1, $src2\n\t"
9585 "MOV $dst, #-1\n\t"
9586 "JP,s done\n\t"
9587 "JB,s done\n\t"
9588 "SETNE $dst\n\t"
9589 "MOVZB $dst, $dst\n"
9590 "done:" %}
9591 ins_encode %{
9592 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9593 emit_cmpfp3(_masm, $dst$$Register);
9594 %}
9595 ins_pipe( pipe_slow );
9596 %}
9597
9598
9599 instruct subDPR_reg(regDPR dst, regDPR src) %{
9600 predicate (UseSSE <=1);
9601 match(Set dst (SubD dst src));
9602
9603 format %{ "FLD $src\n\t"
9604 "DSUBp $dst,ST" %}
9605 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9606 ins_cost(150);
9607 ins_encode( Push_Reg_DPR(src),
9608 OpcP, RegOpc(dst) );
9609 ins_pipe( fpu_reg_reg );
9610 %}
9611
9612 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9613 predicate (UseSSE <=1);
9614 match(Set dst (RoundDouble (SubD src1 src2)));
9615 ins_cost(250);
9616
9617 format %{ "FLD $src2\n\t"
9618 "DSUB ST,$src1\n\t"
9619 "FSTP_D $dst\t# D-round" %}
9620 opcode(0xD8, 0x5);
9621 ins_encode( Push_Reg_DPR(src2),
9622 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9623 ins_pipe( fpu_mem_reg_reg );
9624 %}
9625
9626
9627 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9628 predicate (UseSSE <=1);
9629 match(Set dst (SubD dst (LoadD src)));
9630 ins_cost(150);
9631
9632 format %{ "FLD $src\n\t"
9633 "DSUBp $dst,ST" %}
9634 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9635 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9636 OpcP, RegOpc(dst) );
9637 ins_pipe( fpu_reg_mem );
9638 %}
9639
9640 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9641 predicate (UseSSE<=1);
9642 match(Set dst (AbsD src));
9643 ins_cost(100);
9644 format %{ "FABS" %}
9645 opcode(0xE1, 0xD9);
9646 ins_encode( OpcS, OpcP );
9647 ins_pipe( fpu_reg_reg );
9648 %}
9649
9650 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9651 predicate(UseSSE<=1);
9652 match(Set dst (NegD src));
9653 ins_cost(100);
9654 format %{ "FCHS" %}
9655 opcode(0xE0, 0xD9);
9656 ins_encode( OpcS, OpcP );
9657 ins_pipe( fpu_reg_reg );
9658 %}
9659
9660 instruct addDPR_reg(regDPR dst, regDPR src) %{
9661 predicate(UseSSE<=1);
9662 match(Set dst (AddD dst src));
9663 format %{ "FLD $src\n\t"
9664 "DADD $dst,ST" %}
9665 size(4);
9666 ins_cost(150);
9667 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9668 ins_encode( Push_Reg_DPR(src),
9669 OpcP, RegOpc(dst) );
9670 ins_pipe( fpu_reg_reg );
9671 %}
9672
9673
9674 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9675 predicate(UseSSE<=1);
9676 match(Set dst (RoundDouble (AddD src1 src2)));
9677 ins_cost(250);
9678
9679 format %{ "FLD $src2\n\t"
9680 "DADD ST,$src1\n\t"
9681 "FSTP_D $dst\t# D-round" %}
9682 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9683 ins_encode( Push_Reg_DPR(src2),
9684 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9685 ins_pipe( fpu_mem_reg_reg );
9686 %}
9687
9688
9689 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9690 predicate(UseSSE<=1);
9691 match(Set dst (AddD dst (LoadD src)));
9692 ins_cost(150);
9693
9694 format %{ "FLD $src\n\t"
9695 "DADDp $dst,ST" %}
9696 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9697 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9698 OpcP, RegOpc(dst) );
9699 ins_pipe( fpu_reg_mem );
9700 %}
9701
9702 // add-to-memory
9703 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9704 predicate(UseSSE<=1);
9705 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9706 ins_cost(150);
9707
9708 format %{ "FLD_D $dst\n\t"
9709 "DADD ST,$src\n\t"
9710 "FST_D $dst" %}
9711 opcode(0xDD, 0x0);
9712 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9713 Opcode(0xD8), RegOpc(src),
9714 set_instruction_start,
9715 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9716 ins_pipe( fpu_reg_mem );
9717 %}
9718
9719 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9720 predicate(UseSSE<=1);
9721 match(Set dst (AddD dst con));
9722 ins_cost(125);
9723 format %{ "FLD1\n\t"
9724 "DADDp $dst,ST" %}
9725 ins_encode %{
9726 __ fld1();
9727 __ faddp($dst$$reg);
9728 %}
9729 ins_pipe(fpu_reg);
9730 %}
9731
9732 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9733 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9734 match(Set dst (AddD dst con));
9735 ins_cost(200);
9736 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9737 "DADDp $dst,ST" %}
9738 ins_encode %{
9739 __ fld_d($constantaddress($con));
9740 __ faddp($dst$$reg);
9741 %}
9742 ins_pipe(fpu_reg_mem);
9743 %}
9744
9745 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9746 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9747 match(Set dst (RoundDouble (AddD src con)));
9748 ins_cost(200);
9749 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9750 "DADD ST,$src\n\t"
9751 "FSTP_D $dst\t# D-round" %}
9752 ins_encode %{
9753 __ fld_d($constantaddress($con));
9754 __ fadd($src$$reg);
9755 __ fstp_d(Address(rsp, $dst$$disp));
9756 %}
9757 ins_pipe(fpu_mem_reg_con);
9758 %}
9759
9760 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9761 predicate(UseSSE<=1);
9762 match(Set dst (MulD dst src));
9763 format %{ "FLD $src\n\t"
9764 "DMULp $dst,ST" %}
9765 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9766 ins_cost(150);
9767 ins_encode( Push_Reg_DPR(src),
9768 OpcP, RegOpc(dst) );
9769 ins_pipe( fpu_reg_reg );
9770 %}
9771
9772 // Strict FP instruction biases argument before multiply then
9773 // biases result to avoid double rounding of subnormals.
9774 //
9775 // scale arg1 by multiplying arg1 by 2^(-15360)
9776 // load arg2
9777 // multiply scaled arg1 by arg2
9778 // rescale product by 2^(15360)
9779 //
9780 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9781 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9782 match(Set dst (MulD dst src));
9783 ins_cost(1); // Select this instruction for all strict FP double multiplies
9784
9785 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9786 "DMULp $dst,ST\n\t"
9787 "FLD $src\n\t"
9788 "DMULp $dst,ST\n\t"
9789 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9790 "DMULp $dst,ST\n\t" %}
9791 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9792 ins_encode( strictfp_bias1(dst),
9793 Push_Reg_DPR(src),
9794 OpcP, RegOpc(dst),
9795 strictfp_bias2(dst) );
9796 ins_pipe( fpu_reg_reg );
9797 %}
9798
9799 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9800 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9801 match(Set dst (MulD dst con));
9802 ins_cost(200);
9803 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9804 "DMULp $dst,ST" %}
9805 ins_encode %{
9806 __ fld_d($constantaddress($con));
9807 __ fmulp($dst$$reg);
9808 %}
9809 ins_pipe(fpu_reg_mem);
9810 %}
9811
9812
9813 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9814 predicate( UseSSE<=1 );
9815 match(Set dst (MulD dst (LoadD src)));
9816 ins_cost(200);
9817 format %{ "FLD_D $src\n\t"
9818 "DMULp $dst,ST" %}
9819 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9820 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9821 OpcP, RegOpc(dst) );
9822 ins_pipe( fpu_reg_mem );
9823 %}
9824
9825 //
9826 // Cisc-alternate to reg-reg multiply
9827 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9828 predicate( UseSSE<=1 );
9829 match(Set dst (MulD src (LoadD mem)));
9830 ins_cost(250);
9831 format %{ "FLD_D $mem\n\t"
9832 "DMUL ST,$src\n\t"
9833 "FSTP_D $dst" %}
9834 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9835 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9836 OpcReg_FPR(src),
9837 Pop_Reg_DPR(dst) );
9838 ins_pipe( fpu_reg_reg_mem );
9839 %}
9840
9841
9842 // MACRO3 -- addDPR a mulDPR
9843 // This instruction is a '2-address' instruction in that the result goes
9844 // back to src2. This eliminates a move from the macro; possibly the
9845 // register allocator will have to add it back (and maybe not).
9846 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9847 predicate( UseSSE<=1 );
9848 match(Set src2 (AddD (MulD src0 src1) src2));
9849 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9850 "DMUL ST,$src1\n\t"
9851 "DADDp $src2,ST" %}
9852 ins_cost(250);
9853 opcode(0xDD); /* LoadD DD /0 */
9854 ins_encode( Push_Reg_FPR(src0),
9855 FMul_ST_reg(src1),
9856 FAddP_reg_ST(src2) );
9857 ins_pipe( fpu_reg_reg_reg );
9858 %}
9859
9860
9861 // MACRO3 -- subDPR a mulDPR
9862 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9863 predicate( UseSSE<=1 );
9864 match(Set src2 (SubD (MulD src0 src1) src2));
9865 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9866 "DMUL ST,$src1\n\t"
9867 "DSUBRp $src2,ST" %}
9868 ins_cost(250);
9869 ins_encode( Push_Reg_FPR(src0),
9870 FMul_ST_reg(src1),
9871 Opcode(0xDE), Opc_plus(0xE0,src2));
9872 ins_pipe( fpu_reg_reg_reg );
9873 %}
9874
9875
9876 instruct divDPR_reg(regDPR dst, regDPR src) %{
9877 predicate( UseSSE<=1 );
9878 match(Set dst (DivD dst src));
9879
9880 format %{ "FLD $src\n\t"
9881 "FDIVp $dst,ST" %}
9882 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9883 ins_cost(150);
9884 ins_encode( Push_Reg_DPR(src),
9885 OpcP, RegOpc(dst) );
9886 ins_pipe( fpu_reg_reg );
9887 %}
9888
9889 // Strict FP instruction biases argument before division then
9890 // biases result, to avoid double rounding of subnormals.
9891 //
9892 // scale dividend by multiplying dividend by 2^(-15360)
9893 // load divisor
9894 // divide scaled dividend by divisor
9895 // rescale quotient by 2^(15360)
9896 //
9897 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9898 predicate (UseSSE<=1);
9899 match(Set dst (DivD dst src));
9900 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9901 ins_cost(01);
9902
9903 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9904 "DMULp $dst,ST\n\t"
9905 "FLD $src\n\t"
9906 "FDIVp $dst,ST\n\t"
9907 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9908 "DMULp $dst,ST\n\t" %}
9909 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9910 ins_encode( strictfp_bias1(dst),
9911 Push_Reg_DPR(src),
9912 OpcP, RegOpc(dst),
9913 strictfp_bias2(dst) );
9914 ins_pipe( fpu_reg_reg );
9915 %}
9916
9917 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9918 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9919 match(Set dst (RoundDouble (DivD src1 src2)));
9920
9921 format %{ "FLD $src1\n\t"
9922 "FDIV ST,$src2\n\t"
9923 "FSTP_D $dst\t# D-round" %}
9924 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9925 ins_encode( Push_Reg_DPR(src1),
9926 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9927 ins_pipe( fpu_mem_reg_reg );
9928 %}
9929
9930
9931 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9932 predicate(UseSSE<=1);
9933 match(Set dst (ModD dst src));
9934 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9935
9936 format %{ "DMOD $dst,$src" %}
9937 ins_cost(250);
9938 ins_encode(Push_Reg_Mod_DPR(dst, src),
9939 emitModDPR(),
9940 Push_Result_Mod_DPR(src),
9941 Pop_Reg_DPR(dst));
9942 ins_pipe( pipe_slow );
9943 %}
9944
9945 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9946 predicate(UseSSE>=2);
9947 match(Set dst (ModD src0 src1));
9948 effect(KILL rax, KILL cr);
9949
9950 format %{ "SUB ESP,8\t # DMOD\n"
9951 "\tMOVSD [ESP+0],$src1\n"
9952 "\tFLD_D [ESP+0]\n"
9953 "\tMOVSD [ESP+0],$src0\n"
9954 "\tFLD_D [ESP+0]\n"
9955 "loop:\tFPREM\n"
9956 "\tFWAIT\n"
9957 "\tFNSTSW AX\n"
9958 "\tSAHF\n"
9959 "\tJP loop\n"
9960 "\tFSTP_D [ESP+0]\n"
9961 "\tMOVSD $dst,[ESP+0]\n"
9962 "\tADD ESP,8\n"
9963 "\tFSTP ST0\t # Restore FPU Stack"
9964 %}
9965 ins_cost(250);
9966 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9967 ins_pipe( pipe_slow );
9968 %}
9969
9970 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9971 predicate (UseSSE<=1);
9972 match(Set dst (SinD src));
9973 ins_cost(1800);
9974 format %{ "DSIN $dst" %}
9975 opcode(0xD9, 0xFE);
9976 ins_encode( OpcP, OpcS );
9977 ins_pipe( pipe_slow );
9978 %}
9979
9980 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9981 predicate (UseSSE>=2);
9982 match(Set dst (SinD dst));
9983 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9984 ins_cost(1800);
9985 format %{ "DSIN $dst" %}
9986 opcode(0xD9, 0xFE);
9987 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9988 ins_pipe( pipe_slow );
9989 %}
9990
9991 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9992 predicate (UseSSE<=1);
9993 match(Set dst (CosD src));
9994 ins_cost(1800);
9995 format %{ "DCOS $dst" %}
9996 opcode(0xD9, 0xFF);
9997 ins_encode( OpcP, OpcS );
9998 ins_pipe( pipe_slow );
9999 %}
10000
10001 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10002 predicate (UseSSE>=2);
10003 match(Set dst (CosD dst));
10004 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10005 ins_cost(1800);
10006 format %{ "DCOS $dst" %}
10007 opcode(0xD9, 0xFF);
10008 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10009 ins_pipe( pipe_slow );
10010 %}
10011
10012 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10013 predicate (UseSSE<=1);
10014 match(Set dst(TanD src));
10015 format %{ "DTAN $dst" %}
10016 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10017 Opcode(0xDD), Opcode(0xD8)); // fstp st
10018 ins_pipe( pipe_slow );
10019 %}
10020
10021 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10022 predicate (UseSSE>=2);
10023 match(Set dst(TanD dst));
10024 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10025 format %{ "DTAN $dst" %}
10026 ins_encode( Push_SrcD(dst),
10027 Opcode(0xD9), Opcode(0xF2), // fptan
10028 Opcode(0xDD), Opcode(0xD8), // fstp st
10029 Push_ResultD(dst) );
10030 ins_pipe( pipe_slow );
10031 %}
10032
10033 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10034 predicate (UseSSE<=1);
10035 match(Set dst(AtanD dst src));
10036 format %{ "DATA $dst,$src" %}
10037 opcode(0xD9, 0xF3);
10038 ins_encode( Push_Reg_DPR(src),
10039 OpcP, OpcS, RegOpc(dst) );
10040 ins_pipe( pipe_slow );
10041 %}
10042
10043 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10044 predicate (UseSSE>=2);
10045 match(Set dst(AtanD dst src));
10046 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10047 format %{ "DATA $dst,$src" %}
10048 opcode(0xD9, 0xF3);
10049 ins_encode( Push_SrcD(src),
10050 OpcP, OpcS, Push_ResultD(dst) );
10051 ins_pipe( pipe_slow );
10052 %}
10053
10054 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10055 predicate (UseSSE<=1);
10056 match(Set dst (SqrtD src));
10057 format %{ "DSQRT $dst,$src" %}
10058 opcode(0xFA, 0xD9);
10059 ins_encode( Push_Reg_DPR(src),
10060 OpcS, OpcP, Pop_Reg_DPR(dst) );
10061 ins_pipe( pipe_slow );
10062 %}
10063
10064 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10065 predicate (UseSSE<=1);
10066 match(Set Y (PowD X Y)); // Raise X to the Yth power
10067 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10068 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10069 ins_encode %{
10070 __ subptr(rsp, 8);
10071 __ fld_s($X$$reg - 1);
10072 __ fast_pow();
10073 __ addptr(rsp, 8);
10074 %}
10075 ins_pipe( pipe_slow );
10076 %}
10077
10078 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10079 predicate (UseSSE>=2);
10080 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10081 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10082 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10083 ins_encode %{
10084 __ subptr(rsp, 8);
10085 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10086 __ fld_d(Address(rsp, 0));
10087 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10088 __ fld_d(Address(rsp, 0));
10089 __ fast_pow();
10090 __ fstp_d(Address(rsp, 0));
10091 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10092 __ addptr(rsp, 8);
10093 %}
10094 ins_pipe( pipe_slow );
10095 %}
10096
10097
10098 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10099 predicate (UseSSE<=1);
10100 match(Set dpr1 (ExpD dpr1));
10101 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10102 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10103 ins_encode %{
10104 __ fast_exp();
10105 %}
10106 ins_pipe( pipe_slow );
10107 %}
10108
10109 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10110 predicate (UseSSE>=2);
10111 match(Set dst (ExpD src));
10112 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10113 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10114 ins_encode %{
10115 __ subptr(rsp, 8);
10116 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10117 __ fld_d(Address(rsp, 0));
10118 __ fast_exp();
10119 __ fstp_d(Address(rsp, 0));
10120 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10121 __ addptr(rsp, 8);
10122 %}
10123 ins_pipe( pipe_slow );
10124 %}
10125
10126 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10127 predicate (UseSSE<=1);
10128 // The source Double operand on FPU stack
10129 match(Set dst (Log10D src));
10130 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10131 // fxch ; swap ST(0) with ST(1)
10132 // fyl2x ; compute log_10(2) * log_2(x)
10133 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10134 "FXCH \n\t"
10135 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10136 %}
10137 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10138 Opcode(0xD9), Opcode(0xC9), // fxch
10139 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10140
10141 ins_pipe( pipe_slow );
10142 %}
10143
10144 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10145 predicate (UseSSE>=2);
10146 effect(KILL cr);
10147 match(Set dst (Log10D src));
10148 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10149 // fyl2x ; compute log_10(2) * log_2(x)
10150 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10151 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10152 %}
10153 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10154 Push_SrcD(src),
10155 Opcode(0xD9), Opcode(0xF1), // fyl2x
10156 Push_ResultD(dst));
10157
10158 ins_pipe( pipe_slow );
10159 %}
10160
10161 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10162 predicate (UseSSE<=1);
10163 // The source Double operand on FPU stack
10164 match(Set dst (LogD src));
10165 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10166 // fxch ; swap ST(0) with ST(1)
10167 // fyl2x ; compute log_e(2) * log_2(x)
10168 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10169 "FXCH \n\t"
10170 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10171 %}
10172 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10173 Opcode(0xD9), Opcode(0xC9), // fxch
10174 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10175
10176 ins_pipe( pipe_slow );
10177 %}
10178
10179 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10180 predicate (UseSSE>=2);
10181 effect(KILL cr);
10182 // The source and result Double operands in XMM registers
10183 match(Set dst (LogD src));
10184 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10185 // fyl2x ; compute log_e(2) * log_2(x)
10186 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10187 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10188 %}
10189 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10190 Push_SrcD(src),
10191 Opcode(0xD9), Opcode(0xF1), // fyl2x
10192 Push_ResultD(dst));
10193 ins_pipe( pipe_slow );
10194 %}
10195
10196 //-------------Float Instructions-------------------------------
10197 // Float Math
10198
10199 // Code for float compare:
10200 // fcompp();
10201 // fwait(); fnstsw_ax();
10202 // sahf();
10203 // movl(dst, unordered_result);
10204 // jcc(Assembler::parity, exit);
10205 // movl(dst, less_result);
10206 // jcc(Assembler::below, exit);
10207 // movl(dst, equal_result);
10208 // jcc(Assembler::equal, exit);
10209 // movl(dst, greater_result);
10210 // exit:
10211
10212 // P6 version of float compare, sets condition codes in EFLAGS
10213 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10214 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10215 match(Set cr (CmpF src1 src2));
10216 effect(KILL rax);
10217 ins_cost(150);
10218 format %{ "FLD $src1\n\t"
10219 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10220 "JNP exit\n\t"
10221 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10222 "SAHF\n"
10223 "exit:\tNOP // avoid branch to branch" %}
10224 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10225 ins_encode( Push_Reg_DPR(src1),
10226 OpcP, RegOpc(src2),
10227 cmpF_P6_fixup );
10228 ins_pipe( pipe_slow );
10229 %}
10230
10231 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10232 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10233 match(Set cr (CmpF src1 src2));
10234 ins_cost(100);
10235 format %{ "FLD $src1\n\t"
10236 "FUCOMIP ST,$src2 // P6 instruction" %}
10237 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10238 ins_encode( Push_Reg_DPR(src1),
10239 OpcP, RegOpc(src2));
10240 ins_pipe( pipe_slow );
10241 %}
10242
10243
10244 // Compare & branch
10245 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10246 predicate(UseSSE == 0);
10247 match(Set cr (CmpF src1 src2));
10248 effect(KILL rax);
10249 ins_cost(200);
10250 format %{ "FLD $src1\n\t"
10251 "FCOMp $src2\n\t"
10252 "FNSTSW AX\n\t"
10253 "TEST AX,0x400\n\t"
10254 "JZ,s flags\n\t"
10255 "MOV AH,1\t# unordered treat as LT\n"
10256 "flags:\tSAHF" %}
10257 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10258 ins_encode( Push_Reg_DPR(src1),
10259 OpcP, RegOpc(src2),
10260 fpu_flags);
10261 ins_pipe( pipe_slow );
10262 %}
10263
10264 // Compare vs zero into -1,0,1
10265 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10266 predicate(UseSSE == 0);
10267 match(Set dst (CmpF3 src1 zero));
10268 effect(KILL cr, KILL rax);
10269 ins_cost(280);
10270 format %{ "FTSTF $dst,$src1" %}
10271 opcode(0xE4, 0xD9);
10272 ins_encode( Push_Reg_DPR(src1),
10273 OpcS, OpcP, PopFPU,
10274 CmpF_Result(dst));
10275 ins_pipe( pipe_slow );
10276 %}
10277
10278 // Compare into -1,0,1
10279 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10280 predicate(UseSSE == 0);
10281 match(Set dst (CmpF3 src1 src2));
10282 effect(KILL cr, KILL rax);
10283 ins_cost(300);
10284 format %{ "FCMPF $dst,$src1,$src2" %}
10285 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10286 ins_encode( Push_Reg_DPR(src1),
10287 OpcP, RegOpc(src2),
10288 CmpF_Result(dst));
10289 ins_pipe( pipe_slow );
10290 %}
10291
10292 // float compare and set condition codes in EFLAGS by XMM regs
10293 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10294 predicate(UseSSE>=1);
10295 match(Set cr (CmpF src1 src2));
10296 ins_cost(145);
10297 format %{ "UCOMISS $src1,$src2\n\t"
10298 "JNP,s exit\n\t"
10299 "PUSHF\t# saw NaN, set CF\n\t"
10300 "AND [rsp], #0xffffff2b\n\t"
10301 "POPF\n"
10302 "exit:" %}
10303 ins_encode %{
10304 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10305 emit_cmpfp_fixup(_masm);
10306 %}
10307 ins_pipe( pipe_slow );
10308 %}
10309
10310 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10311 predicate(UseSSE>=1);
10312 match(Set cr (CmpF src1 src2));
10313 ins_cost(100);
10314 format %{ "UCOMISS $src1,$src2" %}
10315 ins_encode %{
10316 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10317 %}
10318 ins_pipe( pipe_slow );
10319 %}
10320
10321 // float compare and set condition codes in EFLAGS by XMM regs
10322 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10323 predicate(UseSSE>=1);
10324 match(Set cr (CmpF src1 (LoadF src2)));
10325 ins_cost(165);
10326 format %{ "UCOMISS $src1,$src2\n\t"
10327 "JNP,s exit\n\t"
10328 "PUSHF\t# saw NaN, set CF\n\t"
10329 "AND [rsp], #0xffffff2b\n\t"
10330 "POPF\n"
10331 "exit:" %}
10332 ins_encode %{
10333 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10334 emit_cmpfp_fixup(_masm);
10335 %}
10336 ins_pipe( pipe_slow );
10337 %}
10338
10339 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10340 predicate(UseSSE>=1);
10341 match(Set cr (CmpF src1 (LoadF src2)));
10342 ins_cost(100);
10343 format %{ "UCOMISS $src1,$src2" %}
10344 ins_encode %{
10345 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10346 %}
10347 ins_pipe( pipe_slow );
10348 %}
10349
10350 // Compare into -1,0,1 in XMM
10351 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10352 predicate(UseSSE>=1);
10353 match(Set dst (CmpF3 src1 src2));
10354 effect(KILL cr);
10355 ins_cost(255);
10356 format %{ "UCOMISS $src1, $src2\n\t"
10357 "MOV $dst, #-1\n\t"
10358 "JP,s done\n\t"
10359 "JB,s done\n\t"
10360 "SETNE $dst\n\t"
10361 "MOVZB $dst, $dst\n"
10362 "done:" %}
10363 ins_encode %{
10364 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10365 emit_cmpfp3(_masm, $dst$$Register);
10366 %}
10367 ins_pipe( pipe_slow );
10368 %}
10369
10370 // Compare into -1,0,1 in XMM and memory
10371 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10372 predicate(UseSSE>=1);
10373 match(Set dst (CmpF3 src1 (LoadF src2)));
10374 effect(KILL cr);
10375 ins_cost(275);
10376 format %{ "UCOMISS $src1, $src2\n\t"
10377 "MOV $dst, #-1\n\t"
10378 "JP,s done\n\t"
10379 "JB,s done\n\t"
10380 "SETNE $dst\n\t"
10381 "MOVZB $dst, $dst\n"
10382 "done:" %}
10383 ins_encode %{
10384 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10385 emit_cmpfp3(_masm, $dst$$Register);
10386 %}
10387 ins_pipe( pipe_slow );
10388 %}
10389
10390 // Spill to obtain 24-bit precision
10391 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10392 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10393 match(Set dst (SubF src1 src2));
10394
10395 format %{ "FSUB $dst,$src1 - $src2" %}
10396 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10397 ins_encode( Push_Reg_FPR(src1),
10398 OpcReg_FPR(src2),
10399 Pop_Mem_FPR(dst) );
10400 ins_pipe( fpu_mem_reg_reg );
10401 %}
10402 //
10403 // This instruction does not round to 24-bits
10404 instruct subFPR_reg(regFPR dst, regFPR src) %{
10405 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10406 match(Set dst (SubF dst src));
10407
10408 format %{ "FSUB $dst,$src" %}
10409 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10410 ins_encode( Push_Reg_FPR(src),
10411 OpcP, RegOpc(dst) );
10412 ins_pipe( fpu_reg_reg );
10413 %}
10414
10415 // Spill to obtain 24-bit precision
10416 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10417 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10418 match(Set dst (AddF src1 src2));
10419
10420 format %{ "FADD $dst,$src1,$src2" %}
10421 opcode(0xD8, 0x0); /* D8 C0+i */
10422 ins_encode( Push_Reg_FPR(src2),
10423 OpcReg_FPR(src1),
10424 Pop_Mem_FPR(dst) );
10425 ins_pipe( fpu_mem_reg_reg );
10426 %}
10427 //
10428 // This instruction does not round to 24-bits
10429 instruct addFPR_reg(regFPR dst, regFPR src) %{
10430 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10431 match(Set dst (AddF dst src));
10432
10433 format %{ "FLD $src\n\t"
10434 "FADDp $dst,ST" %}
10435 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10436 ins_encode( Push_Reg_FPR(src),
10437 OpcP, RegOpc(dst) );
10438 ins_pipe( fpu_reg_reg );
10439 %}
10440
10441 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10442 predicate(UseSSE==0);
10443 match(Set dst (AbsF src));
10444 ins_cost(100);
10445 format %{ "FABS" %}
10446 opcode(0xE1, 0xD9);
10447 ins_encode( OpcS, OpcP );
10448 ins_pipe( fpu_reg_reg );
10449 %}
10450
10451 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10452 predicate(UseSSE==0);
10453 match(Set dst (NegF src));
10454 ins_cost(100);
10455 format %{ "FCHS" %}
10456 opcode(0xE0, 0xD9);
10457 ins_encode( OpcS, OpcP );
10458 ins_pipe( fpu_reg_reg );
10459 %}
10460
10461 // Cisc-alternate to addFPR_reg
10462 // Spill to obtain 24-bit precision
10463 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10464 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10465 match(Set dst (AddF src1 (LoadF src2)));
10466
10467 format %{ "FLD $src2\n\t"
10468 "FADD ST,$src1\n\t"
10469 "FSTP_S $dst" %}
10470 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10471 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10472 OpcReg_FPR(src1),
10473 Pop_Mem_FPR(dst) );
10474 ins_pipe( fpu_mem_reg_mem );
10475 %}
10476 //
10477 // Cisc-alternate to addFPR_reg
10478 // This instruction does not round to 24-bits
10479 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10480 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10481 match(Set dst (AddF dst (LoadF src)));
10482
10483 format %{ "FADD $dst,$src" %}
10484 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10485 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10486 OpcP, RegOpc(dst) );
10487 ins_pipe( fpu_reg_mem );
10488 %}
10489
10490 // // Following two instructions for _222_mpegaudio
10491 // Spill to obtain 24-bit precision
10492 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10493 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10494 match(Set dst (AddF src1 src2));
10495
10496 format %{ "FADD $dst,$src1,$src2" %}
10497 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10498 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10499 OpcReg_FPR(src2),
10500 Pop_Mem_FPR(dst) );
10501 ins_pipe( fpu_mem_reg_mem );
10502 %}
10503
10504 // Cisc-spill variant
10505 // Spill to obtain 24-bit precision
10506 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10507 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10508 match(Set dst (AddF src1 (LoadF src2)));
10509
10510 format %{ "FADD $dst,$src1,$src2 cisc" %}
10511 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10512 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10513 set_instruction_start,
10514 OpcP, RMopc_Mem(secondary,src1),
10515 Pop_Mem_FPR(dst) );
10516 ins_pipe( fpu_mem_mem_mem );
10517 %}
10518
10519 // Spill to obtain 24-bit precision
10520 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10521 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10522 match(Set dst (AddF src1 src2));
10523
10524 format %{ "FADD $dst,$src1,$src2" %}
10525 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10526 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10527 set_instruction_start,
10528 OpcP, RMopc_Mem(secondary,src1),
10529 Pop_Mem_FPR(dst) );
10530 ins_pipe( fpu_mem_mem_mem );
10531 %}
10532
10533
10534 // Spill to obtain 24-bit precision
10535 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10536 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10537 match(Set dst (AddF src con));
10538 format %{ "FLD $src\n\t"
10539 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10540 "FSTP_S $dst" %}
10541 ins_encode %{
10542 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10543 __ fadd_s($constantaddress($con));
10544 __ fstp_s(Address(rsp, $dst$$disp));
10545 %}
10546 ins_pipe(fpu_mem_reg_con);
10547 %}
10548 //
10549 // This instruction does not round to 24-bits
10550 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10551 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10552 match(Set dst (AddF src con));
10553 format %{ "FLD $src\n\t"
10554 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10555 "FSTP $dst" %}
10556 ins_encode %{
10557 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10558 __ fadd_s($constantaddress($con));
10559 __ fstp_d($dst$$reg);
10560 %}
10561 ins_pipe(fpu_reg_reg_con);
10562 %}
10563
10564 // Spill to obtain 24-bit precision
10565 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10566 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10567 match(Set dst (MulF src1 src2));
10568
10569 format %{ "FLD $src1\n\t"
10570 "FMUL $src2\n\t"
10571 "FSTP_S $dst" %}
10572 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10573 ins_encode( Push_Reg_FPR(src1),
10574 OpcReg_FPR(src2),
10575 Pop_Mem_FPR(dst) );
10576 ins_pipe( fpu_mem_reg_reg );
10577 %}
10578 //
10579 // This instruction does not round to 24-bits
10580 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10581 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10582 match(Set dst (MulF src1 src2));
10583
10584 format %{ "FLD $src1\n\t"
10585 "FMUL $src2\n\t"
10586 "FSTP_S $dst" %}
10587 opcode(0xD8, 0x1); /* D8 C8+i */
10588 ins_encode( Push_Reg_FPR(src2),
10589 OpcReg_FPR(src1),
10590 Pop_Reg_FPR(dst) );
10591 ins_pipe( fpu_reg_reg_reg );
10592 %}
10593
10594
10595 // Spill to obtain 24-bit precision
10596 // Cisc-alternate to reg-reg multiply
10597 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10598 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10599 match(Set dst (MulF src1 (LoadF src2)));
10600
10601 format %{ "FLD_S $src2\n\t"
10602 "FMUL $src1\n\t"
10603 "FSTP_S $dst" %}
10604 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10605 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10606 OpcReg_FPR(src1),
10607 Pop_Mem_FPR(dst) );
10608 ins_pipe( fpu_mem_reg_mem );
10609 %}
10610 //
10611 // This instruction does not round to 24-bits
10612 // Cisc-alternate to reg-reg multiply
10613 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10614 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10615 match(Set dst (MulF src1 (LoadF src2)));
10616
10617 format %{ "FMUL $dst,$src1,$src2" %}
10618 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10619 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10620 OpcReg_FPR(src1),
10621 Pop_Reg_FPR(dst) );
10622 ins_pipe( fpu_reg_reg_mem );
10623 %}
10624
10625 // Spill to obtain 24-bit precision
10626 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10627 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10628 match(Set dst (MulF src1 src2));
10629
10630 format %{ "FMUL $dst,$src1,$src2" %}
10631 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10632 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10633 set_instruction_start,
10634 OpcP, RMopc_Mem(secondary,src1),
10635 Pop_Mem_FPR(dst) );
10636 ins_pipe( fpu_mem_mem_mem );
10637 %}
10638
10639 // Spill to obtain 24-bit precision
10640 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10641 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10642 match(Set dst (MulF src con));
10643
10644 format %{ "FLD $src\n\t"
10645 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10646 "FSTP_S $dst" %}
10647 ins_encode %{
10648 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10649 __ fmul_s($constantaddress($con));
10650 __ fstp_s(Address(rsp, $dst$$disp));
10651 %}
10652 ins_pipe(fpu_mem_reg_con);
10653 %}
10654 //
10655 // This instruction does not round to 24-bits
10656 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10657 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10658 match(Set dst (MulF src con));
10659
10660 format %{ "FLD $src\n\t"
10661 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10662 "FSTP $dst" %}
10663 ins_encode %{
10664 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10665 __ fmul_s($constantaddress($con));
10666 __ fstp_d($dst$$reg);
10667 %}
10668 ins_pipe(fpu_reg_reg_con);
10669 %}
10670
10671
10672 //
10673 // MACRO1 -- subsume unshared load into mulFPR
10674 // This instruction does not round to 24-bits
10675 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10676 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10677 match(Set dst (MulF (LoadF mem1) src));
10678
10679 format %{ "FLD $mem1 ===MACRO1===\n\t"
10680 "FMUL ST,$src\n\t"
10681 "FSTP $dst" %}
10682 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10683 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10684 OpcReg_FPR(src),
10685 Pop_Reg_FPR(dst) );
10686 ins_pipe( fpu_reg_reg_mem );
10687 %}
10688 //
10689 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10690 // This instruction does not round to 24-bits
10691 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10692 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10693 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10694 ins_cost(95);
10695
10696 format %{ "FLD $mem1 ===MACRO2===\n\t"
10697 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10698 "FADD ST,$src2\n\t"
10699 "FSTP $dst" %}
10700 opcode(0xD9); /* LoadF D9 /0 */
10701 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10702 FMul_ST_reg(src1),
10703 FAdd_ST_reg(src2),
10704 Pop_Reg_FPR(dst) );
10705 ins_pipe( fpu_reg_mem_reg_reg );
10706 %}
10707
10708 // MACRO3 -- addFPR a mulFPR
10709 // This instruction does not round to 24-bits. It is a '2-address'
10710 // instruction in that the result goes back to src2. This eliminates
10711 // a move from the macro; possibly the register allocator will have
10712 // to add it back (and maybe not).
10713 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10714 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10715 match(Set src2 (AddF (MulF src0 src1) src2));
10716
10717 format %{ "FLD $src0 ===MACRO3===\n\t"
10718 "FMUL ST,$src1\n\t"
10719 "FADDP $src2,ST" %}
10720 opcode(0xD9); /* LoadF D9 /0 */
10721 ins_encode( Push_Reg_FPR(src0),
10722 FMul_ST_reg(src1),
10723 FAddP_reg_ST(src2) );
10724 ins_pipe( fpu_reg_reg_reg );
10725 %}
10726
10727 // MACRO4 -- divFPR subFPR
10728 // This instruction does not round to 24-bits
10729 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10730 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10731 match(Set dst (DivF (SubF src2 src1) src3));
10732
10733 format %{ "FLD $src2 ===MACRO4===\n\t"
10734 "FSUB ST,$src1\n\t"
10735 "FDIV ST,$src3\n\t"
10736 "FSTP $dst" %}
10737 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10738 ins_encode( Push_Reg_FPR(src2),
10739 subFPR_divFPR_encode(src1,src3),
10740 Pop_Reg_FPR(dst) );
10741 ins_pipe( fpu_reg_reg_reg_reg );
10742 %}
10743
10744 // Spill to obtain 24-bit precision
10745 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10746 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10747 match(Set dst (DivF src1 src2));
10748
10749 format %{ "FDIV $dst,$src1,$src2" %}
10750 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10751 ins_encode( Push_Reg_FPR(src1),
10752 OpcReg_FPR(src2),
10753 Pop_Mem_FPR(dst) );
10754 ins_pipe( fpu_mem_reg_reg );
10755 %}
10756 //
10757 // This instruction does not round to 24-bits
10758 instruct divFPR_reg(regFPR dst, regFPR src) %{
10759 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10760 match(Set dst (DivF dst src));
10761
10762 format %{ "FDIV $dst,$src" %}
10763 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10764 ins_encode( Push_Reg_FPR(src),
10765 OpcP, RegOpc(dst) );
10766 ins_pipe( fpu_reg_reg );
10767 %}
10768
10769
10770 // Spill to obtain 24-bit precision
10771 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10772 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10773 match(Set dst (ModF src1 src2));
10774 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10775
10776 format %{ "FMOD $dst,$src1,$src2" %}
10777 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10778 emitModDPR(),
10779 Push_Result_Mod_DPR(src2),
10780 Pop_Mem_FPR(dst));
10781 ins_pipe( pipe_slow );
10782 %}
10783 //
10784 // This instruction does not round to 24-bits
10785 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10786 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10787 match(Set dst (ModF dst src));
10788 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10789
10790 format %{ "FMOD $dst,$src" %}
10791 ins_encode(Push_Reg_Mod_DPR(dst, src),
10792 emitModDPR(),
10793 Push_Result_Mod_DPR(src),
10794 Pop_Reg_FPR(dst));
10795 ins_pipe( pipe_slow );
10796 %}
10797
10798 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10799 predicate(UseSSE>=1);
10800 match(Set dst (ModF src0 src1));
10801 effect(KILL rax, KILL cr);
10802 format %{ "SUB ESP,4\t # FMOD\n"
10803 "\tMOVSS [ESP+0],$src1\n"
10804 "\tFLD_S [ESP+0]\n"
10805 "\tMOVSS [ESP+0],$src0\n"
10806 "\tFLD_S [ESP+0]\n"
10807 "loop:\tFPREM\n"
10808 "\tFWAIT\n"
10809 "\tFNSTSW AX\n"
10810 "\tSAHF\n"
10811 "\tJP loop\n"
10812 "\tFSTP_S [ESP+0]\n"
10813 "\tMOVSS $dst,[ESP+0]\n"
10814 "\tADD ESP,4\n"
10815 "\tFSTP ST0\t # Restore FPU Stack"
10816 %}
10817 ins_cost(250);
10818 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10819 ins_pipe( pipe_slow );
10820 %}
10821
10822
10823 //----------Arithmetic Conversion Instructions---------------------------------
10824 // The conversions operations are all Alpha sorted. Please keep it that way!
10825
10826 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10827 predicate(UseSSE==0);
10828 match(Set dst (RoundFloat src));
10829 ins_cost(125);
10830 format %{ "FST_S $dst,$src\t# F-round" %}
10831 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10832 ins_pipe( fpu_mem_reg );
10833 %}
10834
10835 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10836 predicate(UseSSE<=1);
10837 match(Set dst (RoundDouble src));
10838 ins_cost(125);
10839 format %{ "FST_D $dst,$src\t# D-round" %}
10840 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10841 ins_pipe( fpu_mem_reg );
10842 %}
10843
10844 // Force rounding to 24-bit precision and 6-bit exponent
10845 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10846 predicate(UseSSE==0);
10847 match(Set dst (ConvD2F src));
10848 format %{ "FST_S $dst,$src\t# F-round" %}
10849 expand %{
10850 roundFloat_mem_reg(dst,src);
10851 %}
10852 %}
10853
10854 // Force rounding to 24-bit precision and 6-bit exponent
10855 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10856 predicate(UseSSE==1);
10857 match(Set dst (ConvD2F src));
10858 effect( KILL cr );
10859 format %{ "SUB ESP,4\n\t"
10860 "FST_S [ESP],$src\t# F-round\n\t"
10861 "MOVSS $dst,[ESP]\n\t"
10862 "ADD ESP,4" %}
10863 ins_encode %{
10864 __ subptr(rsp, 4);
10865 if ($src$$reg != FPR1L_enc) {
10866 __ fld_s($src$$reg-1);
10867 __ fstp_s(Address(rsp, 0));
10868 } else {
10869 __ fst_s(Address(rsp, 0));
10870 }
10871 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10872 __ addptr(rsp, 4);
10873 %}
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 // Force rounding double precision to single precision
10878 instruct convD2F_reg(regF dst, regD src) %{
10879 predicate(UseSSE>=2);
10880 match(Set dst (ConvD2F src));
10881 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10882 ins_encode %{
10883 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10884 %}
10885 ins_pipe( pipe_slow );
10886 %}
10887
10888 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10889 predicate(UseSSE==0);
10890 match(Set dst (ConvF2D src));
10891 format %{ "FST_S $dst,$src\t# D-round" %}
10892 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10893 ins_pipe( fpu_reg_reg );
10894 %}
10895
10896 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10897 predicate(UseSSE==1);
10898 match(Set dst (ConvF2D src));
10899 format %{ "FST_D $dst,$src\t# D-round" %}
10900 expand %{
10901 roundDouble_mem_reg(dst,src);
10902 %}
10903 %}
10904
10905 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10906 predicate(UseSSE==1);
10907 match(Set dst (ConvF2D src));
10908 effect( KILL cr );
10909 format %{ "SUB ESP,4\n\t"
10910 "MOVSS [ESP] $src\n\t"
10911 "FLD_S [ESP]\n\t"
10912 "ADD ESP,4\n\t"
10913 "FSTP $dst\t# D-round" %}
10914 ins_encode %{
10915 __ subptr(rsp, 4);
10916 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10917 __ fld_s(Address(rsp, 0));
10918 __ addptr(rsp, 4);
10919 __ fstp_d($dst$$reg);
10920 %}
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 instruct convF2D_reg(regD dst, regF src) %{
10925 predicate(UseSSE>=2);
10926 match(Set dst (ConvF2D src));
10927 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10928 ins_encode %{
10929 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10930 %}
10931 ins_pipe( pipe_slow );
10932 %}
10933
10934 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10935 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10936 predicate(UseSSE<=1);
10937 match(Set dst (ConvD2I src));
10938 effect( KILL tmp, KILL cr );
10939 format %{ "FLD $src\t# Convert double to int \n\t"
10940 "FLDCW trunc mode\n\t"
10941 "SUB ESP,4\n\t"
10942 "FISTp [ESP + #0]\n\t"
10943 "FLDCW std/24-bit mode\n\t"
10944 "POP EAX\n\t"
10945 "CMP EAX,0x80000000\n\t"
10946 "JNE,s fast\n\t"
10947 "FLD_D $src\n\t"
10948 "CALL d2i_wrapper\n"
10949 "fast:" %}
10950 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10955 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10956 predicate(UseSSE>=2);
10957 match(Set dst (ConvD2I src));
10958 effect( KILL tmp, KILL cr );
10959 format %{ "CVTTSD2SI $dst, $src\n\t"
10960 "CMP $dst,0x80000000\n\t"
10961 "JNE,s fast\n\t"
10962 "SUB ESP, 8\n\t"
10963 "MOVSD [ESP], $src\n\t"
10964 "FLD_D [ESP]\n\t"
10965 "ADD ESP, 8\n\t"
10966 "CALL d2i_wrapper\n"
10967 "fast:" %}
10968 ins_encode %{
10969 Label fast;
10970 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10971 __ cmpl($dst$$Register, 0x80000000);
10972 __ jccb(Assembler::notEqual, fast);
10973 __ subptr(rsp, 8);
10974 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10975 __ fld_d(Address(rsp, 0));
10976 __ addptr(rsp, 8);
10977 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10978 __ bind(fast);
10979 %}
10980 ins_pipe( pipe_slow );
10981 %}
10982
10983 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10984 predicate(UseSSE<=1);
10985 match(Set dst (ConvD2L src));
10986 effect( KILL cr );
10987 format %{ "FLD $src\t# Convert double to long\n\t"
10988 "FLDCW trunc mode\n\t"
10989 "SUB ESP,8\n\t"
10990 "FISTp [ESP + #0]\n\t"
10991 "FLDCW std/24-bit mode\n\t"
10992 "POP EAX\n\t"
10993 "POP EDX\n\t"
10994 "CMP EDX,0x80000000\n\t"
10995 "JNE,s fast\n\t"
10996 "TEST EAX,EAX\n\t"
10997 "JNE,s fast\n\t"
10998 "FLD $src\n\t"
10999 "CALL d2l_wrapper\n"
11000 "fast:" %}
11001 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11002 ins_pipe( pipe_slow );
11003 %}
11004
11005 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11006 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11007 predicate (UseSSE>=2);
11008 match(Set dst (ConvD2L src));
11009 effect( KILL cr );
11010 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11011 "MOVSD [ESP],$src\n\t"
11012 "FLD_D [ESP]\n\t"
11013 "FLDCW trunc mode\n\t"
11014 "FISTp [ESP + #0]\n\t"
11015 "FLDCW std/24-bit mode\n\t"
11016 "POP EAX\n\t"
11017 "POP EDX\n\t"
11018 "CMP EDX,0x80000000\n\t"
11019 "JNE,s fast\n\t"
11020 "TEST EAX,EAX\n\t"
11021 "JNE,s fast\n\t"
11022 "SUB ESP,8\n\t"
11023 "MOVSD [ESP],$src\n\t"
11024 "FLD_D [ESP]\n\t"
11025 "ADD ESP,8\n\t"
11026 "CALL d2l_wrapper\n"
11027 "fast:" %}
11028 ins_encode %{
11029 Label fast;
11030 __ subptr(rsp, 8);
11031 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11032 __ fld_d(Address(rsp, 0));
11033 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11034 __ fistp_d(Address(rsp, 0));
11035 // Restore the rounding mode, mask the exception
11036 if (Compile::current()->in_24_bit_fp_mode()) {
11037 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11038 } else {
11039 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11040 }
11041 // Load the converted long, adjust CPU stack
11042 __ pop(rax);
11043 __ pop(rdx);
11044 __ cmpl(rdx, 0x80000000);
11045 __ jccb(Assembler::notEqual, fast);
11046 __ testl(rax, rax);
11047 __ jccb(Assembler::notEqual, fast);
11048 __ subptr(rsp, 8);
11049 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11050 __ fld_d(Address(rsp, 0));
11051 __ addptr(rsp, 8);
11052 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11053 __ bind(fast);
11054 %}
11055 ins_pipe( pipe_slow );
11056 %}
11057
11058 // Convert a double to an int. Java semantics require we do complex
11059 // manglations in the corner cases. So we set the rounding mode to
11060 // 'zero', store the darned double down as an int, and reset the
11061 // rounding mode to 'nearest'. The hardware stores a flag value down
11062 // if we would overflow or converted a NAN; we check for this and
11063 // and go the slow path if needed.
11064 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11065 predicate(UseSSE==0);
11066 match(Set dst (ConvF2I src));
11067 effect( KILL tmp, KILL cr );
11068 format %{ "FLD $src\t# Convert float to int \n\t"
11069 "FLDCW trunc mode\n\t"
11070 "SUB ESP,4\n\t"
11071 "FISTp [ESP + #0]\n\t"
11072 "FLDCW std/24-bit mode\n\t"
11073 "POP EAX\n\t"
11074 "CMP EAX,0x80000000\n\t"
11075 "JNE,s fast\n\t"
11076 "FLD $src\n\t"
11077 "CALL d2i_wrapper\n"
11078 "fast:" %}
11079 // DPR2I_encoding works for FPR2I
11080 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11081 ins_pipe( pipe_slow );
11082 %}
11083
11084 // Convert a float in xmm to an int reg.
11085 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11086 predicate(UseSSE>=1);
11087 match(Set dst (ConvF2I src));
11088 effect( KILL tmp, KILL cr );
11089 format %{ "CVTTSS2SI $dst, $src\n\t"
11090 "CMP $dst,0x80000000\n\t"
11091 "JNE,s fast\n\t"
11092 "SUB ESP, 4\n\t"
11093 "MOVSS [ESP], $src\n\t"
11094 "FLD [ESP]\n\t"
11095 "ADD ESP, 4\n\t"
11096 "CALL d2i_wrapper\n"
11097 "fast:" %}
11098 ins_encode %{
11099 Label fast;
11100 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11101 __ cmpl($dst$$Register, 0x80000000);
11102 __ jccb(Assembler::notEqual, fast);
11103 __ subptr(rsp, 4);
11104 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11105 __ fld_s(Address(rsp, 0));
11106 __ addptr(rsp, 4);
11107 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11108 __ bind(fast);
11109 %}
11110 ins_pipe( pipe_slow );
11111 %}
11112
11113 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11114 predicate(UseSSE==0);
11115 match(Set dst (ConvF2L src));
11116 effect( KILL cr );
11117 format %{ "FLD $src\t# Convert float to long\n\t"
11118 "FLDCW trunc mode\n\t"
11119 "SUB ESP,8\n\t"
11120 "FISTp [ESP + #0]\n\t"
11121 "FLDCW std/24-bit mode\n\t"
11122 "POP EAX\n\t"
11123 "POP EDX\n\t"
11124 "CMP EDX,0x80000000\n\t"
11125 "JNE,s fast\n\t"
11126 "TEST EAX,EAX\n\t"
11127 "JNE,s fast\n\t"
11128 "FLD $src\n\t"
11129 "CALL d2l_wrapper\n"
11130 "fast:" %}
11131 // DPR2L_encoding works for FPR2L
11132 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11133 ins_pipe( pipe_slow );
11134 %}
11135
11136 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11137 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11138 predicate (UseSSE>=1);
11139 match(Set dst (ConvF2L src));
11140 effect( KILL cr );
11141 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11142 "MOVSS [ESP],$src\n\t"
11143 "FLD_S [ESP]\n\t"
11144 "FLDCW trunc mode\n\t"
11145 "FISTp [ESP + #0]\n\t"
11146 "FLDCW std/24-bit mode\n\t"
11147 "POP EAX\n\t"
11148 "POP EDX\n\t"
11149 "CMP EDX,0x80000000\n\t"
11150 "JNE,s fast\n\t"
11151 "TEST EAX,EAX\n\t"
11152 "JNE,s fast\n\t"
11153 "SUB ESP,4\t# Convert float to long\n\t"
11154 "MOVSS [ESP],$src\n\t"
11155 "FLD_S [ESP]\n\t"
11156 "ADD ESP,4\n\t"
11157 "CALL d2l_wrapper\n"
11158 "fast:" %}
11159 ins_encode %{
11160 Label fast;
11161 __ subptr(rsp, 8);
11162 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11163 __ fld_s(Address(rsp, 0));
11164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11165 __ fistp_d(Address(rsp, 0));
11166 // Restore the rounding mode, mask the exception
11167 if (Compile::current()->in_24_bit_fp_mode()) {
11168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11169 } else {
11170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11171 }
11172 // Load the converted long, adjust CPU stack
11173 __ pop(rax);
11174 __ pop(rdx);
11175 __ cmpl(rdx, 0x80000000);
11176 __ jccb(Assembler::notEqual, fast);
11177 __ testl(rax, rax);
11178 __ jccb(Assembler::notEqual, fast);
11179 __ subptr(rsp, 4);
11180 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11181 __ fld_s(Address(rsp, 0));
11182 __ addptr(rsp, 4);
11183 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11184 __ bind(fast);
11185 %}
11186 ins_pipe( pipe_slow );
11187 %}
11188
11189 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11190 predicate( UseSSE<=1 );
11191 match(Set dst (ConvI2D src));
11192 format %{ "FILD $src\n\t"
11193 "FSTP $dst" %}
11194 opcode(0xDB, 0x0); /* DB /0 */
11195 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11196 ins_pipe( fpu_reg_mem );
11197 %}
11198
11199 instruct convI2D_reg(regD dst, eRegI src) %{
11200 predicate( UseSSE>=2 && !UseXmmI2D );
11201 match(Set dst (ConvI2D src));
11202 format %{ "CVTSI2SD $dst,$src" %}
11203 ins_encode %{
11204 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11205 %}
11206 ins_pipe( pipe_slow );
11207 %}
11208
11209 instruct convI2D_mem(regD dst, memory mem) %{
11210 predicate( UseSSE>=2 );
11211 match(Set dst (ConvI2D (LoadI mem)));
11212 format %{ "CVTSI2SD $dst,$mem" %}
11213 ins_encode %{
11214 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11215 %}
11216 ins_pipe( pipe_slow );
11217 %}
11218
11219 instruct convXI2D_reg(regD dst, eRegI src)
11220 %{
11221 predicate( UseSSE>=2 && UseXmmI2D );
11222 match(Set dst (ConvI2D src));
11223
11224 format %{ "MOVD $dst,$src\n\t"
11225 "CVTDQ2PD $dst,$dst\t# i2d" %}
11226 ins_encode %{
11227 __ movdl($dst$$XMMRegister, $src$$Register);
11228 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11229 %}
11230 ins_pipe(pipe_slow); // XXX
11231 %}
11232
11233 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11234 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11235 match(Set dst (ConvI2D (LoadI mem)));
11236 format %{ "FILD $mem\n\t"
11237 "FSTP $dst" %}
11238 opcode(0xDB); /* DB /0 */
11239 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11240 Pop_Reg_DPR(dst));
11241 ins_pipe( fpu_reg_mem );
11242 %}
11243
11244 // Convert a byte to a float; no rounding step needed.
11245 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11246 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11247 match(Set dst (ConvI2F src));
11248 format %{ "FILD $src\n\t"
11249 "FSTP $dst" %}
11250
11251 opcode(0xDB, 0x0); /* DB /0 */
11252 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11253 ins_pipe( fpu_reg_mem );
11254 %}
11255
11256 // In 24-bit mode, force exponent rounding by storing back out
11257 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11258 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11259 match(Set dst (ConvI2F src));
11260 ins_cost(200);
11261 format %{ "FILD $src\n\t"
11262 "FSTP_S $dst" %}
11263 opcode(0xDB, 0x0); /* DB /0 */
11264 ins_encode( Push_Mem_I(src),
11265 Pop_Mem_FPR(dst));
11266 ins_pipe( fpu_mem_mem );
11267 %}
11268
11269 // In 24-bit mode, force exponent rounding by storing back out
11270 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11271 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11272 match(Set dst (ConvI2F (LoadI mem)));
11273 ins_cost(200);
11274 format %{ "FILD $mem\n\t"
11275 "FSTP_S $dst" %}
11276 opcode(0xDB); /* DB /0 */
11277 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11278 Pop_Mem_FPR(dst));
11279 ins_pipe( fpu_mem_mem );
11280 %}
11281
11282 // This instruction does not round to 24-bits
11283 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11284 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11285 match(Set dst (ConvI2F src));
11286 format %{ "FILD $src\n\t"
11287 "FSTP $dst" %}
11288 opcode(0xDB, 0x0); /* DB /0 */
11289 ins_encode( Push_Mem_I(src),
11290 Pop_Reg_FPR(dst));
11291 ins_pipe( fpu_reg_mem );
11292 %}
11293
11294 // This instruction does not round to 24-bits
11295 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11296 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11297 match(Set dst (ConvI2F (LoadI mem)));
11298 format %{ "FILD $mem\n\t"
11299 "FSTP $dst" %}
11300 opcode(0xDB); /* DB /0 */
11301 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11302 Pop_Reg_FPR(dst));
11303 ins_pipe( fpu_reg_mem );
11304 %}
11305
11306 // Convert an int to a float in xmm; no rounding step needed.
11307 instruct convI2F_reg(regF dst, eRegI src) %{
11308 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11309 match(Set dst (ConvI2F src));
11310 format %{ "CVTSI2SS $dst, $src" %}
11311 ins_encode %{
11312 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11313 %}
11314 ins_pipe( pipe_slow );
11315 %}
11316
11317 instruct convXI2F_reg(regF dst, eRegI src)
11318 %{
11319 predicate( UseSSE>=2 && UseXmmI2F );
11320 match(Set dst (ConvI2F src));
11321
11322 format %{ "MOVD $dst,$src\n\t"
11323 "CVTDQ2PS $dst,$dst\t# i2f" %}
11324 ins_encode %{
11325 __ movdl($dst$$XMMRegister, $src$$Register);
11326 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11327 %}
11328 ins_pipe(pipe_slow); // XXX
11329 %}
11330
11331 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11332 match(Set dst (ConvI2L src));
11333 effect(KILL cr);
11334 ins_cost(375);
11335 format %{ "MOV $dst.lo,$src\n\t"
11336 "MOV $dst.hi,$src\n\t"
11337 "SAR $dst.hi,31" %}
11338 ins_encode(convert_int_long(dst,src));
11339 ins_pipe( ialu_reg_reg_long );
11340 %}
11341
11342 // Zero-extend convert int to long
11343 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11344 match(Set dst (AndL (ConvI2L src) mask) );
11345 effect( KILL flags );
11346 ins_cost(250);
11347 format %{ "MOV $dst.lo,$src\n\t"
11348 "XOR $dst.hi,$dst.hi" %}
11349 opcode(0x33); // XOR
11350 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11351 ins_pipe( ialu_reg_reg_long );
11352 %}
11353
11354 // Zero-extend long
11355 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11356 match(Set dst (AndL src mask) );
11357 effect( KILL flags );
11358 ins_cost(250);
11359 format %{ "MOV $dst.lo,$src.lo\n\t"
11360 "XOR $dst.hi,$dst.hi\n\t" %}
11361 opcode(0x33); // XOR
11362 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11363 ins_pipe( ialu_reg_reg_long );
11364 %}
11365
11366 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11367 predicate (UseSSE<=1);
11368 match(Set dst (ConvL2D src));
11369 effect( KILL cr );
11370 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11371 "PUSH $src.lo\n\t"
11372 "FILD ST,[ESP + #0]\n\t"
11373 "ADD ESP,8\n\t"
11374 "FSTP_D $dst\t# D-round" %}
11375 opcode(0xDF, 0x5); /* DF /5 */
11376 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11377 ins_pipe( pipe_slow );
11378 %}
11379
11380 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11381 predicate (UseSSE>=2);
11382 match(Set dst (ConvL2D src));
11383 effect( KILL cr );
11384 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11385 "PUSH $src.lo\n\t"
11386 "FILD_D [ESP]\n\t"
11387 "FSTP_D [ESP]\n\t"
11388 "MOVSD $dst,[ESP]\n\t"
11389 "ADD ESP,8" %}
11390 opcode(0xDF, 0x5); /* DF /5 */
11391 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11392 ins_pipe( pipe_slow );
11393 %}
11394
11395 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11396 predicate (UseSSE>=1);
11397 match(Set dst (ConvL2F src));
11398 effect( KILL cr );
11399 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11400 "PUSH $src.lo\n\t"
11401 "FILD_D [ESP]\n\t"
11402 "FSTP_S [ESP]\n\t"
11403 "MOVSS $dst,[ESP]\n\t"
11404 "ADD ESP,8" %}
11405 opcode(0xDF, 0x5); /* DF /5 */
11406 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11407 ins_pipe( pipe_slow );
11408 %}
11409
11410 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11411 match(Set dst (ConvL2F src));
11412 effect( KILL cr );
11413 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11414 "PUSH $src.lo\n\t"
11415 "FILD ST,[ESP + #0]\n\t"
11416 "ADD ESP,8\n\t"
11417 "FSTP_S $dst\t# F-round" %}
11418 opcode(0xDF, 0x5); /* DF /5 */
11419 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11420 ins_pipe( pipe_slow );
11421 %}
11422
11423 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11424 match(Set dst (ConvL2I src));
11425 effect( DEF dst, USE src );
11426 format %{ "MOV $dst,$src.lo" %}
11427 ins_encode(enc_CopyL_Lo(dst,src));
11428 ins_pipe( ialu_reg_reg );
11429 %}
11430
11431
11432 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11433 match(Set dst (MoveF2I src));
11434 effect( DEF dst, USE src );
11435 ins_cost(100);
11436 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11437 ins_encode %{
11438 __ movl($dst$$Register, Address(rsp, $src$$disp));
11439 %}
11440 ins_pipe( ialu_reg_mem );
11441 %}
11442
11443 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11444 predicate(UseSSE==0);
11445 match(Set dst (MoveF2I src));
11446 effect( DEF dst, USE src );
11447
11448 ins_cost(125);
11449 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11450 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11451 ins_pipe( fpu_mem_reg );
11452 %}
11453
11454 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11455 predicate(UseSSE>=1);
11456 match(Set dst (MoveF2I src));
11457 effect( DEF dst, USE src );
11458
11459 ins_cost(95);
11460 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11461 ins_encode %{
11462 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11463 %}
11464 ins_pipe( pipe_slow );
11465 %}
11466
11467 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
11468 predicate(UseSSE>=2);
11469 match(Set dst (MoveF2I src));
11470 effect( DEF dst, USE src );
11471 ins_cost(85);
11472 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11473 ins_encode %{
11474 __ movdl($dst$$Register, $src$$XMMRegister);
11475 %}
11476 ins_pipe( pipe_slow );
11477 %}
11478
11479 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11480 match(Set dst (MoveI2F src));
11481 effect( DEF dst, USE src );
11482
11483 ins_cost(100);
11484 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11485 ins_encode %{
11486 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11487 %}
11488 ins_pipe( ialu_mem_reg );
11489 %}
11490
11491
11492 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11493 predicate(UseSSE==0);
11494 match(Set dst (MoveI2F src));
11495 effect(DEF dst, USE src);
11496
11497 ins_cost(125);
11498 format %{ "FLD_S $src\n\t"
11499 "FSTP $dst\t# MoveI2F_stack_reg" %}
11500 opcode(0xD9); /* D9 /0, FLD m32real */
11501 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11502 Pop_Reg_FPR(dst) );
11503 ins_pipe( fpu_reg_mem );
11504 %}
11505
11506 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11507 predicate(UseSSE>=1);
11508 match(Set dst (MoveI2F src));
11509 effect( DEF dst, USE src );
11510
11511 ins_cost(95);
11512 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11513 ins_encode %{
11514 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11515 %}
11516 ins_pipe( pipe_slow );
11517 %}
11518
11519 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
11520 predicate(UseSSE>=2);
11521 match(Set dst (MoveI2F src));
11522 effect( DEF dst, USE src );
11523
11524 ins_cost(85);
11525 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11526 ins_encode %{
11527 __ movdl($dst$$XMMRegister, $src$$Register);
11528 %}
11529 ins_pipe( pipe_slow );
11530 %}
11531
11532 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11533 match(Set dst (MoveD2L src));
11534 effect(DEF dst, USE src);
11535
11536 ins_cost(250);
11537 format %{ "MOV $dst.lo,$src\n\t"
11538 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11539 opcode(0x8B, 0x8B);
11540 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11541 ins_pipe( ialu_mem_long_reg );
11542 %}
11543
11544 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11545 predicate(UseSSE<=1);
11546 match(Set dst (MoveD2L src));
11547 effect(DEF dst, USE src);
11548
11549 ins_cost(125);
11550 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11551 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11552 ins_pipe( fpu_mem_reg );
11553 %}
11554
11555 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11556 predicate(UseSSE>=2);
11557 match(Set dst (MoveD2L src));
11558 effect(DEF dst, USE src);
11559 ins_cost(95);
11560 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11561 ins_encode %{
11562 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11563 %}
11564 ins_pipe( pipe_slow );
11565 %}
11566
11567 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11568 predicate(UseSSE>=2);
11569 match(Set dst (MoveD2L src));
11570 effect(DEF dst, USE src, TEMP tmp);
11571 ins_cost(85);
11572 format %{ "MOVD $dst.lo,$src\n\t"
11573 "PSHUFLW $tmp,$src,0x4E\n\t"
11574 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11575 ins_encode %{
11576 __ movdl($dst$$Register, $src$$XMMRegister);
11577 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11578 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11579 %}
11580 ins_pipe( pipe_slow );
11581 %}
11582
11583 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11584 match(Set dst (MoveL2D src));
11585 effect(DEF dst, USE src);
11586
11587 ins_cost(200);
11588 format %{ "MOV $dst,$src.lo\n\t"
11589 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11590 opcode(0x89, 0x89);
11591 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11592 ins_pipe( ialu_mem_long_reg );
11593 %}
11594
11595
11596 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11597 predicate(UseSSE<=1);
11598 match(Set dst (MoveL2D src));
11599 effect(DEF dst, USE src);
11600 ins_cost(125);
11601
11602 format %{ "FLD_D $src\n\t"
11603 "FSTP $dst\t# MoveL2D_stack_reg" %}
11604 opcode(0xDD); /* DD /0, FLD m64real */
11605 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11606 Pop_Reg_DPR(dst) );
11607 ins_pipe( fpu_reg_mem );
11608 %}
11609
11610
11611 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11612 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11613 match(Set dst (MoveL2D src));
11614 effect(DEF dst, USE src);
11615
11616 ins_cost(95);
11617 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11618 ins_encode %{
11619 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11620 %}
11621 ins_pipe( pipe_slow );
11622 %}
11623
11624 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11625 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11626 match(Set dst (MoveL2D src));
11627 effect(DEF dst, USE src);
11628
11629 ins_cost(95);
11630 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11631 ins_encode %{
11632 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11633 %}
11634 ins_pipe( pipe_slow );
11635 %}
11636
11637 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11638 predicate(UseSSE>=2);
11639 match(Set dst (MoveL2D src));
11640 effect(TEMP dst, USE src, TEMP tmp);
11641 ins_cost(85);
11642 format %{ "MOVD $dst,$src.lo\n\t"
11643 "MOVD $tmp,$src.hi\n\t"
11644 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11645 ins_encode %{
11646 __ movdl($dst$$XMMRegister, $src$$Register);
11647 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11648 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11649 %}
11650 ins_pipe( pipe_slow );
11651 %}
11652
11653 // Replicate scalar to packed byte (1 byte) values in xmm
11654 instruct Repl8B_reg(regD dst, regD src) %{
11655 predicate(UseSSE>=2);
11656 match(Set dst (Replicate8B src));
11657 format %{ "MOVDQA $dst,$src\n\t"
11658 "PUNPCKLBW $dst,$dst\n\t"
11659 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11660 ins_encode %{
11661 if ($dst$$reg != $src$$reg) {
11662 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
11663 }
11664 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11665 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11666 %}
11667 ins_pipe( pipe_slow );
11668 %}
11669
11670 // Replicate scalar to packed byte (1 byte) values in xmm
11671 instruct Repl8B_eRegI(regD dst, eRegI src) %{
11672 predicate(UseSSE>=2);
11673 match(Set dst (Replicate8B src));
11674 format %{ "MOVD $dst,$src\n\t"
11675 "PUNPCKLBW $dst,$dst\n\t"
11676 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11677 ins_encode %{
11678 __ movdl($dst$$XMMRegister, $src$$Register);
11679 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11680 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11681 %}
11682 ins_pipe( pipe_slow );
11683 %}
11684
11685 // Replicate scalar zero to packed byte (1 byte) values in xmm
11686 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11687 predicate(UseSSE>=2);
11688 match(Set dst (Replicate8B zero));
11689 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11690 ins_encode %{
11691 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11692 %}
11693 ins_pipe( fpu_reg_reg );
11694 %}
11695
11696 // Replicate scalar to packed shore (2 byte) values in xmm
11697 instruct Repl4S_reg(regD dst, regD src) %{
11698 predicate(UseSSE>=2);
11699 match(Set dst (Replicate4S src));
11700 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11701 ins_encode %{
11702 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11703 %}
11704 ins_pipe( fpu_reg_reg );
11705 %}
11706
11707 // Replicate scalar to packed shore (2 byte) values in xmm
11708 instruct Repl4S_eRegI(regD dst, eRegI src) %{
11709 predicate(UseSSE>=2);
11710 match(Set dst (Replicate4S src));
11711 format %{ "MOVD $dst,$src\n\t"
11712 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11713 ins_encode %{
11714 __ movdl($dst$$XMMRegister, $src$$Register);
11715 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11716 %}
11717 ins_pipe( fpu_reg_reg );
11718 %}
11719
11720 // Replicate scalar zero to packed short (2 byte) values in xmm
11721 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11722 predicate(UseSSE>=2);
11723 match(Set dst (Replicate4S zero));
11724 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11725 ins_encode %{
11726 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11727 %}
11728 ins_pipe( fpu_reg_reg );
11729 %}
11730
11731 // Replicate scalar to packed char (2 byte) values in xmm
11732 instruct Repl4C_reg(regD dst, regD src) %{
11733 predicate(UseSSE>=2);
11734 match(Set dst (Replicate4C src));
11735 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11736 ins_encode %{
11737 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11738 %}
11739 ins_pipe( fpu_reg_reg );
11740 %}
11741
11742 // Replicate scalar to packed char (2 byte) values in xmm
11743 instruct Repl4C_eRegI(regD dst, eRegI src) %{
11744 predicate(UseSSE>=2);
11745 match(Set dst (Replicate4C src));
11746 format %{ "MOVD $dst,$src\n\t"
11747 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11748 ins_encode %{
11749 __ movdl($dst$$XMMRegister, $src$$Register);
11750 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11751 %}
11752 ins_pipe( fpu_reg_reg );
11753 %}
11754
11755 // Replicate scalar zero to packed char (2 byte) values in xmm
11756 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11757 predicate(UseSSE>=2);
11758 match(Set dst (Replicate4C zero));
11759 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11760 ins_encode %{
11761 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11762 %}
11763 ins_pipe( fpu_reg_reg );
11764 %}
11765
11766 // Replicate scalar to packed integer (4 byte) values in xmm
11767 instruct Repl2I_reg(regD dst, regD src) %{
11768 predicate(UseSSE>=2);
11769 match(Set dst (Replicate2I src));
11770 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11771 ins_encode %{
11772 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11773 %}
11774 ins_pipe( fpu_reg_reg );
11775 %}
11776
11777 // Replicate scalar to packed integer (4 byte) values in xmm
11778 instruct Repl2I_eRegI(regD dst, eRegI src) %{
11779 predicate(UseSSE>=2);
11780 match(Set dst (Replicate2I src));
11781 format %{ "MOVD $dst,$src\n\t"
11782 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11783 ins_encode %{
11784 __ movdl($dst$$XMMRegister, $src$$Register);
11785 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11786 %}
11787 ins_pipe( fpu_reg_reg );
11788 %}
11789
11790 // Replicate scalar zero to packed integer (2 byte) values in xmm
11791 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11792 predicate(UseSSE>=2);
11793 match(Set dst (Replicate2I zero));
11794 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11795 ins_encode %{
11796 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11797 %}
11798 ins_pipe( fpu_reg_reg );
11799 %}
11800
11801 // Replicate scalar to packed single precision floating point values in xmm
11802 instruct Repl2F_reg(regD dst, regD src) %{
11803 predicate(UseSSE>=2);
11804 match(Set dst (Replicate2F src));
11805 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11806 ins_encode %{
11807 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11808 %}
11809 ins_pipe( fpu_reg_reg );
11810 %}
11811
11812 // Replicate scalar to packed single precision floating point values in xmm
11813 instruct Repl2F_regF(regD dst, regF src) %{
11814 predicate(UseSSE>=2);
11815 match(Set dst (Replicate2F src));
11816 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11817 ins_encode %{
11818 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11819 %}
11820 ins_pipe( fpu_reg_reg );
11821 %}
11822
11823 // Replicate scalar to packed single precision floating point values in xmm
11824 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11825 predicate(UseSSE>=2);
11826 match(Set dst (Replicate2F zero));
11827 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11828 ins_encode %{
11829 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11830 %}
11831 ins_pipe( fpu_reg_reg );
11832 %}
11833
11834 // =======================================================================
11835 // fast clearing of an array
11836 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11837 match(Set dummy (ClearArray cnt base));
11838 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11839 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11840 "XOR EAX,EAX\n\t"
11841 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11842 opcode(0,0x4);
11843 ins_encode( Opcode(0xD1), RegOpc(ECX),
11844 OpcRegReg(0x33,EAX,EAX),
11845 Opcode(0xF3), Opcode(0xAB) );
11846 ins_pipe( pipe_slow );
11847 %}
11848
11849 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11850 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11851 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11852 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11853
11854 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11855 ins_encode %{
11856 __ string_compare($str1$$Register, $str2$$Register,
11857 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11858 $tmp1$$XMMRegister);
11859 %}
11860 ins_pipe( pipe_slow );
11861 %}
11862
11863 // fast string equals
11864 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11865 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11866 match(Set result (StrEquals (Binary str1 str2) cnt));
11867 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11868
11869 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11870 ins_encode %{
11871 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11872 $cnt$$Register, $result$$Register, $tmp3$$Register,
11873 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11874 %}
11875 ins_pipe( pipe_slow );
11876 %}
11877
11878 // fast search of substring with known size.
11879 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11880 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11881 predicate(UseSSE42Intrinsics);
11882 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11883 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11884
11885 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11886 ins_encode %{
11887 int icnt2 = (int)$int_cnt2$$constant;
11888 if (icnt2 >= 8) {
11889 // IndexOf for constant substrings with size >= 8 elements
11890 // which don't need to be loaded through stack.
11891 __ string_indexofC8($str1$$Register, $str2$$Register,
11892 $cnt1$$Register, $cnt2$$Register,
11893 icnt2, $result$$Register,
11894 $vec$$XMMRegister, $tmp$$Register);
11895 } else {
11896 // Small strings are loaded through stack if they cross page boundary.
11897 __ string_indexof($str1$$Register, $str2$$Register,
11898 $cnt1$$Register, $cnt2$$Register,
11899 icnt2, $result$$Register,
11900 $vec$$XMMRegister, $tmp$$Register);
11901 }
11902 %}
11903 ins_pipe( pipe_slow );
11904 %}
11905
11906 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11907 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11908 predicate(UseSSE42Intrinsics);
11909 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11910 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11911
11912 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11913 ins_encode %{
11914 __ string_indexof($str1$$Register, $str2$$Register,
11915 $cnt1$$Register, $cnt2$$Register,
11916 (-1), $result$$Register,
11917 $vec$$XMMRegister, $tmp$$Register);
11918 %}
11919 ins_pipe( pipe_slow );
11920 %}
11921
11922 // fast array equals
11923 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11924 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11925 %{
11926 match(Set result (AryEq ary1 ary2));
11927 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11928 //ins_cost(300);
11929
11930 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11931 ins_encode %{
11932 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11933 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11934 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11935 %}
11936 ins_pipe( pipe_slow );
11937 %}
11938
11939 //----------Control Flow Instructions------------------------------------------
11940 // Signed compare Instructions
11941 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
11942 match(Set cr (CmpI op1 op2));
11943 effect( DEF cr, USE op1, USE op2 );
11944 format %{ "CMP $op1,$op2" %}
11945 opcode(0x3B); /* Opcode 3B /r */
11946 ins_encode( OpcP, RegReg( op1, op2) );
11947 ins_pipe( ialu_cr_reg_reg );
11948 %}
11949
11950 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
11951 match(Set cr (CmpI op1 op2));
11952 effect( DEF cr, USE op1 );
11953 format %{ "CMP $op1,$op2" %}
11954 opcode(0x81,0x07); /* Opcode 81 /7 */
11955 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11956 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11957 ins_pipe( ialu_cr_reg_imm );
11958 %}
11959
11960 // Cisc-spilled version of cmpI_eReg
11961 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
11962 match(Set cr (CmpI op1 (LoadI op2)));
11963
11964 format %{ "CMP $op1,$op2" %}
11965 ins_cost(500);
11966 opcode(0x3B); /* Opcode 3B /r */
11967 ins_encode( OpcP, RegMem( op1, op2) );
11968 ins_pipe( ialu_cr_reg_mem );
11969 %}
11970
11971 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
11972 match(Set cr (CmpI src zero));
11973 effect( DEF cr, USE src );
11974
11975 format %{ "TEST $src,$src" %}
11976 opcode(0x85);
11977 ins_encode( OpcP, RegReg( src, src ) );
11978 ins_pipe( ialu_cr_reg_imm );
11979 %}
11980
11981 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
11982 match(Set cr (CmpI (AndI src con) zero));
11983
11984 format %{ "TEST $src,$con" %}
11985 opcode(0xF7,0x00);
11986 ins_encode( OpcP, RegOpc(src), Con32(con) );
11987 ins_pipe( ialu_cr_reg_imm );
11988 %}
11989
11990 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
11991 match(Set cr (CmpI (AndI src mem) zero));
11992
11993 format %{ "TEST $src,$mem" %}
11994 opcode(0x85);
11995 ins_encode( OpcP, RegMem( src, mem ) );
11996 ins_pipe( ialu_cr_reg_mem );
11997 %}
11998
11999 // Unsigned compare Instructions; really, same as signed except they
12000 // produce an eFlagsRegU instead of eFlagsReg.
12001 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12002 match(Set cr (CmpU op1 op2));
12003
12004 format %{ "CMPu $op1,$op2" %}
12005 opcode(0x3B); /* Opcode 3B /r */
12006 ins_encode( OpcP, RegReg( op1, op2) );
12007 ins_pipe( ialu_cr_reg_reg );
12008 %}
12009
12010 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12011 match(Set cr (CmpU op1 op2));
12012
12013 format %{ "CMPu $op1,$op2" %}
12014 opcode(0x81,0x07); /* Opcode 81 /7 */
12015 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12016 ins_pipe( ialu_cr_reg_imm );
12017 %}
12018
12019 // // Cisc-spilled version of cmpU_eReg
12020 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12021 match(Set cr (CmpU op1 (LoadI op2)));
12022
12023 format %{ "CMPu $op1,$op2" %}
12024 ins_cost(500);
12025 opcode(0x3B); /* Opcode 3B /r */
12026 ins_encode( OpcP, RegMem( op1, op2) );
12027 ins_pipe( ialu_cr_reg_mem );
12028 %}
12029
12030 // // Cisc-spilled version of cmpU_eReg
12031 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12032 // match(Set cr (CmpU (LoadI op1) op2));
12033 //
12034 // format %{ "CMPu $op1,$op2" %}
12035 // ins_cost(500);
12036 // opcode(0x39); /* Opcode 39 /r */
12037 // ins_encode( OpcP, RegMem( op1, op2) );
12038 //%}
12039
12040 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12041 match(Set cr (CmpU src zero));
12042
12043 format %{ "TESTu $src,$src" %}
12044 opcode(0x85);
12045 ins_encode( OpcP, RegReg( src, src ) );
12046 ins_pipe( ialu_cr_reg_imm );
12047 %}
12048
12049 // Unsigned pointer compare Instructions
12050 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12051 match(Set cr (CmpP op1 op2));
12052
12053 format %{ "CMPu $op1,$op2" %}
12054 opcode(0x3B); /* Opcode 3B /r */
12055 ins_encode( OpcP, RegReg( op1, op2) );
12056 ins_pipe( ialu_cr_reg_reg );
12057 %}
12058
12059 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12060 match(Set cr (CmpP op1 op2));
12061
12062 format %{ "CMPu $op1,$op2" %}
12063 opcode(0x81,0x07); /* Opcode 81 /7 */
12064 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12065 ins_pipe( ialu_cr_reg_imm );
12066 %}
12067
12068 // // Cisc-spilled version of cmpP_eReg
12069 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12070 match(Set cr (CmpP op1 (LoadP op2)));
12071
12072 format %{ "CMPu $op1,$op2" %}
12073 ins_cost(500);
12074 opcode(0x3B); /* Opcode 3B /r */
12075 ins_encode( OpcP, RegMem( op1, op2) );
12076 ins_pipe( ialu_cr_reg_mem );
12077 %}
12078
12079 // // Cisc-spilled version of cmpP_eReg
12080 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12081 // match(Set cr (CmpP (LoadP op1) op2));
12082 //
12083 // format %{ "CMPu $op1,$op2" %}
12084 // ins_cost(500);
12085 // opcode(0x39); /* Opcode 39 /r */
12086 // ins_encode( OpcP, RegMem( op1, op2) );
12087 //%}
12088
12089 // Compare raw pointer (used in out-of-heap check).
12090 // Only works because non-oop pointers must be raw pointers
12091 // and raw pointers have no anti-dependencies.
12092 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12093 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12094 match(Set cr (CmpP op1 (LoadP op2)));
12095
12096 format %{ "CMPu $op1,$op2" %}
12097 opcode(0x3B); /* Opcode 3B /r */
12098 ins_encode( OpcP, RegMem( op1, op2) );
12099 ins_pipe( ialu_cr_reg_mem );
12100 %}
12101
12102 //
12103 // This will generate a signed flags result. This should be ok
12104 // since any compare to a zero should be eq/neq.
12105 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12106 match(Set cr (CmpP src zero));
12107
12108 format %{ "TEST $src,$src" %}
12109 opcode(0x85);
12110 ins_encode( OpcP, RegReg( src, src ) );
12111 ins_pipe( ialu_cr_reg_imm );
12112 %}
12113
12114 // Cisc-spilled version of testP_reg
12115 // This will generate a signed flags result. This should be ok
12116 // since any compare to a zero should be eq/neq.
12117 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12118 match(Set cr (CmpP (LoadP op) zero));
12119
12120 format %{ "TEST $op,0xFFFFFFFF" %}
12121 ins_cost(500);
12122 opcode(0xF7); /* Opcode F7 /0 */
12123 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12124 ins_pipe( ialu_cr_reg_imm );
12125 %}
12126
12127 // Yanked all unsigned pointer compare operations.
12128 // Pointer compares are done with CmpP which is already unsigned.
12129
12130 //----------Max and Min--------------------------------------------------------
12131 // Min Instructions
12132 ////
12133 // *** Min and Max using the conditional move are slower than the
12134 // *** branch version on a Pentium III.
12135 // // Conditional move for min
12136 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12137 // effect( USE_DEF op2, USE op1, USE cr );
12138 // format %{ "CMOVlt $op2,$op1\t! min" %}
12139 // opcode(0x4C,0x0F);
12140 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12141 // ins_pipe( pipe_cmov_reg );
12142 //%}
12143 //
12144 //// Min Register with Register (P6 version)
12145 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12146 // predicate(VM_Version::supports_cmov() );
12147 // match(Set op2 (MinI op1 op2));
12148 // ins_cost(200);
12149 // expand %{
12150 // eFlagsReg cr;
12151 // compI_eReg(cr,op1,op2);
12152 // cmovI_reg_lt(op2,op1,cr);
12153 // %}
12154 //%}
12155
12156 // Min Register with Register (generic version)
12157 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12158 match(Set dst (MinI dst src));
12159 effect(KILL flags);
12160 ins_cost(300);
12161
12162 format %{ "MIN $dst,$src" %}
12163 opcode(0xCC);
12164 ins_encode( min_enc(dst,src) );
12165 ins_pipe( pipe_slow );
12166 %}
12167
12168 // Max Register with Register
12169 // *** Min and Max using the conditional move are slower than the
12170 // *** branch version on a Pentium III.
12171 // // Conditional move for max
12172 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12173 // effect( USE_DEF op2, USE op1, USE cr );
12174 // format %{ "CMOVgt $op2,$op1\t! max" %}
12175 // opcode(0x4F,0x0F);
12176 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12177 // ins_pipe( pipe_cmov_reg );
12178 //%}
12179 //
12180 // // Max Register with Register (P6 version)
12181 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12182 // predicate(VM_Version::supports_cmov() );
12183 // match(Set op2 (MaxI op1 op2));
12184 // ins_cost(200);
12185 // expand %{
12186 // eFlagsReg cr;
12187 // compI_eReg(cr,op1,op2);
12188 // cmovI_reg_gt(op2,op1,cr);
12189 // %}
12190 //%}
12191
12192 // Max Register with Register (generic version)
12193 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12194 match(Set dst (MaxI dst src));
12195 effect(KILL flags);
12196 ins_cost(300);
12197
12198 format %{ "MAX $dst,$src" %}
12199 opcode(0xCC);
12200 ins_encode( max_enc(dst,src) );
12201 ins_pipe( pipe_slow );
12202 %}
12203
12204 // ============================================================================
12205 // Counted Loop limit node which represents exact final iterator value.
12206 // Note: the resulting value should fit into integer range since
12207 // counted loops have limit check on overflow.
12208 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12209 match(Set limit (LoopLimit (Binary init limit) stride));
12210 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12211 ins_cost(300);
12212
12213 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12214 ins_encode %{
12215 int strd = (int)$stride$$constant;
12216 assert(strd != 1 && strd != -1, "sanity");
12217 int m1 = (strd > 0) ? 1 : -1;
12218 // Convert limit to long (EAX:EDX)
12219 __ cdql();
12220 // Convert init to long (init:tmp)
12221 __ movl($tmp$$Register, $init$$Register);
12222 __ sarl($tmp$$Register, 31);
12223 // $limit - $init
12224 __ subl($limit$$Register, $init$$Register);
12225 __ sbbl($limit_hi$$Register, $tmp$$Register);
12226 // + ($stride - 1)
12227 if (strd > 0) {
12228 __ addl($limit$$Register, (strd - 1));
12229 __ adcl($limit_hi$$Register, 0);
12230 __ movl($tmp$$Register, strd);
12231 } else {
12232 __ addl($limit$$Register, (strd + 1));
12233 __ adcl($limit_hi$$Register, -1);
12234 __ lneg($limit_hi$$Register, $limit$$Register);
12235 __ movl($tmp$$Register, -strd);
12236 }
12237 // signed devision: (EAX:EDX) / pos_stride
12238 __ idivl($tmp$$Register);
12239 if (strd < 0) {
12240 // restore sign
12241 __ negl($tmp$$Register);
12242 }
12243 // (EAX) * stride
12244 __ mull($tmp$$Register);
12245 // + init (ignore upper bits)
12246 __ addl($limit$$Register, $init$$Register);
12247 %}
12248 ins_pipe( pipe_slow );
12249 %}
12250
12251 // ============================================================================
12252 // Branch Instructions
12253 // Jump Table
12254 instruct jumpXtnd(eRegI switch_val) %{
12255 match(Jump switch_val);
12256 ins_cost(350);
12257 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12258 ins_encode %{
12259 // Jump to Address(table_base + switch_reg)
12260 Address index(noreg, $switch_val$$Register, Address::times_1);
12261 __ jump(ArrayAddress($constantaddress, index));
12262 %}
12263 ins_pipe(pipe_jmp);
12264 %}
12265
12266 // Jump Direct - Label defines a relative address from JMP+1
12267 instruct jmpDir(label labl) %{
12268 match(Goto);
12269 effect(USE labl);
12270
12271 ins_cost(300);
12272 format %{ "JMP $labl" %}
12273 size(5);
12274 ins_encode %{
12275 Label* L = $labl$$label;
12276 __ jmp(*L, false); // Always long jump
12277 %}
12278 ins_pipe( pipe_jmp );
12279 %}
12280
12281 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12282 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12283 match(If cop cr);
12284 effect(USE labl);
12285
12286 ins_cost(300);
12287 format %{ "J$cop $labl" %}
12288 size(6);
12289 ins_encode %{
12290 Label* L = $labl$$label;
12291 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12292 %}
12293 ins_pipe( pipe_jcc );
12294 %}
12295
12296 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12297 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12298 match(CountedLoopEnd cop cr);
12299 effect(USE labl);
12300
12301 ins_cost(300);
12302 format %{ "J$cop $labl\t# Loop end" %}
12303 size(6);
12304 ins_encode %{
12305 Label* L = $labl$$label;
12306 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12307 %}
12308 ins_pipe( pipe_jcc );
12309 %}
12310
12311 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12312 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12313 match(CountedLoopEnd cop cmp);
12314 effect(USE labl);
12315
12316 ins_cost(300);
12317 format %{ "J$cop,u $labl\t# Loop end" %}
12318 size(6);
12319 ins_encode %{
12320 Label* L = $labl$$label;
12321 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12322 %}
12323 ins_pipe( pipe_jcc );
12324 %}
12325
12326 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12327 match(CountedLoopEnd cop cmp);
12328 effect(USE labl);
12329
12330 ins_cost(200);
12331 format %{ "J$cop,u $labl\t# Loop end" %}
12332 size(6);
12333 ins_encode %{
12334 Label* L = $labl$$label;
12335 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12336 %}
12337 ins_pipe( pipe_jcc );
12338 %}
12339
12340 // Jump Direct Conditional - using unsigned comparison
12341 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12342 match(If cop cmp);
12343 effect(USE labl);
12344
12345 ins_cost(300);
12346 format %{ "J$cop,u $labl" %}
12347 size(6);
12348 ins_encode %{
12349 Label* L = $labl$$label;
12350 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12351 %}
12352 ins_pipe(pipe_jcc);
12353 %}
12354
12355 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12356 match(If cop cmp);
12357 effect(USE labl);
12358
12359 ins_cost(200);
12360 format %{ "J$cop,u $labl" %}
12361 size(6);
12362 ins_encode %{
12363 Label* L = $labl$$label;
12364 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12365 %}
12366 ins_pipe(pipe_jcc);
12367 %}
12368
12369 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12370 match(If cop cmp);
12371 effect(USE labl);
12372
12373 ins_cost(200);
12374 format %{ $$template
12375 if ($cop$$cmpcode == Assembler::notEqual) {
12376 $$emit$$"JP,u $labl\n\t"
12377 $$emit$$"J$cop,u $labl"
12378 } else {
12379 $$emit$$"JP,u done\n\t"
12380 $$emit$$"J$cop,u $labl\n\t"
12381 $$emit$$"done:"
12382 }
12383 %}
12384 ins_encode %{
12385 Label* l = $labl$$label;
12386 if ($cop$$cmpcode == Assembler::notEqual) {
12387 __ jcc(Assembler::parity, *l, false);
12388 __ jcc(Assembler::notEqual, *l, false);
12389 } else if ($cop$$cmpcode == Assembler::equal) {
12390 Label done;
12391 __ jccb(Assembler::parity, done);
12392 __ jcc(Assembler::equal, *l, false);
12393 __ bind(done);
12394 } else {
12395 ShouldNotReachHere();
12396 }
12397 %}
12398 ins_pipe(pipe_jcc);
12399 %}
12400
12401 // ============================================================================
12402 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12403 // array for an instance of the superklass. Set a hidden internal cache on a
12404 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12405 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12406 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12407 match(Set result (PartialSubtypeCheck sub super));
12408 effect( KILL rcx, KILL cr );
12409
12410 ins_cost(1100); // slightly larger than the next version
12411 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12412 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12413 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12414 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12415 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12416 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12417 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12418 "miss:\t" %}
12419
12420 opcode(0x1); // Force a XOR of EDI
12421 ins_encode( enc_PartialSubtypeCheck() );
12422 ins_pipe( pipe_slow );
12423 %}
12424
12425 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12426 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12427 effect( KILL rcx, KILL result );
12428
12429 ins_cost(1000);
12430 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12431 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12432 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12433 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12434 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12435 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12436 "miss:\t" %}
12437
12438 opcode(0x0); // No need to XOR EDI
12439 ins_encode( enc_PartialSubtypeCheck() );
12440 ins_pipe( pipe_slow );
12441 %}
12442
12443 // ============================================================================
12444 // Branch Instructions -- short offset versions
12445 //
12446 // These instructions are used to replace jumps of a long offset (the default
12447 // match) with jumps of a shorter offset. These instructions are all tagged
12448 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12449 // match rules in general matching. Instead, the ADLC generates a conversion
12450 // method in the MachNode which can be used to do in-place replacement of the
12451 // long variant with the shorter variant. The compiler will determine if a
12452 // branch can be taken by the is_short_branch_offset() predicate in the machine
12453 // specific code section of the file.
12454
12455 // Jump Direct - Label defines a relative address from JMP+1
12456 instruct jmpDir_short(label labl) %{
12457 match(Goto);
12458 effect(USE labl);
12459
12460 ins_cost(300);
12461 format %{ "JMP,s $labl" %}
12462 size(2);
12463 ins_encode %{
12464 Label* L = $labl$$label;
12465 __ jmpb(*L);
12466 %}
12467 ins_pipe( pipe_jmp );
12468 ins_short_branch(1);
12469 %}
12470
12471 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12472 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12473 match(If cop cr);
12474 effect(USE labl);
12475
12476 ins_cost(300);
12477 format %{ "J$cop,s $labl" %}
12478 size(2);
12479 ins_encode %{
12480 Label* L = $labl$$label;
12481 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12482 %}
12483 ins_pipe( pipe_jcc );
12484 ins_short_branch(1);
12485 %}
12486
12487 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12488 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12489 match(CountedLoopEnd cop cr);
12490 effect(USE labl);
12491
12492 ins_cost(300);
12493 format %{ "J$cop,s $labl\t# Loop end" %}
12494 size(2);
12495 ins_encode %{
12496 Label* L = $labl$$label;
12497 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12498 %}
12499 ins_pipe( pipe_jcc );
12500 ins_short_branch(1);
12501 %}
12502
12503 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12504 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12505 match(CountedLoopEnd cop cmp);
12506 effect(USE labl);
12507
12508 ins_cost(300);
12509 format %{ "J$cop,us $labl\t# Loop end" %}
12510 size(2);
12511 ins_encode %{
12512 Label* L = $labl$$label;
12513 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12514 %}
12515 ins_pipe( pipe_jcc );
12516 ins_short_branch(1);
12517 %}
12518
12519 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12520 match(CountedLoopEnd cop cmp);
12521 effect(USE labl);
12522
12523 ins_cost(300);
12524 format %{ "J$cop,us $labl\t# Loop end" %}
12525 size(2);
12526 ins_encode %{
12527 Label* L = $labl$$label;
12528 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12529 %}
12530 ins_pipe( pipe_jcc );
12531 ins_short_branch(1);
12532 %}
12533
12534 // Jump Direct Conditional - using unsigned comparison
12535 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12536 match(If cop cmp);
12537 effect(USE labl);
12538
12539 ins_cost(300);
12540 format %{ "J$cop,us $labl" %}
12541 size(2);
12542 ins_encode %{
12543 Label* L = $labl$$label;
12544 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12545 %}
12546 ins_pipe( pipe_jcc );
12547 ins_short_branch(1);
12548 %}
12549
12550 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12551 match(If cop cmp);
12552 effect(USE labl);
12553
12554 ins_cost(300);
12555 format %{ "J$cop,us $labl" %}
12556 size(2);
12557 ins_encode %{
12558 Label* L = $labl$$label;
12559 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12560 %}
12561 ins_pipe( pipe_jcc );
12562 ins_short_branch(1);
12563 %}
12564
12565 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12566 match(If cop cmp);
12567 effect(USE labl);
12568
12569 ins_cost(300);
12570 format %{ $$template
12571 if ($cop$$cmpcode == Assembler::notEqual) {
12572 $$emit$$"JP,u,s $labl\n\t"
12573 $$emit$$"J$cop,u,s $labl"
12574 } else {
12575 $$emit$$"JP,u,s done\n\t"
12576 $$emit$$"J$cop,u,s $labl\n\t"
12577 $$emit$$"done:"
12578 }
12579 %}
12580 size(4);
12581 ins_encode %{
12582 Label* l = $labl$$label;
12583 if ($cop$$cmpcode == Assembler::notEqual) {
12584 __ jccb(Assembler::parity, *l);
12585 __ jccb(Assembler::notEqual, *l);
12586 } else if ($cop$$cmpcode == Assembler::equal) {
12587 Label done;
12588 __ jccb(Assembler::parity, done);
12589 __ jccb(Assembler::equal, *l);
12590 __ bind(done);
12591 } else {
12592 ShouldNotReachHere();
12593 }
12594 %}
12595 ins_pipe(pipe_jcc);
12596 ins_short_branch(1);
12597 %}
12598
12599 // ============================================================================
12600 // Long Compare
12601 //
12602 // Currently we hold longs in 2 registers. Comparing such values efficiently
12603 // is tricky. The flavor of compare used depends on whether we are testing
12604 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12605 // The GE test is the negated LT test. The LE test can be had by commuting
12606 // the operands (yielding a GE test) and then negating; negate again for the
12607 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12608 // NE test is negated from that.
12609
12610 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12611 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12612 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12613 // are collapsed internally in the ADLC's dfa-gen code. The match for
12614 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12615 // foo match ends up with the wrong leaf. One fix is to not match both
12616 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12617 // both forms beat the trinary form of long-compare and both are very useful
12618 // on Intel which has so few registers.
12619
12620 // Manifest a CmpL result in an integer register. Very painful.
12621 // This is the test to avoid.
12622 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12623 match(Set dst (CmpL3 src1 src2));
12624 effect( KILL flags );
12625 ins_cost(1000);
12626 format %{ "XOR $dst,$dst\n\t"
12627 "CMP $src1.hi,$src2.hi\n\t"
12628 "JLT,s m_one\n\t"
12629 "JGT,s p_one\n\t"
12630 "CMP $src1.lo,$src2.lo\n\t"
12631 "JB,s m_one\n\t"
12632 "JEQ,s done\n"
12633 "p_one:\tINC $dst\n\t"
12634 "JMP,s done\n"
12635 "m_one:\tDEC $dst\n"
12636 "done:" %}
12637 ins_encode %{
12638 Label p_one, m_one, done;
12639 __ xorptr($dst$$Register, $dst$$Register);
12640 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12641 __ jccb(Assembler::less, m_one);
12642 __ jccb(Assembler::greater, p_one);
12643 __ cmpl($src1$$Register, $src2$$Register);
12644 __ jccb(Assembler::below, m_one);
12645 __ jccb(Assembler::equal, done);
12646 __ bind(p_one);
12647 __ incrementl($dst$$Register);
12648 __ jmpb(done);
12649 __ bind(m_one);
12650 __ decrementl($dst$$Register);
12651 __ bind(done);
12652 %}
12653 ins_pipe( pipe_slow );
12654 %}
12655
12656 //======
12657 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12658 // compares. Can be used for LE or GT compares by reversing arguments.
12659 // NOT GOOD FOR EQ/NE tests.
12660 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12661 match( Set flags (CmpL src zero ));
12662 ins_cost(100);
12663 format %{ "TEST $src.hi,$src.hi" %}
12664 opcode(0x85);
12665 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12666 ins_pipe( ialu_cr_reg_reg );
12667 %}
12668
12669 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12670 // compares. Can be used for LE or GT compares by reversing arguments.
12671 // NOT GOOD FOR EQ/NE tests.
12672 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12673 match( Set flags (CmpL src1 src2 ));
12674 effect( TEMP tmp );
12675 ins_cost(300);
12676 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12677 "MOV $tmp,$src1.hi\n\t"
12678 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12679 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12680 ins_pipe( ialu_cr_reg_reg );
12681 %}
12682
12683 // Long compares reg < zero/req OR reg >= zero/req.
12684 // Just a wrapper for a normal branch, plus the predicate test.
12685 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12686 match(If cmp flags);
12687 effect(USE labl);
12688 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12689 expand %{
12690 jmpCon(cmp,flags,labl); // JLT or JGE...
12691 %}
12692 %}
12693
12694 // Compare 2 longs and CMOVE longs.
12695 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12696 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12697 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12698 ins_cost(400);
12699 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12700 "CMOV$cmp $dst.hi,$src.hi" %}
12701 opcode(0x0F,0x40);
12702 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12703 ins_pipe( pipe_cmov_reg_long );
12704 %}
12705
12706 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12707 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12708 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12709 ins_cost(500);
12710 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12711 "CMOV$cmp $dst.hi,$src.hi" %}
12712 opcode(0x0F,0x40);
12713 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12714 ins_pipe( pipe_cmov_reg_long );
12715 %}
12716
12717 // Compare 2 longs and CMOVE ints.
12718 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12719 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12720 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12721 ins_cost(200);
12722 format %{ "CMOV$cmp $dst,$src" %}
12723 opcode(0x0F,0x40);
12724 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12725 ins_pipe( pipe_cmov_reg );
12726 %}
12727
12728 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12729 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12730 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12731 ins_cost(250);
12732 format %{ "CMOV$cmp $dst,$src" %}
12733 opcode(0x0F,0x40);
12734 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12735 ins_pipe( pipe_cmov_mem );
12736 %}
12737
12738 // Compare 2 longs and CMOVE ints.
12739 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12740 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12741 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12742 ins_cost(200);
12743 format %{ "CMOV$cmp $dst,$src" %}
12744 opcode(0x0F,0x40);
12745 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12746 ins_pipe( pipe_cmov_reg );
12747 %}
12748
12749 // Compare 2 longs and CMOVE doubles
12750 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12751 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12752 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12753 ins_cost(200);
12754 expand %{
12755 fcmovDPR_regS(cmp,flags,dst,src);
12756 %}
12757 %}
12758
12759 // Compare 2 longs and CMOVE doubles
12760 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12761 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12762 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12763 ins_cost(200);
12764 expand %{
12765 fcmovD_regS(cmp,flags,dst,src);
12766 %}
12767 %}
12768
12769 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12770 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12771 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12772 ins_cost(200);
12773 expand %{
12774 fcmovFPR_regS(cmp,flags,dst,src);
12775 %}
12776 %}
12777
12778 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12779 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12780 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12781 ins_cost(200);
12782 expand %{
12783 fcmovF_regS(cmp,flags,dst,src);
12784 %}
12785 %}
12786
12787 //======
12788 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12789 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12790 match( Set flags (CmpL src zero ));
12791 effect(TEMP tmp);
12792 ins_cost(200);
12793 format %{ "MOV $tmp,$src.lo\n\t"
12794 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12795 ins_encode( long_cmp_flags0( src, tmp ) );
12796 ins_pipe( ialu_reg_reg_long );
12797 %}
12798
12799 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12800 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12801 match( Set flags (CmpL src1 src2 ));
12802 ins_cost(200+300);
12803 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12804 "JNE,s skip\n\t"
12805 "CMP $src1.hi,$src2.hi\n\t"
12806 "skip:\t" %}
12807 ins_encode( long_cmp_flags1( src1, src2 ) );
12808 ins_pipe( ialu_cr_reg_reg );
12809 %}
12810
12811 // Long compare reg == zero/reg OR reg != zero/reg
12812 // Just a wrapper for a normal branch, plus the predicate test.
12813 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12814 match(If cmp flags);
12815 effect(USE labl);
12816 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12817 expand %{
12818 jmpCon(cmp,flags,labl); // JEQ or JNE...
12819 %}
12820 %}
12821
12822 // Compare 2 longs and CMOVE longs.
12823 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12824 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12825 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12826 ins_cost(400);
12827 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12828 "CMOV$cmp $dst.hi,$src.hi" %}
12829 opcode(0x0F,0x40);
12830 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12831 ins_pipe( pipe_cmov_reg_long );
12832 %}
12833
12834 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12835 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12836 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12837 ins_cost(500);
12838 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12839 "CMOV$cmp $dst.hi,$src.hi" %}
12840 opcode(0x0F,0x40);
12841 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12842 ins_pipe( pipe_cmov_reg_long );
12843 %}
12844
12845 // Compare 2 longs and CMOVE ints.
12846 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12847 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12848 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12849 ins_cost(200);
12850 format %{ "CMOV$cmp $dst,$src" %}
12851 opcode(0x0F,0x40);
12852 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12853 ins_pipe( pipe_cmov_reg );
12854 %}
12855
12856 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12857 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12858 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12859 ins_cost(250);
12860 format %{ "CMOV$cmp $dst,$src" %}
12861 opcode(0x0F,0x40);
12862 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12863 ins_pipe( pipe_cmov_mem );
12864 %}
12865
12866 // Compare 2 longs and CMOVE ints.
12867 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12868 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12869 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12870 ins_cost(200);
12871 format %{ "CMOV$cmp $dst,$src" %}
12872 opcode(0x0F,0x40);
12873 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12874 ins_pipe( pipe_cmov_reg );
12875 %}
12876
12877 // Compare 2 longs and CMOVE doubles
12878 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12879 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12880 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12881 ins_cost(200);
12882 expand %{
12883 fcmovDPR_regS(cmp,flags,dst,src);
12884 %}
12885 %}
12886
12887 // Compare 2 longs and CMOVE doubles
12888 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12889 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12890 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12891 ins_cost(200);
12892 expand %{
12893 fcmovD_regS(cmp,flags,dst,src);
12894 %}
12895 %}
12896
12897 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12898 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12899 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12900 ins_cost(200);
12901 expand %{
12902 fcmovFPR_regS(cmp,flags,dst,src);
12903 %}
12904 %}
12905
12906 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12907 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12908 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12909 ins_cost(200);
12910 expand %{
12911 fcmovF_regS(cmp,flags,dst,src);
12912 %}
12913 %}
12914
12915 //======
12916 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12917 // Same as cmpL_reg_flags_LEGT except must negate src
12918 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
12919 match( Set flags (CmpL src zero ));
12920 effect( TEMP tmp );
12921 ins_cost(300);
12922 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12923 "CMP $tmp,$src.lo\n\t"
12924 "SBB $tmp,$src.hi\n\t" %}
12925 ins_encode( long_cmp_flags3(src, tmp) );
12926 ins_pipe( ialu_reg_reg_long );
12927 %}
12928
12929 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12930 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12931 // requires a commuted test to get the same result.
12932 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12933 match( Set flags (CmpL src1 src2 ));
12934 effect( TEMP tmp );
12935 ins_cost(300);
12936 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12937 "MOV $tmp,$src2.hi\n\t"
12938 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12939 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12940 ins_pipe( ialu_cr_reg_reg );
12941 %}
12942
12943 // Long compares reg < zero/req OR reg >= zero/req.
12944 // Just a wrapper for a normal branch, plus the predicate test
12945 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12946 match(If cmp flags);
12947 effect(USE labl);
12948 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12949 ins_cost(300);
12950 expand %{
12951 jmpCon(cmp,flags,labl); // JGT or JLE...
12952 %}
12953 %}
12954
12955 // Compare 2 longs and CMOVE longs.
12956 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12957 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12958 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12959 ins_cost(400);
12960 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12961 "CMOV$cmp $dst.hi,$src.hi" %}
12962 opcode(0x0F,0x40);
12963 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12964 ins_pipe( pipe_cmov_reg_long );
12965 %}
12966
12967 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12968 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12969 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12970 ins_cost(500);
12971 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12972 "CMOV$cmp $dst.hi,$src.hi+4" %}
12973 opcode(0x0F,0x40);
12974 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12975 ins_pipe( pipe_cmov_reg_long );
12976 %}
12977
12978 // Compare 2 longs and CMOVE ints.
12979 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
12980 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12981 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12982 ins_cost(200);
12983 format %{ "CMOV$cmp $dst,$src" %}
12984 opcode(0x0F,0x40);
12985 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12986 ins_pipe( pipe_cmov_reg );
12987 %}
12988
12989 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
12990 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12991 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12992 ins_cost(250);
12993 format %{ "CMOV$cmp $dst,$src" %}
12994 opcode(0x0F,0x40);
12995 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12996 ins_pipe( pipe_cmov_mem );
12997 %}
12998
12999 // Compare 2 longs and CMOVE ptrs.
13000 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13001 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13002 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13003 ins_cost(200);
13004 format %{ "CMOV$cmp $dst,$src" %}
13005 opcode(0x0F,0x40);
13006 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13007 ins_pipe( pipe_cmov_reg );
13008 %}
13009
13010 // Compare 2 longs and CMOVE doubles
13011 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
13012 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13013 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13014 ins_cost(200);
13015 expand %{
13016 fcmovDPR_regS(cmp,flags,dst,src);
13017 %}
13018 %}
13019
13020 // Compare 2 longs and CMOVE doubles
13021 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13022 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13023 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13024 ins_cost(200);
13025 expand %{
13026 fcmovD_regS(cmp,flags,dst,src);
13027 %}
13028 %}
13029
13030 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
13031 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13032 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13033 ins_cost(200);
13034 expand %{
13035 fcmovFPR_regS(cmp,flags,dst,src);
13036 %}
13037 %}
13038
13039
13040 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13041 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13042 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13043 ins_cost(200);
13044 expand %{
13045 fcmovF_regS(cmp,flags,dst,src);
13046 %}
13047 %}
13048
13049
13050 // ============================================================================
13051 // Procedure Call/Return Instructions
13052 // Call Java Static Instruction
13053 // Note: If this code changes, the corresponding ret_addr_offset() and
13054 // compute_padding() functions will have to be adjusted.
13055 instruct CallStaticJavaDirect(method meth) %{
13056 match(CallStaticJava);
13057 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13058 effect(USE meth);
13059
13060 ins_cost(300);
13061 format %{ "CALL,static " %}
13062 opcode(0xE8); /* E8 cd */
13063 ins_encode( pre_call_FPU,
13064 Java_Static_Call( meth ),
13065 call_epilog,
13066 post_call_FPU );
13067 ins_pipe( pipe_slow );
13068 ins_alignment(4);
13069 %}
13070
13071 // Call Java Static Instruction (method handle version)
13072 // Note: If this code changes, the corresponding ret_addr_offset() and
13073 // compute_padding() functions will have to be adjusted.
13074 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13075 match(CallStaticJava);
13076 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13077 effect(USE meth);
13078 // EBP is saved by all callees (for interpreter stack correction).
13079 // We use it here for a similar purpose, in {preserve,restore}_SP.
13080
13081 ins_cost(300);
13082 format %{ "CALL,static/MethodHandle " %}
13083 opcode(0xE8); /* E8 cd */
13084 ins_encode( pre_call_FPU,
13085 preserve_SP,
13086 Java_Static_Call( meth ),
13087 restore_SP,
13088 call_epilog,
13089 post_call_FPU );
13090 ins_pipe( pipe_slow );
13091 ins_alignment(4);
13092 %}
13093
13094 // Call Java Dynamic Instruction
13095 // Note: If this code changes, the corresponding ret_addr_offset() and
13096 // compute_padding() functions will have to be adjusted.
13097 instruct CallDynamicJavaDirect(method meth) %{
13098 match(CallDynamicJava);
13099 effect(USE meth);
13100
13101 ins_cost(300);
13102 format %{ "MOV EAX,(oop)-1\n\t"
13103 "CALL,dynamic" %}
13104 opcode(0xE8); /* E8 cd */
13105 ins_encode( pre_call_FPU,
13106 Java_Dynamic_Call( meth ),
13107 call_epilog,
13108 post_call_FPU );
13109 ins_pipe( pipe_slow );
13110 ins_alignment(4);
13111 %}
13112
13113 // Call Runtime Instruction
13114 instruct CallRuntimeDirect(method meth) %{
13115 match(CallRuntime );
13116 effect(USE meth);
13117
13118 ins_cost(300);
13119 format %{ "CALL,runtime " %}
13120 opcode(0xE8); /* E8 cd */
13121 // Use FFREEs to clear entries in float stack
13122 ins_encode( pre_call_FPU,
13123 FFree_Float_Stack_All,
13124 Java_To_Runtime( meth ),
13125 post_call_FPU );
13126 ins_pipe( pipe_slow );
13127 %}
13128
13129 // Call runtime without safepoint
13130 instruct CallLeafDirect(method meth) %{
13131 match(CallLeaf);
13132 effect(USE meth);
13133
13134 ins_cost(300);
13135 format %{ "CALL_LEAF,runtime " %}
13136 opcode(0xE8); /* E8 cd */
13137 ins_encode( pre_call_FPU,
13138 FFree_Float_Stack_All,
13139 Java_To_Runtime( meth ),
13140 Verify_FPU_For_Leaf, post_call_FPU );
13141 ins_pipe( pipe_slow );
13142 %}
13143
13144 instruct CallLeafNoFPDirect(method meth) %{
13145 match(CallLeafNoFP);
13146 effect(USE meth);
13147
13148 ins_cost(300);
13149 format %{ "CALL_LEAF_NOFP,runtime " %}
13150 opcode(0xE8); /* E8 cd */
13151 ins_encode(Java_To_Runtime(meth));
13152 ins_pipe( pipe_slow );
13153 %}
13154
13155
13156 // Return Instruction
13157 // Remove the return address & jump to it.
13158 instruct Ret() %{
13159 match(Return);
13160 format %{ "RET" %}
13161 opcode(0xC3);
13162 ins_encode(OpcP);
13163 ins_pipe( pipe_jmp );
13164 %}
13165
13166 // Tail Call; Jump from runtime stub to Java code.
13167 // Also known as an 'interprocedural jump'.
13168 // Target of jump will eventually return to caller.
13169 // TailJump below removes the return address.
13170 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13171 match(TailCall jump_target method_oop );
13172 ins_cost(300);
13173 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13174 opcode(0xFF, 0x4); /* Opcode FF /4 */
13175 ins_encode( OpcP, RegOpc(jump_target) );
13176 ins_pipe( pipe_jmp );
13177 %}
13178
13179
13180 // Tail Jump; remove the return address; jump to target.
13181 // TailCall above leaves the return address around.
13182 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13183 match( TailJump jump_target ex_oop );
13184 ins_cost(300);
13185 format %{ "POP EDX\t# pop return address into dummy\n\t"
13186 "JMP $jump_target " %}
13187 opcode(0xFF, 0x4); /* Opcode FF /4 */
13188 ins_encode( enc_pop_rdx,
13189 OpcP, RegOpc(jump_target) );
13190 ins_pipe( pipe_jmp );
13191 %}
13192
13193 // Create exception oop: created by stack-crawling runtime code.
13194 // Created exception is now available to this handler, and is setup
13195 // just prior to jumping to this handler. No code emitted.
13196 instruct CreateException( eAXRegP ex_oop )
13197 %{
13198 match(Set ex_oop (CreateEx));
13199
13200 size(0);
13201 // use the following format syntax
13202 format %{ "# exception oop is in EAX; no code emitted" %}
13203 ins_encode();
13204 ins_pipe( empty );
13205 %}
13206
13207
13208 // Rethrow exception:
13209 // The exception oop will come in the first argument position.
13210 // Then JUMP (not call) to the rethrow stub code.
13211 instruct RethrowException()
13212 %{
13213 match(Rethrow);
13214
13215 // use the following format syntax
13216 format %{ "JMP rethrow_stub" %}
13217 ins_encode(enc_rethrow);
13218 ins_pipe( pipe_jmp );
13219 %}
13220
13221 // inlined locking and unlocking
13222
13223
13224 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13225 match( Set cr (FastLock object box) );
13226 effect( TEMP tmp, TEMP scr, USE_KILL box );
13227 ins_cost(300);
13228 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13229 ins_encode( Fast_Lock(object,box,tmp,scr) );
13230 ins_pipe( pipe_slow );
13231 %}
13232
13233 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13234 match( Set cr (FastUnlock object box) );
13235 effect( TEMP tmp, USE_KILL box );
13236 ins_cost(300);
13237 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13238 ins_encode( Fast_Unlock(object,box,tmp) );
13239 ins_pipe( pipe_slow );
13240 %}
13241
13242
13243
13244 // ============================================================================
13245 // Safepoint Instruction
13246 instruct safePoint_poll(eFlagsReg cr) %{
13247 match(SafePoint);
13248 effect(KILL cr);
13249
13250 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13251 // On SPARC that might be acceptable as we can generate the address with
13252 // just a sethi, saving an or. By polling at offset 0 we can end up
13253 // putting additional pressure on the index-0 in the D$. Because of
13254 // alignment (just like the situation at hand) the lower indices tend
13255 // to see more traffic. It'd be better to change the polling address
13256 // to offset 0 of the last $line in the polling page.
13257
13258 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13259 ins_cost(125);
13260 size(6) ;
13261 ins_encode( Safepoint_Poll() );
13262 ins_pipe( ialu_reg_mem );
13263 %}
13264
13265
13266 // ============================================================================
13267 // This name is KNOWN by the ADLC and cannot be changed.
13268 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13269 // for this guy.
13270 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13271 match(Set dst (ThreadLocal));
13272 effect(DEF dst, KILL cr);
13273
13274 format %{ "MOV $dst, Thread::current()" %}
13275 ins_encode %{
13276 Register dstReg = as_Register($dst$$reg);
13277 __ get_thread(dstReg);
13278 %}
13279 ins_pipe( ialu_reg_fat );
13280 %}
13281
13282
13283
13284 //----------PEEPHOLE RULES-----------------------------------------------------
13285 // These must follow all instruction definitions as they use the names
13286 // defined in the instructions definitions.
13287 //
13288 // peepmatch ( root_instr_name [preceding_instruction]* );
13289 //
13290 // peepconstraint %{
13291 // (instruction_number.operand_name relational_op instruction_number.operand_name
13292 // [, ...] );
13293 // // instruction numbers are zero-based using left to right order in peepmatch
13294 //
13295 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13296 // // provide an instruction_number.operand_name for each operand that appears
13297 // // in the replacement instruction's match rule
13298 //
13299 // ---------VM FLAGS---------------------------------------------------------
13300 //
13301 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13302 //
13303 // Each peephole rule is given an identifying number starting with zero and
13304 // increasing by one in the order seen by the parser. An individual peephole
13305 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13306 // on the command-line.
13307 //
13308 // ---------CURRENT LIMITATIONS----------------------------------------------
13309 //
13310 // Only match adjacent instructions in same basic block
13311 // Only equality constraints
13312 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13313 // Only one replacement instruction
13314 //
13315 // ---------EXAMPLE----------------------------------------------------------
13316 //
13317 // // pertinent parts of existing instructions in architecture description
13318 // instruct movI(eRegI dst, eRegI src) %{
13319 // match(Set dst (CopyI src));
13320 // %}
13321 //
13322 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13323 // match(Set dst (AddI dst src));
13324 // effect(KILL cr);
13325 // %}
13326 //
13327 // // Change (inc mov) to lea
13328 // peephole %{
13329 // // increment preceeded by register-register move
13330 // peepmatch ( incI_eReg movI );
13331 // // require that the destination register of the increment
13332 // // match the destination register of the move
13333 // peepconstraint ( 0.dst == 1.dst );
13334 // // construct a replacement instruction that sets
13335 // // the destination to ( move's source register + one )
13336 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13337 // %}
13338 //
13339 // Implementation no longer uses movX instructions since
13340 // machine-independent system no longer uses CopyX nodes.
13341 //
13342 // peephole %{
13343 // peepmatch ( incI_eReg movI );
13344 // peepconstraint ( 0.dst == 1.dst );
13345 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13346 // %}
13347 //
13348 // peephole %{
13349 // peepmatch ( decI_eReg movI );
13350 // peepconstraint ( 0.dst == 1.dst );
13351 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13352 // %}
13353 //
13354 // peephole %{
13355 // peepmatch ( addI_eReg_imm movI );
13356 // peepconstraint ( 0.dst == 1.dst );
13357 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13358 // %}
13359 //
13360 // peephole %{
13361 // peepmatch ( addP_eReg_imm movP );
13362 // peepconstraint ( 0.dst == 1.dst );
13363 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13364 // %}
13365
13366 // // Change load of spilled value to only a spill
13367 // instruct storeI(memory mem, eRegI src) %{
13368 // match(Set mem (StoreI mem src));
13369 // %}
13370 //
13371 // instruct loadI(eRegI dst, memory mem) %{
13372 // match(Set dst (LoadI mem));
13373 // %}
13374 //
13375 peephole %{
13376 peepmatch ( loadI storeI );
13377 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13378 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13379 %}
13380
13381 //----------SMARTSPILL RULES---------------------------------------------------
13382 // These must follow all instruction definitions as they use the names
13383 // defined in the instructions definitions.