src/cpu/x86/vm/x86_32.ad
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7119644 Cdiff src/cpu/x86/vm/x86_32.ad
src/cpu/x86/vm/x86_32.ad
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*** 72,84 ****
reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
- // Special Registers
- reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
-
// Float registers. We treat TOS/FPR0 special. It is invisible to the
// allocator, and only shows up in the encodings.
reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
// Ok so here's the trick FPR1 is really st(0) except in the midst
--- 72,81 ----
*** 103,133 ****
reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
- // XMM registers. 128-bit registers or 4 words each, labeled a-d.
- // Word a in each register holds a Float, words ab hold a Double.
- // We currently do not use the SIMD capabilities, so registers cd
- // are unused at the moment.
- reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
- reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
- reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
- reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
- reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
- reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
- reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
- reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
- reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
- reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
- reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
- reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
- reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
- reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
- reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
- reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
-
// Specify priority of register selection within phases of register
// allocation. Highest priority is first. A useful heuristic is to
// give registers a low priority when they are required by machine
// instructions, like EAX and EDX. Registers which are used as
// pairs must fall on an even boundary (witness the FPR#L's in this list).
--- 100,109 ----
*** 136,155 ****
alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
FPR6L, FPR6H, FPR7L, FPR7H );
- alloc_class chunk1( XMM0a, XMM0b,
- XMM1a, XMM1b,
- XMM2a, XMM2b,
- XMM3a, XMM3b,
- XMM4a, XMM4b,
- XMM5a, XMM5b,
- XMM6a, XMM6b,
- XMM7a, XMM7b, EFLAGS);
-
//----------Architecture Description Register Classes--------------------------
// Several register classes are automatically defined based upon information in
// this architecture description.
// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
--- 112,122 ----
*** 157,172 ****
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
//
// Class for all registers
reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
// Class for general registers
! reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
// Class for general registers which may be used for implicit null checks on win95
// Also safe for use by tailjump. We don't want to allocate in rbp,
! reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
// Class of "X" registers
! reg_class x_reg(EBX, ECX, EDX, EAX);
// Class of registers that can appear in an address with no offset.
// EBP and ESP require an extra instruction byte for zero offset.
// Used in fast-unlock
reg_class p_reg(EDX, EDI, ESI, EBX);
// Class for general registers not including ECX
--- 124,139 ----
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
//
// Class for all registers
reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
// Class for general registers
! reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
// Class for general registers which may be used for implicit null checks on win95
// Also safe for use by tailjump. We don't want to allocate in rbp,
! reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
// Class of "X" registers
! reg_class int_x_reg(EBX, ECX, EDX, EAX);
// Class of registers that can appear in an address with no offset.
// EBP and ESP require an extra instruction byte for zero offset.
// Used in fast-unlock
reg_class p_reg(EDX, EDI, ESI, EBX);
// Class for general registers not including ECX
*** 191,202 ****
reg_class ebp_reg(EBP);
// Singleton class for stack pointer
reg_class sp_reg(ESP);
// Singleton class for instruction pointer
// reg_class ip_reg(EIP);
- // Singleton class for condition codes
- reg_class int_flags(EFLAGS);
// Class of integer register pairs
reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
// Class of integer register pairs that aligns with calling convention
reg_class eadx_reg( EAX,EDX );
reg_class ebcx_reg( ECX,EBX );
--- 158,167 ----
*** 204,236 ****
reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
// Floating point registers. Notice FPR0 is not a choice.
// FPR0 is not ever allocated; we use clever encodings to fake
// a 2-address instructions out of Intels FP stack.
! reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
! // make a register class for SSE registers
! reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
!
! // make a double register class for SSE2 registers
! reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
! XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
!
! reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
FPR7L,FPR7H );
! reg_class flt_reg0( FPR1L );
! reg_class dbl_reg0( FPR1L,FPR1H );
! reg_class dbl_reg1( FPR2L,FPR2H );
! reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
- // XMM6 and XMM7 could be used as temporary registers for long, float and
- // double values for SSE2.
- reg_class xdb_reg6( XMM6a,XMM6b );
- reg_class xdb_reg7( XMM7a,XMM7b );
%}
//----------SOURCE BLOCK-------------------------------------------------------
// This is a block of C++ code which provides values, functions, and
--- 169,190 ----
reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
// Floating point registers. Notice FPR0 is not a choice.
// FPR0 is not ever allocated; we use clever encodings to fake
// a 2-address instructions out of Intels FP stack.
! reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
! reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
FPR7L,FPR7H );
! reg_class fp_flt_reg0( FPR1L );
! reg_class fp_dbl_reg0( FPR1L,FPR1H );
! reg_class fp_dbl_reg1( FPR2L,FPR2H );
! reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
%}
//----------SOURCE BLOCK-------------------------------------------------------
// This is a block of C++ code which provides values, functions, and
*** 410,420 ****
emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
emit_d32(cbuf, disp); // Displacement // R/M byte
}
}
! // eRegI ereg, memory mem) %{ // emit_reg_mem
void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
// There is no index & no scale, use form without SIB byte
if ((index == 0x4) &&
(scale == 0) && (base != ESP_enc)) {
// If no displacement, mode is 0x0; unless base is [EBP]
--- 364,374 ----
emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
emit_d32(cbuf, disp); // Displacement // R/M byte
}
}
! // rRegI ereg, memory mem) %{ // emit_reg_mem
void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
// There is no index & no scale, use form without SIB byte
if ((index == 0x4) &&
(scale == 0) && (base != ESP_enc)) {
// If no displacement, mode is 0x0; unless base is [EBP]
*** 785,795 ****
offset, Matcher::regName[reg_lo]);
}
#endif
}
int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
! // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
return size+5+offset_size;
}
static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
--- 739,749 ----
offset, Matcher::regName[reg_lo]);
}
#endif
}
int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
! // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
return size+5+offset_size;
}
static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
*** 819,829 ****
st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
}
}
#endif
}
! // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
// Only MOVAPS SSE prefix uses 1 byte.
int sz = 4;
if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
return size + sz;
--- 773,783 ----
st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
}
}
#endif
}
! // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
// Only MOVAPS SSE prefix uses 1 byte.
int sz = 4;
if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
return size + sz;
*** 901,910 ****
--- 855,966 ----
}
return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
}
+ // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
+ static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
+ int src_hi, int dst_hi, uint ireg, outputStream* st);
+
+ static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
+ int stack_offset, int reg, uint ireg, outputStream* st);
+
+ static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
+ int dst_offset, uint ireg, outputStream* st) {
+ int calc_size = 0;
+ int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
+ int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
+ switch (ireg) {
+ case Op_VecS:
+ calc_size = 3+src_offset_size + 3+dst_offset_size;
+ break;
+ case Op_VecD:
+ calc_size = 3+src_offset_size + 3+dst_offset_size;
+ src_offset += 4;
+ dst_offset += 4;
+ src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
+ dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
+ calc_size += 3+src_offset_size + 3+dst_offset_size;
+ break;
+ case Op_VecX:
+ calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
+ break;
+ case Op_VecY:
+ calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
+ break;
+ default:
+ ShouldNotReachHere();
+ }
+ if (cbuf) {
+ MacroAssembler _masm(cbuf);
+ int offset = __ offset();
+ switch (ireg) {
+ case Op_VecS:
+ __ pushl(Address(rsp, src_offset));
+ __ popl (Address(rsp, dst_offset));
+ break;
+ case Op_VecD:
+ __ pushl(Address(rsp, src_offset));
+ __ popl (Address(rsp, dst_offset));
+ __ pushl(Address(rsp, src_offset+4));
+ __ popl (Address(rsp, dst_offset+4));
+ break;
+ case Op_VecX:
+ __ movdqu(Address(rsp, -16), xmm0);
+ __ movdqu(xmm0, Address(rsp, src_offset));
+ __ movdqu(Address(rsp, dst_offset), xmm0);
+ __ movdqu(xmm0, Address(rsp, -16));
+ break;
+ case Op_VecY:
+ __ vmovdqu(Address(rsp, -32), xmm0);
+ __ vmovdqu(xmm0, Address(rsp, src_offset));
+ __ vmovdqu(Address(rsp, dst_offset), xmm0);
+ __ vmovdqu(xmm0, Address(rsp, -32));
+ break;
+ default:
+ ShouldNotReachHere();
+ }
+ int size = __ offset() - offset;
+ assert(size == calc_size, "incorrect size calculattion");
+ return size;
+ #ifndef PRODUCT
+ } else if (!do_size) {
+ switch (ireg) {
+ case Op_VecS:
+ st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
+ "popl [rsp + #%d]",
+ src_offset, dst_offset);
+ break;
+ case Op_VecD:
+ st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
+ "popq [rsp + #%d]\n\t"
+ "pushl [rsp + #%d]\n\t"
+ "popq [rsp + #%d]",
+ src_offset, dst_offset, src_offset+4, dst_offset+4);
+ break;
+ case Op_VecX:
+ st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
+ "movdqu xmm0, [rsp + #%d]\n\t"
+ "movdqu [rsp + #%d], xmm0\n\t"
+ "movdqu xmm0, [rsp - #16]",
+ src_offset, dst_offset);
+ break;
+ case Op_VecY:
+ st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
+ "vmovdqu xmm0, [rsp + #%d]\n\t"
+ "vmovdqu [rsp + #%d], xmm0\n\t"
+ "vmovdqu xmm0, [rsp - #32]",
+ src_offset, dst_offset);
+ break;
+ default:
+ ShouldNotReachHere();
+ }
+ #endif
+ }
+ return calc_size;
+ }
+
uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
// Get registers to move
OptoReg::Name src_second = ra_->get_reg_second(in(1));
OptoReg::Name src_first = ra_->get_reg_first(in(1));
OptoReg::Name dst_second = ra_->get_reg_second(this );
*** 921,930 ****
--- 977,1009 ----
int size = 0;
if( src_first == dst_first && src_second == dst_second )
return size; // Self copy, no move
+ if (bottom_type()->isa_vect() != NULL) {
+ uint ireg = ideal_reg();
+ assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
+ assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
+ assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
+ if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
+ // mem -> mem
+ int src_offset = ra_->reg2offset(src_first);
+ int dst_offset = ra_->reg2offset(dst_first);
+ return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
+ } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
+ return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
+ } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
+ int stack_offset = ra_->reg2offset(dst_first);
+ return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
+ } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
+ int stack_offset = ra_->reg2offset(src_first);
+ return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
+ } else {
+ ShouldNotReachHere();
+ }
+ }
+
// --------------------------------------
// Check for mem-mem move. push/pop to move.
if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
if( src_second == dst_first ) { // overlapping stack copy ranges
assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
*** 1311,1330 ****
// This is UltraSparc specific, true just means we have fast l2f conversion
const bool Matcher::convL2FSupported(void) {
return true;
}
- // Vector width in bytes
- const uint Matcher::vector_width_in_bytes(void) {
- return UseSSE >= 2 ? 8 : 0;
- }
-
- // Vector ideal reg
- const uint Matcher::vector_ideal_reg(void) {
- return Op_RegD;
- }
-
// Is this branch offset short enough that a short branch can be used?
//
// NOTE: If the platform does not provide any short branch variants, then
// this method should return false for offset 0.
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
--- 1390,1399 ----
*** 1450,1460 ****
// function is used on startup to build the trampoline stubs in generateOptoStub.
// Registers not mentioned will be killed by the VM call in the trampoline, and
// arguments in those registers not be available to the callee.
bool Matcher::can_be_java_arg( int reg ) {
if( reg == ECX_num || reg == EDX_num ) return true;
! if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
return false;
}
bool Matcher::is_spillable_arg( int reg ) {
--- 1519,1529 ----
// function is used on startup to build the trampoline stubs in generateOptoStub.
// Registers not mentioned will be killed by the VM call in the trampoline, and
// arguments in those registers not be available to the callee.
bool Matcher::can_be_java_arg( int reg ) {
if( reg == ECX_num || reg == EDX_num ) return true;
! if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
return false;
}
bool Matcher::is_spillable_arg( int reg ) {
*** 1563,1582 ****
enc_class SizePrefix %{
emit_opcode(cbuf,0x66);
%}
! enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
emit_opcode(cbuf,$opcode$$constant);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class mov_r32_imm0( eRegI dst ) %{
emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
emit_d32 ( cbuf, 0x0 ); // imm32==0x0
%}
enc_class cdq_enc %{
--- 1632,1651 ----
enc_class SizePrefix %{
emit_opcode(cbuf,0x66);
%}
! enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
emit_opcode(cbuf,$opcode$$constant);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class mov_r32_imm0( rRegI dst ) %{
emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
emit_d32 ( cbuf, 0x0 ); // imm32==0x0
%}
enc_class cdq_enc %{
*** 1619,1629 ****
// idiv (note: must be emitted by the user of this rule)
// normal:
%}
// Dense encoding for older common ops
! enc_class Opc_plus(immI opcode, eRegI reg) %{
emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
%}
// Opcde enc_class for 8/32 bit immediate instructions with sign-extension
--- 1688,1698 ----
// idiv (note: must be emitted by the user of this rule)
// normal:
%}
// Dense encoding for older common ops
! enc_class Opc_plus(immI opcode, rRegI reg) %{
emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
%}
// Opcde enc_class for 8/32 bit immediate instructions with sign-extension
*** 1635,1645 ****
else { // If 32-bit immediate
emit_opcode(cbuf, $primary);
}
%}
! enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
// Emit primary opcode and set sign-extend bit
// Check for 8-bit immediate, and set sign extend bit in opcode
if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
emit_opcode(cbuf, $primary | 0x02); }
else { // If 32-bit immediate
--- 1704,1714 ----
else { // If 32-bit immediate
emit_opcode(cbuf, $primary);
}
%}
! enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
// Emit primary opcode and set sign-extend bit
// Check for 8-bit immediate, and set sign extend bit in opcode
if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
emit_opcode(cbuf, $primary | 0x02); }
else { // If 32-bit immediate
*** 1680,1690 ****
emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
else emit_d32(cbuf,con);
%}
! enc_class OpcSReg (eRegI dst) %{ // BSWAP
emit_cc(cbuf, $secondary, $dst$$reg );
%}
enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
int destlo = $dst$$reg;
--- 1749,1759 ----
emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
else emit_d32(cbuf,con);
%}
! enc_class OpcSReg (rRegI dst) %{ // BSWAP
emit_cc(cbuf, $secondary, $dst$$reg );
%}
enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
int destlo = $dst$$reg;
*** 1698,1708 ****
// xchg lo and hi
emit_opcode(cbuf, 0x87);
emit_rm(cbuf, 0x3, destlo, desthi);
%}
! enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
emit_rm(cbuf, 0x3, $secondary, $div$$reg );
%}
enc_class enc_cmov(cmpOp cop ) %{ // CMOV
$$$emit8$primary;
--- 1767,1777 ----
// xchg lo and hi
emit_opcode(cbuf, 0x87);
emit_rm(cbuf, 0x3, destlo, desthi);
%}
! enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
emit_rm(cbuf, 0x3, $secondary, $div$$reg );
%}
enc_class enc_cmov(cmpOp cop ) %{ // CMOV
$$$emit8$primary;
*** 1889,1912 ****
// $$$emit8$primary;
// emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
// runtime_call_Relocation::spec(), RELOC_IMM32 );
// %}
! enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
$$$emit8$primary;
emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
$$$emit8$shift$$constant;
%}
! enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
// Load immediate does not have a zero or sign extended version
// for 8-bit immediates
emit_opcode(cbuf, 0xB8 + $dst$$reg);
$$$emit32$src$$constant;
%}
! enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
// Load immediate does not have a zero or sign extended version
// for 8-bit immediates
emit_opcode(cbuf, $primary + $dst$$reg);
$$$emit32$src$$constant;
%}
--- 1958,1981 ----
// $$$emit8$primary;
// emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
// runtime_call_Relocation::spec(), RELOC_IMM32 );
// %}
! enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
$$$emit8$primary;
emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
$$$emit8$shift$$constant;
%}
! enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
// Load immediate does not have a zero or sign extended version
// for 8-bit immediates
emit_opcode(cbuf, 0xB8 + $dst$$reg);
$$$emit32$src$$constant;
%}
! enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
// Load immediate does not have a zero or sign extended version
// for 8-bit immediates
emit_opcode(cbuf, $primary + $dst$$reg);
$$$emit32$src$$constant;
%}
*** 1941,1959 ****
}
%}
// Encode a reg-reg copy. If it is useless, then empty encoding.
! enc_class enc_Copy( eRegI dst, eRegI src ) %{
encode_Copy( cbuf, $dst$$reg, $src$$reg );
%}
! enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
encode_Copy( cbuf, $dst$$reg, $src$$reg );
%}
! enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
$$$emit8$primary;
--- 2010,2028 ----
}
%}
// Encode a reg-reg copy. If it is useless, then empty encoding.
! enc_class enc_Copy( rRegI dst, rRegI src ) %{
encode_Copy( cbuf, $dst$$reg, $src$$reg );
%}
! enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
encode_Copy( cbuf, $dst$$reg, $src$$reg );
%}
! enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
$$$emit8$primary;
*** 1971,1981 ****
enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
%}
! enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
%}
enc_class Con32 (immI src) %{ // Con32(storeImmI)
// Output immediate
--- 2040,2050 ----
enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
%}
! enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
%}
enc_class Con32 (immI src) %{ // Con32(storeImmI)
// Output immediate
*** 2066,2076 ****
enc_class set_instruction_start( ) %{
cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
%}
! enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
int reg_encoding = $ereg$$reg;
int base = $mem$$base;
int index = $mem$$index;
int scale = $mem$$scale;
int displace = $mem$$disp;
--- 2135,2145 ----
enc_class set_instruction_start( ) %{
cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
%}
! enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
int reg_encoding = $ereg$$reg;
int base = $mem$$base;
int index = $mem$$index;
int scale = $mem$$scale;
int displace = $mem$$disp;
*** 2130,2140 ****
emit_rm(cbuf, 0x3, r2, r2);
%}
// Clone of RegMem but accepts an extra parameter to access each
// half of a double in memory; it never needs relocation info.
! enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
emit_opcode(cbuf,$opcode$$constant);
int reg_encoding = $rm_reg$$reg;
int base = $mem$$base;
int index = $mem$$index;
int scale = $mem$$scale;
--- 2199,2209 ----
emit_rm(cbuf, 0x3, r2, r2);
%}
// Clone of RegMem but accepts an extra parameter to access each
// half of a double in memory; it never needs relocation info.
! enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
emit_opcode(cbuf,$opcode$$constant);
int reg_encoding = $rm_reg$$reg;
int base = $mem$$base;
int index = $mem$$index;
int scale = $mem$$scale;
*** 2166,2186 ****
int displace = $mem$$disp;
bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
%}
! enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
int reg_encoding = $dst$$reg;
int base = $src0$$reg; // 0xFFFFFFFF indicates no base
int index = 0x04; // 0x04 indicates no index
int scale = 0x00; // 0x00 indicates no scale
int displace = $src1$$constant; // 0x00 indicates no displacement
bool disp_is_oop = false;
encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
%}
! enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
// Compare dst,src
emit_opcode(cbuf,0x3B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
// jmp dst < src around move
emit_opcode(cbuf,0x7C);
--- 2235,2255 ----
int displace = $mem$$disp;
bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
%}
! enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
int reg_encoding = $dst$$reg;
int base = $src0$$reg; // 0xFFFFFFFF indicates no base
int index = 0x04; // 0x04 indicates no index
int scale = 0x00; // 0x00 indicates no scale
int displace = $src1$$constant; // 0x00 indicates no displacement
bool disp_is_oop = false;
encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
%}
! enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
// Compare dst,src
emit_opcode(cbuf,0x3B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
// jmp dst < src around move
emit_opcode(cbuf,0x7C);
*** 2188,2198 ****
// move dst,src
emit_opcode(cbuf,0x8B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
// Compare dst,src
emit_opcode(cbuf,0x3B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
// jmp dst > src around move
emit_opcode(cbuf,0x7F);
--- 2257,2267 ----
// move dst,src
emit_opcode(cbuf,0x8B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
%}
! enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
// Compare dst,src
emit_opcode(cbuf,0x3B);
emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
// jmp dst > src around move
emit_opcode(cbuf,0x7F);
*** 2219,2229 ****
cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
emit_opcode(cbuf,$primary);
encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
%}
! enc_class neg_reg(eRegI dst) %{
// NEG $dst
emit_opcode(cbuf,0xF7);
emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
%}
--- 2288,2298 ----
cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
emit_opcode(cbuf,$primary);
encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
%}
! enc_class neg_reg(rRegI dst) %{
// NEG $dst
emit_opcode(cbuf,0xF7);
emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
%}
*** 2249,2259 ****
// ADD $p,$tmp
emit_opcode(cbuf,0x03);
emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
%}
! enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
int tmpReg = $tmp$$reg;
// SUB $p,$q
emit_opcode(cbuf,0x2B);
emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
--- 2318,2328 ----
// ADD $p,$tmp
emit_opcode(cbuf,0x03);
emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
%}
! enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
int tmpReg = $tmp$$reg;
// SUB $p,$q
emit_opcode(cbuf,0x2B);
emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
*** 2388,2403 ****
emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
emit_opcode( cbuf, 0xC8+$dst$$reg );
%}
// Special case for moving an integer register to a stack slot.
! enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
%}
// Special case for moving a register to a stack slot.
! enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
// Opcode already emitted
emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
emit_d32(cbuf, $dst$$disp); // Displacement
%}
--- 2457,2472 ----
emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
emit_opcode( cbuf, 0xC8+$dst$$reg );
%}
// Special case for moving an integer register to a stack slot.
! enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
%}
// Special case for moving a register to a stack slot.
! enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
// Opcode already emitted
emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
emit_d32(cbuf, $dst$$disp); // Displacement
%}
*** 2638,2648 ****
// less_result = 1;
// greater_result = -1;
// equal_result = 0;
// nan_result = -1;
! enc_class CmpF_Result(eRegI dst) %{
// fnstsw_ax();
emit_opcode( cbuf, 0xDF);
emit_opcode( cbuf, 0xE0);
// sahf
emit_opcode( cbuf, 0x9E);
--- 2707,2717 ----
// less_result = 1;
// greater_result = -1;
// equal_result = 0;
// nan_result = -1;
! enc_class CmpF_Result(rRegI dst) %{
// fnstsw_ax();
emit_opcode( cbuf, 0xDF);
emit_opcode( cbuf, 0xE0);
// sahf
emit_opcode( cbuf, 0x9E);
*** 2683,2693 ****
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
// done:
%}
! enc_class convert_int_long( regL dst, eRegI src ) %{
// mov $dst.lo,$src
int dst_encoding = $dst$$reg;
int src_encoding = $src$$reg;
encode_Copy( cbuf, dst_encoding , src_encoding );
// mov $dst.hi,$src
--- 2752,2762 ----
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
// done:
%}
! enc_class convert_int_long( regL dst, rRegI src ) %{
// mov $dst.lo,$src
int dst_encoding = $dst$$reg;
int src_encoding = $src$$reg;
encode_Copy( cbuf, dst_encoding , src_encoding );
// mov $dst.hi,$src
*** 2752,2762 ****
// MUL EDX:EAX, src
emit_opcode( cbuf, 0xF7 );
emit_rm( cbuf, 0x3, 0x4, $src$$reg);
%}
! enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
// Basic idea: lo(result) = lo(x_lo * y_lo)
// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
// MOV $tmp,$src.lo
encode_Copy( cbuf, $tmp$$reg, $src$$reg );
// IMUL $tmp,EDX
--- 2821,2831 ----
// MUL EDX:EAX, src
emit_opcode( cbuf, 0xF7 );
emit_rm( cbuf, 0x3, 0x4, $src$$reg);
%}
! enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
// Basic idea: lo(result) = lo(x_lo * y_lo)
// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
// MOV $tmp,$src.lo
encode_Copy( cbuf, $tmp$$reg, $src$$reg );
// IMUL $tmp,EDX
*** 2778,2788 ****
// ADD EDX,ESI
emit_opcode( cbuf, 0x03 );
emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
%}
! enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
// Basic idea: lo(result) = lo(src * y_lo)
// hi(result) = hi(src * y_lo) + lo(src * y_hi)
// IMUL $tmp,EDX,$src
emit_opcode( cbuf, 0x6B );
emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
--- 2847,2857 ----
// ADD EDX,ESI
emit_opcode( cbuf, 0x03 );
emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
%}
! enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
// Basic idea: lo(result) = lo(src * y_lo)
// hi(result) = hi(src * y_lo) + lo(src * y_hi)
// IMUL $tmp,EDX,$src
emit_opcode( cbuf, 0x6B );
emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
*** 2834,2844 ****
emit_opcode(cbuf, 0x83); // add SP, #framesize
emit_rm(cbuf, 0x3, 0x00, ESP_enc);
emit_d8(cbuf, 4*4);
%}
! enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
// MOV $tmp,$src.lo
emit_opcode(cbuf, 0x8B);
emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
// OR $tmp,$src.hi
emit_opcode(cbuf, 0x0B);
--- 2903,2913 ----
emit_opcode(cbuf, 0x83); // add SP, #framesize
emit_rm(cbuf, 0x3, 0x00, ESP_enc);
emit_d8(cbuf, 4*4);
%}
! enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
// MOV $tmp,$src.lo
emit_opcode(cbuf, 0x8B);
emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
// OR $tmp,$src.hi
emit_opcode(cbuf, 0x0B);
*** 2855,2865 ****
// CMP $src1.hi,$src2.hi
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
%}
! enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
// CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
// MOV $tmp,$src1.hi
emit_opcode( cbuf, 0x8B );
--- 2924,2934 ----
// CMP $src1.hi,$src2.hi
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
%}
! enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
// CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
emit_opcode( cbuf, 0x3B );
emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
// MOV $tmp,$src1.hi
emit_opcode( cbuf, 0x8B );
*** 2867,2877 ****
// SBB $tmp,$src2.hi\t! Compute flags for long compare
emit_opcode( cbuf, 0x1B );
emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
%}
! enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
// XOR $tmp,$tmp
emit_opcode(cbuf,0x33); // XOR
emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
// CMP $tmp,$src.lo
emit_opcode( cbuf, 0x3B );
--- 2936,2946 ----
// SBB $tmp,$src2.hi\t! Compute flags for long compare
emit_opcode( cbuf, 0x1B );
emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
%}
! enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
// XOR $tmp,$tmp
emit_opcode(cbuf,0x33); // XOR
emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
// CMP $tmp,$src.lo
emit_opcode( cbuf, 0x3B );
*** 3760,3772 ****
static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
// in SSE2+ mode we want to keep the FPU stack clean so pretend
// that C functions return float and double results in XMM0.
if( ideal_reg == Op_RegD && UseSSE>=2 )
! return OptoRegPair(XMM0b_num,XMM0a_num);
if( ideal_reg == Op_RegF && UseSSE>=2 )
! return OptoRegPair(OptoReg::Bad,XMM0a_num);
return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
%}
// Location of return values
--- 3829,3841 ----
static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
// in SSE2+ mode we want to keep the FPU stack clean so pretend
// that C functions return float and double results in XMM0.
if( ideal_reg == Op_RegD && UseSSE>=2 )
! return OptoRegPair(XMM0b_num,XMM0_num);
if( ideal_reg == Op_RegF && UseSSE>=2 )
! return OptoRegPair(OptoReg::Bad,XMM0_num);
return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
%}
// Location of return values
*** 3773,3785 ****
return_value %{
assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
if( ideal_reg == Op_RegD && UseSSE>=2 )
! return OptoRegPair(XMM0b_num,XMM0a_num);
if( ideal_reg == Op_RegF && UseSSE>=1 )
! return OptoRegPair(OptoReg::Bad,XMM0a_num);
return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
%}
%}
--- 3842,3854 ----
return_value %{
assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
if( ideal_reg == Op_RegD && UseSSE>=2 )
! return OptoRegPair(XMM0b_num,XMM0_num);
if( ideal_reg == Op_RegF && UseSSE>=1 )
! return OptoRegPair(OptoReg::Bad,XMM0_num);
return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
%}
%}
*** 4145,4156 ****
interface(CONST_INTER);
%}
// Register Operands
// Integer Register
! operand eRegI() %{
! constraint(ALLOC_IN_RC(e_reg));
match(RegI);
match(xRegI);
match(eAXRegI);
match(eBXRegI);
match(eCXRegI);
--- 4214,4225 ----
interface(CONST_INTER);
%}
// Register Operands
// Integer Register
! operand rRegI() %{
! constraint(ALLOC_IN_RC(int_reg));
match(RegI);
match(xRegI);
match(eAXRegI);
match(eBXRegI);
match(eCXRegI);
*** 4161,4172 ****
format %{ %}
interface(REG_INTER);
%}
// Subset of Integer Register
! operand xRegI(eRegI reg) %{
! constraint(ALLOC_IN_RC(x_reg));
match(reg);
match(eAXRegI);
match(eBXRegI);
match(eCXRegI);
match(eDXRegI);
--- 4230,4241 ----
format %{ %}
interface(REG_INTER);
%}
// Subset of Integer Register
! operand xRegI(rRegI reg) %{
! constraint(ALLOC_IN_RC(int_x_reg));
match(reg);
match(eAXRegI);
match(eBXRegI);
match(eCXRegI);
match(eDXRegI);
*** 4177,4224 ****
// Special Registers
operand eAXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(eax_reg));
match(reg);
! match(eRegI);
format %{ "EAX" %}
interface(REG_INTER);
%}
// Special Registers
operand eBXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(ebx_reg));
match(reg);
! match(eRegI);
format %{ "EBX" %}
interface(REG_INTER);
%}
operand eCXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(ecx_reg));
match(reg);
! match(eRegI);
format %{ "ECX" %}
interface(REG_INTER);
%}
operand eDXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(edx_reg));
match(reg);
! match(eRegI);
format %{ "EDX" %}
interface(REG_INTER);
%}
operand eDIRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(edi_reg));
match(reg);
! match(eRegI);
format %{ "EDI" %}
interface(REG_INTER);
%}
--- 4246,4293 ----
// Special Registers
operand eAXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(eax_reg));
match(reg);
! match(rRegI);
format %{ "EAX" %}
interface(REG_INTER);
%}
// Special Registers
operand eBXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(ebx_reg));
match(reg);
! match(rRegI);
format %{ "EBX" %}
interface(REG_INTER);
%}
operand eCXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(ecx_reg));
match(reg);
! match(rRegI);
format %{ "ECX" %}
interface(REG_INTER);
%}
operand eDXRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(edx_reg));
match(reg);
! match(rRegI);
format %{ "EDX" %}
interface(REG_INTER);
%}
operand eDIRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(edi_reg));
match(reg);
! match(rRegI);
format %{ "EDI" %}
interface(REG_INTER);
%}
*** 4261,4271 ****
// // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
// //
operand eSIRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(esi_reg));
match(reg);
! match(eRegI);
format %{ "ESI" %}
interface(REG_INTER);
%}
--- 4330,4340 ----
// // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
// //
operand eSIRegI(xRegI reg) %{
constraint(ALLOC_IN_RC(esi_reg));
match(reg);
! match(rRegI);
format %{ "ESI" %}
interface(REG_INTER);
%}
*** 4282,4292 ****
format %{ %}
interface(REG_INTER);
%}
operand eRegP() %{
! constraint(ALLOC_IN_RC(e_reg));
match(RegP);
match(eAXRegP);
match(eBXRegP);
match(eCXRegP);
match(eDIRegP);
--- 4351,4361 ----
format %{ %}
interface(REG_INTER);
%}
operand eRegP() %{
! constraint(ALLOC_IN_RC(int_reg));
match(RegP);
match(eAXRegP);
match(eBXRegP);
match(eCXRegP);
match(eDIRegP);
*** 4295,4305 ****
interface(REG_INTER);
%}
// On windows95, EBP is not safe to use for implicit null tests.
operand eRegP_no_EBP() %{
! constraint(ALLOC_IN_RC(e_reg_no_rbp));
match(RegP);
match(eAXRegP);
match(eBXRegP);
match(eCXRegP);
match(eDIRegP);
--- 4364,4374 ----
interface(REG_INTER);
%}
// On windows95, EBP is not safe to use for implicit null tests.
operand eRegP_no_EBP() %{
! constraint(ALLOC_IN_RC(int_reg_no_rbp));
match(RegP);
match(eAXRegP);
match(eBXRegP);
match(eCXRegP);
match(eDIRegP);
*** 4475,4574 ****
%}
// Float register operands
operand regDPR() %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(dbl_reg));
match(RegD);
match(regDPR1);
match(regDPR2);
format %{ %}
interface(REG_INTER);
%}
operand regDPR1(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(dbl_reg0));
match(reg);
format %{ "FPR1" %}
interface(REG_INTER);
%}
operand regDPR2(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(dbl_reg1));
match(reg);
format %{ "FPR2" %}
interface(REG_INTER);
%}
operand regnotDPR1(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(dbl_notreg0));
match(reg);
format %{ %}
interface(REG_INTER);
%}
- // XMM Double register operands
- operand regD() %{
- predicate( UseSSE>=2 );
- constraint(ALLOC_IN_RC(xdb_reg));
- match(RegD);
- match(regD6);
- match(regD7);
- format %{ %}
- interface(REG_INTER);
- %}
-
- // XMM6 double register operands
- operand regD6(regD reg) %{
- predicate( UseSSE>=2 );
- constraint(ALLOC_IN_RC(xdb_reg6));
- match(reg);
- format %{ "XMM6" %}
- interface(REG_INTER);
- %}
-
- // XMM7 double register operands
- operand regD7(regD reg) %{
- predicate( UseSSE>=2 );
- constraint(ALLOC_IN_RC(xdb_reg7));
- match(reg);
- format %{ "XMM7" %}
- interface(REG_INTER);
- %}
-
// Float register operands
operand regFPR() %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(flt_reg));
match(RegF);
match(regFPR1);
format %{ %}
interface(REG_INTER);
%}
// Float register operands
operand regFPR1(regFPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(flt_reg0));
match(reg);
format %{ "FPR1" %}
interface(REG_INTER);
%}
! // XMM register operands
operand regF() %{
predicate( UseSSE>=1 );
! constraint(ALLOC_IN_RC(xmm_reg));
match(RegF);
format %{ %}
interface(REG_INTER);
%}
//----------Memory Operands----------------------------------------------------
// Direct Memory Operand
operand direct(immP addr) %{
match(addr);
--- 4544,4623 ----
%}
// Float register operands
operand regDPR() %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_dbl_reg));
match(RegD);
match(regDPR1);
match(regDPR2);
format %{ %}
interface(REG_INTER);
%}
operand regDPR1(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_dbl_reg0));
match(reg);
format %{ "FPR1" %}
interface(REG_INTER);
%}
operand regDPR2(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_dbl_reg1));
match(reg);
format %{ "FPR2" %}
interface(REG_INTER);
%}
operand regnotDPR1(regDPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_dbl_notreg0));
match(reg);
format %{ %}
interface(REG_INTER);
%}
// Float register operands
operand regFPR() %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_flt_reg));
match(RegF);
match(regFPR1);
format %{ %}
interface(REG_INTER);
%}
// Float register operands
operand regFPR1(regFPR reg) %{
predicate( UseSSE < 2 );
! constraint(ALLOC_IN_RC(fp_flt_reg0));
match(reg);
format %{ "FPR1" %}
interface(REG_INTER);
%}
! // XMM Float register operands
operand regF() %{
predicate( UseSSE>=1 );
! constraint(ALLOC_IN_RC(float_reg));
match(RegF);
format %{ %}
interface(REG_INTER);
%}
+ // XMM Double register operands
+ operand regD() %{
+ predicate( UseSSE>=2 );
+ constraint(ALLOC_IN_RC(double_reg));
+ match(RegD);
+ format %{ %}
+ interface(REG_INTER);
+ %}
+
//----------Memory Operands----------------------------------------------------
// Direct Memory Operand
operand direct(immP addr) %{
match(addr);
*** 4581,4591 ****
%}
%}
// Indirect Memory Operand
operand indirect(eRegP reg) %{
! constraint(ALLOC_IN_RC(e_reg));
match(reg);
format %{ "[$reg]" %}
interface(MEMORY_INTER) %{
base($reg);
--- 4630,4640 ----
%}
%}
// Indirect Memory Operand
operand indirect(eRegP reg) %{
! constraint(ALLOC_IN_RC(int_reg));
match(reg);
format %{ "[$reg]" %}
interface(MEMORY_INTER) %{
base($reg);
*** 4620,4630 ****
disp($off);
%}
%}
// Indirect Memory Plus Long Offset Operand
! operand indOffset32X(eRegI reg, immP off) %{
match(AddP off reg);
format %{ "[$reg + $off]" %}
interface(MEMORY_INTER) %{
base($reg);
--- 4669,4679 ----
disp($off);
%}
%}
// Indirect Memory Plus Long Offset Operand
! operand indOffset32X(rRegI reg, immP off) %{
match(AddP off reg);
format %{ "[$reg + $off]" %}
interface(MEMORY_INTER) %{
base($reg);
*** 4633,4643 ****
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
match(AddP (AddP reg ireg) off);
op_cost(10);
format %{"[$reg + $off + $ireg]" %}
interface(MEMORY_INTER) %{
--- 4682,4692 ----
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
match(AddP (AddP reg ireg) off);
op_cost(10);
format %{"[$reg + $off + $ireg]" %}
interface(MEMORY_INTER) %{
*** 4647,4657 ****
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndex(eRegP reg, eRegI ireg) %{
match(AddP reg ireg);
op_cost(10);
format %{"[$reg + $ireg]" %}
interface(MEMORY_INTER) %{
--- 4696,4706 ----
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndex(eRegP reg, rRegI ireg) %{
match(AddP reg ireg);
op_cost(10);
format %{"[$reg + $ireg]" %}
interface(MEMORY_INTER) %{
*** 4665,4675 ****
// // -------------------------------------------------------------------------
// // 486 architecture doesn't support "scale * index + offset" with out a base
// // -------------------------------------------------------------------------
// // Scaled Memory Operands
// // Indirect Memory Times Scale Plus Offset Operand
! // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
// match(AddP off (LShiftI ireg scale));
//
// op_cost(10);
// format %{"[$off + $ireg << $scale]" %}
// interface(MEMORY_INTER) %{
--- 4714,4724 ----
// // -------------------------------------------------------------------------
// // 486 architecture doesn't support "scale * index + offset" with out a base
// // -------------------------------------------------------------------------
// // Scaled Memory Operands
// // Indirect Memory Times Scale Plus Offset Operand
! // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
// match(AddP off (LShiftI ireg scale));
//
// op_cost(10);
// format %{"[$off + $ireg << $scale]" %}
// interface(MEMORY_INTER) %{
*** 4679,4689 ****
// disp($off);
// %}
// %}
// Indirect Memory Times Scale Plus Index Register
! operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
match(AddP reg (LShiftI ireg scale));
op_cost(10);
format %{"[$reg + $ireg << $scale]" %}
interface(MEMORY_INTER) %{
--- 4728,4738 ----
// disp($off);
// %}
// %}
// Indirect Memory Times Scale Plus Index Register
! operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
match(AddP reg (LShiftI ireg scale));
op_cost(10);
format %{"[$reg + $ireg << $scale]" %}
interface(MEMORY_INTER) %{
*** 4693,4703 ****
disp(0x0);
%}
%}
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
! operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
match(AddP (AddP reg (LShiftI ireg scale)) off);
op_cost(10);
format %{"[$reg + $off + $ireg << $scale]" %}
interface(MEMORY_INTER) %{
--- 4742,4752 ----
disp(0x0);
%}
%}
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
! operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
match(AddP (AddP reg (LShiftI ireg scale)) off);
op_cost(10);
format %{"[$reg + $off + $ireg << $scale]" %}
interface(MEMORY_INTER) %{
*** 4821,4831 ****
//----------Memory Operands - Win95 Implicit Null Variants----------------
// Indirect Memory Operand
operand indirect_win95_safe(eRegP_no_EBP reg)
%{
! constraint(ALLOC_IN_RC(e_reg));
match(reg);
op_cost(100);
format %{ "[$reg]" %}
interface(MEMORY_INTER) %{
--- 4870,4880 ----
//----------Memory Operands - Win95 Implicit Null Variants----------------
// Indirect Memory Operand
operand indirect_win95_safe(eRegP_no_EBP reg)
%{
! constraint(ALLOC_IN_RC(int_reg));
match(reg);
op_cost(100);
format %{ "[$reg]" %}
interface(MEMORY_INTER) %{
*** 4865,4875 ****
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
%{
match(AddP (AddP reg ireg) off);
op_cost(100);
format %{"[$reg + $off + $ireg]" %}
--- 4914,4924 ----
disp($off);
%}
%}
// Indirect Memory Plus Index Register Plus Offset Operand
! operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
%{
match(AddP (AddP reg ireg) off);
op_cost(100);
format %{"[$reg + $off + $ireg]" %}
*** 4880,4890 ****
disp($off);
%}
%}
// Indirect Memory Times Scale Plus Index Register
! operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
%{
match(AddP reg (LShiftI ireg scale));
op_cost(100);
format %{"[$reg + $ireg << $scale]" %}
--- 4929,4939 ----
disp($off);
%}
%}
// Indirect Memory Times Scale Plus Index Register
! operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
%{
match(AddP reg (LShiftI ireg scale));
op_cost(100);
format %{"[$reg + $ireg << $scale]" %}
*** 4895,4905 ****
disp(0x0);
%}
%}
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
! operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
%{
match(AddP (AddP reg (LShiftI ireg scale)) off);
op_cost(100);
format %{"[$reg + $off + $ireg << $scale]" %}
--- 4944,4954 ----
disp(0x0);
%}
%}
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
! operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
%{
match(AddP (AddP reg (LShiftI ireg scale)) off);
op_cost(100);
format %{"[$reg + $off + $ireg << $scale]" %}
*** 5084,5094 ****
// Then: _long if it's a pair of instructions implementing a long
// Then: _fat if it requires the big decoder
// Or: _mem if it requires the big decoder and a memory unit.
// Integer ALU reg operation
! pipe_class ialu_reg(eRegI dst) %{
single_instruction;
dst : S4(write);
dst : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
--- 5133,5143 ----
// Then: _long if it's a pair of instructions implementing a long
// Then: _fat if it requires the big decoder
// Or: _mem if it requires the big decoder and a memory unit.
// Integer ALU reg operation
! pipe_class ialu_reg(rRegI dst) %{
single_instruction;
dst : S4(write);
dst : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
*** 5102,5112 ****
DECODE : S0(2); // any 2 decoders
ALU : S3(2); // both alus
%}
// Integer ALU reg operation using big decoder
! pipe_class ialu_reg_fat(eRegI dst) %{
single_instruction;
dst : S4(write);
dst : S3(read);
D0 : S0; // big decoder only
ALU : S3; // any alu
--- 5151,5161 ----
DECODE : S0(2); // any 2 decoders
ALU : S3(2); // both alus
%}
// Integer ALU reg operation using big decoder
! pipe_class ialu_reg_fat(rRegI dst) %{
single_instruction;
dst : S4(write);
dst : S3(read);
D0 : S0; // big decoder only
ALU : S3; // any alu
*** 5120,5130 ****
D0 : S0(2); // big decoder only; twice
ALU : S3(2); // any 2 alus
%}
// Integer ALU reg-reg operation
! pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
single_instruction;
dst : S4(write);
src : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
--- 5169,5179 ----
D0 : S0(2); // big decoder only; twice
ALU : S3(2); // any 2 alus
%}
// Integer ALU reg-reg operation
! pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
single_instruction;
dst : S4(write);
src : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
*** 5138,5148 ****
DECODE : S0(2); // any 2 decoders
ALU : S3(2); // both alus
%}
// Integer ALU reg-reg operation
! pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
single_instruction;
dst : S4(write);
src : S3(read);
D0 : S0; // big decoder only
ALU : S3; // any alu
--- 5187,5197 ----
DECODE : S0(2); // any 2 decoders
ALU : S3(2); // both alus
%}
// Integer ALU reg-reg operation
! pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
single_instruction;
dst : S4(write);
src : S3(read);
D0 : S0; // big decoder only
ALU : S3; // any alu
*** 5156,5166 ****
D0 : S0(2); // big decoder only; twice
ALU : S3(2); // both alus
%}
// Integer ALU reg-mem operation
! pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
single_instruction;
dst : S5(write);
mem : S3(read);
D0 : S0; // big decoder only
ALU : S4; // any alu
--- 5205,5215 ----
D0 : S0(2); // big decoder only; twice
ALU : S3(2); // both alus
%}
// Integer ALU reg-mem operation
! pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
single_instruction;
dst : S5(write);
mem : S3(read);
D0 : S0; // big decoder only
ALU : S4; // any alu
*** 5185,5195 ****
D0 : S0; // big decoder only
MEM : S3; // any mem
%}
// Integer Store to Memory
! pipe_class ialu_mem_reg(memory mem, eRegI src) %{
single_instruction;
mem : S3(read);
src : S5(read);
D0 : S0; // big decoder only
ALU : S4; // any alu
--- 5234,5244 ----
D0 : S0; // big decoder only
MEM : S3; // any mem
%}
// Integer Store to Memory
! pipe_class ialu_mem_reg(memory mem, rRegI src) %{
single_instruction;
mem : S3(read);
src : S5(read);
D0 : S0; // big decoder only
ALU : S4; // any alu
*** 5214,5262 ****
ALU : S4; // any alu
MEM : S3;
%}
// Integer ALU0 reg-reg operation
! pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
single_instruction;
dst : S4(write);
src : S3(read);
D0 : S0; // Big decoder only
ALU0 : S3; // only alu0
%}
// Integer ALU0 reg-mem operation
! pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
single_instruction;
dst : S5(write);
mem : S3(read);
D0 : S0; // big decoder only
ALU0 : S4; // ALU0 only
MEM : S3; // any mem
%}
// Integer ALU reg-reg operation
! pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
src2 : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
%}
// Integer ALU reg-imm operation
! pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
%}
// Integer ALU reg-mem operation
! pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
src2 : S3(read);
D0 : S0; // big decoder only
--- 5263,5311 ----
ALU : S4; // any alu
MEM : S3;
%}
// Integer ALU0 reg-reg operation
! pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
single_instruction;
dst : S4(write);
src : S3(read);
D0 : S0; // Big decoder only
ALU0 : S3; // only alu0
%}
// Integer ALU0 reg-mem operation
! pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
single_instruction;
dst : S5(write);
mem : S3(read);
D0 : S0; // big decoder only
ALU0 : S4; // ALU0 only
MEM : S3; // any mem
%}
// Integer ALU reg-reg operation
! pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
src2 : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
%}
// Integer ALU reg-imm operation
! pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
DECODE : S0; // any decoder
ALU : S3; // any alu
%}
// Integer ALU reg-mem operation
! pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
single_instruction;
cr : S4(write);
src1 : S3(read);
src2 : S3(read);
D0 : S0; // big decoder only
*** 5263,5291 ****
ALU : S4; // any alu
MEM : S3;
%}
// Conditional move reg-reg
! pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
instruction_count(4);
y : S4(read);
q : S3(read);
p : S3(read);
DECODE : S0(4); // any decoder
%}
// Conditional move reg-reg
! pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
single_instruction;
dst : S4(write);
src : S3(read);
cr : S3(read);
DECODE : S0; // any decoder
%}
// Conditional move reg-mem
! pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
single_instruction;
dst : S4(write);
src : S3(read);
cr : S3(read);
DECODE : S0; // any decoder
--- 5312,5340 ----
ALU : S4; // any alu
MEM : S3;
%}
// Conditional move reg-reg
! pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
instruction_count(4);
y : S4(read);
q : S3(read);
p : S3(read);
DECODE : S0(4); // any decoder
%}
// Conditional move reg-reg
! pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
single_instruction;
dst : S4(write);
src : S3(read);
cr : S3(read);
DECODE : S0; // any decoder
%}
// Conditional move reg-mem
! pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
single_instruction;
dst : S4(write);
src : S3(read);
cr : S3(read);
DECODE : S0; // any decoder
*** 5532,5542 ****
// ins_encode -- A list of encode classes with parameters. The encode class
// name must have been defined in an 'enc_class' specification
// in the encode section of the architecture description.
//----------BSWAP-Instruction--------------------------------------------------
! instruct bytes_reverse_int(eRegI dst) %{
match(Set dst (ReverseBytesI dst));
format %{ "BSWAP $dst" %}
opcode(0x0F, 0xC8);
ins_encode( OpcP, OpcSReg(dst) );
--- 5581,5591 ----
// ins_encode -- A list of encode classes with parameters. The encode class
// name must have been defined in an 'enc_class' specification
// in the encode section of the architecture description.
//----------BSWAP-Instruction--------------------------------------------------
! instruct bytes_reverse_int(rRegI dst) %{
match(Set dst (ReverseBytesI dst));
format %{ "BSWAP $dst" %}
opcode(0x0F, 0xC8);
ins_encode( OpcP, OpcSReg(dst) );
*** 5553,5563 ****
ins_cost(125);
ins_encode( bswap_long_bytes(dst) );
ins_pipe( ialu_reg_reg);
%}
! instruct bytes_reverse_unsigned_short(eRegI dst) %{
match(Set dst (ReverseBytesUS dst));
format %{ "BSWAP $dst\n\t"
"SHR $dst,16\n\t" %}
ins_encode %{
--- 5602,5612 ----
ins_cost(125);
ins_encode( bswap_long_bytes(dst) );
ins_pipe( ialu_reg_reg);
%}
! instruct bytes_reverse_unsigned_short(rRegI dst) %{
match(Set dst (ReverseBytesUS dst));
format %{ "BSWAP $dst\n\t"
"SHR $dst,16\n\t" %}
ins_encode %{
*** 5565,5575 ****
__ shrl($dst$$Register, 16);
%}
ins_pipe( ialu_reg );
%}
! instruct bytes_reverse_short(eRegI dst) %{
match(Set dst (ReverseBytesS dst));
format %{ "BSWAP $dst\n\t"
"SAR $dst,16\n\t" %}
ins_encode %{
--- 5614,5624 ----
__ shrl($dst$$Register, 16);
%}
ins_pipe( ialu_reg );
%}
! instruct bytes_reverse_short(rRegI dst) %{
match(Set dst (ReverseBytesS dst));
format %{ "BSWAP $dst\n\t"
"SAR $dst,16\n\t" %}
ins_encode %{
*** 5580,5590 ****
%}
//---------- Zeros Count Instructions ------------------------------------------
! instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
predicate(UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosI src));
effect(KILL cr);
format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
--- 5629,5639 ----
%}
//---------- Zeros Count Instructions ------------------------------------------
! instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
predicate(UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosI src));
effect(KILL cr);
format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
*** 5592,5602 ****
__ lzcntl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
predicate(!UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosI src));
effect(KILL cr);
format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
--- 5641,5651 ----
__ lzcntl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
predicate(!UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosI src));
effect(KILL cr);
format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
*** 5617,5627 ****
__ addl(Rdst, BitsPerInt - 1);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
predicate(UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
--- 5666,5676 ----
__ addl(Rdst, BitsPerInt - 1);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
predicate(UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
*** 5640,5650 ****
__ bind(done);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
predicate(!UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
--- 5689,5699 ----
__ bind(done);
%}
ins_pipe(ialu_reg);
%}
! instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
predicate(!UseCountLeadingZerosInstruction);
match(Set dst (CountLeadingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
*** 5676,5686 ****
__ addl(Rdst, BitsPerLong - 1);
%}
ins_pipe(ialu_reg);
%}
! instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (CountTrailingZerosI src));
effect(KILL cr);
format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
"JNZ done\n\t"
--- 5725,5735 ----
__ addl(Rdst, BitsPerLong - 1);
%}
ins_pipe(ialu_reg);
%}
! instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (CountTrailingZerosI src));
effect(KILL cr);
format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
"JNZ done\n\t"
*** 5695,5705 ****
__ bind(done);
%}
ins_pipe(ialu_reg);
%}
! instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
match(Set dst (CountTrailingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
"JNZ done\n\t"
--- 5744,5754 ----
__ bind(done);
%}
ins_pipe(ialu_reg);
%}
! instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
match(Set dst (CountTrailingZerosL src));
effect(TEMP dst, KILL cr);
format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
"JNZ done\n\t"
*** 5727,5737 ****
%}
//---------- Population Count Instructions -------------------------------------
! instruct popCountI(eRegI dst, eRegI src) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountI src));
format %{ "POPCNT $dst, $src" %}
ins_encode %{
--- 5776,5786 ----
%}
//---------- Population Count Instructions -------------------------------------
! instruct popCountI(rRegI dst, rRegI src) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountI src));
format %{ "POPCNT $dst, $src" %}
ins_encode %{
*** 5738,5748 ****
__ popcntl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct popCountI_mem(eRegI dst, memory mem) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountI (LoadI mem)));
format %{ "POPCNT $dst, $mem" %}
ins_encode %{
--- 5787,5797 ----
__ popcntl($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct popCountI_mem(rRegI dst, memory mem) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountI (LoadI mem)));
format %{ "POPCNT $dst, $mem" %}
ins_encode %{
*** 5750,5760 ****
%}
ins_pipe(ialu_reg);
%}
// Note: Long.bitCount(long) returns an int.
! instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountL src));
effect(KILL cr, TEMP tmp, TEMP dst);
format %{ "POPCNT $dst, $src.lo\n\t"
--- 5799,5809 ----
%}
ins_pipe(ialu_reg);
%}
// Note: Long.bitCount(long) returns an int.
! instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountL src));
effect(KILL cr, TEMP tmp, TEMP dst);
format %{ "POPCNT $dst, $src.lo\n\t"
*** 5767,5777 ****
%}
ins_pipe(ialu_reg);
%}
// Note: Long.bitCount(long) returns an int.
! instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountL (LoadL mem)));
effect(KILL cr, TEMP tmp, TEMP dst);
format %{ "POPCNT $dst, $mem\n\t"
--- 5816,5826 ----
%}
ins_pipe(ialu_reg);
%}
// Note: Long.bitCount(long) returns an int.
! instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
predicate(UsePopCountInstruction);
match(Set dst (PopCountL (LoadL mem)));
effect(KILL cr, TEMP tmp, TEMP dst);
format %{ "POPCNT $dst, $mem\n\t"
*** 5871,5881 ****
%}
ins_pipe(ialu_reg_mem);
%}
// Load Short (16bit signed)
! instruct loadS(eRegI dst, memory mem) %{
match(Set dst (LoadS mem));
ins_cost(125);
format %{ "MOVSX $dst,$mem\t# short" %}
--- 5920,5930 ----
%}
ins_pipe(ialu_reg_mem);
%}
// Load Short (16bit signed)
! instruct loadS(rRegI dst, memory mem) %{
match(Set dst (LoadS mem));
ins_cost(125);
format %{ "MOVSX $dst,$mem\t# short" %}
*** 5885,5895 ****
ins_pipe(ialu_reg_mem);
%}
// Load Short (16 bit signed) to Byte (8 bit signed)
! instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# short -> byte" %}
ins_encode %{
--- 5934,5944 ----
ins_pipe(ialu_reg_mem);
%}
// Load Short (16 bit signed) to Byte (8 bit signed)
! instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# short -> byte" %}
ins_encode %{
*** 5916,5926 ****
ins_pipe(ialu_reg_mem);
%}
// Load Unsigned Short/Char (16bit unsigned)
! instruct loadUS(eRegI dst, memory mem) %{
match(Set dst (LoadUS mem));
ins_cost(125);
format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
--- 5965,5975 ----
ins_pipe(ialu_reg_mem);
%}
// Load Unsigned Short/Char (16bit unsigned)
! instruct loadUS(rRegI dst, memory mem) %{
match(Set dst (LoadUS mem));
ins_cost(125);
format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
*** 5930,5940 ****
ins_pipe(ialu_reg_mem);
%}
// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
! instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
ins_encode %{
--- 5979,5989 ----
ins_pipe(ialu_reg_mem);
%}
// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
! instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
ins_encode %{
*** 5991,6001 ****
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer
! instruct loadI(eRegI dst, memory mem) %{
match(Set dst (LoadI mem));
ins_cost(125);
format %{ "MOV $dst,$mem\t# int" %}
--- 6040,6050 ----
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer
! instruct loadI(rRegI dst, memory mem) %{
match(Set dst (LoadI mem));
ins_cost(125);
format %{ "MOV $dst,$mem\t# int" %}
*** 6005,6015 ****
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Byte (8 bit signed)
! instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# int -> byte" %}
ins_encode %{
--- 6054,6064 ----
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Byte (8 bit signed)
! instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# int -> byte" %}
ins_encode %{
*** 6017,6027 ****
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
! instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
match(Set dst (AndI (LoadI mem) mask));
ins_cost(125);
format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
ins_encode %{
--- 6066,6076 ----
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
! instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
match(Set dst (AndI (LoadI mem) mask));
ins_cost(125);
format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
ins_encode %{
*** 6029,6039 ****
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Short (16 bit signed)
! instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# int -> short" %}
ins_encode %{
--- 6078,6088 ----
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Short (16 bit signed)
! instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
ins_cost(125);
format %{ "MOVSX $dst, $mem\t# int -> short" %}
ins_encode %{
*** 6041,6051 ****
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
! instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
match(Set dst (AndI (LoadI mem) mask));
ins_cost(125);
format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
ins_encode %{
--- 6090,6100 ----
%}
ins_pipe(ialu_reg_mem);
%}
// Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
! instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
match(Set dst (AndI (LoadI mem) mask));
ins_cost(125);
format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
ins_encode %{
*** 6202,6212 ****
%}
ins_pipe( pipe_slow );
%}
// Load Range
! instruct loadRange(eRegI dst, memory mem) %{
match(Set dst (LoadRange mem));
ins_cost(125);
format %{ "MOV $dst,$mem" %}
opcode(0x8B);
--- 6251,6261 ----
%}
ins_pipe( pipe_slow );
%}
// Load Range
! instruct loadRange(rRegI dst, memory mem) %{
match(Set dst (LoadRange mem));
ins_cost(125);
format %{ "MOV $dst,$mem" %}
opcode(0x8B);
*** 6299,6368 ****
ins_encode( OpcP, RMopc_Mem(0x00,mem),
Pop_Reg_FPR(dst) );
ins_pipe( fpu_reg_mem );
%}
- // Load Aligned Packed Byte to XMM register
- instruct loadA8B(regD dst, memory mem) %{
- predicate(UseSSE>=1);
- match(Set dst (Load8B mem));
- ins_cost(125);
- format %{ "MOVQ $dst,$mem\t! packed8B" %}
- ins_encode %{
- __ movq($dst$$XMMRegister, $mem$$Address);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Load Aligned Packed Short to XMM register
- instruct loadA4S(regD dst, memory mem) %{
- predicate(UseSSE>=1);
- match(Set dst (Load4S mem));
- ins_cost(125);
- format %{ "MOVQ $dst,$mem\t! packed4S" %}
- ins_encode %{
- __ movq($dst$$XMMRegister, $mem$$Address);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Load Aligned Packed Char to XMM register
- instruct loadA4C(regD dst, memory mem) %{
- predicate(UseSSE>=1);
- match(Set dst (Load4C mem));
- ins_cost(125);
- format %{ "MOVQ $dst,$mem\t! packed4C" %}
- ins_encode %{
- __ movq($dst$$XMMRegister, $mem$$Address);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Load Aligned Packed Integer to XMM register
- instruct load2IU(regD dst, memory mem) %{
- predicate(UseSSE>=1);
- match(Set dst (Load2I mem));
- ins_cost(125);
- format %{ "MOVQ $dst,$mem\t! packed2I" %}
- ins_encode %{
- __ movq($dst$$XMMRegister, $mem$$Address);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Load Aligned Packed Single to XMM
- instruct loadA2F(regD dst, memory mem) %{
- predicate(UseSSE>=1);
- match(Set dst (Load2F mem));
- ins_cost(145);
- format %{ "MOVQ $dst,$mem\t! packed2F" %}
- ins_encode %{
- __ movq($dst$$XMMRegister, $mem$$Address);
- %}
- ins_pipe( pipe_slow );
- %}
-
// Load Effective Address
instruct leaP8(eRegP dst, indOffset8 mem) %{
match(Set dst mem);
ins_cost(110);
--- 6348,6357 ----
*** 6411,6430 ****
ins_encode( OpcP, RegMem(dst,mem));
ins_pipe( ialu_reg_reg_fat );
%}
// Load Constant
! instruct loadConI(eRegI dst, immI src) %{
match(Set dst src);
format %{ "MOV $dst,$src" %}
ins_encode( LdImmI(dst, src) );
ins_pipe( ialu_reg_fat );
%}
// Load Constant zero
! instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
match(Set dst src);
effect(KILL cr);
ins_cost(50);
format %{ "XOR $dst,$dst" %}
--- 6400,6419 ----
ins_encode( OpcP, RegMem(dst,mem));
ins_pipe( ialu_reg_reg_fat );
%}
// Load Constant
! instruct loadConI(rRegI dst, immI src) %{
match(Set dst src);
format %{ "MOV $dst,$src" %}
ins_encode( LdImmI(dst, src) );
ins_pipe( ialu_reg_fat );
%}
// Load Constant zero
! instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
match(Set dst src);
effect(KILL cr);
ins_cost(50);
format %{ "XOR $dst,$dst" %}
*** 6588,6598 ****
%}
ins_pipe( pipe_slow );
%}
// Load Stack Slot
! instruct loadSSI(eRegI dst, stackSlotI src) %{
match(Set dst src);
ins_cost(125);
format %{ "MOV $dst,$src" %}
opcode(0x8B);
--- 6577,6587 ----
%}
ins_pipe( pipe_slow );
%}
// Load Stack Slot
! instruct loadSSI(rRegI dst, stackSlotI src) %{
match(Set dst src);
ins_cost(125);
format %{ "MOV $dst,$src" %}
opcode(0x8B);
*** 6815,6825 ****
ins_encode( OpcP, RegMem( src, mem ) );
ins_pipe( ialu_mem_reg );
%}
// Store Char/Short
! instruct storeC(memory mem, eRegI src) %{
match(Set mem (StoreC mem src));
ins_cost(125);
format %{ "MOV16 $mem,$src" %}
opcode(0x89, 0x66);
--- 6804,6814 ----
ins_encode( OpcP, RegMem( src, mem ) );
ins_pipe( ialu_mem_reg );
%}
// Store Char/Short
! instruct storeC(memory mem, rRegI src) %{
match(Set mem (StoreC mem src));
ins_cost(125);
format %{ "MOV16 $mem,$src" %}
opcode(0x89, 0x66);
*** 6826,6836 ****
ins_encode( OpcS, OpcP, RegMem( src, mem ) );
ins_pipe( ialu_mem_reg );
%}
// Store Integer
! instruct storeI(memory mem, eRegI src) %{
match(Set mem (StoreI mem src));
ins_cost(125);
format %{ "MOV $mem,$src" %}
opcode(0x89);
--- 6815,6825 ----
ins_encode( OpcS, OpcP, RegMem( src, mem ) );
ins_pipe( ialu_mem_reg );
%}
// Store Integer
! instruct storeI(memory mem, rRegI src) %{
match(Set mem (StoreI mem src));
ins_cost(125);
format %{ "MOV $mem,$src" %}
opcode(0x89);
*** 6970,7015 ****
opcode(0xC6); /* C6 /0 */
ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
ins_pipe( ialu_mem_imm );
%}
- // Store Aligned Packed Byte XMM register to memory
- instruct storeA8B(memory mem, regD src) %{
- predicate(UseSSE>=1);
- match(Set mem (Store8B mem src));
- ins_cost(145);
- format %{ "MOVQ $mem,$src\t! packed8B" %}
- ins_encode %{
- __ movq($mem$$Address, $src$$XMMRegister);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Store Aligned Packed Char/Short XMM register to memory
- instruct storeA4C(memory mem, regD src) %{
- predicate(UseSSE>=1);
- match(Set mem (Store4C mem src));
- ins_cost(145);
- format %{ "MOVQ $mem,$src\t! packed4C" %}
- ins_encode %{
- __ movq($mem$$Address, $src$$XMMRegister);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Store Aligned Packed Integer XMM register to memory
- instruct storeA2I(memory mem, regD src) %{
- predicate(UseSSE>=1);
- match(Set mem (Store2I mem src));
- ins_cost(145);
- format %{ "MOVQ $mem,$src\t! packed2I" %}
- ins_encode %{
- __ movq($mem$$Address, $src$$XMMRegister);
- %}
- ins_pipe( pipe_slow );
- %}
-
// Store CMS card-mark Immediate
instruct storeImmCM(memory mem, immI8 src) %{
match(Set mem (StoreCM mem src));
ins_cost(150);
--- 6959,6968 ----
*** 7067,7088 ****
__ movflt($mem$$Address, $src$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
- // Store Aligned Packed Single Float XMM register to memory
- instruct storeA2F(memory mem, regD src) %{
- predicate(UseSSE>=1);
- match(Set mem (Store2F mem src));
- ins_cost(145);
- format %{ "MOVQ $mem,$src\t! packed2F" %}
- ins_encode %{
- __ movq($mem$$Address, $src$$XMMRegister);
- %}
- ins_pipe( pipe_slow );
- %}
-
// Store Float
instruct storeFPR( memory mem, regFPR1 src) %{
predicate(UseSSE==0);
match(Set mem (StoreF mem src));
--- 7020,7029 ----
*** 7140,7150 ****
ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
ins_pipe( ialu_mem_imm );
%}
// Store Integer to stack slot
! instruct storeSSI(stackSlotI dst, eRegI src) %{
match(Set dst src);
ins_cost(100);
format %{ "MOV $dst,$src" %}
opcode(0x89);
--- 7081,7091 ----
ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
ins_pipe( ialu_mem_imm );
%}
// Store Integer to stack slot
! instruct storeSSI(stackSlotI dst, rRegI src) %{
match(Set dst src);
ins_cost(100);
format %{ "MOV $dst,$src" %}
opcode(0x89);
*** 7265,7285 ****
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}
! instruct castP2X(eRegI dst, eRegP src ) %{
match(Set dst (CastP2X src));
ins_cost(50);
format %{ "MOV $dst, $src\t# CastP2X" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
//----------Conditional Move---------------------------------------------------
// Conditional move
! instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
predicate(!VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "J$cop,us skip\t# signed cmove\n\t"
"MOV $dst,$src\n"
--- 7206,7226 ----
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}
! instruct castP2X(rRegI dst, eRegP src ) %{
match(Set dst (CastP2X src));
ins_cost(50);
format %{ "MOV $dst, $src\t# CastP2X" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
//----------Conditional Move---------------------------------------------------
// Conditional move
! instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
predicate(!VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "J$cop,us skip\t# signed cmove\n\t"
"MOV $dst,$src\n"
*** 7292,7302 ****
__ bind(Lskip);
%}
ins_pipe( pipe_cmov_reg );
%}
! instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
predicate(!VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "J$cop,us skip\t# unsigned cmove\n\t"
"MOV $dst,$src\n"
--- 7233,7243 ----
__ bind(Lskip);
%}
ins_pipe( pipe_cmov_reg );
%}
! instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
predicate(!VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "J$cop,us skip\t# unsigned cmove\n\t"
"MOV $dst,$src\n"
*** 7309,7349 ****
__ bind(Lskip);
%}
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
expand %{
cmovI_regU(cop, cr, dst, src);
%}
%}
// Conditional move
! instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
--- 7250,7290 ----
__ bind(Lskip);
%}
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
ins_cost(200);
expand %{
cmovI_regU(cop, cr, dst, src);
%}
%}
// Conditional move
! instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
*** 7350,7370 ****
ins_encode( enc_cmov(cop), RegMem( dst, src ) );
ins_pipe( pipe_cmov_mem );
%}
// Conditional move
! instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegMem( dst, src ) );
ins_pipe( pipe_cmov_mem );
%}
! instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
expand %{
cmovI_memU(cop, cr, dst, src);
--- 7291,7311 ----
ins_encode( enc_cmov(cop), RegMem( dst, src ) );
ins_pipe( pipe_cmov_mem );
%}
// Conditional move
! instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cop $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cop), RegMem( dst, src ) );
ins_pipe( pipe_cmov_mem );
%}
! instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() );
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
ins_cost(250);
expand %{
cmovI_memU(cop, cr, dst, src);
*** 7614,7624 ****
%}
//----------Arithmetic Instructions--------------------------------------------
//----------Addition Instructions----------------------------------------------
// Integer Addition Instructions
! instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (AddI dst src));
effect(KILL cr);
size(2);
format %{ "ADD $dst,$src" %}
--- 7555,7565 ----
%}
//----------Arithmetic Instructions--------------------------------------------
//----------Addition Instructions----------------------------------------------
// Integer Addition Instructions
! instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (AddI dst src));
effect(KILL cr);
size(2);
format %{ "ADD $dst,$src" %}
*** 7625,7645 ****
opcode(0x03);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (AddI dst src));
effect(KILL cr);
format %{ "ADD $dst,$src" %}
opcode(0x81, 0x00); /* /0 id */
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
size(1);
--- 7566,7586 ----
opcode(0x03);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (AddI dst src));
effect(KILL cr);
format %{ "ADD $dst,$src" %}
opcode(0x81, 0x00); /* /0 id */
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
size(1);
*** 7647,7657 ****
opcode(0x40); /* */
ins_encode( Opc_plus( primary, dst ) );
ins_pipe( ialu_reg );
%}
! instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
match(Set dst (AddI src0 src1));
ins_cost(110);
format %{ "LEA $dst,[$src0 + $src1]" %}
opcode(0x8D); /* 0x8D /r */
--- 7588,7598 ----
opcode(0x40); /* */
ins_encode( Opc_plus( primary, dst ) );
ins_pipe( ialu_reg );
%}
! instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
match(Set dst (AddI src0 src1));
ins_cost(110);
format %{ "LEA $dst,[$src0 + $src1]" %}
opcode(0x8D); /* 0x8D /r */
*** 7667,7677 ****
opcode(0x8D); /* 0x8D /r */
ins_encode( OpcP, RegLea( dst, src0, src1 ) );
ins_pipe( ialu_reg_reg );
%}
! instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
size(1);
--- 7608,7618 ----
opcode(0x8D); /* 0x8D /r */
ins_encode( OpcP, RegLea( dst, src0, src1 ) );
ins_pipe( ialu_reg_reg );
%}
! instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
size(1);
*** 7679,7689 ****
opcode(0x48); /* */
ins_encode( Opc_plus( primary, dst ) );
ins_pipe( ialu_reg );
%}
! instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
match(Set dst (AddP dst src));
effect(KILL cr);
size(2);
format %{ "ADD $dst,$src" %}
--- 7620,7630 ----
opcode(0x48); /* */
ins_encode( Opc_plus( primary, dst ) );
ins_pipe( ialu_reg );
%}
! instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
match(Set dst (AddP dst src));
effect(KILL cr);
size(2);
format %{ "ADD $dst,$src" %}
*** 7701,7711 ****
// ins_encode( RegImm( dst, src) );
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AddI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "ADD $dst,$src" %}
--- 7642,7652 ----
// ins_encode( RegImm( dst, src) );
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AddI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "ADD $dst,$src" %}
*** 7712,7722 ****
opcode(0x03);
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
! instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (AddI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "ADD $dst,$src" %}
--- 7653,7663 ----
opcode(0x03);
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
! instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (AddI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "ADD $dst,$src" %}
*** 7774,7784 ****
format %{ "#castPP of $dst" %}
ins_encode( /*empty encoding*/ );
ins_pipe( empty );
%}
! instruct castII( eRegI dst ) %{
match(Set dst (CastII dst));
format %{ "#castII of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe( empty );
--- 7715,7725 ----
format %{ "#castPP of $dst" %}
ins_encode( /*empty encoding*/ );
ins_pipe( empty );
%}
! instruct castII( rRegI dst ) %{
match(Set dst (CastII dst));
format %{ "#castII of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe( empty );
*** 7852,7862 ****
ins_pipe( pipe_cmpxchg );
%}
// Conditional-store of an int value.
// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
! instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
match(Set cr (StoreIConditional mem (Binary oldval newval)));
effect(KILL oldval);
format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
ins_pipe( pipe_cmpxchg );
--- 7793,7803 ----
ins_pipe( pipe_cmpxchg );
%}
// Conditional-store of an int value.
// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
! instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
match(Set cr (StoreIConditional mem (Binary oldval newval)));
effect(KILL oldval);
format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
ins_pipe( pipe_cmpxchg );
*** 7885,7895 ****
ins_pipe( pipe_cmpxchg );
%}
// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
! instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
--- 7826,7836 ----
ins_pipe( pipe_cmpxchg );
%}
// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
! instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
*** 7898,7908 ****
ins_encode( enc_cmpxchg8(mem_ptr),
enc_flags_ne_to_boolean(res) );
ins_pipe( pipe_cmpxchg );
%}
! instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
--- 7839,7849 ----
ins_encode( enc_cmpxchg8(mem_ptr),
enc_flags_ne_to_boolean(res) );
ins_pipe( pipe_cmpxchg );
%}
! instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
*** 7910,7920 ****
"fail:" %}
ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
ins_pipe( pipe_cmpxchg );
%}
! instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
--- 7851,7861 ----
"fail:" %}
ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
ins_pipe( pipe_cmpxchg );
%}
! instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
effect(KILL cr, KILL oldval);
format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
"MOV $res,0\n\t"
"JNE,s fail\n\t"
*** 7924,7934 ****
ins_pipe( pipe_cmpxchg );
%}
//----------Subtraction Instructions-------------------------------------------
// Integer Subtraction Instructions
! instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (SubI dst src));
effect(KILL cr);
size(2);
format %{ "SUB $dst,$src" %}
--- 7865,7875 ----
ins_pipe( pipe_cmpxchg );
%}
//----------Subtraction Instructions-------------------------------------------
// Integer Subtraction Instructions
! instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (SubI dst src));
effect(KILL cr);
size(2);
format %{ "SUB $dst,$src" %}
*** 7935,7945 ****
opcode(0x2B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (SubI dst src));
effect(KILL cr);
format %{ "SUB $dst,$src" %}
opcode(0x81,0x05); /* Opcode 81 /5 */
--- 7876,7886 ----
opcode(0x2B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (SubI dst src));
effect(KILL cr);
format %{ "SUB $dst,$src" %}
opcode(0x81,0x05); /* Opcode 81 /5 */
*** 7946,7956 ****
// ins_encode( RegImm( dst, src) );
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (SubI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "SUB $dst,$src" %}
--- 7887,7897 ----
// ins_encode( RegImm( dst, src) );
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
! instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (SubI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "SUB $dst,$src" %}
*** 7957,7967 ****
opcode(0x2B);
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
! instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (SubI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "SUB $dst,$src" %}
--- 7898,7908 ----
opcode(0x2B);
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
! instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (SubI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "SUB $dst,$src" %}
*** 7969,7979 ****
ins_encode( OpcP, RegMem( src, dst ) );
ins_pipe( ialu_mem_reg );
%}
// Subtract from a pointer
! instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
match(Set dst (AddP dst (SubI zero src)));
effect(KILL cr);
size(2);
format %{ "SUB $dst,$src" %}
--- 7910,7920 ----
ins_encode( OpcP, RegMem( src, dst ) );
ins_pipe( ialu_mem_reg );
%}
// Subtract from a pointer
! instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
match(Set dst (AddP dst (SubI zero src)));
effect(KILL cr);
size(2);
format %{ "SUB $dst,$src" %}
*** 7980,7990 ****
opcode(0x2B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
match(Set dst (SubI zero dst));
effect(KILL cr);
size(2);
format %{ "NEG $dst" %}
--- 7921,7931 ----
opcode(0x2B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
match(Set dst (SubI zero dst));
effect(KILL cr);
size(2);
format %{ "NEG $dst" %}
*** 7995,8005 ****
//----------Multiplication/Division Instructions-------------------------------
// Integer Multiplication Instructions
// Multiply Register
! instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (MulI dst src));
effect(KILL cr);
size(3);
ins_cost(300);
--- 7936,7946 ----
//----------Multiplication/Division Instructions-------------------------------
// Integer Multiplication Instructions
// Multiply Register
! instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (MulI dst src));
effect(KILL cr);
size(3);
ins_cost(300);
*** 8008,8018 ****
ins_encode( OpcS, OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg_alu0 );
%}
// Multiply 32-bit Immediate
! instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
match(Set dst (MulI src imm));
effect(KILL cr);
ins_cost(300);
format %{ "IMUL $dst,$src,$imm" %}
--- 7949,7959 ----
ins_encode( OpcS, OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg_alu0 );
%}
// Multiply 32-bit Immediate
! instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
match(Set dst (MulI src imm));
effect(KILL cr);
ins_cost(300);
format %{ "IMUL $dst,$src,$imm" %}
*** 8064,8074 ****
ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
ins_pipe( pipe_slow );
%}
// Multiply Memory 32-bit Immediate
! instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
match(Set dst (MulI (LoadI src) imm));
effect(KILL cr);
ins_cost(300);
format %{ "IMUL $dst,$src,$imm" %}
--- 8005,8015 ----
ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
ins_pipe( pipe_slow );
%}
// Multiply Memory 32-bit Immediate
! instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
match(Set dst (MulI (LoadI src) imm));
effect(KILL cr);
ins_cost(300);
format %{ "IMUL $dst,$src,$imm" %}
*** 8076,8086 ****
ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
ins_pipe( ialu_reg_mem_alu0 );
%}
// Multiply Memory
! instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (MulI dst (LoadI src)));
effect(KILL cr);
ins_cost(350);
format %{ "IMUL $dst,$src" %}
--- 8017,8027 ----
ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
ins_pipe( ialu_reg_mem_alu0 );
%}
// Multiply Memory
! instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (MulI dst (LoadI src)));
effect(KILL cr);
ins_cost(350);
format %{ "IMUL $dst,$src" %}
*** 8113,8123 ****
ins_encode( long_uint_multiply(dst, src1) );
ins_pipe( ialu_reg_reg_alu0 );
%}
// Multiply Register Long
! instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(4*100+3*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
--- 8054,8064 ----
ins_encode( long_uint_multiply(dst, src1) );
ins_pipe( ialu_reg_reg_alu0 );
%}
// Multiply Register Long
! instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(4*100+3*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
*** 8131,8141 ****
ins_encode( long_multiply( dst, src, tmp ) );
ins_pipe( pipe_slow );
%}
// Multiply Register Long where the left operand's high 32 bits are zero
! instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
predicate(is_operand_hi32_zero(n->in(1)));
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
--- 8072,8082 ----
ins_encode( long_multiply( dst, src, tmp ) );
ins_pipe( pipe_slow );
%}
// Multiply Register Long where the left operand's high 32 bits are zero
! instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
predicate(is_operand_hi32_zero(n->in(1)));
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
*** 8152,8162 ****
%}
ins_pipe( pipe_slow );
%}
// Multiply Register Long where the right operand's high 32 bits are zero
! instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
predicate(is_operand_hi32_zero(n->in(2)));
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
--- 8093,8103 ----
%}
ins_pipe( pipe_slow );
%}
// Multiply Register Long where the right operand's high 32 bits are zero
! instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
predicate(is_operand_hi32_zero(n->in(2)));
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
// Basic idea: lo(result) = lo(x_lo * y_lo)
*** 8188,8198 ****
%}
ins_pipe( pipe_slow );
%}
// Multiply Register Long by small constant
! instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
size(12);
// Basic idea: lo(result) = lo(src * EAX)
--- 8129,8139 ----
%}
ins_pipe( pipe_slow );
%}
// Multiply Register Long by small constant
! instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
match(Set dst (MulL dst src));
effect(KILL cr, TEMP tmp);
ins_cost(2*100+2*400);
size(12);
// Basic idea: lo(result) = lo(src * EAX)
*** 8286,8296 ****
ins_encode( long_mod(src1,src2) );
ins_pipe( pipe_slow );
%}
// Divide Register Long (no special case since divisor != -1)
! instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
match(Set dst (DivL dst imm));
effect( TEMP tmp, TEMP tmp2, KILL cr );
ins_cost(1000);
format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
"XOR $tmp2,$tmp2\n\t"
--- 8227,8237 ----
ins_encode( long_mod(src1,src2) );
ins_pipe( pipe_slow );
%}
// Divide Register Long (no special case since divisor != -1)
! instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
match(Set dst (DivL dst imm));
effect( TEMP tmp, TEMP tmp2, KILL cr );
ins_cost(1000);
format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
"XOR $tmp2,$tmp2\n\t"
*** 8357,8367 ****
%}
ins_pipe( pipe_slow );
%}
// Remainder Register Long (remainder fit into 32 bits)
! instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
match(Set dst (ModL dst imm));
effect( TEMP tmp, TEMP tmp2, KILL cr );
ins_cost(1000);
format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
"CMP $tmp,EDX\n\t"
--- 8298,8308 ----
%}
ins_pipe( pipe_slow );
%}
// Remainder Register Long (remainder fit into 32 bits)
! instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
match(Set dst (ModL dst imm));
effect( TEMP tmp, TEMP tmp2, KILL cr );
ins_cost(1000);
format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
"CMP $tmp,EDX\n\t"
*** 8425,8435 ****
ins_pipe( pipe_slow );
%}
// Integer Shift Instructions
// Shift Left by one
! instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHL $dst,$shift" %}
--- 8366,8376 ----
ins_pipe( pipe_slow );
%}
// Integer Shift Instructions
// Shift Left by one
! instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHL $dst,$shift" %}
*** 8437,8447 ****
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
// Shift Left by 8-bit immediate
! instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SHL $dst,$shift" %}
--- 8378,8388 ----
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
// Shift Left by 8-bit immediate
! instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SHL $dst,$shift" %}
*** 8449,8459 ****
ins_encode( RegOpcImm( dst, shift) );
ins_pipe( ialu_reg );
%}
// Shift Left by variable
! instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHL $dst,$shift" %}
--- 8390,8400 ----
ins_encode( RegOpcImm( dst, shift) );
ins_pipe( ialu_reg );
%}
// Shift Left by variable
! instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHL $dst,$shift" %}
*** 8461,8471 ****
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Arithmetic shift right by one
! instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SAR $dst,$shift" %}
--- 8402,8412 ----
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Arithmetic shift right by one
! instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SAR $dst,$shift" %}
*** 8483,8493 ****
ins_encode( OpcP, RMopc_Mem(secondary,dst) );
ins_pipe( ialu_mem_imm );
%}
// Arithmetic Shift Right by 8-bit immediate
! instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SAR $dst,$shift" %}
--- 8424,8434 ----
ins_encode( OpcP, RMopc_Mem(secondary,dst) );
ins_pipe( ialu_mem_imm );
%}
// Arithmetic Shift Right by 8-bit immediate
! instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SAR $dst,$shift" %}
*** 8506,8516 ****
ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
ins_pipe( ialu_mem_imm );
%}
// Arithmetic Shift Right by variable
! instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SAR $dst,$shift" %}
--- 8447,8457 ----
ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
ins_pipe( ialu_mem_imm );
%}
// Arithmetic Shift Right by variable
! instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SAR $dst,$shift" %}
*** 8518,8528 ****
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Logical shift right by one
! instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHR $dst,$shift" %}
--- 8459,8469 ----
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Logical shift right by one
! instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHR $dst,$shift" %}
*** 8530,8540 ****
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
// Logical Shift Right by 8-bit immediate
! instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SHR $dst,$shift" %}
--- 8471,8481 ----
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
// Logical Shift Right by 8-bit immediate
! instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(3);
format %{ "SHR $dst,$shift" %}
*** 8544,8554 ****
%}
// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
// This idiom is used by the compiler for the i2b bytecode.
! instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
size(3);
format %{ "MOVSX $dst,$src :8" %}
ins_encode %{
--- 8485,8495 ----
%}
// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
// This idiom is used by the compiler for the i2b bytecode.
! instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
size(3);
format %{ "MOVSX $dst,$src :8" %}
ins_encode %{
*** 8557,8567 ****
ins_pipe(ialu_reg_reg);
%}
// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
// This idiom is used by the compiler the i2s bytecode.
! instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
size(3);
format %{ "MOVSX $dst,$src :16" %}
ins_encode %{
--- 8498,8508 ----
ins_pipe(ialu_reg_reg);
%}
// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
// This idiom is used by the compiler the i2s bytecode.
! instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
size(3);
format %{ "MOVSX $dst,$src :16" %}
ins_encode %{
*** 8570,8580 ****
ins_pipe(ialu_reg_reg);
%}
// Logical Shift Right by variable
! instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHR $dst,$shift" %}
--- 8511,8521 ----
ins_pipe(ialu_reg_reg);
%}
// Logical Shift Right by variable
! instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHR $dst,$shift" %}
*** 8586,8596 ****
//----------Logical Instructions-----------------------------------------------
//----------Integer Logical Instructions---------------------------------------
// And Instructions
// And Register with Register
! instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (AndI dst src));
effect(KILL cr);
size(2);
format %{ "AND $dst,$src" %}
--- 8527,8537 ----
//----------Logical Instructions-----------------------------------------------
//----------Integer Logical Instructions---------------------------------------
// And Instructions
// And Register with Register
! instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (AndI dst src));
effect(KILL cr);
size(2);
format %{ "AND $dst,$src" %}
*** 8598,8608 ****
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
// And Register with Immediate
! instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (AndI dst src));
effect(KILL cr);
format %{ "AND $dst,$src" %}
opcode(0x81,0x04); /* Opcode 81 /4 */
--- 8539,8549 ----
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
// And Register with Immediate
! instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (AndI dst src));
effect(KILL cr);
format %{ "AND $dst,$src" %}
opcode(0x81,0x04); /* Opcode 81 /4 */
*** 8610,8620 ****
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// And Register with Memory
! instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AndI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "AND $dst,$src" %}
--- 8551,8561 ----
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// And Register with Memory
! instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (AndI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "AND $dst,$src" %}
*** 8622,8632 ****
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
// And Memory with Register
! instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (AndI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "AND $dst,$src" %}
--- 8563,8573 ----
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
// And Memory with Register
! instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (AndI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "AND $dst,$src" %}
*** 8648,8658 ****
ins_pipe( ialu_mem_imm );
%}
// Or Instructions
// Or Register with Register
! instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (OrI dst src));
effect(KILL cr);
size(2);
format %{ "OR $dst,$src" %}
--- 8589,8599 ----
ins_pipe( ialu_mem_imm );
%}
// Or Instructions
// Or Register with Register
! instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (OrI dst src));
effect(KILL cr);
size(2);
format %{ "OR $dst,$src" %}
*** 8659,8669 ****
opcode(0x0B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
match(Set dst (OrI dst (CastP2X src)));
effect(KILL cr);
size(2);
format %{ "OR $dst,$src" %}
--- 8600,8610 ----
opcode(0x0B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
match(Set dst (OrI dst (CastP2X src)));
effect(KILL cr);
size(2);
format %{ "OR $dst,$src" %}
*** 8672,8682 ****
ins_pipe( ialu_reg_reg );
%}
// Or Register with Immediate
! instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (OrI dst src));
effect(KILL cr);
format %{ "OR $dst,$src" %}
opcode(0x81,0x01); /* Opcode 81 /1 id */
--- 8613,8623 ----
ins_pipe( ialu_reg_reg );
%}
// Or Register with Immediate
! instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (OrI dst src));
effect(KILL cr);
format %{ "OR $dst,$src" %}
opcode(0x81,0x01); /* Opcode 81 /1 id */
*** 8684,8694 ****
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// Or Register with Memory
! instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (OrI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "OR $dst,$src" %}
--- 8625,8635 ----
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// Or Register with Memory
! instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (OrI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "OR $dst,$src" %}
*** 8696,8706 ****
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
// Or Memory with Register
! instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (OrI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "OR $dst,$src" %}
--- 8637,8647 ----
ins_encode( OpcP, RegMem( dst, src) );
ins_pipe( ialu_reg_mem );
%}
// Or Memory with Register
! instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (OrI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "OR $dst,$src" %}
*** 8722,8741 ****
ins_pipe( ialu_mem_imm );
%}
// ROL/ROR
// ROL expand
! instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROL $dst, $shift" %}
opcode(0xD1, 0x0); /* Opcode D1 /0 */
ins_encode( OpcP, RegOpc( dst ));
ins_pipe( ialu_reg );
%}
! instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROL $dst, $shift" %}
opcode(0xC1, 0x0); /*Opcode /C1 /0 */
ins_encode( RegOpcImm(dst, shift) );
--- 8663,8682 ----
ins_pipe( ialu_mem_imm );
%}
// ROL/ROR
// ROL expand
! instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROL $dst, $shift" %}
opcode(0xD1, 0x0); /* Opcode D1 /0 */
ins_encode( OpcP, RegOpc( dst ));
ins_pipe( ialu_reg );
%}
! instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROL $dst, $shift" %}
opcode(0xC1, 0x0); /*Opcode /C1 /0 */
ins_encode( RegOpcImm(dst, shift) );
*** 8751,8770 ****
ins_pipe( ialu_reg_reg );
%}
// end of ROL expand
// ROL 32bit by one once
! instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_eReg_imm1(dst, lshift, cr);
%}
%}
// ROL 32bit var by imm8 once
! instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_eReg_imm8(dst, lshift, cr);
--- 8692,8711 ----
ins_pipe( ialu_reg_reg );
%}
// end of ROL expand
// ROL 32bit by one once
! instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_eReg_imm1(dst, lshift, cr);
%}
%}
// ROL 32bit var by imm8 once
! instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_eReg_imm8(dst, lshift, cr);
*** 8788,8807 ****
rolI_eReg_CL(dst, shift, cr);
%}
%}
// ROR expand
! instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROR $dst, $shift" %}
opcode(0xD1,0x1); /* Opcode D1 /1 */
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
! instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
effect (USE_DEF dst, USE shift, KILL cr);
format %{ "ROR $dst, $shift" %}
opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
ins_encode( RegOpcImm(dst, shift) );
--- 8729,8748 ----
rolI_eReg_CL(dst, shift, cr);
%}
%}
// ROR expand
! instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROR $dst, $shift" %}
opcode(0xD1,0x1); /* Opcode D1 /1 */
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
! instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
effect (USE_DEF dst, USE shift, KILL cr);
format %{ "ROR $dst, $shift" %}
opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
ins_encode( RegOpcImm(dst, shift) );
*** 8817,8836 ****
ins_pipe( ialu_reg_reg );
%}
// end of ROR expand
// ROR right once
! instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_eReg_imm1(dst, rshift, cr);
%}
%}
// ROR 32bit by immI8 once
! instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_eReg_imm8(dst, rshift, cr);
--- 8758,8777 ----
ins_pipe( ialu_reg_reg );
%}
// end of ROR expand
// ROR right once
! instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_eReg_imm1(dst, rshift, cr);
%}
%}
// ROR 32bit by immI8 once
! instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_eReg_imm8(dst, rshift, cr);
*** 8855,8865 ****
%}
%}
// Xor Instructions
// Xor Register with Register
! instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
match(Set dst (XorI dst src));
effect(KILL cr);
size(2);
format %{ "XOR $dst,$src" %}
--- 8796,8806 ----
%}
%}
// Xor Instructions
// Xor Register with Register
! instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
match(Set dst (XorI dst src));
effect(KILL cr);
size(2);
format %{ "XOR $dst,$src" %}
*** 8867,8877 ****
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
// Xor Register with Immediate -1
! instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
match(Set dst (XorI dst imm));
size(2);
format %{ "NOT $dst" %}
ins_encode %{
--- 8808,8818 ----
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
// Xor Register with Immediate -1
! instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
match(Set dst (XorI dst imm));
size(2);
format %{ "NOT $dst" %}
ins_encode %{
*** 8879,8889 ****
%}
ins_pipe( ialu_reg );
%}
// Xor Register with Immediate
! instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (XorI dst src));
effect(KILL cr);
format %{ "XOR $dst,$src" %}
opcode(0x81,0x06); /* Opcode 81 /6 id */
--- 8820,8830 ----
%}
ins_pipe( ialu_reg );
%}
// Xor Register with Immediate
! instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
match(Set dst (XorI dst src));
effect(KILL cr);
format %{ "XOR $dst,$src" %}
opcode(0x81,0x06); /* Opcode 81 /6 id */
*** 8891,8901 ****
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// Xor Register with Memory
! instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (XorI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "XOR $dst,$src" %}
--- 8832,8842 ----
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
// Xor Register with Memory
! instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
match(Set dst (XorI dst (LoadI src)));
effect(KILL cr);
ins_cost(125);
format %{ "XOR $dst,$src" %}
*** 8903,8913 ****
ins_encode( OpcP, RegMem(dst, src) );
ins_pipe( ialu_reg_mem );
%}
// Xor Memory with Register
! instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (XorI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "XOR $dst,$src" %}
--- 8844,8854 ----
ins_encode( OpcP, RegMem(dst, src) );
ins_pipe( ialu_reg_mem );
%}
// Xor Memory with Register
! instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
match(Set dst (StoreI dst (XorI (LoadI dst) src)));
effect(KILL cr);
ins_cost(150);
format %{ "XOR $dst,$src" %}
*** 8928,8945 ****
ins_pipe( ialu_mem_imm );
%}
//----------Convert Int to Boolean---------------------------------------------
! instruct movI_nocopy(eRegI dst, eRegI src) %{
effect( DEF dst, USE src );
format %{ "MOV $dst,$src" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
effect( USE_DEF dst, USE src, KILL cr );
size(4);
format %{ "NEG $dst\n\t"
"ADC $dst,$src" %}
--- 8869,8886 ----
ins_pipe( ialu_mem_imm );
%}
//----------Convert Int to Boolean---------------------------------------------
! instruct movI_nocopy(rRegI dst, rRegI src) %{
effect( DEF dst, USE src );
format %{ "MOV $dst,$src" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
effect( USE_DEF dst, USE src, KILL cr );
size(4);
format %{ "NEG $dst\n\t"
"ADC $dst,$src" %}
*** 8946,8981 ****
ins_encode( neg_reg(dst),
OpcRegReg(0x13,dst,src) );
ins_pipe( ialu_reg_reg_long );
%}
! instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
match(Set dst (Conv2B src));
expand %{
movI_nocopy(dst,src);
ci2b(dst,src,cr);
%}
%}
! instruct movP_nocopy(eRegI dst, eRegP src) %{
effect( DEF dst, USE src );
format %{ "MOV $dst,$src" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
effect( USE_DEF dst, USE src, KILL cr );
format %{ "NEG $dst\n\t"
"ADC $dst,$src" %}
ins_encode( neg_reg(dst),
OpcRegReg(0x13,dst,src) );
ins_pipe( ialu_reg_reg_long );
%}
! instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
match(Set dst (Conv2B src));
expand %{
movP_nocopy(dst,src);
cp2b(dst,src,cr);
--- 8887,8922 ----
ins_encode( neg_reg(dst),
OpcRegReg(0x13,dst,src) );
ins_pipe( ialu_reg_reg_long );
%}
! instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
match(Set dst (Conv2B src));
expand %{
movI_nocopy(dst,src);
ci2b(dst,src,cr);
%}
%}
! instruct movP_nocopy(rRegI dst, eRegP src) %{
effect( DEF dst, USE src );
format %{ "MOV $dst,$src" %}
ins_encode( enc_Copy( dst, src) );
ins_pipe( ialu_reg_reg );
%}
! instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
effect( USE_DEF dst, USE src, KILL cr );
format %{ "NEG $dst\n\t"
"ADC $dst,$src" %}
ins_encode( neg_reg(dst),
OpcRegReg(0x13,dst,src) );
ins_pipe( ialu_reg_reg_long );
%}
! instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
match(Set dst (Conv2B src));
expand %{
movP_nocopy(dst,src);
cp2b(dst,src,cr);
*** 8996,9006 ****
OpcRegReg(0x3B,p,q),
setLT_reg(dst), neg_reg(dst) );
ins_pipe( pipe_slow );
%}
! instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
match(Set dst (CmpLTMask dst zero));
effect( DEF dst, KILL cr );
ins_cost(100);
format %{ "SAR $dst,31" %}
--- 8937,8947 ----
OpcRegReg(0x3B,p,q),
setLT_reg(dst), neg_reg(dst) );
ins_pipe( pipe_slow );
%}
! instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
match(Set dst (CmpLTMask dst zero));
effect( DEF dst, KILL cr );
ins_cost(100);
format %{ "SAR $dst,31" %}
*** 9468,9478 ****
fpu_flags);
ins_pipe( pipe_slow );
%}
// Compare vs zero into -1,0,1
! instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE<=1);
match(Set dst (CmpD3 src1 zero));
effect(KILL cr, KILL rax);
ins_cost(280);
format %{ "FTSTD $dst,$src1" %}
--- 9409,9419 ----
fpu_flags);
ins_pipe( pipe_slow );
%}
// Compare vs zero into -1,0,1
! instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE<=1);
match(Set dst (CmpD3 src1 zero));
effect(KILL cr, KILL rax);
ins_cost(280);
format %{ "FTSTD $dst,$src1" %}
*** 9482,9492 ****
CmpF_Result(dst));
ins_pipe( pipe_slow );
%}
// Compare into -1,0,1
! instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE<=1);
match(Set dst (CmpD3 src1 src2));
effect(KILL cr, KILL rax);
ins_cost(300);
format %{ "FCMPD $dst,$src1,$src2" %}
--- 9423,9433 ----
CmpF_Result(dst));
ins_pipe( pipe_slow );
%}
// Compare into -1,0,1
! instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE<=1);
match(Set dst (CmpD3 src1 src2));
effect(KILL cr, KILL rax);
ins_cost(300);
format %{ "FCMPD $dst,$src1,$src2" %}
*** 10260,10270 ****
fpu_flags);
ins_pipe( pipe_slow );
%}
// Compare vs zero into -1,0,1
! instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE == 0);
match(Set dst (CmpF3 src1 zero));
effect(KILL cr, KILL rax);
ins_cost(280);
format %{ "FTSTF $dst,$src1" %}
--- 10201,10211 ----
fpu_flags);
ins_pipe( pipe_slow );
%}
// Compare vs zero into -1,0,1
! instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE == 0);
match(Set dst (CmpF3 src1 zero));
effect(KILL cr, KILL rax);
ins_cost(280);
format %{ "FTSTF $dst,$src1" %}
*** 10274,10284 ****
CmpF_Result(dst));
ins_pipe( pipe_slow );
%}
// Compare into -1,0,1
! instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE == 0);
match(Set dst (CmpF3 src1 src2));
effect(KILL cr, KILL rax);
ins_cost(300);
format %{ "FCMPF $dst,$src1,$src2" %}
--- 10215,10225 ----
CmpF_Result(dst));
ins_pipe( pipe_slow );
%}
// Compare into -1,0,1
! instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
predicate(UseSSE == 0);
match(Set dst (CmpF3 src1 src2));
effect(KILL cr, KILL rax);
ins_cost(300);
format %{ "FCMPF $dst,$src1,$src2" %}
*** 11194,11204 ****
opcode(0xDB, 0x0); /* DB /0 */
ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
ins_pipe( fpu_reg_mem );
%}
! instruct convI2D_reg(regD dst, eRegI src) %{
predicate( UseSSE>=2 && !UseXmmI2D );
match(Set dst (ConvI2D src));
format %{ "CVTSI2SD $dst,$src" %}
ins_encode %{
__ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
--- 11135,11145 ----
opcode(0xDB, 0x0); /* DB /0 */
ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
ins_pipe( fpu_reg_mem );
%}
! instruct convI2D_reg(regD dst, rRegI src) %{
predicate( UseSSE>=2 && !UseXmmI2D );
match(Set dst (ConvI2D src));
format %{ "CVTSI2SD $dst,$src" %}
ins_encode %{
__ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
*** 11214,11224 ****
__ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe( pipe_slow );
%}
! instruct convXI2D_reg(regD dst, eRegI src)
%{
predicate( UseSSE>=2 && UseXmmI2D );
match(Set dst (ConvI2D src));
format %{ "MOVD $dst,$src\n\t"
--- 11155,11165 ----
__ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe( pipe_slow );
%}
! instruct convXI2D_reg(regD dst, rRegI src)
%{
predicate( UseSSE>=2 && UseXmmI2D );
match(Set dst (ConvI2D src));
format %{ "MOVD $dst,$src\n\t"
*** 11302,11322 ****
Pop_Reg_FPR(dst));
ins_pipe( fpu_reg_mem );
%}
// Convert an int to a float in xmm; no rounding step needed.
! instruct convI2F_reg(regF dst, eRegI src) %{
predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
match(Set dst (ConvI2F src));
format %{ "CVTSI2SS $dst, $src" %}
ins_encode %{
__ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
%}
ins_pipe( pipe_slow );
%}
! instruct convXI2F_reg(regF dst, eRegI src)
%{
predicate( UseSSE>=2 && UseXmmI2F );
match(Set dst (ConvI2F src));
format %{ "MOVD $dst,$src\n\t"
--- 11243,11263 ----
Pop_Reg_FPR(dst));
ins_pipe( fpu_reg_mem );
%}
// Convert an int to a float in xmm; no rounding step needed.
! instruct convI2F_reg(regF dst, rRegI src) %{
predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
match(Set dst (ConvI2F src));
format %{ "CVTSI2SS $dst, $src" %}
ins_encode %{
__ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
%}
ins_pipe( pipe_slow );
%}
! instruct convXI2F_reg(regF dst, rRegI src)
%{
predicate( UseSSE>=2 && UseXmmI2F );
match(Set dst (ConvI2F src));
format %{ "MOVD $dst,$src\n\t"
*** 11326,11336 ****
__ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
%}
ins_pipe(pipe_slow); // XXX
%}
! instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
match(Set dst (ConvI2L src));
effect(KILL cr);
ins_cost(375);
format %{ "MOV $dst.lo,$src\n\t"
"MOV $dst.hi,$src\n\t"
--- 11267,11277 ----
__ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
%}
ins_pipe(pipe_slow); // XXX
%}
! instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
match(Set dst (ConvI2L src));
effect(KILL cr);
ins_cost(375);
format %{ "MOV $dst.lo,$src\n\t"
"MOV $dst.hi,$src\n\t"
*** 11338,11348 ****
ins_encode(convert_int_long(dst,src));
ins_pipe( ialu_reg_reg_long );
%}
// Zero-extend convert int to long
! instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
match(Set dst (AndL (ConvI2L src) mask) );
effect( KILL flags );
ins_cost(250);
format %{ "MOV $dst.lo,$src\n\t"
"XOR $dst.hi,$dst.hi" %}
--- 11279,11289 ----
ins_encode(convert_int_long(dst,src));
ins_pipe( ialu_reg_reg_long );
%}
// Zero-extend convert int to long
! instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
match(Set dst (AndL (ConvI2L src) mask) );
effect( KILL flags );
ins_cost(250);
format %{ "MOV $dst.lo,$src\n\t"
"XOR $dst.hi,$dst.hi" %}
*** 11418,11437 ****
opcode(0xDF, 0x5); /* DF /5 */
ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
ins_pipe( pipe_slow );
%}
! instruct convL2I_reg( eRegI dst, eRegL src ) %{
match(Set dst (ConvL2I src));
effect( DEF dst, USE src );
format %{ "MOV $dst,$src.lo" %}
ins_encode(enc_CopyL_Lo(dst,src));
ins_pipe( ialu_reg_reg );
%}
! instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
match(Set dst (MoveF2I src));
effect( DEF dst, USE src );
ins_cost(100);
format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
ins_encode %{
--- 11359,11378 ----
opcode(0xDF, 0x5); /* DF /5 */
ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
ins_pipe( pipe_slow );
%}
! instruct convL2I_reg( rRegI dst, eRegL src ) %{
match(Set dst (ConvL2I src));
effect( DEF dst, USE src );
format %{ "MOV $dst,$src.lo" %}
ins_encode(enc_CopyL_Lo(dst,src));
ins_pipe( ialu_reg_reg );
%}
! instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
match(Set dst (MoveF2I src));
effect( DEF dst, USE src );
ins_cost(100);
format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
ins_encode %{
*** 11462,11472 ****
__ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
! instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
predicate(UseSSE>=2);
match(Set dst (MoveF2I src));
effect( DEF dst, USE src );
ins_cost(85);
format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
--- 11403,11413 ----
__ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
! instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
predicate(UseSSE>=2);
match(Set dst (MoveF2I src));
effect( DEF dst, USE src );
ins_cost(85);
format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
*** 11474,11484 ****
__ movdl($dst$$Register, $src$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
! instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
match(Set dst (MoveI2F src));
effect( DEF dst, USE src );
ins_cost(100);
format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
--- 11415,11425 ----
__ movdl($dst$$Register, $src$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
! instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
match(Set dst (MoveI2F src));
effect( DEF dst, USE src );
ins_cost(100);
format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
*** 11514,11524 ****
__ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
%}
ins_pipe( pipe_slow );
%}
! instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
predicate(UseSSE>=2);
match(Set dst (MoveI2F src));
effect( DEF dst, USE src );
ins_cost(85);
--- 11455,11465 ----
__ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
%}
ins_pipe( pipe_slow );
%}
! instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
predicate(UseSSE>=2);
match(Set dst (MoveI2F src));
effect( DEF dst, USE src );
ins_cost(85);
*** 11648,11838 ****
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
%}
ins_pipe( pipe_slow );
%}
- // Replicate scalar to packed byte (1 byte) values in xmm
- instruct Repl8B_reg(regD dst, regD src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate8B src));
- format %{ "MOVDQA $dst,$src\n\t"
- "PUNPCKLBW $dst,$dst\n\t"
- "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
- ins_encode %{
- if ($dst$$reg != $src$$reg) {
- __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
- }
- __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
- __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
- %}
- ins_pipe( pipe_slow );
- %}
- // Replicate scalar to packed byte (1 byte) values in xmm
- instruct Repl8B_eRegI(regD dst, eRegI src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate8B src));
- format %{ "MOVD $dst,$src\n\t"
- "PUNPCKLBW $dst,$dst\n\t"
- "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
- ins_encode %{
- __ movdl($dst$$XMMRegister, $src$$Register);
- __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
- __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
- %}
- ins_pipe( pipe_slow );
- %}
-
- // Replicate scalar zero to packed byte (1 byte) values in xmm
- instruct Repl8B_immI0(regD dst, immI0 zero) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate8B zero));
- format %{ "PXOR $dst,$dst\t! replicate8B" %}
- ins_encode %{
- __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed shore (2 byte) values in xmm
- instruct Repl4S_reg(regD dst, regD src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4S src));
- format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
- ins_encode %{
- __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed shore (2 byte) values in xmm
- instruct Repl4S_eRegI(regD dst, eRegI src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4S src));
- format %{ "MOVD $dst,$src\n\t"
- "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
- ins_encode %{
- __ movdl($dst$$XMMRegister, $src$$Register);
- __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar zero to packed short (2 byte) values in xmm
- instruct Repl4S_immI0(regD dst, immI0 zero) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4S zero));
- format %{ "PXOR $dst,$dst\t! replicate4S" %}
- ins_encode %{
- __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed char (2 byte) values in xmm
- instruct Repl4C_reg(regD dst, regD src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4C src));
- format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
- ins_encode %{
- __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed char (2 byte) values in xmm
- instruct Repl4C_eRegI(regD dst, eRegI src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4C src));
- format %{ "MOVD $dst,$src\n\t"
- "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
- ins_encode %{
- __ movdl($dst$$XMMRegister, $src$$Register);
- __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar zero to packed char (2 byte) values in xmm
- instruct Repl4C_immI0(regD dst, immI0 zero) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate4C zero));
- format %{ "PXOR $dst,$dst\t! replicate4C" %}
- ins_encode %{
- __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed integer (4 byte) values in xmm
- instruct Repl2I_reg(regD dst, regD src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2I src));
- format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
- ins_encode %{
- __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed integer (4 byte) values in xmm
- instruct Repl2I_eRegI(regD dst, eRegI src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2I src));
- format %{ "MOVD $dst,$src\n\t"
- "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
- ins_encode %{
- __ movdl($dst$$XMMRegister, $src$$Register);
- __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar zero to packed integer (2 byte) values in xmm
- instruct Repl2I_immI0(regD dst, immI0 zero) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2I zero));
- format %{ "PXOR $dst,$dst\t! replicate2I" %}
- ins_encode %{
- __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed single precision floating point values in xmm
- instruct Repl2F_reg(regD dst, regD src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2F src));
- format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
- ins_encode %{
- __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed single precision floating point values in xmm
- instruct Repl2F_regF(regD dst, regF src) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2F src));
- format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
- ins_encode %{
- __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
- // Replicate scalar to packed single precision floating point values in xmm
- instruct Repl2F_immF0(regD dst, immF0 zero) %{
- predicate(UseSSE>=2);
- match(Set dst (Replicate2F zero));
- format %{ "PXOR $dst,$dst\t! replicate2F" %}
- ins_encode %{
- __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
- %}
- ins_pipe( fpu_reg_reg );
- %}
-
// =======================================================================
// fast clearing of an array
instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
match(Set dummy (ClearArray cnt base));
effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
--- 11589,11599 ----
*** 11936,11955 ****
ins_pipe( pipe_slow );
%}
//----------Control Flow Instructions------------------------------------------
// Signed compare Instructions
! instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
match(Set cr (CmpI op1 op2));
effect( DEF cr, USE op1, USE op2 );
format %{ "CMP $op1,$op2" %}
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegReg( op1, op2) );
ins_pipe( ialu_cr_reg_reg );
%}
! instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
match(Set cr (CmpI op1 op2));
effect( DEF cr, USE op1 );
format %{ "CMP $op1,$op2" %}
opcode(0x81,0x07); /* Opcode 81 /7 */
// ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
--- 11697,11716 ----
ins_pipe( pipe_slow );
%}
//----------Control Flow Instructions------------------------------------------
// Signed compare Instructions
! instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
match(Set cr (CmpI op1 op2));
effect( DEF cr, USE op1, USE op2 );
format %{ "CMP $op1,$op2" %}
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegReg( op1, op2) );
ins_pipe( ialu_cr_reg_reg );
%}
! instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
match(Set cr (CmpI op1 op2));
effect( DEF cr, USE op1 );
format %{ "CMP $op1,$op2" %}
opcode(0x81,0x07); /* Opcode 81 /7 */
// ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
*** 11956,11995 ****
ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
ins_pipe( ialu_cr_reg_imm );
%}
// Cisc-spilled version of cmpI_eReg
! instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
match(Set cr (CmpI op1 (LoadI op2)));
format %{ "CMP $op1,$op2" %}
ins_cost(500);
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegMem( op1, op2) );
ins_pipe( ialu_cr_reg_mem );
%}
! instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
match(Set cr (CmpI src zero));
effect( DEF cr, USE src );
format %{ "TEST $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
ins_pipe( ialu_cr_reg_imm );
%}
! instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
match(Set cr (CmpI (AndI src con) zero));
format %{ "TEST $src,$con" %}
opcode(0xF7,0x00);
ins_encode( OpcP, RegOpc(src), Con32(con) );
ins_pipe( ialu_cr_reg_imm );
%}
! instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
match(Set cr (CmpI (AndI src mem) zero));
format %{ "TEST $src,$mem" %}
opcode(0x85);
ins_encode( OpcP, RegMem( src, mem ) );
--- 11717,11756 ----
ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
ins_pipe( ialu_cr_reg_imm );
%}
// Cisc-spilled version of cmpI_eReg
! instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
match(Set cr (CmpI op1 (LoadI op2)));
format %{ "CMP $op1,$op2" %}
ins_cost(500);
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegMem( op1, op2) );
ins_pipe( ialu_cr_reg_mem );
%}
! instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
match(Set cr (CmpI src zero));
effect( DEF cr, USE src );
format %{ "TEST $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
ins_pipe( ialu_cr_reg_imm );
%}
! instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
match(Set cr (CmpI (AndI src con) zero));
format %{ "TEST $src,$con" %}
opcode(0xF7,0x00);
ins_encode( OpcP, RegOpc(src), Con32(con) );
ins_pipe( ialu_cr_reg_imm );
%}
! instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
match(Set cr (CmpI (AndI src mem) zero));
format %{ "TEST $src,$mem" %}
opcode(0x85);
ins_encode( OpcP, RegMem( src, mem ) );
*** 11996,12025 ****
ins_pipe( ialu_cr_reg_mem );
%}
// Unsigned compare Instructions; really, same as signed except they
// produce an eFlagsRegU instead of eFlagsReg.
! instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
match(Set cr (CmpU op1 op2));
format %{ "CMPu $op1,$op2" %}
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegReg( op1, op2) );
ins_pipe( ialu_cr_reg_reg );
%}
! instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
match(Set cr (CmpU op1 op2));
format %{ "CMPu $op1,$op2" %}
opcode(0x81,0x07); /* Opcode 81 /7 */
ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
ins_pipe( ialu_cr_reg_imm );
%}
// // Cisc-spilled version of cmpU_eReg
! instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
match(Set cr (CmpU op1 (LoadI op2)));
format %{ "CMPu $op1,$op2" %}
ins_cost(500);
opcode(0x3B); /* Opcode 3B /r */
--- 11757,11786 ----
ins_pipe( ialu_cr_reg_mem );
%}
// Unsigned compare Instructions; really, same as signed except they
// produce an eFlagsRegU instead of eFlagsReg.
! instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
match(Set cr (CmpU op1 op2));
format %{ "CMPu $op1,$op2" %}
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegReg( op1, op2) );
ins_pipe( ialu_cr_reg_reg );
%}
! instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
match(Set cr (CmpU op1 op2));
format %{ "CMPu $op1,$op2" %}
opcode(0x81,0x07); /* Opcode 81 /7 */
ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
ins_pipe( ialu_cr_reg_imm );
%}
// // Cisc-spilled version of cmpU_eReg
! instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
match(Set cr (CmpU op1 (LoadI op2)));
format %{ "CMPu $op1,$op2" %}
ins_cost(500);
opcode(0x3B); /* Opcode 3B /r */
*** 12026,12045 ****
ins_encode( OpcP, RegMem( op1, op2) );
ins_pipe( ialu_cr_reg_mem );
%}
// // Cisc-spilled version of cmpU_eReg
! //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
// match(Set cr (CmpU (LoadI op1) op2));
//
// format %{ "CMPu $op1,$op2" %}
// ins_cost(500);
// opcode(0x39); /* Opcode 39 /r */
// ins_encode( OpcP, RegMem( op1, op2) );
//%}
! instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
match(Set cr (CmpU src zero));
format %{ "TESTu $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
--- 11787,11806 ----
ins_encode( OpcP, RegMem( op1, op2) );
ins_pipe( ialu_cr_reg_mem );
%}
// // Cisc-spilled version of cmpU_eReg
! //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
// match(Set cr (CmpU (LoadI op1) op2));
//
// format %{ "CMPu $op1,$op2" %}
// ins_cost(500);
// opcode(0x39); /* Opcode 39 /r */
// ins_encode( OpcP, RegMem( op1, op2) );
//%}
! instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
match(Set cr (CmpU src zero));
format %{ "TESTu $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
*** 12131,12150 ****
// Min Instructions
////
// *** Min and Max using the conditional move are slower than the
// *** branch version on a Pentium III.
// // Conditional move for min
! //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
// effect( USE_DEF op2, USE op1, USE cr );
// format %{ "CMOVlt $op2,$op1\t! min" %}
// opcode(0x4C,0x0F);
// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
// ins_pipe( pipe_cmov_reg );
//%}
//
//// Min Register with Register (P6 version)
! //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
// predicate(VM_Version::supports_cmov() );
// match(Set op2 (MinI op1 op2));
// ins_cost(200);
// expand %{
// eFlagsReg cr;
--- 11892,11911 ----
// Min Instructions
////
// *** Min and Max using the conditional move are slower than the
// *** branch version on a Pentium III.
// // Conditional move for min
! //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
// effect( USE_DEF op2, USE op1, USE cr );
// format %{ "CMOVlt $op2,$op1\t! min" %}
// opcode(0x4C,0x0F);
// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
// ins_pipe( pipe_cmov_reg );
//%}
//
//// Min Register with Register (P6 version)
! //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
// predicate(VM_Version::supports_cmov() );
// match(Set op2 (MinI op1 op2));
// ins_cost(200);
// expand %{
// eFlagsReg cr;
*** 12152,12162 ****
// cmovI_reg_lt(op2,op1,cr);
// %}
//%}
// Min Register with Register (generic version)
! instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
match(Set dst (MinI dst src));
effect(KILL flags);
ins_cost(300);
format %{ "MIN $dst,$src" %}
--- 11913,11923 ----
// cmovI_reg_lt(op2,op1,cr);
// %}
//%}
// Min Register with Register (generic version)
! instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
match(Set dst (MinI dst src));
effect(KILL flags);
ins_cost(300);
format %{ "MIN $dst,$src" %}
*** 12167,12186 ****
// Max Register with Register
// *** Min and Max using the conditional move are slower than the
// *** branch version on a Pentium III.
// // Conditional move for max
! //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
// effect( USE_DEF op2, USE op1, USE cr );
// format %{ "CMOVgt $op2,$op1\t! max" %}
// opcode(0x4F,0x0F);
// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
// ins_pipe( pipe_cmov_reg );
//%}
//
// // Max Register with Register (P6 version)
! //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
// predicate(VM_Version::supports_cmov() );
// match(Set op2 (MaxI op1 op2));
// ins_cost(200);
// expand %{
// eFlagsReg cr;
--- 11928,11947 ----
// Max Register with Register
// *** Min and Max using the conditional move are slower than the
// *** branch version on a Pentium III.
// // Conditional move for max
! //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
// effect( USE_DEF op2, USE op1, USE cr );
// format %{ "CMOVgt $op2,$op1\t! max" %}
// opcode(0x4F,0x0F);
// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
// ins_pipe( pipe_cmov_reg );
//%}
//
// // Max Register with Register (P6 version)
! //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
// predicate(VM_Version::supports_cmov() );
// match(Set op2 (MaxI op1 op2));
// ins_cost(200);
// expand %{
// eFlagsReg cr;
*** 12188,12198 ****
// cmovI_reg_gt(op2,op1,cr);
// %}
//%}
// Max Register with Register (generic version)
! instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
match(Set dst (MaxI dst src));
effect(KILL flags);
ins_cost(300);
format %{ "MAX $dst,$src" %}
--- 11949,11959 ----
// cmovI_reg_gt(op2,op1,cr);
// %}
//%}
// Max Register with Register (generic version)
! instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
match(Set dst (MaxI dst src));
effect(KILL flags);
ins_cost(300);
format %{ "MAX $dst,$src" %}
*** 12249,12259 ****
%}
// ============================================================================
// Branch Instructions
// Jump Table
! instruct jumpXtnd(eRegI switch_val) %{
match(Jump switch_val);
ins_cost(350);
format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
ins_encode %{
// Jump to Address(table_base + switch_reg)
--- 12010,12020 ----
%}
// ============================================================================
// Branch Instructions
// Jump Table
! instruct jumpXtnd(rRegI switch_val) %{
match(Jump switch_val);
ins_cost(350);
format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
ins_encode %{
// Jump to Address(table_base + switch_reg)
*** 12667,12677 ****
%}
// Manifest a CmpL result in the normal flags. Only good for LT or GE
// compares. Can be used for LE or GT compares by reversing arguments.
// NOT GOOD FOR EQ/NE tests.
! instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
match( Set flags (CmpL src1 src2 ));
effect( TEMP tmp );
ins_cost(300);
format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
"MOV $tmp,$src1.hi\n\t"
--- 12428,12438 ----
%}
// Manifest a CmpL result in the normal flags. Only good for LT or GE
// compares. Can be used for LE or GT compares by reversing arguments.
// NOT GOOD FOR EQ/NE tests.
! instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
match( Set flags (CmpL src1 src2 ));
effect( TEMP tmp );
ins_cost(300);
format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
"MOV $tmp,$src1.hi\n\t"
*** 12713,12733 ****
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
--- 12474,12494 ----
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
*** 12784,12794 ****
%}
%}
//======
// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
! instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
match( Set flags (CmpL src zero ));
effect(TEMP tmp);
ins_cost(200);
format %{ "MOV $tmp,$src.lo\n\t"
"OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
--- 12545,12555 ----
%}
%}
//======
// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
! instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
match( Set flags (CmpL src zero ));
effect(TEMP tmp);
ins_cost(200);
format %{ "MOV $tmp,$src.lo\n\t"
"OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
*** 12841,12861 ****
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
--- 12602,12622 ----
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
*** 12913,12923 ****
%}
//======
// Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
// Same as cmpL_reg_flags_LEGT except must negate src
! instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
match( Set flags (CmpL src zero ));
effect( TEMP tmp );
ins_cost(300);
format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
"CMP $tmp,$src.lo\n\t"
--- 12674,12684 ----
%}
//======
// Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
// Same as cmpL_reg_flags_LEGT except must negate src
! instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
match( Set flags (CmpL src zero ));
effect( TEMP tmp );
ins_cost(300);
format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
"CMP $tmp,$src.lo\n\t"
*** 12927,12937 ****
%}
// Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
// Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
// requires a commuted test to get the same result.
! instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
match( Set flags (CmpL src1 src2 ));
effect( TEMP tmp );
ins_cost(300);
format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
"MOV $tmp,$src2.hi\n\t"
--- 12688,12698 ----
%}
// Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
// Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
// requires a commuted test to get the same result.
! instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
match( Set flags (CmpL src1 src2 ));
effect( TEMP tmp );
ins_cost(300);
format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
"MOV $tmp,$src2.hi\n\t"
*** 12974,12994 ****
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
--- 12735,12755 ----
ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
ins_pipe( pipe_cmov_reg_long );
%}
// Compare 2 longs and CMOVE ints.
! instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
ins_cost(200);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
ins_pipe( pipe_cmov_reg );
%}
! instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
ins_cost(250);
format %{ "CMOV$cmp $dst,$src" %}
opcode(0x0F,0x40);
*** 13313,13327 ****
// Only one replacement instruction
//
// ---------EXAMPLE----------------------------------------------------------
//
// // pertinent parts of existing instructions in architecture description
! // instruct movI(eRegI dst, eRegI src) %{
// match(Set dst (CopyI src));
// %}
//
! // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
// match(Set dst (AddI dst src));
// effect(KILL cr);
// %}
//
// // Change (inc mov) to lea
--- 13074,13088 ----
// Only one replacement instruction
//
// ---------EXAMPLE----------------------------------------------------------
//
// // pertinent parts of existing instructions in architecture description
! // instruct movI(rRegI dst, rRegI src) %{
// match(Set dst (CopyI src));
// %}
//
! // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
// match(Set dst (AddI dst src));
// effect(KILL cr);
// %}
//
// // Change (inc mov) to lea
*** 13362,13376 ****
// peepconstraint ( 0.dst == 1.dst );
// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
// %}
// // Change load of spilled value to only a spill
! // instruct storeI(memory mem, eRegI src) %{
// match(Set mem (StoreI mem src));
// %}
//
! // instruct loadI(eRegI dst, memory mem) %{
// match(Set dst (LoadI mem));
// %}
//
peephole %{
peepmatch ( loadI storeI );
--- 13123,13137 ----
// peepconstraint ( 0.dst == 1.dst );
// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
// %}
// // Change load of spilled value to only a spill
! // instruct storeI(memory mem, rRegI src) %{
// match(Set mem (StoreI mem src));
// %}
//
! // instruct loadI(rRegI dst, memory mem) %{
// match(Set dst (LoadI mem));
// %}
//
peephole %{
peepmatch ( loadI storeI );
src/cpu/x86/vm/x86_32.ad
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