1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && !(displace_is_oop) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( displace_is_oop ) {
389 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( displace_is_oop ) {
397 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && !(displace_is_oop) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( displace_is_oop ) {
427 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1251
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1253
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1257
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the methodOop in the code-stream.
1264 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1267
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1279
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1291
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1306
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1309
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1313
1314
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1324
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1328
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1341
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1350
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1363
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1369
1370
1371 const bool Matcher::match_rule_supported(int opcode) {
1372 if (!has_match_rule(opcode))
1373 return false;
1374
1375 switch (opcode) {
1376 case Op_PopCountI:
1377 case Op_PopCountL:
1378 if (!UsePopCountInstruction)
1379 return false;
1380 break;
1381 }
1382
1383 return true; // Per default match rules are supported.
1384 }
1385
1386 int Matcher::regnum_to_fpu_offset(int regnum) {
1387 return regnum - 32; // The FP registers are in the second chunk
1388 }
1389
1390 // This is UltraSparc specific, true just means we have fast l2f conversion
1391 const bool Matcher::convL2FSupported(void) {
1392 return true;
1393 }
1394
1395 // Is this branch offset short enough that a short branch can be used?
1396 //
1397 // NOTE: If the platform does not provide any short branch variants, then
1398 // this method should return false for offset 0.
1399 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1400 // The passed offset is relative to address of the branch.
1401 // On 86 a branch displacement is calculated relative to address
1402 // of a next instruction.
1403 offset -= br_size;
1404
1405 // the short version of jmpConUCF2 contains multiple branches,
1406 // making the reach slightly less
1407 if (rule == jmpConUCF2_rule)
1408 return (-126 <= offset && offset <= 125);
1409 return (-128 <= offset && offset <= 127);
1410 }
1411
1412 const bool Matcher::isSimpleConstant64(jlong value) {
1413 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1414 return false;
1415 }
1416
1417 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1418 const bool Matcher::init_array_count_is_in_bytes = false;
1419
1420 // Threshold size for cleararray.
1421 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1422
1423 // Needs 2 CMOV's for longs.
1424 const int Matcher::long_cmove_cost() { return 1; }
1425
1426 // No CMOVF/CMOVD with SSE/SSE2
1427 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1428
1429 // Should the Matcher clone shifts on addressing modes, expecting them to
1430 // be subsumed into complex addressing expressions or compute them into
1431 // registers? True for Intel but false for most RISCs
1432 const bool Matcher::clone_shift_expressions = true;
1433
1434 // Do we need to mask the count passed to shift instructions or does
1435 // the cpu only look at the lower 5/6 bits anyway?
1436 const bool Matcher::need_masked_shift_count = false;
1437
1438 bool Matcher::narrow_oop_use_complex_address() {
1439 ShouldNotCallThis();
1440 return true;
1441 }
1442
1443
1444 // Is it better to copy float constants, or load them directly from memory?
1445 // Intel can load a float constant from a direct address, requiring no
1446 // extra registers. Most RISCs will have to materialize an address into a
1447 // register first, so they would do better to copy the constant from stack.
1448 const bool Matcher::rematerialize_float_constants = true;
1449
1450 // If CPU can load and store mis-aligned doubles directly then no fixup is
1451 // needed. Else we split the double into 2 integer pieces and move it
1452 // piece-by-piece. Only happens when passing doubles into C code as the
1453 // Java calling convention forces doubles to be aligned.
1454 const bool Matcher::misaligned_doubles_ok = true;
1455
1456
1457 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1458 // Get the memory operand from the node
1459 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1460 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1461 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1462 uint opcnt = 1; // First operand
1463 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1464 while( idx >= skipped+num_edges ) {
1465 skipped += num_edges;
1466 opcnt++; // Bump operand count
1467 assert( opcnt < numopnds, "Accessing non-existent operand" );
1468 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1469 }
1470
1471 MachOper *memory = node->_opnds[opcnt];
1472 MachOper *new_memory = NULL;
1473 switch (memory->opcode()) {
1474 case DIRECT:
1475 case INDOFFSET32X:
1476 // No transformation necessary.
1477 return;
1478 case INDIRECT:
1479 new_memory = new (C) indirect_win95_safeOper( );
1480 break;
1481 case INDOFFSET8:
1482 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1483 break;
1484 case INDOFFSET32:
1485 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1486 break;
1487 case INDINDEXOFFSET:
1488 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1489 break;
1490 case INDINDEXSCALE:
1491 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1492 break;
1493 case INDINDEXSCALEOFFSET:
1494 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1495 break;
1496 case LOAD_LONG_INDIRECT:
1497 case LOAD_LONG_INDOFFSET32:
1498 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1499 return;
1500 default:
1501 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1502 return;
1503 }
1504 node->_opnds[opcnt] = new_memory;
1505 }
1506
1507 // Advertise here if the CPU requires explicit rounding operations
1508 // to implement the UseStrictFP mode.
1509 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1510
1511 // Are floats conerted to double when stored to stack during deoptimization?
1512 // On x32 it is stored with convertion only when FPU is used for floats.
1513 bool Matcher::float_in_double() { return (UseSSE == 0); }
1514
1515 // Do ints take an entire long register or just half?
1516 const bool Matcher::int_in_long = false;
1517
1518 // Return whether or not this register is ever used as an argument. This
1519 // function is used on startup to build the trampoline stubs in generateOptoStub.
1520 // Registers not mentioned will be killed by the VM call in the trampoline, and
1521 // arguments in those registers not be available to the callee.
1522 bool Matcher::can_be_java_arg( int reg ) {
1523 if( reg == ECX_num || reg == EDX_num ) return true;
1524 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1525 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1526 return false;
1527 }
1528
1529 bool Matcher::is_spillable_arg( int reg ) {
1530 return can_be_java_arg(reg);
1531 }
1532
1533 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1534 // Use hardware integer DIV instruction when
1535 // it is faster than a code which use multiply.
1536 // Only when constant divisor fits into 32 bit
1537 // (min_jint is excluded to get only correct
1538 // positive 32 bit values from negative).
1539 return VM_Version::has_fast_idiv() &&
1540 (divisor == (int)divisor && divisor != min_jint);
1541 }
1542
1543 // Register for DIVI projection of divmodI
1544 RegMask Matcher::divI_proj_mask() {
1545 return EAX_REG_mask();
1546 }
1547
1548 // Register for MODI projection of divmodI
1549 RegMask Matcher::modI_proj_mask() {
1550 return EDX_REG_mask();
1551 }
1552
1553 // Register for DIVL projection of divmodL
1554 RegMask Matcher::divL_proj_mask() {
1555 ShouldNotReachHere();
1556 return RegMask();
1557 }
1558
1559 // Register for MODL projection of divmodL
1560 RegMask Matcher::modL_proj_mask() {
1561 ShouldNotReachHere();
1562 return RegMask();
1563 }
1564
1565 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1566 return EBP_REG_mask();
1567 }
1568
1569 // Returns true if the high 32 bits of the value is known to be zero.
1570 bool is_operand_hi32_zero(Node* n) {
1571 int opc = n->Opcode();
1572 if (opc == Op_LoadUI2L) {
1573 return true;
1574 }
1575 if (opc == Op_AndL) {
1576 Node* o2 = n->in(2);
1577 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1578 return true;
1579 }
1580 }
1581 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1582 return true;
1583 }
1584 return false;
1585 }
1586
1587 %}
1588
1589 //----------ENCODING BLOCK-----------------------------------------------------
1590 // This block specifies the encoding classes used by the compiler to output
1591 // byte streams. Encoding classes generate functions which are called by
1592 // Machine Instruction Nodes in order to generate the bit encoding of the
1593 // instruction. Operands specify their base encoding interface with the
1594 // interface keyword. There are currently supported four interfaces,
1595 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1596 // operand to generate a function which returns its register number when
1597 // queried. CONST_INTER causes an operand to generate a function which
1598 // returns the value of the constant when queried. MEMORY_INTER causes an
1599 // operand to generate four functions which return the Base Register, the
1600 // Index Register, the Scale Value, and the Offset Value of the operand when
1601 // queried. COND_INTER causes an operand to generate six functions which
1602 // return the encoding code (ie - encoding bits for the instruction)
1603 // associated with each basic boolean condition for a conditional instruction.
1604 // Instructions specify two basic values for encoding. They use the
1605 // ins_encode keyword to specify their encoding class (which must be one of
1606 // the class names specified in the encoding block), and they use the
1607 // opcode keyword to specify, in order, their primary, secondary, and
1608 // tertiary opcode. Only the opcode sections which a particular instruction
1609 // needs for encoding need to be specified.
1610 encode %{
1611 // Build emit functions for each basic byte or larger field in the intel
1612 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1613 // code in the enc_class source block. Emit functions will live in the
1614 // main source block for now. In future, we can generalize this by
1615 // adding a syntax that specifies the sizes of fields in an order,
1616 // so that the adlc can build the emit functions automagically
1617
1618 // Emit primary opcode
1619 enc_class OpcP %{
1620 emit_opcode(cbuf, $primary);
1621 %}
1622
1623 // Emit secondary opcode
1624 enc_class OpcS %{
1625 emit_opcode(cbuf, $secondary);
1626 %}
1627
1628 // Emit opcode directly
1629 enc_class Opcode(immI d8) %{
1630 emit_opcode(cbuf, $d8$$constant);
1631 %}
1632
1633 enc_class SizePrefix %{
1634 emit_opcode(cbuf,0x66);
1635 %}
1636
1637 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1638 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1639 %}
1640
1641 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1642 emit_opcode(cbuf,$opcode$$constant);
1643 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1644 %}
1645
1646 enc_class mov_r32_imm0( rRegI dst ) %{
1647 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1648 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1649 %}
1650
1651 enc_class cdq_enc %{
1652 // Full implementation of Java idiv and irem; checks for
1653 // special case as described in JVM spec., p.243 & p.271.
1654 //
1655 // normal case special case
1656 //
1657 // input : rax,: dividend min_int
1658 // reg: divisor -1
1659 //
1660 // output: rax,: quotient (= rax, idiv reg) min_int
1661 // rdx: remainder (= rax, irem reg) 0
1662 //
1663 // Code sequnce:
1664 //
1665 // 81 F8 00 00 00 80 cmp rax,80000000h
1666 // 0F 85 0B 00 00 00 jne normal_case
1667 // 33 D2 xor rdx,edx
1668 // 83 F9 FF cmp rcx,0FFh
1669 // 0F 84 03 00 00 00 je done
1670 // normal_case:
1671 // 99 cdq
1672 // F7 F9 idiv rax,ecx
1673 // done:
1674 //
1675 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1676 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1677 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1678 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1679 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1680 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1681 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1682 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1683 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1684 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1685 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1686 // normal_case:
1687 emit_opcode(cbuf,0x99); // cdq
1688 // idiv (note: must be emitted by the user of this rule)
1689 // normal:
1690 %}
1691
1692 // Dense encoding for older common ops
1693 enc_class Opc_plus(immI opcode, rRegI reg) %{
1694 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1695 %}
1696
1697
1698 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1699 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1700 // Check for 8-bit immediate, and set sign extend bit in opcode
1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1702 emit_opcode(cbuf, $primary | 0x02);
1703 }
1704 else { // If 32-bit immediate
1705 emit_opcode(cbuf, $primary);
1706 }
1707 %}
1708
1709 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1710 // Emit primary opcode and set sign-extend bit
1711 // Check for 8-bit immediate, and set sign extend bit in opcode
1712 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1713 emit_opcode(cbuf, $primary | 0x02); }
1714 else { // If 32-bit immediate
1715 emit_opcode(cbuf, $primary);
1716 }
1717 // Emit r/m byte with secondary opcode, after primary opcode.
1718 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1719 %}
1720
1721 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1722 // Check for 8-bit immediate, and set sign extend bit in opcode
1723 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1724 $$$emit8$imm$$constant;
1725 }
1726 else { // If 32-bit immediate
1727 // Output immediate
1728 $$$emit32$imm$$constant;
1729 }
1730 %}
1731
1732 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1733 // Emit primary opcode and set sign-extend bit
1734 // Check for 8-bit immediate, and set sign extend bit in opcode
1735 int con = (int)$imm$$constant; // Throw away top bits
1736 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1737 // Emit r/m byte with secondary opcode, after primary opcode.
1738 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1739 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1740 else emit_d32(cbuf,con);
1741 %}
1742
1743 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1744 // Emit primary opcode and set sign-extend bit
1745 // Check for 8-bit immediate, and set sign extend bit in opcode
1746 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1747 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1748 // Emit r/m byte with tertiary opcode, after primary opcode.
1749 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1750 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1751 else emit_d32(cbuf,con);
1752 %}
1753
1754 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1755 emit_cc(cbuf, $secondary, $dst$$reg );
1756 %}
1757
1758 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1759 int destlo = $dst$$reg;
1760 int desthi = HIGH_FROM_LOW(destlo);
1761 // bswap lo
1762 emit_opcode(cbuf, 0x0F);
1763 emit_cc(cbuf, 0xC8, destlo);
1764 // bswap hi
1765 emit_opcode(cbuf, 0x0F);
1766 emit_cc(cbuf, 0xC8, desthi);
1767 // xchg lo and hi
1768 emit_opcode(cbuf, 0x87);
1769 emit_rm(cbuf, 0x3, destlo, desthi);
1770 %}
1771
1772 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1773 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1774 %}
1775
1776 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1777 $$$emit8$primary;
1778 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1779 %}
1780
1781 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1782 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1783 emit_d8(cbuf, op >> 8 );
1784 emit_d8(cbuf, op & 255);
1785 %}
1786
1787 // emulate a CMOV with a conditional branch around a MOV
1788 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1789 // Invert sense of branch from sense of CMOV
1790 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1791 emit_d8( cbuf, $brOffs$$constant );
1792 %}
1793
1794 enc_class enc_PartialSubtypeCheck( ) %{
1795 Register Redi = as_Register(EDI_enc); // result register
1796 Register Reax = as_Register(EAX_enc); // super class
1797 Register Recx = as_Register(ECX_enc); // killed
1798 Register Resi = as_Register(ESI_enc); // sub class
1799 Label miss;
1800
1801 MacroAssembler _masm(&cbuf);
1802 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1803 NULL, &miss,
1804 /*set_cond_codes:*/ true);
1805 if ($primary) {
1806 __ xorptr(Redi, Redi);
1807 }
1808 __ bind(miss);
1809 %}
1810
1811 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1812 MacroAssembler masm(&cbuf);
1813 int start = masm.offset();
1814 if (UseSSE >= 2) {
1815 if (VerifyFPU) {
1816 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1817 }
1818 } else {
1819 // External c_calling_convention expects the FPU stack to be 'clean'.
1820 // Compiled code leaves it dirty. Do cleanup now.
1821 masm.empty_FPU_stack();
1822 }
1823 if (sizeof_FFree_Float_Stack_All == -1) {
1824 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1825 } else {
1826 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1827 }
1828 %}
1829
1830 enc_class Verify_FPU_For_Leaf %{
1831 if( VerifyFPU ) {
1832 MacroAssembler masm(&cbuf);
1833 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1834 }
1835 %}
1836
1837 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1838 // This is the instruction starting address for relocation info.
1839 cbuf.set_insts_mark();
1840 $$$emit8$primary;
1841 // CALL directly to the runtime
1842 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1843 runtime_call_Relocation::spec(), RELOC_IMM32 );
1844
1845 if (UseSSE >= 2) {
1846 MacroAssembler _masm(&cbuf);
1847 BasicType rt = tf()->return_type();
1848
1849 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1850 // A C runtime call where the return value is unused. In SSE2+
1851 // mode the result needs to be removed from the FPU stack. It's
1852 // likely that this function call could be removed by the
1853 // optimizer if the C function is a pure function.
1854 __ ffree(0);
1855 } else if (rt == T_FLOAT) {
1856 __ lea(rsp, Address(rsp, -4));
1857 __ fstp_s(Address(rsp, 0));
1858 __ movflt(xmm0, Address(rsp, 0));
1859 __ lea(rsp, Address(rsp, 4));
1860 } else if (rt == T_DOUBLE) {
1861 __ lea(rsp, Address(rsp, -8));
1862 __ fstp_d(Address(rsp, 0));
1863 __ movdbl(xmm0, Address(rsp, 0));
1864 __ lea(rsp, Address(rsp, 8));
1865 }
1866 }
1867 %}
1868
1869
1870 enc_class pre_call_FPU %{
1871 // If method sets FPU control word restore it here
1872 debug_only(int off0 = cbuf.insts_size());
1873 if( Compile::current()->in_24_bit_fp_mode() ) {
1874 MacroAssembler masm(&cbuf);
1875 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1876 }
1877 debug_only(int off1 = cbuf.insts_size());
1878 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1879 %}
1880
1881 enc_class post_call_FPU %{
1882 // If method sets FPU control word do it here also
1883 if( Compile::current()->in_24_bit_fp_mode() ) {
1884 MacroAssembler masm(&cbuf);
1885 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1886 }
1887 %}
1888
1889 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1890 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1891 // who we intended to call.
1892 cbuf.set_insts_mark();
1893 $$$emit8$primary;
1894 if ( !_method ) {
1895 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1896 runtime_call_Relocation::spec(), RELOC_IMM32 );
1897 } else if(_optimized_virtual) {
1898 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1899 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1900 } else {
1901 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1902 static_call_Relocation::spec(), RELOC_IMM32 );
1903 }
1904 if( _method ) { // Emit stub for static call
1905 emit_java_to_interp(cbuf);
1906 }
1907 %}
1908
1909 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1910 // !!!!!
1911 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1912 // emit_call_dynamic_prologue( cbuf );
1913 cbuf.set_insts_mark();
1914 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1915 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1916 address virtual_call_oop_addr = cbuf.insts_mark();
1917 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1918 // who we intended to call.
1919 cbuf.set_insts_mark();
1920 $$$emit8$primary;
1921 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1922 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1923 %}
1924
1925 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1926 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1927 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1928
1929 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1930 cbuf.set_insts_mark();
1931 $$$emit8$primary;
1932 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1933 emit_d8(cbuf, disp); // Displacement
1934
1935 %}
1936
1937 // Following encoding is no longer used, but may be restored if calling
1938 // convention changes significantly.
1939 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1940 //
1941 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1942 // // int ic_reg = Matcher::inline_cache_reg();
1943 // // int ic_encode = Matcher::_regEncode[ic_reg];
1944 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1945 // // int imo_encode = Matcher::_regEncode[imo_reg];
1946 //
1947 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1948 // // // so we load it immediately before the call
1949 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1950 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1951 //
1952 // // xor rbp,ebp
1953 // emit_opcode(cbuf, 0x33);
1954 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1955 //
1956 // // CALL to interpreter.
1957 // cbuf.set_insts_mark();
1958 // $$$emit8$primary;
1959 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1960 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1961 // %}
1962
1963 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1964 $$$emit8$primary;
1965 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1966 $$$emit8$shift$$constant;
1967 %}
1968
1969 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1970 // Load immediate does not have a zero or sign extended version
1971 // for 8-bit immediates
1972 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1973 $$$emit32$src$$constant;
1974 %}
1975
1976 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1977 // Load immediate does not have a zero or sign extended version
1978 // for 8-bit immediates
1979 emit_opcode(cbuf, $primary + $dst$$reg);
1980 $$$emit32$src$$constant;
1981 %}
1982
1983 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1984 // Load immediate does not have a zero or sign extended version
1985 // for 8-bit immediates
1986 int dst_enc = $dst$$reg;
1987 int src_con = $src$$constant & 0x0FFFFFFFFL;
1988 if (src_con == 0) {
1989 // xor dst, dst
1990 emit_opcode(cbuf, 0x33);
1991 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1992 } else {
1993 emit_opcode(cbuf, $primary + dst_enc);
1994 emit_d32(cbuf, src_con);
1995 }
1996 %}
1997
1998 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1999 // Load immediate does not have a zero or sign extended version
2000 // for 8-bit immediates
2001 int dst_enc = $dst$$reg + 2;
2002 int src_con = ((julong)($src$$constant)) >> 32;
2003 if (src_con == 0) {
2004 // xor dst, dst
2005 emit_opcode(cbuf, 0x33);
2006 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2007 } else {
2008 emit_opcode(cbuf, $primary + dst_enc);
2009 emit_d32(cbuf, src_con);
2010 }
2011 %}
2012
2013
2014 // Encode a reg-reg copy. If it is useless, then empty encoding.
2015 enc_class enc_Copy( rRegI dst, rRegI src ) %{
2016 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2017 %}
2018
2019 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2020 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2021 %}
2022
2023 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2024 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2025 %}
2026
2027 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2028 $$$emit8$primary;
2029 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2030 %}
2031
2032 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2033 $$$emit8$secondary;
2034 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2035 %}
2036
2037 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2038 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2039 %}
2040
2041 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2042 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2043 %}
2044
2045 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2046 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2047 %}
2048
2049 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2050 // Output immediate
2051 $$$emit32$src$$constant;
2052 %}
2053
2054 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2055 // Output Float immediate bits
2056 jfloat jf = $src$$constant;
2057 int jf_as_bits = jint_cast( jf );
2058 emit_d32(cbuf, jf_as_bits);
2059 %}
2060
2061 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2062 // Output Float immediate bits
2063 jfloat jf = $src$$constant;
2064 int jf_as_bits = jint_cast( jf );
2065 emit_d32(cbuf, jf_as_bits);
2066 %}
2067
2068 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2069 // Output immediate
2070 $$$emit16$src$$constant;
2071 %}
2072
2073 enc_class Con_d32(immI src) %{
2074 emit_d32(cbuf,$src$$constant);
2075 %}
2076
2077 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2078 // Output immediate memory reference
2079 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2080 emit_d32(cbuf, 0x00);
2081 %}
2082
2083 enc_class lock_prefix( ) %{
2084 if( os::is_MP() )
2085 emit_opcode(cbuf,0xF0); // [Lock]
2086 %}
2087
2088 // Cmp-xchg long value.
2089 // Note: we need to swap rbx, and rcx before and after the
2090 // cmpxchg8 instruction because the instruction uses
2091 // rcx as the high order word of the new value to store but
2092 // our register encoding uses rbx,.
2093 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2094
2095 // XCHG rbx,ecx
2096 emit_opcode(cbuf,0x87);
2097 emit_opcode(cbuf,0xD9);
2098 // [Lock]
2099 if( os::is_MP() )
2100 emit_opcode(cbuf,0xF0);
2101 // CMPXCHG8 [Eptr]
2102 emit_opcode(cbuf,0x0F);
2103 emit_opcode(cbuf,0xC7);
2104 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2105 // XCHG rbx,ecx
2106 emit_opcode(cbuf,0x87);
2107 emit_opcode(cbuf,0xD9);
2108 %}
2109
2110 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2111 // [Lock]
2112 if( os::is_MP() )
2113 emit_opcode(cbuf,0xF0);
2114
2115 // CMPXCHG [Eptr]
2116 emit_opcode(cbuf,0x0F);
2117 emit_opcode(cbuf,0xB1);
2118 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2119 %}
2120
2121 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2122 int res_encoding = $res$$reg;
2123
2124 // MOV res,0
2125 emit_opcode( cbuf, 0xB8 + res_encoding);
2126 emit_d32( cbuf, 0 );
2127 // JNE,s fail
2128 emit_opcode(cbuf,0x75);
2129 emit_d8(cbuf, 5 );
2130 // MOV res,1
2131 emit_opcode( cbuf, 0xB8 + res_encoding);
2132 emit_d32( cbuf, 1 );
2133 // fail:
2134 %}
2135
2136 enc_class set_instruction_start( ) %{
2137 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2138 %}
2139
2140 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2141 int reg_encoding = $ereg$$reg;
2142 int base = $mem$$base;
2143 int index = $mem$$index;
2144 int scale = $mem$$scale;
2145 int displace = $mem$$disp;
2146 bool disp_is_oop = $mem->disp_is_oop();
2147 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2148 %}
2149
2150 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2151 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2152 int base = $mem$$base;
2153 int index = $mem$$index;
2154 int scale = $mem$$scale;
2155 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2156 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2157 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2158 %}
2159
2160 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2161 int r1, r2;
2162 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2163 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2164 emit_opcode(cbuf,0x0F);
2165 emit_opcode(cbuf,$tertiary);
2166 emit_rm(cbuf, 0x3, r1, r2);
2167 emit_d8(cbuf,$cnt$$constant);
2168 emit_d8(cbuf,$primary);
2169 emit_rm(cbuf, 0x3, $secondary, r1);
2170 emit_d8(cbuf,$cnt$$constant);
2171 %}
2172
2173 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2174 emit_opcode( cbuf, 0x8B ); // Move
2175 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2176 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2177 emit_d8(cbuf,$primary);
2178 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2179 emit_d8(cbuf,$cnt$$constant-32);
2180 }
2181 emit_d8(cbuf,$primary);
2182 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2183 emit_d8(cbuf,31);
2184 %}
2185
2186 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2187 int r1, r2;
2188 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2189 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2190
2191 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2192 emit_rm(cbuf, 0x3, r1, r2);
2193 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2194 emit_opcode(cbuf,$primary);
2195 emit_rm(cbuf, 0x3, $secondary, r1);
2196 emit_d8(cbuf,$cnt$$constant-32);
2197 }
2198 emit_opcode(cbuf,0x33); // XOR r2,r2
2199 emit_rm(cbuf, 0x3, r2, r2);
2200 %}
2201
2202 // Clone of RegMem but accepts an extra parameter to access each
2203 // half of a double in memory; it never needs relocation info.
2204 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2205 emit_opcode(cbuf,$opcode$$constant);
2206 int reg_encoding = $rm_reg$$reg;
2207 int base = $mem$$base;
2208 int index = $mem$$index;
2209 int scale = $mem$$scale;
2210 int displace = $mem$$disp + $disp_for_half$$constant;
2211 bool disp_is_oop = false;
2212 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2213 %}
2214
2215 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2216 //
2217 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2218 // and it never needs relocation information.
2219 // Frequently used to move data between FPU's Stack Top and memory.
2220 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2221 int rm_byte_opcode = $rm_opcode$$constant;
2222 int base = $mem$$base;
2223 int index = $mem$$index;
2224 int scale = $mem$$scale;
2225 int displace = $mem$$disp;
2226 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2227 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2228 %}
2229
2230 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2231 int rm_byte_opcode = $rm_opcode$$constant;
2232 int base = $mem$$base;
2233 int index = $mem$$index;
2234 int scale = $mem$$scale;
2235 int displace = $mem$$disp;
2236 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2237 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2238 %}
2239
2240 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2241 int reg_encoding = $dst$$reg;
2242 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2243 int index = 0x04; // 0x04 indicates no index
2244 int scale = 0x00; // 0x00 indicates no scale
2245 int displace = $src1$$constant; // 0x00 indicates no displacement
2246 bool disp_is_oop = false;
2247 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2248 %}
2249
2250 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2251 // Compare dst,src
2252 emit_opcode(cbuf,0x3B);
2253 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2254 // jmp dst < src around move
2255 emit_opcode(cbuf,0x7C);
2256 emit_d8(cbuf,2);
2257 // move dst,src
2258 emit_opcode(cbuf,0x8B);
2259 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2260 %}
2261
2262 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2263 // Compare dst,src
2264 emit_opcode(cbuf,0x3B);
2265 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2266 // jmp dst > src around move
2267 emit_opcode(cbuf,0x7F);
2268 emit_d8(cbuf,2);
2269 // move dst,src
2270 emit_opcode(cbuf,0x8B);
2271 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2272 %}
2273
2274 enc_class enc_FPR_store(memory mem, regDPR src) %{
2275 // If src is FPR1, we can just FST to store it.
2276 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2277 int reg_encoding = 0x2; // Just store
2278 int base = $mem$$base;
2279 int index = $mem$$index;
2280 int scale = $mem$$scale;
2281 int displace = $mem$$disp;
2282 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2283 if( $src$$reg != FPR1L_enc ) {
2284 reg_encoding = 0x3; // Store & pop
2285 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2286 emit_d8( cbuf, 0xC0-1+$src$$reg );
2287 }
2288 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2289 emit_opcode(cbuf,$primary);
2290 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2291 %}
2292
2293 enc_class neg_reg(rRegI dst) %{
2294 // NEG $dst
2295 emit_opcode(cbuf,0xF7);
2296 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2297 %}
2298
2299 enc_class setLT_reg(eCXRegI dst) %{
2300 // SETLT $dst
2301 emit_opcode(cbuf,0x0F);
2302 emit_opcode(cbuf,0x9C);
2303 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2304 %}
2305
2306 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2307 int tmpReg = $tmp$$reg;
2308
2309 // SUB $p,$q
2310 emit_opcode(cbuf,0x2B);
2311 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2312 // SBB $tmp,$tmp
2313 emit_opcode(cbuf,0x1B);
2314 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2315 // AND $tmp,$y
2316 emit_opcode(cbuf,0x23);
2317 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2318 // ADD $p,$tmp
2319 emit_opcode(cbuf,0x03);
2320 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2321 %}
2322
2323 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2324 int tmpReg = $tmp$$reg;
2325
2326 // SUB $p,$q
2327 emit_opcode(cbuf,0x2B);
2328 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2329 // SBB $tmp,$tmp
2330 emit_opcode(cbuf,0x1B);
2331 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2332 // AND $tmp,$y
2333 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2334 emit_opcode(cbuf,0x23);
2335 int reg_encoding = tmpReg;
2336 int base = $mem$$base;
2337 int index = $mem$$index;
2338 int scale = $mem$$scale;
2339 int displace = $mem$$disp;
2340 bool disp_is_oop = $mem->disp_is_oop();
2341 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2342 // ADD $p,$tmp
2343 emit_opcode(cbuf,0x03);
2344 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2345 %}
2346
2347 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2348 // TEST shift,32
2349 emit_opcode(cbuf,0xF7);
2350 emit_rm(cbuf, 0x3, 0, ECX_enc);
2351 emit_d32(cbuf,0x20);
2352 // JEQ,s small
2353 emit_opcode(cbuf, 0x74);
2354 emit_d8(cbuf, 0x04);
2355 // MOV $dst.hi,$dst.lo
2356 emit_opcode( cbuf, 0x8B );
2357 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2358 // CLR $dst.lo
2359 emit_opcode(cbuf, 0x33);
2360 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2361 // small:
2362 // SHLD $dst.hi,$dst.lo,$shift
2363 emit_opcode(cbuf,0x0F);
2364 emit_opcode(cbuf,0xA5);
2365 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2366 // SHL $dst.lo,$shift"
2367 emit_opcode(cbuf,0xD3);
2368 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2369 %}
2370
2371 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2372 // TEST shift,32
2373 emit_opcode(cbuf,0xF7);
2374 emit_rm(cbuf, 0x3, 0, ECX_enc);
2375 emit_d32(cbuf,0x20);
2376 // JEQ,s small
2377 emit_opcode(cbuf, 0x74);
2378 emit_d8(cbuf, 0x04);
2379 // MOV $dst.lo,$dst.hi
2380 emit_opcode( cbuf, 0x8B );
2381 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2382 // CLR $dst.hi
2383 emit_opcode(cbuf, 0x33);
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2385 // small:
2386 // SHRD $dst.lo,$dst.hi,$shift
2387 emit_opcode(cbuf,0x0F);
2388 emit_opcode(cbuf,0xAD);
2389 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2390 // SHR $dst.hi,$shift"
2391 emit_opcode(cbuf,0xD3);
2392 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2393 %}
2394
2395 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2396 // TEST shift,32
2397 emit_opcode(cbuf,0xF7);
2398 emit_rm(cbuf, 0x3, 0, ECX_enc);
2399 emit_d32(cbuf,0x20);
2400 // JEQ,s small
2401 emit_opcode(cbuf, 0x74);
2402 emit_d8(cbuf, 0x05);
2403 // MOV $dst.lo,$dst.hi
2404 emit_opcode( cbuf, 0x8B );
2405 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2406 // SAR $dst.hi,31
2407 emit_opcode(cbuf, 0xC1);
2408 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2409 emit_d8(cbuf, 0x1F );
2410 // small:
2411 // SHRD $dst.lo,$dst.hi,$shift
2412 emit_opcode(cbuf,0x0F);
2413 emit_opcode(cbuf,0xAD);
2414 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2415 // SAR $dst.hi,$shift"
2416 emit_opcode(cbuf,0xD3);
2417 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2418 %}
2419
2420
2421 // ----------------- Encodings for floating point unit -----------------
2422 // May leave result in FPU-TOS or FPU reg depending on opcodes
2423 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2424 $$$emit8$primary;
2425 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2426 %}
2427
2428 // Pop argument in FPR0 with FSTP ST(0)
2429 enc_class PopFPU() %{
2430 emit_opcode( cbuf, 0xDD );
2431 emit_d8( cbuf, 0xD8 );
2432 %}
2433
2434 // !!!!! equivalent to Pop_Reg_F
2435 enc_class Pop_Reg_DPR( regDPR dst ) %{
2436 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2437 emit_d8( cbuf, 0xD8+$dst$$reg );
2438 %}
2439
2440 enc_class Push_Reg_DPR( regDPR dst ) %{
2441 emit_opcode( cbuf, 0xD9 );
2442 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2443 %}
2444
2445 enc_class strictfp_bias1( regDPR dst ) %{
2446 emit_opcode( cbuf, 0xDB ); // FLD m80real
2447 emit_opcode( cbuf, 0x2D );
2448 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2449 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2450 emit_opcode( cbuf, 0xC8+$dst$$reg );
2451 %}
2452
2453 enc_class strictfp_bias2( regDPR dst ) %{
2454 emit_opcode( cbuf, 0xDB ); // FLD m80real
2455 emit_opcode( cbuf, 0x2D );
2456 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2457 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2458 emit_opcode( cbuf, 0xC8+$dst$$reg );
2459 %}
2460
2461 // Special case for moving an integer register to a stack slot.
2462 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2463 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2464 %}
2465
2466 // Special case for moving a register to a stack slot.
2467 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2468 // Opcode already emitted
2469 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2470 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2471 emit_d32(cbuf, $dst$$disp); // Displacement
2472 %}
2473
2474 // Push the integer in stackSlot 'src' onto FP-stack
2475 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2476 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2477 %}
2478
2479 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2480 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2481 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2482 %}
2483
2484 // Same as Pop_Mem_F except for opcode
2485 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2486 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2487 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2488 %}
2489
2490 enc_class Pop_Reg_FPR( regFPR dst ) %{
2491 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2492 emit_d8( cbuf, 0xD8+$dst$$reg );
2493 %}
2494
2495 enc_class Push_Reg_FPR( regFPR dst ) %{
2496 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2497 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2498 %}
2499
2500 // Push FPU's float to a stack-slot, and pop FPU-stack
2501 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2502 int pop = 0x02;
2503 if ($src$$reg != FPR1L_enc) {
2504 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2505 emit_d8( cbuf, 0xC0-1+$src$$reg );
2506 pop = 0x03;
2507 }
2508 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2509 %}
2510
2511 // Push FPU's double to a stack-slot, and pop FPU-stack
2512 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2513 int pop = 0x02;
2514 if ($src$$reg != FPR1L_enc) {
2515 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2516 emit_d8( cbuf, 0xC0-1+$src$$reg );
2517 pop = 0x03;
2518 }
2519 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2520 %}
2521
2522 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2523 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2524 int pop = 0xD0 - 1; // -1 since we skip FLD
2525 if ($src$$reg != FPR1L_enc) {
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2527 emit_d8( cbuf, 0xC0-1+$src$$reg );
2528 pop = 0xD8;
2529 }
2530 emit_opcode( cbuf, 0xDD );
2531 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2532 %}
2533
2534
2535 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2536 // load dst in FPR0
2537 emit_opcode( cbuf, 0xD9 );
2538 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2539 if ($src$$reg != FPR1L_enc) {
2540 // fincstp
2541 emit_opcode (cbuf, 0xD9);
2542 emit_opcode (cbuf, 0xF7);
2543 // swap src with FPR1:
2544 // FXCH FPR1 with src
2545 emit_opcode(cbuf, 0xD9);
2546 emit_d8(cbuf, 0xC8-1+$src$$reg );
2547 // fdecstp
2548 emit_opcode (cbuf, 0xD9);
2549 emit_opcode (cbuf, 0xF6);
2550 }
2551 %}
2552
2553 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2554 MacroAssembler _masm(&cbuf);
2555 __ subptr(rsp, 8);
2556 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2557 __ fld_d(Address(rsp, 0));
2558 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2559 __ fld_d(Address(rsp, 0));
2560 %}
2561
2562 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ subptr(rsp, 4);
2565 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2566 __ fld_s(Address(rsp, 0));
2567 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2568 __ fld_s(Address(rsp, 0));
2569 %}
2570
2571 enc_class Push_ResultD(regD dst) %{
2572 MacroAssembler _masm(&cbuf);
2573 __ fstp_d(Address(rsp, 0));
2574 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2575 __ addptr(rsp, 8);
2576 %}
2577
2578 enc_class Push_ResultF(regF dst, immI d8) %{
2579 MacroAssembler _masm(&cbuf);
2580 __ fstp_s(Address(rsp, 0));
2581 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2582 __ addptr(rsp, $d8$$constant);
2583 %}
2584
2585 enc_class Push_SrcD(regD src) %{
2586 MacroAssembler _masm(&cbuf);
2587 __ subptr(rsp, 8);
2588 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2589 __ fld_d(Address(rsp, 0));
2590 %}
2591
2592 enc_class push_stack_temp_qword() %{
2593 MacroAssembler _masm(&cbuf);
2594 __ subptr(rsp, 8);
2595 %}
2596
2597 enc_class pop_stack_temp_qword() %{
2598 MacroAssembler _masm(&cbuf);
2599 __ addptr(rsp, 8);
2600 %}
2601
2602 enc_class push_xmm_to_fpr1(regD src) %{
2603 MacroAssembler _masm(&cbuf);
2604 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2605 __ fld_d(Address(rsp, 0));
2606 %}
2607
2608 enc_class Push_Result_Mod_DPR( regDPR src) %{
2609 if ($src$$reg != FPR1L_enc) {
2610 // fincstp
2611 emit_opcode (cbuf, 0xD9);
2612 emit_opcode (cbuf, 0xF7);
2613 // FXCH FPR1 with src
2614 emit_opcode(cbuf, 0xD9);
2615 emit_d8(cbuf, 0xC8-1+$src$$reg );
2616 // fdecstp
2617 emit_opcode (cbuf, 0xD9);
2618 emit_opcode (cbuf, 0xF6);
2619 }
2620 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2621 // // FSTP FPR$dst$$reg
2622 // emit_opcode( cbuf, 0xDD );
2623 // emit_d8( cbuf, 0xD8+$dst$$reg );
2624 %}
2625
2626 enc_class fnstsw_sahf_skip_parity() %{
2627 // fnstsw ax
2628 emit_opcode( cbuf, 0xDF );
2629 emit_opcode( cbuf, 0xE0 );
2630 // sahf
2631 emit_opcode( cbuf, 0x9E );
2632 // jnp ::skip
2633 emit_opcode( cbuf, 0x7B );
2634 emit_opcode( cbuf, 0x05 );
2635 %}
2636
2637 enc_class emitModDPR() %{
2638 // fprem must be iterative
2639 // :: loop
2640 // fprem
2641 emit_opcode( cbuf, 0xD9 );
2642 emit_opcode( cbuf, 0xF8 );
2643 // wait
2644 emit_opcode( cbuf, 0x9b );
2645 // fnstsw ax
2646 emit_opcode( cbuf, 0xDF );
2647 emit_opcode( cbuf, 0xE0 );
2648 // sahf
2649 emit_opcode( cbuf, 0x9E );
2650 // jp ::loop
2651 emit_opcode( cbuf, 0x0F );
2652 emit_opcode( cbuf, 0x8A );
2653 emit_opcode( cbuf, 0xF4 );
2654 emit_opcode( cbuf, 0xFF );
2655 emit_opcode( cbuf, 0xFF );
2656 emit_opcode( cbuf, 0xFF );
2657 %}
2658
2659 enc_class fpu_flags() %{
2660 // fnstsw_ax
2661 emit_opcode( cbuf, 0xDF);
2662 emit_opcode( cbuf, 0xE0);
2663 // test ax,0x0400
2664 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2665 emit_opcode( cbuf, 0xA9 );
2666 emit_d16 ( cbuf, 0x0400 );
2667 // // // This sequence works, but stalls for 12-16 cycles on PPro
2668 // // test rax,0x0400
2669 // emit_opcode( cbuf, 0xA9 );
2670 // emit_d32 ( cbuf, 0x00000400 );
2671 //
2672 // jz exit (no unordered comparison)
2673 emit_opcode( cbuf, 0x74 );
2674 emit_d8 ( cbuf, 0x02 );
2675 // mov ah,1 - treat as LT case (set carry flag)
2676 emit_opcode( cbuf, 0xB4 );
2677 emit_d8 ( cbuf, 0x01 );
2678 // sahf
2679 emit_opcode( cbuf, 0x9E);
2680 %}
2681
2682 enc_class cmpF_P6_fixup() %{
2683 // Fixup the integer flags in case comparison involved a NaN
2684 //
2685 // JNP exit (no unordered comparison, P-flag is set by NaN)
2686 emit_opcode( cbuf, 0x7B );
2687 emit_d8 ( cbuf, 0x03 );
2688 // MOV AH,1 - treat as LT case (set carry flag)
2689 emit_opcode( cbuf, 0xB4 );
2690 emit_d8 ( cbuf, 0x01 );
2691 // SAHF
2692 emit_opcode( cbuf, 0x9E);
2693 // NOP // target for branch to avoid branch to branch
2694 emit_opcode( cbuf, 0x90);
2695 %}
2696
2697 // fnstsw_ax();
2698 // sahf();
2699 // movl(dst, nan_result);
2700 // jcc(Assembler::parity, exit);
2701 // movl(dst, less_result);
2702 // jcc(Assembler::below, exit);
2703 // movl(dst, equal_result);
2704 // jcc(Assembler::equal, exit);
2705 // movl(dst, greater_result);
2706
2707 // less_result = 1;
2708 // greater_result = -1;
2709 // equal_result = 0;
2710 // nan_result = -1;
2711
2712 enc_class CmpF_Result(rRegI dst) %{
2713 // fnstsw_ax();
2714 emit_opcode( cbuf, 0xDF);
2715 emit_opcode( cbuf, 0xE0);
2716 // sahf
2717 emit_opcode( cbuf, 0x9E);
2718 // movl(dst, nan_result);
2719 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2720 emit_d32( cbuf, -1 );
2721 // jcc(Assembler::parity, exit);
2722 emit_opcode( cbuf, 0x7A );
2723 emit_d8 ( cbuf, 0x13 );
2724 // movl(dst, less_result);
2725 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2726 emit_d32( cbuf, -1 );
2727 // jcc(Assembler::below, exit);
2728 emit_opcode( cbuf, 0x72 );
2729 emit_d8 ( cbuf, 0x0C );
2730 // movl(dst, equal_result);
2731 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2732 emit_d32( cbuf, 0 );
2733 // jcc(Assembler::equal, exit);
2734 emit_opcode( cbuf, 0x74 );
2735 emit_d8 ( cbuf, 0x05 );
2736 // movl(dst, greater_result);
2737 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2738 emit_d32( cbuf, 1 );
2739 %}
2740
2741
2742 // Compare the longs and set flags
2743 // BROKEN! Do Not use as-is
2744 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2745 // CMP $src1.hi,$src2.hi
2746 emit_opcode( cbuf, 0x3B );
2747 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2748 // JNE,s done
2749 emit_opcode(cbuf,0x75);
2750 emit_d8(cbuf, 2 );
2751 // CMP $src1.lo,$src2.lo
2752 emit_opcode( cbuf, 0x3B );
2753 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2754 // done:
2755 %}
2756
2757 enc_class convert_int_long( regL dst, rRegI src ) %{
2758 // mov $dst.lo,$src
2759 int dst_encoding = $dst$$reg;
2760 int src_encoding = $src$$reg;
2761 encode_Copy( cbuf, dst_encoding , src_encoding );
2762 // mov $dst.hi,$src
2763 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2764 // sar $dst.hi,31
2765 emit_opcode( cbuf, 0xC1 );
2766 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2767 emit_d8(cbuf, 0x1F );
2768 %}
2769
2770 enc_class convert_long_double( eRegL src ) %{
2771 // push $src.hi
2772 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2773 // push $src.lo
2774 emit_opcode(cbuf, 0x50+$src$$reg );
2775 // fild 64-bits at [SP]
2776 emit_opcode(cbuf,0xdf);
2777 emit_d8(cbuf, 0x6C);
2778 emit_d8(cbuf, 0x24);
2779 emit_d8(cbuf, 0x00);
2780 // pop stack
2781 emit_opcode(cbuf, 0x83); // add SP, #8
2782 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2783 emit_d8(cbuf, 0x8);
2784 %}
2785
2786 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2787 // IMUL EDX:EAX,$src1
2788 emit_opcode( cbuf, 0xF7 );
2789 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2790 // SAR EDX,$cnt-32
2791 int shift_count = ((int)$cnt$$constant) - 32;
2792 if (shift_count > 0) {
2793 emit_opcode(cbuf, 0xC1);
2794 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2795 emit_d8(cbuf, shift_count);
2796 }
2797 %}
2798
2799 // this version doesn't have add sp, 8
2800 enc_class convert_long_double2( eRegL src ) %{
2801 // push $src.hi
2802 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2803 // push $src.lo
2804 emit_opcode(cbuf, 0x50+$src$$reg );
2805 // fild 64-bits at [SP]
2806 emit_opcode(cbuf,0xdf);
2807 emit_d8(cbuf, 0x6C);
2808 emit_d8(cbuf, 0x24);
2809 emit_d8(cbuf, 0x00);
2810 %}
2811
2812 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2813 // Basic idea: long = (long)int * (long)int
2814 // IMUL EDX:EAX, src
2815 emit_opcode( cbuf, 0xF7 );
2816 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2817 %}
2818
2819 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2820 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2821 // MUL EDX:EAX, src
2822 emit_opcode( cbuf, 0xF7 );
2823 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2824 %}
2825
2826 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2827 // Basic idea: lo(result) = lo(x_lo * y_lo)
2828 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2829 // MOV $tmp,$src.lo
2830 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2831 // IMUL $tmp,EDX
2832 emit_opcode( cbuf, 0x0F );
2833 emit_opcode( cbuf, 0xAF );
2834 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2835 // MOV EDX,$src.hi
2836 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2837 // IMUL EDX,EAX
2838 emit_opcode( cbuf, 0x0F );
2839 emit_opcode( cbuf, 0xAF );
2840 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2841 // ADD $tmp,EDX
2842 emit_opcode( cbuf, 0x03 );
2843 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2844 // MUL EDX:EAX,$src.lo
2845 emit_opcode( cbuf, 0xF7 );
2846 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2847 // ADD EDX,ESI
2848 emit_opcode( cbuf, 0x03 );
2849 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2850 %}
2851
2852 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2853 // Basic idea: lo(result) = lo(src * y_lo)
2854 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2855 // IMUL $tmp,EDX,$src
2856 emit_opcode( cbuf, 0x6B );
2857 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2858 emit_d8( cbuf, (int)$src$$constant );
2859 // MOV EDX,$src
2860 emit_opcode(cbuf, 0xB8 + EDX_enc);
2861 emit_d32( cbuf, (int)$src$$constant );
2862 // MUL EDX:EAX,EDX
2863 emit_opcode( cbuf, 0xF7 );
2864 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2865 // ADD EDX,ESI
2866 emit_opcode( cbuf, 0x03 );
2867 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2868 %}
2869
2870 enc_class long_div( eRegL src1, eRegL src2 ) %{
2871 // PUSH src1.hi
2872 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2873 // PUSH src1.lo
2874 emit_opcode(cbuf, 0x50+$src1$$reg );
2875 // PUSH src2.hi
2876 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2877 // PUSH src2.lo
2878 emit_opcode(cbuf, 0x50+$src2$$reg );
2879 // CALL directly to the runtime
2880 cbuf.set_insts_mark();
2881 emit_opcode(cbuf,0xE8); // Call into runtime
2882 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2883 // Restore stack
2884 emit_opcode(cbuf, 0x83); // add SP, #framesize
2885 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2886 emit_d8(cbuf, 4*4);
2887 %}
2888
2889 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2890 // PUSH src1.hi
2891 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2892 // PUSH src1.lo
2893 emit_opcode(cbuf, 0x50+$src1$$reg );
2894 // PUSH src2.hi
2895 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2896 // PUSH src2.lo
2897 emit_opcode(cbuf, 0x50+$src2$$reg );
2898 // CALL directly to the runtime
2899 cbuf.set_insts_mark();
2900 emit_opcode(cbuf,0xE8); // Call into runtime
2901 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2902 // Restore stack
2903 emit_opcode(cbuf, 0x83); // add SP, #framesize
2904 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2905 emit_d8(cbuf, 4*4);
2906 %}
2907
2908 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2909 // MOV $tmp,$src.lo
2910 emit_opcode(cbuf, 0x8B);
2911 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2912 // OR $tmp,$src.hi
2913 emit_opcode(cbuf, 0x0B);
2914 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2915 %}
2916
2917 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2918 // CMP $src1.lo,$src2.lo
2919 emit_opcode( cbuf, 0x3B );
2920 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2921 // JNE,s skip
2922 emit_cc(cbuf, 0x70, 0x5);
2923 emit_d8(cbuf,2);
2924 // CMP $src1.hi,$src2.hi
2925 emit_opcode( cbuf, 0x3B );
2926 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2927 %}
2928
2929 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2930 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2931 emit_opcode( cbuf, 0x3B );
2932 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2933 // MOV $tmp,$src1.hi
2934 emit_opcode( cbuf, 0x8B );
2935 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2936 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2937 emit_opcode( cbuf, 0x1B );
2938 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2939 %}
2940
2941 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2942 // XOR $tmp,$tmp
2943 emit_opcode(cbuf,0x33); // XOR
2944 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2945 // CMP $tmp,$src.lo
2946 emit_opcode( cbuf, 0x3B );
2947 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2948 // SBB $tmp,$src.hi
2949 emit_opcode( cbuf, 0x1B );
2950 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2951 %}
2952
2953 // Sniff, sniff... smells like Gnu Superoptimizer
2954 enc_class neg_long( eRegL dst ) %{
2955 emit_opcode(cbuf,0xF7); // NEG hi
2956 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2957 emit_opcode(cbuf,0xF7); // NEG lo
2958 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2959 emit_opcode(cbuf,0x83); // SBB hi,0
2960 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2961 emit_d8 (cbuf,0 );
2962 %}
2963
2964
2965 // Because the transitions from emitted code to the runtime
2966 // monitorenter/exit helper stubs are so slow it's critical that
2967 // we inline both the stack-locking fast-path and the inflated fast path.
2968 //
2969 // See also: cmpFastLock and cmpFastUnlock.
2970 //
2971 // What follows is a specialized inline transliteration of the code
2972 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2973 // another option would be to emit TrySlowEnter and TrySlowExit methods
2974 // at startup-time. These methods would accept arguments as
2975 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2976 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2977 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2978 // In practice, however, the # of lock sites is bounded and is usually small.
2979 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2980 // if the processor uses simple bimodal branch predictors keyed by EIP
2981 // Since the helper routines would be called from multiple synchronization
2982 // sites.
2983 //
2984 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2985 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2986 // to those specialized methods. That'd give us a mostly platform-independent
2987 // implementation that the JITs could optimize and inline at their pleasure.
2988 // Done correctly, the only time we'd need to cross to native could would be
2989 // to park() or unpark() threads. We'd also need a few more unsafe operators
2990 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2991 // (b) explicit barriers or fence operations.
2992 //
2993 // TODO:
2994 //
2995 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2996 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2997 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2998 // the lock operators would typically be faster than reifying Self.
2999 //
3000 // * Ideally I'd define the primitives as:
3001 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3002 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3003 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3004 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3005 // Furthermore the register assignments are overconstrained, possibly resulting in
3006 // sub-optimal code near the synchronization site.
3007 //
3008 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3009 // Alternately, use a better sp-proximity test.
3010 //
3011 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3012 // Either one is sufficient to uniquely identify a thread.
3013 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3014 //
3015 // * Intrinsify notify() and notifyAll() for the common cases where the
3016 // object is locked by the calling thread but the waitlist is empty.
3017 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3018 //
3019 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3020 // But beware of excessive branch density on AMD Opterons.
3021 //
3022 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3023 // or failure of the fast-path. If the fast-path fails then we pass
3024 // control to the slow-path, typically in C. In Fast_Lock and
3025 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3026 // will emit a conditional branch immediately after the node.
3027 // So we have branches to branches and lots of ICC.ZF games.
3028 // Instead, it might be better to have C2 pass a "FailureLabel"
3029 // into Fast_Lock and Fast_Unlock. In the case of success, control
3030 // will drop through the node. ICC.ZF is undefined at exit.
3031 // In the case of failure, the node will branch directly to the
3032 // FailureLabel
3033
3034
3035 // obj: object to lock
3036 // box: on-stack box address (displaced header location) - KILLED
3037 // rax,: tmp -- KILLED
3038 // scr: tmp -- KILLED
3039 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3040
3041 Register objReg = as_Register($obj$$reg);
3042 Register boxReg = as_Register($box$$reg);
3043 Register tmpReg = as_Register($tmp$$reg);
3044 Register scrReg = as_Register($scr$$reg);
3045
3046 // Ensure the register assignents are disjoint
3047 guarantee (objReg != boxReg, "") ;
3048 guarantee (objReg != tmpReg, "") ;
3049 guarantee (objReg != scrReg, "") ;
3050 guarantee (boxReg != tmpReg, "") ;
3051 guarantee (boxReg != scrReg, "") ;
3052 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3053
3054 MacroAssembler masm(&cbuf);
3055
3056 if (_counters != NULL) {
3057 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3058 }
3059 if (EmitSync & 1) {
3060 // set box->dhw = unused_mark (3)
3061 // Force all sync thru slow-path: slow_enter() and slow_exit()
3062 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3063 masm.cmpptr (rsp, (int32_t)0) ;
3064 } else
3065 if (EmitSync & 2) {
3066 Label DONE_LABEL ;
3067 if (UseBiasedLocking) {
3068 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3069 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3070 }
3071
3072 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3073 masm.orptr (tmpReg, 0x1);
3074 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3075 if (os::is_MP()) { masm.lock(); }
3076 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3077 masm.jcc(Assembler::equal, DONE_LABEL);
3078 // Recursive locking
3079 masm.subptr(tmpReg, rsp);
3080 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3081 masm.movptr(Address(boxReg, 0), tmpReg);
3082 masm.bind(DONE_LABEL) ;
3083 } else {
3084 // Possible cases that we'll encounter in fast_lock
3085 // ------------------------------------------------
3086 // * Inflated
3087 // -- unlocked
3088 // -- Locked
3089 // = by self
3090 // = by other
3091 // * biased
3092 // -- by Self
3093 // -- by other
3094 // * neutral
3095 // * stack-locked
3096 // -- by self
3097 // = sp-proximity test hits
3098 // = sp-proximity test generates false-negative
3099 // -- by other
3100 //
3101
3102 Label IsInflated, DONE_LABEL, PopDone ;
3103
3104 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3105 // order to reduce the number of conditional branches in the most common cases.
3106 // Beware -- there's a subtle invariant that fetch of the markword
3107 // at [FETCH], below, will never observe a biased encoding (*101b).
3108 // If this invariant is not held we risk exclusion (safety) failure.
3109 if (UseBiasedLocking && !UseOptoBiasInlining) {
3110 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3111 }
3112
3113 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3114 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3115 masm.jccb (Assembler::notZero, IsInflated) ;
3116
3117 // Attempt stack-locking ...
3118 masm.orptr (tmpReg, 0x1);
3119 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3120 if (os::is_MP()) { masm.lock(); }
3121 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3122 if (_counters != NULL) {
3123 masm.cond_inc32(Assembler::equal,
3124 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3125 }
3126 masm.jccb (Assembler::equal, DONE_LABEL);
3127
3128 // Recursive locking
3129 masm.subptr(tmpReg, rsp);
3130 masm.andptr(tmpReg, 0xFFFFF003 );
3131 masm.movptr(Address(boxReg, 0), tmpReg);
3132 if (_counters != NULL) {
3133 masm.cond_inc32(Assembler::equal,
3134 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3135 }
3136 masm.jmp (DONE_LABEL) ;
3137
3138 masm.bind (IsInflated) ;
3139
3140 // The object is inflated.
3141 //
3142 // TODO-FIXME: eliminate the ugly use of manifest constants:
3143 // Use markOopDesc::monitor_value instead of "2".
3144 // use markOop::unused_mark() instead of "3".
3145 // The tmpReg value is an objectMonitor reference ORed with
3146 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3147 // objectmonitor pointer by masking off the "2" bit or we can just
3148 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3149 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3150 //
3151 // I use the latter as it avoids AGI stalls.
3152 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3153 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3154 //
3155 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3156
3157 // boxReg refers to the on-stack BasicLock in the current frame.
3158 // We'd like to write:
3159 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3160 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3161 // additional latency as we have another ST in the store buffer that must drain.
3162
3163 if (EmitSync & 8192) {
3164 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3165 masm.get_thread (scrReg) ;
3166 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3167 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3168 if (os::is_MP()) { masm.lock(); }
3169 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3170 } else
3171 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3172 masm.movptr(scrReg, boxReg) ;
3173 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3174
3175 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3176 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3177 // prefetchw [eax + Offset(_owner)-2]
3178 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3179 }
3180
3181 if ((EmitSync & 64) == 0) {
3182 // Optimistic form: consider XORL tmpReg,tmpReg
3183 masm.movptr(tmpReg, NULL_WORD) ;
3184 } else {
3185 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3186 // Test-And-CAS instead of CAS
3187 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3188 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3189 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3190 }
3191
3192 // Appears unlocked - try to swing _owner from null to non-null.
3193 // Ideally, I'd manifest "Self" with get_thread and then attempt
3194 // to CAS the register containing Self into m->Owner.
3195 // But we don't have enough registers, so instead we can either try to CAS
3196 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3197 // we later store "Self" into m->Owner. Transiently storing a stack address
3198 // (rsp or the address of the box) into m->owner is harmless.
3199 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3200 if (os::is_MP()) { masm.lock(); }
3201 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3202 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3203 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3204 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3205 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3206 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3207
3208 // If the CAS fails we can either retry or pass control to the slow-path.
3209 // We use the latter tactic.
3210 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3211 // If the CAS was successful ...
3212 // Self has acquired the lock
3213 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3214 // Intentional fall-through into DONE_LABEL ...
3215 } else {
3216 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3217 masm.movptr(boxReg, tmpReg) ;
3218
3219 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3220 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3221 // prefetchw [eax + Offset(_owner)-2]
3222 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3223 }
3224
3225 if ((EmitSync & 64) == 0) {
3226 // Optimistic form
3227 masm.xorptr (tmpReg, tmpReg) ;
3228 } else {
3229 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3230 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3231 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3232 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3233 }
3234
3235 // Appears unlocked - try to swing _owner from null to non-null.
3236 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3237 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3238 masm.get_thread (scrReg) ;
3239 if (os::is_MP()) { masm.lock(); }
3240 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3241
3242 // If the CAS fails we can either retry or pass control to the slow-path.
3243 // We use the latter tactic.
3244 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3245 // If the CAS was successful ...
3246 // Self has acquired the lock
3247 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3248 // Intentional fall-through into DONE_LABEL ...
3249 }
3250
3251 // DONE_LABEL is a hot target - we'd really like to place it at the
3252 // start of cache line by padding with NOPs.
3253 // See the AMD and Intel software optimization manuals for the
3254 // most efficient "long" NOP encodings.
3255 // Unfortunately none of our alignment mechanisms suffice.
3256 masm.bind(DONE_LABEL);
3257
3258 // Avoid branch-to-branch on AMD processors
3259 // This appears to be superstition.
3260 if (EmitSync & 32) masm.nop() ;
3261
3262
3263 // At DONE_LABEL the icc ZFlag is set as follows ...
3264 // Fast_Unlock uses the same protocol.
3265 // ZFlag == 1 -> Success
3266 // ZFlag == 0 -> Failure - force control through the slow-path
3267 }
3268 %}
3269
3270 // obj: object to unlock
3271 // box: box address (displaced header location), killed. Must be EAX.
3272 // rbx,: killed tmp; cannot be obj nor box.
3273 //
3274 // Some commentary on balanced locking:
3275 //
3276 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3277 // Methods that don't have provably balanced locking are forced to run in the
3278 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3279 // The interpreter provides two properties:
3280 // I1: At return-time the interpreter automatically and quietly unlocks any
3281 // objects acquired the current activation (frame). Recall that the
3282 // interpreter maintains an on-stack list of locks currently held by
3283 // a frame.
3284 // I2: If a method attempts to unlock an object that is not held by the
3285 // the frame the interpreter throws IMSX.
3286 //
3287 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3288 // B() doesn't have provably balanced locking so it runs in the interpreter.
3289 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3290 // is still locked by A().
3291 //
3292 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3293 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3294 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3295 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3296
3297 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3298
3299 Register objReg = as_Register($obj$$reg);
3300 Register boxReg = as_Register($box$$reg);
3301 Register tmpReg = as_Register($tmp$$reg);
3302
3303 guarantee (objReg != boxReg, "") ;
3304 guarantee (objReg != tmpReg, "") ;
3305 guarantee (boxReg != tmpReg, "") ;
3306 guarantee (boxReg == as_Register(EAX_enc), "") ;
3307 MacroAssembler masm(&cbuf);
3308
3309 if (EmitSync & 4) {
3310 // Disable - inhibit all inlining. Force control through the slow-path
3311 masm.cmpptr (rsp, 0) ;
3312 } else
3313 if (EmitSync & 8) {
3314 Label DONE_LABEL ;
3315 if (UseBiasedLocking) {
3316 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3317 }
3318 // classic stack-locking code ...
3319 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3320 masm.testptr(tmpReg, tmpReg) ;
3321 masm.jcc (Assembler::zero, DONE_LABEL) ;
3322 if (os::is_MP()) { masm.lock(); }
3323 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3324 masm.bind(DONE_LABEL);
3325 } else {
3326 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3327
3328 // Critically, the biased locking test must have precedence over
3329 // and appear before the (box->dhw == 0) recursive stack-lock test.
3330 if (UseBiasedLocking && !UseOptoBiasInlining) {
3331 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3332 }
3333
3334 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3335 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3336 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3337
3338 masm.testptr(tmpReg, 0x02) ; // Inflated?
3339 masm.jccb (Assembler::zero, Stacked) ;
3340
3341 masm.bind (Inflated) ;
3342 // It's inflated.
3343 // Despite our balanced locking property we still check that m->_owner == Self
3344 // as java routines or native JNI code called by this thread might
3345 // have released the lock.
3346 // Refer to the comments in synchronizer.cpp for how we might encode extra
3347 // state in _succ so we can avoid fetching EntryList|cxq.
3348 //
3349 // I'd like to add more cases in fast_lock() and fast_unlock() --
3350 // such as recursive enter and exit -- but we have to be wary of
3351 // I$ bloat, T$ effects and BP$ effects.
3352 //
3353 // If there's no contention try a 1-0 exit. That is, exit without
3354 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3355 // we detect and recover from the race that the 1-0 exit admits.
3356 //
3357 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3358 // before it STs null into _owner, releasing the lock. Updates
3359 // to data protected by the critical section must be visible before
3360 // we drop the lock (and thus before any other thread could acquire
3361 // the lock and observe the fields protected by the lock).
3362 // IA32's memory-model is SPO, so STs are ordered with respect to
3363 // each other and there's no need for an explicit barrier (fence).
3364 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3365
3366 masm.get_thread (boxReg) ;
3367 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3368 // prefetchw [ebx + Offset(_owner)-2]
3369 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3370 }
3371
3372 // Note that we could employ various encoding schemes to reduce
3373 // the number of loads below (currently 4) to just 2 or 3.
3374 // Refer to the comments in synchronizer.cpp.
3375 // In practice the chain of fetches doesn't seem to impact performance, however.
3376 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3377 // Attempt to reduce branch density - AMD's branch predictor.
3378 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3379 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3380 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3381 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3382 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3383 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3384 masm.jmpb (DONE_LABEL) ;
3385 } else {
3386 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3387 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3388 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3389 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3390 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3391 masm.jccb (Assembler::notZero, CheckSucc) ;
3392 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3393 masm.jmpb (DONE_LABEL) ;
3394 }
3395
3396 // The Following code fragment (EmitSync & 65536) improves the performance of
3397 // contended applications and contended synchronization microbenchmarks.
3398 // Unfortunately the emission of the code - even though not executed - causes regressions
3399 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3400 // with an equal number of never-executed NOPs results in the same regression.
3401 // We leave it off by default.
3402
3403 if ((EmitSync & 65536) != 0) {
3404 Label LSuccess, LGoSlowPath ;
3405
3406 masm.bind (CheckSucc) ;
3407
3408 // Optional pre-test ... it's safe to elide this
3409 if ((EmitSync & 16) == 0) {
3410 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3411 masm.jccb (Assembler::zero, LGoSlowPath) ;
3412 }
3413
3414 // We have a classic Dekker-style idiom:
3415 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3416 // There are a number of ways to implement the barrier:
3417 // (1) lock:andl &m->_owner, 0
3418 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3419 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3420 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3421 // (2) If supported, an explicit MFENCE is appealing.
3422 // In older IA32 processors MFENCE is slower than lock:add or xchg
3423 // particularly if the write-buffer is full as might be the case if
3424 // if stores closely precede the fence or fence-equivalent instruction.
3425 // In more modern implementations MFENCE appears faster, however.
3426 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3427 // The $lines underlying the top-of-stack should be in M-state.
3428 // The locked add instruction is serializing, of course.
3429 // (4) Use xchg, which is serializing
3430 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3431 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3432 // The integer condition codes will tell us if succ was 0.
3433 // Since _succ and _owner should reside in the same $line and
3434 // we just stored into _owner, it's likely that the $line
3435 // remains in M-state for the lock:orl.
3436 //
3437 // We currently use (3), although it's likely that switching to (2)
3438 // is correct for the future.
3439
3440 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3441 if (os::is_MP()) {
3442 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3443 masm.mfence();
3444 } else {
3445 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3446 }
3447 }
3448 // Ratify _succ remains non-null
3449 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3450 masm.jccb (Assembler::notZero, LSuccess) ;
3451
3452 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3453 if (os::is_MP()) { masm.lock(); }
3454 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3455 masm.jccb (Assembler::notEqual, LSuccess) ;
3456 // Since we're low on registers we installed rsp as a placeholding in _owner.
3457 // Now install Self over rsp. This is safe as we're transitioning from
3458 // non-null to non=null
3459 masm.get_thread (boxReg) ;
3460 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3461 // Intentional fall-through into LGoSlowPath ...
3462
3463 masm.bind (LGoSlowPath) ;
3464 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3465 masm.jmpb (DONE_LABEL) ;
3466
3467 masm.bind (LSuccess) ;
3468 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3469 masm.jmpb (DONE_LABEL) ;
3470 }
3471
3472 masm.bind (Stacked) ;
3473 // It's not inflated and it's not recursively stack-locked and it's not biased.
3474 // It must be stack-locked.
3475 // Try to reset the header to displaced header.
3476 // The "box" value on the stack is stable, so we can reload
3477 // and be assured we observe the same value as above.
3478 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3479 if (os::is_MP()) { masm.lock(); }
3480 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3481 // Intention fall-thru into DONE_LABEL
3482
3483
3484 // DONE_LABEL is a hot target - we'd really like to place it at the
3485 // start of cache line by padding with NOPs.
3486 // See the AMD and Intel software optimization manuals for the
3487 // most efficient "long" NOP encodings.
3488 // Unfortunately none of our alignment mechanisms suffice.
3489 if ((EmitSync & 65536) == 0) {
3490 masm.bind (CheckSucc) ;
3491 }
3492 masm.bind(DONE_LABEL);
3493
3494 // Avoid branch to branch on AMD processors
3495 if (EmitSync & 32768) { masm.nop() ; }
3496 }
3497 %}
3498
3499
3500 enc_class enc_pop_rdx() %{
3501 emit_opcode(cbuf,0x5A);
3502 %}
3503
3504 enc_class enc_rethrow() %{
3505 cbuf.set_insts_mark();
3506 emit_opcode(cbuf, 0xE9); // jmp entry
3507 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3508 runtime_call_Relocation::spec(), RELOC_IMM32 );
3509 %}
3510
3511
3512 // Convert a double to an int. Java semantics require we do complex
3513 // manglelations in the corner cases. So we set the rounding mode to
3514 // 'zero', store the darned double down as an int, and reset the
3515 // rounding mode to 'nearest'. The hardware throws an exception which
3516 // patches up the correct value directly to the stack.
3517 enc_class DPR2I_encoding( regDPR src ) %{
3518 // Flip to round-to-zero mode. We attempted to allow invalid-op
3519 // exceptions here, so that a NAN or other corner-case value will
3520 // thrown an exception (but normal values get converted at full speed).
3521 // However, I2C adapters and other float-stack manglers leave pending
3522 // invalid-op exceptions hanging. We would have to clear them before
3523 // enabling them and that is more expensive than just testing for the
3524 // invalid value Intel stores down in the corner cases.
3525 emit_opcode(cbuf,0xD9); // FLDCW trunc
3526 emit_opcode(cbuf,0x2D);
3527 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3528 // Allocate a word
3529 emit_opcode(cbuf,0x83); // SUB ESP,4
3530 emit_opcode(cbuf,0xEC);
3531 emit_d8(cbuf,0x04);
3532 // Encoding assumes a double has been pushed into FPR0.
3533 // Store down the double as an int, popping the FPU stack
3534 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3535 emit_opcode(cbuf,0x1C);
3536 emit_d8(cbuf,0x24);
3537 // Restore the rounding mode; mask the exception
3538 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3539 emit_opcode(cbuf,0x2D);
3540 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3541 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3542 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3543
3544 // Load the converted int; adjust CPU stack
3545 emit_opcode(cbuf,0x58); // POP EAX
3546 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3547 emit_d32 (cbuf,0x80000000); // 0x80000000
3548 emit_opcode(cbuf,0x75); // JNE around_slow_call
3549 emit_d8 (cbuf,0x07); // Size of slow_call
3550 // Push src onto stack slow-path
3551 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3552 emit_d8 (cbuf,0xC0-1+$src$$reg );
3553 // CALL directly to the runtime
3554 cbuf.set_insts_mark();
3555 emit_opcode(cbuf,0xE8); // Call into runtime
3556 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3557 // Carry on here...
3558 %}
3559
3560 enc_class DPR2L_encoding( regDPR src ) %{
3561 emit_opcode(cbuf,0xD9); // FLDCW trunc
3562 emit_opcode(cbuf,0x2D);
3563 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3564 // Allocate a word
3565 emit_opcode(cbuf,0x83); // SUB ESP,8
3566 emit_opcode(cbuf,0xEC);
3567 emit_d8(cbuf,0x08);
3568 // Encoding assumes a double has been pushed into FPR0.
3569 // Store down the double as a long, popping the FPU stack
3570 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3571 emit_opcode(cbuf,0x3C);
3572 emit_d8(cbuf,0x24);
3573 // Restore the rounding mode; mask the exception
3574 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3575 emit_opcode(cbuf,0x2D);
3576 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3577 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3578 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3579
3580 // Load the converted int; adjust CPU stack
3581 emit_opcode(cbuf,0x58); // POP EAX
3582 emit_opcode(cbuf,0x5A); // POP EDX
3583 emit_opcode(cbuf,0x81); // CMP EDX,imm
3584 emit_d8 (cbuf,0xFA); // rdx
3585 emit_d32 (cbuf,0x80000000); // 0x80000000
3586 emit_opcode(cbuf,0x75); // JNE around_slow_call
3587 emit_d8 (cbuf,0x07+4); // Size of slow_call
3588 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3589 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3590 emit_opcode(cbuf,0x75); // JNE around_slow_call
3591 emit_d8 (cbuf,0x07); // Size of slow_call
3592 // Push src onto stack slow-path
3593 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3594 emit_d8 (cbuf,0xC0-1+$src$$reg );
3595 // CALL directly to the runtime
3596 cbuf.set_insts_mark();
3597 emit_opcode(cbuf,0xE8); // Call into runtime
3598 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3599 // Carry on here...
3600 %}
3601
3602 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3603 // Operand was loaded from memory into fp ST (stack top)
3604 // FMUL ST,$src /* D8 C8+i */
3605 emit_opcode(cbuf, 0xD8);
3606 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3607 %}
3608
3609 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3610 // FADDP ST,src2 /* D8 C0+i */
3611 emit_opcode(cbuf, 0xD8);
3612 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3613 //could use FADDP src2,fpST /* DE C0+i */
3614 %}
3615
3616 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3617 // FADDP src2,ST /* DE C0+i */
3618 emit_opcode(cbuf, 0xDE);
3619 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3620 %}
3621
3622 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3623 // Operand has been loaded into fp ST (stack top)
3624 // FSUB ST,$src1
3625 emit_opcode(cbuf, 0xD8);
3626 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3627
3628 // FDIV
3629 emit_opcode(cbuf, 0xD8);
3630 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3631 %}
3632
3633 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3634 // Operand was loaded from memory into fp ST (stack top)
3635 // FADD ST,$src /* D8 C0+i */
3636 emit_opcode(cbuf, 0xD8);
3637 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3638
3639 // FMUL ST,src2 /* D8 C*+i */
3640 emit_opcode(cbuf, 0xD8);
3641 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3642 %}
3643
3644
3645 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3646 // Operand was loaded from memory into fp ST (stack top)
3647 // FADD ST,$src /* D8 C0+i */
3648 emit_opcode(cbuf, 0xD8);
3649 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3650
3651 // FMULP src2,ST /* DE C8+i */
3652 emit_opcode(cbuf, 0xDE);
3653 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3654 %}
3655
3656 // Atomically load the volatile long
3657 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3658 emit_opcode(cbuf,0xDF);
3659 int rm_byte_opcode = 0x05;
3660 int base = $mem$$base;
3661 int index = $mem$$index;
3662 int scale = $mem$$scale;
3663 int displace = $mem$$disp;
3664 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3665 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3666 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3667 %}
3668
3669 // Volatile Store Long. Must be atomic, so move it into
3670 // the FP TOS and then do a 64-bit FIST. Has to probe the
3671 // target address before the store (for null-ptr checks)
3672 // so the memory operand is used twice in the encoding.
3673 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3674 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3675 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3676 emit_opcode(cbuf,0xDF);
3677 int rm_byte_opcode = 0x07;
3678 int base = $mem$$base;
3679 int index = $mem$$index;
3680 int scale = $mem$$scale;
3681 int displace = $mem$$disp;
3682 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3683 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3684 %}
3685
3686 // Safepoint Poll. This polls the safepoint page, and causes an
3687 // exception if it is not readable. Unfortunately, it kills the condition code
3688 // in the process
3689 // We current use TESTL [spp],EDI
3690 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3691
3692 enc_class Safepoint_Poll() %{
3693 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3694 emit_opcode(cbuf,0x85);
3695 emit_rm (cbuf, 0x0, 0x7, 0x5);
3696 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3697 %}
3698 %}
3699
3700
3701 //----------FRAME--------------------------------------------------------------
3702 // Definition of frame structure and management information.
3703 //
3704 // S T A C K L A Y O U T Allocators stack-slot number
3705 // | (to get allocators register number
3706 // G Owned by | | v add OptoReg::stack0())
3707 // r CALLER | |
3708 // o | +--------+ pad to even-align allocators stack-slot
3709 // w V | pad0 | numbers; owned by CALLER
3710 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3711 // h ^ | in | 5
3712 // | | args | 4 Holes in incoming args owned by SELF
3713 // | | | | 3
3714 // | | +--------+
3715 // V | | old out| Empty on Intel, window on Sparc
3716 // | old |preserve| Must be even aligned.
3717 // | SP-+--------+----> Matcher::_old_SP, even aligned
3718 // | | in | 3 area for Intel ret address
3719 // Owned by |preserve| Empty on Sparc.
3720 // SELF +--------+
3721 // | | pad2 | 2 pad to align old SP
3722 // | +--------+ 1
3723 // | | locks | 0
3724 // | +--------+----> OptoReg::stack0(), even aligned
3725 // | | pad1 | 11 pad to align new SP
3726 // | +--------+
3727 // | | | 10
3728 // | | spills | 9 spills
3729 // V | | 8 (pad0 slot for callee)
3730 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3731 // ^ | out | 7
3732 // | | args | 6 Holes in outgoing args owned by CALLEE
3733 // Owned by +--------+
3734 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3735 // | new |preserve| Must be even-aligned.
3736 // | SP-+--------+----> Matcher::_new_SP, even aligned
3737 // | | |
3738 //
3739 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3740 // known from SELF's arguments and the Java calling convention.
3741 // Region 6-7 is determined per call site.
3742 // Note 2: If the calling convention leaves holes in the incoming argument
3743 // area, those holes are owned by SELF. Holes in the outgoing area
3744 // are owned by the CALLEE. Holes should not be nessecary in the
3745 // incoming area, as the Java calling convention is completely under
3746 // the control of the AD file. Doubles can be sorted and packed to
3747 // avoid holes. Holes in the outgoing arguments may be nessecary for
3748 // varargs C calling conventions.
3749 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3750 // even aligned with pad0 as needed.
3751 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3752 // region 6-11 is even aligned; it may be padded out more so that
3753 // the region from SP to FP meets the minimum stack alignment.
3754
3755 frame %{
3756 // What direction does stack grow in (assumed to be same for C & Java)
3757 stack_direction(TOWARDS_LOW);
3758
3759 // These three registers define part of the calling convention
3760 // between compiled code and the interpreter.
3761 inline_cache_reg(EAX); // Inline Cache Register
3762 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3763
3764 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3765 cisc_spilling_operand_name(indOffset32);
3766
3767 // Number of stack slots consumed by locking an object
3768 sync_stack_slots(1);
3769
3770 // Compiled code's Frame Pointer
3771 frame_pointer(ESP);
3772 // Interpreter stores its frame pointer in a register which is
3773 // stored to the stack by I2CAdaptors.
3774 // I2CAdaptors convert from interpreted java to compiled java.
3775 interpreter_frame_pointer(EBP);
3776
3777 // Stack alignment requirement
3778 // Alignment size in bytes (128-bit -> 16 bytes)
3779 stack_alignment(StackAlignmentInBytes);
3780
3781 // Number of stack slots between incoming argument block and the start of
3782 // a new frame. The PROLOG must add this many slots to the stack. The
3783 // EPILOG must remove this many slots. Intel needs one slot for
3784 // return address and one for rbp, (must save rbp)
3785 in_preserve_stack_slots(2+VerifyStackAtCalls);
3786
3787 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3788 // for calls to C. Supports the var-args backing area for register parms.
3789 varargs_C_out_slots_killed(0);
3790
3791 // The after-PROLOG location of the return address. Location of
3792 // return address specifies a type (REG or STACK) and a number
3793 // representing the register number (i.e. - use a register name) or
3794 // stack slot.
3795 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3796 // Otherwise, it is above the locks and verification slot and alignment word
3797 return_addr(STACK - 1 +
3798 round_to((Compile::current()->in_preserve_stack_slots() +
3799 Compile::current()->fixed_slots()),
3800 stack_alignment_in_slots()));
3801
3802 // Body of function which returns an integer array locating
3803 // arguments either in registers or in stack slots. Passed an array
3804 // of ideal registers called "sig" and a "length" count. Stack-slot
3805 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3806 // arguments for a CALLEE. Incoming stack arguments are
3807 // automatically biased by the preserve_stack_slots field above.
3808 calling_convention %{
3809 // No difference between ingoing/outgoing just pass false
3810 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3811 %}
3812
3813
3814 // Body of function which returns an integer array locating
3815 // arguments either in registers or in stack slots. Passed an array
3816 // of ideal registers called "sig" and a "length" count. Stack-slot
3817 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3818 // arguments for a CALLEE. Incoming stack arguments are
3819 // automatically biased by the preserve_stack_slots field above.
3820 c_calling_convention %{
3821 // This is obviously always outgoing
3822 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3823 %}
3824
3825 // Location of C & interpreter return values
3826 c_return_value %{
3827 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3828 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3829 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3830
3831 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3832 // that C functions return float and double results in XMM0.
3833 if( ideal_reg == Op_RegD && UseSSE>=2 )
3834 return OptoRegPair(XMM0b_num,XMM0_num);
3835 if( ideal_reg == Op_RegF && UseSSE>=2 )
3836 return OptoRegPair(OptoReg::Bad,XMM0_num);
3837
3838 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3839 %}
3840
3841 // Location of return values
3842 return_value %{
3843 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3844 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3845 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3846 if( ideal_reg == Op_RegD && UseSSE>=2 )
3847 return OptoRegPair(XMM0b_num,XMM0_num);
3848 if( ideal_reg == Op_RegF && UseSSE>=1 )
3849 return OptoRegPair(OptoReg::Bad,XMM0_num);
3850 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3851 %}
3852
3853 %}
3854
3855 //----------ATTRIBUTES---------------------------------------------------------
3856 //----------Operand Attributes-------------------------------------------------
3857 op_attrib op_cost(0); // Required cost attribute
3858
3859 //----------Instruction Attributes---------------------------------------------
3860 ins_attrib ins_cost(100); // Required cost attribute
3861 ins_attrib ins_size(8); // Required size attribute (in bits)
3862 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3863 // non-matching short branch variant of some
3864 // long branch?
3865 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3866 // specifies the alignment that some part of the instruction (not
3867 // necessarily the start) requires. If > 1, a compute_padding()
3868 // function must be provided for the instruction
3869
3870 //----------OPERANDS-----------------------------------------------------------
3871 // Operand definitions must precede instruction definitions for correct parsing
3872 // in the ADLC because operands constitute user defined types which are used in
3873 // instruction definitions.
3874
3875 //----------Simple Operands----------------------------------------------------
3876 // Immediate Operands
3877 // Integer Immediate
3878 operand immI() %{
3879 match(ConI);
3880
3881 op_cost(10);
3882 format %{ %}
3883 interface(CONST_INTER);
3884 %}
3885
3886 // Constant for test vs zero
3887 operand immI0() %{
3888 predicate(n->get_int() == 0);
3889 match(ConI);
3890
3891 op_cost(0);
3892 format %{ %}
3893 interface(CONST_INTER);
3894 %}
3895
3896 // Constant for increment
3897 operand immI1() %{
3898 predicate(n->get_int() == 1);
3899 match(ConI);
3900
3901 op_cost(0);
3902 format %{ %}
3903 interface(CONST_INTER);
3904 %}
3905
3906 // Constant for decrement
3907 operand immI_M1() %{
3908 predicate(n->get_int() == -1);
3909 match(ConI);
3910
3911 op_cost(0);
3912 format %{ %}
3913 interface(CONST_INTER);
3914 %}
3915
3916 // Valid scale values for addressing modes
3917 operand immI2() %{
3918 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3919 match(ConI);
3920
3921 format %{ %}
3922 interface(CONST_INTER);
3923 %}
3924
3925 operand immI8() %{
3926 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3927 match(ConI);
3928
3929 op_cost(5);
3930 format %{ %}
3931 interface(CONST_INTER);
3932 %}
3933
3934 operand immI16() %{
3935 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3936 match(ConI);
3937
3938 op_cost(10);
3939 format %{ %}
3940 interface(CONST_INTER);
3941 %}
3942
3943 // Constant for long shifts
3944 operand immI_32() %{
3945 predicate( n->get_int() == 32 );
3946 match(ConI);
3947
3948 op_cost(0);
3949 format %{ %}
3950 interface(CONST_INTER);
3951 %}
3952
3953 operand immI_1_31() %{
3954 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3955 match(ConI);
3956
3957 op_cost(0);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3961
3962 operand immI_32_63() %{
3963 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3964 match(ConI);
3965 op_cost(0);
3966
3967 format %{ %}
3968 interface(CONST_INTER);
3969 %}
3970
3971 operand immI_1() %{
3972 predicate( n->get_int() == 1 );
3973 match(ConI);
3974
3975 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3979
3980 operand immI_2() %{
3981 predicate( n->get_int() == 2 );
3982 match(ConI);
3983
3984 op_cost(0);
3985 format %{ %}
3986 interface(CONST_INTER);
3987 %}
3988
3989 operand immI_3() %{
3990 predicate( n->get_int() == 3 );
3991 match(ConI);
3992
3993 op_cost(0);
3994 format %{ %}
3995 interface(CONST_INTER);
3996 %}
3997
3998 // Pointer Immediate
3999 operand immP() %{
4000 match(ConP);
4001
4002 op_cost(10);
4003 format %{ %}
4004 interface(CONST_INTER);
4005 %}
4006
4007 // NULL Pointer Immediate
4008 operand immP0() %{
4009 predicate( n->get_ptr() == 0 );
4010 match(ConP);
4011 op_cost(0);
4012
4013 format %{ %}
4014 interface(CONST_INTER);
4015 %}
4016
4017 // Long Immediate
4018 operand immL() %{
4019 match(ConL);
4020
4021 op_cost(20);
4022 format %{ %}
4023 interface(CONST_INTER);
4024 %}
4025
4026 // Long Immediate zero
4027 operand immL0() %{
4028 predicate( n->get_long() == 0L );
4029 match(ConL);
4030 op_cost(0);
4031
4032 format %{ %}
4033 interface(CONST_INTER);
4034 %}
4035
4036 // Long Immediate zero
4037 operand immL_M1() %{
4038 predicate( n->get_long() == -1L );
4039 match(ConL);
4040 op_cost(0);
4041
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4045
4046 // Long immediate from 0 to 127.
4047 // Used for a shorter form of long mul by 10.
4048 operand immL_127() %{
4049 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4050 match(ConL);
4051 op_cost(0);
4052
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 // Long Immediate: low 32-bit mask
4058 operand immL_32bits() %{
4059 predicate(n->get_long() == 0xFFFFFFFFL);
4060 match(ConL);
4061 op_cost(0);
4062
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4066
4067 // Long Immediate: low 32-bit mask
4068 operand immL32() %{
4069 predicate(n->get_long() == (int)(n->get_long()));
4070 match(ConL);
4071 op_cost(20);
4072
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 //Double Immediate zero
4078 operand immDPR0() %{
4079 // Do additional (and counter-intuitive) test against NaN to work around VC++
4080 // bug that generates code such that NaNs compare equal to 0.0
4081 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4082 match(ConD);
4083
4084 op_cost(5);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4088
4089 // Double Immediate one
4090 operand immDPR1() %{
4091 predicate( UseSSE<=1 && n->getd() == 1.0 );
4092 match(ConD);
4093
4094 op_cost(5);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4098
4099 // Double Immediate
4100 operand immDPR() %{
4101 predicate(UseSSE<=1);
4102 match(ConD);
4103
4104 op_cost(5);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4108
4109 operand immD() %{
4110 predicate(UseSSE>=2);
4111 match(ConD);
4112
4113 op_cost(5);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4117
4118 // Double Immediate zero
4119 operand immD0() %{
4120 // Do additional (and counter-intuitive) test against NaN to work around VC++
4121 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4122 // compare equal to -0.0.
4123 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4124 match(ConD);
4125
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 // Float Immediate zero
4131 operand immFPR0() %{
4132 predicate(UseSSE == 0 && n->getf() == 0.0F);
4133 match(ConF);
4134
4135 op_cost(5);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Float Immediate one
4141 operand immFPR1() %{
4142 predicate(UseSSE == 0 && n->getf() == 1.0F);
4143 match(ConF);
4144
4145 op_cost(5);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4149
4150 // Float Immediate
4151 operand immFPR() %{
4152 predicate( UseSSE == 0 );
4153 match(ConF);
4154
4155 op_cost(5);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // Float Immediate
4161 operand immF() %{
4162 predicate(UseSSE >= 1);
4163 match(ConF);
4164
4165 op_cost(5);
4166 format %{ %}
4167 interface(CONST_INTER);
4168 %}
4169
4170 // Float Immediate zero. Zero and not -0.0
4171 operand immF0() %{
4172 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4173 match(ConF);
4174
4175 op_cost(5);
4176 format %{ %}
4177 interface(CONST_INTER);
4178 %}
4179
4180 // Immediates for special shifts (sign extend)
4181
4182 // Constants for increment
4183 operand immI_16() %{
4184 predicate( n->get_int() == 16 );
4185 match(ConI);
4186
4187 format %{ %}
4188 interface(CONST_INTER);
4189 %}
4190
4191 operand immI_24() %{
4192 predicate( n->get_int() == 24 );
4193 match(ConI);
4194
4195 format %{ %}
4196 interface(CONST_INTER);
4197 %}
4198
4199 // Constant for byte-wide masking
4200 operand immI_255() %{
4201 predicate( n->get_int() == 255 );
4202 match(ConI);
4203
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4207
4208 // Constant for short-wide masking
4209 operand immI_65535() %{
4210 predicate(n->get_int() == 65535);
4211 match(ConI);
4212
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4216
4217 // Register Operands
4218 // Integer Register
4219 operand rRegI() %{
4220 constraint(ALLOC_IN_RC(int_reg));
4221 match(RegI);
4222 match(xRegI);
4223 match(eAXRegI);
4224 match(eBXRegI);
4225 match(eCXRegI);
4226 match(eDXRegI);
4227 match(eDIRegI);
4228 match(eSIRegI);
4229
4230 format %{ %}
4231 interface(REG_INTER);
4232 %}
4233
4234 // Subset of Integer Register
4235 operand xRegI(rRegI reg) %{
4236 constraint(ALLOC_IN_RC(int_x_reg));
4237 match(reg);
4238 match(eAXRegI);
4239 match(eBXRegI);
4240 match(eCXRegI);
4241 match(eDXRegI);
4242
4243 format %{ %}
4244 interface(REG_INTER);
4245 %}
4246
4247 // Special Registers
4248 operand eAXRegI(xRegI reg) %{
4249 constraint(ALLOC_IN_RC(eax_reg));
4250 match(reg);
4251 match(rRegI);
4252
4253 format %{ "EAX" %}
4254 interface(REG_INTER);
4255 %}
4256
4257 // Special Registers
4258 operand eBXRegI(xRegI reg) %{
4259 constraint(ALLOC_IN_RC(ebx_reg));
4260 match(reg);
4261 match(rRegI);
4262
4263 format %{ "EBX" %}
4264 interface(REG_INTER);
4265 %}
4266
4267 operand eCXRegI(xRegI reg) %{
4268 constraint(ALLOC_IN_RC(ecx_reg));
4269 match(reg);
4270 match(rRegI);
4271
4272 format %{ "ECX" %}
4273 interface(REG_INTER);
4274 %}
4275
4276 operand eDXRegI(xRegI reg) %{
4277 constraint(ALLOC_IN_RC(edx_reg));
4278 match(reg);
4279 match(rRegI);
4280
4281 format %{ "EDX" %}
4282 interface(REG_INTER);
4283 %}
4284
4285 operand eDIRegI(xRegI reg) %{
4286 constraint(ALLOC_IN_RC(edi_reg));
4287 match(reg);
4288 match(rRegI);
4289
4290 format %{ "EDI" %}
4291 interface(REG_INTER);
4292 %}
4293
4294 operand naxRegI() %{
4295 constraint(ALLOC_IN_RC(nax_reg));
4296 match(RegI);
4297 match(eCXRegI);
4298 match(eDXRegI);
4299 match(eSIRegI);
4300 match(eDIRegI);
4301
4302 format %{ %}
4303 interface(REG_INTER);
4304 %}
4305
4306 operand nadxRegI() %{
4307 constraint(ALLOC_IN_RC(nadx_reg));
4308 match(RegI);
4309 match(eBXRegI);
4310 match(eCXRegI);
4311 match(eSIRegI);
4312 match(eDIRegI);
4313
4314 format %{ %}
4315 interface(REG_INTER);
4316 %}
4317
4318 operand ncxRegI() %{
4319 constraint(ALLOC_IN_RC(ncx_reg));
4320 match(RegI);
4321 match(eAXRegI);
4322 match(eDXRegI);
4323 match(eSIRegI);
4324 match(eDIRegI);
4325
4326 format %{ %}
4327 interface(REG_INTER);
4328 %}
4329
4330 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4331 // //
4332 operand eSIRegI(xRegI reg) %{
4333 constraint(ALLOC_IN_RC(esi_reg));
4334 match(reg);
4335 match(rRegI);
4336
4337 format %{ "ESI" %}
4338 interface(REG_INTER);
4339 %}
4340
4341 // Pointer Register
4342 operand anyRegP() %{
4343 constraint(ALLOC_IN_RC(any_reg));
4344 match(RegP);
4345 match(eAXRegP);
4346 match(eBXRegP);
4347 match(eCXRegP);
4348 match(eDIRegP);
4349 match(eRegP);
4350
4351 format %{ %}
4352 interface(REG_INTER);
4353 %}
4354
4355 operand eRegP() %{
4356 constraint(ALLOC_IN_RC(int_reg));
4357 match(RegP);
4358 match(eAXRegP);
4359 match(eBXRegP);
4360 match(eCXRegP);
4361 match(eDIRegP);
4362
4363 format %{ %}
4364 interface(REG_INTER);
4365 %}
4366
4367 // On windows95, EBP is not safe to use for implicit null tests.
4368 operand eRegP_no_EBP() %{
4369 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4370 match(RegP);
4371 match(eAXRegP);
4372 match(eBXRegP);
4373 match(eCXRegP);
4374 match(eDIRegP);
4375
4376 op_cost(100);
4377 format %{ %}
4378 interface(REG_INTER);
4379 %}
4380
4381 operand naxRegP() %{
4382 constraint(ALLOC_IN_RC(nax_reg));
4383 match(RegP);
4384 match(eBXRegP);
4385 match(eDXRegP);
4386 match(eCXRegP);
4387 match(eSIRegP);
4388 match(eDIRegP);
4389
4390 format %{ %}
4391 interface(REG_INTER);
4392 %}
4393
4394 operand nabxRegP() %{
4395 constraint(ALLOC_IN_RC(nabx_reg));
4396 match(RegP);
4397 match(eCXRegP);
4398 match(eDXRegP);
4399 match(eSIRegP);
4400 match(eDIRegP);
4401
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4405
4406 operand pRegP() %{
4407 constraint(ALLOC_IN_RC(p_reg));
4408 match(RegP);
4409 match(eBXRegP);
4410 match(eDXRegP);
4411 match(eSIRegP);
4412 match(eDIRegP);
4413
4414 format %{ %}
4415 interface(REG_INTER);
4416 %}
4417
4418 // Special Registers
4419 // Return a pointer value
4420 operand eAXRegP(eRegP reg) %{
4421 constraint(ALLOC_IN_RC(eax_reg));
4422 match(reg);
4423 format %{ "EAX" %}
4424 interface(REG_INTER);
4425 %}
4426
4427 // Used in AtomicAdd
4428 operand eBXRegP(eRegP reg) %{
4429 constraint(ALLOC_IN_RC(ebx_reg));
4430 match(reg);
4431 format %{ "EBX" %}
4432 interface(REG_INTER);
4433 %}
4434
4435 // Tail-call (interprocedural jump) to interpreter
4436 operand eCXRegP(eRegP reg) %{
4437 constraint(ALLOC_IN_RC(ecx_reg));
4438 match(reg);
4439 format %{ "ECX" %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand eSIRegP(eRegP reg) %{
4444 constraint(ALLOC_IN_RC(esi_reg));
4445 match(reg);
4446 format %{ "ESI" %}
4447 interface(REG_INTER);
4448 %}
4449
4450 // Used in rep stosw
4451 operand eDIRegP(eRegP reg) %{
4452 constraint(ALLOC_IN_RC(edi_reg));
4453 match(reg);
4454 format %{ "EDI" %}
4455 interface(REG_INTER);
4456 %}
4457
4458 operand eBPRegP() %{
4459 constraint(ALLOC_IN_RC(ebp_reg));
4460 match(RegP);
4461 format %{ "EBP" %}
4462 interface(REG_INTER);
4463 %}
4464
4465 operand eRegL() %{
4466 constraint(ALLOC_IN_RC(long_reg));
4467 match(RegL);
4468 match(eADXRegL);
4469
4470 format %{ %}
4471 interface(REG_INTER);
4472 %}
4473
4474 operand eADXRegL( eRegL reg ) %{
4475 constraint(ALLOC_IN_RC(eadx_reg));
4476 match(reg);
4477
4478 format %{ "EDX:EAX" %}
4479 interface(REG_INTER);
4480 %}
4481
4482 operand eBCXRegL( eRegL reg ) %{
4483 constraint(ALLOC_IN_RC(ebcx_reg));
4484 match(reg);
4485
4486 format %{ "EBX:ECX" %}
4487 interface(REG_INTER);
4488 %}
4489
4490 // Special case for integer high multiply
4491 operand eADXRegL_low_only() %{
4492 constraint(ALLOC_IN_RC(eadx_reg));
4493 match(RegL);
4494
4495 format %{ "EAX" %}
4496 interface(REG_INTER);
4497 %}
4498
4499 // Flags register, used as output of compare instructions
4500 operand eFlagsReg() %{
4501 constraint(ALLOC_IN_RC(int_flags));
4502 match(RegFlags);
4503
4504 format %{ "EFLAGS" %}
4505 interface(REG_INTER);
4506 %}
4507
4508 // Flags register, used as output of FLOATING POINT compare instructions
4509 operand eFlagsRegU() %{
4510 constraint(ALLOC_IN_RC(int_flags));
4511 match(RegFlags);
4512
4513 format %{ "EFLAGS_U" %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand eFlagsRegUCF() %{
4518 constraint(ALLOC_IN_RC(int_flags));
4519 match(RegFlags);
4520 predicate(false);
4521
4522 format %{ "EFLAGS_U_CF" %}
4523 interface(REG_INTER);
4524 %}
4525
4526 // Condition Code Register used by long compare
4527 operand flagsReg_long_LTGE() %{
4528 constraint(ALLOC_IN_RC(int_flags));
4529 match(RegFlags);
4530 format %{ "FLAGS_LTGE" %}
4531 interface(REG_INTER);
4532 %}
4533 operand flagsReg_long_EQNE() %{
4534 constraint(ALLOC_IN_RC(int_flags));
4535 match(RegFlags);
4536 format %{ "FLAGS_EQNE" %}
4537 interface(REG_INTER);
4538 %}
4539 operand flagsReg_long_LEGT() %{
4540 constraint(ALLOC_IN_RC(int_flags));
4541 match(RegFlags);
4542 format %{ "FLAGS_LEGT" %}
4543 interface(REG_INTER);
4544 %}
4545
4546 // Float register operands
4547 operand regDPR() %{
4548 predicate( UseSSE < 2 );
4549 constraint(ALLOC_IN_RC(fp_dbl_reg));
4550 match(RegD);
4551 match(regDPR1);
4552 match(regDPR2);
4553 format %{ %}
4554 interface(REG_INTER);
4555 %}
4556
4557 operand regDPR1(regDPR reg) %{
4558 predicate( UseSSE < 2 );
4559 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4560 match(reg);
4561 format %{ "FPR1" %}
4562 interface(REG_INTER);
4563 %}
4564
4565 operand regDPR2(regDPR reg) %{
4566 predicate( UseSSE < 2 );
4567 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4568 match(reg);
4569 format %{ "FPR2" %}
4570 interface(REG_INTER);
4571 %}
4572
4573 operand regnotDPR1(regDPR reg) %{
4574 predicate( UseSSE < 2 );
4575 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4576 match(reg);
4577 format %{ %}
4578 interface(REG_INTER);
4579 %}
4580
4581 // Float register operands
4582 operand regFPR() %{
4583 predicate( UseSSE < 2 );
4584 constraint(ALLOC_IN_RC(fp_flt_reg));
4585 match(RegF);
4586 match(regFPR1);
4587 format %{ %}
4588 interface(REG_INTER);
4589 %}
4590
4591 // Float register operands
4592 operand regFPR1(regFPR reg) %{
4593 predicate( UseSSE < 2 );
4594 constraint(ALLOC_IN_RC(fp_flt_reg0));
4595 match(reg);
4596 format %{ "FPR1" %}
4597 interface(REG_INTER);
4598 %}
4599
4600 // XMM Float register operands
4601 operand regF() %{
4602 predicate( UseSSE>=1 );
4603 constraint(ALLOC_IN_RC(float_reg));
4604 match(RegF);
4605 format %{ %}
4606 interface(REG_INTER);
4607 %}
4608
4609 // XMM Double register operands
4610 operand regD() %{
4611 predicate( UseSSE>=2 );
4612 constraint(ALLOC_IN_RC(double_reg));
4613 match(RegD);
4614 format %{ %}
4615 interface(REG_INTER);
4616 %}
4617
4618
4619 //----------Memory Operands----------------------------------------------------
4620 // Direct Memory Operand
4621 operand direct(immP addr) %{
4622 match(addr);
4623
4624 format %{ "[$addr]" %}
4625 interface(MEMORY_INTER) %{
4626 base(0xFFFFFFFF);
4627 index(0x4);
4628 scale(0x0);
4629 disp($addr);
4630 %}
4631 %}
4632
4633 // Indirect Memory Operand
4634 operand indirect(eRegP reg) %{
4635 constraint(ALLOC_IN_RC(int_reg));
4636 match(reg);
4637
4638 format %{ "[$reg]" %}
4639 interface(MEMORY_INTER) %{
4640 base($reg);
4641 index(0x4);
4642 scale(0x0);
4643 disp(0x0);
4644 %}
4645 %}
4646
4647 // Indirect Memory Plus Short Offset Operand
4648 operand indOffset8(eRegP reg, immI8 off) %{
4649 match(AddP reg off);
4650
4651 format %{ "[$reg + $off]" %}
4652 interface(MEMORY_INTER) %{
4653 base($reg);
4654 index(0x4);
4655 scale(0x0);
4656 disp($off);
4657 %}
4658 %}
4659
4660 // Indirect Memory Plus Long Offset Operand
4661 operand indOffset32(eRegP reg, immI off) %{
4662 match(AddP reg off);
4663
4664 format %{ "[$reg + $off]" %}
4665 interface(MEMORY_INTER) %{
4666 base($reg);
4667 index(0x4);
4668 scale(0x0);
4669 disp($off);
4670 %}
4671 %}
4672
4673 // Indirect Memory Plus Long Offset Operand
4674 operand indOffset32X(rRegI reg, immP off) %{
4675 match(AddP off reg);
4676
4677 format %{ "[$reg + $off]" %}
4678 interface(MEMORY_INTER) %{
4679 base($reg);
4680 index(0x4);
4681 scale(0x0);
4682 disp($off);
4683 %}
4684 %}
4685
4686 // Indirect Memory Plus Index Register Plus Offset Operand
4687 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4688 match(AddP (AddP reg ireg) off);
4689
4690 op_cost(10);
4691 format %{"[$reg + $off + $ireg]" %}
4692 interface(MEMORY_INTER) %{
4693 base($reg);
4694 index($ireg);
4695 scale(0x0);
4696 disp($off);
4697 %}
4698 %}
4699
4700 // Indirect Memory Plus Index Register Plus Offset Operand
4701 operand indIndex(eRegP reg, rRegI ireg) %{
4702 match(AddP reg ireg);
4703
4704 op_cost(10);
4705 format %{"[$reg + $ireg]" %}
4706 interface(MEMORY_INTER) %{
4707 base($reg);
4708 index($ireg);
4709 scale(0x0);
4710 disp(0x0);
4711 %}
4712 %}
4713
4714 // // -------------------------------------------------------------------------
4715 // // 486 architecture doesn't support "scale * index + offset" with out a base
4716 // // -------------------------------------------------------------------------
4717 // // Scaled Memory Operands
4718 // // Indirect Memory Times Scale Plus Offset Operand
4719 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4720 // match(AddP off (LShiftI ireg scale));
4721 //
4722 // op_cost(10);
4723 // format %{"[$off + $ireg << $scale]" %}
4724 // interface(MEMORY_INTER) %{
4725 // base(0x4);
4726 // index($ireg);
4727 // scale($scale);
4728 // disp($off);
4729 // %}
4730 // %}
4731
4732 // Indirect Memory Times Scale Plus Index Register
4733 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4734 match(AddP reg (LShiftI ireg scale));
4735
4736 op_cost(10);
4737 format %{"[$reg + $ireg << $scale]" %}
4738 interface(MEMORY_INTER) %{
4739 base($reg);
4740 index($ireg);
4741 scale($scale);
4742 disp(0x0);
4743 %}
4744 %}
4745
4746 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4747 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4748 match(AddP (AddP reg (LShiftI ireg scale)) off);
4749
4750 op_cost(10);
4751 format %{"[$reg + $off + $ireg << $scale]" %}
4752 interface(MEMORY_INTER) %{
4753 base($reg);
4754 index($ireg);
4755 scale($scale);
4756 disp($off);
4757 %}
4758 %}
4759
4760 //----------Load Long Memory Operands------------------------------------------
4761 // The load-long idiom will use it's address expression again after loading
4762 // the first word of the long. If the load-long destination overlaps with
4763 // registers used in the addressing expression, the 2nd half will be loaded
4764 // from a clobbered address. Fix this by requiring that load-long use
4765 // address registers that do not overlap with the load-long target.
4766
4767 // load-long support
4768 operand load_long_RegP() %{
4769 constraint(ALLOC_IN_RC(esi_reg));
4770 match(RegP);
4771 match(eSIRegP);
4772 op_cost(100);
4773 format %{ %}
4774 interface(REG_INTER);
4775 %}
4776
4777 // Indirect Memory Operand Long
4778 operand load_long_indirect(load_long_RegP reg) %{
4779 constraint(ALLOC_IN_RC(esi_reg));
4780 match(reg);
4781
4782 format %{ "[$reg]" %}
4783 interface(MEMORY_INTER) %{
4784 base($reg);
4785 index(0x4);
4786 scale(0x0);
4787 disp(0x0);
4788 %}
4789 %}
4790
4791 // Indirect Memory Plus Long Offset Operand
4792 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4793 match(AddP reg off);
4794
4795 format %{ "[$reg + $off]" %}
4796 interface(MEMORY_INTER) %{
4797 base($reg);
4798 index(0x4);
4799 scale(0x0);
4800 disp($off);
4801 %}
4802 %}
4803
4804 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4805
4806
4807 //----------Special Memory Operands--------------------------------------------
4808 // Stack Slot Operand - This operand is used for loading and storing temporary
4809 // values on the stack where a match requires a value to
4810 // flow through memory.
4811 operand stackSlotP(sRegP reg) %{
4812 constraint(ALLOC_IN_RC(stack_slots));
4813 // No match rule because this operand is only generated in matching
4814 format %{ "[$reg]" %}
4815 interface(MEMORY_INTER) %{
4816 base(0x4); // ESP
4817 index(0x4); // No Index
4818 scale(0x0); // No Scale
4819 disp($reg); // Stack Offset
4820 %}
4821 %}
4822
4823 operand stackSlotI(sRegI reg) %{
4824 constraint(ALLOC_IN_RC(stack_slots));
4825 // No match rule because this operand is only generated in matching
4826 format %{ "[$reg]" %}
4827 interface(MEMORY_INTER) %{
4828 base(0x4); // ESP
4829 index(0x4); // No Index
4830 scale(0x0); // No Scale
4831 disp($reg); // Stack Offset
4832 %}
4833 %}
4834
4835 operand stackSlotF(sRegF reg) %{
4836 constraint(ALLOC_IN_RC(stack_slots));
4837 // No match rule because this operand is only generated in matching
4838 format %{ "[$reg]" %}
4839 interface(MEMORY_INTER) %{
4840 base(0x4); // ESP
4841 index(0x4); // No Index
4842 scale(0x0); // No Scale
4843 disp($reg); // Stack Offset
4844 %}
4845 %}
4846
4847 operand stackSlotD(sRegD reg) %{
4848 constraint(ALLOC_IN_RC(stack_slots));
4849 // No match rule because this operand is only generated in matching
4850 format %{ "[$reg]" %}
4851 interface(MEMORY_INTER) %{
4852 base(0x4); // ESP
4853 index(0x4); // No Index
4854 scale(0x0); // No Scale
4855 disp($reg); // Stack Offset
4856 %}
4857 %}
4858
4859 operand stackSlotL(sRegL reg) %{
4860 constraint(ALLOC_IN_RC(stack_slots));
4861 // No match rule because this operand is only generated in matching
4862 format %{ "[$reg]" %}
4863 interface(MEMORY_INTER) %{
4864 base(0x4); // ESP
4865 index(0x4); // No Index
4866 scale(0x0); // No Scale
4867 disp($reg); // Stack Offset
4868 %}
4869 %}
4870
4871 //----------Memory Operands - Win95 Implicit Null Variants----------------
4872 // Indirect Memory Operand
4873 operand indirect_win95_safe(eRegP_no_EBP reg)
4874 %{
4875 constraint(ALLOC_IN_RC(int_reg));
4876 match(reg);
4877
4878 op_cost(100);
4879 format %{ "[$reg]" %}
4880 interface(MEMORY_INTER) %{
4881 base($reg);
4882 index(0x4);
4883 scale(0x0);
4884 disp(0x0);
4885 %}
4886 %}
4887
4888 // Indirect Memory Plus Short Offset Operand
4889 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4890 %{
4891 match(AddP reg off);
4892
4893 op_cost(100);
4894 format %{ "[$reg + $off]" %}
4895 interface(MEMORY_INTER) %{
4896 base($reg);
4897 index(0x4);
4898 scale(0x0);
4899 disp($off);
4900 %}
4901 %}
4902
4903 // Indirect Memory Plus Long Offset Operand
4904 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4905 %{
4906 match(AddP reg off);
4907
4908 op_cost(100);
4909 format %{ "[$reg + $off]" %}
4910 interface(MEMORY_INTER) %{
4911 base($reg);
4912 index(0x4);
4913 scale(0x0);
4914 disp($off);
4915 %}
4916 %}
4917
4918 // Indirect Memory Plus Index Register Plus Offset Operand
4919 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4920 %{
4921 match(AddP (AddP reg ireg) off);
4922
4923 op_cost(100);
4924 format %{"[$reg + $off + $ireg]" %}
4925 interface(MEMORY_INTER) %{
4926 base($reg);
4927 index($ireg);
4928 scale(0x0);
4929 disp($off);
4930 %}
4931 %}
4932
4933 // Indirect Memory Times Scale Plus Index Register
4934 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4935 %{
4936 match(AddP reg (LShiftI ireg scale));
4937
4938 op_cost(100);
4939 format %{"[$reg + $ireg << $scale]" %}
4940 interface(MEMORY_INTER) %{
4941 base($reg);
4942 index($ireg);
4943 scale($scale);
4944 disp(0x0);
4945 %}
4946 %}
4947
4948 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4949 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4950 %{
4951 match(AddP (AddP reg (LShiftI ireg scale)) off);
4952
4953 op_cost(100);
4954 format %{"[$reg + $off + $ireg << $scale]" %}
4955 interface(MEMORY_INTER) %{
4956 base($reg);
4957 index($ireg);
4958 scale($scale);
4959 disp($off);
4960 %}
4961 %}
4962
4963 //----------Conditional Branch Operands----------------------------------------
4964 // Comparison Op - This is the operation of the comparison, and is limited to
4965 // the following set of codes:
4966 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4967 //
4968 // Other attributes of the comparison, such as unsignedness, are specified
4969 // by the comparison instruction that sets a condition code flags register.
4970 // That result is represented by a flags operand whose subtype is appropriate
4971 // to the unsignedness (etc.) of the comparison.
4972 //
4973 // Later, the instruction which matches both the Comparison Op (a Bool) and
4974 // the flags (produced by the Cmp) specifies the coding of the comparison op
4975 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4976
4977 // Comparision Code
4978 operand cmpOp() %{
4979 match(Bool);
4980
4981 format %{ "" %}
4982 interface(COND_INTER) %{
4983 equal(0x4, "e");
4984 not_equal(0x5, "ne");
4985 less(0xC, "l");
4986 greater_equal(0xD, "ge");
4987 less_equal(0xE, "le");
4988 greater(0xF, "g");
4989 %}
4990 %}
4991
4992 // Comparison Code, unsigned compare. Used by FP also, with
4993 // C2 (unordered) turned into GT or LT already. The other bits
4994 // C0 and C3 are turned into Carry & Zero flags.
4995 operand cmpOpU() %{
4996 match(Bool);
4997
4998 format %{ "" %}
4999 interface(COND_INTER) %{
5000 equal(0x4, "e");
5001 not_equal(0x5, "ne");
5002 less(0x2, "b");
5003 greater_equal(0x3, "nb");
5004 less_equal(0x6, "be");
5005 greater(0x7, "nbe");
5006 %}
5007 %}
5008
5009 // Floating comparisons that don't require any fixup for the unordered case
5010 operand cmpOpUCF() %{
5011 match(Bool);
5012 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5013 n->as_Bool()->_test._test == BoolTest::ge ||
5014 n->as_Bool()->_test._test == BoolTest::le ||
5015 n->as_Bool()->_test._test == BoolTest::gt);
5016 format %{ "" %}
5017 interface(COND_INTER) %{
5018 equal(0x4, "e");
5019 not_equal(0x5, "ne");
5020 less(0x2, "b");
5021 greater_equal(0x3, "nb");
5022 less_equal(0x6, "be");
5023 greater(0x7, "nbe");
5024 %}
5025 %}
5026
5027
5028 // Floating comparisons that can be fixed up with extra conditional jumps
5029 operand cmpOpUCF2() %{
5030 match(Bool);
5031 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5032 n->as_Bool()->_test._test == BoolTest::eq);
5033 format %{ "" %}
5034 interface(COND_INTER) %{
5035 equal(0x4, "e");
5036 not_equal(0x5, "ne");
5037 less(0x2, "b");
5038 greater_equal(0x3, "nb");
5039 less_equal(0x6, "be");
5040 greater(0x7, "nbe");
5041 %}
5042 %}
5043
5044 // Comparison Code for FP conditional move
5045 operand cmpOp_fcmov() %{
5046 match(Bool);
5047
5048 format %{ "" %}
5049 interface(COND_INTER) %{
5050 equal (0x0C8);
5051 not_equal (0x1C8);
5052 less (0x0C0);
5053 greater_equal(0x1C0);
5054 less_equal (0x0D0);
5055 greater (0x1D0);
5056 %}
5057 %}
5058
5059 // Comparision Code used in long compares
5060 operand cmpOp_commute() %{
5061 match(Bool);
5062
5063 format %{ "" %}
5064 interface(COND_INTER) %{
5065 equal(0x4, "e");
5066 not_equal(0x5, "ne");
5067 less(0xF, "g");
5068 greater_equal(0xE, "le");
5069 less_equal(0xD, "ge");
5070 greater(0xC, "l");
5071 %}
5072 %}
5073
5074 //----------OPERAND CLASSES----------------------------------------------------
5075 // Operand Classes are groups of operands that are used as to simplify
5076 // instruction definitions by not requiring the AD writer to specify separate
5077 // instructions for every form of operand when the instruction accepts
5078 // multiple operand types with the same basic encoding and format. The classic
5079 // case of this is memory operands.
5080
5081 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5082 indIndex, indIndexScale, indIndexScaleOffset);
5083
5084 // Long memory operations are encoded in 2 instructions and a +4 offset.
5085 // This means some kind of offset is always required and you cannot use
5086 // an oop as the offset (done when working on static globals).
5087 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5088 indIndex, indIndexScale, indIndexScaleOffset);
5089
5090
5091 //----------PIPELINE-----------------------------------------------------------
5092 // Rules which define the behavior of the target architectures pipeline.
5093 pipeline %{
5094
5095 //----------ATTRIBUTES---------------------------------------------------------
5096 attributes %{
5097 variable_size_instructions; // Fixed size instructions
5098 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5099 instruction_unit_size = 1; // An instruction is 1 bytes long
5100 instruction_fetch_unit_size = 16; // The processor fetches one line
5101 instruction_fetch_units = 1; // of 16 bytes
5102
5103 // List of nop instructions
5104 nops( MachNop );
5105 %}
5106
5107 //----------RESOURCES----------------------------------------------------------
5108 // Resources are the functional units available to the machine
5109
5110 // Generic P2/P3 pipeline
5111 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5112 // 3 instructions decoded per cycle.
5113 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5114 // 2 ALU op, only ALU0 handles mul/div instructions.
5115 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5116 MS0, MS1, MEM = MS0 | MS1,
5117 BR, FPU,
5118 ALU0, ALU1, ALU = ALU0 | ALU1 );
5119
5120 //----------PIPELINE DESCRIPTION-----------------------------------------------
5121 // Pipeline Description specifies the stages in the machine's pipeline
5122
5123 // Generic P2/P3 pipeline
5124 pipe_desc(S0, S1, S2, S3, S4, S5);
5125
5126 //----------PIPELINE CLASSES---------------------------------------------------
5127 // Pipeline Classes describe the stages in which input and output are
5128 // referenced by the hardware pipeline.
5129
5130 // Naming convention: ialu or fpu
5131 // Then: _reg
5132 // Then: _reg if there is a 2nd register
5133 // Then: _long if it's a pair of instructions implementing a long
5134 // Then: _fat if it requires the big decoder
5135 // Or: _mem if it requires the big decoder and a memory unit.
5136
5137 // Integer ALU reg operation
5138 pipe_class ialu_reg(rRegI dst) %{
5139 single_instruction;
5140 dst : S4(write);
5141 dst : S3(read);
5142 DECODE : S0; // any decoder
5143 ALU : S3; // any alu
5144 %}
5145
5146 // Long ALU reg operation
5147 pipe_class ialu_reg_long(eRegL dst) %{
5148 instruction_count(2);
5149 dst : S4(write);
5150 dst : S3(read);
5151 DECODE : S0(2); // any 2 decoders
5152 ALU : S3(2); // both alus
5153 %}
5154
5155 // Integer ALU reg operation using big decoder
5156 pipe_class ialu_reg_fat(rRegI dst) %{
5157 single_instruction;
5158 dst : S4(write);
5159 dst : S3(read);
5160 D0 : S0; // big decoder only
5161 ALU : S3; // any alu
5162 %}
5163
5164 // Long ALU reg operation using big decoder
5165 pipe_class ialu_reg_long_fat(eRegL dst) %{
5166 instruction_count(2);
5167 dst : S4(write);
5168 dst : S3(read);
5169 D0 : S0(2); // big decoder only; twice
5170 ALU : S3(2); // any 2 alus
5171 %}
5172
5173 // Integer ALU reg-reg operation
5174 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5175 single_instruction;
5176 dst : S4(write);
5177 src : S3(read);
5178 DECODE : S0; // any decoder
5179 ALU : S3; // any alu
5180 %}
5181
5182 // Long ALU reg-reg operation
5183 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5184 instruction_count(2);
5185 dst : S4(write);
5186 src : S3(read);
5187 DECODE : S0(2); // any 2 decoders
5188 ALU : S3(2); // both alus
5189 %}
5190
5191 // Integer ALU reg-reg operation
5192 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5193 single_instruction;
5194 dst : S4(write);
5195 src : S3(read);
5196 D0 : S0; // big decoder only
5197 ALU : S3; // any alu
5198 %}
5199
5200 // Long ALU reg-reg operation
5201 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5202 instruction_count(2);
5203 dst : S4(write);
5204 src : S3(read);
5205 D0 : S0(2); // big decoder only; twice
5206 ALU : S3(2); // both alus
5207 %}
5208
5209 // Integer ALU reg-mem operation
5210 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5211 single_instruction;
5212 dst : S5(write);
5213 mem : S3(read);
5214 D0 : S0; // big decoder only
5215 ALU : S4; // any alu
5216 MEM : S3; // any mem
5217 %}
5218
5219 // Long ALU reg-mem operation
5220 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5221 instruction_count(2);
5222 dst : S5(write);
5223 mem : S3(read);
5224 D0 : S0(2); // big decoder only; twice
5225 ALU : S4(2); // any 2 alus
5226 MEM : S3(2); // both mems
5227 %}
5228
5229 // Integer mem operation (prefetch)
5230 pipe_class ialu_mem(memory mem)
5231 %{
5232 single_instruction;
5233 mem : S3(read);
5234 D0 : S0; // big decoder only
5235 MEM : S3; // any mem
5236 %}
5237
5238 // Integer Store to Memory
5239 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5240 single_instruction;
5241 mem : S3(read);
5242 src : S5(read);
5243 D0 : S0; // big decoder only
5244 ALU : S4; // any alu
5245 MEM : S3;
5246 %}
5247
5248 // Long Store to Memory
5249 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5250 instruction_count(2);
5251 mem : S3(read);
5252 src : S5(read);
5253 D0 : S0(2); // big decoder only; twice
5254 ALU : S4(2); // any 2 alus
5255 MEM : S3(2); // Both mems
5256 %}
5257
5258 // Integer Store to Memory
5259 pipe_class ialu_mem_imm(memory mem) %{
5260 single_instruction;
5261 mem : S3(read);
5262 D0 : S0; // big decoder only
5263 ALU : S4; // any alu
5264 MEM : S3;
5265 %}
5266
5267 // Integer ALU0 reg-reg operation
5268 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5269 single_instruction;
5270 dst : S4(write);
5271 src : S3(read);
5272 D0 : S0; // Big decoder only
5273 ALU0 : S3; // only alu0
5274 %}
5275
5276 // Integer ALU0 reg-mem operation
5277 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5278 single_instruction;
5279 dst : S5(write);
5280 mem : S3(read);
5281 D0 : S0; // big decoder only
5282 ALU0 : S4; // ALU0 only
5283 MEM : S3; // any mem
5284 %}
5285
5286 // Integer ALU reg-reg operation
5287 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5288 single_instruction;
5289 cr : S4(write);
5290 src1 : S3(read);
5291 src2 : S3(read);
5292 DECODE : S0; // any decoder
5293 ALU : S3; // any alu
5294 %}
5295
5296 // Integer ALU reg-imm operation
5297 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5298 single_instruction;
5299 cr : S4(write);
5300 src1 : S3(read);
5301 DECODE : S0; // any decoder
5302 ALU : S3; // any alu
5303 %}
5304
5305 // Integer ALU reg-mem operation
5306 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5307 single_instruction;
5308 cr : S4(write);
5309 src1 : S3(read);
5310 src2 : S3(read);
5311 D0 : S0; // big decoder only
5312 ALU : S4; // any alu
5313 MEM : S3;
5314 %}
5315
5316 // Conditional move reg-reg
5317 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5318 instruction_count(4);
5319 y : S4(read);
5320 q : S3(read);
5321 p : S3(read);
5322 DECODE : S0(4); // any decoder
5323 %}
5324
5325 // Conditional move reg-reg
5326 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5327 single_instruction;
5328 dst : S4(write);
5329 src : S3(read);
5330 cr : S3(read);
5331 DECODE : S0; // any decoder
5332 %}
5333
5334 // Conditional move reg-mem
5335 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5336 single_instruction;
5337 dst : S4(write);
5338 src : S3(read);
5339 cr : S3(read);
5340 DECODE : S0; // any decoder
5341 MEM : S3;
5342 %}
5343
5344 // Conditional move reg-reg long
5345 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5346 single_instruction;
5347 dst : S4(write);
5348 src : S3(read);
5349 cr : S3(read);
5350 DECODE : S0(2); // any 2 decoders
5351 %}
5352
5353 // Conditional move double reg-reg
5354 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5355 single_instruction;
5356 dst : S4(write);
5357 src : S3(read);
5358 cr : S3(read);
5359 DECODE : S0; // any decoder
5360 %}
5361
5362 // Float reg-reg operation
5363 pipe_class fpu_reg(regDPR dst) %{
5364 instruction_count(2);
5365 dst : S3(read);
5366 DECODE : S0(2); // any 2 decoders
5367 FPU : S3;
5368 %}
5369
5370 // Float reg-reg operation
5371 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5372 instruction_count(2);
5373 dst : S4(write);
5374 src : S3(read);
5375 DECODE : S0(2); // any 2 decoders
5376 FPU : S3;
5377 %}
5378
5379 // Float reg-reg operation
5380 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5381 instruction_count(3);
5382 dst : S4(write);
5383 src1 : S3(read);
5384 src2 : S3(read);
5385 DECODE : S0(3); // any 3 decoders
5386 FPU : S3(2);
5387 %}
5388
5389 // Float reg-reg operation
5390 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5391 instruction_count(4);
5392 dst : S4(write);
5393 src1 : S3(read);
5394 src2 : S3(read);
5395 src3 : S3(read);
5396 DECODE : S0(4); // any 3 decoders
5397 FPU : S3(2);
5398 %}
5399
5400 // Float reg-reg operation
5401 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5402 instruction_count(4);
5403 dst : S4(write);
5404 src1 : S3(read);
5405 src2 : S3(read);
5406 src3 : S3(read);
5407 DECODE : S1(3); // any 3 decoders
5408 D0 : S0; // Big decoder only
5409 FPU : S3(2);
5410 MEM : S3;
5411 %}
5412
5413 // Float reg-mem operation
5414 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5415 instruction_count(2);
5416 dst : S5(write);
5417 mem : S3(read);
5418 D0 : S0; // big decoder only
5419 DECODE : S1; // any decoder for FPU POP
5420 FPU : S4;
5421 MEM : S3; // any mem
5422 %}
5423
5424 // Float reg-mem operation
5425 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5426 instruction_count(3);
5427 dst : S5(write);
5428 src1 : S3(read);
5429 mem : S3(read);
5430 D0 : S0; // big decoder only
5431 DECODE : S1(2); // any decoder for FPU POP
5432 FPU : S4;
5433 MEM : S3; // any mem
5434 %}
5435
5436 // Float mem-reg operation
5437 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5438 instruction_count(2);
5439 src : S5(read);
5440 mem : S3(read);
5441 DECODE : S0; // any decoder for FPU PUSH
5442 D0 : S1; // big decoder only
5443 FPU : S4;
5444 MEM : S3; // any mem
5445 %}
5446
5447 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5448 instruction_count(3);
5449 src1 : S3(read);
5450 src2 : S3(read);
5451 mem : S3(read);
5452 DECODE : S0(2); // any decoder for FPU PUSH
5453 D0 : S1; // big decoder only
5454 FPU : S4;
5455 MEM : S3; // any mem
5456 %}
5457
5458 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5459 instruction_count(3);
5460 src1 : S3(read);
5461 src2 : S3(read);
5462 mem : S4(read);
5463 DECODE : S0; // any decoder for FPU PUSH
5464 D0 : S0(2); // big decoder only
5465 FPU : S4;
5466 MEM : S3(2); // any mem
5467 %}
5468
5469 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5470 instruction_count(2);
5471 src1 : S3(read);
5472 dst : S4(read);
5473 D0 : S0(2); // big decoder only
5474 MEM : S3(2); // any mem
5475 %}
5476
5477 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5478 instruction_count(3);
5479 src1 : S3(read);
5480 src2 : S3(read);
5481 dst : S4(read);
5482 D0 : S0(3); // big decoder only
5483 FPU : S4;
5484 MEM : S3(3); // any mem
5485 %}
5486
5487 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5488 instruction_count(3);
5489 src1 : S4(read);
5490 mem : S4(read);
5491 DECODE : S0; // any decoder for FPU PUSH
5492 D0 : S0(2); // big decoder only
5493 FPU : S4;
5494 MEM : S3(2); // any mem
5495 %}
5496
5497 // Float load constant
5498 pipe_class fpu_reg_con(regDPR dst) %{
5499 instruction_count(2);
5500 dst : S5(write);
5501 D0 : S0; // big decoder only for the load
5502 DECODE : S1; // any decoder for FPU POP
5503 FPU : S4;
5504 MEM : S3; // any mem
5505 %}
5506
5507 // Float load constant
5508 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5509 instruction_count(3);
5510 dst : S5(write);
5511 src : S3(read);
5512 D0 : S0; // big decoder only for the load
5513 DECODE : S1(2); // any decoder for FPU POP
5514 FPU : S4;
5515 MEM : S3; // any mem
5516 %}
5517
5518 // UnConditional branch
5519 pipe_class pipe_jmp( label labl ) %{
5520 single_instruction;
5521 BR : S3;
5522 %}
5523
5524 // Conditional branch
5525 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5526 single_instruction;
5527 cr : S1(read);
5528 BR : S3;
5529 %}
5530
5531 // Allocation idiom
5532 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5533 instruction_count(1); force_serialization;
5534 fixed_latency(6);
5535 heap_ptr : S3(read);
5536 DECODE : S0(3);
5537 D0 : S2;
5538 MEM : S3;
5539 ALU : S3(2);
5540 dst : S5(write);
5541 BR : S5;
5542 %}
5543
5544 // Generic big/slow expanded idiom
5545 pipe_class pipe_slow( ) %{
5546 instruction_count(10); multiple_bundles; force_serialization;
5547 fixed_latency(100);
5548 D0 : S0(2);
5549 MEM : S3(2);
5550 %}
5551
5552 // The real do-nothing guy
5553 pipe_class empty( ) %{
5554 instruction_count(0);
5555 %}
5556
5557 // Define the class for the Nop node
5558 define %{
5559 MachNop = empty;
5560 %}
5561
5562 %}
5563
5564 //----------INSTRUCTIONS-------------------------------------------------------
5565 //
5566 // match -- States which machine-independent subtree may be replaced
5567 // by this instruction.
5568 // ins_cost -- The estimated cost of this instruction is used by instruction
5569 // selection to identify a minimum cost tree of machine
5570 // instructions that matches a tree of machine-independent
5571 // instructions.
5572 // format -- A string providing the disassembly for this instruction.
5573 // The value of an instruction's operand may be inserted
5574 // by referring to it with a '$' prefix.
5575 // opcode -- Three instruction opcodes may be provided. These are referred
5576 // to within an encode class as $primary, $secondary, and $tertiary
5577 // respectively. The primary opcode is commonly used to
5578 // indicate the type of machine instruction, while secondary
5579 // and tertiary are often used for prefix options or addressing
5580 // modes.
5581 // ins_encode -- A list of encode classes with parameters. The encode class
5582 // name must have been defined in an 'enc_class' specification
5583 // in the encode section of the architecture description.
5584
5585 //----------BSWAP-Instruction--------------------------------------------------
5586 instruct bytes_reverse_int(rRegI dst) %{
5587 match(Set dst (ReverseBytesI dst));
5588
5589 format %{ "BSWAP $dst" %}
5590 opcode(0x0F, 0xC8);
5591 ins_encode( OpcP, OpcSReg(dst) );
5592 ins_pipe( ialu_reg );
5593 %}
5594
5595 instruct bytes_reverse_long(eRegL dst) %{
5596 match(Set dst (ReverseBytesL dst));
5597
5598 format %{ "BSWAP $dst.lo\n\t"
5599 "BSWAP $dst.hi\n\t"
5600 "XCHG $dst.lo $dst.hi" %}
5601
5602 ins_cost(125);
5603 ins_encode( bswap_long_bytes(dst) );
5604 ins_pipe( ialu_reg_reg);
5605 %}
5606
5607 instruct bytes_reverse_unsigned_short(rRegI dst) %{
5608 match(Set dst (ReverseBytesUS dst));
5609
5610 format %{ "BSWAP $dst\n\t"
5611 "SHR $dst,16\n\t" %}
5612 ins_encode %{
5613 __ bswapl($dst$$Register);
5614 __ shrl($dst$$Register, 16);
5615 %}
5616 ins_pipe( ialu_reg );
5617 %}
5618
5619 instruct bytes_reverse_short(rRegI dst) %{
5620 match(Set dst (ReverseBytesS dst));
5621
5622 format %{ "BSWAP $dst\n\t"
5623 "SAR $dst,16\n\t" %}
5624 ins_encode %{
5625 __ bswapl($dst$$Register);
5626 __ sarl($dst$$Register, 16);
5627 %}
5628 ins_pipe( ialu_reg );
5629 %}
5630
5631
5632 //---------- Zeros Count Instructions ------------------------------------------
5633
5634 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5635 predicate(UseCountLeadingZerosInstruction);
5636 match(Set dst (CountLeadingZerosI src));
5637 effect(KILL cr);
5638
5639 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5640 ins_encode %{
5641 __ lzcntl($dst$$Register, $src$$Register);
5642 %}
5643 ins_pipe(ialu_reg);
5644 %}
5645
5646 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5647 predicate(!UseCountLeadingZerosInstruction);
5648 match(Set dst (CountLeadingZerosI src));
5649 effect(KILL cr);
5650
5651 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5652 "JNZ skip\n\t"
5653 "MOV $dst, -1\n"
5654 "skip:\n\t"
5655 "NEG $dst\n\t"
5656 "ADD $dst, 31" %}
5657 ins_encode %{
5658 Register Rdst = $dst$$Register;
5659 Register Rsrc = $src$$Register;
5660 Label skip;
5661 __ bsrl(Rdst, Rsrc);
5662 __ jccb(Assembler::notZero, skip);
5663 __ movl(Rdst, -1);
5664 __ bind(skip);
5665 __ negl(Rdst);
5666 __ addl(Rdst, BitsPerInt - 1);
5667 %}
5668 ins_pipe(ialu_reg);
5669 %}
5670
5671 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5672 predicate(UseCountLeadingZerosInstruction);
5673 match(Set dst (CountLeadingZerosL src));
5674 effect(TEMP dst, KILL cr);
5675
5676 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5677 "JNC done\n\t"
5678 "LZCNT $dst, $src.lo\n\t"
5679 "ADD $dst, 32\n"
5680 "done:" %}
5681 ins_encode %{
5682 Register Rdst = $dst$$Register;
5683 Register Rsrc = $src$$Register;
5684 Label done;
5685 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5686 __ jccb(Assembler::carryClear, done);
5687 __ lzcntl(Rdst, Rsrc);
5688 __ addl(Rdst, BitsPerInt);
5689 __ bind(done);
5690 %}
5691 ins_pipe(ialu_reg);
5692 %}
5693
5694 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5695 predicate(!UseCountLeadingZerosInstruction);
5696 match(Set dst (CountLeadingZerosL src));
5697 effect(TEMP dst, KILL cr);
5698
5699 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5700 "JZ msw_is_zero\n\t"
5701 "ADD $dst, 32\n\t"
5702 "JMP not_zero\n"
5703 "msw_is_zero:\n\t"
5704 "BSR $dst, $src.lo\n\t"
5705 "JNZ not_zero\n\t"
5706 "MOV $dst, -1\n"
5707 "not_zero:\n\t"
5708 "NEG $dst\n\t"
5709 "ADD $dst, 63\n" %}
5710 ins_encode %{
5711 Register Rdst = $dst$$Register;
5712 Register Rsrc = $src$$Register;
5713 Label msw_is_zero;
5714 Label not_zero;
5715 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5716 __ jccb(Assembler::zero, msw_is_zero);
5717 __ addl(Rdst, BitsPerInt);
5718 __ jmpb(not_zero);
5719 __ bind(msw_is_zero);
5720 __ bsrl(Rdst, Rsrc);
5721 __ jccb(Assembler::notZero, not_zero);
5722 __ movl(Rdst, -1);
5723 __ bind(not_zero);
5724 __ negl(Rdst);
5725 __ addl(Rdst, BitsPerLong - 1);
5726 %}
5727 ins_pipe(ialu_reg);
5728 %}
5729
5730 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5731 match(Set dst (CountTrailingZerosI src));
5732 effect(KILL cr);
5733
5734 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5735 "JNZ done\n\t"
5736 "MOV $dst, 32\n"
5737 "done:" %}
5738 ins_encode %{
5739 Register Rdst = $dst$$Register;
5740 Label done;
5741 __ bsfl(Rdst, $src$$Register);
5742 __ jccb(Assembler::notZero, done);
5743 __ movl(Rdst, BitsPerInt);
5744 __ bind(done);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5750 match(Set dst (CountTrailingZerosL src));
5751 effect(TEMP dst, KILL cr);
5752
5753 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5754 "JNZ done\n\t"
5755 "BSF $dst, $src.hi\n\t"
5756 "JNZ msw_not_zero\n\t"
5757 "MOV $dst, 32\n"
5758 "msw_not_zero:\n\t"
5759 "ADD $dst, 32\n"
5760 "done:" %}
5761 ins_encode %{
5762 Register Rdst = $dst$$Register;
5763 Register Rsrc = $src$$Register;
5764 Label msw_not_zero;
5765 Label done;
5766 __ bsfl(Rdst, Rsrc);
5767 __ jccb(Assembler::notZero, done);
5768 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5769 __ jccb(Assembler::notZero, msw_not_zero);
5770 __ movl(Rdst, BitsPerInt);
5771 __ bind(msw_not_zero);
5772 __ addl(Rdst, BitsPerInt);
5773 __ bind(done);
5774 %}
5775 ins_pipe(ialu_reg);
5776 %}
5777
5778
5779 //---------- Population Count Instructions -------------------------------------
5780
5781 instruct popCountI(rRegI dst, rRegI src) %{
5782 predicate(UsePopCountInstruction);
5783 match(Set dst (PopCountI src));
5784
5785 format %{ "POPCNT $dst, $src" %}
5786 ins_encode %{
5787 __ popcntl($dst$$Register, $src$$Register);
5788 %}
5789 ins_pipe(ialu_reg);
5790 %}
5791
5792 instruct popCountI_mem(rRegI dst, memory mem) %{
5793 predicate(UsePopCountInstruction);
5794 match(Set dst (PopCountI (LoadI mem)));
5795
5796 format %{ "POPCNT $dst, $mem" %}
5797 ins_encode %{
5798 __ popcntl($dst$$Register, $mem$$Address);
5799 %}
5800 ins_pipe(ialu_reg);
5801 %}
5802
5803 // Note: Long.bitCount(long) returns an int.
5804 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5805 predicate(UsePopCountInstruction);
5806 match(Set dst (PopCountL src));
5807 effect(KILL cr, TEMP tmp, TEMP dst);
5808
5809 format %{ "POPCNT $dst, $src.lo\n\t"
5810 "POPCNT $tmp, $src.hi\n\t"
5811 "ADD $dst, $tmp" %}
5812 ins_encode %{
5813 __ popcntl($dst$$Register, $src$$Register);
5814 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5815 __ addl($dst$$Register, $tmp$$Register);
5816 %}
5817 ins_pipe(ialu_reg);
5818 %}
5819
5820 // Note: Long.bitCount(long) returns an int.
5821 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5822 predicate(UsePopCountInstruction);
5823 match(Set dst (PopCountL (LoadL mem)));
5824 effect(KILL cr, TEMP tmp, TEMP dst);
5825
5826 format %{ "POPCNT $dst, $mem\n\t"
5827 "POPCNT $tmp, $mem+4\n\t"
5828 "ADD $dst, $tmp" %}
5829 ins_encode %{
5830 //__ popcntl($dst$$Register, $mem$$Address$$first);
5831 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5832 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5833 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5834 __ addl($dst$$Register, $tmp$$Register);
5835 %}
5836 ins_pipe(ialu_reg);
5837 %}
5838
5839
5840 //----------Load/Store/Move Instructions---------------------------------------
5841 //----------Load Instructions--------------------------------------------------
5842 // Load Byte (8bit signed)
5843 instruct loadB(xRegI dst, memory mem) %{
5844 match(Set dst (LoadB mem));
5845
5846 ins_cost(125);
5847 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5848
5849 ins_encode %{
5850 __ movsbl($dst$$Register, $mem$$Address);
5851 %}
5852
5853 ins_pipe(ialu_reg_mem);
5854 %}
5855
5856 // Load Byte (8bit signed) into Long Register
5857 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5858 match(Set dst (ConvI2L (LoadB mem)));
5859 effect(KILL cr);
5860
5861 ins_cost(375);
5862 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5863 "MOV $dst.hi,$dst.lo\n\t"
5864 "SAR $dst.hi,7" %}
5865
5866 ins_encode %{
5867 __ movsbl($dst$$Register, $mem$$Address);
5868 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5869 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5870 %}
5871
5872 ins_pipe(ialu_reg_mem);
5873 %}
5874
5875 // Load Unsigned Byte (8bit UNsigned)
5876 instruct loadUB(xRegI dst, memory mem) %{
5877 match(Set dst (LoadUB mem));
5878
5879 ins_cost(125);
5880 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5881
5882 ins_encode %{
5883 __ movzbl($dst$$Register, $mem$$Address);
5884 %}
5885
5886 ins_pipe(ialu_reg_mem);
5887 %}
5888
5889 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5890 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5891 match(Set dst (ConvI2L (LoadUB mem)));
5892 effect(KILL cr);
5893
5894 ins_cost(250);
5895 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5896 "XOR $dst.hi,$dst.hi" %}
5897
5898 ins_encode %{
5899 Register Rdst = $dst$$Register;
5900 __ movzbl(Rdst, $mem$$Address);
5901 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5902 %}
5903
5904 ins_pipe(ialu_reg_mem);
5905 %}
5906
5907 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5908 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5909 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5910 effect(KILL cr);
5911
5912 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5913 "XOR $dst.hi,$dst.hi\n\t"
5914 "AND $dst.lo,$mask" %}
5915 ins_encode %{
5916 Register Rdst = $dst$$Register;
5917 __ movzbl(Rdst, $mem$$Address);
5918 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5919 __ andl(Rdst, $mask$$constant);
5920 %}
5921 ins_pipe(ialu_reg_mem);
5922 %}
5923
5924 // Load Short (16bit signed)
5925 instruct loadS(rRegI dst, memory mem) %{
5926 match(Set dst (LoadS mem));
5927
5928 ins_cost(125);
5929 format %{ "MOVSX $dst,$mem\t# short" %}
5930
5931 ins_encode %{
5932 __ movswl($dst$$Register, $mem$$Address);
5933 %}
5934
5935 ins_pipe(ialu_reg_mem);
5936 %}
5937
5938 // Load Short (16 bit signed) to Byte (8 bit signed)
5939 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5940 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5941
5942 ins_cost(125);
5943 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5944 ins_encode %{
5945 __ movsbl($dst$$Register, $mem$$Address);
5946 %}
5947 ins_pipe(ialu_reg_mem);
5948 %}
5949
5950 // Load Short (16bit signed) into Long Register
5951 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5952 match(Set dst (ConvI2L (LoadS mem)));
5953 effect(KILL cr);
5954
5955 ins_cost(375);
5956 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5957 "MOV $dst.hi,$dst.lo\n\t"
5958 "SAR $dst.hi,15" %}
5959
5960 ins_encode %{
5961 __ movswl($dst$$Register, $mem$$Address);
5962 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5963 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5964 %}
5965
5966 ins_pipe(ialu_reg_mem);
5967 %}
5968
5969 // Load Unsigned Short/Char (16bit unsigned)
5970 instruct loadUS(rRegI dst, memory mem) %{
5971 match(Set dst (LoadUS mem));
5972
5973 ins_cost(125);
5974 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5975
5976 ins_encode %{
5977 __ movzwl($dst$$Register, $mem$$Address);
5978 %}
5979
5980 ins_pipe(ialu_reg_mem);
5981 %}
5982
5983 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5984 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5985 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5986
5987 ins_cost(125);
5988 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5989 ins_encode %{
5990 __ movsbl($dst$$Register, $mem$$Address);
5991 %}
5992 ins_pipe(ialu_reg_mem);
5993 %}
5994
5995 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5996 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5997 match(Set dst (ConvI2L (LoadUS mem)));
5998 effect(KILL cr);
5999
6000 ins_cost(250);
6001 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6002 "XOR $dst.hi,$dst.hi" %}
6003
6004 ins_encode %{
6005 __ movzwl($dst$$Register, $mem$$Address);
6006 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6007 %}
6008
6009 ins_pipe(ialu_reg_mem);
6010 %}
6011
6012 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6013 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6014 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6015 effect(KILL cr);
6016
6017 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6018 "XOR $dst.hi,$dst.hi" %}
6019 ins_encode %{
6020 Register Rdst = $dst$$Register;
6021 __ movzbl(Rdst, $mem$$Address);
6022 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6023 %}
6024 ins_pipe(ialu_reg_mem);
6025 %}
6026
6027 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6028 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6029 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6030 effect(KILL cr);
6031
6032 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6033 "XOR $dst.hi,$dst.hi\n\t"
6034 "AND $dst.lo,$mask" %}
6035 ins_encode %{
6036 Register Rdst = $dst$$Register;
6037 __ movzwl(Rdst, $mem$$Address);
6038 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6039 __ andl(Rdst, $mask$$constant);
6040 %}
6041 ins_pipe(ialu_reg_mem);
6042 %}
6043
6044 // Load Integer
6045 instruct loadI(rRegI dst, memory mem) %{
6046 match(Set dst (LoadI mem));
6047
6048 ins_cost(125);
6049 format %{ "MOV $dst,$mem\t# int" %}
6050
6051 ins_encode %{
6052 __ movl($dst$$Register, $mem$$Address);
6053 %}
6054
6055 ins_pipe(ialu_reg_mem);
6056 %}
6057
6058 // Load Integer (32 bit signed) to Byte (8 bit signed)
6059 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6060 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6061
6062 ins_cost(125);
6063 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6064 ins_encode %{
6065 __ movsbl($dst$$Register, $mem$$Address);
6066 %}
6067 ins_pipe(ialu_reg_mem);
6068 %}
6069
6070 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6071 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6072 match(Set dst (AndI (LoadI mem) mask));
6073
6074 ins_cost(125);
6075 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6076 ins_encode %{
6077 __ movzbl($dst$$Register, $mem$$Address);
6078 %}
6079 ins_pipe(ialu_reg_mem);
6080 %}
6081
6082 // Load Integer (32 bit signed) to Short (16 bit signed)
6083 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6084 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6085
6086 ins_cost(125);
6087 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6088 ins_encode %{
6089 __ movswl($dst$$Register, $mem$$Address);
6090 %}
6091 ins_pipe(ialu_reg_mem);
6092 %}
6093
6094 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6095 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6096 match(Set dst (AndI (LoadI mem) mask));
6097
6098 ins_cost(125);
6099 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6100 ins_encode %{
6101 __ movzwl($dst$$Register, $mem$$Address);
6102 %}
6103 ins_pipe(ialu_reg_mem);
6104 %}
6105
6106 // Load Integer into Long Register
6107 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6108 match(Set dst (ConvI2L (LoadI mem)));
6109 effect(KILL cr);
6110
6111 ins_cost(375);
6112 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6113 "MOV $dst.hi,$dst.lo\n\t"
6114 "SAR $dst.hi,31" %}
6115
6116 ins_encode %{
6117 __ movl($dst$$Register, $mem$$Address);
6118 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6119 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6120 %}
6121
6122 ins_pipe(ialu_reg_mem);
6123 %}
6124
6125 // Load Integer with mask 0xFF into Long Register
6126 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6127 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6128 effect(KILL cr);
6129
6130 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6131 "XOR $dst.hi,$dst.hi" %}
6132 ins_encode %{
6133 Register Rdst = $dst$$Register;
6134 __ movzbl(Rdst, $mem$$Address);
6135 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6136 %}
6137 ins_pipe(ialu_reg_mem);
6138 %}
6139
6140 // Load Integer with mask 0xFFFF into Long Register
6141 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6142 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6143 effect(KILL cr);
6144
6145 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6146 "XOR $dst.hi,$dst.hi" %}
6147 ins_encode %{
6148 Register Rdst = $dst$$Register;
6149 __ movzwl(Rdst, $mem$$Address);
6150 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6151 %}
6152 ins_pipe(ialu_reg_mem);
6153 %}
6154
6155 // Load Integer with 32-bit mask into Long Register
6156 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6157 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6158 effect(KILL cr);
6159
6160 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6161 "XOR $dst.hi,$dst.hi\n\t"
6162 "AND $dst.lo,$mask" %}
6163 ins_encode %{
6164 Register Rdst = $dst$$Register;
6165 __ movl(Rdst, $mem$$Address);
6166 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6167 __ andl(Rdst, $mask$$constant);
6168 %}
6169 ins_pipe(ialu_reg_mem);
6170 %}
6171
6172 // Load Unsigned Integer into Long Register
6173 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6174 match(Set dst (LoadUI2L mem));
6175 effect(KILL cr);
6176
6177 ins_cost(250);
6178 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6179 "XOR $dst.hi,$dst.hi" %}
6180
6181 ins_encode %{
6182 __ movl($dst$$Register, $mem$$Address);
6183 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6184 %}
6185
6186 ins_pipe(ialu_reg_mem);
6187 %}
6188
6189 // Load Long. Cannot clobber address while loading, so restrict address
6190 // register to ESI
6191 instruct loadL(eRegL dst, load_long_memory mem) %{
6192 predicate(!((LoadLNode*)n)->require_atomic_access());
6193 match(Set dst (LoadL mem));
6194
6195 ins_cost(250);
6196 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6197 "MOV $dst.hi,$mem+4" %}
6198
6199 ins_encode %{
6200 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6201 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6202 __ movl($dst$$Register, Amemlo);
6203 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6204 %}
6205
6206 ins_pipe(ialu_reg_long_mem);
6207 %}
6208
6209 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6210 // then store it down to the stack and reload on the int
6211 // side.
6212 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6213 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6214 match(Set dst (LoadL mem));
6215
6216 ins_cost(200);
6217 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6218 "FISTp $dst" %}
6219 ins_encode(enc_loadL_volatile(mem,dst));
6220 ins_pipe( fpu_reg_mem );
6221 %}
6222
6223 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6224 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6225 match(Set dst (LoadL mem));
6226 effect(TEMP tmp);
6227 ins_cost(180);
6228 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6229 "MOVSD $dst,$tmp" %}
6230 ins_encode %{
6231 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6232 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6233 %}
6234 ins_pipe( pipe_slow );
6235 %}
6236
6237 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6238 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6239 match(Set dst (LoadL mem));
6240 effect(TEMP tmp);
6241 ins_cost(160);
6242 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6243 "MOVD $dst.lo,$tmp\n\t"
6244 "PSRLQ $tmp,32\n\t"
6245 "MOVD $dst.hi,$tmp" %}
6246 ins_encode %{
6247 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6248 __ movdl($dst$$Register, $tmp$$XMMRegister);
6249 __ psrlq($tmp$$XMMRegister, 32);
6250 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6251 %}
6252 ins_pipe( pipe_slow );
6253 %}
6254
6255 // Load Range
6256 instruct loadRange(rRegI dst, memory mem) %{
6257 match(Set dst (LoadRange mem));
6258
6259 ins_cost(125);
6260 format %{ "MOV $dst,$mem" %}
6261 opcode(0x8B);
6262 ins_encode( OpcP, RegMem(dst,mem));
6263 ins_pipe( ialu_reg_mem );
6264 %}
6265
6266
6267 // Load Pointer
6268 instruct loadP(eRegP dst, memory mem) %{
6269 match(Set dst (LoadP mem));
6270
6271 ins_cost(125);
6272 format %{ "MOV $dst,$mem" %}
6273 opcode(0x8B);
6274 ins_encode( OpcP, RegMem(dst,mem));
6275 ins_pipe( ialu_reg_mem );
6276 %}
6277
6278 // Load Klass Pointer
6279 instruct loadKlass(eRegP dst, memory mem) %{
6280 match(Set dst (LoadKlass mem));
6281
6282 ins_cost(125);
6283 format %{ "MOV $dst,$mem" %}
6284 opcode(0x8B);
6285 ins_encode( OpcP, RegMem(dst,mem));
6286 ins_pipe( ialu_reg_mem );
6287 %}
6288
6289 // Load Double
6290 instruct loadDPR(regDPR dst, memory mem) %{
6291 predicate(UseSSE<=1);
6292 match(Set dst (LoadD mem));
6293
6294 ins_cost(150);
6295 format %{ "FLD_D ST,$mem\n\t"
6296 "FSTP $dst" %}
6297 opcode(0xDD); /* DD /0 */
6298 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6299 Pop_Reg_DPR(dst) );
6300 ins_pipe( fpu_reg_mem );
6301 %}
6302
6303 // Load Double to XMM
6304 instruct loadD(regD dst, memory mem) %{
6305 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6306 match(Set dst (LoadD mem));
6307 ins_cost(145);
6308 format %{ "MOVSD $dst,$mem" %}
6309 ins_encode %{
6310 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6311 %}
6312 ins_pipe( pipe_slow );
6313 %}
6314
6315 instruct loadD_partial(regD dst, memory mem) %{
6316 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6317 match(Set dst (LoadD mem));
6318 ins_cost(145);
6319 format %{ "MOVLPD $dst,$mem" %}
6320 ins_encode %{
6321 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6322 %}
6323 ins_pipe( pipe_slow );
6324 %}
6325
6326 // Load to XMM register (single-precision floating point)
6327 // MOVSS instruction
6328 instruct loadF(regF dst, memory mem) %{
6329 predicate(UseSSE>=1);
6330 match(Set dst (LoadF mem));
6331 ins_cost(145);
6332 format %{ "MOVSS $dst,$mem" %}
6333 ins_encode %{
6334 __ movflt ($dst$$XMMRegister, $mem$$Address);
6335 %}
6336 ins_pipe( pipe_slow );
6337 %}
6338
6339 // Load Float
6340 instruct loadFPR(regFPR dst, memory mem) %{
6341 predicate(UseSSE==0);
6342 match(Set dst (LoadF mem));
6343
6344 ins_cost(150);
6345 format %{ "FLD_S ST,$mem\n\t"
6346 "FSTP $dst" %}
6347 opcode(0xD9); /* D9 /0 */
6348 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6349 Pop_Reg_FPR(dst) );
6350 ins_pipe( fpu_reg_mem );
6351 %}
6352
6353 // Load Effective Address
6354 instruct leaP8(eRegP dst, indOffset8 mem) %{
6355 match(Set dst mem);
6356
6357 ins_cost(110);
6358 format %{ "LEA $dst,$mem" %}
6359 opcode(0x8D);
6360 ins_encode( OpcP, RegMem(dst,mem));
6361 ins_pipe( ialu_reg_reg_fat );
6362 %}
6363
6364 instruct leaP32(eRegP dst, indOffset32 mem) %{
6365 match(Set dst mem);
6366
6367 ins_cost(110);
6368 format %{ "LEA $dst,$mem" %}
6369 opcode(0x8D);
6370 ins_encode( OpcP, RegMem(dst,mem));
6371 ins_pipe( ialu_reg_reg_fat );
6372 %}
6373
6374 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6375 match(Set dst mem);
6376
6377 ins_cost(110);
6378 format %{ "LEA $dst,$mem" %}
6379 opcode(0x8D);
6380 ins_encode( OpcP, RegMem(dst,mem));
6381 ins_pipe( ialu_reg_reg_fat );
6382 %}
6383
6384 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6385 match(Set dst mem);
6386
6387 ins_cost(110);
6388 format %{ "LEA $dst,$mem" %}
6389 opcode(0x8D);
6390 ins_encode( OpcP, RegMem(dst,mem));
6391 ins_pipe( ialu_reg_reg_fat );
6392 %}
6393
6394 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6395 match(Set dst mem);
6396
6397 ins_cost(110);
6398 format %{ "LEA $dst,$mem" %}
6399 opcode(0x8D);
6400 ins_encode( OpcP, RegMem(dst,mem));
6401 ins_pipe( ialu_reg_reg_fat );
6402 %}
6403
6404 // Load Constant
6405 instruct loadConI(rRegI dst, immI src) %{
6406 match(Set dst src);
6407
6408 format %{ "MOV $dst,$src" %}
6409 ins_encode( LdImmI(dst, src) );
6410 ins_pipe( ialu_reg_fat );
6411 %}
6412
6413 // Load Constant zero
6414 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6415 match(Set dst src);
6416 effect(KILL cr);
6417
6418 ins_cost(50);
6419 format %{ "XOR $dst,$dst" %}
6420 opcode(0x33); /* + rd */
6421 ins_encode( OpcP, RegReg( dst, dst ) );
6422 ins_pipe( ialu_reg );
6423 %}
6424
6425 instruct loadConP(eRegP dst, immP src) %{
6426 match(Set dst src);
6427
6428 format %{ "MOV $dst,$src" %}
6429 opcode(0xB8); /* + rd */
6430 ins_encode( LdImmP(dst, src) );
6431 ins_pipe( ialu_reg_fat );
6432 %}
6433
6434 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6435 match(Set dst src);
6436 effect(KILL cr);
6437 ins_cost(200);
6438 format %{ "MOV $dst.lo,$src.lo\n\t"
6439 "MOV $dst.hi,$src.hi" %}
6440 opcode(0xB8);
6441 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6442 ins_pipe( ialu_reg_long_fat );
6443 %}
6444
6445 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6446 match(Set dst src);
6447 effect(KILL cr);
6448 ins_cost(150);
6449 format %{ "XOR $dst.lo,$dst.lo\n\t"
6450 "XOR $dst.hi,$dst.hi" %}
6451 opcode(0x33,0x33);
6452 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6453 ins_pipe( ialu_reg_long );
6454 %}
6455
6456 // The instruction usage is guarded by predicate in operand immFPR().
6457 instruct loadConFPR(regFPR dst, immFPR con) %{
6458 match(Set dst con);
6459 ins_cost(125);
6460 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6461 "FSTP $dst" %}
6462 ins_encode %{
6463 __ fld_s($constantaddress($con));
6464 __ fstp_d($dst$$reg);
6465 %}
6466 ins_pipe(fpu_reg_con);
6467 %}
6468
6469 // The instruction usage is guarded by predicate in operand immFPR0().
6470 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6471 match(Set dst con);
6472 ins_cost(125);
6473 format %{ "FLDZ ST\n\t"
6474 "FSTP $dst" %}
6475 ins_encode %{
6476 __ fldz();
6477 __ fstp_d($dst$$reg);
6478 %}
6479 ins_pipe(fpu_reg_con);
6480 %}
6481
6482 // The instruction usage is guarded by predicate in operand immFPR1().
6483 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6484 match(Set dst con);
6485 ins_cost(125);
6486 format %{ "FLD1 ST\n\t"
6487 "FSTP $dst" %}
6488 ins_encode %{
6489 __ fld1();
6490 __ fstp_d($dst$$reg);
6491 %}
6492 ins_pipe(fpu_reg_con);
6493 %}
6494
6495 // The instruction usage is guarded by predicate in operand immF().
6496 instruct loadConF(regF dst, immF con) %{
6497 match(Set dst con);
6498 ins_cost(125);
6499 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6500 ins_encode %{
6501 __ movflt($dst$$XMMRegister, $constantaddress($con));
6502 %}
6503 ins_pipe(pipe_slow);
6504 %}
6505
6506 // The instruction usage is guarded by predicate in operand immF0().
6507 instruct loadConF0(regF dst, immF0 src) %{
6508 match(Set dst src);
6509 ins_cost(100);
6510 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6511 ins_encode %{
6512 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6513 %}
6514 ins_pipe(pipe_slow);
6515 %}
6516
6517 // The instruction usage is guarded by predicate in operand immDPR().
6518 instruct loadConDPR(regDPR dst, immDPR con) %{
6519 match(Set dst con);
6520 ins_cost(125);
6521
6522 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6523 "FSTP $dst" %}
6524 ins_encode %{
6525 __ fld_d($constantaddress($con));
6526 __ fstp_d($dst$$reg);
6527 %}
6528 ins_pipe(fpu_reg_con);
6529 %}
6530
6531 // The instruction usage is guarded by predicate in operand immDPR0().
6532 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6533 match(Set dst con);
6534 ins_cost(125);
6535
6536 format %{ "FLDZ ST\n\t"
6537 "FSTP $dst" %}
6538 ins_encode %{
6539 __ fldz();
6540 __ fstp_d($dst$$reg);
6541 %}
6542 ins_pipe(fpu_reg_con);
6543 %}
6544
6545 // The instruction usage is guarded by predicate in operand immDPR1().
6546 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6547 match(Set dst con);
6548 ins_cost(125);
6549
6550 format %{ "FLD1 ST\n\t"
6551 "FSTP $dst" %}
6552 ins_encode %{
6553 __ fld1();
6554 __ fstp_d($dst$$reg);
6555 %}
6556 ins_pipe(fpu_reg_con);
6557 %}
6558
6559 // The instruction usage is guarded by predicate in operand immD().
6560 instruct loadConD(regD dst, immD con) %{
6561 match(Set dst con);
6562 ins_cost(125);
6563 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6564 ins_encode %{
6565 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6566 %}
6567 ins_pipe(pipe_slow);
6568 %}
6569
6570 // The instruction usage is guarded by predicate in operand immD0().
6571 instruct loadConD0(regD dst, immD0 src) %{
6572 match(Set dst src);
6573 ins_cost(100);
6574 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6575 ins_encode %{
6576 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6577 %}
6578 ins_pipe( pipe_slow );
6579 %}
6580
6581 // Load Stack Slot
6582 instruct loadSSI(rRegI dst, stackSlotI src) %{
6583 match(Set dst src);
6584 ins_cost(125);
6585
6586 format %{ "MOV $dst,$src" %}
6587 opcode(0x8B);
6588 ins_encode( OpcP, RegMem(dst,src));
6589 ins_pipe( ialu_reg_mem );
6590 %}
6591
6592 instruct loadSSL(eRegL dst, stackSlotL src) %{
6593 match(Set dst src);
6594
6595 ins_cost(200);
6596 format %{ "MOV $dst,$src.lo\n\t"
6597 "MOV $dst+4,$src.hi" %}
6598 opcode(0x8B, 0x8B);
6599 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6600 ins_pipe( ialu_mem_long_reg );
6601 %}
6602
6603 // Load Stack Slot
6604 instruct loadSSP(eRegP dst, stackSlotP src) %{
6605 match(Set dst src);
6606 ins_cost(125);
6607
6608 format %{ "MOV $dst,$src" %}
6609 opcode(0x8B);
6610 ins_encode( OpcP, RegMem(dst,src));
6611 ins_pipe( ialu_reg_mem );
6612 %}
6613
6614 // Load Stack Slot
6615 instruct loadSSF(regFPR dst, stackSlotF src) %{
6616 match(Set dst src);
6617 ins_cost(125);
6618
6619 format %{ "FLD_S $src\n\t"
6620 "FSTP $dst" %}
6621 opcode(0xD9); /* D9 /0, FLD m32real */
6622 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6623 Pop_Reg_FPR(dst) );
6624 ins_pipe( fpu_reg_mem );
6625 %}
6626
6627 // Load Stack Slot
6628 instruct loadSSD(regDPR dst, stackSlotD src) %{
6629 match(Set dst src);
6630 ins_cost(125);
6631
6632 format %{ "FLD_D $src\n\t"
6633 "FSTP $dst" %}
6634 opcode(0xDD); /* DD /0, FLD m64real */
6635 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6636 Pop_Reg_DPR(dst) );
6637 ins_pipe( fpu_reg_mem );
6638 %}
6639
6640 // Prefetch instructions.
6641 // Must be safe to execute with invalid address (cannot fault).
6642
6643 instruct prefetchr0( memory mem ) %{
6644 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6645 match(PrefetchRead mem);
6646 ins_cost(0);
6647 size(0);
6648 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6649 ins_encode();
6650 ins_pipe(empty);
6651 %}
6652
6653 instruct prefetchr( memory mem ) %{
6654 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6655 match(PrefetchRead mem);
6656 ins_cost(100);
6657
6658 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6659 ins_encode %{
6660 __ prefetchr($mem$$Address);
6661 %}
6662 ins_pipe(ialu_mem);
6663 %}
6664
6665 instruct prefetchrNTA( memory mem ) %{
6666 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6667 match(PrefetchRead mem);
6668 ins_cost(100);
6669
6670 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6671 ins_encode %{
6672 __ prefetchnta($mem$$Address);
6673 %}
6674 ins_pipe(ialu_mem);
6675 %}
6676
6677 instruct prefetchrT0( memory mem ) %{
6678 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6679 match(PrefetchRead mem);
6680 ins_cost(100);
6681
6682 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6683 ins_encode %{
6684 __ prefetcht0($mem$$Address);
6685 %}
6686 ins_pipe(ialu_mem);
6687 %}
6688
6689 instruct prefetchrT2( memory mem ) %{
6690 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6691 match(PrefetchRead mem);
6692 ins_cost(100);
6693
6694 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6695 ins_encode %{
6696 __ prefetcht2($mem$$Address);
6697 %}
6698 ins_pipe(ialu_mem);
6699 %}
6700
6701 instruct prefetchw0( memory mem ) %{
6702 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6703 match(PrefetchWrite mem);
6704 ins_cost(0);
6705 size(0);
6706 format %{ "Prefetch (non-SSE is empty encoding)" %}
6707 ins_encode();
6708 ins_pipe(empty);
6709 %}
6710
6711 instruct prefetchw( memory mem ) %{
6712 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6713 match( PrefetchWrite mem );
6714 ins_cost(100);
6715
6716 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6717 ins_encode %{
6718 __ prefetchw($mem$$Address);
6719 %}
6720 ins_pipe(ialu_mem);
6721 %}
6722
6723 instruct prefetchwNTA( memory mem ) %{
6724 predicate(UseSSE>=1);
6725 match(PrefetchWrite mem);
6726 ins_cost(100);
6727
6728 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6729 ins_encode %{
6730 __ prefetchnta($mem$$Address);
6731 %}
6732 ins_pipe(ialu_mem);
6733 %}
6734
6735 // Prefetch instructions for allocation.
6736
6737 instruct prefetchAlloc0( memory mem ) %{
6738 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6739 match(PrefetchAllocation mem);
6740 ins_cost(0);
6741 size(0);
6742 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6743 ins_encode();
6744 ins_pipe(empty);
6745 %}
6746
6747 instruct prefetchAlloc( memory mem ) %{
6748 predicate(AllocatePrefetchInstr==3);
6749 match( PrefetchAllocation mem );
6750 ins_cost(100);
6751
6752 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6753 ins_encode %{
6754 __ prefetchw($mem$$Address);
6755 %}
6756 ins_pipe(ialu_mem);
6757 %}
6758
6759 instruct prefetchAllocNTA( memory mem ) %{
6760 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6761 match(PrefetchAllocation mem);
6762 ins_cost(100);
6763
6764 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6765 ins_encode %{
6766 __ prefetchnta($mem$$Address);
6767 %}
6768 ins_pipe(ialu_mem);
6769 %}
6770
6771 instruct prefetchAllocT0( memory mem ) %{
6772 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6773 match(PrefetchAllocation mem);
6774 ins_cost(100);
6775
6776 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6777 ins_encode %{
6778 __ prefetcht0($mem$$Address);
6779 %}
6780 ins_pipe(ialu_mem);
6781 %}
6782
6783 instruct prefetchAllocT2( memory mem ) %{
6784 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6785 match(PrefetchAllocation mem);
6786 ins_cost(100);
6787
6788 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6789 ins_encode %{
6790 __ prefetcht2($mem$$Address);
6791 %}
6792 ins_pipe(ialu_mem);
6793 %}
6794
6795 //----------Store Instructions-------------------------------------------------
6796
6797 // Store Byte
6798 instruct storeB(memory mem, xRegI src) %{
6799 match(Set mem (StoreB mem src));
6800
6801 ins_cost(125);
6802 format %{ "MOV8 $mem,$src" %}
6803 opcode(0x88);
6804 ins_encode( OpcP, RegMem( src, mem ) );
6805 ins_pipe( ialu_mem_reg );
6806 %}
6807
6808 // Store Char/Short
6809 instruct storeC(memory mem, rRegI src) %{
6810 match(Set mem (StoreC mem src));
6811
6812 ins_cost(125);
6813 format %{ "MOV16 $mem,$src" %}
6814 opcode(0x89, 0x66);
6815 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6816 ins_pipe( ialu_mem_reg );
6817 %}
6818
6819 // Store Integer
6820 instruct storeI(memory mem, rRegI src) %{
6821 match(Set mem (StoreI mem src));
6822
6823 ins_cost(125);
6824 format %{ "MOV $mem,$src" %}
6825 opcode(0x89);
6826 ins_encode( OpcP, RegMem( src, mem ) );
6827 ins_pipe( ialu_mem_reg );
6828 %}
6829
6830 // Store Long
6831 instruct storeL(long_memory mem, eRegL src) %{
6832 predicate(!((StoreLNode*)n)->require_atomic_access());
6833 match(Set mem (StoreL mem src));
6834
6835 ins_cost(200);
6836 format %{ "MOV $mem,$src.lo\n\t"
6837 "MOV $mem+4,$src.hi" %}
6838 opcode(0x89, 0x89);
6839 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6840 ins_pipe( ialu_mem_long_reg );
6841 %}
6842
6843 // Store Long to Integer
6844 instruct storeL2I(memory mem, eRegL src) %{
6845 match(Set mem (StoreI mem (ConvL2I src)));
6846
6847 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6848 ins_encode %{
6849 __ movl($mem$$Address, $src$$Register);
6850 %}
6851 ins_pipe(ialu_mem_reg);
6852 %}
6853
6854 // Volatile Store Long. Must be atomic, so move it into
6855 // the FP TOS and then do a 64-bit FIST. Has to probe the
6856 // target address before the store (for null-ptr checks)
6857 // so the memory operand is used twice in the encoding.
6858 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6859 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6860 match(Set mem (StoreL mem src));
6861 effect( KILL cr );
6862 ins_cost(400);
6863 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6864 "FILD $src\n\t"
6865 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6866 opcode(0x3B);
6867 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6868 ins_pipe( fpu_reg_mem );
6869 %}
6870
6871 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6872 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6873 match(Set mem (StoreL mem src));
6874 effect( TEMP tmp, KILL cr );
6875 ins_cost(380);
6876 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6877 "MOVSD $tmp,$src\n\t"
6878 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6879 ins_encode %{
6880 __ cmpl(rax, $mem$$Address);
6881 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6882 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6883 %}
6884 ins_pipe( pipe_slow );
6885 %}
6886
6887 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6888 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6889 match(Set mem (StoreL mem src));
6890 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6891 ins_cost(360);
6892 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6893 "MOVD $tmp,$src.lo\n\t"
6894 "MOVD $tmp2,$src.hi\n\t"
6895 "PUNPCKLDQ $tmp,$tmp2\n\t"
6896 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6897 ins_encode %{
6898 __ cmpl(rax, $mem$$Address);
6899 __ movdl($tmp$$XMMRegister, $src$$Register);
6900 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6901 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6902 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6903 %}
6904 ins_pipe( pipe_slow );
6905 %}
6906
6907 // Store Pointer; for storing unknown oops and raw pointers
6908 instruct storeP(memory mem, anyRegP src) %{
6909 match(Set mem (StoreP mem src));
6910
6911 ins_cost(125);
6912 format %{ "MOV $mem,$src" %}
6913 opcode(0x89);
6914 ins_encode( OpcP, RegMem( src, mem ) );
6915 ins_pipe( ialu_mem_reg );
6916 %}
6917
6918 // Store Integer Immediate
6919 instruct storeImmI(memory mem, immI src) %{
6920 match(Set mem (StoreI mem src));
6921
6922 ins_cost(150);
6923 format %{ "MOV $mem,$src" %}
6924 opcode(0xC7); /* C7 /0 */
6925 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6926 ins_pipe( ialu_mem_imm );
6927 %}
6928
6929 // Store Short/Char Immediate
6930 instruct storeImmI16(memory mem, immI16 src) %{
6931 predicate(UseStoreImmI16);
6932 match(Set mem (StoreC mem src));
6933
6934 ins_cost(150);
6935 format %{ "MOV16 $mem,$src" %}
6936 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6937 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6938 ins_pipe( ialu_mem_imm );
6939 %}
6940
6941 // Store Pointer Immediate; null pointers or constant oops that do not
6942 // need card-mark barriers.
6943 instruct storeImmP(memory mem, immP src) %{
6944 match(Set mem (StoreP mem src));
6945
6946 ins_cost(150);
6947 format %{ "MOV $mem,$src" %}
6948 opcode(0xC7); /* C7 /0 */
6949 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6950 ins_pipe( ialu_mem_imm );
6951 %}
6952
6953 // Store Byte Immediate
6954 instruct storeImmB(memory mem, immI8 src) %{
6955 match(Set mem (StoreB mem src));
6956
6957 ins_cost(150);
6958 format %{ "MOV8 $mem,$src" %}
6959 opcode(0xC6); /* C6 /0 */
6960 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6961 ins_pipe( ialu_mem_imm );
6962 %}
6963
6964 // Store CMS card-mark Immediate
6965 instruct storeImmCM(memory mem, immI8 src) %{
6966 match(Set mem (StoreCM mem src));
6967
6968 ins_cost(150);
6969 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6970 opcode(0xC6); /* C6 /0 */
6971 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6972 ins_pipe( ialu_mem_imm );
6973 %}
6974
6975 // Store Double
6976 instruct storeDPR( memory mem, regDPR1 src) %{
6977 predicate(UseSSE<=1);
6978 match(Set mem (StoreD mem src));
6979
6980 ins_cost(100);
6981 format %{ "FST_D $mem,$src" %}
6982 opcode(0xDD); /* DD /2 */
6983 ins_encode( enc_FPR_store(mem,src) );
6984 ins_pipe( fpu_mem_reg );
6985 %}
6986
6987 // Store double does rounding on x86
6988 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6989 predicate(UseSSE<=1);
6990 match(Set mem (StoreD mem (RoundDouble src)));
6991
6992 ins_cost(100);
6993 format %{ "FST_D $mem,$src\t# round" %}
6994 opcode(0xDD); /* DD /2 */
6995 ins_encode( enc_FPR_store(mem,src) );
6996 ins_pipe( fpu_mem_reg );
6997 %}
6998
6999 // Store XMM register to memory (double-precision floating points)
7000 // MOVSD instruction
7001 instruct storeD(memory mem, regD src) %{
7002 predicate(UseSSE>=2);
7003 match(Set mem (StoreD mem src));
7004 ins_cost(95);
7005 format %{ "MOVSD $mem,$src" %}
7006 ins_encode %{
7007 __ movdbl($mem$$Address, $src$$XMMRegister);
7008 %}
7009 ins_pipe( pipe_slow );
7010 %}
7011
7012 // Store XMM register to memory (single-precision floating point)
7013 // MOVSS instruction
7014 instruct storeF(memory mem, regF src) %{
7015 predicate(UseSSE>=1);
7016 match(Set mem (StoreF mem src));
7017 ins_cost(95);
7018 format %{ "MOVSS $mem,$src" %}
7019 ins_encode %{
7020 __ movflt($mem$$Address, $src$$XMMRegister);
7021 %}
7022 ins_pipe( pipe_slow );
7023 %}
7024
7025 // Store Float
7026 instruct storeFPR( memory mem, regFPR1 src) %{
7027 predicate(UseSSE==0);
7028 match(Set mem (StoreF mem src));
7029
7030 ins_cost(100);
7031 format %{ "FST_S $mem,$src" %}
7032 opcode(0xD9); /* D9 /2 */
7033 ins_encode( enc_FPR_store(mem,src) );
7034 ins_pipe( fpu_mem_reg );
7035 %}
7036
7037 // Store Float does rounding on x86
7038 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7039 predicate(UseSSE==0);
7040 match(Set mem (StoreF mem (RoundFloat src)));
7041
7042 ins_cost(100);
7043 format %{ "FST_S $mem,$src\t# round" %}
7044 opcode(0xD9); /* D9 /2 */
7045 ins_encode( enc_FPR_store(mem,src) );
7046 ins_pipe( fpu_mem_reg );
7047 %}
7048
7049 // Store Float does rounding on x86
7050 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7051 predicate(UseSSE<=1);
7052 match(Set mem (StoreF mem (ConvD2F src)));
7053
7054 ins_cost(100);
7055 format %{ "FST_S $mem,$src\t# D-round" %}
7056 opcode(0xD9); /* D9 /2 */
7057 ins_encode( enc_FPR_store(mem,src) );
7058 ins_pipe( fpu_mem_reg );
7059 %}
7060
7061 // Store immediate Float value (it is faster than store from FPU register)
7062 // The instruction usage is guarded by predicate in operand immFPR().
7063 instruct storeFPR_imm( memory mem, immFPR src) %{
7064 match(Set mem (StoreF mem src));
7065
7066 ins_cost(50);
7067 format %{ "MOV $mem,$src\t# store float" %}
7068 opcode(0xC7); /* C7 /0 */
7069 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7070 ins_pipe( ialu_mem_imm );
7071 %}
7072
7073 // Store immediate Float value (it is faster than store from XMM register)
7074 // The instruction usage is guarded by predicate in operand immF().
7075 instruct storeF_imm( memory mem, immF src) %{
7076 match(Set mem (StoreF mem src));
7077
7078 ins_cost(50);
7079 format %{ "MOV $mem,$src\t# store float" %}
7080 opcode(0xC7); /* C7 /0 */
7081 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7082 ins_pipe( ialu_mem_imm );
7083 %}
7084
7085 // Store Integer to stack slot
7086 instruct storeSSI(stackSlotI dst, rRegI src) %{
7087 match(Set dst src);
7088
7089 ins_cost(100);
7090 format %{ "MOV $dst,$src" %}
7091 opcode(0x89);
7092 ins_encode( OpcPRegSS( dst, src ) );
7093 ins_pipe( ialu_mem_reg );
7094 %}
7095
7096 // Store Integer to stack slot
7097 instruct storeSSP(stackSlotP dst, eRegP src) %{
7098 match(Set dst src);
7099
7100 ins_cost(100);
7101 format %{ "MOV $dst,$src" %}
7102 opcode(0x89);
7103 ins_encode( OpcPRegSS( dst, src ) );
7104 ins_pipe( ialu_mem_reg );
7105 %}
7106
7107 // Store Long to stack slot
7108 instruct storeSSL(stackSlotL dst, eRegL src) %{
7109 match(Set dst src);
7110
7111 ins_cost(200);
7112 format %{ "MOV $dst,$src.lo\n\t"
7113 "MOV $dst+4,$src.hi" %}
7114 opcode(0x89, 0x89);
7115 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7116 ins_pipe( ialu_mem_long_reg );
7117 %}
7118
7119 //----------MemBar Instructions-----------------------------------------------
7120 // Memory barrier flavors
7121
7122 instruct membar_acquire() %{
7123 match(MemBarAcquire);
7124 ins_cost(400);
7125
7126 size(0);
7127 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7128 ins_encode();
7129 ins_pipe(empty);
7130 %}
7131
7132 instruct membar_acquire_lock() %{
7133 match(MemBarAcquireLock);
7134 ins_cost(0);
7135
7136 size(0);
7137 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7138 ins_encode( );
7139 ins_pipe(empty);
7140 %}
7141
7142 instruct membar_release() %{
7143 match(MemBarRelease);
7144 ins_cost(400);
7145
7146 size(0);
7147 format %{ "MEMBAR-release ! (empty encoding)" %}
7148 ins_encode( );
7149 ins_pipe(empty);
7150 %}
7151
7152 instruct membar_release_lock() %{
7153 match(MemBarReleaseLock);
7154 ins_cost(0);
7155
7156 size(0);
7157 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7158 ins_encode( );
7159 ins_pipe(empty);
7160 %}
7161
7162 instruct membar_volatile(eFlagsReg cr) %{
7163 match(MemBarVolatile);
7164 effect(KILL cr);
7165 ins_cost(400);
7166
7167 format %{
7168 $$template
7169 if (os::is_MP()) {
7170 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7171 } else {
7172 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7173 }
7174 %}
7175 ins_encode %{
7176 __ membar(Assembler::StoreLoad);
7177 %}
7178 ins_pipe(pipe_slow);
7179 %}
7180
7181 instruct unnecessary_membar_volatile() %{
7182 match(MemBarVolatile);
7183 predicate(Matcher::post_store_load_barrier(n));
7184 ins_cost(0);
7185
7186 size(0);
7187 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7188 ins_encode( );
7189 ins_pipe(empty);
7190 %}
7191
7192 instruct membar_storestore() %{
7193 match(MemBarStoreStore);
7194 ins_cost(0);
7195
7196 size(0);
7197 format %{ "MEMBAR-storestore (empty encoding)" %}
7198 ins_encode( );
7199 ins_pipe(empty);
7200 %}
7201
7202 //----------Move Instructions--------------------------------------------------
7203 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7204 match(Set dst (CastX2P src));
7205 format %{ "# X2P $dst, $src" %}
7206 ins_encode( /*empty encoding*/ );
7207 ins_cost(0);
7208 ins_pipe(empty);
7209 %}
7210
7211 instruct castP2X(rRegI dst, eRegP src ) %{
7212 match(Set dst (CastP2X src));
7213 ins_cost(50);
7214 format %{ "MOV $dst, $src\t# CastP2X" %}
7215 ins_encode( enc_Copy( dst, src) );
7216 ins_pipe( ialu_reg_reg );
7217 %}
7218
7219 //----------Conditional Move---------------------------------------------------
7220 // Conditional move
7221 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7222 predicate(!VM_Version::supports_cmov() );
7223 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7224 ins_cost(200);
7225 format %{ "J$cop,us skip\t# signed cmove\n\t"
7226 "MOV $dst,$src\n"
7227 "skip:" %}
7228 ins_encode %{
7229 Label Lskip;
7230 // Invert sense of branch from sense of CMOV
7231 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7232 __ movl($dst$$Register, $src$$Register);
7233 __ bind(Lskip);
7234 %}
7235 ins_pipe( pipe_cmov_reg );
7236 %}
7237
7238 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7239 predicate(!VM_Version::supports_cmov() );
7240 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7241 ins_cost(200);
7242 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7243 "MOV $dst,$src\n"
7244 "skip:" %}
7245 ins_encode %{
7246 Label Lskip;
7247 // Invert sense of branch from sense of CMOV
7248 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7249 __ movl($dst$$Register, $src$$Register);
7250 __ bind(Lskip);
7251 %}
7252 ins_pipe( pipe_cmov_reg );
7253 %}
7254
7255 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7256 predicate(VM_Version::supports_cmov() );
7257 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7258 ins_cost(200);
7259 format %{ "CMOV$cop $dst,$src" %}
7260 opcode(0x0F,0x40);
7261 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7262 ins_pipe( pipe_cmov_reg );
7263 %}
7264
7265 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7266 predicate(VM_Version::supports_cmov() );
7267 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7268 ins_cost(200);
7269 format %{ "CMOV$cop $dst,$src" %}
7270 opcode(0x0F,0x40);
7271 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7272 ins_pipe( pipe_cmov_reg );
7273 %}
7274
7275 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7276 predicate(VM_Version::supports_cmov() );
7277 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7278 ins_cost(200);
7279 expand %{
7280 cmovI_regU(cop, cr, dst, src);
7281 %}
7282 %}
7283
7284 // Conditional move
7285 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7286 predicate(VM_Version::supports_cmov() );
7287 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7288 ins_cost(250);
7289 format %{ "CMOV$cop $dst,$src" %}
7290 opcode(0x0F,0x40);
7291 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7292 ins_pipe( pipe_cmov_mem );
7293 %}
7294
7295 // Conditional move
7296 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7297 predicate(VM_Version::supports_cmov() );
7298 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7299 ins_cost(250);
7300 format %{ "CMOV$cop $dst,$src" %}
7301 opcode(0x0F,0x40);
7302 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7303 ins_pipe( pipe_cmov_mem );
7304 %}
7305
7306 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7307 predicate(VM_Version::supports_cmov() );
7308 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7309 ins_cost(250);
7310 expand %{
7311 cmovI_memU(cop, cr, dst, src);
7312 %}
7313 %}
7314
7315 // Conditional move
7316 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7317 predicate(VM_Version::supports_cmov() );
7318 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7319 ins_cost(200);
7320 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7321 opcode(0x0F,0x40);
7322 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7323 ins_pipe( pipe_cmov_reg );
7324 %}
7325
7326 // Conditional move (non-P6 version)
7327 // Note: a CMoveP is generated for stubs and native wrappers
7328 // regardless of whether we are on a P6, so we
7329 // emulate a cmov here
7330 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7331 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7332 ins_cost(300);
7333 format %{ "Jn$cop skip\n\t"
7334 "MOV $dst,$src\t# pointer\n"
7335 "skip:" %}
7336 opcode(0x8b);
7337 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7338 ins_pipe( pipe_cmov_reg );
7339 %}
7340
7341 // Conditional move
7342 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7343 predicate(VM_Version::supports_cmov() );
7344 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7345 ins_cost(200);
7346 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7347 opcode(0x0F,0x40);
7348 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7349 ins_pipe( pipe_cmov_reg );
7350 %}
7351
7352 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7353 predicate(VM_Version::supports_cmov() );
7354 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7355 ins_cost(200);
7356 expand %{
7357 cmovP_regU(cop, cr, dst, src);
7358 %}
7359 %}
7360
7361 // DISABLED: Requires the ADLC to emit a bottom_type call that
7362 // correctly meets the two pointer arguments; one is an incoming
7363 // register but the other is a memory operand. ALSO appears to
7364 // be buggy with implicit null checks.
7365 //
7366 //// Conditional move
7367 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7368 // predicate(VM_Version::supports_cmov() );
7369 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7370 // ins_cost(250);
7371 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7372 // opcode(0x0F,0x40);
7373 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7374 // ins_pipe( pipe_cmov_mem );
7375 //%}
7376 //
7377 //// Conditional move
7378 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7379 // predicate(VM_Version::supports_cmov() );
7380 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7381 // ins_cost(250);
7382 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7383 // opcode(0x0F,0x40);
7384 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7385 // ins_pipe( pipe_cmov_mem );
7386 //%}
7387
7388 // Conditional move
7389 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7390 predicate(UseSSE<=1);
7391 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7392 ins_cost(200);
7393 format %{ "FCMOV$cop $dst,$src\t# double" %}
7394 opcode(0xDA);
7395 ins_encode( enc_cmov_dpr(cop,src) );
7396 ins_pipe( pipe_cmovDPR_reg );
7397 %}
7398
7399 // Conditional move
7400 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7401 predicate(UseSSE==0);
7402 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7403 ins_cost(200);
7404 format %{ "FCMOV$cop $dst,$src\t# float" %}
7405 opcode(0xDA);
7406 ins_encode( enc_cmov_dpr(cop,src) );
7407 ins_pipe( pipe_cmovDPR_reg );
7408 %}
7409
7410 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7411 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7412 predicate(UseSSE<=1);
7413 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7414 ins_cost(200);
7415 format %{ "Jn$cop skip\n\t"
7416 "MOV $dst,$src\t# double\n"
7417 "skip:" %}
7418 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7419 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7420 ins_pipe( pipe_cmovDPR_reg );
7421 %}
7422
7423 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7424 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7425 predicate(UseSSE==0);
7426 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7427 ins_cost(200);
7428 format %{ "Jn$cop skip\n\t"
7429 "MOV $dst,$src\t# float\n"
7430 "skip:" %}
7431 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7432 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7433 ins_pipe( pipe_cmovDPR_reg );
7434 %}
7435
7436 // No CMOVE with SSE/SSE2
7437 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7438 predicate (UseSSE>=1);
7439 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7440 ins_cost(200);
7441 format %{ "Jn$cop skip\n\t"
7442 "MOVSS $dst,$src\t# float\n"
7443 "skip:" %}
7444 ins_encode %{
7445 Label skip;
7446 // Invert sense of branch from sense of CMOV
7447 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7448 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7449 __ bind(skip);
7450 %}
7451 ins_pipe( pipe_slow );
7452 %}
7453
7454 // No CMOVE with SSE/SSE2
7455 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7456 predicate (UseSSE>=2);
7457 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7458 ins_cost(200);
7459 format %{ "Jn$cop skip\n\t"
7460 "MOVSD $dst,$src\t# float\n"
7461 "skip:" %}
7462 ins_encode %{
7463 Label skip;
7464 // Invert sense of branch from sense of CMOV
7465 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7466 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7467 __ bind(skip);
7468 %}
7469 ins_pipe( pipe_slow );
7470 %}
7471
7472 // unsigned version
7473 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7474 predicate (UseSSE>=1);
7475 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7476 ins_cost(200);
7477 format %{ "Jn$cop skip\n\t"
7478 "MOVSS $dst,$src\t# float\n"
7479 "skip:" %}
7480 ins_encode %{
7481 Label skip;
7482 // Invert sense of branch from sense of CMOV
7483 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7484 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7485 __ bind(skip);
7486 %}
7487 ins_pipe( pipe_slow );
7488 %}
7489
7490 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7491 predicate (UseSSE>=1);
7492 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7493 ins_cost(200);
7494 expand %{
7495 fcmovF_regU(cop, cr, dst, src);
7496 %}
7497 %}
7498
7499 // unsigned version
7500 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7501 predicate (UseSSE>=2);
7502 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7503 ins_cost(200);
7504 format %{ "Jn$cop skip\n\t"
7505 "MOVSD $dst,$src\t# float\n"
7506 "skip:" %}
7507 ins_encode %{
7508 Label skip;
7509 // Invert sense of branch from sense of CMOV
7510 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7511 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7512 __ bind(skip);
7513 %}
7514 ins_pipe( pipe_slow );
7515 %}
7516
7517 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7518 predicate (UseSSE>=2);
7519 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7520 ins_cost(200);
7521 expand %{
7522 fcmovD_regU(cop, cr, dst, src);
7523 %}
7524 %}
7525
7526 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7527 predicate(VM_Version::supports_cmov() );
7528 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7529 ins_cost(200);
7530 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7531 "CMOV$cop $dst.hi,$src.hi" %}
7532 opcode(0x0F,0x40);
7533 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7534 ins_pipe( pipe_cmov_reg_long );
7535 %}
7536
7537 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7538 predicate(VM_Version::supports_cmov() );
7539 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7540 ins_cost(200);
7541 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7542 "CMOV$cop $dst.hi,$src.hi" %}
7543 opcode(0x0F,0x40);
7544 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7545 ins_pipe( pipe_cmov_reg_long );
7546 %}
7547
7548 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7549 predicate(VM_Version::supports_cmov() );
7550 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7551 ins_cost(200);
7552 expand %{
7553 cmovL_regU(cop, cr, dst, src);
7554 %}
7555 %}
7556
7557 //----------Arithmetic Instructions--------------------------------------------
7558 //----------Addition Instructions----------------------------------------------
7559 // Integer Addition Instructions
7560 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7561 match(Set dst (AddI dst src));
7562 effect(KILL cr);
7563
7564 size(2);
7565 format %{ "ADD $dst,$src" %}
7566 opcode(0x03);
7567 ins_encode( OpcP, RegReg( dst, src) );
7568 ins_pipe( ialu_reg_reg );
7569 %}
7570
7571 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7572 match(Set dst (AddI dst src));
7573 effect(KILL cr);
7574
7575 format %{ "ADD $dst,$src" %}
7576 opcode(0x81, 0x00); /* /0 id */
7577 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7578 ins_pipe( ialu_reg );
7579 %}
7580
7581 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7582 predicate(UseIncDec);
7583 match(Set dst (AddI dst src));
7584 effect(KILL cr);
7585
7586 size(1);
7587 format %{ "INC $dst" %}
7588 opcode(0x40); /* */
7589 ins_encode( Opc_plus( primary, dst ) );
7590 ins_pipe( ialu_reg );
7591 %}
7592
7593 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7594 match(Set dst (AddI src0 src1));
7595 ins_cost(110);
7596
7597 format %{ "LEA $dst,[$src0 + $src1]" %}
7598 opcode(0x8D); /* 0x8D /r */
7599 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7600 ins_pipe( ialu_reg_reg );
7601 %}
7602
7603 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7604 match(Set dst (AddP src0 src1));
7605 ins_cost(110);
7606
7607 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7608 opcode(0x8D); /* 0x8D /r */
7609 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7610 ins_pipe( ialu_reg_reg );
7611 %}
7612
7613 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7614 predicate(UseIncDec);
7615 match(Set dst (AddI dst src));
7616 effect(KILL cr);
7617
7618 size(1);
7619 format %{ "DEC $dst" %}
7620 opcode(0x48); /* */
7621 ins_encode( Opc_plus( primary, dst ) );
7622 ins_pipe( ialu_reg );
7623 %}
7624
7625 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7626 match(Set dst (AddP dst src));
7627 effect(KILL cr);
7628
7629 size(2);
7630 format %{ "ADD $dst,$src" %}
7631 opcode(0x03);
7632 ins_encode( OpcP, RegReg( dst, src) );
7633 ins_pipe( ialu_reg_reg );
7634 %}
7635
7636 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7637 match(Set dst (AddP dst src));
7638 effect(KILL cr);
7639
7640 format %{ "ADD $dst,$src" %}
7641 opcode(0x81,0x00); /* Opcode 81 /0 id */
7642 // ins_encode( RegImm( dst, src) );
7643 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7644 ins_pipe( ialu_reg );
7645 %}
7646
7647 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7648 match(Set dst (AddI dst (LoadI src)));
7649 effect(KILL cr);
7650
7651 ins_cost(125);
7652 format %{ "ADD $dst,$src" %}
7653 opcode(0x03);
7654 ins_encode( OpcP, RegMem( dst, src) );
7655 ins_pipe( ialu_reg_mem );
7656 %}
7657
7658 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7659 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7660 effect(KILL cr);
7661
7662 ins_cost(150);
7663 format %{ "ADD $dst,$src" %}
7664 opcode(0x01); /* Opcode 01 /r */
7665 ins_encode( OpcP, RegMem( src, dst ) );
7666 ins_pipe( ialu_mem_reg );
7667 %}
7668
7669 // Add Memory with Immediate
7670 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7671 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7672 effect(KILL cr);
7673
7674 ins_cost(125);
7675 format %{ "ADD $dst,$src" %}
7676 opcode(0x81); /* Opcode 81 /0 id */
7677 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7678 ins_pipe( ialu_mem_imm );
7679 %}
7680
7681 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7682 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7683 effect(KILL cr);
7684
7685 ins_cost(125);
7686 format %{ "INC $dst" %}
7687 opcode(0xFF); /* Opcode FF /0 */
7688 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7689 ins_pipe( ialu_mem_imm );
7690 %}
7691
7692 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7693 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7694 effect(KILL cr);
7695
7696 ins_cost(125);
7697 format %{ "DEC $dst" %}
7698 opcode(0xFF); /* Opcode FF /1 */
7699 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7700 ins_pipe( ialu_mem_imm );
7701 %}
7702
7703
7704 instruct checkCastPP( eRegP dst ) %{
7705 match(Set dst (CheckCastPP dst));
7706
7707 size(0);
7708 format %{ "#checkcastPP of $dst" %}
7709 ins_encode( /*empty encoding*/ );
7710 ins_pipe( empty );
7711 %}
7712
7713 instruct castPP( eRegP dst ) %{
7714 match(Set dst (CastPP dst));
7715 format %{ "#castPP of $dst" %}
7716 ins_encode( /*empty encoding*/ );
7717 ins_pipe( empty );
7718 %}
7719
7720 instruct castII( rRegI dst ) %{
7721 match(Set dst (CastII dst));
7722 format %{ "#castII of $dst" %}
7723 ins_encode( /*empty encoding*/ );
7724 ins_cost(0);
7725 ins_pipe( empty );
7726 %}
7727
7728
7729 // Load-locked - same as a regular pointer load when used with compare-swap
7730 instruct loadPLocked(eRegP dst, memory mem) %{
7731 match(Set dst (LoadPLocked mem));
7732
7733 ins_cost(125);
7734 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7735 opcode(0x8B);
7736 ins_encode( OpcP, RegMem(dst,mem));
7737 ins_pipe( ialu_reg_mem );
7738 %}
7739
7740 // LoadLong-locked - same as a volatile long load when used with compare-swap
7741 instruct loadLLocked(stackSlotL dst, memory mem) %{
7742 predicate(UseSSE<=1);
7743 match(Set dst (LoadLLocked mem));
7744
7745 ins_cost(200);
7746 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7747 "FISTp $dst" %}
7748 ins_encode(enc_loadL_volatile(mem,dst));
7749 ins_pipe( fpu_reg_mem );
7750 %}
7751
7752 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{
7753 predicate(UseSSE>=2);
7754 match(Set dst (LoadLLocked mem));
7755 effect(TEMP tmp);
7756 ins_cost(180);
7757 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7758 "MOVSD $dst,$tmp" %}
7759 ins_encode %{
7760 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7761 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7762 %}
7763 ins_pipe( pipe_slow );
7764 %}
7765
7766 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{
7767 predicate(UseSSE>=2);
7768 match(Set dst (LoadLLocked mem));
7769 effect(TEMP tmp);
7770 ins_cost(160);
7771 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7772 "MOVD $dst.lo,$tmp\n\t"
7773 "PSRLQ $tmp,32\n\t"
7774 "MOVD $dst.hi,$tmp" %}
7775 ins_encode %{
7776 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7777 __ movdl($dst$$Register, $tmp$$XMMRegister);
7778 __ psrlq($tmp$$XMMRegister, 32);
7779 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7780 %}
7781 ins_pipe( pipe_slow );
7782 %}
7783
7784 // Conditional-store of the updated heap-top.
7785 // Used during allocation of the shared heap.
7786 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7787 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7788 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7789 // EAX is killed if there is contention, but then it's also unused.
7790 // In the common case of no contention, EAX holds the new oop address.
7791 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7792 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7793 ins_pipe( pipe_cmpxchg );
7794 %}
7795
7796 // Conditional-store of an int value.
7797 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7798 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7799 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7800 effect(KILL oldval);
7801 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7802 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7803 ins_pipe( pipe_cmpxchg );
7804 %}
7805
7806 // Conditional-store of a long value.
7807 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7808 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7809 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7810 effect(KILL oldval);
7811 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7812 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7813 "XCHG EBX,ECX"
7814 %}
7815 ins_encode %{
7816 // Note: we need to swap rbx, and rcx before and after the
7817 // cmpxchg8 instruction because the instruction uses
7818 // rcx as the high order word of the new value to store but
7819 // our register encoding uses rbx.
7820 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7821 if( os::is_MP() )
7822 __ lock();
7823 __ cmpxchg8($mem$$Address);
7824 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7825 %}
7826 ins_pipe( pipe_cmpxchg );
7827 %}
7828
7829 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7830
7831 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7832 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7833 effect(KILL cr, KILL oldval);
7834 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7835 "MOV $res,0\n\t"
7836 "JNE,s fail\n\t"
7837 "MOV $res,1\n"
7838 "fail:" %}
7839 ins_encode( enc_cmpxchg8(mem_ptr),
7840 enc_flags_ne_to_boolean(res) );
7841 ins_pipe( pipe_cmpxchg );
7842 %}
7843
7844 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7845 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7846 effect(KILL cr, KILL oldval);
7847 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7848 "MOV $res,0\n\t"
7849 "JNE,s fail\n\t"
7850 "MOV $res,1\n"
7851 "fail:" %}
7852 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7853 ins_pipe( pipe_cmpxchg );
7854 %}
7855
7856 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7857 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7858 effect(KILL cr, KILL oldval);
7859 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7860 "MOV $res,0\n\t"
7861 "JNE,s fail\n\t"
7862 "MOV $res,1\n"
7863 "fail:" %}
7864 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7865 ins_pipe( pipe_cmpxchg );
7866 %}
7867
7868 //----------Subtraction Instructions-------------------------------------------
7869 // Integer Subtraction Instructions
7870 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7871 match(Set dst (SubI dst src));
7872 effect(KILL cr);
7873
7874 size(2);
7875 format %{ "SUB $dst,$src" %}
7876 opcode(0x2B);
7877 ins_encode( OpcP, RegReg( dst, src) );
7878 ins_pipe( ialu_reg_reg );
7879 %}
7880
7881 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7882 match(Set dst (SubI dst src));
7883 effect(KILL cr);
7884
7885 format %{ "SUB $dst,$src" %}
7886 opcode(0x81,0x05); /* Opcode 81 /5 */
7887 // ins_encode( RegImm( dst, src) );
7888 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7889 ins_pipe( ialu_reg );
7890 %}
7891
7892 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7893 match(Set dst (SubI dst (LoadI src)));
7894 effect(KILL cr);
7895
7896 ins_cost(125);
7897 format %{ "SUB $dst,$src" %}
7898 opcode(0x2B);
7899 ins_encode( OpcP, RegMem( dst, src) );
7900 ins_pipe( ialu_reg_mem );
7901 %}
7902
7903 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7904 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7905 effect(KILL cr);
7906
7907 ins_cost(150);
7908 format %{ "SUB $dst,$src" %}
7909 opcode(0x29); /* Opcode 29 /r */
7910 ins_encode( OpcP, RegMem( src, dst ) );
7911 ins_pipe( ialu_mem_reg );
7912 %}
7913
7914 // Subtract from a pointer
7915 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7916 match(Set dst (AddP dst (SubI zero src)));
7917 effect(KILL cr);
7918
7919 size(2);
7920 format %{ "SUB $dst,$src" %}
7921 opcode(0x2B);
7922 ins_encode( OpcP, RegReg( dst, src) );
7923 ins_pipe( ialu_reg_reg );
7924 %}
7925
7926 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7927 match(Set dst (SubI zero dst));
7928 effect(KILL cr);
7929
7930 size(2);
7931 format %{ "NEG $dst" %}
7932 opcode(0xF7,0x03); // Opcode F7 /3
7933 ins_encode( OpcP, RegOpc( dst ) );
7934 ins_pipe( ialu_reg );
7935 %}
7936
7937
7938 //----------Multiplication/Division Instructions-------------------------------
7939 // Integer Multiplication Instructions
7940 // Multiply Register
7941 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7942 match(Set dst (MulI dst src));
7943 effect(KILL cr);
7944
7945 size(3);
7946 ins_cost(300);
7947 format %{ "IMUL $dst,$src" %}
7948 opcode(0xAF, 0x0F);
7949 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7950 ins_pipe( ialu_reg_reg_alu0 );
7951 %}
7952
7953 // Multiply 32-bit Immediate
7954 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7955 match(Set dst (MulI src imm));
7956 effect(KILL cr);
7957
7958 ins_cost(300);
7959 format %{ "IMUL $dst,$src,$imm" %}
7960 opcode(0x69); /* 69 /r id */
7961 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7962 ins_pipe( ialu_reg_reg_alu0 );
7963 %}
7964
7965 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7966 match(Set dst src);
7967 effect(KILL cr);
7968
7969 // Note that this is artificially increased to make it more expensive than loadConL
7970 ins_cost(250);
7971 format %{ "MOV EAX,$src\t// low word only" %}
7972 opcode(0xB8);
7973 ins_encode( LdImmL_Lo(dst, src) );
7974 ins_pipe( ialu_reg_fat );
7975 %}
7976
7977 // Multiply by 32-bit Immediate, taking the shifted high order results
7978 // (special case for shift by 32)
7979 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7980 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7981 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7982 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7983 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7984 effect(USE src1, KILL cr);
7985
7986 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7987 ins_cost(0*100 + 1*400 - 150);
7988 format %{ "IMUL EDX:EAX,$src1" %}
7989 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7990 ins_pipe( pipe_slow );
7991 %}
7992
7993 // Multiply by 32-bit Immediate, taking the shifted high order results
7994 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7995 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7996 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7997 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7998 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7999 effect(USE src1, KILL cr);
8000
8001 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8002 ins_cost(1*100 + 1*400 - 150);
8003 format %{ "IMUL EDX:EAX,$src1\n\t"
8004 "SAR EDX,$cnt-32" %}
8005 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8006 ins_pipe( pipe_slow );
8007 %}
8008
8009 // Multiply Memory 32-bit Immediate
8010 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8011 match(Set dst (MulI (LoadI src) imm));
8012 effect(KILL cr);
8013
8014 ins_cost(300);
8015 format %{ "IMUL $dst,$src,$imm" %}
8016 opcode(0x69); /* 69 /r id */
8017 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8018 ins_pipe( ialu_reg_mem_alu0 );
8019 %}
8020
8021 // Multiply Memory
8022 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8023 match(Set dst (MulI dst (LoadI src)));
8024 effect(KILL cr);
8025
8026 ins_cost(350);
8027 format %{ "IMUL $dst,$src" %}
8028 opcode(0xAF, 0x0F);
8029 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8030 ins_pipe( ialu_reg_mem_alu0 );
8031 %}
8032
8033 // Multiply Register Int to Long
8034 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8035 // Basic Idea: long = (long)int * (long)int
8036 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8037 effect(DEF dst, USE src, USE src1, KILL flags);
8038
8039 ins_cost(300);
8040 format %{ "IMUL $dst,$src1" %}
8041
8042 ins_encode( long_int_multiply( dst, src1 ) );
8043 ins_pipe( ialu_reg_reg_alu0 );
8044 %}
8045
8046 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8047 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8048 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8049 effect(KILL flags);
8050
8051 ins_cost(300);
8052 format %{ "MUL $dst,$src1" %}
8053
8054 ins_encode( long_uint_multiply(dst, src1) );
8055 ins_pipe( ialu_reg_reg_alu0 );
8056 %}
8057
8058 // Multiply Register Long
8059 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8060 match(Set dst (MulL dst src));
8061 effect(KILL cr, TEMP tmp);
8062 ins_cost(4*100+3*400);
8063 // Basic idea: lo(result) = lo(x_lo * y_lo)
8064 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8065 format %{ "MOV $tmp,$src.lo\n\t"
8066 "IMUL $tmp,EDX\n\t"
8067 "MOV EDX,$src.hi\n\t"
8068 "IMUL EDX,EAX\n\t"
8069 "ADD $tmp,EDX\n\t"
8070 "MUL EDX:EAX,$src.lo\n\t"
8071 "ADD EDX,$tmp" %}
8072 ins_encode( long_multiply( dst, src, tmp ) );
8073 ins_pipe( pipe_slow );
8074 %}
8075
8076 // Multiply Register Long where the left operand's high 32 bits are zero
8077 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8078 predicate(is_operand_hi32_zero(n->in(1)));
8079 match(Set dst (MulL dst src));
8080 effect(KILL cr, TEMP tmp);
8081 ins_cost(2*100+2*400);
8082 // Basic idea: lo(result) = lo(x_lo * y_lo)
8083 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8084 format %{ "MOV $tmp,$src.hi\n\t"
8085 "IMUL $tmp,EAX\n\t"
8086 "MUL EDX:EAX,$src.lo\n\t"
8087 "ADD EDX,$tmp" %}
8088 ins_encode %{
8089 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8090 __ imull($tmp$$Register, rax);
8091 __ mull($src$$Register);
8092 __ addl(rdx, $tmp$$Register);
8093 %}
8094 ins_pipe( pipe_slow );
8095 %}
8096
8097 // Multiply Register Long where the right operand's high 32 bits are zero
8098 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8099 predicate(is_operand_hi32_zero(n->in(2)));
8100 match(Set dst (MulL dst src));
8101 effect(KILL cr, TEMP tmp);
8102 ins_cost(2*100+2*400);
8103 // Basic idea: lo(result) = lo(x_lo * y_lo)
8104 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8105 format %{ "MOV $tmp,$src.lo\n\t"
8106 "IMUL $tmp,EDX\n\t"
8107 "MUL EDX:EAX,$src.lo\n\t"
8108 "ADD EDX,$tmp" %}
8109 ins_encode %{
8110 __ movl($tmp$$Register, $src$$Register);
8111 __ imull($tmp$$Register, rdx);
8112 __ mull($src$$Register);
8113 __ addl(rdx, $tmp$$Register);
8114 %}
8115 ins_pipe( pipe_slow );
8116 %}
8117
8118 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8119 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8120 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8121 match(Set dst (MulL dst src));
8122 effect(KILL cr);
8123 ins_cost(1*400);
8124 // Basic idea: lo(result) = lo(x_lo * y_lo)
8125 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8126 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8127 ins_encode %{
8128 __ mull($src$$Register);
8129 %}
8130 ins_pipe( pipe_slow );
8131 %}
8132
8133 // Multiply Register Long by small constant
8134 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8135 match(Set dst (MulL dst src));
8136 effect(KILL cr, TEMP tmp);
8137 ins_cost(2*100+2*400);
8138 size(12);
8139 // Basic idea: lo(result) = lo(src * EAX)
8140 // hi(result) = hi(src * EAX) + lo(src * EDX)
8141 format %{ "IMUL $tmp,EDX,$src\n\t"
8142 "MOV EDX,$src\n\t"
8143 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8144 "ADD EDX,$tmp" %}
8145 ins_encode( long_multiply_con( dst, src, tmp ) );
8146 ins_pipe( pipe_slow );
8147 %}
8148
8149 // Integer DIV with Register
8150 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8151 match(Set rax (DivI rax div));
8152 effect(KILL rdx, KILL cr);
8153 size(26);
8154 ins_cost(30*100+10*100);
8155 format %{ "CMP EAX,0x80000000\n\t"
8156 "JNE,s normal\n\t"
8157 "XOR EDX,EDX\n\t"
8158 "CMP ECX,-1\n\t"
8159 "JE,s done\n"
8160 "normal: CDQ\n\t"
8161 "IDIV $div\n\t"
8162 "done:" %}
8163 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8164 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8165 ins_pipe( ialu_reg_reg_alu0 );
8166 %}
8167
8168 // Divide Register Long
8169 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8170 match(Set dst (DivL src1 src2));
8171 effect( KILL cr, KILL cx, KILL bx );
8172 ins_cost(10000);
8173 format %{ "PUSH $src1.hi\n\t"
8174 "PUSH $src1.lo\n\t"
8175 "PUSH $src2.hi\n\t"
8176 "PUSH $src2.lo\n\t"
8177 "CALL SharedRuntime::ldiv\n\t"
8178 "ADD ESP,16" %}
8179 ins_encode( long_div(src1,src2) );
8180 ins_pipe( pipe_slow );
8181 %}
8182
8183 // Integer DIVMOD with Register, both quotient and mod results
8184 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8185 match(DivModI rax div);
8186 effect(KILL cr);
8187 size(26);
8188 ins_cost(30*100+10*100);
8189 format %{ "CMP EAX,0x80000000\n\t"
8190 "JNE,s normal\n\t"
8191 "XOR EDX,EDX\n\t"
8192 "CMP ECX,-1\n\t"
8193 "JE,s done\n"
8194 "normal: CDQ\n\t"
8195 "IDIV $div\n\t"
8196 "done:" %}
8197 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8198 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8199 ins_pipe( pipe_slow );
8200 %}
8201
8202 // Integer MOD with Register
8203 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8204 match(Set rdx (ModI rax div));
8205 effect(KILL rax, KILL cr);
8206
8207 size(26);
8208 ins_cost(300);
8209 format %{ "CDQ\n\t"
8210 "IDIV $div" %}
8211 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8212 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8213 ins_pipe( ialu_reg_reg_alu0 );
8214 %}
8215
8216 // Remainder Register Long
8217 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8218 match(Set dst (ModL src1 src2));
8219 effect( KILL cr, KILL cx, KILL bx );
8220 ins_cost(10000);
8221 format %{ "PUSH $src1.hi\n\t"
8222 "PUSH $src1.lo\n\t"
8223 "PUSH $src2.hi\n\t"
8224 "PUSH $src2.lo\n\t"
8225 "CALL SharedRuntime::lrem\n\t"
8226 "ADD ESP,16" %}
8227 ins_encode( long_mod(src1,src2) );
8228 ins_pipe( pipe_slow );
8229 %}
8230
8231 // Divide Register Long (no special case since divisor != -1)
8232 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8233 match(Set dst (DivL dst imm));
8234 effect( TEMP tmp, TEMP tmp2, KILL cr );
8235 ins_cost(1000);
8236 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8237 "XOR $tmp2,$tmp2\n\t"
8238 "CMP $tmp,EDX\n\t"
8239 "JA,s fast\n\t"
8240 "MOV $tmp2,EAX\n\t"
8241 "MOV EAX,EDX\n\t"
8242 "MOV EDX,0\n\t"
8243 "JLE,s pos\n\t"
8244 "LNEG EAX : $tmp2\n\t"
8245 "DIV $tmp # unsigned division\n\t"
8246 "XCHG EAX,$tmp2\n\t"
8247 "DIV $tmp\n\t"
8248 "LNEG $tmp2 : EAX\n\t"
8249 "JMP,s done\n"
8250 "pos:\n\t"
8251 "DIV $tmp\n\t"
8252 "XCHG EAX,$tmp2\n"
8253 "fast:\n\t"
8254 "DIV $tmp\n"
8255 "done:\n\t"
8256 "MOV EDX,$tmp2\n\t"
8257 "NEG EDX:EAX # if $imm < 0" %}
8258 ins_encode %{
8259 int con = (int)$imm$$constant;
8260 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8261 int pcon = (con > 0) ? con : -con;
8262 Label Lfast, Lpos, Ldone;
8263
8264 __ movl($tmp$$Register, pcon);
8265 __ xorl($tmp2$$Register,$tmp2$$Register);
8266 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8267 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8268
8269 __ movl($tmp2$$Register, $dst$$Register); // save
8270 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8271 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8272 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8273
8274 // Negative dividend.
8275 // convert value to positive to use unsigned division
8276 __ lneg($dst$$Register, $tmp2$$Register);
8277 __ divl($tmp$$Register);
8278 __ xchgl($dst$$Register, $tmp2$$Register);
8279 __ divl($tmp$$Register);
8280 // revert result back to negative
8281 __ lneg($tmp2$$Register, $dst$$Register);
8282 __ jmpb(Ldone);
8283
8284 __ bind(Lpos);
8285 __ divl($tmp$$Register); // Use unsigned division
8286 __ xchgl($dst$$Register, $tmp2$$Register);
8287 // Fallthrow for final divide, tmp2 has 32 bit hi result
8288
8289 __ bind(Lfast);
8290 // fast path: src is positive
8291 __ divl($tmp$$Register); // Use unsigned division
8292
8293 __ bind(Ldone);
8294 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8295 if (con < 0) {
8296 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8297 }
8298 %}
8299 ins_pipe( pipe_slow );
8300 %}
8301
8302 // Remainder Register Long (remainder fit into 32 bits)
8303 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8304 match(Set dst (ModL dst imm));
8305 effect( TEMP tmp, TEMP tmp2, KILL cr );
8306 ins_cost(1000);
8307 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8308 "CMP $tmp,EDX\n\t"
8309 "JA,s fast\n\t"
8310 "MOV $tmp2,EAX\n\t"
8311 "MOV EAX,EDX\n\t"
8312 "MOV EDX,0\n\t"
8313 "JLE,s pos\n\t"
8314 "LNEG EAX : $tmp2\n\t"
8315 "DIV $tmp # unsigned division\n\t"
8316 "MOV EAX,$tmp2\n\t"
8317 "DIV $tmp\n\t"
8318 "NEG EDX\n\t"
8319 "JMP,s done\n"
8320 "pos:\n\t"
8321 "DIV $tmp\n\t"
8322 "MOV EAX,$tmp2\n"
8323 "fast:\n\t"
8324 "DIV $tmp\n"
8325 "done:\n\t"
8326 "MOV EAX,EDX\n\t"
8327 "SAR EDX,31\n\t" %}
8328 ins_encode %{
8329 int con = (int)$imm$$constant;
8330 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8331 int pcon = (con > 0) ? con : -con;
8332 Label Lfast, Lpos, Ldone;
8333
8334 __ movl($tmp$$Register, pcon);
8335 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8336 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8337
8338 __ movl($tmp2$$Register, $dst$$Register); // save
8339 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8340 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8341 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8342
8343 // Negative dividend.
8344 // convert value to positive to use unsigned division
8345 __ lneg($dst$$Register, $tmp2$$Register);
8346 __ divl($tmp$$Register);
8347 __ movl($dst$$Register, $tmp2$$Register);
8348 __ divl($tmp$$Register);
8349 // revert remainder back to negative
8350 __ negl(HIGH_FROM_LOW($dst$$Register));
8351 __ jmpb(Ldone);
8352
8353 __ bind(Lpos);
8354 __ divl($tmp$$Register);
8355 __ movl($dst$$Register, $tmp2$$Register);
8356
8357 __ bind(Lfast);
8358 // fast path: src is positive
8359 __ divl($tmp$$Register);
8360
8361 __ bind(Ldone);
8362 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8363 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8364
8365 %}
8366 ins_pipe( pipe_slow );
8367 %}
8368
8369 // Integer Shift Instructions
8370 // Shift Left by one
8371 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8372 match(Set dst (LShiftI dst shift));
8373 effect(KILL cr);
8374
8375 size(2);
8376 format %{ "SHL $dst,$shift" %}
8377 opcode(0xD1, 0x4); /* D1 /4 */
8378 ins_encode( OpcP, RegOpc( dst ) );
8379 ins_pipe( ialu_reg );
8380 %}
8381
8382 // Shift Left by 8-bit immediate
8383 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8384 match(Set dst (LShiftI dst shift));
8385 effect(KILL cr);
8386
8387 size(3);
8388 format %{ "SHL $dst,$shift" %}
8389 opcode(0xC1, 0x4); /* C1 /4 ib */
8390 ins_encode( RegOpcImm( dst, shift) );
8391 ins_pipe( ialu_reg );
8392 %}
8393
8394 // Shift Left by variable
8395 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8396 match(Set dst (LShiftI dst shift));
8397 effect(KILL cr);
8398
8399 size(2);
8400 format %{ "SHL $dst,$shift" %}
8401 opcode(0xD3, 0x4); /* D3 /4 */
8402 ins_encode( OpcP, RegOpc( dst ) );
8403 ins_pipe( ialu_reg_reg );
8404 %}
8405
8406 // Arithmetic shift right by one
8407 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8408 match(Set dst (RShiftI dst shift));
8409 effect(KILL cr);
8410
8411 size(2);
8412 format %{ "SAR $dst,$shift" %}
8413 opcode(0xD1, 0x7); /* D1 /7 */
8414 ins_encode( OpcP, RegOpc( dst ) );
8415 ins_pipe( ialu_reg );
8416 %}
8417
8418 // Arithmetic shift right by one
8419 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8420 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8421 effect(KILL cr);
8422 format %{ "SAR $dst,$shift" %}
8423 opcode(0xD1, 0x7); /* D1 /7 */
8424 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8425 ins_pipe( ialu_mem_imm );
8426 %}
8427
8428 // Arithmetic Shift Right by 8-bit immediate
8429 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8430 match(Set dst (RShiftI dst shift));
8431 effect(KILL cr);
8432
8433 size(3);
8434 format %{ "SAR $dst,$shift" %}
8435 opcode(0xC1, 0x7); /* C1 /7 ib */
8436 ins_encode( RegOpcImm( dst, shift ) );
8437 ins_pipe( ialu_mem_imm );
8438 %}
8439
8440 // Arithmetic Shift Right by 8-bit immediate
8441 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8442 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8443 effect(KILL cr);
8444
8445 format %{ "SAR $dst,$shift" %}
8446 opcode(0xC1, 0x7); /* C1 /7 ib */
8447 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8448 ins_pipe( ialu_mem_imm );
8449 %}
8450
8451 // Arithmetic Shift Right by variable
8452 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8453 match(Set dst (RShiftI dst shift));
8454 effect(KILL cr);
8455
8456 size(2);
8457 format %{ "SAR $dst,$shift" %}
8458 opcode(0xD3, 0x7); /* D3 /7 */
8459 ins_encode( OpcP, RegOpc( dst ) );
8460 ins_pipe( ialu_reg_reg );
8461 %}
8462
8463 // Logical shift right by one
8464 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8465 match(Set dst (URShiftI dst shift));
8466 effect(KILL cr);
8467
8468 size(2);
8469 format %{ "SHR $dst,$shift" %}
8470 opcode(0xD1, 0x5); /* D1 /5 */
8471 ins_encode( OpcP, RegOpc( dst ) );
8472 ins_pipe( ialu_reg );
8473 %}
8474
8475 // Logical Shift Right by 8-bit immediate
8476 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8477 match(Set dst (URShiftI dst shift));
8478 effect(KILL cr);
8479
8480 size(3);
8481 format %{ "SHR $dst,$shift" %}
8482 opcode(0xC1, 0x5); /* C1 /5 ib */
8483 ins_encode( RegOpcImm( dst, shift) );
8484 ins_pipe( ialu_reg );
8485 %}
8486
8487
8488 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8489 // This idiom is used by the compiler for the i2b bytecode.
8490 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8491 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8492
8493 size(3);
8494 format %{ "MOVSX $dst,$src :8" %}
8495 ins_encode %{
8496 __ movsbl($dst$$Register, $src$$Register);
8497 %}
8498 ins_pipe(ialu_reg_reg);
8499 %}
8500
8501 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8502 // This idiom is used by the compiler the i2s bytecode.
8503 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8504 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8505
8506 size(3);
8507 format %{ "MOVSX $dst,$src :16" %}
8508 ins_encode %{
8509 __ movswl($dst$$Register, $src$$Register);
8510 %}
8511 ins_pipe(ialu_reg_reg);
8512 %}
8513
8514
8515 // Logical Shift Right by variable
8516 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8517 match(Set dst (URShiftI dst shift));
8518 effect(KILL cr);
8519
8520 size(2);
8521 format %{ "SHR $dst,$shift" %}
8522 opcode(0xD3, 0x5); /* D3 /5 */
8523 ins_encode( OpcP, RegOpc( dst ) );
8524 ins_pipe( ialu_reg_reg );
8525 %}
8526
8527
8528 //----------Logical Instructions-----------------------------------------------
8529 //----------Integer Logical Instructions---------------------------------------
8530 // And Instructions
8531 // And Register with Register
8532 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8533 match(Set dst (AndI dst src));
8534 effect(KILL cr);
8535
8536 size(2);
8537 format %{ "AND $dst,$src" %}
8538 opcode(0x23);
8539 ins_encode( OpcP, RegReg( dst, src) );
8540 ins_pipe( ialu_reg_reg );
8541 %}
8542
8543 // And Register with Immediate
8544 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8545 match(Set dst (AndI dst src));
8546 effect(KILL cr);
8547
8548 format %{ "AND $dst,$src" %}
8549 opcode(0x81,0x04); /* Opcode 81 /4 */
8550 // ins_encode( RegImm( dst, src) );
8551 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8552 ins_pipe( ialu_reg );
8553 %}
8554
8555 // And Register with Memory
8556 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8557 match(Set dst (AndI dst (LoadI src)));
8558 effect(KILL cr);
8559
8560 ins_cost(125);
8561 format %{ "AND $dst,$src" %}
8562 opcode(0x23);
8563 ins_encode( OpcP, RegMem( dst, src) );
8564 ins_pipe( ialu_reg_mem );
8565 %}
8566
8567 // And Memory with Register
8568 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8569 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8570 effect(KILL cr);
8571
8572 ins_cost(150);
8573 format %{ "AND $dst,$src" %}
8574 opcode(0x21); /* Opcode 21 /r */
8575 ins_encode( OpcP, RegMem( src, dst ) );
8576 ins_pipe( ialu_mem_reg );
8577 %}
8578
8579 // And Memory with Immediate
8580 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8581 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8582 effect(KILL cr);
8583
8584 ins_cost(125);
8585 format %{ "AND $dst,$src" %}
8586 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8587 // ins_encode( MemImm( dst, src) );
8588 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8589 ins_pipe( ialu_mem_imm );
8590 %}
8591
8592 // Or Instructions
8593 // Or Register with Register
8594 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8595 match(Set dst (OrI dst src));
8596 effect(KILL cr);
8597
8598 size(2);
8599 format %{ "OR $dst,$src" %}
8600 opcode(0x0B);
8601 ins_encode( OpcP, RegReg( dst, src) );
8602 ins_pipe( ialu_reg_reg );
8603 %}
8604
8605 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8606 match(Set dst (OrI dst (CastP2X src)));
8607 effect(KILL cr);
8608
8609 size(2);
8610 format %{ "OR $dst,$src" %}
8611 opcode(0x0B);
8612 ins_encode( OpcP, RegReg( dst, src) );
8613 ins_pipe( ialu_reg_reg );
8614 %}
8615
8616
8617 // Or Register with Immediate
8618 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8619 match(Set dst (OrI dst src));
8620 effect(KILL cr);
8621
8622 format %{ "OR $dst,$src" %}
8623 opcode(0x81,0x01); /* Opcode 81 /1 id */
8624 // ins_encode( RegImm( dst, src) );
8625 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8626 ins_pipe( ialu_reg );
8627 %}
8628
8629 // Or Register with Memory
8630 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8631 match(Set dst (OrI dst (LoadI src)));
8632 effect(KILL cr);
8633
8634 ins_cost(125);
8635 format %{ "OR $dst,$src" %}
8636 opcode(0x0B);
8637 ins_encode( OpcP, RegMem( dst, src) );
8638 ins_pipe( ialu_reg_mem );
8639 %}
8640
8641 // Or Memory with Register
8642 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8643 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8644 effect(KILL cr);
8645
8646 ins_cost(150);
8647 format %{ "OR $dst,$src" %}
8648 opcode(0x09); /* Opcode 09 /r */
8649 ins_encode( OpcP, RegMem( src, dst ) );
8650 ins_pipe( ialu_mem_reg );
8651 %}
8652
8653 // Or Memory with Immediate
8654 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8655 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8656 effect(KILL cr);
8657
8658 ins_cost(125);
8659 format %{ "OR $dst,$src" %}
8660 opcode(0x81,0x1); /* Opcode 81 /1 id */
8661 // ins_encode( MemImm( dst, src) );
8662 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8663 ins_pipe( ialu_mem_imm );
8664 %}
8665
8666 // ROL/ROR
8667 // ROL expand
8668 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8669 effect(USE_DEF dst, USE shift, KILL cr);
8670
8671 format %{ "ROL $dst, $shift" %}
8672 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8673 ins_encode( OpcP, RegOpc( dst ));
8674 ins_pipe( ialu_reg );
8675 %}
8676
8677 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8678 effect(USE_DEF dst, USE shift, KILL cr);
8679
8680 format %{ "ROL $dst, $shift" %}
8681 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8682 ins_encode( RegOpcImm(dst, shift) );
8683 ins_pipe(ialu_reg);
8684 %}
8685
8686 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8687 effect(USE_DEF dst, USE shift, KILL cr);
8688
8689 format %{ "ROL $dst, $shift" %}
8690 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8691 ins_encode(OpcP, RegOpc(dst));
8692 ins_pipe( ialu_reg_reg );
8693 %}
8694 // end of ROL expand
8695
8696 // ROL 32bit by one once
8697 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8698 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8699
8700 expand %{
8701 rolI_eReg_imm1(dst, lshift, cr);
8702 %}
8703 %}
8704
8705 // ROL 32bit var by imm8 once
8706 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8707 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8708 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8709
8710 expand %{
8711 rolI_eReg_imm8(dst, lshift, cr);
8712 %}
8713 %}
8714
8715 // ROL 32bit var by var once
8716 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8717 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8718
8719 expand %{
8720 rolI_eReg_CL(dst, shift, cr);
8721 %}
8722 %}
8723
8724 // ROL 32bit var by var once
8725 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8726 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8727
8728 expand %{
8729 rolI_eReg_CL(dst, shift, cr);
8730 %}
8731 %}
8732
8733 // ROR expand
8734 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8735 effect(USE_DEF dst, USE shift, KILL cr);
8736
8737 format %{ "ROR $dst, $shift" %}
8738 opcode(0xD1,0x1); /* Opcode D1 /1 */
8739 ins_encode( OpcP, RegOpc( dst ) );
8740 ins_pipe( ialu_reg );
8741 %}
8742
8743 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8744 effect (USE_DEF dst, USE shift, KILL cr);
8745
8746 format %{ "ROR $dst, $shift" %}
8747 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8748 ins_encode( RegOpcImm(dst, shift) );
8749 ins_pipe( ialu_reg );
8750 %}
8751
8752 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8753 effect(USE_DEF dst, USE shift, KILL cr);
8754
8755 format %{ "ROR $dst, $shift" %}
8756 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8757 ins_encode(OpcP, RegOpc(dst));
8758 ins_pipe( ialu_reg_reg );
8759 %}
8760 // end of ROR expand
8761
8762 // ROR right once
8763 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8764 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8765
8766 expand %{
8767 rorI_eReg_imm1(dst, rshift, cr);
8768 %}
8769 %}
8770
8771 // ROR 32bit by immI8 once
8772 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8773 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8774 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8775
8776 expand %{
8777 rorI_eReg_imm8(dst, rshift, cr);
8778 %}
8779 %}
8780
8781 // ROR 32bit var by var once
8782 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8783 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8784
8785 expand %{
8786 rorI_eReg_CL(dst, shift, cr);
8787 %}
8788 %}
8789
8790 // ROR 32bit var by var once
8791 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8792 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8793
8794 expand %{
8795 rorI_eReg_CL(dst, shift, cr);
8796 %}
8797 %}
8798
8799 // Xor Instructions
8800 // Xor Register with Register
8801 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8802 match(Set dst (XorI dst src));
8803 effect(KILL cr);
8804
8805 size(2);
8806 format %{ "XOR $dst,$src" %}
8807 opcode(0x33);
8808 ins_encode( OpcP, RegReg( dst, src) );
8809 ins_pipe( ialu_reg_reg );
8810 %}
8811
8812 // Xor Register with Immediate -1
8813 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8814 match(Set dst (XorI dst imm));
8815
8816 size(2);
8817 format %{ "NOT $dst" %}
8818 ins_encode %{
8819 __ notl($dst$$Register);
8820 %}
8821 ins_pipe( ialu_reg );
8822 %}
8823
8824 // Xor Register with Immediate
8825 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8826 match(Set dst (XorI dst src));
8827 effect(KILL cr);
8828
8829 format %{ "XOR $dst,$src" %}
8830 opcode(0x81,0x06); /* Opcode 81 /6 id */
8831 // ins_encode( RegImm( dst, src) );
8832 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8833 ins_pipe( ialu_reg );
8834 %}
8835
8836 // Xor Register with Memory
8837 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8838 match(Set dst (XorI dst (LoadI src)));
8839 effect(KILL cr);
8840
8841 ins_cost(125);
8842 format %{ "XOR $dst,$src" %}
8843 opcode(0x33);
8844 ins_encode( OpcP, RegMem(dst, src) );
8845 ins_pipe( ialu_reg_mem );
8846 %}
8847
8848 // Xor Memory with Register
8849 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8850 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8851 effect(KILL cr);
8852
8853 ins_cost(150);
8854 format %{ "XOR $dst,$src" %}
8855 opcode(0x31); /* Opcode 31 /r */
8856 ins_encode( OpcP, RegMem( src, dst ) );
8857 ins_pipe( ialu_mem_reg );
8858 %}
8859
8860 // Xor Memory with Immediate
8861 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8862 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8863 effect(KILL cr);
8864
8865 ins_cost(125);
8866 format %{ "XOR $dst,$src" %}
8867 opcode(0x81,0x6); /* Opcode 81 /6 id */
8868 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8869 ins_pipe( ialu_mem_imm );
8870 %}
8871
8872 //----------Convert Int to Boolean---------------------------------------------
8873
8874 instruct movI_nocopy(rRegI dst, rRegI src) %{
8875 effect( DEF dst, USE src );
8876 format %{ "MOV $dst,$src" %}
8877 ins_encode( enc_Copy( dst, src) );
8878 ins_pipe( ialu_reg_reg );
8879 %}
8880
8881 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8882 effect( USE_DEF dst, USE src, KILL cr );
8883
8884 size(4);
8885 format %{ "NEG $dst\n\t"
8886 "ADC $dst,$src" %}
8887 ins_encode( neg_reg(dst),
8888 OpcRegReg(0x13,dst,src) );
8889 ins_pipe( ialu_reg_reg_long );
8890 %}
8891
8892 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8893 match(Set dst (Conv2B src));
8894
8895 expand %{
8896 movI_nocopy(dst,src);
8897 ci2b(dst,src,cr);
8898 %}
8899 %}
8900
8901 instruct movP_nocopy(rRegI dst, eRegP src) %{
8902 effect( DEF dst, USE src );
8903 format %{ "MOV $dst,$src" %}
8904 ins_encode( enc_Copy( dst, src) );
8905 ins_pipe( ialu_reg_reg );
8906 %}
8907
8908 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8909 effect( USE_DEF dst, USE src, KILL cr );
8910 format %{ "NEG $dst\n\t"
8911 "ADC $dst,$src" %}
8912 ins_encode( neg_reg(dst),
8913 OpcRegReg(0x13,dst,src) );
8914 ins_pipe( ialu_reg_reg_long );
8915 %}
8916
8917 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8918 match(Set dst (Conv2B src));
8919
8920 expand %{
8921 movP_nocopy(dst,src);
8922 cp2b(dst,src,cr);
8923 %}
8924 %}
8925
8926 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8927 match(Set dst (CmpLTMask p q));
8928 effect( KILL cr );
8929 ins_cost(400);
8930
8931 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8932 format %{ "XOR $dst,$dst\n\t"
8933 "CMP $p,$q\n\t"
8934 "SETlt $dst\n\t"
8935 "NEG $dst" %}
8936 ins_encode( OpcRegReg(0x33,dst,dst),
8937 OpcRegReg(0x3B,p,q),
8938 setLT_reg(dst), neg_reg(dst) );
8939 ins_pipe( pipe_slow );
8940 %}
8941
8942 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8943 match(Set dst (CmpLTMask dst zero));
8944 effect( DEF dst, KILL cr );
8945 ins_cost(100);
8946
8947 format %{ "SAR $dst,31" %}
8948 opcode(0xC1, 0x7); /* C1 /7 ib */
8949 ins_encode( RegOpcImm( dst, 0x1F ) );
8950 ins_pipe( ialu_reg );
8951 %}
8952
8953
8954 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8955 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8956 effect( KILL tmp, KILL cr );
8957 ins_cost(400);
8958 // annoyingly, $tmp has no edges so you cant ask for it in
8959 // any format or encoding
8960 format %{ "SUB $p,$q\n\t"
8961 "SBB ECX,ECX\n\t"
8962 "AND ECX,$y\n\t"
8963 "ADD $p,ECX" %}
8964 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8965 ins_pipe( pipe_cmplt );
8966 %}
8967
8968 /* If I enable this, I encourage spilling in the inner loop of compress.
8969 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8970 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8971 effect( USE_KILL tmp, KILL cr );
8972 ins_cost(400);
8973
8974 format %{ "SUB $p,$q\n\t"
8975 "SBB ECX,ECX\n\t"
8976 "AND ECX,$y\n\t"
8977 "ADD $p,ECX" %}
8978 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8979 %}
8980 */
8981
8982 //----------Long Instructions------------------------------------------------
8983 // Add Long Register with Register
8984 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8985 match(Set dst (AddL dst src));
8986 effect(KILL cr);
8987 ins_cost(200);
8988 format %{ "ADD $dst.lo,$src.lo\n\t"
8989 "ADC $dst.hi,$src.hi" %}
8990 opcode(0x03, 0x13);
8991 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8992 ins_pipe( ialu_reg_reg_long );
8993 %}
8994
8995 // Add Long Register with Immediate
8996 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8997 match(Set dst (AddL dst src));
8998 effect(KILL cr);
8999 format %{ "ADD $dst.lo,$src.lo\n\t"
9000 "ADC $dst.hi,$src.hi" %}
9001 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9002 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9003 ins_pipe( ialu_reg_long );
9004 %}
9005
9006 // Add Long Register with Memory
9007 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9008 match(Set dst (AddL dst (LoadL mem)));
9009 effect(KILL cr);
9010 ins_cost(125);
9011 format %{ "ADD $dst.lo,$mem\n\t"
9012 "ADC $dst.hi,$mem+4" %}
9013 opcode(0x03, 0x13);
9014 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9015 ins_pipe( ialu_reg_long_mem );
9016 %}
9017
9018 // Subtract Long Register with Register.
9019 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9020 match(Set dst (SubL dst src));
9021 effect(KILL cr);
9022 ins_cost(200);
9023 format %{ "SUB $dst.lo,$src.lo\n\t"
9024 "SBB $dst.hi,$src.hi" %}
9025 opcode(0x2B, 0x1B);
9026 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9027 ins_pipe( ialu_reg_reg_long );
9028 %}
9029
9030 // Subtract Long Register with Immediate
9031 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9032 match(Set dst (SubL dst src));
9033 effect(KILL cr);
9034 format %{ "SUB $dst.lo,$src.lo\n\t"
9035 "SBB $dst.hi,$src.hi" %}
9036 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9037 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9038 ins_pipe( ialu_reg_long );
9039 %}
9040
9041 // Subtract Long Register with Memory
9042 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9043 match(Set dst (SubL dst (LoadL mem)));
9044 effect(KILL cr);
9045 ins_cost(125);
9046 format %{ "SUB $dst.lo,$mem\n\t"
9047 "SBB $dst.hi,$mem+4" %}
9048 opcode(0x2B, 0x1B);
9049 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9050 ins_pipe( ialu_reg_long_mem );
9051 %}
9052
9053 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9054 match(Set dst (SubL zero dst));
9055 effect(KILL cr);
9056 ins_cost(300);
9057 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9058 ins_encode( neg_long(dst) );
9059 ins_pipe( ialu_reg_reg_long );
9060 %}
9061
9062 // And Long Register with Register
9063 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9064 match(Set dst (AndL dst src));
9065 effect(KILL cr);
9066 format %{ "AND $dst.lo,$src.lo\n\t"
9067 "AND $dst.hi,$src.hi" %}
9068 opcode(0x23,0x23);
9069 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9070 ins_pipe( ialu_reg_reg_long );
9071 %}
9072
9073 // And Long Register with Immediate
9074 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9075 match(Set dst (AndL dst src));
9076 effect(KILL cr);
9077 format %{ "AND $dst.lo,$src.lo\n\t"
9078 "AND $dst.hi,$src.hi" %}
9079 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9080 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9081 ins_pipe( ialu_reg_long );
9082 %}
9083
9084 // And Long Register with Memory
9085 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9086 match(Set dst (AndL dst (LoadL mem)));
9087 effect(KILL cr);
9088 ins_cost(125);
9089 format %{ "AND $dst.lo,$mem\n\t"
9090 "AND $dst.hi,$mem+4" %}
9091 opcode(0x23, 0x23);
9092 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9093 ins_pipe( ialu_reg_long_mem );
9094 %}
9095
9096 // Or Long Register with Register
9097 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9098 match(Set dst (OrL dst src));
9099 effect(KILL cr);
9100 format %{ "OR $dst.lo,$src.lo\n\t"
9101 "OR $dst.hi,$src.hi" %}
9102 opcode(0x0B,0x0B);
9103 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9104 ins_pipe( ialu_reg_reg_long );
9105 %}
9106
9107 // Or Long Register with Immediate
9108 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9109 match(Set dst (OrL dst src));
9110 effect(KILL cr);
9111 format %{ "OR $dst.lo,$src.lo\n\t"
9112 "OR $dst.hi,$src.hi" %}
9113 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9114 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9115 ins_pipe( ialu_reg_long );
9116 %}
9117
9118 // Or Long Register with Memory
9119 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9120 match(Set dst (OrL dst (LoadL mem)));
9121 effect(KILL cr);
9122 ins_cost(125);
9123 format %{ "OR $dst.lo,$mem\n\t"
9124 "OR $dst.hi,$mem+4" %}
9125 opcode(0x0B,0x0B);
9126 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9127 ins_pipe( ialu_reg_long_mem );
9128 %}
9129
9130 // Xor Long Register with Register
9131 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9132 match(Set dst (XorL dst src));
9133 effect(KILL cr);
9134 format %{ "XOR $dst.lo,$src.lo\n\t"
9135 "XOR $dst.hi,$src.hi" %}
9136 opcode(0x33,0x33);
9137 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9138 ins_pipe( ialu_reg_reg_long );
9139 %}
9140
9141 // Xor Long Register with Immediate -1
9142 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9143 match(Set dst (XorL dst imm));
9144 format %{ "NOT $dst.lo\n\t"
9145 "NOT $dst.hi" %}
9146 ins_encode %{
9147 __ notl($dst$$Register);
9148 __ notl(HIGH_FROM_LOW($dst$$Register));
9149 %}
9150 ins_pipe( ialu_reg_long );
9151 %}
9152
9153 // Xor Long Register with Immediate
9154 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9155 match(Set dst (XorL dst src));
9156 effect(KILL cr);
9157 format %{ "XOR $dst.lo,$src.lo\n\t"
9158 "XOR $dst.hi,$src.hi" %}
9159 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9160 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9161 ins_pipe( ialu_reg_long );
9162 %}
9163
9164 // Xor Long Register with Memory
9165 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9166 match(Set dst (XorL dst (LoadL mem)));
9167 effect(KILL cr);
9168 ins_cost(125);
9169 format %{ "XOR $dst.lo,$mem\n\t"
9170 "XOR $dst.hi,$mem+4" %}
9171 opcode(0x33,0x33);
9172 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9173 ins_pipe( ialu_reg_long_mem );
9174 %}
9175
9176 // Shift Left Long by 1
9177 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9178 predicate(UseNewLongLShift);
9179 match(Set dst (LShiftL dst cnt));
9180 effect(KILL cr);
9181 ins_cost(100);
9182 format %{ "ADD $dst.lo,$dst.lo\n\t"
9183 "ADC $dst.hi,$dst.hi" %}
9184 ins_encode %{
9185 __ addl($dst$$Register,$dst$$Register);
9186 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9187 %}
9188 ins_pipe( ialu_reg_long );
9189 %}
9190
9191 // Shift Left Long by 2
9192 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9193 predicate(UseNewLongLShift);
9194 match(Set dst (LShiftL dst cnt));
9195 effect(KILL cr);
9196 ins_cost(100);
9197 format %{ "ADD $dst.lo,$dst.lo\n\t"
9198 "ADC $dst.hi,$dst.hi\n\t"
9199 "ADD $dst.lo,$dst.lo\n\t"
9200 "ADC $dst.hi,$dst.hi" %}
9201 ins_encode %{
9202 __ addl($dst$$Register,$dst$$Register);
9203 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9204 __ addl($dst$$Register,$dst$$Register);
9205 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9206 %}
9207 ins_pipe( ialu_reg_long );
9208 %}
9209
9210 // Shift Left Long by 3
9211 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9212 predicate(UseNewLongLShift);
9213 match(Set dst (LShiftL dst cnt));
9214 effect(KILL cr);
9215 ins_cost(100);
9216 format %{ "ADD $dst.lo,$dst.lo\n\t"
9217 "ADC $dst.hi,$dst.hi\n\t"
9218 "ADD $dst.lo,$dst.lo\n\t"
9219 "ADC $dst.hi,$dst.hi\n\t"
9220 "ADD $dst.lo,$dst.lo\n\t"
9221 "ADC $dst.hi,$dst.hi" %}
9222 ins_encode %{
9223 __ addl($dst$$Register,$dst$$Register);
9224 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9225 __ addl($dst$$Register,$dst$$Register);
9226 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9227 __ addl($dst$$Register,$dst$$Register);
9228 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9229 %}
9230 ins_pipe( ialu_reg_long );
9231 %}
9232
9233 // Shift Left Long by 1-31
9234 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9235 match(Set dst (LShiftL dst cnt));
9236 effect(KILL cr);
9237 ins_cost(200);
9238 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9239 "SHL $dst.lo,$cnt" %}
9240 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9241 ins_encode( move_long_small_shift(dst,cnt) );
9242 ins_pipe( ialu_reg_long );
9243 %}
9244
9245 // Shift Left Long by 32-63
9246 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9247 match(Set dst (LShiftL dst cnt));
9248 effect(KILL cr);
9249 ins_cost(300);
9250 format %{ "MOV $dst.hi,$dst.lo\n"
9251 "\tSHL $dst.hi,$cnt-32\n"
9252 "\tXOR $dst.lo,$dst.lo" %}
9253 opcode(0xC1, 0x4); /* C1 /4 ib */
9254 ins_encode( move_long_big_shift_clr(dst,cnt) );
9255 ins_pipe( ialu_reg_long );
9256 %}
9257
9258 // Shift Left Long by variable
9259 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9260 match(Set dst (LShiftL dst shift));
9261 effect(KILL cr);
9262 ins_cost(500+200);
9263 size(17);
9264 format %{ "TEST $shift,32\n\t"
9265 "JEQ,s small\n\t"
9266 "MOV $dst.hi,$dst.lo\n\t"
9267 "XOR $dst.lo,$dst.lo\n"
9268 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9269 "SHL $dst.lo,$shift" %}
9270 ins_encode( shift_left_long( dst, shift ) );
9271 ins_pipe( pipe_slow );
9272 %}
9273
9274 // Shift Right Long by 1-31
9275 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9276 match(Set dst (URShiftL dst cnt));
9277 effect(KILL cr);
9278 ins_cost(200);
9279 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9280 "SHR $dst.hi,$cnt" %}
9281 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9282 ins_encode( move_long_small_shift(dst,cnt) );
9283 ins_pipe( ialu_reg_long );
9284 %}
9285
9286 // Shift Right Long by 32-63
9287 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9288 match(Set dst (URShiftL dst cnt));
9289 effect(KILL cr);
9290 ins_cost(300);
9291 format %{ "MOV $dst.lo,$dst.hi\n"
9292 "\tSHR $dst.lo,$cnt-32\n"
9293 "\tXOR $dst.hi,$dst.hi" %}
9294 opcode(0xC1, 0x5); /* C1 /5 ib */
9295 ins_encode( move_long_big_shift_clr(dst,cnt) );
9296 ins_pipe( ialu_reg_long );
9297 %}
9298
9299 // Shift Right Long by variable
9300 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9301 match(Set dst (URShiftL dst shift));
9302 effect(KILL cr);
9303 ins_cost(600);
9304 size(17);
9305 format %{ "TEST $shift,32\n\t"
9306 "JEQ,s small\n\t"
9307 "MOV $dst.lo,$dst.hi\n\t"
9308 "XOR $dst.hi,$dst.hi\n"
9309 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9310 "SHR $dst.hi,$shift" %}
9311 ins_encode( shift_right_long( dst, shift ) );
9312 ins_pipe( pipe_slow );
9313 %}
9314
9315 // Shift Right Long by 1-31
9316 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9317 match(Set dst (RShiftL dst cnt));
9318 effect(KILL cr);
9319 ins_cost(200);
9320 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9321 "SAR $dst.hi,$cnt" %}
9322 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9323 ins_encode( move_long_small_shift(dst,cnt) );
9324 ins_pipe( ialu_reg_long );
9325 %}
9326
9327 // Shift Right Long by 32-63
9328 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9329 match(Set dst (RShiftL dst cnt));
9330 effect(KILL cr);
9331 ins_cost(300);
9332 format %{ "MOV $dst.lo,$dst.hi\n"
9333 "\tSAR $dst.lo,$cnt-32\n"
9334 "\tSAR $dst.hi,31" %}
9335 opcode(0xC1, 0x7); /* C1 /7 ib */
9336 ins_encode( move_long_big_shift_sign(dst,cnt) );
9337 ins_pipe( ialu_reg_long );
9338 %}
9339
9340 // Shift Right arithmetic Long by variable
9341 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9342 match(Set dst (RShiftL dst shift));
9343 effect(KILL cr);
9344 ins_cost(600);
9345 size(18);
9346 format %{ "TEST $shift,32\n\t"
9347 "JEQ,s small\n\t"
9348 "MOV $dst.lo,$dst.hi\n\t"
9349 "SAR $dst.hi,31\n"
9350 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9351 "SAR $dst.hi,$shift" %}
9352 ins_encode( shift_right_arith_long( dst, shift ) );
9353 ins_pipe( pipe_slow );
9354 %}
9355
9356
9357 //----------Double Instructions------------------------------------------------
9358 // Double Math
9359
9360 // Compare & branch
9361
9362 // P6 version of float compare, sets condition codes in EFLAGS
9363 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9364 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9365 match(Set cr (CmpD src1 src2));
9366 effect(KILL rax);
9367 ins_cost(150);
9368 format %{ "FLD $src1\n\t"
9369 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9370 "JNP exit\n\t"
9371 "MOV ah,1 // saw a NaN, set CF\n\t"
9372 "SAHF\n"
9373 "exit:\tNOP // avoid branch to branch" %}
9374 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9375 ins_encode( Push_Reg_DPR(src1),
9376 OpcP, RegOpc(src2),
9377 cmpF_P6_fixup );
9378 ins_pipe( pipe_slow );
9379 %}
9380
9381 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9382 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9383 match(Set cr (CmpD src1 src2));
9384 ins_cost(150);
9385 format %{ "FLD $src1\n\t"
9386 "FUCOMIP ST,$src2 // P6 instruction" %}
9387 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9388 ins_encode( Push_Reg_DPR(src1),
9389 OpcP, RegOpc(src2));
9390 ins_pipe( pipe_slow );
9391 %}
9392
9393 // Compare & branch
9394 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9395 predicate(UseSSE<=1);
9396 match(Set cr (CmpD src1 src2));
9397 effect(KILL rax);
9398 ins_cost(200);
9399 format %{ "FLD $src1\n\t"
9400 "FCOMp $src2\n\t"
9401 "FNSTSW AX\n\t"
9402 "TEST AX,0x400\n\t"
9403 "JZ,s flags\n\t"
9404 "MOV AH,1\t# unordered treat as LT\n"
9405 "flags:\tSAHF" %}
9406 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9407 ins_encode( Push_Reg_DPR(src1),
9408 OpcP, RegOpc(src2),
9409 fpu_flags);
9410 ins_pipe( pipe_slow );
9411 %}
9412
9413 // Compare vs zero into -1,0,1
9414 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9415 predicate(UseSSE<=1);
9416 match(Set dst (CmpD3 src1 zero));
9417 effect(KILL cr, KILL rax);
9418 ins_cost(280);
9419 format %{ "FTSTD $dst,$src1" %}
9420 opcode(0xE4, 0xD9);
9421 ins_encode( Push_Reg_DPR(src1),
9422 OpcS, OpcP, PopFPU,
9423 CmpF_Result(dst));
9424 ins_pipe( pipe_slow );
9425 %}
9426
9427 // Compare into -1,0,1
9428 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9429 predicate(UseSSE<=1);
9430 match(Set dst (CmpD3 src1 src2));
9431 effect(KILL cr, KILL rax);
9432 ins_cost(300);
9433 format %{ "FCMPD $dst,$src1,$src2" %}
9434 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9435 ins_encode( Push_Reg_DPR(src1),
9436 OpcP, RegOpc(src2),
9437 CmpF_Result(dst));
9438 ins_pipe( pipe_slow );
9439 %}
9440
9441 // float compare and set condition codes in EFLAGS by XMM regs
9442 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9443 predicate(UseSSE>=2);
9444 match(Set cr (CmpD src1 src2));
9445 ins_cost(145);
9446 format %{ "UCOMISD $src1,$src2\n\t"
9447 "JNP,s exit\n\t"
9448 "PUSHF\t# saw NaN, set CF\n\t"
9449 "AND [rsp], #0xffffff2b\n\t"
9450 "POPF\n"
9451 "exit:" %}
9452 ins_encode %{
9453 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9454 emit_cmpfp_fixup(_masm);
9455 %}
9456 ins_pipe( pipe_slow );
9457 %}
9458
9459 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9460 predicate(UseSSE>=2);
9461 match(Set cr (CmpD src1 src2));
9462 ins_cost(100);
9463 format %{ "UCOMISD $src1,$src2" %}
9464 ins_encode %{
9465 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9466 %}
9467 ins_pipe( pipe_slow );
9468 %}
9469
9470 // float compare and set condition codes in EFLAGS by XMM regs
9471 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9472 predicate(UseSSE>=2);
9473 match(Set cr (CmpD src1 (LoadD src2)));
9474 ins_cost(145);
9475 format %{ "UCOMISD $src1,$src2\n\t"
9476 "JNP,s exit\n\t"
9477 "PUSHF\t# saw NaN, set CF\n\t"
9478 "AND [rsp], #0xffffff2b\n\t"
9479 "POPF\n"
9480 "exit:" %}
9481 ins_encode %{
9482 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9483 emit_cmpfp_fixup(_masm);
9484 %}
9485 ins_pipe( pipe_slow );
9486 %}
9487
9488 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9489 predicate(UseSSE>=2);
9490 match(Set cr (CmpD src1 (LoadD src2)));
9491 ins_cost(100);
9492 format %{ "UCOMISD $src1,$src2" %}
9493 ins_encode %{
9494 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9495 %}
9496 ins_pipe( pipe_slow );
9497 %}
9498
9499 // Compare into -1,0,1 in XMM
9500 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9501 predicate(UseSSE>=2);
9502 match(Set dst (CmpD3 src1 src2));
9503 effect(KILL cr);
9504 ins_cost(255);
9505 format %{ "UCOMISD $src1, $src2\n\t"
9506 "MOV $dst, #-1\n\t"
9507 "JP,s done\n\t"
9508 "JB,s done\n\t"
9509 "SETNE $dst\n\t"
9510 "MOVZB $dst, $dst\n"
9511 "done:" %}
9512 ins_encode %{
9513 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9514 emit_cmpfp3(_masm, $dst$$Register);
9515 %}
9516 ins_pipe( pipe_slow );
9517 %}
9518
9519 // Compare into -1,0,1 in XMM and memory
9520 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9521 predicate(UseSSE>=2);
9522 match(Set dst (CmpD3 src1 (LoadD src2)));
9523 effect(KILL cr);
9524 ins_cost(275);
9525 format %{ "UCOMISD $src1, $src2\n\t"
9526 "MOV $dst, #-1\n\t"
9527 "JP,s done\n\t"
9528 "JB,s done\n\t"
9529 "SETNE $dst\n\t"
9530 "MOVZB $dst, $dst\n"
9531 "done:" %}
9532 ins_encode %{
9533 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9534 emit_cmpfp3(_masm, $dst$$Register);
9535 %}
9536 ins_pipe( pipe_slow );
9537 %}
9538
9539
9540 instruct subDPR_reg(regDPR dst, regDPR src) %{
9541 predicate (UseSSE <=1);
9542 match(Set dst (SubD dst src));
9543
9544 format %{ "FLD $src\n\t"
9545 "DSUBp $dst,ST" %}
9546 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9547 ins_cost(150);
9548 ins_encode( Push_Reg_DPR(src),
9549 OpcP, RegOpc(dst) );
9550 ins_pipe( fpu_reg_reg );
9551 %}
9552
9553 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9554 predicate (UseSSE <=1);
9555 match(Set dst (RoundDouble (SubD src1 src2)));
9556 ins_cost(250);
9557
9558 format %{ "FLD $src2\n\t"
9559 "DSUB ST,$src1\n\t"
9560 "FSTP_D $dst\t# D-round" %}
9561 opcode(0xD8, 0x5);
9562 ins_encode( Push_Reg_DPR(src2),
9563 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9564 ins_pipe( fpu_mem_reg_reg );
9565 %}
9566
9567
9568 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9569 predicate (UseSSE <=1);
9570 match(Set dst (SubD dst (LoadD src)));
9571 ins_cost(150);
9572
9573 format %{ "FLD $src\n\t"
9574 "DSUBp $dst,ST" %}
9575 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9576 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9577 OpcP, RegOpc(dst) );
9578 ins_pipe( fpu_reg_mem );
9579 %}
9580
9581 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9582 predicate (UseSSE<=1);
9583 match(Set dst (AbsD src));
9584 ins_cost(100);
9585 format %{ "FABS" %}
9586 opcode(0xE1, 0xD9);
9587 ins_encode( OpcS, OpcP );
9588 ins_pipe( fpu_reg_reg );
9589 %}
9590
9591 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9592 predicate(UseSSE<=1);
9593 match(Set dst (NegD src));
9594 ins_cost(100);
9595 format %{ "FCHS" %}
9596 opcode(0xE0, 0xD9);
9597 ins_encode( OpcS, OpcP );
9598 ins_pipe( fpu_reg_reg );
9599 %}
9600
9601 instruct addDPR_reg(regDPR dst, regDPR src) %{
9602 predicate(UseSSE<=1);
9603 match(Set dst (AddD dst src));
9604 format %{ "FLD $src\n\t"
9605 "DADD $dst,ST" %}
9606 size(4);
9607 ins_cost(150);
9608 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9609 ins_encode( Push_Reg_DPR(src),
9610 OpcP, RegOpc(dst) );
9611 ins_pipe( fpu_reg_reg );
9612 %}
9613
9614
9615 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9616 predicate(UseSSE<=1);
9617 match(Set dst (RoundDouble (AddD src1 src2)));
9618 ins_cost(250);
9619
9620 format %{ "FLD $src2\n\t"
9621 "DADD ST,$src1\n\t"
9622 "FSTP_D $dst\t# D-round" %}
9623 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9624 ins_encode( Push_Reg_DPR(src2),
9625 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9626 ins_pipe( fpu_mem_reg_reg );
9627 %}
9628
9629
9630 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9631 predicate(UseSSE<=1);
9632 match(Set dst (AddD dst (LoadD src)));
9633 ins_cost(150);
9634
9635 format %{ "FLD $src\n\t"
9636 "DADDp $dst,ST" %}
9637 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9638 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9639 OpcP, RegOpc(dst) );
9640 ins_pipe( fpu_reg_mem );
9641 %}
9642
9643 // add-to-memory
9644 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9645 predicate(UseSSE<=1);
9646 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9647 ins_cost(150);
9648
9649 format %{ "FLD_D $dst\n\t"
9650 "DADD ST,$src\n\t"
9651 "FST_D $dst" %}
9652 opcode(0xDD, 0x0);
9653 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9654 Opcode(0xD8), RegOpc(src),
9655 set_instruction_start,
9656 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9657 ins_pipe( fpu_reg_mem );
9658 %}
9659
9660 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9661 predicate(UseSSE<=1);
9662 match(Set dst (AddD dst con));
9663 ins_cost(125);
9664 format %{ "FLD1\n\t"
9665 "DADDp $dst,ST" %}
9666 ins_encode %{
9667 __ fld1();
9668 __ faddp($dst$$reg);
9669 %}
9670 ins_pipe(fpu_reg);
9671 %}
9672
9673 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9674 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9675 match(Set dst (AddD dst con));
9676 ins_cost(200);
9677 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9678 "DADDp $dst,ST" %}
9679 ins_encode %{
9680 __ fld_d($constantaddress($con));
9681 __ faddp($dst$$reg);
9682 %}
9683 ins_pipe(fpu_reg_mem);
9684 %}
9685
9686 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9687 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9688 match(Set dst (RoundDouble (AddD src con)));
9689 ins_cost(200);
9690 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9691 "DADD ST,$src\n\t"
9692 "FSTP_D $dst\t# D-round" %}
9693 ins_encode %{
9694 __ fld_d($constantaddress($con));
9695 __ fadd($src$$reg);
9696 __ fstp_d(Address(rsp, $dst$$disp));
9697 %}
9698 ins_pipe(fpu_mem_reg_con);
9699 %}
9700
9701 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9702 predicate(UseSSE<=1);
9703 match(Set dst (MulD dst src));
9704 format %{ "FLD $src\n\t"
9705 "DMULp $dst,ST" %}
9706 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9707 ins_cost(150);
9708 ins_encode( Push_Reg_DPR(src),
9709 OpcP, RegOpc(dst) );
9710 ins_pipe( fpu_reg_reg );
9711 %}
9712
9713 // Strict FP instruction biases argument before multiply then
9714 // biases result to avoid double rounding of subnormals.
9715 //
9716 // scale arg1 by multiplying arg1 by 2^(-15360)
9717 // load arg2
9718 // multiply scaled arg1 by arg2
9719 // rescale product by 2^(15360)
9720 //
9721 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9722 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9723 match(Set dst (MulD dst src));
9724 ins_cost(1); // Select this instruction for all strict FP double multiplies
9725
9726 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9727 "DMULp $dst,ST\n\t"
9728 "FLD $src\n\t"
9729 "DMULp $dst,ST\n\t"
9730 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9731 "DMULp $dst,ST\n\t" %}
9732 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9733 ins_encode( strictfp_bias1(dst),
9734 Push_Reg_DPR(src),
9735 OpcP, RegOpc(dst),
9736 strictfp_bias2(dst) );
9737 ins_pipe( fpu_reg_reg );
9738 %}
9739
9740 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9741 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9742 match(Set dst (MulD dst con));
9743 ins_cost(200);
9744 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9745 "DMULp $dst,ST" %}
9746 ins_encode %{
9747 __ fld_d($constantaddress($con));
9748 __ fmulp($dst$$reg);
9749 %}
9750 ins_pipe(fpu_reg_mem);
9751 %}
9752
9753
9754 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9755 predicate( UseSSE<=1 );
9756 match(Set dst (MulD dst (LoadD src)));
9757 ins_cost(200);
9758 format %{ "FLD_D $src\n\t"
9759 "DMULp $dst,ST" %}
9760 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9761 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9762 OpcP, RegOpc(dst) );
9763 ins_pipe( fpu_reg_mem );
9764 %}
9765
9766 //
9767 // Cisc-alternate to reg-reg multiply
9768 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9769 predicate( UseSSE<=1 );
9770 match(Set dst (MulD src (LoadD mem)));
9771 ins_cost(250);
9772 format %{ "FLD_D $mem\n\t"
9773 "DMUL ST,$src\n\t"
9774 "FSTP_D $dst" %}
9775 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9776 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9777 OpcReg_FPR(src),
9778 Pop_Reg_DPR(dst) );
9779 ins_pipe( fpu_reg_reg_mem );
9780 %}
9781
9782
9783 // MACRO3 -- addDPR a mulDPR
9784 // This instruction is a '2-address' instruction in that the result goes
9785 // back to src2. This eliminates a move from the macro; possibly the
9786 // register allocator will have to add it back (and maybe not).
9787 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9788 predicate( UseSSE<=1 );
9789 match(Set src2 (AddD (MulD src0 src1) src2));
9790 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9791 "DMUL ST,$src1\n\t"
9792 "DADDp $src2,ST" %}
9793 ins_cost(250);
9794 opcode(0xDD); /* LoadD DD /0 */
9795 ins_encode( Push_Reg_FPR(src0),
9796 FMul_ST_reg(src1),
9797 FAddP_reg_ST(src2) );
9798 ins_pipe( fpu_reg_reg_reg );
9799 %}
9800
9801
9802 // MACRO3 -- subDPR a mulDPR
9803 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9804 predicate( UseSSE<=1 );
9805 match(Set src2 (SubD (MulD src0 src1) src2));
9806 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9807 "DMUL ST,$src1\n\t"
9808 "DSUBRp $src2,ST" %}
9809 ins_cost(250);
9810 ins_encode( Push_Reg_FPR(src0),
9811 FMul_ST_reg(src1),
9812 Opcode(0xDE), Opc_plus(0xE0,src2));
9813 ins_pipe( fpu_reg_reg_reg );
9814 %}
9815
9816
9817 instruct divDPR_reg(regDPR dst, regDPR src) %{
9818 predicate( UseSSE<=1 );
9819 match(Set dst (DivD dst src));
9820
9821 format %{ "FLD $src\n\t"
9822 "FDIVp $dst,ST" %}
9823 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9824 ins_cost(150);
9825 ins_encode( Push_Reg_DPR(src),
9826 OpcP, RegOpc(dst) );
9827 ins_pipe( fpu_reg_reg );
9828 %}
9829
9830 // Strict FP instruction biases argument before division then
9831 // biases result, to avoid double rounding of subnormals.
9832 //
9833 // scale dividend by multiplying dividend by 2^(-15360)
9834 // load divisor
9835 // divide scaled dividend by divisor
9836 // rescale quotient by 2^(15360)
9837 //
9838 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9839 predicate (UseSSE<=1);
9840 match(Set dst (DivD dst src));
9841 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9842 ins_cost(01);
9843
9844 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9845 "DMULp $dst,ST\n\t"
9846 "FLD $src\n\t"
9847 "FDIVp $dst,ST\n\t"
9848 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9849 "DMULp $dst,ST\n\t" %}
9850 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9851 ins_encode( strictfp_bias1(dst),
9852 Push_Reg_DPR(src),
9853 OpcP, RegOpc(dst),
9854 strictfp_bias2(dst) );
9855 ins_pipe( fpu_reg_reg );
9856 %}
9857
9858 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9859 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9860 match(Set dst (RoundDouble (DivD src1 src2)));
9861
9862 format %{ "FLD $src1\n\t"
9863 "FDIV ST,$src2\n\t"
9864 "FSTP_D $dst\t# D-round" %}
9865 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9866 ins_encode( Push_Reg_DPR(src1),
9867 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9868 ins_pipe( fpu_mem_reg_reg );
9869 %}
9870
9871
9872 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9873 predicate(UseSSE<=1);
9874 match(Set dst (ModD dst src));
9875 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9876
9877 format %{ "DMOD $dst,$src" %}
9878 ins_cost(250);
9879 ins_encode(Push_Reg_Mod_DPR(dst, src),
9880 emitModDPR(),
9881 Push_Result_Mod_DPR(src),
9882 Pop_Reg_DPR(dst));
9883 ins_pipe( pipe_slow );
9884 %}
9885
9886 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9887 predicate(UseSSE>=2);
9888 match(Set dst (ModD src0 src1));
9889 effect(KILL rax, KILL cr);
9890
9891 format %{ "SUB ESP,8\t # DMOD\n"
9892 "\tMOVSD [ESP+0],$src1\n"
9893 "\tFLD_D [ESP+0]\n"
9894 "\tMOVSD [ESP+0],$src0\n"
9895 "\tFLD_D [ESP+0]\n"
9896 "loop:\tFPREM\n"
9897 "\tFWAIT\n"
9898 "\tFNSTSW AX\n"
9899 "\tSAHF\n"
9900 "\tJP loop\n"
9901 "\tFSTP_D [ESP+0]\n"
9902 "\tMOVSD $dst,[ESP+0]\n"
9903 "\tADD ESP,8\n"
9904 "\tFSTP ST0\t # Restore FPU Stack"
9905 %}
9906 ins_cost(250);
9907 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9908 ins_pipe( pipe_slow );
9909 %}
9910
9911 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9912 predicate (UseSSE<=1);
9913 match(Set dst (SinD src));
9914 ins_cost(1800);
9915 format %{ "DSIN $dst" %}
9916 opcode(0xD9, 0xFE);
9917 ins_encode( OpcP, OpcS );
9918 ins_pipe( pipe_slow );
9919 %}
9920
9921 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9922 predicate (UseSSE>=2);
9923 match(Set dst (SinD dst));
9924 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9925 ins_cost(1800);
9926 format %{ "DSIN $dst" %}
9927 opcode(0xD9, 0xFE);
9928 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9929 ins_pipe( pipe_slow );
9930 %}
9931
9932 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9933 predicate (UseSSE<=1);
9934 match(Set dst (CosD src));
9935 ins_cost(1800);
9936 format %{ "DCOS $dst" %}
9937 opcode(0xD9, 0xFF);
9938 ins_encode( OpcP, OpcS );
9939 ins_pipe( pipe_slow );
9940 %}
9941
9942 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9943 predicate (UseSSE>=2);
9944 match(Set dst (CosD dst));
9945 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9946 ins_cost(1800);
9947 format %{ "DCOS $dst" %}
9948 opcode(0xD9, 0xFF);
9949 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9950 ins_pipe( pipe_slow );
9951 %}
9952
9953 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9954 predicate (UseSSE<=1);
9955 match(Set dst(TanD src));
9956 format %{ "DTAN $dst" %}
9957 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9958 Opcode(0xDD), Opcode(0xD8)); // fstp st
9959 ins_pipe( pipe_slow );
9960 %}
9961
9962 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9963 predicate (UseSSE>=2);
9964 match(Set dst(TanD dst));
9965 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9966 format %{ "DTAN $dst" %}
9967 ins_encode( Push_SrcD(dst),
9968 Opcode(0xD9), Opcode(0xF2), // fptan
9969 Opcode(0xDD), Opcode(0xD8), // fstp st
9970 Push_ResultD(dst) );
9971 ins_pipe( pipe_slow );
9972 %}
9973
9974 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9975 predicate (UseSSE<=1);
9976 match(Set dst(AtanD dst src));
9977 format %{ "DATA $dst,$src" %}
9978 opcode(0xD9, 0xF3);
9979 ins_encode( Push_Reg_DPR(src),
9980 OpcP, OpcS, RegOpc(dst) );
9981 ins_pipe( pipe_slow );
9982 %}
9983
9984 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9985 predicate (UseSSE>=2);
9986 match(Set dst(AtanD dst src));
9987 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9988 format %{ "DATA $dst,$src" %}
9989 opcode(0xD9, 0xF3);
9990 ins_encode( Push_SrcD(src),
9991 OpcP, OpcS, Push_ResultD(dst) );
9992 ins_pipe( pipe_slow );
9993 %}
9994
9995 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9996 predicate (UseSSE<=1);
9997 match(Set dst (SqrtD src));
9998 format %{ "DSQRT $dst,$src" %}
9999 opcode(0xFA, 0xD9);
10000 ins_encode( Push_Reg_DPR(src),
10001 OpcS, OpcP, Pop_Reg_DPR(dst) );
10002 ins_pipe( pipe_slow );
10003 %}
10004
10005 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10006 predicate (UseSSE<=1);
10007 match(Set Y (PowD X Y)); // Raise X to the Yth power
10008 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10009 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10010 ins_encode %{
10011 __ subptr(rsp, 8);
10012 __ fld_s($X$$reg - 1);
10013 __ fast_pow();
10014 __ addptr(rsp, 8);
10015 %}
10016 ins_pipe( pipe_slow );
10017 %}
10018
10019 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10020 predicate (UseSSE>=2);
10021 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10022 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10023 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10024 ins_encode %{
10025 __ subptr(rsp, 8);
10026 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10027 __ fld_d(Address(rsp, 0));
10028 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10029 __ fld_d(Address(rsp, 0));
10030 __ fast_pow();
10031 __ fstp_d(Address(rsp, 0));
10032 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10033 __ addptr(rsp, 8);
10034 %}
10035 ins_pipe( pipe_slow );
10036 %}
10037
10038
10039 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10040 predicate (UseSSE<=1);
10041 match(Set dpr1 (ExpD dpr1));
10042 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10043 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10044 ins_encode %{
10045 __ fast_exp();
10046 %}
10047 ins_pipe( pipe_slow );
10048 %}
10049
10050 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10051 predicate (UseSSE>=2);
10052 match(Set dst (ExpD src));
10053 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10054 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10055 ins_encode %{
10056 __ subptr(rsp, 8);
10057 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10058 __ fld_d(Address(rsp, 0));
10059 __ fast_exp();
10060 __ fstp_d(Address(rsp, 0));
10061 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10062 __ addptr(rsp, 8);
10063 %}
10064 ins_pipe( pipe_slow );
10065 %}
10066
10067 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10068 predicate (UseSSE<=1);
10069 // The source Double operand on FPU stack
10070 match(Set dst (Log10D src));
10071 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10072 // fxch ; swap ST(0) with ST(1)
10073 // fyl2x ; compute log_10(2) * log_2(x)
10074 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10075 "FXCH \n\t"
10076 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10077 %}
10078 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10079 Opcode(0xD9), Opcode(0xC9), // fxch
10080 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10081
10082 ins_pipe( pipe_slow );
10083 %}
10084
10085 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10086 predicate (UseSSE>=2);
10087 effect(KILL cr);
10088 match(Set dst (Log10D src));
10089 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10090 // fyl2x ; compute log_10(2) * log_2(x)
10091 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10092 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10093 %}
10094 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10095 Push_SrcD(src),
10096 Opcode(0xD9), Opcode(0xF1), // fyl2x
10097 Push_ResultD(dst));
10098
10099 ins_pipe( pipe_slow );
10100 %}
10101
10102 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10103 predicate (UseSSE<=1);
10104 // The source Double operand on FPU stack
10105 match(Set dst (LogD src));
10106 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10107 // fxch ; swap ST(0) with ST(1)
10108 // fyl2x ; compute log_e(2) * log_2(x)
10109 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10110 "FXCH \n\t"
10111 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10112 %}
10113 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10114 Opcode(0xD9), Opcode(0xC9), // fxch
10115 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10116
10117 ins_pipe( pipe_slow );
10118 %}
10119
10120 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10121 predicate (UseSSE>=2);
10122 effect(KILL cr);
10123 // The source and result Double operands in XMM registers
10124 match(Set dst (LogD src));
10125 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10126 // fyl2x ; compute log_e(2) * log_2(x)
10127 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10128 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10129 %}
10130 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10131 Push_SrcD(src),
10132 Opcode(0xD9), Opcode(0xF1), // fyl2x
10133 Push_ResultD(dst));
10134 ins_pipe( pipe_slow );
10135 %}
10136
10137 //-------------Float Instructions-------------------------------
10138 // Float Math
10139
10140 // Code for float compare:
10141 // fcompp();
10142 // fwait(); fnstsw_ax();
10143 // sahf();
10144 // movl(dst, unordered_result);
10145 // jcc(Assembler::parity, exit);
10146 // movl(dst, less_result);
10147 // jcc(Assembler::below, exit);
10148 // movl(dst, equal_result);
10149 // jcc(Assembler::equal, exit);
10150 // movl(dst, greater_result);
10151 // exit:
10152
10153 // P6 version of float compare, sets condition codes in EFLAGS
10154 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10155 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10156 match(Set cr (CmpF src1 src2));
10157 effect(KILL rax);
10158 ins_cost(150);
10159 format %{ "FLD $src1\n\t"
10160 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10161 "JNP exit\n\t"
10162 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10163 "SAHF\n"
10164 "exit:\tNOP // avoid branch to branch" %}
10165 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10166 ins_encode( Push_Reg_DPR(src1),
10167 OpcP, RegOpc(src2),
10168 cmpF_P6_fixup );
10169 ins_pipe( pipe_slow );
10170 %}
10171
10172 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10173 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10174 match(Set cr (CmpF src1 src2));
10175 ins_cost(100);
10176 format %{ "FLD $src1\n\t"
10177 "FUCOMIP ST,$src2 // P6 instruction" %}
10178 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10179 ins_encode( Push_Reg_DPR(src1),
10180 OpcP, RegOpc(src2));
10181 ins_pipe( pipe_slow );
10182 %}
10183
10184
10185 // Compare & branch
10186 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10187 predicate(UseSSE == 0);
10188 match(Set cr (CmpF src1 src2));
10189 effect(KILL rax);
10190 ins_cost(200);
10191 format %{ "FLD $src1\n\t"
10192 "FCOMp $src2\n\t"
10193 "FNSTSW AX\n\t"
10194 "TEST AX,0x400\n\t"
10195 "JZ,s flags\n\t"
10196 "MOV AH,1\t# unordered treat as LT\n"
10197 "flags:\tSAHF" %}
10198 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10199 ins_encode( Push_Reg_DPR(src1),
10200 OpcP, RegOpc(src2),
10201 fpu_flags);
10202 ins_pipe( pipe_slow );
10203 %}
10204
10205 // Compare vs zero into -1,0,1
10206 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10207 predicate(UseSSE == 0);
10208 match(Set dst (CmpF3 src1 zero));
10209 effect(KILL cr, KILL rax);
10210 ins_cost(280);
10211 format %{ "FTSTF $dst,$src1" %}
10212 opcode(0xE4, 0xD9);
10213 ins_encode( Push_Reg_DPR(src1),
10214 OpcS, OpcP, PopFPU,
10215 CmpF_Result(dst));
10216 ins_pipe( pipe_slow );
10217 %}
10218
10219 // Compare into -1,0,1
10220 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10221 predicate(UseSSE == 0);
10222 match(Set dst (CmpF3 src1 src2));
10223 effect(KILL cr, KILL rax);
10224 ins_cost(300);
10225 format %{ "FCMPF $dst,$src1,$src2" %}
10226 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10227 ins_encode( Push_Reg_DPR(src1),
10228 OpcP, RegOpc(src2),
10229 CmpF_Result(dst));
10230 ins_pipe( pipe_slow );
10231 %}
10232
10233 // float compare and set condition codes in EFLAGS by XMM regs
10234 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10235 predicate(UseSSE>=1);
10236 match(Set cr (CmpF src1 src2));
10237 ins_cost(145);
10238 format %{ "UCOMISS $src1,$src2\n\t"
10239 "JNP,s exit\n\t"
10240 "PUSHF\t# saw NaN, set CF\n\t"
10241 "AND [rsp], #0xffffff2b\n\t"
10242 "POPF\n"
10243 "exit:" %}
10244 ins_encode %{
10245 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10246 emit_cmpfp_fixup(_masm);
10247 %}
10248 ins_pipe( pipe_slow );
10249 %}
10250
10251 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10252 predicate(UseSSE>=1);
10253 match(Set cr (CmpF src1 src2));
10254 ins_cost(100);
10255 format %{ "UCOMISS $src1,$src2" %}
10256 ins_encode %{
10257 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10258 %}
10259 ins_pipe( pipe_slow );
10260 %}
10261
10262 // float compare and set condition codes in EFLAGS by XMM regs
10263 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10264 predicate(UseSSE>=1);
10265 match(Set cr (CmpF src1 (LoadF src2)));
10266 ins_cost(165);
10267 format %{ "UCOMISS $src1,$src2\n\t"
10268 "JNP,s exit\n\t"
10269 "PUSHF\t# saw NaN, set CF\n\t"
10270 "AND [rsp], #0xffffff2b\n\t"
10271 "POPF\n"
10272 "exit:" %}
10273 ins_encode %{
10274 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10275 emit_cmpfp_fixup(_masm);
10276 %}
10277 ins_pipe( pipe_slow );
10278 %}
10279
10280 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10281 predicate(UseSSE>=1);
10282 match(Set cr (CmpF src1 (LoadF src2)));
10283 ins_cost(100);
10284 format %{ "UCOMISS $src1,$src2" %}
10285 ins_encode %{
10286 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10287 %}
10288 ins_pipe( pipe_slow );
10289 %}
10290
10291 // Compare into -1,0,1 in XMM
10292 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10293 predicate(UseSSE>=1);
10294 match(Set dst (CmpF3 src1 src2));
10295 effect(KILL cr);
10296 ins_cost(255);
10297 format %{ "UCOMISS $src1, $src2\n\t"
10298 "MOV $dst, #-1\n\t"
10299 "JP,s done\n\t"
10300 "JB,s done\n\t"
10301 "SETNE $dst\n\t"
10302 "MOVZB $dst, $dst\n"
10303 "done:" %}
10304 ins_encode %{
10305 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10306 emit_cmpfp3(_masm, $dst$$Register);
10307 %}
10308 ins_pipe( pipe_slow );
10309 %}
10310
10311 // Compare into -1,0,1 in XMM and memory
10312 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10313 predicate(UseSSE>=1);
10314 match(Set dst (CmpF3 src1 (LoadF src2)));
10315 effect(KILL cr);
10316 ins_cost(275);
10317 format %{ "UCOMISS $src1, $src2\n\t"
10318 "MOV $dst, #-1\n\t"
10319 "JP,s done\n\t"
10320 "JB,s done\n\t"
10321 "SETNE $dst\n\t"
10322 "MOVZB $dst, $dst\n"
10323 "done:" %}
10324 ins_encode %{
10325 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10326 emit_cmpfp3(_masm, $dst$$Register);
10327 %}
10328 ins_pipe( pipe_slow );
10329 %}
10330
10331 // Spill to obtain 24-bit precision
10332 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10333 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10334 match(Set dst (SubF src1 src2));
10335
10336 format %{ "FSUB $dst,$src1 - $src2" %}
10337 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10338 ins_encode( Push_Reg_FPR(src1),
10339 OpcReg_FPR(src2),
10340 Pop_Mem_FPR(dst) );
10341 ins_pipe( fpu_mem_reg_reg );
10342 %}
10343 //
10344 // This instruction does not round to 24-bits
10345 instruct subFPR_reg(regFPR dst, regFPR src) %{
10346 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10347 match(Set dst (SubF dst src));
10348
10349 format %{ "FSUB $dst,$src" %}
10350 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10351 ins_encode( Push_Reg_FPR(src),
10352 OpcP, RegOpc(dst) );
10353 ins_pipe( fpu_reg_reg );
10354 %}
10355
10356 // Spill to obtain 24-bit precision
10357 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10358 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10359 match(Set dst (AddF src1 src2));
10360
10361 format %{ "FADD $dst,$src1,$src2" %}
10362 opcode(0xD8, 0x0); /* D8 C0+i */
10363 ins_encode( Push_Reg_FPR(src2),
10364 OpcReg_FPR(src1),
10365 Pop_Mem_FPR(dst) );
10366 ins_pipe( fpu_mem_reg_reg );
10367 %}
10368 //
10369 // This instruction does not round to 24-bits
10370 instruct addFPR_reg(regFPR dst, regFPR src) %{
10371 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10372 match(Set dst (AddF dst src));
10373
10374 format %{ "FLD $src\n\t"
10375 "FADDp $dst,ST" %}
10376 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10377 ins_encode( Push_Reg_FPR(src),
10378 OpcP, RegOpc(dst) );
10379 ins_pipe( fpu_reg_reg );
10380 %}
10381
10382 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10383 predicate(UseSSE==0);
10384 match(Set dst (AbsF src));
10385 ins_cost(100);
10386 format %{ "FABS" %}
10387 opcode(0xE1, 0xD9);
10388 ins_encode( OpcS, OpcP );
10389 ins_pipe( fpu_reg_reg );
10390 %}
10391
10392 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10393 predicate(UseSSE==0);
10394 match(Set dst (NegF src));
10395 ins_cost(100);
10396 format %{ "FCHS" %}
10397 opcode(0xE0, 0xD9);
10398 ins_encode( OpcS, OpcP );
10399 ins_pipe( fpu_reg_reg );
10400 %}
10401
10402 // Cisc-alternate to addFPR_reg
10403 // Spill to obtain 24-bit precision
10404 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10405 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10406 match(Set dst (AddF src1 (LoadF src2)));
10407
10408 format %{ "FLD $src2\n\t"
10409 "FADD ST,$src1\n\t"
10410 "FSTP_S $dst" %}
10411 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10412 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10413 OpcReg_FPR(src1),
10414 Pop_Mem_FPR(dst) );
10415 ins_pipe( fpu_mem_reg_mem );
10416 %}
10417 //
10418 // Cisc-alternate to addFPR_reg
10419 // This instruction does not round to 24-bits
10420 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10421 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10422 match(Set dst (AddF dst (LoadF src)));
10423
10424 format %{ "FADD $dst,$src" %}
10425 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10426 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10427 OpcP, RegOpc(dst) );
10428 ins_pipe( fpu_reg_mem );
10429 %}
10430
10431 // // Following two instructions for _222_mpegaudio
10432 // Spill to obtain 24-bit precision
10433 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10434 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10435 match(Set dst (AddF src1 src2));
10436
10437 format %{ "FADD $dst,$src1,$src2" %}
10438 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10439 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10440 OpcReg_FPR(src2),
10441 Pop_Mem_FPR(dst) );
10442 ins_pipe( fpu_mem_reg_mem );
10443 %}
10444
10445 // Cisc-spill variant
10446 // Spill to obtain 24-bit precision
10447 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10448 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10449 match(Set dst (AddF src1 (LoadF src2)));
10450
10451 format %{ "FADD $dst,$src1,$src2 cisc" %}
10452 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10453 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10454 set_instruction_start,
10455 OpcP, RMopc_Mem(secondary,src1),
10456 Pop_Mem_FPR(dst) );
10457 ins_pipe( fpu_mem_mem_mem );
10458 %}
10459
10460 // Spill to obtain 24-bit precision
10461 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10462 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10463 match(Set dst (AddF src1 src2));
10464
10465 format %{ "FADD $dst,$src1,$src2" %}
10466 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10467 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10468 set_instruction_start,
10469 OpcP, RMopc_Mem(secondary,src1),
10470 Pop_Mem_FPR(dst) );
10471 ins_pipe( fpu_mem_mem_mem );
10472 %}
10473
10474
10475 // Spill to obtain 24-bit precision
10476 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10477 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10478 match(Set dst (AddF src con));
10479 format %{ "FLD $src\n\t"
10480 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10481 "FSTP_S $dst" %}
10482 ins_encode %{
10483 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10484 __ fadd_s($constantaddress($con));
10485 __ fstp_s(Address(rsp, $dst$$disp));
10486 %}
10487 ins_pipe(fpu_mem_reg_con);
10488 %}
10489 //
10490 // This instruction does not round to 24-bits
10491 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10492 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10493 match(Set dst (AddF src con));
10494 format %{ "FLD $src\n\t"
10495 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10496 "FSTP $dst" %}
10497 ins_encode %{
10498 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10499 __ fadd_s($constantaddress($con));
10500 __ fstp_d($dst$$reg);
10501 %}
10502 ins_pipe(fpu_reg_reg_con);
10503 %}
10504
10505 // Spill to obtain 24-bit precision
10506 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10507 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10508 match(Set dst (MulF src1 src2));
10509
10510 format %{ "FLD $src1\n\t"
10511 "FMUL $src2\n\t"
10512 "FSTP_S $dst" %}
10513 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10514 ins_encode( Push_Reg_FPR(src1),
10515 OpcReg_FPR(src2),
10516 Pop_Mem_FPR(dst) );
10517 ins_pipe( fpu_mem_reg_reg );
10518 %}
10519 //
10520 // This instruction does not round to 24-bits
10521 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10522 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10523 match(Set dst (MulF src1 src2));
10524
10525 format %{ "FLD $src1\n\t"
10526 "FMUL $src2\n\t"
10527 "FSTP_S $dst" %}
10528 opcode(0xD8, 0x1); /* D8 C8+i */
10529 ins_encode( Push_Reg_FPR(src2),
10530 OpcReg_FPR(src1),
10531 Pop_Reg_FPR(dst) );
10532 ins_pipe( fpu_reg_reg_reg );
10533 %}
10534
10535
10536 // Spill to obtain 24-bit precision
10537 // Cisc-alternate to reg-reg multiply
10538 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10539 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10540 match(Set dst (MulF src1 (LoadF src2)));
10541
10542 format %{ "FLD_S $src2\n\t"
10543 "FMUL $src1\n\t"
10544 "FSTP_S $dst" %}
10545 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10546 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10547 OpcReg_FPR(src1),
10548 Pop_Mem_FPR(dst) );
10549 ins_pipe( fpu_mem_reg_mem );
10550 %}
10551 //
10552 // This instruction does not round to 24-bits
10553 // Cisc-alternate to reg-reg multiply
10554 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10555 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10556 match(Set dst (MulF src1 (LoadF src2)));
10557
10558 format %{ "FMUL $dst,$src1,$src2" %}
10559 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10560 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10561 OpcReg_FPR(src1),
10562 Pop_Reg_FPR(dst) );
10563 ins_pipe( fpu_reg_reg_mem );
10564 %}
10565
10566 // Spill to obtain 24-bit precision
10567 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10568 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10569 match(Set dst (MulF src1 src2));
10570
10571 format %{ "FMUL $dst,$src1,$src2" %}
10572 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10573 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10574 set_instruction_start,
10575 OpcP, RMopc_Mem(secondary,src1),
10576 Pop_Mem_FPR(dst) );
10577 ins_pipe( fpu_mem_mem_mem );
10578 %}
10579
10580 // Spill to obtain 24-bit precision
10581 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10582 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10583 match(Set dst (MulF src con));
10584
10585 format %{ "FLD $src\n\t"
10586 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10587 "FSTP_S $dst" %}
10588 ins_encode %{
10589 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10590 __ fmul_s($constantaddress($con));
10591 __ fstp_s(Address(rsp, $dst$$disp));
10592 %}
10593 ins_pipe(fpu_mem_reg_con);
10594 %}
10595 //
10596 // This instruction does not round to 24-bits
10597 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10598 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10599 match(Set dst (MulF src con));
10600
10601 format %{ "FLD $src\n\t"
10602 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10603 "FSTP $dst" %}
10604 ins_encode %{
10605 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10606 __ fmul_s($constantaddress($con));
10607 __ fstp_d($dst$$reg);
10608 %}
10609 ins_pipe(fpu_reg_reg_con);
10610 %}
10611
10612
10613 //
10614 // MACRO1 -- subsume unshared load into mulFPR
10615 // This instruction does not round to 24-bits
10616 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10617 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10618 match(Set dst (MulF (LoadF mem1) src));
10619
10620 format %{ "FLD $mem1 ===MACRO1===\n\t"
10621 "FMUL ST,$src\n\t"
10622 "FSTP $dst" %}
10623 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10624 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10625 OpcReg_FPR(src),
10626 Pop_Reg_FPR(dst) );
10627 ins_pipe( fpu_reg_reg_mem );
10628 %}
10629 //
10630 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10631 // This instruction does not round to 24-bits
10632 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10633 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10634 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10635 ins_cost(95);
10636
10637 format %{ "FLD $mem1 ===MACRO2===\n\t"
10638 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10639 "FADD ST,$src2\n\t"
10640 "FSTP $dst" %}
10641 opcode(0xD9); /* LoadF D9 /0 */
10642 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10643 FMul_ST_reg(src1),
10644 FAdd_ST_reg(src2),
10645 Pop_Reg_FPR(dst) );
10646 ins_pipe( fpu_reg_mem_reg_reg );
10647 %}
10648
10649 // MACRO3 -- addFPR a mulFPR
10650 // This instruction does not round to 24-bits. It is a '2-address'
10651 // instruction in that the result goes back to src2. This eliminates
10652 // a move from the macro; possibly the register allocator will have
10653 // to add it back (and maybe not).
10654 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10655 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10656 match(Set src2 (AddF (MulF src0 src1) src2));
10657
10658 format %{ "FLD $src0 ===MACRO3===\n\t"
10659 "FMUL ST,$src1\n\t"
10660 "FADDP $src2,ST" %}
10661 opcode(0xD9); /* LoadF D9 /0 */
10662 ins_encode( Push_Reg_FPR(src0),
10663 FMul_ST_reg(src1),
10664 FAddP_reg_ST(src2) );
10665 ins_pipe( fpu_reg_reg_reg );
10666 %}
10667
10668 // MACRO4 -- divFPR subFPR
10669 // This instruction does not round to 24-bits
10670 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10671 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10672 match(Set dst (DivF (SubF src2 src1) src3));
10673
10674 format %{ "FLD $src2 ===MACRO4===\n\t"
10675 "FSUB ST,$src1\n\t"
10676 "FDIV ST,$src3\n\t"
10677 "FSTP $dst" %}
10678 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10679 ins_encode( Push_Reg_FPR(src2),
10680 subFPR_divFPR_encode(src1,src3),
10681 Pop_Reg_FPR(dst) );
10682 ins_pipe( fpu_reg_reg_reg_reg );
10683 %}
10684
10685 // Spill to obtain 24-bit precision
10686 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10687 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10688 match(Set dst (DivF src1 src2));
10689
10690 format %{ "FDIV $dst,$src1,$src2" %}
10691 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10692 ins_encode( Push_Reg_FPR(src1),
10693 OpcReg_FPR(src2),
10694 Pop_Mem_FPR(dst) );
10695 ins_pipe( fpu_mem_reg_reg );
10696 %}
10697 //
10698 // This instruction does not round to 24-bits
10699 instruct divFPR_reg(regFPR dst, regFPR src) %{
10700 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10701 match(Set dst (DivF dst src));
10702
10703 format %{ "FDIV $dst,$src" %}
10704 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10705 ins_encode( Push_Reg_FPR(src),
10706 OpcP, RegOpc(dst) );
10707 ins_pipe( fpu_reg_reg );
10708 %}
10709
10710
10711 // Spill to obtain 24-bit precision
10712 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10713 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10714 match(Set dst (ModF src1 src2));
10715 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10716
10717 format %{ "FMOD $dst,$src1,$src2" %}
10718 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10719 emitModDPR(),
10720 Push_Result_Mod_DPR(src2),
10721 Pop_Mem_FPR(dst));
10722 ins_pipe( pipe_slow );
10723 %}
10724 //
10725 // This instruction does not round to 24-bits
10726 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10727 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10728 match(Set dst (ModF dst src));
10729 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10730
10731 format %{ "FMOD $dst,$src" %}
10732 ins_encode(Push_Reg_Mod_DPR(dst, src),
10733 emitModDPR(),
10734 Push_Result_Mod_DPR(src),
10735 Pop_Reg_FPR(dst));
10736 ins_pipe( pipe_slow );
10737 %}
10738
10739 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10740 predicate(UseSSE>=1);
10741 match(Set dst (ModF src0 src1));
10742 effect(KILL rax, KILL cr);
10743 format %{ "SUB ESP,4\t # FMOD\n"
10744 "\tMOVSS [ESP+0],$src1\n"
10745 "\tFLD_S [ESP+0]\n"
10746 "\tMOVSS [ESP+0],$src0\n"
10747 "\tFLD_S [ESP+0]\n"
10748 "loop:\tFPREM\n"
10749 "\tFWAIT\n"
10750 "\tFNSTSW AX\n"
10751 "\tSAHF\n"
10752 "\tJP loop\n"
10753 "\tFSTP_S [ESP+0]\n"
10754 "\tMOVSS $dst,[ESP+0]\n"
10755 "\tADD ESP,4\n"
10756 "\tFSTP ST0\t # Restore FPU Stack"
10757 %}
10758 ins_cost(250);
10759 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10760 ins_pipe( pipe_slow );
10761 %}
10762
10763
10764 //----------Arithmetic Conversion Instructions---------------------------------
10765 // The conversions operations are all Alpha sorted. Please keep it that way!
10766
10767 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10768 predicate(UseSSE==0);
10769 match(Set dst (RoundFloat src));
10770 ins_cost(125);
10771 format %{ "FST_S $dst,$src\t# F-round" %}
10772 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10773 ins_pipe( fpu_mem_reg );
10774 %}
10775
10776 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10777 predicate(UseSSE<=1);
10778 match(Set dst (RoundDouble src));
10779 ins_cost(125);
10780 format %{ "FST_D $dst,$src\t# D-round" %}
10781 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10782 ins_pipe( fpu_mem_reg );
10783 %}
10784
10785 // Force rounding to 24-bit precision and 6-bit exponent
10786 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10787 predicate(UseSSE==0);
10788 match(Set dst (ConvD2F src));
10789 format %{ "FST_S $dst,$src\t# F-round" %}
10790 expand %{
10791 roundFloat_mem_reg(dst,src);
10792 %}
10793 %}
10794
10795 // Force rounding to 24-bit precision and 6-bit exponent
10796 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10797 predicate(UseSSE==1);
10798 match(Set dst (ConvD2F src));
10799 effect( KILL cr );
10800 format %{ "SUB ESP,4\n\t"
10801 "FST_S [ESP],$src\t# F-round\n\t"
10802 "MOVSS $dst,[ESP]\n\t"
10803 "ADD ESP,4" %}
10804 ins_encode %{
10805 __ subptr(rsp, 4);
10806 if ($src$$reg != FPR1L_enc) {
10807 __ fld_s($src$$reg-1);
10808 __ fstp_s(Address(rsp, 0));
10809 } else {
10810 __ fst_s(Address(rsp, 0));
10811 }
10812 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10813 __ addptr(rsp, 4);
10814 %}
10815 ins_pipe( pipe_slow );
10816 %}
10817
10818 // Force rounding double precision to single precision
10819 instruct convD2F_reg(regF dst, regD src) %{
10820 predicate(UseSSE>=2);
10821 match(Set dst (ConvD2F src));
10822 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10823 ins_encode %{
10824 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10825 %}
10826 ins_pipe( pipe_slow );
10827 %}
10828
10829 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10830 predicate(UseSSE==0);
10831 match(Set dst (ConvF2D src));
10832 format %{ "FST_S $dst,$src\t# D-round" %}
10833 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10834 ins_pipe( fpu_reg_reg );
10835 %}
10836
10837 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10838 predicate(UseSSE==1);
10839 match(Set dst (ConvF2D src));
10840 format %{ "FST_D $dst,$src\t# D-round" %}
10841 expand %{
10842 roundDouble_mem_reg(dst,src);
10843 %}
10844 %}
10845
10846 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10847 predicate(UseSSE==1);
10848 match(Set dst (ConvF2D src));
10849 effect( KILL cr );
10850 format %{ "SUB ESP,4\n\t"
10851 "MOVSS [ESP] $src\n\t"
10852 "FLD_S [ESP]\n\t"
10853 "ADD ESP,4\n\t"
10854 "FSTP $dst\t# D-round" %}
10855 ins_encode %{
10856 __ subptr(rsp, 4);
10857 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10858 __ fld_s(Address(rsp, 0));
10859 __ addptr(rsp, 4);
10860 __ fstp_d($dst$$reg);
10861 %}
10862 ins_pipe( pipe_slow );
10863 %}
10864
10865 instruct convF2D_reg(regD dst, regF src) %{
10866 predicate(UseSSE>=2);
10867 match(Set dst (ConvF2D src));
10868 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10869 ins_encode %{
10870 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10871 %}
10872 ins_pipe( pipe_slow );
10873 %}
10874
10875 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10876 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10877 predicate(UseSSE<=1);
10878 match(Set dst (ConvD2I src));
10879 effect( KILL tmp, KILL cr );
10880 format %{ "FLD $src\t# Convert double to int \n\t"
10881 "FLDCW trunc mode\n\t"
10882 "SUB ESP,4\n\t"
10883 "FISTp [ESP + #0]\n\t"
10884 "FLDCW std/24-bit mode\n\t"
10885 "POP EAX\n\t"
10886 "CMP EAX,0x80000000\n\t"
10887 "JNE,s fast\n\t"
10888 "FLD_D $src\n\t"
10889 "CALL d2i_wrapper\n"
10890 "fast:" %}
10891 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10892 ins_pipe( pipe_slow );
10893 %}
10894
10895 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10896 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10897 predicate(UseSSE>=2);
10898 match(Set dst (ConvD2I src));
10899 effect( KILL tmp, KILL cr );
10900 format %{ "CVTTSD2SI $dst, $src\n\t"
10901 "CMP $dst,0x80000000\n\t"
10902 "JNE,s fast\n\t"
10903 "SUB ESP, 8\n\t"
10904 "MOVSD [ESP], $src\n\t"
10905 "FLD_D [ESP]\n\t"
10906 "ADD ESP, 8\n\t"
10907 "CALL d2i_wrapper\n"
10908 "fast:" %}
10909 ins_encode %{
10910 Label fast;
10911 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10912 __ cmpl($dst$$Register, 0x80000000);
10913 __ jccb(Assembler::notEqual, fast);
10914 __ subptr(rsp, 8);
10915 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10916 __ fld_d(Address(rsp, 0));
10917 __ addptr(rsp, 8);
10918 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10919 __ bind(fast);
10920 %}
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10925 predicate(UseSSE<=1);
10926 match(Set dst (ConvD2L src));
10927 effect( KILL cr );
10928 format %{ "FLD $src\t# Convert double to long\n\t"
10929 "FLDCW trunc mode\n\t"
10930 "SUB ESP,8\n\t"
10931 "FISTp [ESP + #0]\n\t"
10932 "FLDCW std/24-bit mode\n\t"
10933 "POP EAX\n\t"
10934 "POP EDX\n\t"
10935 "CMP EDX,0x80000000\n\t"
10936 "JNE,s fast\n\t"
10937 "TEST EAX,EAX\n\t"
10938 "JNE,s fast\n\t"
10939 "FLD $src\n\t"
10940 "CALL d2l_wrapper\n"
10941 "fast:" %}
10942 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10943 ins_pipe( pipe_slow );
10944 %}
10945
10946 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10947 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10948 predicate (UseSSE>=2);
10949 match(Set dst (ConvD2L src));
10950 effect( KILL cr );
10951 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10952 "MOVSD [ESP],$src\n\t"
10953 "FLD_D [ESP]\n\t"
10954 "FLDCW trunc mode\n\t"
10955 "FISTp [ESP + #0]\n\t"
10956 "FLDCW std/24-bit mode\n\t"
10957 "POP EAX\n\t"
10958 "POP EDX\n\t"
10959 "CMP EDX,0x80000000\n\t"
10960 "JNE,s fast\n\t"
10961 "TEST EAX,EAX\n\t"
10962 "JNE,s fast\n\t"
10963 "SUB ESP,8\n\t"
10964 "MOVSD [ESP],$src\n\t"
10965 "FLD_D [ESP]\n\t"
10966 "ADD ESP,8\n\t"
10967 "CALL d2l_wrapper\n"
10968 "fast:" %}
10969 ins_encode %{
10970 Label fast;
10971 __ subptr(rsp, 8);
10972 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10973 __ fld_d(Address(rsp, 0));
10974 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10975 __ fistp_d(Address(rsp, 0));
10976 // Restore the rounding mode, mask the exception
10977 if (Compile::current()->in_24_bit_fp_mode()) {
10978 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10979 } else {
10980 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10981 }
10982 // Load the converted long, adjust CPU stack
10983 __ pop(rax);
10984 __ pop(rdx);
10985 __ cmpl(rdx, 0x80000000);
10986 __ jccb(Assembler::notEqual, fast);
10987 __ testl(rax, rax);
10988 __ jccb(Assembler::notEqual, fast);
10989 __ subptr(rsp, 8);
10990 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10991 __ fld_d(Address(rsp, 0));
10992 __ addptr(rsp, 8);
10993 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10994 __ bind(fast);
10995 %}
10996 ins_pipe( pipe_slow );
10997 %}
10998
10999 // Convert a double to an int. Java semantics require we do complex
11000 // manglations in the corner cases. So we set the rounding mode to
11001 // 'zero', store the darned double down as an int, and reset the
11002 // rounding mode to 'nearest'. The hardware stores a flag value down
11003 // if we would overflow or converted a NAN; we check for this and
11004 // and go the slow path if needed.
11005 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11006 predicate(UseSSE==0);
11007 match(Set dst (ConvF2I src));
11008 effect( KILL tmp, KILL cr );
11009 format %{ "FLD $src\t# Convert float to int \n\t"
11010 "FLDCW trunc mode\n\t"
11011 "SUB ESP,4\n\t"
11012 "FISTp [ESP + #0]\n\t"
11013 "FLDCW std/24-bit mode\n\t"
11014 "POP EAX\n\t"
11015 "CMP EAX,0x80000000\n\t"
11016 "JNE,s fast\n\t"
11017 "FLD $src\n\t"
11018 "CALL d2i_wrapper\n"
11019 "fast:" %}
11020 // DPR2I_encoding works for FPR2I
11021 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11022 ins_pipe( pipe_slow );
11023 %}
11024
11025 // Convert a float in xmm to an int reg.
11026 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11027 predicate(UseSSE>=1);
11028 match(Set dst (ConvF2I src));
11029 effect( KILL tmp, KILL cr );
11030 format %{ "CVTTSS2SI $dst, $src\n\t"
11031 "CMP $dst,0x80000000\n\t"
11032 "JNE,s fast\n\t"
11033 "SUB ESP, 4\n\t"
11034 "MOVSS [ESP], $src\n\t"
11035 "FLD [ESP]\n\t"
11036 "ADD ESP, 4\n\t"
11037 "CALL d2i_wrapper\n"
11038 "fast:" %}
11039 ins_encode %{
11040 Label fast;
11041 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11042 __ cmpl($dst$$Register, 0x80000000);
11043 __ jccb(Assembler::notEqual, fast);
11044 __ subptr(rsp, 4);
11045 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11046 __ fld_s(Address(rsp, 0));
11047 __ addptr(rsp, 4);
11048 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11049 __ bind(fast);
11050 %}
11051 ins_pipe( pipe_slow );
11052 %}
11053
11054 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11055 predicate(UseSSE==0);
11056 match(Set dst (ConvF2L src));
11057 effect( KILL cr );
11058 format %{ "FLD $src\t# Convert float to long\n\t"
11059 "FLDCW trunc mode\n\t"
11060 "SUB ESP,8\n\t"
11061 "FISTp [ESP + #0]\n\t"
11062 "FLDCW std/24-bit mode\n\t"
11063 "POP EAX\n\t"
11064 "POP EDX\n\t"
11065 "CMP EDX,0x80000000\n\t"
11066 "JNE,s fast\n\t"
11067 "TEST EAX,EAX\n\t"
11068 "JNE,s fast\n\t"
11069 "FLD $src\n\t"
11070 "CALL d2l_wrapper\n"
11071 "fast:" %}
11072 // DPR2L_encoding works for FPR2L
11073 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11074 ins_pipe( pipe_slow );
11075 %}
11076
11077 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11078 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11079 predicate (UseSSE>=1);
11080 match(Set dst (ConvF2L src));
11081 effect( KILL cr );
11082 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11083 "MOVSS [ESP],$src\n\t"
11084 "FLD_S [ESP]\n\t"
11085 "FLDCW trunc mode\n\t"
11086 "FISTp [ESP + #0]\n\t"
11087 "FLDCW std/24-bit mode\n\t"
11088 "POP EAX\n\t"
11089 "POP EDX\n\t"
11090 "CMP EDX,0x80000000\n\t"
11091 "JNE,s fast\n\t"
11092 "TEST EAX,EAX\n\t"
11093 "JNE,s fast\n\t"
11094 "SUB ESP,4\t# Convert float to long\n\t"
11095 "MOVSS [ESP],$src\n\t"
11096 "FLD_S [ESP]\n\t"
11097 "ADD ESP,4\n\t"
11098 "CALL d2l_wrapper\n"
11099 "fast:" %}
11100 ins_encode %{
11101 Label fast;
11102 __ subptr(rsp, 8);
11103 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11104 __ fld_s(Address(rsp, 0));
11105 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11106 __ fistp_d(Address(rsp, 0));
11107 // Restore the rounding mode, mask the exception
11108 if (Compile::current()->in_24_bit_fp_mode()) {
11109 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11110 } else {
11111 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11112 }
11113 // Load the converted long, adjust CPU stack
11114 __ pop(rax);
11115 __ pop(rdx);
11116 __ cmpl(rdx, 0x80000000);
11117 __ jccb(Assembler::notEqual, fast);
11118 __ testl(rax, rax);
11119 __ jccb(Assembler::notEqual, fast);
11120 __ subptr(rsp, 4);
11121 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11122 __ fld_s(Address(rsp, 0));
11123 __ addptr(rsp, 4);
11124 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11125 __ bind(fast);
11126 %}
11127 ins_pipe( pipe_slow );
11128 %}
11129
11130 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11131 predicate( UseSSE<=1 );
11132 match(Set dst (ConvI2D src));
11133 format %{ "FILD $src\n\t"
11134 "FSTP $dst" %}
11135 opcode(0xDB, 0x0); /* DB /0 */
11136 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11137 ins_pipe( fpu_reg_mem );
11138 %}
11139
11140 instruct convI2D_reg(regD dst, rRegI src) %{
11141 predicate( UseSSE>=2 && !UseXmmI2D );
11142 match(Set dst (ConvI2D src));
11143 format %{ "CVTSI2SD $dst,$src" %}
11144 ins_encode %{
11145 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11146 %}
11147 ins_pipe( pipe_slow );
11148 %}
11149
11150 instruct convI2D_mem(regD dst, memory mem) %{
11151 predicate( UseSSE>=2 );
11152 match(Set dst (ConvI2D (LoadI mem)));
11153 format %{ "CVTSI2SD $dst,$mem" %}
11154 ins_encode %{
11155 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11156 %}
11157 ins_pipe( pipe_slow );
11158 %}
11159
11160 instruct convXI2D_reg(regD dst, rRegI src)
11161 %{
11162 predicate( UseSSE>=2 && UseXmmI2D );
11163 match(Set dst (ConvI2D src));
11164
11165 format %{ "MOVD $dst,$src\n\t"
11166 "CVTDQ2PD $dst,$dst\t# i2d" %}
11167 ins_encode %{
11168 __ movdl($dst$$XMMRegister, $src$$Register);
11169 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11170 %}
11171 ins_pipe(pipe_slow); // XXX
11172 %}
11173
11174 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11175 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11176 match(Set dst (ConvI2D (LoadI mem)));
11177 format %{ "FILD $mem\n\t"
11178 "FSTP $dst" %}
11179 opcode(0xDB); /* DB /0 */
11180 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11181 Pop_Reg_DPR(dst));
11182 ins_pipe( fpu_reg_mem );
11183 %}
11184
11185 // Convert a byte to a float; no rounding step needed.
11186 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11187 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11188 match(Set dst (ConvI2F src));
11189 format %{ "FILD $src\n\t"
11190 "FSTP $dst" %}
11191
11192 opcode(0xDB, 0x0); /* DB /0 */
11193 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11194 ins_pipe( fpu_reg_mem );
11195 %}
11196
11197 // In 24-bit mode, force exponent rounding by storing back out
11198 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11199 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11200 match(Set dst (ConvI2F src));
11201 ins_cost(200);
11202 format %{ "FILD $src\n\t"
11203 "FSTP_S $dst" %}
11204 opcode(0xDB, 0x0); /* DB /0 */
11205 ins_encode( Push_Mem_I(src),
11206 Pop_Mem_FPR(dst));
11207 ins_pipe( fpu_mem_mem );
11208 %}
11209
11210 // In 24-bit mode, force exponent rounding by storing back out
11211 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11212 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11213 match(Set dst (ConvI2F (LoadI mem)));
11214 ins_cost(200);
11215 format %{ "FILD $mem\n\t"
11216 "FSTP_S $dst" %}
11217 opcode(0xDB); /* DB /0 */
11218 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11219 Pop_Mem_FPR(dst));
11220 ins_pipe( fpu_mem_mem );
11221 %}
11222
11223 // This instruction does not round to 24-bits
11224 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11225 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11226 match(Set dst (ConvI2F src));
11227 format %{ "FILD $src\n\t"
11228 "FSTP $dst" %}
11229 opcode(0xDB, 0x0); /* DB /0 */
11230 ins_encode( Push_Mem_I(src),
11231 Pop_Reg_FPR(dst));
11232 ins_pipe( fpu_reg_mem );
11233 %}
11234
11235 // This instruction does not round to 24-bits
11236 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11237 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11238 match(Set dst (ConvI2F (LoadI mem)));
11239 format %{ "FILD $mem\n\t"
11240 "FSTP $dst" %}
11241 opcode(0xDB); /* DB /0 */
11242 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11243 Pop_Reg_FPR(dst));
11244 ins_pipe( fpu_reg_mem );
11245 %}
11246
11247 // Convert an int to a float in xmm; no rounding step needed.
11248 instruct convI2F_reg(regF dst, rRegI src) %{
11249 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11250 match(Set dst (ConvI2F src));
11251 format %{ "CVTSI2SS $dst, $src" %}
11252 ins_encode %{
11253 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11254 %}
11255 ins_pipe( pipe_slow );
11256 %}
11257
11258 instruct convXI2F_reg(regF dst, rRegI src)
11259 %{
11260 predicate( UseSSE>=2 && UseXmmI2F );
11261 match(Set dst (ConvI2F src));
11262
11263 format %{ "MOVD $dst,$src\n\t"
11264 "CVTDQ2PS $dst,$dst\t# i2f" %}
11265 ins_encode %{
11266 __ movdl($dst$$XMMRegister, $src$$Register);
11267 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11268 %}
11269 ins_pipe(pipe_slow); // XXX
11270 %}
11271
11272 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11273 match(Set dst (ConvI2L src));
11274 effect(KILL cr);
11275 ins_cost(375);
11276 format %{ "MOV $dst.lo,$src\n\t"
11277 "MOV $dst.hi,$src\n\t"
11278 "SAR $dst.hi,31" %}
11279 ins_encode(convert_int_long(dst,src));
11280 ins_pipe( ialu_reg_reg_long );
11281 %}
11282
11283 // Zero-extend convert int to long
11284 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11285 match(Set dst (AndL (ConvI2L src) mask) );
11286 effect( KILL flags );
11287 ins_cost(250);
11288 format %{ "MOV $dst.lo,$src\n\t"
11289 "XOR $dst.hi,$dst.hi" %}
11290 opcode(0x33); // XOR
11291 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11292 ins_pipe( ialu_reg_reg_long );
11293 %}
11294
11295 // Zero-extend long
11296 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11297 match(Set dst (AndL src mask) );
11298 effect( KILL flags );
11299 ins_cost(250);
11300 format %{ "MOV $dst.lo,$src.lo\n\t"
11301 "XOR $dst.hi,$dst.hi\n\t" %}
11302 opcode(0x33); // XOR
11303 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11304 ins_pipe( ialu_reg_reg_long );
11305 %}
11306
11307 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11308 predicate (UseSSE<=1);
11309 match(Set dst (ConvL2D src));
11310 effect( KILL cr );
11311 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11312 "PUSH $src.lo\n\t"
11313 "FILD ST,[ESP + #0]\n\t"
11314 "ADD ESP,8\n\t"
11315 "FSTP_D $dst\t# D-round" %}
11316 opcode(0xDF, 0x5); /* DF /5 */
11317 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11318 ins_pipe( pipe_slow );
11319 %}
11320
11321 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11322 predicate (UseSSE>=2);
11323 match(Set dst (ConvL2D src));
11324 effect( KILL cr );
11325 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11326 "PUSH $src.lo\n\t"
11327 "FILD_D [ESP]\n\t"
11328 "FSTP_D [ESP]\n\t"
11329 "MOVSD $dst,[ESP]\n\t"
11330 "ADD ESP,8" %}
11331 opcode(0xDF, 0x5); /* DF /5 */
11332 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11333 ins_pipe( pipe_slow );
11334 %}
11335
11336 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11337 predicate (UseSSE>=1);
11338 match(Set dst (ConvL2F src));
11339 effect( KILL cr );
11340 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11341 "PUSH $src.lo\n\t"
11342 "FILD_D [ESP]\n\t"
11343 "FSTP_S [ESP]\n\t"
11344 "MOVSS $dst,[ESP]\n\t"
11345 "ADD ESP,8" %}
11346 opcode(0xDF, 0x5); /* DF /5 */
11347 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11348 ins_pipe( pipe_slow );
11349 %}
11350
11351 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11352 match(Set dst (ConvL2F src));
11353 effect( KILL cr );
11354 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11355 "PUSH $src.lo\n\t"
11356 "FILD ST,[ESP + #0]\n\t"
11357 "ADD ESP,8\n\t"
11358 "FSTP_S $dst\t# F-round" %}
11359 opcode(0xDF, 0x5); /* DF /5 */
11360 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11361 ins_pipe( pipe_slow );
11362 %}
11363
11364 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11365 match(Set dst (ConvL2I src));
11366 effect( DEF dst, USE src );
11367 format %{ "MOV $dst,$src.lo" %}
11368 ins_encode(enc_CopyL_Lo(dst,src));
11369 ins_pipe( ialu_reg_reg );
11370 %}
11371
11372
11373 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11374 match(Set dst (MoveF2I src));
11375 effect( DEF dst, USE src );
11376 ins_cost(100);
11377 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11378 ins_encode %{
11379 __ movl($dst$$Register, Address(rsp, $src$$disp));
11380 %}
11381 ins_pipe( ialu_reg_mem );
11382 %}
11383
11384 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11385 predicate(UseSSE==0);
11386 match(Set dst (MoveF2I src));
11387 effect( DEF dst, USE src );
11388
11389 ins_cost(125);
11390 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11391 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11392 ins_pipe( fpu_mem_reg );
11393 %}
11394
11395 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11396 predicate(UseSSE>=1);
11397 match(Set dst (MoveF2I src));
11398 effect( DEF dst, USE src );
11399
11400 ins_cost(95);
11401 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11402 ins_encode %{
11403 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11404 %}
11405 ins_pipe( pipe_slow );
11406 %}
11407
11408 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11409 predicate(UseSSE>=2);
11410 match(Set dst (MoveF2I src));
11411 effect( DEF dst, USE src );
11412 ins_cost(85);
11413 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11414 ins_encode %{
11415 __ movdl($dst$$Register, $src$$XMMRegister);
11416 %}
11417 ins_pipe( pipe_slow );
11418 %}
11419
11420 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11421 match(Set dst (MoveI2F src));
11422 effect( DEF dst, USE src );
11423
11424 ins_cost(100);
11425 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11426 ins_encode %{
11427 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11428 %}
11429 ins_pipe( ialu_mem_reg );
11430 %}
11431
11432
11433 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11434 predicate(UseSSE==0);
11435 match(Set dst (MoveI2F src));
11436 effect(DEF dst, USE src);
11437
11438 ins_cost(125);
11439 format %{ "FLD_S $src\n\t"
11440 "FSTP $dst\t# MoveI2F_stack_reg" %}
11441 opcode(0xD9); /* D9 /0, FLD m32real */
11442 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11443 Pop_Reg_FPR(dst) );
11444 ins_pipe( fpu_reg_mem );
11445 %}
11446
11447 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11448 predicate(UseSSE>=1);
11449 match(Set dst (MoveI2F src));
11450 effect( DEF dst, USE src );
11451
11452 ins_cost(95);
11453 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11454 ins_encode %{
11455 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11456 %}
11457 ins_pipe( pipe_slow );
11458 %}
11459
11460 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11461 predicate(UseSSE>=2);
11462 match(Set dst (MoveI2F src));
11463 effect( DEF dst, USE src );
11464
11465 ins_cost(85);
11466 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11467 ins_encode %{
11468 __ movdl($dst$$XMMRegister, $src$$Register);
11469 %}
11470 ins_pipe( pipe_slow );
11471 %}
11472
11473 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11474 match(Set dst (MoveD2L src));
11475 effect(DEF dst, USE src);
11476
11477 ins_cost(250);
11478 format %{ "MOV $dst.lo,$src\n\t"
11479 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11480 opcode(0x8B, 0x8B);
11481 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11482 ins_pipe( ialu_mem_long_reg );
11483 %}
11484
11485 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11486 predicate(UseSSE<=1);
11487 match(Set dst (MoveD2L src));
11488 effect(DEF dst, USE src);
11489
11490 ins_cost(125);
11491 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11492 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11493 ins_pipe( fpu_mem_reg );
11494 %}
11495
11496 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11497 predicate(UseSSE>=2);
11498 match(Set dst (MoveD2L src));
11499 effect(DEF dst, USE src);
11500 ins_cost(95);
11501 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11502 ins_encode %{
11503 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11504 %}
11505 ins_pipe( pipe_slow );
11506 %}
11507
11508 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11509 predicate(UseSSE>=2);
11510 match(Set dst (MoveD2L src));
11511 effect(DEF dst, USE src, TEMP tmp);
11512 ins_cost(85);
11513 format %{ "MOVD $dst.lo,$src\n\t"
11514 "PSHUFLW $tmp,$src,0x4E\n\t"
11515 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11516 ins_encode %{
11517 __ movdl($dst$$Register, $src$$XMMRegister);
11518 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11519 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11520 %}
11521 ins_pipe( pipe_slow );
11522 %}
11523
11524 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11525 match(Set dst (MoveL2D src));
11526 effect(DEF dst, USE src);
11527
11528 ins_cost(200);
11529 format %{ "MOV $dst,$src.lo\n\t"
11530 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11531 opcode(0x89, 0x89);
11532 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11533 ins_pipe( ialu_mem_long_reg );
11534 %}
11535
11536
11537 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11538 predicate(UseSSE<=1);
11539 match(Set dst (MoveL2D src));
11540 effect(DEF dst, USE src);
11541 ins_cost(125);
11542
11543 format %{ "FLD_D $src\n\t"
11544 "FSTP $dst\t# MoveL2D_stack_reg" %}
11545 opcode(0xDD); /* DD /0, FLD m64real */
11546 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11547 Pop_Reg_DPR(dst) );
11548 ins_pipe( fpu_reg_mem );
11549 %}
11550
11551
11552 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11553 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11554 match(Set dst (MoveL2D src));
11555 effect(DEF dst, USE src);
11556
11557 ins_cost(95);
11558 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11559 ins_encode %{
11560 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11561 %}
11562 ins_pipe( pipe_slow );
11563 %}
11564
11565 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11566 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11567 match(Set dst (MoveL2D src));
11568 effect(DEF dst, USE src);
11569
11570 ins_cost(95);
11571 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11572 ins_encode %{
11573 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11574 %}
11575 ins_pipe( pipe_slow );
11576 %}
11577
11578 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11579 predicate(UseSSE>=2);
11580 match(Set dst (MoveL2D src));
11581 effect(TEMP dst, USE src, TEMP tmp);
11582 ins_cost(85);
11583 format %{ "MOVD $dst,$src.lo\n\t"
11584 "MOVD $tmp,$src.hi\n\t"
11585 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11586 ins_encode %{
11587 __ movdl($dst$$XMMRegister, $src$$Register);
11588 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11589 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11590 %}
11591 ins_pipe( pipe_slow );
11592 %}
11593
11594
11595 // =======================================================================
11596 // fast clearing of an array
11597 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11598 match(Set dummy (ClearArray cnt base));
11599 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11600 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11601 "XOR EAX,EAX\n\t"
11602 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11603 opcode(0,0x4);
11604 ins_encode( Opcode(0xD1), RegOpc(ECX),
11605 OpcRegReg(0x33,EAX,EAX),
11606 Opcode(0xF3), Opcode(0xAB) );
11607 ins_pipe( pipe_slow );
11608 %}
11609
11610 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11611 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11612 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11613 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11614
11615 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11616 ins_encode %{
11617 __ string_compare($str1$$Register, $str2$$Register,
11618 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11619 $tmp1$$XMMRegister);
11620 %}
11621 ins_pipe( pipe_slow );
11622 %}
11623
11624 // fast string equals
11625 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11626 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11627 match(Set result (StrEquals (Binary str1 str2) cnt));
11628 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11629
11630 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11631 ins_encode %{
11632 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11633 $cnt$$Register, $result$$Register, $tmp3$$Register,
11634 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11635 %}
11636 ins_pipe( pipe_slow );
11637 %}
11638
11639 // fast search of substring with known size.
11640 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11641 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11642 predicate(UseSSE42Intrinsics);
11643 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11644 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11645
11646 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11647 ins_encode %{
11648 int icnt2 = (int)$int_cnt2$$constant;
11649 if (icnt2 >= 8) {
11650 // IndexOf for constant substrings with size >= 8 elements
11651 // which don't need to be loaded through stack.
11652 __ string_indexofC8($str1$$Register, $str2$$Register,
11653 $cnt1$$Register, $cnt2$$Register,
11654 icnt2, $result$$Register,
11655 $vec$$XMMRegister, $tmp$$Register);
11656 } else {
11657 // Small strings are loaded through stack if they cross page boundary.
11658 __ string_indexof($str1$$Register, $str2$$Register,
11659 $cnt1$$Register, $cnt2$$Register,
11660 icnt2, $result$$Register,
11661 $vec$$XMMRegister, $tmp$$Register);
11662 }
11663 %}
11664 ins_pipe( pipe_slow );
11665 %}
11666
11667 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11668 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11669 predicate(UseSSE42Intrinsics);
11670 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11671 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11672
11673 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11674 ins_encode %{
11675 __ string_indexof($str1$$Register, $str2$$Register,
11676 $cnt1$$Register, $cnt2$$Register,
11677 (-1), $result$$Register,
11678 $vec$$XMMRegister, $tmp$$Register);
11679 %}
11680 ins_pipe( pipe_slow );
11681 %}
11682
11683 // fast array equals
11684 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11685 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11686 %{
11687 match(Set result (AryEq ary1 ary2));
11688 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11689 //ins_cost(300);
11690
11691 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11692 ins_encode %{
11693 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11694 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11695 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11696 %}
11697 ins_pipe( pipe_slow );
11698 %}
11699
11700 //----------Control Flow Instructions------------------------------------------
11701 // Signed compare Instructions
11702 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11703 match(Set cr (CmpI op1 op2));
11704 effect( DEF cr, USE op1, USE op2 );
11705 format %{ "CMP $op1,$op2" %}
11706 opcode(0x3B); /* Opcode 3B /r */
11707 ins_encode( OpcP, RegReg( op1, op2) );
11708 ins_pipe( ialu_cr_reg_reg );
11709 %}
11710
11711 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11712 match(Set cr (CmpI op1 op2));
11713 effect( DEF cr, USE op1 );
11714 format %{ "CMP $op1,$op2" %}
11715 opcode(0x81,0x07); /* Opcode 81 /7 */
11716 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11717 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11718 ins_pipe( ialu_cr_reg_imm );
11719 %}
11720
11721 // Cisc-spilled version of cmpI_eReg
11722 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11723 match(Set cr (CmpI op1 (LoadI op2)));
11724
11725 format %{ "CMP $op1,$op2" %}
11726 ins_cost(500);
11727 opcode(0x3B); /* Opcode 3B /r */
11728 ins_encode( OpcP, RegMem( op1, op2) );
11729 ins_pipe( ialu_cr_reg_mem );
11730 %}
11731
11732 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11733 match(Set cr (CmpI src zero));
11734 effect( DEF cr, USE src );
11735
11736 format %{ "TEST $src,$src" %}
11737 opcode(0x85);
11738 ins_encode( OpcP, RegReg( src, src ) );
11739 ins_pipe( ialu_cr_reg_imm );
11740 %}
11741
11742 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11743 match(Set cr (CmpI (AndI src con) zero));
11744
11745 format %{ "TEST $src,$con" %}
11746 opcode(0xF7,0x00);
11747 ins_encode( OpcP, RegOpc(src), Con32(con) );
11748 ins_pipe( ialu_cr_reg_imm );
11749 %}
11750
11751 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11752 match(Set cr (CmpI (AndI src mem) zero));
11753
11754 format %{ "TEST $src,$mem" %}
11755 opcode(0x85);
11756 ins_encode( OpcP, RegMem( src, mem ) );
11757 ins_pipe( ialu_cr_reg_mem );
11758 %}
11759
11760 // Unsigned compare Instructions; really, same as signed except they
11761 // produce an eFlagsRegU instead of eFlagsReg.
11762 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11763 match(Set cr (CmpU op1 op2));
11764
11765 format %{ "CMPu $op1,$op2" %}
11766 opcode(0x3B); /* Opcode 3B /r */
11767 ins_encode( OpcP, RegReg( op1, op2) );
11768 ins_pipe( ialu_cr_reg_reg );
11769 %}
11770
11771 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11772 match(Set cr (CmpU op1 op2));
11773
11774 format %{ "CMPu $op1,$op2" %}
11775 opcode(0x81,0x07); /* Opcode 81 /7 */
11776 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11777 ins_pipe( ialu_cr_reg_imm );
11778 %}
11779
11780 // // Cisc-spilled version of cmpU_eReg
11781 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11782 match(Set cr (CmpU op1 (LoadI op2)));
11783
11784 format %{ "CMPu $op1,$op2" %}
11785 ins_cost(500);
11786 opcode(0x3B); /* Opcode 3B /r */
11787 ins_encode( OpcP, RegMem( op1, op2) );
11788 ins_pipe( ialu_cr_reg_mem );
11789 %}
11790
11791 // // Cisc-spilled version of cmpU_eReg
11792 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11793 // match(Set cr (CmpU (LoadI op1) op2));
11794 //
11795 // format %{ "CMPu $op1,$op2" %}
11796 // ins_cost(500);
11797 // opcode(0x39); /* Opcode 39 /r */
11798 // ins_encode( OpcP, RegMem( op1, op2) );
11799 //%}
11800
11801 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11802 match(Set cr (CmpU src zero));
11803
11804 format %{ "TESTu $src,$src" %}
11805 opcode(0x85);
11806 ins_encode( OpcP, RegReg( src, src ) );
11807 ins_pipe( ialu_cr_reg_imm );
11808 %}
11809
11810 // Unsigned pointer compare Instructions
11811 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11812 match(Set cr (CmpP op1 op2));
11813
11814 format %{ "CMPu $op1,$op2" %}
11815 opcode(0x3B); /* Opcode 3B /r */
11816 ins_encode( OpcP, RegReg( op1, op2) );
11817 ins_pipe( ialu_cr_reg_reg );
11818 %}
11819
11820 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11821 match(Set cr (CmpP op1 op2));
11822
11823 format %{ "CMPu $op1,$op2" %}
11824 opcode(0x81,0x07); /* Opcode 81 /7 */
11825 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11826 ins_pipe( ialu_cr_reg_imm );
11827 %}
11828
11829 // // Cisc-spilled version of cmpP_eReg
11830 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11831 match(Set cr (CmpP op1 (LoadP op2)));
11832
11833 format %{ "CMPu $op1,$op2" %}
11834 ins_cost(500);
11835 opcode(0x3B); /* Opcode 3B /r */
11836 ins_encode( OpcP, RegMem( op1, op2) );
11837 ins_pipe( ialu_cr_reg_mem );
11838 %}
11839
11840 // // Cisc-spilled version of cmpP_eReg
11841 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11842 // match(Set cr (CmpP (LoadP op1) op2));
11843 //
11844 // format %{ "CMPu $op1,$op2" %}
11845 // ins_cost(500);
11846 // opcode(0x39); /* Opcode 39 /r */
11847 // ins_encode( OpcP, RegMem( op1, op2) );
11848 //%}
11849
11850 // Compare raw pointer (used in out-of-heap check).
11851 // Only works because non-oop pointers must be raw pointers
11852 // and raw pointers have no anti-dependencies.
11853 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11854 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11855 match(Set cr (CmpP op1 (LoadP op2)));
11856
11857 format %{ "CMPu $op1,$op2" %}
11858 opcode(0x3B); /* Opcode 3B /r */
11859 ins_encode( OpcP, RegMem( op1, op2) );
11860 ins_pipe( ialu_cr_reg_mem );
11861 %}
11862
11863 //
11864 // This will generate a signed flags result. This should be ok
11865 // since any compare to a zero should be eq/neq.
11866 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11867 match(Set cr (CmpP src zero));
11868
11869 format %{ "TEST $src,$src" %}
11870 opcode(0x85);
11871 ins_encode( OpcP, RegReg( src, src ) );
11872 ins_pipe( ialu_cr_reg_imm );
11873 %}
11874
11875 // Cisc-spilled version of testP_reg
11876 // This will generate a signed flags result. This should be ok
11877 // since any compare to a zero should be eq/neq.
11878 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11879 match(Set cr (CmpP (LoadP op) zero));
11880
11881 format %{ "TEST $op,0xFFFFFFFF" %}
11882 ins_cost(500);
11883 opcode(0xF7); /* Opcode F7 /0 */
11884 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11885 ins_pipe( ialu_cr_reg_imm );
11886 %}
11887
11888 // Yanked all unsigned pointer compare operations.
11889 // Pointer compares are done with CmpP which is already unsigned.
11890
11891 //----------Max and Min--------------------------------------------------------
11892 // Min Instructions
11893 ////
11894 // *** Min and Max using the conditional move are slower than the
11895 // *** branch version on a Pentium III.
11896 // // Conditional move for min
11897 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11898 // effect( USE_DEF op2, USE op1, USE cr );
11899 // format %{ "CMOVlt $op2,$op1\t! min" %}
11900 // opcode(0x4C,0x0F);
11901 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11902 // ins_pipe( pipe_cmov_reg );
11903 //%}
11904 //
11905 //// Min Register with Register (P6 version)
11906 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11907 // predicate(VM_Version::supports_cmov() );
11908 // match(Set op2 (MinI op1 op2));
11909 // ins_cost(200);
11910 // expand %{
11911 // eFlagsReg cr;
11912 // compI_eReg(cr,op1,op2);
11913 // cmovI_reg_lt(op2,op1,cr);
11914 // %}
11915 //%}
11916
11917 // Min Register with Register (generic version)
11918 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11919 match(Set dst (MinI dst src));
11920 effect(KILL flags);
11921 ins_cost(300);
11922
11923 format %{ "MIN $dst,$src" %}
11924 opcode(0xCC);
11925 ins_encode( min_enc(dst,src) );
11926 ins_pipe( pipe_slow );
11927 %}
11928
11929 // Max Register with Register
11930 // *** Min and Max using the conditional move are slower than the
11931 // *** branch version on a Pentium III.
11932 // // Conditional move for max
11933 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11934 // effect( USE_DEF op2, USE op1, USE cr );
11935 // format %{ "CMOVgt $op2,$op1\t! max" %}
11936 // opcode(0x4F,0x0F);
11937 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11938 // ins_pipe( pipe_cmov_reg );
11939 //%}
11940 //
11941 // // Max Register with Register (P6 version)
11942 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11943 // predicate(VM_Version::supports_cmov() );
11944 // match(Set op2 (MaxI op1 op2));
11945 // ins_cost(200);
11946 // expand %{
11947 // eFlagsReg cr;
11948 // compI_eReg(cr,op1,op2);
11949 // cmovI_reg_gt(op2,op1,cr);
11950 // %}
11951 //%}
11952
11953 // Max Register with Register (generic version)
11954 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11955 match(Set dst (MaxI dst src));
11956 effect(KILL flags);
11957 ins_cost(300);
11958
11959 format %{ "MAX $dst,$src" %}
11960 opcode(0xCC);
11961 ins_encode( max_enc(dst,src) );
11962 ins_pipe( pipe_slow );
11963 %}
11964
11965 // ============================================================================
11966 // Counted Loop limit node which represents exact final iterator value.
11967 // Note: the resulting value should fit into integer range since
11968 // counted loops have limit check on overflow.
11969 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11970 match(Set limit (LoopLimit (Binary init limit) stride));
11971 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11972 ins_cost(300);
11973
11974 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11975 ins_encode %{
11976 int strd = (int)$stride$$constant;
11977 assert(strd != 1 && strd != -1, "sanity");
11978 int m1 = (strd > 0) ? 1 : -1;
11979 // Convert limit to long (EAX:EDX)
11980 __ cdql();
11981 // Convert init to long (init:tmp)
11982 __ movl($tmp$$Register, $init$$Register);
11983 __ sarl($tmp$$Register, 31);
11984 // $limit - $init
11985 __ subl($limit$$Register, $init$$Register);
11986 __ sbbl($limit_hi$$Register, $tmp$$Register);
11987 // + ($stride - 1)
11988 if (strd > 0) {
11989 __ addl($limit$$Register, (strd - 1));
11990 __ adcl($limit_hi$$Register, 0);
11991 __ movl($tmp$$Register, strd);
11992 } else {
11993 __ addl($limit$$Register, (strd + 1));
11994 __ adcl($limit_hi$$Register, -1);
11995 __ lneg($limit_hi$$Register, $limit$$Register);
11996 __ movl($tmp$$Register, -strd);
11997 }
11998 // signed devision: (EAX:EDX) / pos_stride
11999 __ idivl($tmp$$Register);
12000 if (strd < 0) {
12001 // restore sign
12002 __ negl($tmp$$Register);
12003 }
12004 // (EAX) * stride
12005 __ mull($tmp$$Register);
12006 // + init (ignore upper bits)
12007 __ addl($limit$$Register, $init$$Register);
12008 %}
12009 ins_pipe( pipe_slow );
12010 %}
12011
12012 // ============================================================================
12013 // Branch Instructions
12014 // Jump Table
12015 instruct jumpXtnd(rRegI switch_val) %{
12016 match(Jump switch_val);
12017 ins_cost(350);
12018 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12019 ins_encode %{
12020 // Jump to Address(table_base + switch_reg)
12021 Address index(noreg, $switch_val$$Register, Address::times_1);
12022 __ jump(ArrayAddress($constantaddress, index));
12023 %}
12024 ins_pipe(pipe_jmp);
12025 %}
12026
12027 // Jump Direct - Label defines a relative address from JMP+1
12028 instruct jmpDir(label labl) %{
12029 match(Goto);
12030 effect(USE labl);
12031
12032 ins_cost(300);
12033 format %{ "JMP $labl" %}
12034 size(5);
12035 ins_encode %{
12036 Label* L = $labl$$label;
12037 __ jmp(*L, false); // Always long jump
12038 %}
12039 ins_pipe( pipe_jmp );
12040 %}
12041
12042 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12043 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12044 match(If cop cr);
12045 effect(USE labl);
12046
12047 ins_cost(300);
12048 format %{ "J$cop $labl" %}
12049 size(6);
12050 ins_encode %{
12051 Label* L = $labl$$label;
12052 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12053 %}
12054 ins_pipe( pipe_jcc );
12055 %}
12056
12057 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12058 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12059 match(CountedLoopEnd cop cr);
12060 effect(USE labl);
12061
12062 ins_cost(300);
12063 format %{ "J$cop $labl\t# Loop end" %}
12064 size(6);
12065 ins_encode %{
12066 Label* L = $labl$$label;
12067 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12068 %}
12069 ins_pipe( pipe_jcc );
12070 %}
12071
12072 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12073 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12074 match(CountedLoopEnd cop cmp);
12075 effect(USE labl);
12076
12077 ins_cost(300);
12078 format %{ "J$cop,u $labl\t# Loop end" %}
12079 size(6);
12080 ins_encode %{
12081 Label* L = $labl$$label;
12082 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12083 %}
12084 ins_pipe( pipe_jcc );
12085 %}
12086
12087 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12088 match(CountedLoopEnd cop cmp);
12089 effect(USE labl);
12090
12091 ins_cost(200);
12092 format %{ "J$cop,u $labl\t# Loop end" %}
12093 size(6);
12094 ins_encode %{
12095 Label* L = $labl$$label;
12096 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12097 %}
12098 ins_pipe( pipe_jcc );
12099 %}
12100
12101 // Jump Direct Conditional - using unsigned comparison
12102 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12103 match(If cop cmp);
12104 effect(USE labl);
12105
12106 ins_cost(300);
12107 format %{ "J$cop,u $labl" %}
12108 size(6);
12109 ins_encode %{
12110 Label* L = $labl$$label;
12111 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12112 %}
12113 ins_pipe(pipe_jcc);
12114 %}
12115
12116 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12117 match(If cop cmp);
12118 effect(USE labl);
12119
12120 ins_cost(200);
12121 format %{ "J$cop,u $labl" %}
12122 size(6);
12123 ins_encode %{
12124 Label* L = $labl$$label;
12125 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12126 %}
12127 ins_pipe(pipe_jcc);
12128 %}
12129
12130 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12131 match(If cop cmp);
12132 effect(USE labl);
12133
12134 ins_cost(200);
12135 format %{ $$template
12136 if ($cop$$cmpcode == Assembler::notEqual) {
12137 $$emit$$"JP,u $labl\n\t"
12138 $$emit$$"J$cop,u $labl"
12139 } else {
12140 $$emit$$"JP,u done\n\t"
12141 $$emit$$"J$cop,u $labl\n\t"
12142 $$emit$$"done:"
12143 }
12144 %}
12145 ins_encode %{
12146 Label* l = $labl$$label;
12147 if ($cop$$cmpcode == Assembler::notEqual) {
12148 __ jcc(Assembler::parity, *l, false);
12149 __ jcc(Assembler::notEqual, *l, false);
12150 } else if ($cop$$cmpcode == Assembler::equal) {
12151 Label done;
12152 __ jccb(Assembler::parity, done);
12153 __ jcc(Assembler::equal, *l, false);
12154 __ bind(done);
12155 } else {
12156 ShouldNotReachHere();
12157 }
12158 %}
12159 ins_pipe(pipe_jcc);
12160 %}
12161
12162 // ============================================================================
12163 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12164 // array for an instance of the superklass. Set a hidden internal cache on a
12165 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12166 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12167 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12168 match(Set result (PartialSubtypeCheck sub super));
12169 effect( KILL rcx, KILL cr );
12170
12171 ins_cost(1100); // slightly larger than the next version
12172 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12173 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12174 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12175 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12176 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12177 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12178 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12179 "miss:\t" %}
12180
12181 opcode(0x1); // Force a XOR of EDI
12182 ins_encode( enc_PartialSubtypeCheck() );
12183 ins_pipe( pipe_slow );
12184 %}
12185
12186 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12187 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12188 effect( KILL rcx, KILL result );
12189
12190 ins_cost(1000);
12191 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12192 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12193 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12194 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12195 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12196 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12197 "miss:\t" %}
12198
12199 opcode(0x0); // No need to XOR EDI
12200 ins_encode( enc_PartialSubtypeCheck() );
12201 ins_pipe( pipe_slow );
12202 %}
12203
12204 // ============================================================================
12205 // Branch Instructions -- short offset versions
12206 //
12207 // These instructions are used to replace jumps of a long offset (the default
12208 // match) with jumps of a shorter offset. These instructions are all tagged
12209 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12210 // match rules in general matching. Instead, the ADLC generates a conversion
12211 // method in the MachNode which can be used to do in-place replacement of the
12212 // long variant with the shorter variant. The compiler will determine if a
12213 // branch can be taken by the is_short_branch_offset() predicate in the machine
12214 // specific code section of the file.
12215
12216 // Jump Direct - Label defines a relative address from JMP+1
12217 instruct jmpDir_short(label labl) %{
12218 match(Goto);
12219 effect(USE labl);
12220
12221 ins_cost(300);
12222 format %{ "JMP,s $labl" %}
12223 size(2);
12224 ins_encode %{
12225 Label* L = $labl$$label;
12226 __ jmpb(*L);
12227 %}
12228 ins_pipe( pipe_jmp );
12229 ins_short_branch(1);
12230 %}
12231
12232 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12233 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12234 match(If cop cr);
12235 effect(USE labl);
12236
12237 ins_cost(300);
12238 format %{ "J$cop,s $labl" %}
12239 size(2);
12240 ins_encode %{
12241 Label* L = $labl$$label;
12242 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12243 %}
12244 ins_pipe( pipe_jcc );
12245 ins_short_branch(1);
12246 %}
12247
12248 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12249 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12250 match(CountedLoopEnd cop cr);
12251 effect(USE labl);
12252
12253 ins_cost(300);
12254 format %{ "J$cop,s $labl\t# Loop end" %}
12255 size(2);
12256 ins_encode %{
12257 Label* L = $labl$$label;
12258 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12259 %}
12260 ins_pipe( pipe_jcc );
12261 ins_short_branch(1);
12262 %}
12263
12264 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12265 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12266 match(CountedLoopEnd cop cmp);
12267 effect(USE labl);
12268
12269 ins_cost(300);
12270 format %{ "J$cop,us $labl\t# Loop end" %}
12271 size(2);
12272 ins_encode %{
12273 Label* L = $labl$$label;
12274 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12275 %}
12276 ins_pipe( pipe_jcc );
12277 ins_short_branch(1);
12278 %}
12279
12280 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12281 match(CountedLoopEnd cop cmp);
12282 effect(USE labl);
12283
12284 ins_cost(300);
12285 format %{ "J$cop,us $labl\t# Loop end" %}
12286 size(2);
12287 ins_encode %{
12288 Label* L = $labl$$label;
12289 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12290 %}
12291 ins_pipe( pipe_jcc );
12292 ins_short_branch(1);
12293 %}
12294
12295 // Jump Direct Conditional - using unsigned comparison
12296 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12297 match(If cop cmp);
12298 effect(USE labl);
12299
12300 ins_cost(300);
12301 format %{ "J$cop,us $labl" %}
12302 size(2);
12303 ins_encode %{
12304 Label* L = $labl$$label;
12305 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12306 %}
12307 ins_pipe( pipe_jcc );
12308 ins_short_branch(1);
12309 %}
12310
12311 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12312 match(If cop cmp);
12313 effect(USE labl);
12314
12315 ins_cost(300);
12316 format %{ "J$cop,us $labl" %}
12317 size(2);
12318 ins_encode %{
12319 Label* L = $labl$$label;
12320 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12321 %}
12322 ins_pipe( pipe_jcc );
12323 ins_short_branch(1);
12324 %}
12325
12326 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12327 match(If cop cmp);
12328 effect(USE labl);
12329
12330 ins_cost(300);
12331 format %{ $$template
12332 if ($cop$$cmpcode == Assembler::notEqual) {
12333 $$emit$$"JP,u,s $labl\n\t"
12334 $$emit$$"J$cop,u,s $labl"
12335 } else {
12336 $$emit$$"JP,u,s done\n\t"
12337 $$emit$$"J$cop,u,s $labl\n\t"
12338 $$emit$$"done:"
12339 }
12340 %}
12341 size(4);
12342 ins_encode %{
12343 Label* l = $labl$$label;
12344 if ($cop$$cmpcode == Assembler::notEqual) {
12345 __ jccb(Assembler::parity, *l);
12346 __ jccb(Assembler::notEqual, *l);
12347 } else if ($cop$$cmpcode == Assembler::equal) {
12348 Label done;
12349 __ jccb(Assembler::parity, done);
12350 __ jccb(Assembler::equal, *l);
12351 __ bind(done);
12352 } else {
12353 ShouldNotReachHere();
12354 }
12355 %}
12356 ins_pipe(pipe_jcc);
12357 ins_short_branch(1);
12358 %}
12359
12360 // ============================================================================
12361 // Long Compare
12362 //
12363 // Currently we hold longs in 2 registers. Comparing such values efficiently
12364 // is tricky. The flavor of compare used depends on whether we are testing
12365 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12366 // The GE test is the negated LT test. The LE test can be had by commuting
12367 // the operands (yielding a GE test) and then negating; negate again for the
12368 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12369 // NE test is negated from that.
12370
12371 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12372 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12373 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12374 // are collapsed internally in the ADLC's dfa-gen code. The match for
12375 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12376 // foo match ends up with the wrong leaf. One fix is to not match both
12377 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12378 // both forms beat the trinary form of long-compare and both are very useful
12379 // on Intel which has so few registers.
12380
12381 // Manifest a CmpL result in an integer register. Very painful.
12382 // This is the test to avoid.
12383 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12384 match(Set dst (CmpL3 src1 src2));
12385 effect( KILL flags );
12386 ins_cost(1000);
12387 format %{ "XOR $dst,$dst\n\t"
12388 "CMP $src1.hi,$src2.hi\n\t"
12389 "JLT,s m_one\n\t"
12390 "JGT,s p_one\n\t"
12391 "CMP $src1.lo,$src2.lo\n\t"
12392 "JB,s m_one\n\t"
12393 "JEQ,s done\n"
12394 "p_one:\tINC $dst\n\t"
12395 "JMP,s done\n"
12396 "m_one:\tDEC $dst\n"
12397 "done:" %}
12398 ins_encode %{
12399 Label p_one, m_one, done;
12400 __ xorptr($dst$$Register, $dst$$Register);
12401 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12402 __ jccb(Assembler::less, m_one);
12403 __ jccb(Assembler::greater, p_one);
12404 __ cmpl($src1$$Register, $src2$$Register);
12405 __ jccb(Assembler::below, m_one);
12406 __ jccb(Assembler::equal, done);
12407 __ bind(p_one);
12408 __ incrementl($dst$$Register);
12409 __ jmpb(done);
12410 __ bind(m_one);
12411 __ decrementl($dst$$Register);
12412 __ bind(done);
12413 %}
12414 ins_pipe( pipe_slow );
12415 %}
12416
12417 //======
12418 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12419 // compares. Can be used for LE or GT compares by reversing arguments.
12420 // NOT GOOD FOR EQ/NE tests.
12421 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12422 match( Set flags (CmpL src zero ));
12423 ins_cost(100);
12424 format %{ "TEST $src.hi,$src.hi" %}
12425 opcode(0x85);
12426 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12427 ins_pipe( ialu_cr_reg_reg );
12428 %}
12429
12430 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12431 // compares. Can be used for LE or GT compares by reversing arguments.
12432 // NOT GOOD FOR EQ/NE tests.
12433 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12434 match( Set flags (CmpL src1 src2 ));
12435 effect( TEMP tmp );
12436 ins_cost(300);
12437 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12438 "MOV $tmp,$src1.hi\n\t"
12439 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12440 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12441 ins_pipe( ialu_cr_reg_reg );
12442 %}
12443
12444 // Long compares reg < zero/req OR reg >= zero/req.
12445 // Just a wrapper for a normal branch, plus the predicate test.
12446 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12447 match(If cmp flags);
12448 effect(USE labl);
12449 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12450 expand %{
12451 jmpCon(cmp,flags,labl); // JLT or JGE...
12452 %}
12453 %}
12454
12455 // Compare 2 longs and CMOVE longs.
12456 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12457 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12458 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12459 ins_cost(400);
12460 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12461 "CMOV$cmp $dst.hi,$src.hi" %}
12462 opcode(0x0F,0x40);
12463 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12464 ins_pipe( pipe_cmov_reg_long );
12465 %}
12466
12467 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12468 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12469 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12470 ins_cost(500);
12471 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12472 "CMOV$cmp $dst.hi,$src.hi" %}
12473 opcode(0x0F,0x40);
12474 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12475 ins_pipe( pipe_cmov_reg_long );
12476 %}
12477
12478 // Compare 2 longs and CMOVE ints.
12479 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12480 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12481 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12482 ins_cost(200);
12483 format %{ "CMOV$cmp $dst,$src" %}
12484 opcode(0x0F,0x40);
12485 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12486 ins_pipe( pipe_cmov_reg );
12487 %}
12488
12489 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12490 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12491 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12492 ins_cost(250);
12493 format %{ "CMOV$cmp $dst,$src" %}
12494 opcode(0x0F,0x40);
12495 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12496 ins_pipe( pipe_cmov_mem );
12497 %}
12498
12499 // Compare 2 longs and CMOVE ints.
12500 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12501 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12502 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12503 ins_cost(200);
12504 format %{ "CMOV$cmp $dst,$src" %}
12505 opcode(0x0F,0x40);
12506 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12507 ins_pipe( pipe_cmov_reg );
12508 %}
12509
12510 // Compare 2 longs and CMOVE doubles
12511 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12512 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12513 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12514 ins_cost(200);
12515 expand %{
12516 fcmovDPR_regS(cmp,flags,dst,src);
12517 %}
12518 %}
12519
12520 // Compare 2 longs and CMOVE doubles
12521 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12522 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12523 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12524 ins_cost(200);
12525 expand %{
12526 fcmovD_regS(cmp,flags,dst,src);
12527 %}
12528 %}
12529
12530 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12531 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12532 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12533 ins_cost(200);
12534 expand %{
12535 fcmovFPR_regS(cmp,flags,dst,src);
12536 %}
12537 %}
12538
12539 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12540 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12541 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12542 ins_cost(200);
12543 expand %{
12544 fcmovF_regS(cmp,flags,dst,src);
12545 %}
12546 %}
12547
12548 //======
12549 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12550 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12551 match( Set flags (CmpL src zero ));
12552 effect(TEMP tmp);
12553 ins_cost(200);
12554 format %{ "MOV $tmp,$src.lo\n\t"
12555 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12556 ins_encode( long_cmp_flags0( src, tmp ) );
12557 ins_pipe( ialu_reg_reg_long );
12558 %}
12559
12560 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12561 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12562 match( Set flags (CmpL src1 src2 ));
12563 ins_cost(200+300);
12564 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12565 "JNE,s skip\n\t"
12566 "CMP $src1.hi,$src2.hi\n\t"
12567 "skip:\t" %}
12568 ins_encode( long_cmp_flags1( src1, src2 ) );
12569 ins_pipe( ialu_cr_reg_reg );
12570 %}
12571
12572 // Long compare reg == zero/reg OR reg != zero/reg
12573 // Just a wrapper for a normal branch, plus the predicate test.
12574 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12575 match(If cmp flags);
12576 effect(USE labl);
12577 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12578 expand %{
12579 jmpCon(cmp,flags,labl); // JEQ or JNE...
12580 %}
12581 %}
12582
12583 // Compare 2 longs and CMOVE longs.
12584 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12585 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12586 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12587 ins_cost(400);
12588 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12589 "CMOV$cmp $dst.hi,$src.hi" %}
12590 opcode(0x0F,0x40);
12591 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12592 ins_pipe( pipe_cmov_reg_long );
12593 %}
12594
12595 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12596 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12597 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12598 ins_cost(500);
12599 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12600 "CMOV$cmp $dst.hi,$src.hi" %}
12601 opcode(0x0F,0x40);
12602 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12603 ins_pipe( pipe_cmov_reg_long );
12604 %}
12605
12606 // Compare 2 longs and CMOVE ints.
12607 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12608 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12609 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12610 ins_cost(200);
12611 format %{ "CMOV$cmp $dst,$src" %}
12612 opcode(0x0F,0x40);
12613 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12614 ins_pipe( pipe_cmov_reg );
12615 %}
12616
12617 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12618 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12619 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12620 ins_cost(250);
12621 format %{ "CMOV$cmp $dst,$src" %}
12622 opcode(0x0F,0x40);
12623 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12624 ins_pipe( pipe_cmov_mem );
12625 %}
12626
12627 // Compare 2 longs and CMOVE ints.
12628 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12629 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12630 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12631 ins_cost(200);
12632 format %{ "CMOV$cmp $dst,$src" %}
12633 opcode(0x0F,0x40);
12634 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12635 ins_pipe( pipe_cmov_reg );
12636 %}
12637
12638 // Compare 2 longs and CMOVE doubles
12639 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12640 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12641 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12642 ins_cost(200);
12643 expand %{
12644 fcmovDPR_regS(cmp,flags,dst,src);
12645 %}
12646 %}
12647
12648 // Compare 2 longs and CMOVE doubles
12649 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12650 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12651 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12652 ins_cost(200);
12653 expand %{
12654 fcmovD_regS(cmp,flags,dst,src);
12655 %}
12656 %}
12657
12658 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12659 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12660 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12661 ins_cost(200);
12662 expand %{
12663 fcmovFPR_regS(cmp,flags,dst,src);
12664 %}
12665 %}
12666
12667 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12668 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12669 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12670 ins_cost(200);
12671 expand %{
12672 fcmovF_regS(cmp,flags,dst,src);
12673 %}
12674 %}
12675
12676 //======
12677 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12678 // Same as cmpL_reg_flags_LEGT except must negate src
12679 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12680 match( Set flags (CmpL src zero ));
12681 effect( TEMP tmp );
12682 ins_cost(300);
12683 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12684 "CMP $tmp,$src.lo\n\t"
12685 "SBB $tmp,$src.hi\n\t" %}
12686 ins_encode( long_cmp_flags3(src, tmp) );
12687 ins_pipe( ialu_reg_reg_long );
12688 %}
12689
12690 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12691 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12692 // requires a commuted test to get the same result.
12693 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12694 match( Set flags (CmpL src1 src2 ));
12695 effect( TEMP tmp );
12696 ins_cost(300);
12697 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12698 "MOV $tmp,$src2.hi\n\t"
12699 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12700 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12701 ins_pipe( ialu_cr_reg_reg );
12702 %}
12703
12704 // Long compares reg < zero/req OR reg >= zero/req.
12705 // Just a wrapper for a normal branch, plus the predicate test
12706 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12707 match(If cmp flags);
12708 effect(USE labl);
12709 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12710 ins_cost(300);
12711 expand %{
12712 jmpCon(cmp,flags,labl); // JGT or JLE...
12713 %}
12714 %}
12715
12716 // Compare 2 longs and CMOVE longs.
12717 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12718 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12719 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12720 ins_cost(400);
12721 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12722 "CMOV$cmp $dst.hi,$src.hi" %}
12723 opcode(0x0F,0x40);
12724 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12725 ins_pipe( pipe_cmov_reg_long );
12726 %}
12727
12728 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12729 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12730 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12731 ins_cost(500);
12732 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12733 "CMOV$cmp $dst.hi,$src.hi+4" %}
12734 opcode(0x0F,0x40);
12735 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12736 ins_pipe( pipe_cmov_reg_long );
12737 %}
12738
12739 // Compare 2 longs and CMOVE ints.
12740 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12741 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12742 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12743 ins_cost(200);
12744 format %{ "CMOV$cmp $dst,$src" %}
12745 opcode(0x0F,0x40);
12746 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12747 ins_pipe( pipe_cmov_reg );
12748 %}
12749
12750 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12751 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12752 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12753 ins_cost(250);
12754 format %{ "CMOV$cmp $dst,$src" %}
12755 opcode(0x0F,0x40);
12756 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12757 ins_pipe( pipe_cmov_mem );
12758 %}
12759
12760 // Compare 2 longs and CMOVE ptrs.
12761 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12762 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12763 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12764 ins_cost(200);
12765 format %{ "CMOV$cmp $dst,$src" %}
12766 opcode(0x0F,0x40);
12767 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12768 ins_pipe( pipe_cmov_reg );
12769 %}
12770
12771 // Compare 2 longs and CMOVE doubles
12772 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12773 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12774 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12775 ins_cost(200);
12776 expand %{
12777 fcmovDPR_regS(cmp,flags,dst,src);
12778 %}
12779 %}
12780
12781 // Compare 2 longs and CMOVE doubles
12782 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12783 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12784 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12785 ins_cost(200);
12786 expand %{
12787 fcmovD_regS(cmp,flags,dst,src);
12788 %}
12789 %}
12790
12791 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12792 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12793 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12794 ins_cost(200);
12795 expand %{
12796 fcmovFPR_regS(cmp,flags,dst,src);
12797 %}
12798 %}
12799
12800
12801 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12802 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12803 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12804 ins_cost(200);
12805 expand %{
12806 fcmovF_regS(cmp,flags,dst,src);
12807 %}
12808 %}
12809
12810
12811 // ============================================================================
12812 // Procedure Call/Return Instructions
12813 // Call Java Static Instruction
12814 // Note: If this code changes, the corresponding ret_addr_offset() and
12815 // compute_padding() functions will have to be adjusted.
12816 instruct CallStaticJavaDirect(method meth) %{
12817 match(CallStaticJava);
12818 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12819 effect(USE meth);
12820
12821 ins_cost(300);
12822 format %{ "CALL,static " %}
12823 opcode(0xE8); /* E8 cd */
12824 ins_encode( pre_call_FPU,
12825 Java_Static_Call( meth ),
12826 call_epilog,
12827 post_call_FPU );
12828 ins_pipe( pipe_slow );
12829 ins_alignment(4);
12830 %}
12831
12832 // Call Java Static Instruction (method handle version)
12833 // Note: If this code changes, the corresponding ret_addr_offset() and
12834 // compute_padding() functions will have to be adjusted.
12835 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12836 match(CallStaticJava);
12837 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12838 effect(USE meth);
12839 // EBP is saved by all callees (for interpreter stack correction).
12840 // We use it here for a similar purpose, in {preserve,restore}_SP.
12841
12842 ins_cost(300);
12843 format %{ "CALL,static/MethodHandle " %}
12844 opcode(0xE8); /* E8 cd */
12845 ins_encode( pre_call_FPU,
12846 preserve_SP,
12847 Java_Static_Call( meth ),
12848 restore_SP,
12849 call_epilog,
12850 post_call_FPU );
12851 ins_pipe( pipe_slow );
12852 ins_alignment(4);
12853 %}
12854
12855 // Call Java Dynamic Instruction
12856 // Note: If this code changes, the corresponding ret_addr_offset() and
12857 // compute_padding() functions will have to be adjusted.
12858 instruct CallDynamicJavaDirect(method meth) %{
12859 match(CallDynamicJava);
12860 effect(USE meth);
12861
12862 ins_cost(300);
12863 format %{ "MOV EAX,(oop)-1\n\t"
12864 "CALL,dynamic" %}
12865 opcode(0xE8); /* E8 cd */
12866 ins_encode( pre_call_FPU,
12867 Java_Dynamic_Call( meth ),
12868 call_epilog,
12869 post_call_FPU );
12870 ins_pipe( pipe_slow );
12871 ins_alignment(4);
12872 %}
12873
12874 // Call Runtime Instruction
12875 instruct CallRuntimeDirect(method meth) %{
12876 match(CallRuntime );
12877 effect(USE meth);
12878
12879 ins_cost(300);
12880 format %{ "CALL,runtime " %}
12881 opcode(0xE8); /* E8 cd */
12882 // Use FFREEs to clear entries in float stack
12883 ins_encode( pre_call_FPU,
12884 FFree_Float_Stack_All,
12885 Java_To_Runtime( meth ),
12886 post_call_FPU );
12887 ins_pipe( pipe_slow );
12888 %}
12889
12890 // Call runtime without safepoint
12891 instruct CallLeafDirect(method meth) %{
12892 match(CallLeaf);
12893 effect(USE meth);
12894
12895 ins_cost(300);
12896 format %{ "CALL_LEAF,runtime " %}
12897 opcode(0xE8); /* E8 cd */
12898 ins_encode( pre_call_FPU,
12899 FFree_Float_Stack_All,
12900 Java_To_Runtime( meth ),
12901 Verify_FPU_For_Leaf, post_call_FPU );
12902 ins_pipe( pipe_slow );
12903 %}
12904
12905 instruct CallLeafNoFPDirect(method meth) %{
12906 match(CallLeafNoFP);
12907 effect(USE meth);
12908
12909 ins_cost(300);
12910 format %{ "CALL_LEAF_NOFP,runtime " %}
12911 opcode(0xE8); /* E8 cd */
12912 ins_encode(Java_To_Runtime(meth));
12913 ins_pipe( pipe_slow );
12914 %}
12915
12916
12917 // Return Instruction
12918 // Remove the return address & jump to it.
12919 instruct Ret() %{
12920 match(Return);
12921 format %{ "RET" %}
12922 opcode(0xC3);
12923 ins_encode(OpcP);
12924 ins_pipe( pipe_jmp );
12925 %}
12926
12927 // Tail Call; Jump from runtime stub to Java code.
12928 // Also known as an 'interprocedural jump'.
12929 // Target of jump will eventually return to caller.
12930 // TailJump below removes the return address.
12931 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12932 match(TailCall jump_target method_oop );
12933 ins_cost(300);
12934 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12935 opcode(0xFF, 0x4); /* Opcode FF /4 */
12936 ins_encode( OpcP, RegOpc(jump_target) );
12937 ins_pipe( pipe_jmp );
12938 %}
12939
12940
12941 // Tail Jump; remove the return address; jump to target.
12942 // TailCall above leaves the return address around.
12943 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12944 match( TailJump jump_target ex_oop );
12945 ins_cost(300);
12946 format %{ "POP EDX\t# pop return address into dummy\n\t"
12947 "JMP $jump_target " %}
12948 opcode(0xFF, 0x4); /* Opcode FF /4 */
12949 ins_encode( enc_pop_rdx,
12950 OpcP, RegOpc(jump_target) );
12951 ins_pipe( pipe_jmp );
12952 %}
12953
12954 // Create exception oop: created by stack-crawling runtime code.
12955 // Created exception is now available to this handler, and is setup
12956 // just prior to jumping to this handler. No code emitted.
12957 instruct CreateException( eAXRegP ex_oop )
12958 %{
12959 match(Set ex_oop (CreateEx));
12960
12961 size(0);
12962 // use the following format syntax
12963 format %{ "# exception oop is in EAX; no code emitted" %}
12964 ins_encode();
12965 ins_pipe( empty );
12966 %}
12967
12968
12969 // Rethrow exception:
12970 // The exception oop will come in the first argument position.
12971 // Then JUMP (not call) to the rethrow stub code.
12972 instruct RethrowException()
12973 %{
12974 match(Rethrow);
12975
12976 // use the following format syntax
12977 format %{ "JMP rethrow_stub" %}
12978 ins_encode(enc_rethrow);
12979 ins_pipe( pipe_jmp );
12980 %}
12981
12982 // inlined locking and unlocking
12983
12984
12985 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12986 match( Set cr (FastLock object box) );
12987 effect( TEMP tmp, TEMP scr, USE_KILL box );
12988 ins_cost(300);
12989 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12990 ins_encode( Fast_Lock(object,box,tmp,scr) );
12991 ins_pipe( pipe_slow );
12992 %}
12993
12994 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12995 match( Set cr (FastUnlock object box) );
12996 effect( TEMP tmp, USE_KILL box );
12997 ins_cost(300);
12998 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12999 ins_encode( Fast_Unlock(object,box,tmp) );
13000 ins_pipe( pipe_slow );
13001 %}
13002
13003
13004
13005 // ============================================================================
13006 // Safepoint Instruction
13007 instruct safePoint_poll(eFlagsReg cr) %{
13008 match(SafePoint);
13009 effect(KILL cr);
13010
13011 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13012 // On SPARC that might be acceptable as we can generate the address with
13013 // just a sethi, saving an or. By polling at offset 0 we can end up
13014 // putting additional pressure on the index-0 in the D$. Because of
13015 // alignment (just like the situation at hand) the lower indices tend
13016 // to see more traffic. It'd be better to change the polling address
13017 // to offset 0 of the last $line in the polling page.
13018
13019 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13020 ins_cost(125);
13021 size(6) ;
13022 ins_encode( Safepoint_Poll() );
13023 ins_pipe( ialu_reg_mem );
13024 %}
13025
13026
13027 // ============================================================================
13028 // This name is KNOWN by the ADLC and cannot be changed.
13029 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13030 // for this guy.
13031 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13032 match(Set dst (ThreadLocal));
13033 effect(DEF dst, KILL cr);
13034
13035 format %{ "MOV $dst, Thread::current()" %}
13036 ins_encode %{
13037 Register dstReg = as_Register($dst$$reg);
13038 __ get_thread(dstReg);
13039 %}
13040 ins_pipe( ialu_reg_fat );
13041 %}
13042
13043
13044
13045 //----------PEEPHOLE RULES-----------------------------------------------------
13046 // These must follow all instruction definitions as they use the names
13047 // defined in the instructions definitions.
13048 //
13049 // peepmatch ( root_instr_name [preceding_instruction]* );
13050 //
13051 // peepconstraint %{
13052 // (instruction_number.operand_name relational_op instruction_number.operand_name
13053 // [, ...] );
13054 // // instruction numbers are zero-based using left to right order in peepmatch
13055 //
13056 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13057 // // provide an instruction_number.operand_name for each operand that appears
13058 // // in the replacement instruction's match rule
13059 //
13060 // ---------VM FLAGS---------------------------------------------------------
13061 //
13062 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13063 //
13064 // Each peephole rule is given an identifying number starting with zero and
13065 // increasing by one in the order seen by the parser. An individual peephole
13066 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13067 // on the command-line.
13068 //
13069 // ---------CURRENT LIMITATIONS----------------------------------------------
13070 //
13071 // Only match adjacent instructions in same basic block
13072 // Only equality constraints
13073 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13074 // Only one replacement instruction
13075 //
13076 // ---------EXAMPLE----------------------------------------------------------
13077 //
13078 // // pertinent parts of existing instructions in architecture description
13079 // instruct movI(rRegI dst, rRegI src) %{
13080 // match(Set dst (CopyI src));
13081 // %}
13082 //
13083 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13084 // match(Set dst (AddI dst src));
13085 // effect(KILL cr);
13086 // %}
13087 //
13088 // // Change (inc mov) to lea
13089 // peephole %{
13090 // // increment preceeded by register-register move
13091 // peepmatch ( incI_eReg movI );
13092 // // require that the destination register of the increment
13093 // // match the destination register of the move
13094 // peepconstraint ( 0.dst == 1.dst );
13095 // // construct a replacement instruction that sets
13096 // // the destination to ( move's source register + one )
13097 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13098 // %}
13099 //
13100 // Implementation no longer uses movX instructions since
13101 // machine-independent system no longer uses CopyX nodes.
13102 //
13103 // peephole %{
13104 // peepmatch ( incI_eReg movI );
13105 // peepconstraint ( 0.dst == 1.dst );
13106 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13107 // %}
13108 //
13109 // peephole %{
13110 // peepmatch ( decI_eReg movI );
13111 // peepconstraint ( 0.dst == 1.dst );
13112 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13113 // %}
13114 //
13115 // peephole %{
13116 // peepmatch ( addI_eReg_imm movI );
13117 // peepconstraint ( 0.dst == 1.dst );
13118 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13119 // %}
13120 //
13121 // peephole %{
13122 // peepmatch ( addP_eReg_imm movP );
13123 // peepconstraint ( 0.dst == 1.dst );
13124 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13125 // %}
13126
13127 // // Change load of spilled value to only a spill
13128 // instruct storeI(memory mem, rRegI src) %{
13129 // match(Set mem (StoreI mem src));
13130 // %}
13131 //
13132 // instruct loadI(rRegI dst, memory mem) %{
13133 // match(Set dst (LoadI mem));
13134 // %}
13135 //
13136 peephole %{
13137 peepmatch ( loadI storeI );
13138 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13139 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13140 %}
13141
13142 //----------SMARTSPILL RULES---------------------------------------------------
13143 // These must follow all instruction definitions as they use the names
13144 // defined in the instructions definitions.