1 //
2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
186
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
201
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
215
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
228
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
241
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
244
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
247
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
250
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
253
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
256
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
259
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
262
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
277
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
304
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
318
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
321
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
324
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
327
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
342
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
356
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
369
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
372
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
375
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
378
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
381
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
384
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
387
388 %}
389
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
396
397 #define __ _masm.
398
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402
403 // !!!!! Special hack to get all types of calls to specify the byte offset
404 // from the start of the call to the point where the return address
405 // will point.
406 int MachCallStaticJavaNode::ret_addr_offset()
407 {
408 int offset = 5; // 5 bytes from start of call to where return address points
409 if (_method_handle_invoke)
410 offset += preserve_SP_size();
411 return offset;
412 }
413
414 int MachCallDynamicJavaNode::ret_addr_offset()
415 {
416 return 15; // 15 bytes from start of call to where return address points
417 }
418
419 // In os_cpu .ad file
420 // int MachCallRuntimeNode::ret_addr_offset()
421
422 // Indicate if the safepoint node needs the polling page as an input,
423 // it does if the polling page is more than disp32 away.
424 bool SafePointNode::needs_polling_address_input()
425 {
426 return Assembler::is_polling_page_far();
427 }
428
429 //
430 // Compute padding required for nodes which need alignment
431 //
432
433 // The address of the call instruction needs to be 4-byte aligned to
434 // ensure that it does not span a cache line so that it can be patched.
435 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
436 {
437 current_offset += 1; // skip call opcode byte
438 return round_to(current_offset, alignment_required()) - current_offset;
439 }
440
441 // The address of the call instruction needs to be 4-byte aligned to
442 // ensure that it does not span a cache line so that it can be patched.
443 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
444 {
445 current_offset += preserve_SP_size(); // skip mov rbp, rsp
446 current_offset += 1; // skip call opcode byte
447 return round_to(current_offset, alignment_required()) - current_offset;
448 }
449
450 // The address of the call instruction needs to be 4-byte aligned to
451 // ensure that it does not span a cache line so that it can be patched.
452 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
453 {
454 current_offset += 11; // skip movq instruction + call opcode byte
455 return round_to(current_offset, alignment_required()) - current_offset;
456 }
457
458 // EMIT_RM()
459 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
460 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
461 cbuf.insts()->emit_int8(c);
462 }
463
464 // EMIT_CC()
465 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
466 unsigned char c = (unsigned char) (f1 | f2);
467 cbuf.insts()->emit_int8(c);
468 }
469
470 // EMIT_OPCODE()
471 void emit_opcode(CodeBuffer &cbuf, int code) {
472 cbuf.insts()->emit_int8((unsigned char) code);
473 }
474
475 // EMIT_OPCODE() w/ relocation information
476 void emit_opcode(CodeBuffer &cbuf,
477 int code, relocInfo::relocType reloc, int offset, int format)
478 {
479 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
480 emit_opcode(cbuf, code);
481 }
482
483 // EMIT_D8()
484 void emit_d8(CodeBuffer &cbuf, int d8) {
485 cbuf.insts()->emit_int8((unsigned char) d8);
486 }
487
488 // EMIT_D16()
489 void emit_d16(CodeBuffer &cbuf, int d16) {
490 cbuf.insts()->emit_int16(d16);
491 }
492
493 // EMIT_D32()
494 void emit_d32(CodeBuffer &cbuf, int d32) {
495 cbuf.insts()->emit_int32(d32);
496 }
497
498 // EMIT_D64()
499 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
500 cbuf.insts()->emit_int64(d64);
501 }
502
503 // emit 32 bit value and construct relocation entry from relocInfo::relocType
504 void emit_d32_reloc(CodeBuffer& cbuf,
505 int d32,
506 relocInfo::relocType reloc,
507 int format)
508 {
509 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
510 cbuf.relocate(cbuf.insts_mark(), reloc, format);
511 cbuf.insts()->emit_int32(d32);
512 }
513
514 // emit 32 bit value and construct relocation entry from RelocationHolder
515 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
516 #ifdef ASSERT
517 if (rspec.reloc()->type() == relocInfo::oop_type &&
518 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
519 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
520 }
521 #endif
522 cbuf.relocate(cbuf.insts_mark(), rspec, format);
523 cbuf.insts()->emit_int32(d32);
524 }
525
526 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
527 address next_ip = cbuf.insts_end() + 4;
528 emit_d32_reloc(cbuf, (int) (addr - next_ip),
529 external_word_Relocation::spec(addr),
530 RELOC_DISP32);
531 }
532
533
534 // emit 64 bit value and construct relocation entry from relocInfo::relocType
535 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
536 cbuf.relocate(cbuf.insts_mark(), reloc, format);
537 cbuf.insts()->emit_int64(d64);
538 }
539
540 // emit 64 bit value and construct relocation entry from RelocationHolder
541 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
542 #ifdef ASSERT
543 if (rspec.reloc()->type() == relocInfo::oop_type &&
544 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
545 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
546 "cannot embed scavengable oops in code");
547 }
548 #endif
549 cbuf.relocate(cbuf.insts_mark(), rspec, format);
550 cbuf.insts()->emit_int64(d64);
551 }
552
553 // Access stack slot for load or store
554 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
555 {
556 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
557 if (-0x80 <= disp && disp < 0x80) {
558 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
559 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
560 emit_d8(cbuf, disp); // Displacement // R/M byte
561 } else {
562 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
563 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
564 emit_d32(cbuf, disp); // Displacement // R/M byte
565 }
566 }
567
568 // rRegI ereg, memory mem) %{ // emit_reg_mem
569 void encode_RegMem(CodeBuffer &cbuf,
570 int reg,
571 int base, int index, int scale, int disp, bool disp_is_oop)
572 {
573 assert(!disp_is_oop, "cannot have disp");
574 int regenc = reg & 7;
575 int baseenc = base & 7;
576 int indexenc = index & 7;
577
578 // There is no index & no scale, use form without SIB byte
579 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
580 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
581 if (disp == 0 && base != RBP_enc && base != R13_enc) {
582 emit_rm(cbuf, 0x0, regenc, baseenc); // *
583 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
584 // If 8-bit displacement, mode 0x1
585 emit_rm(cbuf, 0x1, regenc, baseenc); // *
586 emit_d8(cbuf, disp);
587 } else {
588 // If 32-bit displacement
589 if (base == -1) { // Special flag for absolute address
590 emit_rm(cbuf, 0x0, regenc, 0x5); // *
591 if (disp_is_oop) {
592 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
593 } else {
594 emit_d32(cbuf, disp);
595 }
596 } else {
597 // Normal base + offset
598 emit_rm(cbuf, 0x2, regenc, baseenc); // *
599 if (disp_is_oop) {
600 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
601 } else {
602 emit_d32(cbuf, disp);
603 }
604 }
605 }
606 } else {
607 // Else, encode with the SIB byte
608 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
609 if (disp == 0 && base != RBP_enc && base != R13_enc) {
610 // If no displacement
611 emit_rm(cbuf, 0x0, regenc, 0x4); // *
612 emit_rm(cbuf, scale, indexenc, baseenc);
613 } else {
614 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
615 // If 8-bit displacement, mode 0x1
616 emit_rm(cbuf, 0x1, regenc, 0x4); // *
617 emit_rm(cbuf, scale, indexenc, baseenc);
618 emit_d8(cbuf, disp);
619 } else {
620 // If 32-bit displacement
621 if (base == 0x04 ) {
622 emit_rm(cbuf, 0x2, regenc, 0x4);
623 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
624 } else {
625 emit_rm(cbuf, 0x2, regenc, 0x4);
626 emit_rm(cbuf, scale, indexenc, baseenc); // *
627 }
628 if (disp_is_oop) {
629 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
630 } else {
631 emit_d32(cbuf, disp);
632 }
633 }
634 }
635 }
636 }
637
638 // This could be in MacroAssembler but it's fairly C2 specific
639 void emit_cmpfp_fixup(MacroAssembler& _masm) {
640 Label exit;
641 __ jccb(Assembler::noParity, exit);
642 __ pushf();
643 //
644 // comiss/ucomiss instructions set ZF,PF,CF flags and
645 // zero OF,AF,SF for NaN values.
646 // Fixup flags by zeroing ZF,PF so that compare of NaN
647 // values returns 'less than' result (CF is set).
648 // Leave the rest of flags unchanged.
649 //
650 // 7 6 5 4 3 2 1 0
651 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
652 // 0 0 1 0 1 0 1 1 (0x2B)
653 //
654 __ andq(Address(rsp, 0), 0xffffff2b);
655 __ popf();
656 __ bind(exit);
657 }
658
659 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
660 Label done;
661 __ movl(dst, -1);
662 __ jcc(Assembler::parity, done);
663 __ jcc(Assembler::below, done);
664 __ setb(Assembler::notEqual, dst);
665 __ movzbl(dst, dst);
666 __ bind(done);
667 }
668
669
670 //=============================================================================
671 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
672
673 int Compile::ConstantTable::calculate_table_base_offset() const {
674 return 0; // absolute addressing, no offset
675 }
676
677 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
678 // Empty encoding
679 }
680
681 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
682 return 0;
683 }
684
685 #ifndef PRODUCT
686 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
687 st->print("# MachConstantBaseNode (empty encoding)");
688 }
689 #endif
690
691
692 //=============================================================================
693 #ifndef PRODUCT
694 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
695 Compile* C = ra_->C;
696
697 int framesize = C->frame_slots() << LogBytesPerInt;
698 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
699 // Remove wordSize for return addr which is already pushed.
700 framesize -= wordSize;
701
702 if (C->need_stack_bang(framesize)) {
703 framesize -= wordSize;
704 st->print("# stack bang");
705 st->print("\n\t");
706 st->print("pushq rbp\t# Save rbp");
707 if (framesize) {
708 st->print("\n\t");
709 st->print("subq rsp, #%d\t# Create frame",framesize);
710 }
711 } else {
712 st->print("subq rsp, #%d\t# Create frame",framesize);
713 st->print("\n\t");
714 framesize -= wordSize;
715 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
716 }
717
718 if (VerifyStackAtCalls) {
719 st->print("\n\t");
720 framesize -= wordSize;
721 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
722 #ifdef ASSERT
723 st->print("\n\t");
724 st->print("# stack alignment check");
725 #endif
726 }
727 st->cr();
728 }
729 #endif
730
731 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
732 Compile* C = ra_->C;
733 MacroAssembler _masm(&cbuf);
734
735 int framesize = C->frame_slots() << LogBytesPerInt;
736
737 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
738
739 C->set_frame_complete(cbuf.insts_size());
740
741 if (C->has_mach_constant_base_node()) {
742 // NOTE: We set the table base offset here because users might be
743 // emitted before MachConstantBaseNode.
744 Compile::ConstantTable& constant_table = C->constant_table();
745 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
746 }
747 }
748
749 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
750 {
751 return MachNode::size(ra_); // too many variables; just compute it
752 // the hard way
753 }
754
755 int MachPrologNode::reloc() const
756 {
757 return 0; // a large enough number
758 }
759
760 //=============================================================================
761 #ifndef PRODUCT
762 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
763 {
764 Compile* C = ra_->C;
765 int framesize = C->frame_slots() << LogBytesPerInt;
766 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
767 // Remove word for return adr already pushed
768 // and RBP
769 framesize -= 2*wordSize;
770
771 if (framesize) {
772 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
773 st->print("\t");
774 }
775
776 st->print_cr("popq rbp");
777 if (do_polling() && C->is_method_compilation()) {
778 st->print("\t");
779 if (Assembler::is_polling_page_far()) {
780 st->print_cr("movq rscratch1, #polling_page_address\n\t"
781 "testl rax, [rscratch1]\t"
782 "# Safepoint: poll for GC");
783 } else {
784 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
785 "# Safepoint: poll for GC");
786 }
787 }
788 }
789 #endif
790
791 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
792 {
793 Compile* C = ra_->C;
794 int framesize = C->frame_slots() << LogBytesPerInt;
795 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
796 // Remove word for return adr already pushed
797 // and RBP
798 framesize -= 2*wordSize;
799
800 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
801
802 if (framesize) {
803 emit_opcode(cbuf, Assembler::REX_W);
804 if (framesize < 0x80) {
805 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
806 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
807 emit_d8(cbuf, framesize);
808 } else {
809 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
810 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
811 emit_d32(cbuf, framesize);
812 }
813 }
814
815 // popq rbp
816 emit_opcode(cbuf, 0x58 | RBP_enc);
817
818 if (do_polling() && C->is_method_compilation()) {
819 MacroAssembler _masm(&cbuf);
820 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
821 if (Assembler::is_polling_page_far()) {
822 __ lea(rscratch1, polling_page);
823 __ relocate(relocInfo::poll_return_type);
824 __ testl(rax, Address(rscratch1, 0));
825 } else {
826 __ testl(rax, polling_page);
827 }
828 }
829 }
830
831 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
832 {
833 return MachNode::size(ra_); // too many variables; just compute it
834 // the hard way
835 }
836
837 int MachEpilogNode::reloc() const
838 {
839 return 2; // a large enough number
840 }
841
842 const Pipeline* MachEpilogNode::pipeline() const
843 {
844 return MachNode::pipeline_class();
845 }
846
847 int MachEpilogNode::safepoint_offset() const
848 {
849 return 0;
850 }
851
852 //=============================================================================
853
854 enum RC {
855 rc_bad,
856 rc_int,
857 rc_float,
858 rc_stack
859 };
860
861 static enum RC rc_class(OptoReg::Name reg)
862 {
863 if( !OptoReg::is_valid(reg) ) return rc_bad;
864
865 if (OptoReg::is_stack(reg)) return rc_stack;
866
867 VMReg r = OptoReg::as_VMReg(reg);
868
869 if (r->is_Register()) return rc_int;
870
871 assert(r->is_XMMRegister(), "must be");
872 return rc_float;
873 }
874
875 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
876 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
877 int src_hi, int dst_hi, uint ireg, outputStream* st);
878
879 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
880 int stack_offset, int reg, uint ireg, outputStream* st);
881
882 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
883 int dst_offset, uint ireg, outputStream* st) {
884 if (cbuf) {
885 MacroAssembler _masm(cbuf);
886 switch (ireg) {
887 case Op_VecS:
888 __ movq(Address(rsp, -8), rax);
889 __ movl(rax, Address(rsp, src_offset));
890 __ movl(Address(rsp, dst_offset), rax);
891 __ movq(rax, Address(rsp, -8));
892 break;
893 case Op_VecD:
894 __ pushq(Address(rsp, src_offset));
895 __ popq (Address(rsp, dst_offset));
896 break;
897 case Op_VecX:
898 __ pushq(Address(rsp, src_offset));
899 __ popq (Address(rsp, dst_offset));
900 __ pushq(Address(rsp, src_offset+8));
901 __ popq (Address(rsp, dst_offset+8));
902 break;
903 case Op_VecY:
904 __ vmovdqu(Address(rsp, -32), xmm0);
905 __ vmovdqu(xmm0, Address(rsp, src_offset));
906 __ vmovdqu(Address(rsp, dst_offset), xmm0);
907 __ vmovdqu(xmm0, Address(rsp, -32));
908 break;
909 default:
910 ShouldNotReachHere();
911 }
912 #ifndef PRODUCT
913 } else {
914 switch (ireg) {
915 case Op_VecS:
916 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
917 "movl rax, [rsp + #%d]\n\t"
918 "movl [rsp + #%d], rax\n\t"
919 "movq rax, [rsp - #8]",
920 src_offset, dst_offset);
921 break;
922 case Op_VecD:
923 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
924 "popq [rsp + #%d]",
925 src_offset, dst_offset);
926 break;
927 case Op_VecX:
928 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
929 "popq [rsp + #%d]\n\t"
930 "pushq [rsp + #%d]\n\t"
931 "popq [rsp + #%d]",
932 src_offset, dst_offset, src_offset+8, dst_offset+8);
933 break;
934 case Op_VecY:
935 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
936 "vmovdqu xmm0, [rsp + #%d]\n\t"
937 "vmovdqu [rsp + #%d], xmm0\n\t"
938 "vmovdqu xmm0, [rsp - #32]",
939 src_offset, dst_offset);
940 break;
941 default:
942 ShouldNotReachHere();
943 }
944 #endif
945 }
946 }
947
948 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
949 PhaseRegAlloc* ra_,
950 bool do_size,
951 outputStream* st) const {
952 assert(cbuf != NULL || st != NULL, "sanity");
953 // Get registers to move
954 OptoReg::Name src_second = ra_->get_reg_second(in(1));
955 OptoReg::Name src_first = ra_->get_reg_first(in(1));
956 OptoReg::Name dst_second = ra_->get_reg_second(this);
957 OptoReg::Name dst_first = ra_->get_reg_first(this);
958
959 enum RC src_second_rc = rc_class(src_second);
960 enum RC src_first_rc = rc_class(src_first);
961 enum RC dst_second_rc = rc_class(dst_second);
962 enum RC dst_first_rc = rc_class(dst_first);
963
964 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
965 "must move at least 1 register" );
966
967 if (src_first == dst_first && src_second == dst_second) {
968 // Self copy, no move
969 return 0;
970 }
971 if (bottom_type()->isa_vect() != NULL) {
972 uint ireg = ideal_reg();
973 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
974 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
975 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
976 // mem -> mem
977 int src_offset = ra_->reg2offset(src_first);
978 int dst_offset = ra_->reg2offset(dst_first);
979 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
980 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
981 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
982 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
983 int stack_offset = ra_->reg2offset(dst_first);
984 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
985 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
986 int stack_offset = ra_->reg2offset(src_first);
987 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
988 } else {
989 ShouldNotReachHere();
990 }
991 return 0;
992 }
993 if (src_first_rc == rc_stack) {
994 // mem ->
995 if (dst_first_rc == rc_stack) {
996 // mem -> mem
997 assert(src_second != dst_first, "overlap");
998 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
999 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1000 // 64-bit
1001 int src_offset = ra_->reg2offset(src_first);
1002 int dst_offset = ra_->reg2offset(dst_first);
1003 if (cbuf) {
1004 MacroAssembler _masm(cbuf);
1005 __ pushq(Address(rsp, src_offset));
1006 __ popq (Address(rsp, dst_offset));
1007 #ifndef PRODUCT
1008 } else {
1009 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1010 "popq [rsp + #%d]",
1011 src_offset, dst_offset);
1012 #endif
1013 }
1014 } else {
1015 // 32-bit
1016 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1017 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1018 // No pushl/popl, so:
1019 int src_offset = ra_->reg2offset(src_first);
1020 int dst_offset = ra_->reg2offset(dst_first);
1021 if (cbuf) {
1022 MacroAssembler _masm(cbuf);
1023 __ movq(Address(rsp, -8), rax);
1024 __ movl(rax, Address(rsp, src_offset));
1025 __ movl(Address(rsp, dst_offset), rax);
1026 __ movq(rax, Address(rsp, -8));
1027 #ifndef PRODUCT
1028 } else {
1029 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1030 "movl rax, [rsp + #%d]\n\t"
1031 "movl [rsp + #%d], rax\n\t"
1032 "movq rax, [rsp - #8]",
1033 src_offset, dst_offset);
1034 #endif
1035 }
1036 }
1037 return 0;
1038 } else if (dst_first_rc == rc_int) {
1039 // mem -> gpr
1040 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1041 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1042 // 64-bit
1043 int offset = ra_->reg2offset(src_first);
1044 if (cbuf) {
1045 MacroAssembler _masm(cbuf);
1046 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1047 #ifndef PRODUCT
1048 } else {
1049 st->print("movq %s, [rsp + #%d]\t# spill",
1050 Matcher::regName[dst_first],
1051 offset);
1052 #endif
1053 }
1054 } else {
1055 // 32-bit
1056 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1057 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1058 int offset = ra_->reg2offset(src_first);
1059 if (cbuf) {
1060 MacroAssembler _masm(cbuf);
1061 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1062 #ifndef PRODUCT
1063 } else {
1064 st->print("movl %s, [rsp + #%d]\t# spill",
1065 Matcher::regName[dst_first],
1066 offset);
1067 #endif
1068 }
1069 }
1070 return 0;
1071 } else if (dst_first_rc == rc_float) {
1072 // mem-> xmm
1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1075 // 64-bit
1076 int offset = ra_->reg2offset(src_first);
1077 if (cbuf) {
1078 MacroAssembler _masm(cbuf);
1079 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1080 #ifndef PRODUCT
1081 } else {
1082 st->print("%s %s, [rsp + #%d]\t# spill",
1083 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1084 Matcher::regName[dst_first],
1085 offset);
1086 #endif
1087 }
1088 } else {
1089 // 32-bit
1090 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1091 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1092 int offset = ra_->reg2offset(src_first);
1093 if (cbuf) {
1094 MacroAssembler _masm(cbuf);
1095 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1096 #ifndef PRODUCT
1097 } else {
1098 st->print("movss %s, [rsp + #%d]\t# spill",
1099 Matcher::regName[dst_first],
1100 offset);
1101 #endif
1102 }
1103 }
1104 return 0;
1105 }
1106 } else if (src_first_rc == rc_int) {
1107 // gpr ->
1108 if (dst_first_rc == rc_stack) {
1109 // gpr -> mem
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1112 // 64-bit
1113 int offset = ra_->reg2offset(dst_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1117 #ifndef PRODUCT
1118 } else {
1119 st->print("movq [rsp + #%d], %s\t# spill",
1120 offset,
1121 Matcher::regName[src_first]);
1122 #endif
1123 }
1124 } else {
1125 // 32-bit
1126 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1127 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1128 int offset = ra_->reg2offset(dst_first);
1129 if (cbuf) {
1130 MacroAssembler _masm(cbuf);
1131 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1132 #ifndef PRODUCT
1133 } else {
1134 st->print("movl [rsp + #%d], %s\t# spill",
1135 offset,
1136 Matcher::regName[src_first]);
1137 #endif
1138 }
1139 }
1140 return 0;
1141 } else if (dst_first_rc == rc_int) {
1142 // gpr -> gpr
1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1145 // 64-bit
1146 if (cbuf) {
1147 MacroAssembler _masm(cbuf);
1148 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1149 as_Register(Matcher::_regEncode[src_first]));
1150 #ifndef PRODUCT
1151 } else {
1152 st->print("movq %s, %s\t# spill",
1153 Matcher::regName[dst_first],
1154 Matcher::regName[src_first]);
1155 #endif
1156 }
1157 return 0;
1158 } else {
1159 // 32-bit
1160 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1161 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1162 if (cbuf) {
1163 MacroAssembler _masm(cbuf);
1164 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1165 as_Register(Matcher::_regEncode[src_first]));
1166 #ifndef PRODUCT
1167 } else {
1168 st->print("movl %s, %s\t# spill",
1169 Matcher::regName[dst_first],
1170 Matcher::regName[src_first]);
1171 #endif
1172 }
1173 return 0;
1174 }
1175 } else if (dst_first_rc == rc_float) {
1176 // gpr -> xmm
1177 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1178 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1179 // 64-bit
1180 if (cbuf) {
1181 MacroAssembler _masm(cbuf);
1182 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1183 #ifndef PRODUCT
1184 } else {
1185 st->print("movdq %s, %s\t# spill",
1186 Matcher::regName[dst_first],
1187 Matcher::regName[src_first]);
1188 #endif
1189 }
1190 } else {
1191 // 32-bit
1192 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1193 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1194 if (cbuf) {
1195 MacroAssembler _masm(cbuf);
1196 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1197 #ifndef PRODUCT
1198 } else {
1199 st->print("movdl %s, %s\t# spill",
1200 Matcher::regName[dst_first],
1201 Matcher::regName[src_first]);
1202 #endif
1203 }
1204 }
1205 return 0;
1206 }
1207 } else if (src_first_rc == rc_float) {
1208 // xmm ->
1209 if (dst_first_rc == rc_stack) {
1210 // xmm -> mem
1211 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1212 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1213 // 64-bit
1214 int offset = ra_->reg2offset(dst_first);
1215 if (cbuf) {
1216 MacroAssembler _masm(cbuf);
1217 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1218 #ifndef PRODUCT
1219 } else {
1220 st->print("movsd [rsp + #%d], %s\t# spill",
1221 offset,
1222 Matcher::regName[src_first]);
1223 #endif
1224 }
1225 } else {
1226 // 32-bit
1227 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1228 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1229 int offset = ra_->reg2offset(dst_first);
1230 if (cbuf) {
1231 MacroAssembler _masm(cbuf);
1232 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1233 #ifndef PRODUCT
1234 } else {
1235 st->print("movss [rsp + #%d], %s\t# spill",
1236 offset,
1237 Matcher::regName[src_first]);
1238 #endif
1239 }
1240 }
1241 return 0;
1242 } else if (dst_first_rc == rc_int) {
1243 // xmm -> gpr
1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1246 // 64-bit
1247 if (cbuf) {
1248 MacroAssembler _masm(cbuf);
1249 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1250 #ifndef PRODUCT
1251 } else {
1252 st->print("movdq %s, %s\t# spill",
1253 Matcher::regName[dst_first],
1254 Matcher::regName[src_first]);
1255 #endif
1256 }
1257 } else {
1258 // 32-bit
1259 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1260 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1261 if (cbuf) {
1262 MacroAssembler _masm(cbuf);
1263 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1264 #ifndef PRODUCT
1265 } else {
1266 st->print("movdl %s, %s\t# spill",
1267 Matcher::regName[dst_first],
1268 Matcher::regName[src_first]);
1269 #endif
1270 }
1271 }
1272 return 0;
1273 } else if (dst_first_rc == rc_float) {
1274 // xmm -> xmm
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1277 // 64-bit
1278 if (cbuf) {
1279 MacroAssembler _masm(cbuf);
1280 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1281 #ifndef PRODUCT
1282 } else {
1283 st->print("%s %s, %s\t# spill",
1284 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1285 Matcher::regName[dst_first],
1286 Matcher::regName[src_first]);
1287 #endif
1288 }
1289 } else {
1290 // 32-bit
1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1293 if (cbuf) {
1294 MacroAssembler _masm(cbuf);
1295 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1296 #ifndef PRODUCT
1297 } else {
1298 st->print("%s %s, %s\t# spill",
1299 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1300 Matcher::regName[dst_first],
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 }
1305 return 0;
1306 }
1307 }
1308
1309 assert(0," foo ");
1310 Unimplemented();
1311 return 0;
1312 }
1313
1314 #ifndef PRODUCT
1315 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1316 implementation(NULL, ra_, false, st);
1317 }
1318 #endif
1319
1320 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1321 implementation(&cbuf, ra_, false, NULL);
1322 }
1323
1324 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1325 return MachNode::size(ra_);
1326 }
1327
1328 //=============================================================================
1329 #ifndef PRODUCT
1330 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1331 {
1332 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1333 int reg = ra_->get_reg_first(this);
1334 st->print("leaq %s, [rsp + #%d]\t# box lock",
1335 Matcher::regName[reg], offset);
1336 }
1337 #endif
1338
1339 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1340 {
1341 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1342 int reg = ra_->get_encode(this);
1343 if (offset >= 0x80) {
1344 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1345 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1346 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1347 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1348 emit_d32(cbuf, offset);
1349 } else {
1350 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1351 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1352 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1353 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1354 emit_d8(cbuf, offset);
1355 }
1356 }
1357
1358 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1359 {
1360 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1361 return (offset < 0x80) ? 5 : 8; // REX
1362 }
1363
1364 //=============================================================================
1365
1366 // emit call stub, compiled java to interpreter
1367 void emit_java_to_interp(CodeBuffer& cbuf)
1368 {
1369 // Stub is fixed up when the corresponding call is converted from
1370 // calling compiled code to calling interpreted code.
1371 // movq rbx, 0
1372 // jmp -5 # to self
1373
1374 address mark = cbuf.insts_mark(); // get mark within main instrs section
1375
1376 // Note that the code buffer's insts_mark is always relative to insts.
1377 // That's why we must use the macroassembler to generate a stub.
1378 MacroAssembler _masm(&cbuf);
1379
1380 address base =
1381 __ start_a_stub(Compile::MAX_stubs_size);
1382 if (base == NULL) return; // CodeBuffer::expand failed
1383 // static stub relocation stores the instruction address of the call
1384 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1385 // static stub relocation also tags the methodOop in the code-stream.
1386 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1387 // This is recognized as unresolved by relocs/nativeinst/ic code
1388 __ jump(RuntimeAddress(__ pc()));
1389
1390 // Update current stubs pointer and restore insts_end.
1391 __ end_a_stub();
1392 }
1393
1394 // size of call stub, compiled java to interpretor
1395 uint size_java_to_interp()
1396 {
1397 return 15; // movq (1+1+8); jmp (1+4)
1398 }
1399
1400 // relocation entries for call stub, compiled java to interpretor
1401 uint reloc_java_to_interp()
1402 {
1403 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1404 }
1405
1406 //=============================================================================
1407 #ifndef PRODUCT
1408 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1409 {
1410 if (UseCompressedOops) {
1411 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1412 if (Universe::narrow_oop_shift() != 0) {
1413 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1414 }
1415 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1416 } else {
1417 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1418 "# Inline cache check");
1419 }
1420 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1421 st->print_cr("\tnop\t# nops to align entry point");
1422 }
1423 #endif
1424
1425 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1426 {
1427 MacroAssembler masm(&cbuf);
1428 uint insts_size = cbuf.insts_size();
1429 if (UseCompressedOops) {
1430 masm.load_klass(rscratch1, j_rarg0);
1431 masm.cmpptr(rax, rscratch1);
1432 } else {
1433 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1434 }
1435
1436 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1437
1438 /* WARNING these NOPs are critical so that verified entry point is properly
1439 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1440 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1441 if (OptoBreakpoint) {
1442 // Leave space for int3
1443 nops_cnt -= 1;
1444 }
1445 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1446 if (nops_cnt > 0)
1447 masm.nop(nops_cnt);
1448 }
1449
1450 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1451 {
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1455
1456
1457 //=============================================================================
1458 uint size_exception_handler()
1459 {
1460 // NativeCall instruction size is the same as NativeJump.
1461 // Note that this value is also credited (in output.cpp) to
1462 // the size of the code section.
1463 return NativeJump::instruction_size;
1464 }
1465
1466 // Emit exception handler code.
1467 int emit_exception_handler(CodeBuffer& cbuf)
1468 {
1469
1470 // Note that the code buffer's insts_mark is always relative to insts.
1471 // That's why we must use the macroassembler to generate a handler.
1472 MacroAssembler _masm(&cbuf);
1473 address base =
1474 __ start_a_stub(size_exception_handler());
1475 if (base == NULL) return 0; // CodeBuffer::expand failed
1476 int offset = __ offset();
1477 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1478 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1479 __ end_a_stub();
1480 return offset;
1481 }
1482
1483 uint size_deopt_handler()
1484 {
1485 // three 5 byte instructions
1486 return 15;
1487 }
1488
1489 // Emit deopt handler code.
1490 int emit_deopt_handler(CodeBuffer& cbuf)
1491 {
1492
1493 // Note that the code buffer's insts_mark is always relative to insts.
1494 // That's why we must use the macroassembler to generate a handler.
1495 MacroAssembler _masm(&cbuf);
1496 address base =
1497 __ start_a_stub(size_deopt_handler());
1498 if (base == NULL) return 0; // CodeBuffer::expand failed
1499 int offset = __ offset();
1500 address the_pc = (address) __ pc();
1501 Label next;
1502 // push a "the_pc" on the stack without destroying any registers
1503 // as they all may be live.
1504
1505 // push address of "next"
1506 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1507 __ bind(next);
1508 // adjust it so it matches "the_pc"
1509 __ subptr(Address(rsp, 0), __ offset() - offset);
1510 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1512 __ end_a_stub();
1513 return offset;
1514 }
1515
1516
1517 const bool Matcher::match_rule_supported(int opcode) {
1518 if (!has_match_rule(opcode))
1519 return false;
1520
1521 switch (opcode) {
1522 case Op_PopCountI:
1523 case Op_PopCountL:
1524 if (!UsePopCountInstruction)
1525 return false;
1526 break;
1527 }
1528
1529 return true; // Per default match rules are supported.
1530 }
1531
1532 int Matcher::regnum_to_fpu_offset(int regnum)
1533 {
1534 return regnum - 32; // The FP registers are in the second chunk
1535 }
1536
1537 // This is UltraSparc specific, true just means we have fast l2f conversion
1538 const bool Matcher::convL2FSupported(void) {
1539 return true;
1540 }
1541
1542 // Is this branch offset short enough that a short branch can be used?
1543 //
1544 // NOTE: If the platform does not provide any short branch variants, then
1545 // this method should return false for offset 0.
1546 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1547 // The passed offset is relative to address of the branch.
1548 // On 86 a branch displacement is calculated relative to address
1549 // of a next instruction.
1550 offset -= br_size;
1551
1552 // the short version of jmpConUCF2 contains multiple branches,
1553 // making the reach slightly less
1554 if (rule == jmpConUCF2_rule)
1555 return (-126 <= offset && offset <= 125);
1556 return (-128 <= offset && offset <= 127);
1557 }
1558
1559 const bool Matcher::isSimpleConstant64(jlong value) {
1560 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1561 //return value == (int) value; // Cf. storeImmL and immL32.
1562
1563 // Probably always true, even if a temp register is required.
1564 return true;
1565 }
1566
1567 // The ecx parameter to rep stosq for the ClearArray node is in words.
1568 const bool Matcher::init_array_count_is_in_bytes = false;
1569
1570 // Threshold size for cleararray.
1571 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1572
1573 // No additional cost for CMOVL.
1574 const int Matcher::long_cmove_cost() { return 0; }
1575
1576 // No CMOVF/CMOVD with SSE2
1577 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1578
1579 // Should the Matcher clone shifts on addressing modes, expecting them
1580 // to be subsumed into complex addressing expressions or compute them
1581 // into registers? True for Intel but false for most RISCs
1582 const bool Matcher::clone_shift_expressions = true;
1583
1584 // Do we need to mask the count passed to shift instructions or does
1585 // the cpu only look at the lower 5/6 bits anyway?
1586 const bool Matcher::need_masked_shift_count = false;
1587
1588 bool Matcher::narrow_oop_use_complex_address() {
1589 assert(UseCompressedOops, "only for compressed oops code");
1590 return (LogMinObjAlignmentInBytes <= 3);
1591 }
1592
1593 // Is it better to copy float constants, or load them directly from
1594 // memory? Intel can load a float constant from a direct address,
1595 // requiring no extra registers. Most RISCs will have to materialize
1596 // an address into a register first, so they would do better to copy
1597 // the constant from stack.
1598 const bool Matcher::rematerialize_float_constants = true; // XXX
1599
1600 // If CPU can load and store mis-aligned doubles directly then no
1601 // fixup is needed. Else we split the double into 2 integer pieces
1602 // and move it piece-by-piece. Only happens when passing doubles into
1603 // C code as the Java calling convention forces doubles to be aligned.
1604 const bool Matcher::misaligned_doubles_ok = true;
1605
1606 // No-op on amd64
1607 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1608
1609 // Advertise here if the CPU requires explicit rounding operations to
1610 // implement the UseStrictFP mode.
1611 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1612
1613 // Are floats conerted to double when stored to stack during deoptimization?
1614 // On x64 it is stored without convertion so we can use normal access.
1615 bool Matcher::float_in_double() { return false; }
1616
1617 // Do ints take an entire long register or just half?
1618 const bool Matcher::int_in_long = true;
1619
1620 // Return whether or not this register is ever used as an argument.
1621 // This function is used on startup to build the trampoline stubs in
1622 // generateOptoStub. Registers not mentioned will be killed by the VM
1623 // call in the trampoline, and arguments in those registers not be
1624 // available to the callee.
1625 bool Matcher::can_be_java_arg(int reg)
1626 {
1627 return
1628 reg == RDI_num || reg == RDI_H_num ||
1629 reg == RSI_num || reg == RSI_H_num ||
1630 reg == RDX_num || reg == RDX_H_num ||
1631 reg == RCX_num || reg == RCX_H_num ||
1632 reg == R8_num || reg == R8_H_num ||
1633 reg == R9_num || reg == R9_H_num ||
1634 reg == R12_num || reg == R12_H_num ||
1635 reg == XMM0_num || reg == XMM0b_num ||
1636 reg == XMM1_num || reg == XMM1b_num ||
1637 reg == XMM2_num || reg == XMM2b_num ||
1638 reg == XMM3_num || reg == XMM3b_num ||
1639 reg == XMM4_num || reg == XMM4b_num ||
1640 reg == XMM5_num || reg == XMM5b_num ||
1641 reg == XMM6_num || reg == XMM6b_num ||
1642 reg == XMM7_num || reg == XMM7b_num;
1643 }
1644
1645 bool Matcher::is_spillable_arg(int reg)
1646 {
1647 return can_be_java_arg(reg);
1648 }
1649
1650 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1651 // In 64 bit mode a code which use multiply when
1652 // devisor is constant is faster than hardware
1653 // DIV instruction (it uses MulHiL).
1654 return false;
1655 }
1656
1657 // Register for DIVI projection of divmodI
1658 RegMask Matcher::divI_proj_mask() {
1659 return INT_RAX_REG_mask();
1660 }
1661
1662 // Register for MODI projection of divmodI
1663 RegMask Matcher::modI_proj_mask() {
1664 return INT_RDX_REG_mask();
1665 }
1666
1667 // Register for DIVL projection of divmodL
1668 RegMask Matcher::divL_proj_mask() {
1669 return LONG_RAX_REG_mask();
1670 }
1671
1672 // Register for MODL projection of divmodL
1673 RegMask Matcher::modL_proj_mask() {
1674 return LONG_RDX_REG_mask();
1675 }
1676
1677 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1678 return PTR_RBP_REG_mask();
1679 }
1680
1681 static Address build_address(int b, int i, int s, int d) {
1682 Register index = as_Register(i);
1683 Address::ScaleFactor scale = (Address::ScaleFactor)s;
1684 if (index == rsp) {
1685 index = noreg;
1686 scale = Address::no_scale;
1687 }
1688 Address addr(as_Register(b), index, scale, d);
1689 return addr;
1690 }
1691
1692 %}
1693
1694 //----------ENCODING BLOCK-----------------------------------------------------
1695 // This block specifies the encoding classes used by the compiler to
1696 // output byte streams. Encoding classes are parameterized macros
1697 // used by Machine Instruction Nodes in order to generate the bit
1698 // encoding of the instruction. Operands specify their base encoding
1699 // interface with the interface keyword. There are currently
1700 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1701 // COND_INTER. REG_INTER causes an operand to generate a function
1702 // which returns its register number when queried. CONST_INTER causes
1703 // an operand to generate a function which returns the value of the
1704 // constant when queried. MEMORY_INTER causes an operand to generate
1705 // four functions which return the Base Register, the Index Register,
1706 // the Scale Value, and the Offset Value of the operand when queried.
1707 // COND_INTER causes an operand to generate six functions which return
1708 // the encoding code (ie - encoding bits for the instruction)
1709 // associated with each basic boolean condition for a conditional
1710 // instruction.
1711 //
1712 // Instructions specify two basic values for encoding. Again, a
1713 // function is available to check if the constant displacement is an
1714 // oop. They use the ins_encode keyword to specify their encoding
1715 // classes (which must be a sequence of enc_class names, and their
1716 // parameters, specified in the encoding block), and they use the
1717 // opcode keyword to specify, in order, their primary, secondary, and
1718 // tertiary opcode. Only the opcode sections which a particular
1719 // instruction needs for encoding need to be specified.
1720 encode %{
1721 // Build emit functions for each basic byte or larger field in the
1722 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1723 // from C++ code in the enc_class source block. Emit functions will
1724 // live in the main source block for now. In future, we can
1725 // generalize this by adding a syntax that specifies the sizes of
1726 // fields in an order, so that the adlc can build the emit functions
1727 // automagically
1728
1729 // Emit primary opcode
1730 enc_class OpcP
1731 %{
1732 emit_opcode(cbuf, $primary);
1733 %}
1734
1735 // Emit secondary opcode
1736 enc_class OpcS
1737 %{
1738 emit_opcode(cbuf, $secondary);
1739 %}
1740
1741 // Emit tertiary opcode
1742 enc_class OpcT
1743 %{
1744 emit_opcode(cbuf, $tertiary);
1745 %}
1746
1747 // Emit opcode directly
1748 enc_class Opcode(immI d8)
1749 %{
1750 emit_opcode(cbuf, $d8$$constant);
1751 %}
1752
1753 // Emit size prefix
1754 enc_class SizePrefix
1755 %{
1756 emit_opcode(cbuf, 0x66);
1757 %}
1758
1759 enc_class reg(rRegI reg)
1760 %{
1761 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1762 %}
1763
1764 enc_class reg_reg(rRegI dst, rRegI src)
1765 %{
1766 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1767 %}
1768
1769 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1770 %{
1771 emit_opcode(cbuf, $opcode$$constant);
1772 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1773 %}
1774
1775 enc_class cdql_enc(no_rax_rdx_RegI div)
1776 %{
1777 // Full implementation of Java idiv and irem; checks for
1778 // special case as described in JVM spec., p.243 & p.271.
1779 //
1780 // normal case special case
1781 //
1782 // input : rax: dividend min_int
1783 // reg: divisor -1
1784 //
1785 // output: rax: quotient (= rax idiv reg) min_int
1786 // rdx: remainder (= rax irem reg) 0
1787 //
1788 // Code sequnce:
1789 //
1790 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1791 // 5: 75 07/08 jne e <normal>
1792 // 7: 33 d2 xor %edx,%edx
1793 // [div >= 8 -> offset + 1]
1794 // [REX_B]
1795 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1796 // c: 74 03/04 je 11 <done>
1797 // 000000000000000e <normal>:
1798 // e: 99 cltd
1799 // [div >= 8 -> offset + 1]
1800 // [REX_B]
1801 // f: f7 f9 idiv $div
1802 // 0000000000000011 <done>:
1803
1804 // cmp $0x80000000,%eax
1805 emit_opcode(cbuf, 0x3d);
1806 emit_d8(cbuf, 0x00);
1807 emit_d8(cbuf, 0x00);
1808 emit_d8(cbuf, 0x00);
1809 emit_d8(cbuf, 0x80);
1810
1811 // jne e <normal>
1812 emit_opcode(cbuf, 0x75);
1813 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1814
1815 // xor %edx,%edx
1816 emit_opcode(cbuf, 0x33);
1817 emit_d8(cbuf, 0xD2);
1818
1819 // cmp $0xffffffffffffffff,%ecx
1820 if ($div$$reg >= 8) {
1821 emit_opcode(cbuf, Assembler::REX_B);
1822 }
1823 emit_opcode(cbuf, 0x83);
1824 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1825 emit_d8(cbuf, 0xFF);
1826
1827 // je 11 <done>
1828 emit_opcode(cbuf, 0x74);
1829 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1830
1831 // <normal>
1832 // cltd
1833 emit_opcode(cbuf, 0x99);
1834
1835 // idivl (note: must be emitted by the user of this rule)
1836 // <done>
1837 %}
1838
1839 enc_class cdqq_enc(no_rax_rdx_RegL div)
1840 %{
1841 // Full implementation of Java ldiv and lrem; checks for
1842 // special case as described in JVM spec., p.243 & p.271.
1843 //
1844 // normal case special case
1845 //
1846 // input : rax: dividend min_long
1847 // reg: divisor -1
1848 //
1849 // output: rax: quotient (= rax idiv reg) min_long
1850 // rdx: remainder (= rax irem reg) 0
1851 //
1852 // Code sequnce:
1853 //
1854 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1855 // 7: 00 00 80
1856 // a: 48 39 d0 cmp %rdx,%rax
1857 // d: 75 08 jne 17 <normal>
1858 // f: 33 d2 xor %edx,%edx
1859 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1860 // 15: 74 05 je 1c <done>
1861 // 0000000000000017 <normal>:
1862 // 17: 48 99 cqto
1863 // 19: 48 f7 f9 idiv $div
1864 // 000000000000001c <done>:
1865
1866 // mov $0x8000000000000000,%rdx
1867 emit_opcode(cbuf, Assembler::REX_W);
1868 emit_opcode(cbuf, 0xBA);
1869 emit_d8(cbuf, 0x00);
1870 emit_d8(cbuf, 0x00);
1871 emit_d8(cbuf, 0x00);
1872 emit_d8(cbuf, 0x00);
1873 emit_d8(cbuf, 0x00);
1874 emit_d8(cbuf, 0x00);
1875 emit_d8(cbuf, 0x00);
1876 emit_d8(cbuf, 0x80);
1877
1878 // cmp %rdx,%rax
1879 emit_opcode(cbuf, Assembler::REX_W);
1880 emit_opcode(cbuf, 0x39);
1881 emit_d8(cbuf, 0xD0);
1882
1883 // jne 17 <normal>
1884 emit_opcode(cbuf, 0x75);
1885 emit_d8(cbuf, 0x08);
1886
1887 // xor %edx,%edx
1888 emit_opcode(cbuf, 0x33);
1889 emit_d8(cbuf, 0xD2);
1890
1891 // cmp $0xffffffffffffffff,$div
1892 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1893 emit_opcode(cbuf, 0x83);
1894 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1895 emit_d8(cbuf, 0xFF);
1896
1897 // je 1e <done>
1898 emit_opcode(cbuf, 0x74);
1899 emit_d8(cbuf, 0x05);
1900
1901 // <normal>
1902 // cqto
1903 emit_opcode(cbuf, Assembler::REX_W);
1904 emit_opcode(cbuf, 0x99);
1905
1906 // idivq (note: must be emitted by the user of this rule)
1907 // <done>
1908 %}
1909
1910 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1911 enc_class OpcSE(immI imm)
1912 %{
1913 // Emit primary opcode and set sign-extend bit
1914 // Check for 8-bit immediate, and set sign extend bit in opcode
1915 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1916 emit_opcode(cbuf, $primary | 0x02);
1917 } else {
1918 // 32-bit immediate
1919 emit_opcode(cbuf, $primary);
1920 }
1921 %}
1922
1923 enc_class OpcSErm(rRegI dst, immI imm)
1924 %{
1925 // OpcSEr/m
1926 int dstenc = $dst$$reg;
1927 if (dstenc >= 8) {
1928 emit_opcode(cbuf, Assembler::REX_B);
1929 dstenc -= 8;
1930 }
1931 // Emit primary opcode and set sign-extend bit
1932 // Check for 8-bit immediate, and set sign extend bit in opcode
1933 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1934 emit_opcode(cbuf, $primary | 0x02);
1935 } else {
1936 // 32-bit immediate
1937 emit_opcode(cbuf, $primary);
1938 }
1939 // Emit r/m byte with secondary opcode, after primary opcode.
1940 emit_rm(cbuf, 0x3, $secondary, dstenc);
1941 %}
1942
1943 enc_class OpcSErm_wide(rRegL dst, immI imm)
1944 %{
1945 // OpcSEr/m
1946 int dstenc = $dst$$reg;
1947 if (dstenc < 8) {
1948 emit_opcode(cbuf, Assembler::REX_W);
1949 } else {
1950 emit_opcode(cbuf, Assembler::REX_WB);
1951 dstenc -= 8;
1952 }
1953 // Emit primary opcode and set sign-extend bit
1954 // Check for 8-bit immediate, and set sign extend bit in opcode
1955 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1956 emit_opcode(cbuf, $primary | 0x02);
1957 } else {
1958 // 32-bit immediate
1959 emit_opcode(cbuf, $primary);
1960 }
1961 // Emit r/m byte with secondary opcode, after primary opcode.
1962 emit_rm(cbuf, 0x3, $secondary, dstenc);
1963 %}
1964
1965 enc_class Con8or32(immI imm)
1966 %{
1967 // Check for 8-bit immediate, and set sign extend bit in opcode
1968 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1969 $$$emit8$imm$$constant;
1970 } else {
1971 // 32-bit immediate
1972 $$$emit32$imm$$constant;
1973 }
1974 %}
1975
1976 enc_class opc2_reg(rRegI dst)
1977 %{
1978 // BSWAP
1979 emit_cc(cbuf, $secondary, $dst$$reg);
1980 %}
1981
1982 enc_class opc3_reg(rRegI dst)
1983 %{
1984 // BSWAP
1985 emit_cc(cbuf, $tertiary, $dst$$reg);
1986 %}
1987
1988 enc_class reg_opc(rRegI div)
1989 %{
1990 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1991 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1992 %}
1993
1994 enc_class enc_cmov(cmpOp cop)
1995 %{
1996 // CMOV
1997 $$$emit8$primary;
1998 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1999 %}
2000
2001 enc_class enc_PartialSubtypeCheck()
2002 %{
2003 Register Rrdi = as_Register(RDI_enc); // result register
2004 Register Rrax = as_Register(RAX_enc); // super class
2005 Register Rrcx = as_Register(RCX_enc); // killed
2006 Register Rrsi = as_Register(RSI_enc); // sub class
2007 Label miss;
2008 const bool set_cond_codes = true;
2009
2010 MacroAssembler _masm(&cbuf);
2011 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2012 NULL, &miss,
2013 /*set_cond_codes:*/ true);
2014 if ($primary) {
2015 __ xorptr(Rrdi, Rrdi);
2016 }
2017 __ bind(miss);
2018 %}
2019
2020 enc_class Java_To_Interpreter(method meth)
2021 %{
2022 // CALL Java_To_Interpreter
2023 // This is the instruction starting address for relocation info.
2024 cbuf.set_insts_mark();
2025 $$$emit8$primary;
2026 // CALL directly to the runtime
2027 emit_d32_reloc(cbuf,
2028 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2029 runtime_call_Relocation::spec(),
2030 RELOC_DISP32);
2031 %}
2032
2033 enc_class Java_Static_Call(method meth)
2034 %{
2035 // JAVA STATIC CALL
2036 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2037 // determine who we intended to call.
2038 cbuf.set_insts_mark();
2039 $$$emit8$primary;
2040
2041 if (!_method) {
2042 emit_d32_reloc(cbuf,
2043 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2044 runtime_call_Relocation::spec(),
2045 RELOC_DISP32);
2046 } else if (_optimized_virtual) {
2047 emit_d32_reloc(cbuf,
2048 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2049 opt_virtual_call_Relocation::spec(),
2050 RELOC_DISP32);
2051 } else {
2052 emit_d32_reloc(cbuf,
2053 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2054 static_call_Relocation::spec(),
2055 RELOC_DISP32);
2056 }
2057 if (_method) {
2058 // Emit stub for static call
2059 emit_java_to_interp(cbuf);
2060 }
2061 %}
2062
2063 enc_class Java_Dynamic_Call(method meth)
2064 %{
2065 // JAVA DYNAMIC CALL
2066 // !!!!!
2067 // Generate "movq rax, -1", placeholder instruction to load oop-info
2068 // emit_call_dynamic_prologue( cbuf );
2069 cbuf.set_insts_mark();
2070
2071 // movq rax, -1
2072 emit_opcode(cbuf, Assembler::REX_W);
2073 emit_opcode(cbuf, 0xB8 | RAX_enc);
2074 emit_d64_reloc(cbuf,
2075 (int64_t) Universe::non_oop_word(),
2076 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2077 address virtual_call_oop_addr = cbuf.insts_mark();
2078 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2079 // who we intended to call.
2080 cbuf.set_insts_mark();
2081 $$$emit8$primary;
2082 emit_d32_reloc(cbuf,
2083 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2084 virtual_call_Relocation::spec(virtual_call_oop_addr),
2085 RELOC_DISP32);
2086 %}
2087
2088 enc_class Java_Compiled_Call(method meth)
2089 %{
2090 // JAVA COMPILED CALL
2091 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2092
2093 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2094 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2095
2096 // callq *disp(%rax)
2097 cbuf.set_insts_mark();
2098 $$$emit8$primary;
2099 if (disp < 0x80) {
2100 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2101 emit_d8(cbuf, disp); // Displacement
2102 } else {
2103 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2104 emit_d32(cbuf, disp); // Displacement
2105 }
2106 %}
2107
2108 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2109 %{
2110 // SAL, SAR, SHR
2111 int dstenc = $dst$$reg;
2112 if (dstenc >= 8) {
2113 emit_opcode(cbuf, Assembler::REX_B);
2114 dstenc -= 8;
2115 }
2116 $$$emit8$primary;
2117 emit_rm(cbuf, 0x3, $secondary, dstenc);
2118 $$$emit8$shift$$constant;
2119 %}
2120
2121 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2122 %{
2123 // SAL, SAR, SHR
2124 int dstenc = $dst$$reg;
2125 if (dstenc < 8) {
2126 emit_opcode(cbuf, Assembler::REX_W);
2127 } else {
2128 emit_opcode(cbuf, Assembler::REX_WB);
2129 dstenc -= 8;
2130 }
2131 $$$emit8$primary;
2132 emit_rm(cbuf, 0x3, $secondary, dstenc);
2133 $$$emit8$shift$$constant;
2134 %}
2135
2136 enc_class load_immI(rRegI dst, immI src)
2137 %{
2138 int dstenc = $dst$$reg;
2139 if (dstenc >= 8) {
2140 emit_opcode(cbuf, Assembler::REX_B);
2141 dstenc -= 8;
2142 }
2143 emit_opcode(cbuf, 0xB8 | dstenc);
2144 $$$emit32$src$$constant;
2145 %}
2146
2147 enc_class load_immL(rRegL dst, immL src)
2148 %{
2149 int dstenc = $dst$$reg;
2150 if (dstenc < 8) {
2151 emit_opcode(cbuf, Assembler::REX_W);
2152 } else {
2153 emit_opcode(cbuf, Assembler::REX_WB);
2154 dstenc -= 8;
2155 }
2156 emit_opcode(cbuf, 0xB8 | dstenc);
2157 emit_d64(cbuf, $src$$constant);
2158 %}
2159
2160 enc_class load_immUL32(rRegL dst, immUL32 src)
2161 %{
2162 // same as load_immI, but this time we care about zeroes in the high word
2163 int dstenc = $dst$$reg;
2164 if (dstenc >= 8) {
2165 emit_opcode(cbuf, Assembler::REX_B);
2166 dstenc -= 8;
2167 }
2168 emit_opcode(cbuf, 0xB8 | dstenc);
2169 $$$emit32$src$$constant;
2170 %}
2171
2172 enc_class load_immL32(rRegL dst, immL32 src)
2173 %{
2174 int dstenc = $dst$$reg;
2175 if (dstenc < 8) {
2176 emit_opcode(cbuf, Assembler::REX_W);
2177 } else {
2178 emit_opcode(cbuf, Assembler::REX_WB);
2179 dstenc -= 8;
2180 }
2181 emit_opcode(cbuf, 0xC7);
2182 emit_rm(cbuf, 0x03, 0x00, dstenc);
2183 $$$emit32$src$$constant;
2184 %}
2185
2186 enc_class load_immP31(rRegP dst, immP32 src)
2187 %{
2188 // same as load_immI, but this time we care about zeroes in the high word
2189 int dstenc = $dst$$reg;
2190 if (dstenc >= 8) {
2191 emit_opcode(cbuf, Assembler::REX_B);
2192 dstenc -= 8;
2193 }
2194 emit_opcode(cbuf, 0xB8 | dstenc);
2195 $$$emit32$src$$constant;
2196 %}
2197
2198 enc_class load_immP(rRegP dst, immP src)
2199 %{
2200 int dstenc = $dst$$reg;
2201 if (dstenc < 8) {
2202 emit_opcode(cbuf, Assembler::REX_W);
2203 } else {
2204 emit_opcode(cbuf, Assembler::REX_WB);
2205 dstenc -= 8;
2206 }
2207 emit_opcode(cbuf, 0xB8 | dstenc);
2208 // This next line should be generated from ADLC
2209 if ($src->constant_is_oop()) {
2210 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2211 } else {
2212 emit_d64(cbuf, $src$$constant);
2213 }
2214 %}
2215
2216 enc_class Con32(immI src)
2217 %{
2218 // Output immediate
2219 $$$emit32$src$$constant;
2220 %}
2221
2222 enc_class Con64(immL src)
2223 %{
2224 // Output immediate
2225 emit_d64($src$$constant);
2226 %}
2227
2228 enc_class Con32F_as_bits(immF src)
2229 %{
2230 // Output Float immediate bits
2231 jfloat jf = $src$$constant;
2232 jint jf_as_bits = jint_cast(jf);
2233 emit_d32(cbuf, jf_as_bits);
2234 %}
2235
2236 enc_class Con16(immI src)
2237 %{
2238 // Output immediate
2239 $$$emit16$src$$constant;
2240 %}
2241
2242 // How is this different from Con32??? XXX
2243 enc_class Con_d32(immI src)
2244 %{
2245 emit_d32(cbuf,$src$$constant);
2246 %}
2247
2248 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2249 // Output immediate memory reference
2250 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2251 emit_d32(cbuf, 0x00);
2252 %}
2253
2254 enc_class lock_prefix()
2255 %{
2256 if (os::is_MP()) {
2257 emit_opcode(cbuf, 0xF0); // lock
2258 }
2259 %}
2260
2261 enc_class REX_mem(memory mem)
2262 %{
2263 if ($mem$$base >= 8) {
2264 if ($mem$$index < 8) {
2265 emit_opcode(cbuf, Assembler::REX_B);
2266 } else {
2267 emit_opcode(cbuf, Assembler::REX_XB);
2268 }
2269 } else {
2270 if ($mem$$index >= 8) {
2271 emit_opcode(cbuf, Assembler::REX_X);
2272 }
2273 }
2274 %}
2275
2276 enc_class REX_mem_wide(memory mem)
2277 %{
2278 if ($mem$$base >= 8) {
2279 if ($mem$$index < 8) {
2280 emit_opcode(cbuf, Assembler::REX_WB);
2281 } else {
2282 emit_opcode(cbuf, Assembler::REX_WXB);
2283 }
2284 } else {
2285 if ($mem$$index < 8) {
2286 emit_opcode(cbuf, Assembler::REX_W);
2287 } else {
2288 emit_opcode(cbuf, Assembler::REX_WX);
2289 }
2290 }
2291 %}
2292
2293 // for byte regs
2294 enc_class REX_breg(rRegI reg)
2295 %{
2296 if ($reg$$reg >= 4) {
2297 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2298 }
2299 %}
2300
2301 // for byte regs
2302 enc_class REX_reg_breg(rRegI dst, rRegI src)
2303 %{
2304 if ($dst$$reg < 8) {
2305 if ($src$$reg >= 4) {
2306 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2307 }
2308 } else {
2309 if ($src$$reg < 8) {
2310 emit_opcode(cbuf, Assembler::REX_R);
2311 } else {
2312 emit_opcode(cbuf, Assembler::REX_RB);
2313 }
2314 }
2315 %}
2316
2317 // for byte regs
2318 enc_class REX_breg_mem(rRegI reg, memory mem)
2319 %{
2320 if ($reg$$reg < 8) {
2321 if ($mem$$base < 8) {
2322 if ($mem$$index >= 8) {
2323 emit_opcode(cbuf, Assembler::REX_X);
2324 } else if ($reg$$reg >= 4) {
2325 emit_opcode(cbuf, Assembler::REX);
2326 }
2327 } else {
2328 if ($mem$$index < 8) {
2329 emit_opcode(cbuf, Assembler::REX_B);
2330 } else {
2331 emit_opcode(cbuf, Assembler::REX_XB);
2332 }
2333 }
2334 } else {
2335 if ($mem$$base < 8) {
2336 if ($mem$$index < 8) {
2337 emit_opcode(cbuf, Assembler::REX_R);
2338 } else {
2339 emit_opcode(cbuf, Assembler::REX_RX);
2340 }
2341 } else {
2342 if ($mem$$index < 8) {
2343 emit_opcode(cbuf, Assembler::REX_RB);
2344 } else {
2345 emit_opcode(cbuf, Assembler::REX_RXB);
2346 }
2347 }
2348 }
2349 %}
2350
2351 enc_class REX_reg(rRegI reg)
2352 %{
2353 if ($reg$$reg >= 8) {
2354 emit_opcode(cbuf, Assembler::REX_B);
2355 }
2356 %}
2357
2358 enc_class REX_reg_wide(rRegI reg)
2359 %{
2360 if ($reg$$reg < 8) {
2361 emit_opcode(cbuf, Assembler::REX_W);
2362 } else {
2363 emit_opcode(cbuf, Assembler::REX_WB);
2364 }
2365 %}
2366
2367 enc_class REX_reg_reg(rRegI dst, rRegI src)
2368 %{
2369 if ($dst$$reg < 8) {
2370 if ($src$$reg >= 8) {
2371 emit_opcode(cbuf, Assembler::REX_B);
2372 }
2373 } else {
2374 if ($src$$reg < 8) {
2375 emit_opcode(cbuf, Assembler::REX_R);
2376 } else {
2377 emit_opcode(cbuf, Assembler::REX_RB);
2378 }
2379 }
2380 %}
2381
2382 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2383 %{
2384 if ($dst$$reg < 8) {
2385 if ($src$$reg < 8) {
2386 emit_opcode(cbuf, Assembler::REX_W);
2387 } else {
2388 emit_opcode(cbuf, Assembler::REX_WB);
2389 }
2390 } else {
2391 if ($src$$reg < 8) {
2392 emit_opcode(cbuf, Assembler::REX_WR);
2393 } else {
2394 emit_opcode(cbuf, Assembler::REX_WRB);
2395 }
2396 }
2397 %}
2398
2399 enc_class REX_reg_mem(rRegI reg, memory mem)
2400 %{
2401 if ($reg$$reg < 8) {
2402 if ($mem$$base < 8) {
2403 if ($mem$$index >= 8) {
2404 emit_opcode(cbuf, Assembler::REX_X);
2405 }
2406 } else {
2407 if ($mem$$index < 8) {
2408 emit_opcode(cbuf, Assembler::REX_B);
2409 } else {
2410 emit_opcode(cbuf, Assembler::REX_XB);
2411 }
2412 }
2413 } else {
2414 if ($mem$$base < 8) {
2415 if ($mem$$index < 8) {
2416 emit_opcode(cbuf, Assembler::REX_R);
2417 } else {
2418 emit_opcode(cbuf, Assembler::REX_RX);
2419 }
2420 } else {
2421 if ($mem$$index < 8) {
2422 emit_opcode(cbuf, Assembler::REX_RB);
2423 } else {
2424 emit_opcode(cbuf, Assembler::REX_RXB);
2425 }
2426 }
2427 }
2428 %}
2429
2430 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2431 %{
2432 if ($reg$$reg < 8) {
2433 if ($mem$$base < 8) {
2434 if ($mem$$index < 8) {
2435 emit_opcode(cbuf, Assembler::REX_W);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_WX);
2438 }
2439 } else {
2440 if ($mem$$index < 8) {
2441 emit_opcode(cbuf, Assembler::REX_WB);
2442 } else {
2443 emit_opcode(cbuf, Assembler::REX_WXB);
2444 }
2445 }
2446 } else {
2447 if ($mem$$base < 8) {
2448 if ($mem$$index < 8) {
2449 emit_opcode(cbuf, Assembler::REX_WR);
2450 } else {
2451 emit_opcode(cbuf, Assembler::REX_WRX);
2452 }
2453 } else {
2454 if ($mem$$index < 8) {
2455 emit_opcode(cbuf, Assembler::REX_WRB);
2456 } else {
2457 emit_opcode(cbuf, Assembler::REX_WRXB);
2458 }
2459 }
2460 }
2461 %}
2462
2463 enc_class reg_mem(rRegI ereg, memory mem)
2464 %{
2465 // High registers handle in encode_RegMem
2466 int reg = $ereg$$reg;
2467 int base = $mem$$base;
2468 int index = $mem$$index;
2469 int scale = $mem$$scale;
2470 int disp = $mem$$disp;
2471 bool disp_is_oop = $mem->disp_is_oop();
2472
2473 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
2474 %}
2475
2476 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2477 %{
2478 int rm_byte_opcode = $rm_opcode$$constant;
2479
2480 // High registers handle in encode_RegMem
2481 int base = $mem$$base;
2482 int index = $mem$$index;
2483 int scale = $mem$$scale;
2484 int displace = $mem$$disp;
2485
2486 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
2487 // working with static
2488 // globals
2489 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2490 disp_is_oop);
2491 %}
2492
2493 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2494 %{
2495 int reg_encoding = $dst$$reg;
2496 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2497 int index = 0x04; // 0x04 indicates no index
2498 int scale = 0x00; // 0x00 indicates no scale
2499 int displace = $src1$$constant; // 0x00 indicates no displacement
2500 bool disp_is_oop = false;
2501 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2502 disp_is_oop);
2503 %}
2504
2505 enc_class neg_reg(rRegI dst)
2506 %{
2507 int dstenc = $dst$$reg;
2508 if (dstenc >= 8) {
2509 emit_opcode(cbuf, Assembler::REX_B);
2510 dstenc -= 8;
2511 }
2512 // NEG $dst
2513 emit_opcode(cbuf, 0xF7);
2514 emit_rm(cbuf, 0x3, 0x03, dstenc);
2515 %}
2516
2517 enc_class neg_reg_wide(rRegI dst)
2518 %{
2519 int dstenc = $dst$$reg;
2520 if (dstenc < 8) {
2521 emit_opcode(cbuf, Assembler::REX_W);
2522 } else {
2523 emit_opcode(cbuf, Assembler::REX_WB);
2524 dstenc -= 8;
2525 }
2526 // NEG $dst
2527 emit_opcode(cbuf, 0xF7);
2528 emit_rm(cbuf, 0x3, 0x03, dstenc);
2529 %}
2530
2531 enc_class setLT_reg(rRegI dst)
2532 %{
2533 int dstenc = $dst$$reg;
2534 if (dstenc >= 8) {
2535 emit_opcode(cbuf, Assembler::REX_B);
2536 dstenc -= 8;
2537 } else if (dstenc >= 4) {
2538 emit_opcode(cbuf, Assembler::REX);
2539 }
2540 // SETLT $dst
2541 emit_opcode(cbuf, 0x0F);
2542 emit_opcode(cbuf, 0x9C);
2543 emit_rm(cbuf, 0x3, 0x0, dstenc);
2544 %}
2545
2546 enc_class setNZ_reg(rRegI dst)
2547 %{
2548 int dstenc = $dst$$reg;
2549 if (dstenc >= 8) {
2550 emit_opcode(cbuf, Assembler::REX_B);
2551 dstenc -= 8;
2552 } else if (dstenc >= 4) {
2553 emit_opcode(cbuf, Assembler::REX);
2554 }
2555 // SETNZ $dst
2556 emit_opcode(cbuf, 0x0F);
2557 emit_opcode(cbuf, 0x95);
2558 emit_rm(cbuf, 0x3, 0x0, dstenc);
2559 %}
2560
2561
2562 // Compare the lonogs and set -1, 0, or 1 into dst
2563 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2564 %{
2565 int src1enc = $src1$$reg;
2566 int src2enc = $src2$$reg;
2567 int dstenc = $dst$$reg;
2568
2569 // cmpq $src1, $src2
2570 if (src1enc < 8) {
2571 if (src2enc < 8) {
2572 emit_opcode(cbuf, Assembler::REX_W);
2573 } else {
2574 emit_opcode(cbuf, Assembler::REX_WB);
2575 }
2576 } else {
2577 if (src2enc < 8) {
2578 emit_opcode(cbuf, Assembler::REX_WR);
2579 } else {
2580 emit_opcode(cbuf, Assembler::REX_WRB);
2581 }
2582 }
2583 emit_opcode(cbuf, 0x3B);
2584 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2585
2586 // movl $dst, -1
2587 if (dstenc >= 8) {
2588 emit_opcode(cbuf, Assembler::REX_B);
2589 }
2590 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2591 emit_d32(cbuf, -1);
2592
2593 // jl,s done
2594 emit_opcode(cbuf, 0x7C);
2595 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2596
2597 // setne $dst
2598 if (dstenc >= 4) {
2599 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2600 }
2601 emit_opcode(cbuf, 0x0F);
2602 emit_opcode(cbuf, 0x95);
2603 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2604
2605 // movzbl $dst, $dst
2606 if (dstenc >= 4) {
2607 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2608 }
2609 emit_opcode(cbuf, 0x0F);
2610 emit_opcode(cbuf, 0xB6);
2611 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2612 %}
2613
2614 enc_class Push_ResultXD(regD dst) %{
2615 MacroAssembler _masm(&cbuf);
2616 __ fstp_d(Address(rsp, 0));
2617 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2618 __ addptr(rsp, 8);
2619 %}
2620
2621 enc_class Push_SrcXD(regD src) %{
2622 MacroAssembler _masm(&cbuf);
2623 __ subptr(rsp, 8);
2624 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2625 __ fld_d(Address(rsp, 0));
2626 %}
2627
2628
2629 // obj: object to lock
2630 // box: box address (header location) -- killed
2631 // tmp: rax -- killed
2632 // scr: rbx -- killed
2633 //
2634 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2635 // from i486.ad. See that file for comments.
2636 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2637 // use the shorter encoding. (Movl clears the high-order 32-bits).
2638
2639
2640 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2641 %{
2642 Register objReg = as_Register((int)$obj$$reg);
2643 Register boxReg = as_Register((int)$box$$reg);
2644 Register tmpReg = as_Register($tmp$$reg);
2645 Register scrReg = as_Register($scr$$reg);
2646 MacroAssembler masm(&cbuf);
2647
2648 // Verify uniqueness of register assignments -- necessary but not sufficient
2649 assert (objReg != boxReg && objReg != tmpReg &&
2650 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2651
2652 if (_counters != NULL) {
2653 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2654 }
2655 if (EmitSync & 1) {
2656 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2657 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2658 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2659 } else
2660 if (EmitSync & 2) {
2661 Label DONE_LABEL;
2662 if (UseBiasedLocking) {
2663 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2664 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2665 }
2666 // QQQ was movl...
2667 masm.movptr(tmpReg, 0x1);
2668 masm.orptr(tmpReg, Address(objReg, 0));
2669 masm.movptr(Address(boxReg, 0), tmpReg);
2670 if (os::is_MP()) {
2671 masm.lock();
2672 }
2673 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2674 masm.jcc(Assembler::equal, DONE_LABEL);
2675
2676 // Recursive locking
2677 masm.subptr(tmpReg, rsp);
2678 masm.andptr(tmpReg, 7 - os::vm_page_size());
2679 masm.movptr(Address(boxReg, 0), tmpReg);
2680
2681 masm.bind(DONE_LABEL);
2682 masm.nop(); // avoid branch to branch
2683 } else {
2684 Label DONE_LABEL, IsInflated, Egress;
2685
2686 masm.movptr(tmpReg, Address(objReg, 0)) ;
2687 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2688 masm.jcc (Assembler::notZero, IsInflated) ;
2689
2690 // it's stack-locked, biased or neutral
2691 // TODO: optimize markword triage order to reduce the number of
2692 // conditional branches in the most common cases.
2693 // Beware -- there's a subtle invariant that fetch of the markword
2694 // at [FETCH], below, will never observe a biased encoding (*101b).
2695 // If this invariant is not held we'll suffer exclusion (safety) failure.
2696
2697 if (UseBiasedLocking && !UseOptoBiasInlining) {
2698 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
2699 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
2700 }
2701
2702 // was q will it destroy high?
2703 masm.orl (tmpReg, 1) ;
2704 masm.movptr(Address(boxReg, 0), tmpReg) ;
2705 if (os::is_MP()) { masm.lock(); }
2706 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2707 if (_counters != NULL) {
2708 masm.cond_inc32(Assembler::equal,
2709 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2710 }
2711 masm.jcc (Assembler::equal, DONE_LABEL);
2712
2713 // Recursive locking
2714 masm.subptr(tmpReg, rsp);
2715 masm.andptr(tmpReg, 7 - os::vm_page_size());
2716 masm.movptr(Address(boxReg, 0), tmpReg);
2717 if (_counters != NULL) {
2718 masm.cond_inc32(Assembler::equal,
2719 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2720 }
2721 masm.jmp (DONE_LABEL) ;
2722
2723 masm.bind (IsInflated) ;
2724 // It's inflated
2725
2726 // TODO: someday avoid the ST-before-CAS penalty by
2727 // relocating (deferring) the following ST.
2728 // We should also think about trying a CAS without having
2729 // fetched _owner. If the CAS is successful we may
2730 // avoid an RTO->RTS upgrade on the $line.
2731 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2732 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2733
2734 masm.mov (boxReg, tmpReg) ;
2735 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2736 masm.testptr(tmpReg, tmpReg) ;
2737 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2738
2739 // It's inflated and appears unlocked
2740 if (os::is_MP()) { masm.lock(); }
2741 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2742 // Intentional fall-through into DONE_LABEL ...
2743
2744 masm.bind (DONE_LABEL) ;
2745 masm.nop () ; // avoid jmp to jmp
2746 }
2747 %}
2748
2749 // obj: object to unlock
2750 // box: box address (displaced header location), killed
2751 // RBX: killed tmp; cannot be obj nor box
2752 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
2753 %{
2754
2755 Register objReg = as_Register($obj$$reg);
2756 Register boxReg = as_Register($box$$reg);
2757 Register tmpReg = as_Register($tmp$$reg);
2758 MacroAssembler masm(&cbuf);
2759
2760 if (EmitSync & 4) {
2761 masm.cmpptr(rsp, 0) ;
2762 } else
2763 if (EmitSync & 8) {
2764 Label DONE_LABEL;
2765 if (UseBiasedLocking) {
2766 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2767 }
2768
2769 // Check whether the displaced header is 0
2770 //(=> recursive unlock)
2771 masm.movptr(tmpReg, Address(boxReg, 0));
2772 masm.testptr(tmpReg, tmpReg);
2773 masm.jcc(Assembler::zero, DONE_LABEL);
2774
2775 // If not recursive lock, reset the header to displaced header
2776 if (os::is_MP()) {
2777 masm.lock();
2778 }
2779 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2780 masm.bind(DONE_LABEL);
2781 masm.nop(); // avoid branch to branch
2782 } else {
2783 Label DONE_LABEL, Stacked, CheckSucc ;
2784
2785 if (UseBiasedLocking && !UseOptoBiasInlining) {
2786 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2787 }
2788
2789 masm.movptr(tmpReg, Address(objReg, 0)) ;
2790 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
2791 masm.jcc (Assembler::zero, DONE_LABEL) ;
2792 masm.testl (tmpReg, 0x02) ;
2793 masm.jcc (Assembler::zero, Stacked) ;
2794
2795 // It's inflated
2796 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2797 masm.xorptr(boxReg, r15_thread) ;
2798 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
2799 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2800 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
2801 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
2802 masm.jcc (Assembler::notZero, CheckSucc) ;
2803 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2804 masm.jmp (DONE_LABEL) ;
2805
2806 if ((EmitSync & 65536) == 0) {
2807 Label LSuccess, LGoSlowPath ;
2808 masm.bind (CheckSucc) ;
2809 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2810 masm.jcc (Assembler::zero, LGoSlowPath) ;
2811
2812 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2813 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2814 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2815 // are all faster when the write buffer is populated.
2816 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2817 if (os::is_MP()) {
2818 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
2819 }
2820 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2821 masm.jcc (Assembler::notZero, LSuccess) ;
2822
2823 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
2824 if (os::is_MP()) { masm.lock(); }
2825 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2826 masm.jcc (Assembler::notEqual, LSuccess) ;
2827 // Intentional fall-through into slow-path
2828
2829 masm.bind (LGoSlowPath) ;
2830 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
2831 masm.jmp (DONE_LABEL) ;
2832
2833 masm.bind (LSuccess) ;
2834 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
2835 masm.jmp (DONE_LABEL) ;
2836 }
2837
2838 masm.bind (Stacked) ;
2839 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2840 if (os::is_MP()) { masm.lock(); }
2841 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2842
2843 if (EmitSync & 65536) {
2844 masm.bind (CheckSucc) ;
2845 }
2846 masm.bind(DONE_LABEL);
2847 if (EmitSync & 32768) {
2848 masm.nop(); // avoid branch to branch
2849 }
2850 }
2851 %}
2852
2853
2854 enc_class enc_rethrow()
2855 %{
2856 cbuf.set_insts_mark();
2857 emit_opcode(cbuf, 0xE9); // jmp entry
2858 emit_d32_reloc(cbuf,
2859 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2860 runtime_call_Relocation::spec(),
2861 RELOC_DISP32);
2862 %}
2863
2864 %}
2865
2866
2867
2868 //----------FRAME--------------------------------------------------------------
2869 // Definition of frame structure and management information.
2870 //
2871 // S T A C K L A Y O U T Allocators stack-slot number
2872 // | (to get allocators register number
2873 // G Owned by | | v add OptoReg::stack0())
2874 // r CALLER | |
2875 // o | +--------+ pad to even-align allocators stack-slot
2876 // w V | pad0 | numbers; owned by CALLER
2877 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2878 // h ^ | in | 5
2879 // | | args | 4 Holes in incoming args owned by SELF
2880 // | | | | 3
2881 // | | +--------+
2882 // V | | old out| Empty on Intel, window on Sparc
2883 // | old |preserve| Must be even aligned.
2884 // | SP-+--------+----> Matcher::_old_SP, even aligned
2885 // | | in | 3 area for Intel ret address
2886 // Owned by |preserve| Empty on Sparc.
2887 // SELF +--------+
2888 // | | pad2 | 2 pad to align old SP
2889 // | +--------+ 1
2890 // | | locks | 0
2891 // | +--------+----> OptoReg::stack0(), even aligned
2892 // | | pad1 | 11 pad to align new SP
2893 // | +--------+
2894 // | | | 10
2895 // | | spills | 9 spills
2896 // V | | 8 (pad0 slot for callee)
2897 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2898 // ^ | out | 7
2899 // | | args | 6 Holes in outgoing args owned by CALLEE
2900 // Owned by +--------+
2901 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2902 // | new |preserve| Must be even-aligned.
2903 // | SP-+--------+----> Matcher::_new_SP, even aligned
2904 // | | |
2905 //
2906 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2907 // known from SELF's arguments and the Java calling convention.
2908 // Region 6-7 is determined per call site.
2909 // Note 2: If the calling convention leaves holes in the incoming argument
2910 // area, those holes are owned by SELF. Holes in the outgoing area
2911 // are owned by the CALLEE. Holes should not be nessecary in the
2912 // incoming area, as the Java calling convention is completely under
2913 // the control of the AD file. Doubles can be sorted and packed to
2914 // avoid holes. Holes in the outgoing arguments may be nessecary for
2915 // varargs C calling conventions.
2916 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2917 // even aligned with pad0 as needed.
2918 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2919 // region 6-11 is even aligned; it may be padded out more so that
2920 // the region from SP to FP meets the minimum stack alignment.
2921 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2922 // alignment. Region 11, pad1, may be dynamically extended so that
2923 // SP meets the minimum alignment.
2924
2925 frame
2926 %{
2927 // What direction does stack grow in (assumed to be same for C & Java)
2928 stack_direction(TOWARDS_LOW);
2929
2930 // These three registers define part of the calling convention
2931 // between compiled code and the interpreter.
2932 inline_cache_reg(RAX); // Inline Cache Register
2933 interpreter_method_oop_reg(RBX); // Method Oop Register when
2934 // calling interpreter
2935
2936 // Optional: name the operand used by cisc-spilling to access
2937 // [stack_pointer + offset]
2938 cisc_spilling_operand_name(indOffset32);
2939
2940 // Number of stack slots consumed by locking an object
2941 sync_stack_slots(2);
2942
2943 // Compiled code's Frame Pointer
2944 frame_pointer(RSP);
2945
2946 // Interpreter stores its frame pointer in a register which is
2947 // stored to the stack by I2CAdaptors.
2948 // I2CAdaptors convert from interpreted java to compiled java.
2949 interpreter_frame_pointer(RBP);
2950
2951 // Stack alignment requirement
2952 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2953
2954 // Number of stack slots between incoming argument block and the start of
2955 // a new frame. The PROLOG must add this many slots to the stack. The
2956 // EPILOG must remove this many slots. amd64 needs two slots for
2957 // return address.
2958 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2959
2960 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2961 // for calls to C. Supports the var-args backing area for register parms.
2962 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2963
2964 // The after-PROLOG location of the return address. Location of
2965 // return address specifies a type (REG or STACK) and a number
2966 // representing the register number (i.e. - use a register name) or
2967 // stack slot.
2968 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2969 // Otherwise, it is above the locks and verification slot and alignment word
2970 return_addr(STACK - 2 +
2971 round_to((Compile::current()->in_preserve_stack_slots() +
2972 Compile::current()->fixed_slots()),
2973 stack_alignment_in_slots()));
2974
2975 // Body of function which returns an integer array locating
2976 // arguments either in registers or in stack slots. Passed an array
2977 // of ideal registers called "sig" and a "length" count. Stack-slot
2978 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2979 // arguments for a CALLEE. Incoming stack arguments are
2980 // automatically biased by the preserve_stack_slots field above.
2981
2982 calling_convention
2983 %{
2984 // No difference between ingoing/outgoing just pass false
2985 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2986 %}
2987
2988 c_calling_convention
2989 %{
2990 // This is obviously always outgoing
2991 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
2992 %}
2993
2994 // Location of compiled Java return values. Same as C for now.
2995 return_value
2996 %{
2997 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2998 "only return normal values");
2999
3000 static const int lo[Op_RegL + 1] = {
3001 0,
3002 0,
3003 RAX_num, // Op_RegN
3004 RAX_num, // Op_RegI
3005 RAX_num, // Op_RegP
3006 XMM0_num, // Op_RegF
3007 XMM0_num, // Op_RegD
3008 RAX_num // Op_RegL
3009 };
3010 static const int hi[Op_RegL + 1] = {
3011 0,
3012 0,
3013 OptoReg::Bad, // Op_RegN
3014 OptoReg::Bad, // Op_RegI
3015 RAX_H_num, // Op_RegP
3016 OptoReg::Bad, // Op_RegF
3017 XMM0b_num, // Op_RegD
3018 RAX_H_num // Op_RegL
3019 };
3020 // Excluded flags and vector registers.
3021 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
3022 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3023 %}
3024 %}
3025
3026 //----------ATTRIBUTES---------------------------------------------------------
3027 //----------Operand Attributes-------------------------------------------------
3028 op_attrib op_cost(0); // Required cost attribute
3029
3030 //----------Instruction Attributes---------------------------------------------
3031 ins_attrib ins_cost(100); // Required cost attribute
3032 ins_attrib ins_size(8); // Required size attribute (in bits)
3033 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3034 // a non-matching short branch variant
3035 // of some long branch?
3036 ins_attrib ins_alignment(1); // Required alignment attribute (must
3037 // be a power of 2) specifies the
3038 // alignment that some part of the
3039 // instruction (not necessarily the
3040 // start) requires. If > 1, a
3041 // compute_padding() function must be
3042 // provided for the instruction
3043
3044 //----------OPERANDS-----------------------------------------------------------
3045 // Operand definitions must precede instruction definitions for correct parsing
3046 // in the ADLC because operands constitute user defined types which are used in
3047 // instruction definitions.
3048
3049 //----------Simple Operands----------------------------------------------------
3050 // Immediate Operands
3051 // Integer Immediate
3052 operand immI()
3053 %{
3054 match(ConI);
3055
3056 op_cost(10);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061 // Constant for test vs zero
3062 operand immI0()
3063 %{
3064 predicate(n->get_int() == 0);
3065 match(ConI);
3066
3067 op_cost(0);
3068 format %{ %}
3069 interface(CONST_INTER);
3070 %}
3071
3072 // Constant for increment
3073 operand immI1()
3074 %{
3075 predicate(n->get_int() == 1);
3076 match(ConI);
3077
3078 op_cost(0);
3079 format %{ %}
3080 interface(CONST_INTER);
3081 %}
3082
3083 // Constant for decrement
3084 operand immI_M1()
3085 %{
3086 predicate(n->get_int() == -1);
3087 match(ConI);
3088
3089 op_cost(0);
3090 format %{ %}
3091 interface(CONST_INTER);
3092 %}
3093
3094 // Valid scale values for addressing modes
3095 operand immI2()
3096 %{
3097 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3098 match(ConI);
3099
3100 format %{ %}
3101 interface(CONST_INTER);
3102 %}
3103
3104 operand immI8()
3105 %{
3106 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3107 match(ConI);
3108
3109 op_cost(5);
3110 format %{ %}
3111 interface(CONST_INTER);
3112 %}
3113
3114 operand immI16()
3115 %{
3116 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3117 match(ConI);
3118
3119 op_cost(10);
3120 format %{ %}
3121 interface(CONST_INTER);
3122 %}
3123
3124 // Constant for long shifts
3125 operand immI_32()
3126 %{
3127 predicate( n->get_int() == 32 );
3128 match(ConI);
3129
3130 op_cost(0);
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Constant for long shifts
3136 operand immI_64()
3137 %{
3138 predicate( n->get_int() == 64 );
3139 match(ConI);
3140
3141 op_cost(0);
3142 format %{ %}
3143 interface(CONST_INTER);
3144 %}
3145
3146 // Pointer Immediate
3147 operand immP()
3148 %{
3149 match(ConP);
3150
3151 op_cost(10);
3152 format %{ %}
3153 interface(CONST_INTER);
3154 %}
3155
3156 // NULL Pointer Immediate
3157 operand immP0()
3158 %{
3159 predicate(n->get_ptr() == 0);
3160 match(ConP);
3161
3162 op_cost(5);
3163 format %{ %}
3164 interface(CONST_INTER);
3165 %}
3166
3167 // Pointer Immediate
3168 operand immN() %{
3169 match(ConN);
3170
3171 op_cost(10);
3172 format %{ %}
3173 interface(CONST_INTER);
3174 %}
3175
3176 // NULL Pointer Immediate
3177 operand immN0() %{
3178 predicate(n->get_narrowcon() == 0);
3179 match(ConN);
3180
3181 op_cost(5);
3182 format %{ %}
3183 interface(CONST_INTER);
3184 %}
3185
3186 operand immP31()
3187 %{
3188 predicate(!n->as_Type()->type()->isa_oopptr()
3189 && (n->get_ptr() >> 31) == 0);
3190 match(ConP);
3191
3192 op_cost(5);
3193 format %{ %}
3194 interface(CONST_INTER);
3195 %}
3196
3197
3198 // Long Immediate
3199 operand immL()
3200 %{
3201 match(ConL);
3202
3203 op_cost(20);
3204 format %{ %}
3205 interface(CONST_INTER);
3206 %}
3207
3208 // Long Immediate 8-bit
3209 operand immL8()
3210 %{
3211 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3212 match(ConL);
3213
3214 op_cost(5);
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Long Immediate 32-bit unsigned
3220 operand immUL32()
3221 %{
3222 predicate(n->get_long() == (unsigned int) (n->get_long()));
3223 match(ConL);
3224
3225 op_cost(10);
3226 format %{ %}
3227 interface(CONST_INTER);
3228 %}
3229
3230 // Long Immediate 32-bit signed
3231 operand immL32()
3232 %{
3233 predicate(n->get_long() == (int) (n->get_long()));
3234 match(ConL);
3235
3236 op_cost(15);
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Long Immediate zero
3242 operand immL0()
3243 %{
3244 predicate(n->get_long() == 0L);
3245 match(ConL);
3246
3247 op_cost(10);
3248 format %{ %}
3249 interface(CONST_INTER);
3250 %}
3251
3252 // Constant for increment
3253 operand immL1()
3254 %{
3255 predicate(n->get_long() == 1);
3256 match(ConL);
3257
3258 format %{ %}
3259 interface(CONST_INTER);
3260 %}
3261
3262 // Constant for decrement
3263 operand immL_M1()
3264 %{
3265 predicate(n->get_long() == -1);
3266 match(ConL);
3267
3268 format %{ %}
3269 interface(CONST_INTER);
3270 %}
3271
3272 // Long Immediate: the value 10
3273 operand immL10()
3274 %{
3275 predicate(n->get_long() == 10);
3276 match(ConL);
3277
3278 format %{ %}
3279 interface(CONST_INTER);
3280 %}
3281
3282 // Long immediate from 0 to 127.
3283 // Used for a shorter form of long mul by 10.
3284 operand immL_127()
3285 %{
3286 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3287 match(ConL);
3288
3289 op_cost(10);
3290 format %{ %}
3291 interface(CONST_INTER);
3292 %}
3293
3294 // Long Immediate: low 32-bit mask
3295 operand immL_32bits()
3296 %{
3297 predicate(n->get_long() == 0xFFFFFFFFL);
3298 match(ConL);
3299 op_cost(20);
3300
3301 format %{ %}
3302 interface(CONST_INTER);
3303 %}
3304
3305 // Float Immediate zero
3306 operand immF0()
3307 %{
3308 predicate(jint_cast(n->getf()) == 0);
3309 match(ConF);
3310
3311 op_cost(5);
3312 format %{ %}
3313 interface(CONST_INTER);
3314 %}
3315
3316 // Float Immediate
3317 operand immF()
3318 %{
3319 match(ConF);
3320
3321 op_cost(15);
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3325
3326 // Double Immediate zero
3327 operand immD0()
3328 %{
3329 predicate(jlong_cast(n->getd()) == 0);
3330 match(ConD);
3331
3332 op_cost(5);
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3336
3337 // Double Immediate
3338 operand immD()
3339 %{
3340 match(ConD);
3341
3342 op_cost(15);
3343 format %{ %}
3344 interface(CONST_INTER);
3345 %}
3346
3347 // Immediates for special shifts (sign extend)
3348
3349 // Constants for increment
3350 operand immI_16()
3351 %{
3352 predicate(n->get_int() == 16);
3353 match(ConI);
3354
3355 format %{ %}
3356 interface(CONST_INTER);
3357 %}
3358
3359 operand immI_24()
3360 %{
3361 predicate(n->get_int() == 24);
3362 match(ConI);
3363
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3367
3368 // Constant for byte-wide masking
3369 operand immI_255()
3370 %{
3371 predicate(n->get_int() == 255);
3372 match(ConI);
3373
3374 format %{ %}
3375 interface(CONST_INTER);
3376 %}
3377
3378 // Constant for short-wide masking
3379 operand immI_65535()
3380 %{
3381 predicate(n->get_int() == 65535);
3382 match(ConI);
3383
3384 format %{ %}
3385 interface(CONST_INTER);
3386 %}
3387
3388 // Constant for byte-wide masking
3389 operand immL_255()
3390 %{
3391 predicate(n->get_long() == 255);
3392 match(ConL);
3393
3394 format %{ %}
3395 interface(CONST_INTER);
3396 %}
3397
3398 // Constant for short-wide masking
3399 operand immL_65535()
3400 %{
3401 predicate(n->get_long() == 65535);
3402 match(ConL);
3403
3404 format %{ %}
3405 interface(CONST_INTER);
3406 %}
3407
3408 // Register Operands
3409 // Integer Register
3410 operand rRegI()
3411 %{
3412 constraint(ALLOC_IN_RC(int_reg));
3413 match(RegI);
3414
3415 match(rax_RegI);
3416 match(rbx_RegI);
3417 match(rcx_RegI);
3418 match(rdx_RegI);
3419 match(rdi_RegI);
3420
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 // Special Registers
3426 operand rax_RegI()
3427 %{
3428 constraint(ALLOC_IN_RC(int_rax_reg));
3429 match(RegI);
3430 match(rRegI);
3431
3432 format %{ "RAX" %}
3433 interface(REG_INTER);
3434 %}
3435
3436 // Special Registers
3437 operand rbx_RegI()
3438 %{
3439 constraint(ALLOC_IN_RC(int_rbx_reg));
3440 match(RegI);
3441 match(rRegI);
3442
3443 format %{ "RBX" %}
3444 interface(REG_INTER);
3445 %}
3446
3447 operand rcx_RegI()
3448 %{
3449 constraint(ALLOC_IN_RC(int_rcx_reg));
3450 match(RegI);
3451 match(rRegI);
3452
3453 format %{ "RCX" %}
3454 interface(REG_INTER);
3455 %}
3456
3457 operand rdx_RegI()
3458 %{
3459 constraint(ALLOC_IN_RC(int_rdx_reg));
3460 match(RegI);
3461 match(rRegI);
3462
3463 format %{ "RDX" %}
3464 interface(REG_INTER);
3465 %}
3466
3467 operand rdi_RegI()
3468 %{
3469 constraint(ALLOC_IN_RC(int_rdi_reg));
3470 match(RegI);
3471 match(rRegI);
3472
3473 format %{ "RDI" %}
3474 interface(REG_INTER);
3475 %}
3476
3477 operand no_rcx_RegI()
3478 %{
3479 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3480 match(RegI);
3481 match(rax_RegI);
3482 match(rbx_RegI);
3483 match(rdx_RegI);
3484 match(rdi_RegI);
3485
3486 format %{ %}
3487 interface(REG_INTER);
3488 %}
3489
3490 operand no_rax_rdx_RegI()
3491 %{
3492 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3493 match(RegI);
3494 match(rbx_RegI);
3495 match(rcx_RegI);
3496 match(rdi_RegI);
3497
3498 format %{ %}
3499 interface(REG_INTER);
3500 %}
3501
3502 // Pointer Register
3503 operand any_RegP()
3504 %{
3505 constraint(ALLOC_IN_RC(any_reg));
3506 match(RegP);
3507 match(rax_RegP);
3508 match(rbx_RegP);
3509 match(rdi_RegP);
3510 match(rsi_RegP);
3511 match(rbp_RegP);
3512 match(r15_RegP);
3513 match(rRegP);
3514
3515 format %{ %}
3516 interface(REG_INTER);
3517 %}
3518
3519 operand rRegP()
3520 %{
3521 constraint(ALLOC_IN_RC(ptr_reg));
3522 match(RegP);
3523 match(rax_RegP);
3524 match(rbx_RegP);
3525 match(rdi_RegP);
3526 match(rsi_RegP);
3527 match(rbp_RegP);
3528 match(r15_RegP); // See Q&A below about r15_RegP.
3529
3530 format %{ %}
3531 interface(REG_INTER);
3532 %}
3533
3534 operand rRegN() %{
3535 constraint(ALLOC_IN_RC(int_reg));
3536 match(RegN);
3537
3538 format %{ %}
3539 interface(REG_INTER);
3540 %}
3541
3542 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3543 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3544 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3545 // The output of an instruction is controlled by the allocator, which respects
3546 // register class masks, not match rules. Unless an instruction mentions
3547 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3548 // by the allocator as an input.
3549
3550 operand no_rax_RegP()
3551 %{
3552 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3553 match(RegP);
3554 match(rbx_RegP);
3555 match(rsi_RegP);
3556 match(rdi_RegP);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 operand no_rbp_RegP()
3563 %{
3564 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3565 match(RegP);
3566 match(rbx_RegP);
3567 match(rsi_RegP);
3568 match(rdi_RegP);
3569
3570 format %{ %}
3571 interface(REG_INTER);
3572 %}
3573
3574 operand no_rax_rbx_RegP()
3575 %{
3576 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3577 match(RegP);
3578 match(rsi_RegP);
3579 match(rdi_RegP);
3580
3581 format %{ %}
3582 interface(REG_INTER);
3583 %}
3584
3585 // Special Registers
3586 // Return a pointer value
3587 operand rax_RegP()
3588 %{
3589 constraint(ALLOC_IN_RC(ptr_rax_reg));
3590 match(RegP);
3591 match(rRegP);
3592
3593 format %{ %}
3594 interface(REG_INTER);
3595 %}
3596
3597 // Special Registers
3598 // Return a compressed pointer value
3599 operand rax_RegN()
3600 %{
3601 constraint(ALLOC_IN_RC(int_rax_reg));
3602 match(RegN);
3603 match(rRegN);
3604
3605 format %{ %}
3606 interface(REG_INTER);
3607 %}
3608
3609 // Used in AtomicAdd
3610 operand rbx_RegP()
3611 %{
3612 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3613 match(RegP);
3614 match(rRegP);
3615
3616 format %{ %}
3617 interface(REG_INTER);
3618 %}
3619
3620 operand rsi_RegP()
3621 %{
3622 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3623 match(RegP);
3624 match(rRegP);
3625
3626 format %{ %}
3627 interface(REG_INTER);
3628 %}
3629
3630 // Used in rep stosq
3631 operand rdi_RegP()
3632 %{
3633 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3634 match(RegP);
3635 match(rRegP);
3636
3637 format %{ %}
3638 interface(REG_INTER);
3639 %}
3640
3641 operand rbp_RegP()
3642 %{
3643 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3644 match(RegP);
3645 match(rRegP);
3646
3647 format %{ %}
3648 interface(REG_INTER);
3649 %}
3650
3651 operand r15_RegP()
3652 %{
3653 constraint(ALLOC_IN_RC(ptr_r15_reg));
3654 match(RegP);
3655 match(rRegP);
3656
3657 format %{ %}
3658 interface(REG_INTER);
3659 %}
3660
3661 operand rRegL()
3662 %{
3663 constraint(ALLOC_IN_RC(long_reg));
3664 match(RegL);
3665 match(rax_RegL);
3666 match(rdx_RegL);
3667
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3671
3672 // Special Registers
3673 operand no_rax_rdx_RegL()
3674 %{
3675 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3676 match(RegL);
3677 match(rRegL);
3678
3679 format %{ %}
3680 interface(REG_INTER);
3681 %}
3682
3683 operand no_rax_RegL()
3684 %{
3685 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3686 match(RegL);
3687 match(rRegL);
3688 match(rdx_RegL);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 operand no_rcx_RegL()
3695 %{
3696 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3697 match(RegL);
3698 match(rRegL);
3699
3700 format %{ %}
3701 interface(REG_INTER);
3702 %}
3703
3704 operand rax_RegL()
3705 %{
3706 constraint(ALLOC_IN_RC(long_rax_reg));
3707 match(RegL);
3708 match(rRegL);
3709
3710 format %{ "RAX" %}
3711 interface(REG_INTER);
3712 %}
3713
3714 operand rcx_RegL()
3715 %{
3716 constraint(ALLOC_IN_RC(long_rcx_reg));
3717 match(RegL);
3718 match(rRegL);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand rdx_RegL()
3725 %{
3726 constraint(ALLOC_IN_RC(long_rdx_reg));
3727 match(RegL);
3728 match(rRegL);
3729
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3733
3734 // Flags register, used as output of compare instructions
3735 operand rFlagsReg()
3736 %{
3737 constraint(ALLOC_IN_RC(int_flags));
3738 match(RegFlags);
3739
3740 format %{ "RFLAGS" %}
3741 interface(REG_INTER);
3742 %}
3743
3744 // Flags register, used as output of FLOATING POINT compare instructions
3745 operand rFlagsRegU()
3746 %{
3747 constraint(ALLOC_IN_RC(int_flags));
3748 match(RegFlags);
3749
3750 format %{ "RFLAGS_U" %}
3751 interface(REG_INTER);
3752 %}
3753
3754 operand rFlagsRegUCF() %{
3755 constraint(ALLOC_IN_RC(int_flags));
3756 match(RegFlags);
3757 predicate(false);
3758
3759 format %{ "RFLAGS_U_CF" %}
3760 interface(REG_INTER);
3761 %}
3762
3763 // Float register operands
3764 operand regF()
3765 %{
3766 constraint(ALLOC_IN_RC(float_reg));
3767 match(RegF);
3768
3769 format %{ %}
3770 interface(REG_INTER);
3771 %}
3772
3773 // Double register operands
3774 operand regD()
3775 %{
3776 constraint(ALLOC_IN_RC(double_reg));
3777 match(RegD);
3778
3779 format %{ %}
3780 interface(REG_INTER);
3781 %}
3782
3783 //----------Memory Operands----------------------------------------------------
3784 // Direct Memory Operand
3785 // operand direct(immP addr)
3786 // %{
3787 // match(addr);
3788
3789 // format %{ "[$addr]" %}
3790 // interface(MEMORY_INTER) %{
3791 // base(0xFFFFFFFF);
3792 // index(0x4);
3793 // scale(0x0);
3794 // disp($addr);
3795 // %}
3796 // %}
3797
3798 // Indirect Memory Operand
3799 operand indirect(any_RegP reg)
3800 %{
3801 constraint(ALLOC_IN_RC(ptr_reg));
3802 match(reg);
3803
3804 format %{ "[$reg]" %}
3805 interface(MEMORY_INTER) %{
3806 base($reg);
3807 index(0x4);
3808 scale(0x0);
3809 disp(0x0);
3810 %}
3811 %}
3812
3813 // Indirect Memory Plus Short Offset Operand
3814 operand indOffset8(any_RegP reg, immL8 off)
3815 %{
3816 constraint(ALLOC_IN_RC(ptr_reg));
3817 match(AddP reg off);
3818
3819 format %{ "[$reg + $off (8-bit)]" %}
3820 interface(MEMORY_INTER) %{
3821 base($reg);
3822 index(0x4);
3823 scale(0x0);
3824 disp($off);
3825 %}
3826 %}
3827
3828 // Indirect Memory Plus Long Offset Operand
3829 operand indOffset32(any_RegP reg, immL32 off)
3830 %{
3831 constraint(ALLOC_IN_RC(ptr_reg));
3832 match(AddP reg off);
3833
3834 format %{ "[$reg + $off (32-bit)]" %}
3835 interface(MEMORY_INTER) %{
3836 base($reg);
3837 index(0x4);
3838 scale(0x0);
3839 disp($off);
3840 %}
3841 %}
3842
3843 // Indirect Memory Plus Index Register Plus Offset Operand
3844 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3845 %{
3846 constraint(ALLOC_IN_RC(ptr_reg));
3847 match(AddP (AddP reg lreg) off);
3848
3849 op_cost(10);
3850 format %{"[$reg + $off + $lreg]" %}
3851 interface(MEMORY_INTER) %{
3852 base($reg);
3853 index($lreg);
3854 scale(0x0);
3855 disp($off);
3856 %}
3857 %}
3858
3859 // Indirect Memory Plus Index Register Plus Offset Operand
3860 operand indIndex(any_RegP reg, rRegL lreg)
3861 %{
3862 constraint(ALLOC_IN_RC(ptr_reg));
3863 match(AddP reg lreg);
3864
3865 op_cost(10);
3866 format %{"[$reg + $lreg]" %}
3867 interface(MEMORY_INTER) %{
3868 base($reg);
3869 index($lreg);
3870 scale(0x0);
3871 disp(0x0);
3872 %}
3873 %}
3874
3875 // Indirect Memory Times Scale Plus Index Register
3876 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3877 %{
3878 constraint(ALLOC_IN_RC(ptr_reg));
3879 match(AddP reg (LShiftL lreg scale));
3880
3881 op_cost(10);
3882 format %{"[$reg + $lreg << $scale]" %}
3883 interface(MEMORY_INTER) %{
3884 base($reg);
3885 index($lreg);
3886 scale($scale);
3887 disp(0x0);
3888 %}
3889 %}
3890
3891 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3892 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3893 %{
3894 constraint(ALLOC_IN_RC(ptr_reg));
3895 match(AddP (AddP reg (LShiftL lreg scale)) off);
3896
3897 op_cost(10);
3898 format %{"[$reg + $off + $lreg << $scale]" %}
3899 interface(MEMORY_INTER) %{
3900 base($reg);
3901 index($lreg);
3902 scale($scale);
3903 disp($off);
3904 %}
3905 %}
3906
3907 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3908 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3909 %{
3910 constraint(ALLOC_IN_RC(ptr_reg));
3911 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3912 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3913
3914 op_cost(10);
3915 format %{"[$reg + $off + $idx << $scale]" %}
3916 interface(MEMORY_INTER) %{
3917 base($reg);
3918 index($idx);
3919 scale($scale);
3920 disp($off);
3921 %}
3922 %}
3923
3924 // Indirect Narrow Oop Plus Offset Operand
3925 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3926 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3927 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3928 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3929 constraint(ALLOC_IN_RC(ptr_reg));
3930 match(AddP (DecodeN reg) off);
3931
3932 op_cost(10);
3933 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3934 interface(MEMORY_INTER) %{
3935 base(0xc); // R12
3936 index($reg);
3937 scale(0x3);
3938 disp($off);
3939 %}
3940 %}
3941
3942 // Indirect Memory Operand
3943 operand indirectNarrow(rRegN reg)
3944 %{
3945 predicate(Universe::narrow_oop_shift() == 0);
3946 constraint(ALLOC_IN_RC(ptr_reg));
3947 match(DecodeN reg);
3948
3949 format %{ "[$reg]" %}
3950 interface(MEMORY_INTER) %{
3951 base($reg);
3952 index(0x4);
3953 scale(0x0);
3954 disp(0x0);
3955 %}
3956 %}
3957
3958 // Indirect Memory Plus Short Offset Operand
3959 operand indOffset8Narrow(rRegN reg, immL8 off)
3960 %{
3961 predicate(Universe::narrow_oop_shift() == 0);
3962 constraint(ALLOC_IN_RC(ptr_reg));
3963 match(AddP (DecodeN reg) off);
3964
3965 format %{ "[$reg + $off (8-bit)]" %}
3966 interface(MEMORY_INTER) %{
3967 base($reg);
3968 index(0x4);
3969 scale(0x0);
3970 disp($off);
3971 %}
3972 %}
3973
3974 // Indirect Memory Plus Long Offset Operand
3975 operand indOffset32Narrow(rRegN reg, immL32 off)
3976 %{
3977 predicate(Universe::narrow_oop_shift() == 0);
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 match(AddP (DecodeN reg) off);
3980
3981 format %{ "[$reg + $off (32-bit)]" %}
3982 interface(MEMORY_INTER) %{
3983 base($reg);
3984 index(0x4);
3985 scale(0x0);
3986 disp($off);
3987 %}
3988 %}
3989
3990 // Indirect Memory Plus Index Register Plus Offset Operand
3991 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3992 %{
3993 predicate(Universe::narrow_oop_shift() == 0);
3994 constraint(ALLOC_IN_RC(ptr_reg));
3995 match(AddP (AddP (DecodeN reg) lreg) off);
3996
3997 op_cost(10);
3998 format %{"[$reg + $off + $lreg]" %}
3999 interface(MEMORY_INTER) %{
4000 base($reg);
4001 index($lreg);
4002 scale(0x0);
4003 disp($off);
4004 %}
4005 %}
4006
4007 // Indirect Memory Plus Index Register Plus Offset Operand
4008 operand indIndexNarrow(rRegN reg, rRegL lreg)
4009 %{
4010 predicate(Universe::narrow_oop_shift() == 0);
4011 constraint(ALLOC_IN_RC(ptr_reg));
4012 match(AddP (DecodeN reg) lreg);
4013
4014 op_cost(10);
4015 format %{"[$reg + $lreg]" %}
4016 interface(MEMORY_INTER) %{
4017 base($reg);
4018 index($lreg);
4019 scale(0x0);
4020 disp(0x0);
4021 %}
4022 %}
4023
4024 // Indirect Memory Times Scale Plus Index Register
4025 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4026 %{
4027 predicate(Universe::narrow_oop_shift() == 0);
4028 constraint(ALLOC_IN_RC(ptr_reg));
4029 match(AddP (DecodeN reg) (LShiftL lreg scale));
4030
4031 op_cost(10);
4032 format %{"[$reg + $lreg << $scale]" %}
4033 interface(MEMORY_INTER) %{
4034 base($reg);
4035 index($lreg);
4036 scale($scale);
4037 disp(0x0);
4038 %}
4039 %}
4040
4041 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4042 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4043 %{
4044 predicate(Universe::narrow_oop_shift() == 0);
4045 constraint(ALLOC_IN_RC(ptr_reg));
4046 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4047
4048 op_cost(10);
4049 format %{"[$reg + $off + $lreg << $scale]" %}
4050 interface(MEMORY_INTER) %{
4051 base($reg);
4052 index($lreg);
4053 scale($scale);
4054 disp($off);
4055 %}
4056 %}
4057
4058 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4059 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4060 %{
4061 constraint(ALLOC_IN_RC(ptr_reg));
4062 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4063 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4064
4065 op_cost(10);
4066 format %{"[$reg + $off + $idx << $scale]" %}
4067 interface(MEMORY_INTER) %{
4068 base($reg);
4069 index($idx);
4070 scale($scale);
4071 disp($off);
4072 %}
4073 %}
4074
4075
4076 //----------Special Memory Operands--------------------------------------------
4077 // Stack Slot Operand - This operand is used for loading and storing temporary
4078 // values on the stack where a match requires a value to
4079 // flow through memory.
4080 operand stackSlotP(sRegP reg)
4081 %{
4082 constraint(ALLOC_IN_RC(stack_slots));
4083 // No match rule because this operand is only generated in matching
4084
4085 format %{ "[$reg]" %}
4086 interface(MEMORY_INTER) %{
4087 base(0x4); // RSP
4088 index(0x4); // No Index
4089 scale(0x0); // No Scale
4090 disp($reg); // Stack Offset
4091 %}
4092 %}
4093
4094 operand stackSlotI(sRegI reg)
4095 %{
4096 constraint(ALLOC_IN_RC(stack_slots));
4097 // No match rule because this operand is only generated in matching
4098
4099 format %{ "[$reg]" %}
4100 interface(MEMORY_INTER) %{
4101 base(0x4); // RSP
4102 index(0x4); // No Index
4103 scale(0x0); // No Scale
4104 disp($reg); // Stack Offset
4105 %}
4106 %}
4107
4108 operand stackSlotF(sRegF reg)
4109 %{
4110 constraint(ALLOC_IN_RC(stack_slots));
4111 // No match rule because this operand is only generated in matching
4112
4113 format %{ "[$reg]" %}
4114 interface(MEMORY_INTER) %{
4115 base(0x4); // RSP
4116 index(0x4); // No Index
4117 scale(0x0); // No Scale
4118 disp($reg); // Stack Offset
4119 %}
4120 %}
4121
4122 operand stackSlotD(sRegD reg)
4123 %{
4124 constraint(ALLOC_IN_RC(stack_slots));
4125 // No match rule because this operand is only generated in matching
4126
4127 format %{ "[$reg]" %}
4128 interface(MEMORY_INTER) %{
4129 base(0x4); // RSP
4130 index(0x4); // No Index
4131 scale(0x0); // No Scale
4132 disp($reg); // Stack Offset
4133 %}
4134 %}
4135 operand stackSlotL(sRegL reg)
4136 %{
4137 constraint(ALLOC_IN_RC(stack_slots));
4138 // No match rule because this operand is only generated in matching
4139
4140 format %{ "[$reg]" %}
4141 interface(MEMORY_INTER) %{
4142 base(0x4); // RSP
4143 index(0x4); // No Index
4144 scale(0x0); // No Scale
4145 disp($reg); // Stack Offset
4146 %}
4147 %}
4148
4149 //----------Conditional Branch Operands----------------------------------------
4150 // Comparison Op - This is the operation of the comparison, and is limited to
4151 // the following set of codes:
4152 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4153 //
4154 // Other attributes of the comparison, such as unsignedness, are specified
4155 // by the comparison instruction that sets a condition code flags register.
4156 // That result is represented by a flags operand whose subtype is appropriate
4157 // to the unsignedness (etc.) of the comparison.
4158 //
4159 // Later, the instruction which matches both the Comparison Op (a Bool) and
4160 // the flags (produced by the Cmp) specifies the coding of the comparison op
4161 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4162
4163 // Comparision Code
4164 operand cmpOp()
4165 %{
4166 match(Bool);
4167
4168 format %{ "" %}
4169 interface(COND_INTER) %{
4170 equal(0x4, "e");
4171 not_equal(0x5, "ne");
4172 less(0xC, "l");
4173 greater_equal(0xD, "ge");
4174 less_equal(0xE, "le");
4175 greater(0xF, "g");
4176 %}
4177 %}
4178
4179 // Comparison Code, unsigned compare. Used by FP also, with
4180 // C2 (unordered) turned into GT or LT already. The other bits
4181 // C0 and C3 are turned into Carry & Zero flags.
4182 operand cmpOpU()
4183 %{
4184 match(Bool);
4185
4186 format %{ "" %}
4187 interface(COND_INTER) %{
4188 equal(0x4, "e");
4189 not_equal(0x5, "ne");
4190 less(0x2, "b");
4191 greater_equal(0x3, "nb");
4192 less_equal(0x6, "be");
4193 greater(0x7, "nbe");
4194 %}
4195 %}
4196
4197
4198 // Floating comparisons that don't require any fixup for the unordered case
4199 operand cmpOpUCF() %{
4200 match(Bool);
4201 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4202 n->as_Bool()->_test._test == BoolTest::ge ||
4203 n->as_Bool()->_test._test == BoolTest::le ||
4204 n->as_Bool()->_test._test == BoolTest::gt);
4205 format %{ "" %}
4206 interface(COND_INTER) %{
4207 equal(0x4, "e");
4208 not_equal(0x5, "ne");
4209 less(0x2, "b");
4210 greater_equal(0x3, "nb");
4211 less_equal(0x6, "be");
4212 greater(0x7, "nbe");
4213 %}
4214 %}
4215
4216
4217 // Floating comparisons that can be fixed up with extra conditional jumps
4218 operand cmpOpUCF2() %{
4219 match(Bool);
4220 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4221 n->as_Bool()->_test._test == BoolTest::eq);
4222 format %{ "" %}
4223 interface(COND_INTER) %{
4224 equal(0x4, "e");
4225 not_equal(0x5, "ne");
4226 less(0x2, "b");
4227 greater_equal(0x3, "nb");
4228 less_equal(0x6, "be");
4229 greater(0x7, "nbe");
4230 %}
4231 %}
4232
4233
4234 //----------OPERAND CLASSES----------------------------------------------------
4235 // Operand Classes are groups of operands that are used as to simplify
4236 // instruction definitions by not requiring the AD writer to specify separate
4237 // instructions for every form of operand when the instruction accepts
4238 // multiple operand types with the same basic encoding and format. The classic
4239 // case of this is memory operands.
4240
4241 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4242 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4243 indCompressedOopOffset,
4244 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4245 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4246 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4247
4248 //----------PIPELINE-----------------------------------------------------------
4249 // Rules which define the behavior of the target architectures pipeline.
4250 pipeline %{
4251
4252 //----------ATTRIBUTES---------------------------------------------------------
4253 attributes %{
4254 variable_size_instructions; // Fixed size instructions
4255 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4256 instruction_unit_size = 1; // An instruction is 1 bytes long
4257 instruction_fetch_unit_size = 16; // The processor fetches one line
4258 instruction_fetch_units = 1; // of 16 bytes
4259
4260 // List of nop instructions
4261 nops( MachNop );
4262 %}
4263
4264 //----------RESOURCES----------------------------------------------------------
4265 // Resources are the functional units available to the machine
4266
4267 // Generic P2/P3 pipeline
4268 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4269 // 3 instructions decoded per cycle.
4270 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4271 // 3 ALU op, only ALU0 handles mul instructions.
4272 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4273 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4274 BR, FPU,
4275 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4276
4277 //----------PIPELINE DESCRIPTION-----------------------------------------------
4278 // Pipeline Description specifies the stages in the machine's pipeline
4279
4280 // Generic P2/P3 pipeline
4281 pipe_desc(S0, S1, S2, S3, S4, S5);
4282
4283 //----------PIPELINE CLASSES---------------------------------------------------
4284 // Pipeline Classes describe the stages in which input and output are
4285 // referenced by the hardware pipeline.
4286
4287 // Naming convention: ialu or fpu
4288 // Then: _reg
4289 // Then: _reg if there is a 2nd register
4290 // Then: _long if it's a pair of instructions implementing a long
4291 // Then: _fat if it requires the big decoder
4292 // Or: _mem if it requires the big decoder and a memory unit.
4293
4294 // Integer ALU reg operation
4295 pipe_class ialu_reg(rRegI dst)
4296 %{
4297 single_instruction;
4298 dst : S4(write);
4299 dst : S3(read);
4300 DECODE : S0; // any decoder
4301 ALU : S3; // any alu
4302 %}
4303
4304 // Long ALU reg operation
4305 pipe_class ialu_reg_long(rRegL dst)
4306 %{
4307 instruction_count(2);
4308 dst : S4(write);
4309 dst : S3(read);
4310 DECODE : S0(2); // any 2 decoders
4311 ALU : S3(2); // both alus
4312 %}
4313
4314 // Integer ALU reg operation using big decoder
4315 pipe_class ialu_reg_fat(rRegI dst)
4316 %{
4317 single_instruction;
4318 dst : S4(write);
4319 dst : S3(read);
4320 D0 : S0; // big decoder only
4321 ALU : S3; // any alu
4322 %}
4323
4324 // Long ALU reg operation using big decoder
4325 pipe_class ialu_reg_long_fat(rRegL dst)
4326 %{
4327 instruction_count(2);
4328 dst : S4(write);
4329 dst : S3(read);
4330 D0 : S0(2); // big decoder only; twice
4331 ALU : S3(2); // any 2 alus
4332 %}
4333
4334 // Integer ALU reg-reg operation
4335 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4336 %{
4337 single_instruction;
4338 dst : S4(write);
4339 src : S3(read);
4340 DECODE : S0; // any decoder
4341 ALU : S3; // any alu
4342 %}
4343
4344 // Long ALU reg-reg operation
4345 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4346 %{
4347 instruction_count(2);
4348 dst : S4(write);
4349 src : S3(read);
4350 DECODE : S0(2); // any 2 decoders
4351 ALU : S3(2); // both alus
4352 %}
4353
4354 // Integer ALU reg-reg operation
4355 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4356 %{
4357 single_instruction;
4358 dst : S4(write);
4359 src : S3(read);
4360 D0 : S0; // big decoder only
4361 ALU : S3; // any alu
4362 %}
4363
4364 // Long ALU reg-reg operation
4365 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4366 %{
4367 instruction_count(2);
4368 dst : S4(write);
4369 src : S3(read);
4370 D0 : S0(2); // big decoder only; twice
4371 ALU : S3(2); // both alus
4372 %}
4373
4374 // Integer ALU reg-mem operation
4375 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4376 %{
4377 single_instruction;
4378 dst : S5(write);
4379 mem : S3(read);
4380 D0 : S0; // big decoder only
4381 ALU : S4; // any alu
4382 MEM : S3; // any mem
4383 %}
4384
4385 // Integer mem operation (prefetch)
4386 pipe_class ialu_mem(memory mem)
4387 %{
4388 single_instruction;
4389 mem : S3(read);
4390 D0 : S0; // big decoder only
4391 MEM : S3; // any mem
4392 %}
4393
4394 // Integer Store to Memory
4395 pipe_class ialu_mem_reg(memory mem, rRegI src)
4396 %{
4397 single_instruction;
4398 mem : S3(read);
4399 src : S5(read);
4400 D0 : S0; // big decoder only
4401 ALU : S4; // any alu
4402 MEM : S3;
4403 %}
4404
4405 // // Long Store to Memory
4406 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4407 // %{
4408 // instruction_count(2);
4409 // mem : S3(read);
4410 // src : S5(read);
4411 // D0 : S0(2); // big decoder only; twice
4412 // ALU : S4(2); // any 2 alus
4413 // MEM : S3(2); // Both mems
4414 // %}
4415
4416 // Integer Store to Memory
4417 pipe_class ialu_mem_imm(memory mem)
4418 %{
4419 single_instruction;
4420 mem : S3(read);
4421 D0 : S0; // big decoder only
4422 ALU : S4; // any alu
4423 MEM : S3;
4424 %}
4425
4426 // Integer ALU0 reg-reg operation
4427 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4428 %{
4429 single_instruction;
4430 dst : S4(write);
4431 src : S3(read);
4432 D0 : S0; // Big decoder only
4433 ALU0 : S3; // only alu0
4434 %}
4435
4436 // Integer ALU0 reg-mem operation
4437 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4438 %{
4439 single_instruction;
4440 dst : S5(write);
4441 mem : S3(read);
4442 D0 : S0; // big decoder only
4443 ALU0 : S4; // ALU0 only
4444 MEM : S3; // any mem
4445 %}
4446
4447 // Integer ALU reg-reg operation
4448 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4449 %{
4450 single_instruction;
4451 cr : S4(write);
4452 src1 : S3(read);
4453 src2 : S3(read);
4454 DECODE : S0; // any decoder
4455 ALU : S3; // any alu
4456 %}
4457
4458 // Integer ALU reg-imm operation
4459 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4460 %{
4461 single_instruction;
4462 cr : S4(write);
4463 src1 : S3(read);
4464 DECODE : S0; // any decoder
4465 ALU : S3; // any alu
4466 %}
4467
4468 // Integer ALU reg-mem operation
4469 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4470 %{
4471 single_instruction;
4472 cr : S4(write);
4473 src1 : S3(read);
4474 src2 : S3(read);
4475 D0 : S0; // big decoder only
4476 ALU : S4; // any alu
4477 MEM : S3;
4478 %}
4479
4480 // Conditional move reg-reg
4481 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4482 %{
4483 instruction_count(4);
4484 y : S4(read);
4485 q : S3(read);
4486 p : S3(read);
4487 DECODE : S0(4); // any decoder
4488 %}
4489
4490 // Conditional move reg-reg
4491 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4492 %{
4493 single_instruction;
4494 dst : S4(write);
4495 src : S3(read);
4496 cr : S3(read);
4497 DECODE : S0; // any decoder
4498 %}
4499
4500 // Conditional move reg-mem
4501 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4502 %{
4503 single_instruction;
4504 dst : S4(write);
4505 src : S3(read);
4506 cr : S3(read);
4507 DECODE : S0; // any decoder
4508 MEM : S3;
4509 %}
4510
4511 // Conditional move reg-reg long
4512 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4513 %{
4514 single_instruction;
4515 dst : S4(write);
4516 src : S3(read);
4517 cr : S3(read);
4518 DECODE : S0(2); // any 2 decoders
4519 %}
4520
4521 // XXX
4522 // // Conditional move double reg-reg
4523 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4524 // %{
4525 // single_instruction;
4526 // dst : S4(write);
4527 // src : S3(read);
4528 // cr : S3(read);
4529 // DECODE : S0; // any decoder
4530 // %}
4531
4532 // Float reg-reg operation
4533 pipe_class fpu_reg(regD dst)
4534 %{
4535 instruction_count(2);
4536 dst : S3(read);
4537 DECODE : S0(2); // any 2 decoders
4538 FPU : S3;
4539 %}
4540
4541 // Float reg-reg operation
4542 pipe_class fpu_reg_reg(regD dst, regD src)
4543 %{
4544 instruction_count(2);
4545 dst : S4(write);
4546 src : S3(read);
4547 DECODE : S0(2); // any 2 decoders
4548 FPU : S3;
4549 %}
4550
4551 // Float reg-reg operation
4552 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4553 %{
4554 instruction_count(3);
4555 dst : S4(write);
4556 src1 : S3(read);
4557 src2 : S3(read);
4558 DECODE : S0(3); // any 3 decoders
4559 FPU : S3(2);
4560 %}
4561
4562 // Float reg-reg operation
4563 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4564 %{
4565 instruction_count(4);
4566 dst : S4(write);
4567 src1 : S3(read);
4568 src2 : S3(read);
4569 src3 : S3(read);
4570 DECODE : S0(4); // any 3 decoders
4571 FPU : S3(2);
4572 %}
4573
4574 // Float reg-reg operation
4575 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4576 %{
4577 instruction_count(4);
4578 dst : S4(write);
4579 src1 : S3(read);
4580 src2 : S3(read);
4581 src3 : S3(read);
4582 DECODE : S1(3); // any 3 decoders
4583 D0 : S0; // Big decoder only
4584 FPU : S3(2);
4585 MEM : S3;
4586 %}
4587
4588 // Float reg-mem operation
4589 pipe_class fpu_reg_mem(regD dst, memory mem)
4590 %{
4591 instruction_count(2);
4592 dst : S5(write);
4593 mem : S3(read);
4594 D0 : S0; // big decoder only
4595 DECODE : S1; // any decoder for FPU POP
4596 FPU : S4;
4597 MEM : S3; // any mem
4598 %}
4599
4600 // Float reg-mem operation
4601 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4602 %{
4603 instruction_count(3);
4604 dst : S5(write);
4605 src1 : S3(read);
4606 mem : S3(read);
4607 D0 : S0; // big decoder only
4608 DECODE : S1(2); // any decoder for FPU POP
4609 FPU : S4;
4610 MEM : S3; // any mem
4611 %}
4612
4613 // Float mem-reg operation
4614 pipe_class fpu_mem_reg(memory mem, regD src)
4615 %{
4616 instruction_count(2);
4617 src : S5(read);
4618 mem : S3(read);
4619 DECODE : S0; // any decoder for FPU PUSH
4620 D0 : S1; // big decoder only
4621 FPU : S4;
4622 MEM : S3; // any mem
4623 %}
4624
4625 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4626 %{
4627 instruction_count(3);
4628 src1 : S3(read);
4629 src2 : S3(read);
4630 mem : S3(read);
4631 DECODE : S0(2); // any decoder for FPU PUSH
4632 D0 : S1; // big decoder only
4633 FPU : S4;
4634 MEM : S3; // any mem
4635 %}
4636
4637 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4638 %{
4639 instruction_count(3);
4640 src1 : S3(read);
4641 src2 : S3(read);
4642 mem : S4(read);
4643 DECODE : S0; // any decoder for FPU PUSH
4644 D0 : S0(2); // big decoder only
4645 FPU : S4;
4646 MEM : S3(2); // any mem
4647 %}
4648
4649 pipe_class fpu_mem_mem(memory dst, memory src1)
4650 %{
4651 instruction_count(2);
4652 src1 : S3(read);
4653 dst : S4(read);
4654 D0 : S0(2); // big decoder only
4655 MEM : S3(2); // any mem
4656 %}
4657
4658 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4659 %{
4660 instruction_count(3);
4661 src1 : S3(read);
4662 src2 : S3(read);
4663 dst : S4(read);
4664 D0 : S0(3); // big decoder only
4665 FPU : S4;
4666 MEM : S3(3); // any mem
4667 %}
4668
4669 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4670 %{
4671 instruction_count(3);
4672 src1 : S4(read);
4673 mem : S4(read);
4674 DECODE : S0; // any decoder for FPU PUSH
4675 D0 : S0(2); // big decoder only
4676 FPU : S4;
4677 MEM : S3(2); // any mem
4678 %}
4679
4680 // Float load constant
4681 pipe_class fpu_reg_con(regD dst)
4682 %{
4683 instruction_count(2);
4684 dst : S5(write);
4685 D0 : S0; // big decoder only for the load
4686 DECODE : S1; // any decoder for FPU POP
4687 FPU : S4;
4688 MEM : S3; // any mem
4689 %}
4690
4691 // Float load constant
4692 pipe_class fpu_reg_reg_con(regD dst, regD src)
4693 %{
4694 instruction_count(3);
4695 dst : S5(write);
4696 src : S3(read);
4697 D0 : S0; // big decoder only for the load
4698 DECODE : S1(2); // any decoder for FPU POP
4699 FPU : S4;
4700 MEM : S3; // any mem
4701 %}
4702
4703 // UnConditional branch
4704 pipe_class pipe_jmp(label labl)
4705 %{
4706 single_instruction;
4707 BR : S3;
4708 %}
4709
4710 // Conditional branch
4711 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4712 %{
4713 single_instruction;
4714 cr : S1(read);
4715 BR : S3;
4716 %}
4717
4718 // Allocation idiom
4719 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4720 %{
4721 instruction_count(1); force_serialization;
4722 fixed_latency(6);
4723 heap_ptr : S3(read);
4724 DECODE : S0(3);
4725 D0 : S2;
4726 MEM : S3;
4727 ALU : S3(2);
4728 dst : S5(write);
4729 BR : S5;
4730 %}
4731
4732 // Generic big/slow expanded idiom
4733 pipe_class pipe_slow()
4734 %{
4735 instruction_count(10); multiple_bundles; force_serialization;
4736 fixed_latency(100);
4737 D0 : S0(2);
4738 MEM : S3(2);
4739 %}
4740
4741 // The real do-nothing guy
4742 pipe_class empty()
4743 %{
4744 instruction_count(0);
4745 %}
4746
4747 // Define the class for the Nop node
4748 define
4749 %{
4750 MachNop = empty;
4751 %}
4752
4753 %}
4754
4755 //----------INSTRUCTIONS-------------------------------------------------------
4756 //
4757 // match -- States which machine-independent subtree may be replaced
4758 // by this instruction.
4759 // ins_cost -- The estimated cost of this instruction is used by instruction
4760 // selection to identify a minimum cost tree of machine
4761 // instructions that matches a tree of machine-independent
4762 // instructions.
4763 // format -- A string providing the disassembly for this instruction.
4764 // The value of an instruction's operand may be inserted
4765 // by referring to it with a '$' prefix.
4766 // opcode -- Three instruction opcodes may be provided. These are referred
4767 // to within an encode class as $primary, $secondary, and $tertiary
4768 // rrspectively. The primary opcode is commonly used to
4769 // indicate the type of machine instruction, while secondary
4770 // and tertiary are often used for prefix options or addressing
4771 // modes.
4772 // ins_encode -- A list of encode classes with parameters. The encode class
4773 // name must have been defined in an 'enc_class' specification
4774 // in the encode section of the architecture description.
4775
4776
4777 //----------Load/Store/Move Instructions---------------------------------------
4778 //----------Load Instructions--------------------------------------------------
4779
4780 // Load Byte (8 bit signed)
4781 instruct loadB(rRegI dst, memory mem)
4782 %{
4783 match(Set dst (LoadB mem));
4784
4785 ins_cost(125);
4786 format %{ "movsbl $dst, $mem\t# byte" %}
4787
4788 ins_encode %{
4789 __ movsbl($dst$$Register, $mem$$Address);
4790 %}
4791
4792 ins_pipe(ialu_reg_mem);
4793 %}
4794
4795 // Load Byte (8 bit signed) into Long Register
4796 instruct loadB2L(rRegL dst, memory mem)
4797 %{
4798 match(Set dst (ConvI2L (LoadB mem)));
4799
4800 ins_cost(125);
4801 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4802
4803 ins_encode %{
4804 __ movsbq($dst$$Register, $mem$$Address);
4805 %}
4806
4807 ins_pipe(ialu_reg_mem);
4808 %}
4809
4810 // Load Unsigned Byte (8 bit UNsigned)
4811 instruct loadUB(rRegI dst, memory mem)
4812 %{
4813 match(Set dst (LoadUB mem));
4814
4815 ins_cost(125);
4816 format %{ "movzbl $dst, $mem\t# ubyte" %}
4817
4818 ins_encode %{
4819 __ movzbl($dst$$Register, $mem$$Address);
4820 %}
4821
4822 ins_pipe(ialu_reg_mem);
4823 %}
4824
4825 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4826 instruct loadUB2L(rRegL dst, memory mem)
4827 %{
4828 match(Set dst (ConvI2L (LoadUB mem)));
4829
4830 ins_cost(125);
4831 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4832
4833 ins_encode %{
4834 __ movzbq($dst$$Register, $mem$$Address);
4835 %}
4836
4837 ins_pipe(ialu_reg_mem);
4838 %}
4839
4840 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4841 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4842 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4843 effect(KILL cr);
4844
4845 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4846 "andl $dst, $mask" %}
4847 ins_encode %{
4848 Register Rdst = $dst$$Register;
4849 __ movzbq(Rdst, $mem$$Address);
4850 __ andl(Rdst, $mask$$constant);
4851 %}
4852 ins_pipe(ialu_reg_mem);
4853 %}
4854
4855 // Load Short (16 bit signed)
4856 instruct loadS(rRegI dst, memory mem)
4857 %{
4858 match(Set dst (LoadS mem));
4859
4860 ins_cost(125);
4861 format %{ "movswl $dst, $mem\t# short" %}
4862
4863 ins_encode %{
4864 __ movswl($dst$$Register, $mem$$Address);
4865 %}
4866
4867 ins_pipe(ialu_reg_mem);
4868 %}
4869
4870 // Load Short (16 bit signed) to Byte (8 bit signed)
4871 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4872 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4873
4874 ins_cost(125);
4875 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4876 ins_encode %{
4877 __ movsbl($dst$$Register, $mem$$Address);
4878 %}
4879 ins_pipe(ialu_reg_mem);
4880 %}
4881
4882 // Load Short (16 bit signed) into Long Register
4883 instruct loadS2L(rRegL dst, memory mem)
4884 %{
4885 match(Set dst (ConvI2L (LoadS mem)));
4886
4887 ins_cost(125);
4888 format %{ "movswq $dst, $mem\t# short -> long" %}
4889
4890 ins_encode %{
4891 __ movswq($dst$$Register, $mem$$Address);
4892 %}
4893
4894 ins_pipe(ialu_reg_mem);
4895 %}
4896
4897 // Load Unsigned Short/Char (16 bit UNsigned)
4898 instruct loadUS(rRegI dst, memory mem)
4899 %{
4900 match(Set dst (LoadUS mem));
4901
4902 ins_cost(125);
4903 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4904
4905 ins_encode %{
4906 __ movzwl($dst$$Register, $mem$$Address);
4907 %}
4908
4909 ins_pipe(ialu_reg_mem);
4910 %}
4911
4912 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4913 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4914 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4915
4916 ins_cost(125);
4917 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4918 ins_encode %{
4919 __ movsbl($dst$$Register, $mem$$Address);
4920 %}
4921 ins_pipe(ialu_reg_mem);
4922 %}
4923
4924 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4925 instruct loadUS2L(rRegL dst, memory mem)
4926 %{
4927 match(Set dst (ConvI2L (LoadUS mem)));
4928
4929 ins_cost(125);
4930 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4931
4932 ins_encode %{
4933 __ movzwq($dst$$Register, $mem$$Address);
4934 %}
4935
4936 ins_pipe(ialu_reg_mem);
4937 %}
4938
4939 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4940 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4941 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4942
4943 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4944 ins_encode %{
4945 __ movzbq($dst$$Register, $mem$$Address);
4946 %}
4947 ins_pipe(ialu_reg_mem);
4948 %}
4949
4950 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4951 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4952 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4953 effect(KILL cr);
4954
4955 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4956 "andl $dst, $mask" %}
4957 ins_encode %{
4958 Register Rdst = $dst$$Register;
4959 __ movzwq(Rdst, $mem$$Address);
4960 __ andl(Rdst, $mask$$constant);
4961 %}
4962 ins_pipe(ialu_reg_mem);
4963 %}
4964
4965 // Load Integer
4966 instruct loadI(rRegI dst, memory mem)
4967 %{
4968 match(Set dst (LoadI mem));
4969
4970 ins_cost(125);
4971 format %{ "movl $dst, $mem\t# int" %}
4972
4973 ins_encode %{
4974 __ movl($dst$$Register, $mem$$Address);
4975 %}
4976
4977 ins_pipe(ialu_reg_mem);
4978 %}
4979
4980 // Load Integer (32 bit signed) to Byte (8 bit signed)
4981 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4982 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4983
4984 ins_cost(125);
4985 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4986 ins_encode %{
4987 __ movsbl($dst$$Register, $mem$$Address);
4988 %}
4989 ins_pipe(ialu_reg_mem);
4990 %}
4991
4992 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4993 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4994 match(Set dst (AndI (LoadI mem) mask));
4995
4996 ins_cost(125);
4997 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4998 ins_encode %{
4999 __ movzbl($dst$$Register, $mem$$Address);
5000 %}
5001 ins_pipe(ialu_reg_mem);
5002 %}
5003
5004 // Load Integer (32 bit signed) to Short (16 bit signed)
5005 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5006 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5007
5008 ins_cost(125);
5009 format %{ "movswl $dst, $mem\t# int -> short" %}
5010 ins_encode %{
5011 __ movswl($dst$$Register, $mem$$Address);
5012 %}
5013 ins_pipe(ialu_reg_mem);
5014 %}
5015
5016 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5017 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5018 match(Set dst (AndI (LoadI mem) mask));
5019
5020 ins_cost(125);
5021 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5022 ins_encode %{
5023 __ movzwl($dst$$Register, $mem$$Address);
5024 %}
5025 ins_pipe(ialu_reg_mem);
5026 %}
5027
5028 // Load Integer into Long Register
5029 instruct loadI2L(rRegL dst, memory mem)
5030 %{
5031 match(Set dst (ConvI2L (LoadI mem)));
5032
5033 ins_cost(125);
5034 format %{ "movslq $dst, $mem\t# int -> long" %}
5035
5036 ins_encode %{
5037 __ movslq($dst$$Register, $mem$$Address);
5038 %}
5039
5040 ins_pipe(ialu_reg_mem);
5041 %}
5042
5043 // Load Integer with mask 0xFF into Long Register
5044 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5045 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5046
5047 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5048 ins_encode %{
5049 __ movzbq($dst$$Register, $mem$$Address);
5050 %}
5051 ins_pipe(ialu_reg_mem);
5052 %}
5053
5054 // Load Integer with mask 0xFFFF into Long Register
5055 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5056 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5057
5058 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5059 ins_encode %{
5060 __ movzwq($dst$$Register, $mem$$Address);
5061 %}
5062 ins_pipe(ialu_reg_mem);
5063 %}
5064
5065 // Load Integer with a 32-bit mask into Long Register
5066 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5067 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5068 effect(KILL cr);
5069
5070 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
5071 "andl $dst, $mask" %}
5072 ins_encode %{
5073 Register Rdst = $dst$$Register;
5074 __ movl(Rdst, $mem$$Address);
5075 __ andl(Rdst, $mask$$constant);
5076 %}
5077 ins_pipe(ialu_reg_mem);
5078 %}
5079
5080 // Load Unsigned Integer into Long Register
5081 instruct loadUI2L(rRegL dst, memory mem)
5082 %{
5083 match(Set dst (LoadUI2L mem));
5084
5085 ins_cost(125);
5086 format %{ "movl $dst, $mem\t# uint -> long" %}
5087
5088 ins_encode %{
5089 __ movl($dst$$Register, $mem$$Address);
5090 %}
5091
5092 ins_pipe(ialu_reg_mem);
5093 %}
5094
5095 // Load Long
5096 instruct loadL(rRegL dst, memory mem)
5097 %{
5098 match(Set dst (LoadL mem));
5099
5100 ins_cost(125);
5101 format %{ "movq $dst, $mem\t# long" %}
5102
5103 ins_encode %{
5104 __ movq($dst$$Register, $mem$$Address);
5105 %}
5106
5107 ins_pipe(ialu_reg_mem); // XXX
5108 %}
5109
5110 // Load Range
5111 instruct loadRange(rRegI dst, memory mem)
5112 %{
5113 match(Set dst (LoadRange mem));
5114
5115 ins_cost(125); // XXX
5116 format %{ "movl $dst, $mem\t# range" %}
5117 opcode(0x8B);
5118 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5119 ins_pipe(ialu_reg_mem);
5120 %}
5121
5122 // Load Pointer
5123 instruct loadP(rRegP dst, memory mem)
5124 %{
5125 match(Set dst (LoadP mem));
5126
5127 ins_cost(125); // XXX
5128 format %{ "movq $dst, $mem\t# ptr" %}
5129 opcode(0x8B);
5130 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5131 ins_pipe(ialu_reg_mem); // XXX
5132 %}
5133
5134 // Load Compressed Pointer
5135 instruct loadN(rRegN dst, memory mem)
5136 %{
5137 match(Set dst (LoadN mem));
5138
5139 ins_cost(125); // XXX
5140 format %{ "movl $dst, $mem\t# compressed ptr" %}
5141 ins_encode %{
5142 __ movl($dst$$Register, $mem$$Address);
5143 %}
5144 ins_pipe(ialu_reg_mem); // XXX
5145 %}
5146
5147
5148 // Load Klass Pointer
5149 instruct loadKlass(rRegP dst, memory mem)
5150 %{
5151 match(Set dst (LoadKlass mem));
5152
5153 ins_cost(125); // XXX
5154 format %{ "movq $dst, $mem\t# class" %}
5155 opcode(0x8B);
5156 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5157 ins_pipe(ialu_reg_mem); // XXX
5158 %}
5159
5160 // Load narrow Klass Pointer
5161 instruct loadNKlass(rRegN dst, memory mem)
5162 %{
5163 match(Set dst (LoadNKlass mem));
5164
5165 ins_cost(125); // XXX
5166 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5167 ins_encode %{
5168 __ movl($dst$$Register, $mem$$Address);
5169 %}
5170 ins_pipe(ialu_reg_mem); // XXX
5171 %}
5172
5173 // Load Float
5174 instruct loadF(regF dst, memory mem)
5175 %{
5176 match(Set dst (LoadF mem));
5177
5178 ins_cost(145); // XXX
5179 format %{ "movss $dst, $mem\t# float" %}
5180 ins_encode %{
5181 __ movflt($dst$$XMMRegister, $mem$$Address);
5182 %}
5183 ins_pipe(pipe_slow); // XXX
5184 %}
5185
5186 // Load Double
5187 instruct loadD_partial(regD dst, memory mem)
5188 %{
5189 predicate(!UseXmmLoadAndClearUpper);
5190 match(Set dst (LoadD mem));
5191
5192 ins_cost(145); // XXX
5193 format %{ "movlpd $dst, $mem\t# double" %}
5194 ins_encode %{
5195 __ movdbl($dst$$XMMRegister, $mem$$Address);
5196 %}
5197 ins_pipe(pipe_slow); // XXX
5198 %}
5199
5200 instruct loadD(regD dst, memory mem)
5201 %{
5202 predicate(UseXmmLoadAndClearUpper);
5203 match(Set dst (LoadD mem));
5204
5205 ins_cost(145); // XXX
5206 format %{ "movsd $dst, $mem\t# double" %}
5207 ins_encode %{
5208 __ movdbl($dst$$XMMRegister, $mem$$Address);
5209 %}
5210 ins_pipe(pipe_slow); // XXX
5211 %}
5212
5213 // Load Effective Address
5214 instruct leaP8(rRegP dst, indOffset8 mem)
5215 %{
5216 match(Set dst mem);
5217
5218 ins_cost(110); // XXX
5219 format %{ "leaq $dst, $mem\t# ptr 8" %}
5220 opcode(0x8D);
5221 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5222 ins_pipe(ialu_reg_reg_fat);
5223 %}
5224
5225 instruct leaP32(rRegP dst, indOffset32 mem)
5226 %{
5227 match(Set dst mem);
5228
5229 ins_cost(110);
5230 format %{ "leaq $dst, $mem\t# ptr 32" %}
5231 opcode(0x8D);
5232 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5233 ins_pipe(ialu_reg_reg_fat);
5234 %}
5235
5236 // instruct leaPIdx(rRegP dst, indIndex mem)
5237 // %{
5238 // match(Set dst mem);
5239
5240 // ins_cost(110);
5241 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5242 // opcode(0x8D);
5243 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5244 // ins_pipe(ialu_reg_reg_fat);
5245 // %}
5246
5247 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5248 %{
5249 match(Set dst mem);
5250
5251 ins_cost(110);
5252 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5253 opcode(0x8D);
5254 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5255 ins_pipe(ialu_reg_reg_fat);
5256 %}
5257
5258 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5259 %{
5260 match(Set dst mem);
5261
5262 ins_cost(110);
5263 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5264 opcode(0x8D);
5265 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5266 ins_pipe(ialu_reg_reg_fat);
5267 %}
5268
5269 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5270 %{
5271 match(Set dst mem);
5272
5273 ins_cost(110);
5274 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5275 opcode(0x8D);
5276 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5277 ins_pipe(ialu_reg_reg_fat);
5278 %}
5279
5280 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5281 %{
5282 match(Set dst mem);
5283
5284 ins_cost(110);
5285 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5286 opcode(0x8D);
5287 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5288 ins_pipe(ialu_reg_reg_fat);
5289 %}
5290
5291 // Load Effective Address which uses Narrow (32-bits) oop
5292 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5293 %{
5294 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5295 match(Set dst mem);
5296
5297 ins_cost(110);
5298 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5299 opcode(0x8D);
5300 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5301 ins_pipe(ialu_reg_reg_fat);
5302 %}
5303
5304 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5305 %{
5306 predicate(Universe::narrow_oop_shift() == 0);
5307 match(Set dst mem);
5308
5309 ins_cost(110); // XXX
5310 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5311 opcode(0x8D);
5312 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5313 ins_pipe(ialu_reg_reg_fat);
5314 %}
5315
5316 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5317 %{
5318 predicate(Universe::narrow_oop_shift() == 0);
5319 match(Set dst mem);
5320
5321 ins_cost(110);
5322 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5323 opcode(0x8D);
5324 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5325 ins_pipe(ialu_reg_reg_fat);
5326 %}
5327
5328 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5329 %{
5330 predicate(Universe::narrow_oop_shift() == 0);
5331 match(Set dst mem);
5332
5333 ins_cost(110);
5334 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5335 opcode(0x8D);
5336 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5337 ins_pipe(ialu_reg_reg_fat);
5338 %}
5339
5340 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5341 %{
5342 predicate(Universe::narrow_oop_shift() == 0);
5343 match(Set dst mem);
5344
5345 ins_cost(110);
5346 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5347 opcode(0x8D);
5348 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5349 ins_pipe(ialu_reg_reg_fat);
5350 %}
5351
5352 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5353 %{
5354 predicate(Universe::narrow_oop_shift() == 0);
5355 match(Set dst mem);
5356
5357 ins_cost(110);
5358 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5359 opcode(0x8D);
5360 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5361 ins_pipe(ialu_reg_reg_fat);
5362 %}
5363
5364 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5365 %{
5366 predicate(Universe::narrow_oop_shift() == 0);
5367 match(Set dst mem);
5368
5369 ins_cost(110);
5370 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5371 opcode(0x8D);
5372 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5373 ins_pipe(ialu_reg_reg_fat);
5374 %}
5375
5376 instruct loadConI(rRegI dst, immI src)
5377 %{
5378 match(Set dst src);
5379
5380 format %{ "movl $dst, $src\t# int" %}
5381 ins_encode(load_immI(dst, src));
5382 ins_pipe(ialu_reg_fat); // XXX
5383 %}
5384
5385 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5386 %{
5387 match(Set dst src);
5388 effect(KILL cr);
5389
5390 ins_cost(50);
5391 format %{ "xorl $dst, $dst\t# int" %}
5392 opcode(0x33); /* + rd */
5393 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5394 ins_pipe(ialu_reg);
5395 %}
5396
5397 instruct loadConL(rRegL dst, immL src)
5398 %{
5399 match(Set dst src);
5400
5401 ins_cost(150);
5402 format %{ "movq $dst, $src\t# long" %}
5403 ins_encode(load_immL(dst, src));
5404 ins_pipe(ialu_reg);
5405 %}
5406
5407 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5408 %{
5409 match(Set dst src);
5410 effect(KILL cr);
5411
5412 ins_cost(50);
5413 format %{ "xorl $dst, $dst\t# long" %}
5414 opcode(0x33); /* + rd */
5415 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5416 ins_pipe(ialu_reg); // XXX
5417 %}
5418
5419 instruct loadConUL32(rRegL dst, immUL32 src)
5420 %{
5421 match(Set dst src);
5422
5423 ins_cost(60);
5424 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5425 ins_encode(load_immUL32(dst, src));
5426 ins_pipe(ialu_reg);
5427 %}
5428
5429 instruct loadConL32(rRegL dst, immL32 src)
5430 %{
5431 match(Set dst src);
5432
5433 ins_cost(70);
5434 format %{ "movq $dst, $src\t# long (32-bit)" %}
5435 ins_encode(load_immL32(dst, src));
5436 ins_pipe(ialu_reg);
5437 %}
5438
5439 instruct loadConP(rRegP dst, immP con) %{
5440 match(Set dst con);
5441
5442 format %{ "movq $dst, $con\t# ptr" %}
5443 ins_encode(load_immP(dst, con));
5444 ins_pipe(ialu_reg_fat); // XXX
5445 %}
5446
5447 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5448 %{
5449 match(Set dst src);
5450 effect(KILL cr);
5451
5452 ins_cost(50);
5453 format %{ "xorl $dst, $dst\t# ptr" %}
5454 opcode(0x33); /* + rd */
5455 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5456 ins_pipe(ialu_reg);
5457 %}
5458
5459 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5460 %{
5461 match(Set dst src);
5462 effect(KILL cr);
5463
5464 ins_cost(60);
5465 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5466 ins_encode(load_immP31(dst, src));
5467 ins_pipe(ialu_reg);
5468 %}
5469
5470 instruct loadConF(regF dst, immF con) %{
5471 match(Set dst con);
5472 ins_cost(125);
5473 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5474 ins_encode %{
5475 __ movflt($dst$$XMMRegister, $constantaddress($con));
5476 %}
5477 ins_pipe(pipe_slow);
5478 %}
5479
5480 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5481 match(Set dst src);
5482 effect(KILL cr);
5483 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5484 ins_encode %{
5485 __ xorq($dst$$Register, $dst$$Register);
5486 %}
5487 ins_pipe(ialu_reg);
5488 %}
5489
5490 instruct loadConN(rRegN dst, immN src) %{
5491 match(Set dst src);
5492
5493 ins_cost(125);
5494 format %{ "movl $dst, $src\t# compressed ptr" %}
5495 ins_encode %{
5496 address con = (address)$src$$constant;
5497 if (con == NULL) {
5498 ShouldNotReachHere();
5499 } else {
5500 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5501 }
5502 %}
5503 ins_pipe(ialu_reg_fat); // XXX
5504 %}
5505
5506 instruct loadConF0(regF dst, immF0 src)
5507 %{
5508 match(Set dst src);
5509 ins_cost(100);
5510
5511 format %{ "xorps $dst, $dst\t# float 0.0" %}
5512 ins_encode %{
5513 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5514 %}
5515 ins_pipe(pipe_slow);
5516 %}
5517
5518 // Use the same format since predicate() can not be used here.
5519 instruct loadConD(regD dst, immD con) %{
5520 match(Set dst con);
5521 ins_cost(125);
5522 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5523 ins_encode %{
5524 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5525 %}
5526 ins_pipe(pipe_slow);
5527 %}
5528
5529 instruct loadConD0(regD dst, immD0 src)
5530 %{
5531 match(Set dst src);
5532 ins_cost(100);
5533
5534 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5535 ins_encode %{
5536 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5537 %}
5538 ins_pipe(pipe_slow);
5539 %}
5540
5541 instruct loadSSI(rRegI dst, stackSlotI src)
5542 %{
5543 match(Set dst src);
5544
5545 ins_cost(125);
5546 format %{ "movl $dst, $src\t# int stk" %}
5547 opcode(0x8B);
5548 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5549 ins_pipe(ialu_reg_mem);
5550 %}
5551
5552 instruct loadSSL(rRegL dst, stackSlotL src)
5553 %{
5554 match(Set dst src);
5555
5556 ins_cost(125);
5557 format %{ "movq $dst, $src\t# long stk" %}
5558 opcode(0x8B);
5559 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5560 ins_pipe(ialu_reg_mem);
5561 %}
5562
5563 instruct loadSSP(rRegP dst, stackSlotP src)
5564 %{
5565 match(Set dst src);
5566
5567 ins_cost(125);
5568 format %{ "movq $dst, $src\t# ptr stk" %}
5569 opcode(0x8B);
5570 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5571 ins_pipe(ialu_reg_mem);
5572 %}
5573
5574 instruct loadSSF(regF dst, stackSlotF src)
5575 %{
5576 match(Set dst src);
5577
5578 ins_cost(125);
5579 format %{ "movss $dst, $src\t# float stk" %}
5580 ins_encode %{
5581 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5582 %}
5583 ins_pipe(pipe_slow); // XXX
5584 %}
5585
5586 // Use the same format since predicate() can not be used here.
5587 instruct loadSSD(regD dst, stackSlotD src)
5588 %{
5589 match(Set dst src);
5590
5591 ins_cost(125);
5592 format %{ "movsd $dst, $src\t# double stk" %}
5593 ins_encode %{
5594 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5595 %}
5596 ins_pipe(pipe_slow); // XXX
5597 %}
5598
5599 // Prefetch instructions.
5600 // Must be safe to execute with invalid address (cannot fault).
5601
5602 instruct prefetchr( memory mem ) %{
5603 predicate(ReadPrefetchInstr==3);
5604 match(PrefetchRead mem);
5605 ins_cost(125);
5606
5607 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5608 ins_encode %{
5609 __ prefetchr($mem$$Address);
5610 %}
5611 ins_pipe(ialu_mem);
5612 %}
5613
5614 instruct prefetchrNTA( memory mem ) %{
5615 predicate(ReadPrefetchInstr==0);
5616 match(PrefetchRead mem);
5617 ins_cost(125);
5618
5619 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5620 ins_encode %{
5621 __ prefetchnta($mem$$Address);
5622 %}
5623 ins_pipe(ialu_mem);
5624 %}
5625
5626 instruct prefetchrT0( memory mem ) %{
5627 predicate(ReadPrefetchInstr==1);
5628 match(PrefetchRead mem);
5629 ins_cost(125);
5630
5631 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5632 ins_encode %{
5633 __ prefetcht0($mem$$Address);
5634 %}
5635 ins_pipe(ialu_mem);
5636 %}
5637
5638 instruct prefetchrT2( memory mem ) %{
5639 predicate(ReadPrefetchInstr==2);
5640 match(PrefetchRead mem);
5641 ins_cost(125);
5642
5643 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5644 ins_encode %{
5645 __ prefetcht2($mem$$Address);
5646 %}
5647 ins_pipe(ialu_mem);
5648 %}
5649
5650 instruct prefetchwNTA( memory mem ) %{
5651 match(PrefetchWrite mem);
5652 ins_cost(125);
5653
5654 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5655 ins_encode %{
5656 __ prefetchnta($mem$$Address);
5657 %}
5658 ins_pipe(ialu_mem);
5659 %}
5660
5661 // Prefetch instructions for allocation.
5662
5663 instruct prefetchAlloc( memory mem ) %{
5664 predicate(AllocatePrefetchInstr==3);
5665 match(PrefetchAllocation mem);
5666 ins_cost(125);
5667
5668 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5669 ins_encode %{
5670 __ prefetchw($mem$$Address);
5671 %}
5672 ins_pipe(ialu_mem);
5673 %}
5674
5675 instruct prefetchAllocNTA( memory mem ) %{
5676 predicate(AllocatePrefetchInstr==0);
5677 match(PrefetchAllocation mem);
5678 ins_cost(125);
5679
5680 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5681 ins_encode %{
5682 __ prefetchnta($mem$$Address);
5683 %}
5684 ins_pipe(ialu_mem);
5685 %}
5686
5687 instruct prefetchAllocT0( memory mem ) %{
5688 predicate(AllocatePrefetchInstr==1);
5689 match(PrefetchAllocation mem);
5690 ins_cost(125);
5691
5692 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5693 ins_encode %{
5694 __ prefetcht0($mem$$Address);
5695 %}
5696 ins_pipe(ialu_mem);
5697 %}
5698
5699 instruct prefetchAllocT2( memory mem ) %{
5700 predicate(AllocatePrefetchInstr==2);
5701 match(PrefetchAllocation mem);
5702 ins_cost(125);
5703
5704 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5705 ins_encode %{
5706 __ prefetcht2($mem$$Address);
5707 %}
5708 ins_pipe(ialu_mem);
5709 %}
5710
5711 //----------Store Instructions-------------------------------------------------
5712
5713 // Store Byte
5714 instruct storeB(memory mem, rRegI src)
5715 %{
5716 match(Set mem (StoreB mem src));
5717
5718 ins_cost(125); // XXX
5719 format %{ "movb $mem, $src\t# byte" %}
5720 opcode(0x88);
5721 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5722 ins_pipe(ialu_mem_reg);
5723 %}
5724
5725 // Store Char/Short
5726 instruct storeC(memory mem, rRegI src)
5727 %{
5728 match(Set mem (StoreC mem src));
5729
5730 ins_cost(125); // XXX
5731 format %{ "movw $mem, $src\t# char/short" %}
5732 opcode(0x89);
5733 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5734 ins_pipe(ialu_mem_reg);
5735 %}
5736
5737 // Store Integer
5738 instruct storeI(memory mem, rRegI src)
5739 %{
5740 match(Set mem (StoreI mem src));
5741
5742 ins_cost(125); // XXX
5743 format %{ "movl $mem, $src\t# int" %}
5744 opcode(0x89);
5745 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5746 ins_pipe(ialu_mem_reg);
5747 %}
5748
5749 // Store Long
5750 instruct storeL(memory mem, rRegL src)
5751 %{
5752 match(Set mem (StoreL mem src));
5753
5754 ins_cost(125); // XXX
5755 format %{ "movq $mem, $src\t# long" %}
5756 opcode(0x89);
5757 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5758 ins_pipe(ialu_mem_reg); // XXX
5759 %}
5760
5761 // Store Pointer
5762 instruct storeP(memory mem, any_RegP src)
5763 %{
5764 match(Set mem (StoreP mem src));
5765
5766 ins_cost(125); // XXX
5767 format %{ "movq $mem, $src\t# ptr" %}
5768 opcode(0x89);
5769 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5770 ins_pipe(ialu_mem_reg);
5771 %}
5772
5773 instruct storeImmP0(memory mem, immP0 zero)
5774 %{
5775 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5776 match(Set mem (StoreP mem zero));
5777
5778 ins_cost(125); // XXX
5779 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5780 ins_encode %{
5781 __ movq($mem$$Address, r12);
5782 %}
5783 ins_pipe(ialu_mem_reg);
5784 %}
5785
5786 // Store NULL Pointer, mark word, or other simple pointer constant.
5787 instruct storeImmP(memory mem, immP31 src)
5788 %{
5789 match(Set mem (StoreP mem src));
5790
5791 ins_cost(150); // XXX
5792 format %{ "movq $mem, $src\t# ptr" %}
5793 opcode(0xC7); /* C7 /0 */
5794 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5795 ins_pipe(ialu_mem_imm);
5796 %}
5797
5798 // Store Compressed Pointer
5799 instruct storeN(memory mem, rRegN src)
5800 %{
5801 match(Set mem (StoreN mem src));
5802
5803 ins_cost(125); // XXX
5804 format %{ "movl $mem, $src\t# compressed ptr" %}
5805 ins_encode %{
5806 __ movl($mem$$Address, $src$$Register);
5807 %}
5808 ins_pipe(ialu_mem_reg);
5809 %}
5810
5811 instruct storeImmN0(memory mem, immN0 zero)
5812 %{
5813 predicate(Universe::narrow_oop_base() == NULL);
5814 match(Set mem (StoreN mem zero));
5815
5816 ins_cost(125); // XXX
5817 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5818 ins_encode %{
5819 __ movl($mem$$Address, r12);
5820 %}
5821 ins_pipe(ialu_mem_reg);
5822 %}
5823
5824 instruct storeImmN(memory mem, immN src)
5825 %{
5826 match(Set mem (StoreN mem src));
5827
5828 ins_cost(150); // XXX
5829 format %{ "movl $mem, $src\t# compressed ptr" %}
5830 ins_encode %{
5831 address con = (address)$src$$constant;
5832 if (con == NULL) {
5833 __ movl($mem$$Address, (int32_t)0);
5834 } else {
5835 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5836 }
5837 %}
5838 ins_pipe(ialu_mem_imm);
5839 %}
5840
5841 // Store Integer Immediate
5842 instruct storeImmI0(memory mem, immI0 zero)
5843 %{
5844 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5845 match(Set mem (StoreI mem zero));
5846
5847 ins_cost(125); // XXX
5848 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5849 ins_encode %{
5850 __ movl($mem$$Address, r12);
5851 %}
5852 ins_pipe(ialu_mem_reg);
5853 %}
5854
5855 instruct storeImmI(memory mem, immI src)
5856 %{
5857 match(Set mem (StoreI mem src));
5858
5859 ins_cost(150);
5860 format %{ "movl $mem, $src\t# int" %}
5861 opcode(0xC7); /* C7 /0 */
5862 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5863 ins_pipe(ialu_mem_imm);
5864 %}
5865
5866 // Store Long Immediate
5867 instruct storeImmL0(memory mem, immL0 zero)
5868 %{
5869 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5870 match(Set mem (StoreL mem zero));
5871
5872 ins_cost(125); // XXX
5873 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5874 ins_encode %{
5875 __ movq($mem$$Address, r12);
5876 %}
5877 ins_pipe(ialu_mem_reg);
5878 %}
5879
5880 instruct storeImmL(memory mem, immL32 src)
5881 %{
5882 match(Set mem (StoreL mem src));
5883
5884 ins_cost(150);
5885 format %{ "movq $mem, $src\t# long" %}
5886 opcode(0xC7); /* C7 /0 */
5887 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5888 ins_pipe(ialu_mem_imm);
5889 %}
5890
5891 // Store Short/Char Immediate
5892 instruct storeImmC0(memory mem, immI0 zero)
5893 %{
5894 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5895 match(Set mem (StoreC mem zero));
5896
5897 ins_cost(125); // XXX
5898 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5899 ins_encode %{
5900 __ movw($mem$$Address, r12);
5901 %}
5902 ins_pipe(ialu_mem_reg);
5903 %}
5904
5905 instruct storeImmI16(memory mem, immI16 src)
5906 %{
5907 predicate(UseStoreImmI16);
5908 match(Set mem (StoreC mem src));
5909
5910 ins_cost(150);
5911 format %{ "movw $mem, $src\t# short/char" %}
5912 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5913 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5914 ins_pipe(ialu_mem_imm);
5915 %}
5916
5917 // Store Byte Immediate
5918 instruct storeImmB0(memory mem, immI0 zero)
5919 %{
5920 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5921 match(Set mem (StoreB mem zero));
5922
5923 ins_cost(125); // XXX
5924 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5925 ins_encode %{
5926 __ movb($mem$$Address, r12);
5927 %}
5928 ins_pipe(ialu_mem_reg);
5929 %}
5930
5931 instruct storeImmB(memory mem, immI8 src)
5932 %{
5933 match(Set mem (StoreB mem src));
5934
5935 ins_cost(150); // XXX
5936 format %{ "movb $mem, $src\t# byte" %}
5937 opcode(0xC6); /* C6 /0 */
5938 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5939 ins_pipe(ialu_mem_imm);
5940 %}
5941
5942 // Store CMS card-mark Immediate
5943 instruct storeImmCM0_reg(memory mem, immI0 zero)
5944 %{
5945 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5946 match(Set mem (StoreCM mem zero));
5947
5948 ins_cost(125); // XXX
5949 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5950 ins_encode %{
5951 __ movb($mem$$Address, r12);
5952 %}
5953 ins_pipe(ialu_mem_reg);
5954 %}
5955
5956 instruct storeImmCM0(memory mem, immI0 src)
5957 %{
5958 match(Set mem (StoreCM mem src));
5959
5960 ins_cost(150); // XXX
5961 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5962 opcode(0xC6); /* C6 /0 */
5963 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5964 ins_pipe(ialu_mem_imm);
5965 %}
5966
5967 // Store Float
5968 instruct storeF(memory mem, regF src)
5969 %{
5970 match(Set mem (StoreF mem src));
5971
5972 ins_cost(95); // XXX
5973 format %{ "movss $mem, $src\t# float" %}
5974 ins_encode %{
5975 __ movflt($mem$$Address, $src$$XMMRegister);
5976 %}
5977 ins_pipe(pipe_slow); // XXX
5978 %}
5979
5980 // Store immediate Float value (it is faster than store from XMM register)
5981 instruct storeF0(memory mem, immF0 zero)
5982 %{
5983 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5984 match(Set mem (StoreF mem zero));
5985
5986 ins_cost(25); // XXX
5987 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5988 ins_encode %{
5989 __ movl($mem$$Address, r12);
5990 %}
5991 ins_pipe(ialu_mem_reg);
5992 %}
5993
5994 instruct storeF_imm(memory mem, immF src)
5995 %{
5996 match(Set mem (StoreF mem src));
5997
5998 ins_cost(50);
5999 format %{ "movl $mem, $src\t# float" %}
6000 opcode(0xC7); /* C7 /0 */
6001 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6002 ins_pipe(ialu_mem_imm);
6003 %}
6004
6005 // Store Double
6006 instruct storeD(memory mem, regD src)
6007 %{
6008 match(Set mem (StoreD mem src));
6009
6010 ins_cost(95); // XXX
6011 format %{ "movsd $mem, $src\t# double" %}
6012 ins_encode %{
6013 __ movdbl($mem$$Address, $src$$XMMRegister);
6014 %}
6015 ins_pipe(pipe_slow); // XXX
6016 %}
6017
6018 // Store immediate double 0.0 (it is faster than store from XMM register)
6019 instruct storeD0_imm(memory mem, immD0 src)
6020 %{
6021 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6022 match(Set mem (StoreD mem src));
6023
6024 ins_cost(50);
6025 format %{ "movq $mem, $src\t# double 0." %}
6026 opcode(0xC7); /* C7 /0 */
6027 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6028 ins_pipe(ialu_mem_imm);
6029 %}
6030
6031 instruct storeD0(memory mem, immD0 zero)
6032 %{
6033 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6034 match(Set mem (StoreD mem zero));
6035
6036 ins_cost(25); // XXX
6037 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6038 ins_encode %{
6039 __ movq($mem$$Address, r12);
6040 %}
6041 ins_pipe(ialu_mem_reg);
6042 %}
6043
6044 instruct storeSSI(stackSlotI dst, rRegI src)
6045 %{
6046 match(Set dst src);
6047
6048 ins_cost(100);
6049 format %{ "movl $dst, $src\t# int stk" %}
6050 opcode(0x89);
6051 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6052 ins_pipe( ialu_mem_reg );
6053 %}
6054
6055 instruct storeSSL(stackSlotL dst, rRegL src)
6056 %{
6057 match(Set dst src);
6058
6059 ins_cost(100);
6060 format %{ "movq $dst, $src\t# long stk" %}
6061 opcode(0x89);
6062 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6063 ins_pipe(ialu_mem_reg);
6064 %}
6065
6066 instruct storeSSP(stackSlotP dst, rRegP src)
6067 %{
6068 match(Set dst src);
6069
6070 ins_cost(100);
6071 format %{ "movq $dst, $src\t# ptr stk" %}
6072 opcode(0x89);
6073 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6074 ins_pipe(ialu_mem_reg);
6075 %}
6076
6077 instruct storeSSF(stackSlotF dst, regF src)
6078 %{
6079 match(Set dst src);
6080
6081 ins_cost(95); // XXX
6082 format %{ "movss $dst, $src\t# float stk" %}
6083 ins_encode %{
6084 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6085 %}
6086 ins_pipe(pipe_slow); // XXX
6087 %}
6088
6089 instruct storeSSD(stackSlotD dst, regD src)
6090 %{
6091 match(Set dst src);
6092
6093 ins_cost(95); // XXX
6094 format %{ "movsd $dst, $src\t# double stk" %}
6095 ins_encode %{
6096 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6097 %}
6098 ins_pipe(pipe_slow); // XXX
6099 %}
6100
6101 //----------BSWAP Instructions-------------------------------------------------
6102 instruct bytes_reverse_int(rRegI dst) %{
6103 match(Set dst (ReverseBytesI dst));
6104
6105 format %{ "bswapl $dst" %}
6106 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6107 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6108 ins_pipe( ialu_reg );
6109 %}
6110
6111 instruct bytes_reverse_long(rRegL dst) %{
6112 match(Set dst (ReverseBytesL dst));
6113
6114 format %{ "bswapq $dst" %}
6115
6116 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6117 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6118 ins_pipe( ialu_reg);
6119 %}
6120
6121 instruct bytes_reverse_unsigned_short(rRegI dst) %{
6122 match(Set dst (ReverseBytesUS dst));
6123
6124 format %{ "bswapl $dst\n\t"
6125 "shrl $dst,16\n\t" %}
6126 ins_encode %{
6127 __ bswapl($dst$$Register);
6128 __ shrl($dst$$Register, 16);
6129 %}
6130 ins_pipe( ialu_reg );
6131 %}
6132
6133 instruct bytes_reverse_short(rRegI dst) %{
6134 match(Set dst (ReverseBytesS dst));
6135
6136 format %{ "bswapl $dst\n\t"
6137 "sar $dst,16\n\t" %}
6138 ins_encode %{
6139 __ bswapl($dst$$Register);
6140 __ sarl($dst$$Register, 16);
6141 %}
6142 ins_pipe( ialu_reg );
6143 %}
6144
6145 //---------- Zeros Count Instructions ------------------------------------------
6146
6147 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6148 predicate(UseCountLeadingZerosInstruction);
6149 match(Set dst (CountLeadingZerosI src));
6150 effect(KILL cr);
6151
6152 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6153 ins_encode %{
6154 __ lzcntl($dst$$Register, $src$$Register);
6155 %}
6156 ins_pipe(ialu_reg);
6157 %}
6158
6159 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6160 predicate(!UseCountLeadingZerosInstruction);
6161 match(Set dst (CountLeadingZerosI src));
6162 effect(KILL cr);
6163
6164 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6165 "jnz skip\n\t"
6166 "movl $dst, -1\n"
6167 "skip:\n\t"
6168 "negl $dst\n\t"
6169 "addl $dst, 31" %}
6170 ins_encode %{
6171 Register Rdst = $dst$$Register;
6172 Register Rsrc = $src$$Register;
6173 Label skip;
6174 __ bsrl(Rdst, Rsrc);
6175 __ jccb(Assembler::notZero, skip);
6176 __ movl(Rdst, -1);
6177 __ bind(skip);
6178 __ negl(Rdst);
6179 __ addl(Rdst, BitsPerInt - 1);
6180 %}
6181 ins_pipe(ialu_reg);
6182 %}
6183
6184 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6185 predicate(UseCountLeadingZerosInstruction);
6186 match(Set dst (CountLeadingZerosL src));
6187 effect(KILL cr);
6188
6189 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6190 ins_encode %{
6191 __ lzcntq($dst$$Register, $src$$Register);
6192 %}
6193 ins_pipe(ialu_reg);
6194 %}
6195
6196 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6197 predicate(!UseCountLeadingZerosInstruction);
6198 match(Set dst (CountLeadingZerosL src));
6199 effect(KILL cr);
6200
6201 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6202 "jnz skip\n\t"
6203 "movl $dst, -1\n"
6204 "skip:\n\t"
6205 "negl $dst\n\t"
6206 "addl $dst, 63" %}
6207 ins_encode %{
6208 Register Rdst = $dst$$Register;
6209 Register Rsrc = $src$$Register;
6210 Label skip;
6211 __ bsrq(Rdst, Rsrc);
6212 __ jccb(Assembler::notZero, skip);
6213 __ movl(Rdst, -1);
6214 __ bind(skip);
6215 __ negl(Rdst);
6216 __ addl(Rdst, BitsPerLong - 1);
6217 %}
6218 ins_pipe(ialu_reg);
6219 %}
6220
6221 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6222 match(Set dst (CountTrailingZerosI src));
6223 effect(KILL cr);
6224
6225 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6226 "jnz done\n\t"
6227 "movl $dst, 32\n"
6228 "done:" %}
6229 ins_encode %{
6230 Register Rdst = $dst$$Register;
6231 Label done;
6232 __ bsfl(Rdst, $src$$Register);
6233 __ jccb(Assembler::notZero, done);
6234 __ movl(Rdst, BitsPerInt);
6235 __ bind(done);
6236 %}
6237 ins_pipe(ialu_reg);
6238 %}
6239
6240 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6241 match(Set dst (CountTrailingZerosL src));
6242 effect(KILL cr);
6243
6244 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6245 "jnz done\n\t"
6246 "movl $dst, 64\n"
6247 "done:" %}
6248 ins_encode %{
6249 Register Rdst = $dst$$Register;
6250 Label done;
6251 __ bsfq(Rdst, $src$$Register);
6252 __ jccb(Assembler::notZero, done);
6253 __ movl(Rdst, BitsPerLong);
6254 __ bind(done);
6255 %}
6256 ins_pipe(ialu_reg);
6257 %}
6258
6259
6260 //---------- Population Count Instructions -------------------------------------
6261
6262 instruct popCountI(rRegI dst, rRegI src) %{
6263 predicate(UsePopCountInstruction);
6264 match(Set dst (PopCountI src));
6265
6266 format %{ "popcnt $dst, $src" %}
6267 ins_encode %{
6268 __ popcntl($dst$$Register, $src$$Register);
6269 %}
6270 ins_pipe(ialu_reg);
6271 %}
6272
6273 instruct popCountI_mem(rRegI dst, memory mem) %{
6274 predicate(UsePopCountInstruction);
6275 match(Set dst (PopCountI (LoadI mem)));
6276
6277 format %{ "popcnt $dst, $mem" %}
6278 ins_encode %{
6279 __ popcntl($dst$$Register, $mem$$Address);
6280 %}
6281 ins_pipe(ialu_reg);
6282 %}
6283
6284 // Note: Long.bitCount(long) returns an int.
6285 instruct popCountL(rRegI dst, rRegL src) %{
6286 predicate(UsePopCountInstruction);
6287 match(Set dst (PopCountL src));
6288
6289 format %{ "popcnt $dst, $src" %}
6290 ins_encode %{
6291 __ popcntq($dst$$Register, $src$$Register);
6292 %}
6293 ins_pipe(ialu_reg);
6294 %}
6295
6296 // Note: Long.bitCount(long) returns an int.
6297 instruct popCountL_mem(rRegI dst, memory mem) %{
6298 predicate(UsePopCountInstruction);
6299 match(Set dst (PopCountL (LoadL mem)));
6300
6301 format %{ "popcnt $dst, $mem" %}
6302 ins_encode %{
6303 __ popcntq($dst$$Register, $mem$$Address);
6304 %}
6305 ins_pipe(ialu_reg);
6306 %}
6307
6308
6309 //----------MemBar Instructions-----------------------------------------------
6310 // Memory barrier flavors
6311
6312 instruct membar_acquire()
6313 %{
6314 match(MemBarAcquire);
6315 ins_cost(0);
6316
6317 size(0);
6318 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6319 ins_encode();
6320 ins_pipe(empty);
6321 %}
6322
6323 instruct membar_acquire_lock()
6324 %{
6325 match(MemBarAcquireLock);
6326 ins_cost(0);
6327
6328 size(0);
6329 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6330 ins_encode();
6331 ins_pipe(empty);
6332 %}
6333
6334 instruct membar_release()
6335 %{
6336 match(MemBarRelease);
6337 ins_cost(0);
6338
6339 size(0);
6340 format %{ "MEMBAR-release ! (empty encoding)" %}
6341 ins_encode();
6342 ins_pipe(empty);
6343 %}
6344
6345 instruct membar_release_lock()
6346 %{
6347 match(MemBarReleaseLock);
6348 ins_cost(0);
6349
6350 size(0);
6351 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6352 ins_encode();
6353 ins_pipe(empty);
6354 %}
6355
6356 instruct membar_volatile(rFlagsReg cr) %{
6357 match(MemBarVolatile);
6358 effect(KILL cr);
6359 ins_cost(400);
6360
6361 format %{
6362 $$template
6363 if (os::is_MP()) {
6364 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6365 } else {
6366 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6367 }
6368 %}
6369 ins_encode %{
6370 __ membar(Assembler::StoreLoad);
6371 %}
6372 ins_pipe(pipe_slow);
6373 %}
6374
6375 instruct unnecessary_membar_volatile()
6376 %{
6377 match(MemBarVolatile);
6378 predicate(Matcher::post_store_load_barrier(n));
6379 ins_cost(0);
6380
6381 size(0);
6382 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6383 ins_encode();
6384 ins_pipe(empty);
6385 %}
6386
6387 instruct membar_storestore() %{
6388 match(MemBarStoreStore);
6389 ins_cost(0);
6390
6391 size(0);
6392 format %{ "MEMBAR-storestore (empty encoding)" %}
6393 ins_encode( );
6394 ins_pipe(empty);
6395 %}
6396
6397 //----------Move Instructions--------------------------------------------------
6398
6399 instruct castX2P(rRegP dst, rRegL src)
6400 %{
6401 match(Set dst (CastX2P src));
6402
6403 format %{ "movq $dst, $src\t# long->ptr" %}
6404 ins_encode %{
6405 if ($dst$$reg != $src$$reg) {
6406 __ movptr($dst$$Register, $src$$Register);
6407 }
6408 %}
6409 ins_pipe(ialu_reg_reg); // XXX
6410 %}
6411
6412 instruct castP2X(rRegL dst, rRegP src)
6413 %{
6414 match(Set dst (CastP2X src));
6415
6416 format %{ "movq $dst, $src\t# ptr -> long" %}
6417 ins_encode %{
6418 if ($dst$$reg != $src$$reg) {
6419 __ movptr($dst$$Register, $src$$Register);
6420 }
6421 %}
6422 ins_pipe(ialu_reg_reg); // XXX
6423 %}
6424
6425
6426 // Convert oop pointer into compressed form
6427 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6428 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6429 match(Set dst (EncodeP src));
6430 effect(KILL cr);
6431 format %{ "encode_heap_oop $dst,$src" %}
6432 ins_encode %{
6433 Register s = $src$$Register;
6434 Register d = $dst$$Register;
6435 if (s != d) {
6436 __ movq(d, s);
6437 }
6438 __ encode_heap_oop(d);
6439 %}
6440 ins_pipe(ialu_reg_long);
6441 %}
6442
6443 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6444 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6445 match(Set dst (EncodeP src));
6446 effect(KILL cr);
6447 format %{ "encode_heap_oop_not_null $dst,$src" %}
6448 ins_encode %{
6449 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6450 %}
6451 ins_pipe(ialu_reg_long);
6452 %}
6453
6454 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6455 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6456 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6457 match(Set dst (DecodeN src));
6458 effect(KILL cr);
6459 format %{ "decode_heap_oop $dst,$src" %}
6460 ins_encode %{
6461 Register s = $src$$Register;
6462 Register d = $dst$$Register;
6463 if (s != d) {
6464 __ movq(d, s);
6465 }
6466 __ decode_heap_oop(d);
6467 %}
6468 ins_pipe(ialu_reg_long);
6469 %}
6470
6471 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6472 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6473 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6474 match(Set dst (DecodeN src));
6475 effect(KILL cr);
6476 format %{ "decode_heap_oop_not_null $dst,$src" %}
6477 ins_encode %{
6478 Register s = $src$$Register;
6479 Register d = $dst$$Register;
6480 if (s != d) {
6481 __ decode_heap_oop_not_null(d, s);
6482 } else {
6483 __ decode_heap_oop_not_null(d);
6484 }
6485 %}
6486 ins_pipe(ialu_reg_long);
6487 %}
6488
6489
6490 //----------Conditional Move---------------------------------------------------
6491 // Jump
6492 // dummy instruction for generating temp registers
6493 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6494 match(Jump (LShiftL switch_val shift));
6495 ins_cost(350);
6496 predicate(false);
6497 effect(TEMP dest);
6498
6499 format %{ "leaq $dest, [$constantaddress]\n\t"
6500 "jmp [$dest + $switch_val << $shift]\n\t" %}
6501 ins_encode %{
6502 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6503 // to do that and the compiler is using that register as one it can allocate.
6504 // So we build it all by hand.
6505 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6506 // ArrayAddress dispatch(table, index);
6507 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6508 __ lea($dest$$Register, $constantaddress);
6509 __ jmp(dispatch);
6510 %}
6511 ins_pipe(pipe_jmp);
6512 %}
6513
6514 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6515 match(Jump (AddL (LShiftL switch_val shift) offset));
6516 ins_cost(350);
6517 effect(TEMP dest);
6518
6519 format %{ "leaq $dest, [$constantaddress]\n\t"
6520 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6521 ins_encode %{
6522 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6523 // to do that and the compiler is using that register as one it can allocate.
6524 // So we build it all by hand.
6525 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6526 // ArrayAddress dispatch(table, index);
6527 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6528 __ lea($dest$$Register, $constantaddress);
6529 __ jmp(dispatch);
6530 %}
6531 ins_pipe(pipe_jmp);
6532 %}
6533
6534 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6535 match(Jump switch_val);
6536 ins_cost(350);
6537 effect(TEMP dest);
6538
6539 format %{ "leaq $dest, [$constantaddress]\n\t"
6540 "jmp [$dest + $switch_val]\n\t" %}
6541 ins_encode %{
6542 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6543 // to do that and the compiler is using that register as one it can allocate.
6544 // So we build it all by hand.
6545 // Address index(noreg, switch_reg, Address::times_1);
6546 // ArrayAddress dispatch(table, index);
6547 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6548 __ lea($dest$$Register, $constantaddress);
6549 __ jmp(dispatch);
6550 %}
6551 ins_pipe(pipe_jmp);
6552 %}
6553
6554 // Conditional move
6555 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6556 %{
6557 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6558
6559 ins_cost(200); // XXX
6560 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6561 opcode(0x0F, 0x40);
6562 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6563 ins_pipe(pipe_cmov_reg);
6564 %}
6565
6566 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6567 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6568
6569 ins_cost(200); // XXX
6570 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6571 opcode(0x0F, 0x40);
6572 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6573 ins_pipe(pipe_cmov_reg);
6574 %}
6575
6576 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6577 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6578 ins_cost(200);
6579 expand %{
6580 cmovI_regU(cop, cr, dst, src);
6581 %}
6582 %}
6583
6584 // Conditional move
6585 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6586 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6587
6588 ins_cost(250); // XXX
6589 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6590 opcode(0x0F, 0x40);
6591 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6592 ins_pipe(pipe_cmov_mem);
6593 %}
6594
6595 // Conditional move
6596 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6597 %{
6598 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6599
6600 ins_cost(250); // XXX
6601 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6602 opcode(0x0F, 0x40);
6603 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6604 ins_pipe(pipe_cmov_mem);
6605 %}
6606
6607 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6608 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6609 ins_cost(250);
6610 expand %{
6611 cmovI_memU(cop, cr, dst, src);
6612 %}
6613 %}
6614
6615 // Conditional move
6616 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6617 %{
6618 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6619
6620 ins_cost(200); // XXX
6621 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6622 opcode(0x0F, 0x40);
6623 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6624 ins_pipe(pipe_cmov_reg);
6625 %}
6626
6627 // Conditional move
6628 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6629 %{
6630 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6631
6632 ins_cost(200); // XXX
6633 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6634 opcode(0x0F, 0x40);
6635 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6636 ins_pipe(pipe_cmov_reg);
6637 %}
6638
6639 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6640 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6641 ins_cost(200);
6642 expand %{
6643 cmovN_regU(cop, cr, dst, src);
6644 %}
6645 %}
6646
6647 // Conditional move
6648 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6649 %{
6650 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6651
6652 ins_cost(200); // XXX
6653 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6654 opcode(0x0F, 0x40);
6655 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6656 ins_pipe(pipe_cmov_reg); // XXX
6657 %}
6658
6659 // Conditional move
6660 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6661 %{
6662 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6663
6664 ins_cost(200); // XXX
6665 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6666 opcode(0x0F, 0x40);
6667 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6668 ins_pipe(pipe_cmov_reg); // XXX
6669 %}
6670
6671 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6672 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6673 ins_cost(200);
6674 expand %{
6675 cmovP_regU(cop, cr, dst, src);
6676 %}
6677 %}
6678
6679 // DISABLED: Requires the ADLC to emit a bottom_type call that
6680 // correctly meets the two pointer arguments; one is an incoming
6681 // register but the other is a memory operand. ALSO appears to
6682 // be buggy with implicit null checks.
6683 //
6684 //// Conditional move
6685 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6686 //%{
6687 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6688 // ins_cost(250);
6689 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6690 // opcode(0x0F,0x40);
6691 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6692 // ins_pipe( pipe_cmov_mem );
6693 //%}
6694 //
6695 //// Conditional move
6696 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6697 //%{
6698 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6699 // ins_cost(250);
6700 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6701 // opcode(0x0F,0x40);
6702 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6703 // ins_pipe( pipe_cmov_mem );
6704 //%}
6705
6706 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6707 %{
6708 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6709
6710 ins_cost(200); // XXX
6711 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6712 opcode(0x0F, 0x40);
6713 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6714 ins_pipe(pipe_cmov_reg); // XXX
6715 %}
6716
6717 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6718 %{
6719 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6720
6721 ins_cost(200); // XXX
6722 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6723 opcode(0x0F, 0x40);
6724 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6725 ins_pipe(pipe_cmov_mem); // XXX
6726 %}
6727
6728 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6729 %{
6730 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6731
6732 ins_cost(200); // XXX
6733 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6734 opcode(0x0F, 0x40);
6735 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6736 ins_pipe(pipe_cmov_reg); // XXX
6737 %}
6738
6739 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6740 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6741 ins_cost(200);
6742 expand %{
6743 cmovL_regU(cop, cr, dst, src);
6744 %}
6745 %}
6746
6747 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6748 %{
6749 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6750
6751 ins_cost(200); // XXX
6752 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6753 opcode(0x0F, 0x40);
6754 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6755 ins_pipe(pipe_cmov_mem); // XXX
6756 %}
6757
6758 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6759 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6760 ins_cost(200);
6761 expand %{
6762 cmovL_memU(cop, cr, dst, src);
6763 %}
6764 %}
6765
6766 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6767 %{
6768 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6769
6770 ins_cost(200); // XXX
6771 format %{ "jn$cop skip\t# signed cmove float\n\t"
6772 "movss $dst, $src\n"
6773 "skip:" %}
6774 ins_encode %{
6775 Label Lskip;
6776 // Invert sense of branch from sense of CMOV
6777 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6778 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6779 __ bind(Lskip);
6780 %}
6781 ins_pipe(pipe_slow);
6782 %}
6783
6784 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6785 // %{
6786 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6787
6788 // ins_cost(200); // XXX
6789 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6790 // "movss $dst, $src\n"
6791 // "skip:" %}
6792 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6793 // ins_pipe(pipe_slow);
6794 // %}
6795
6796 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6797 %{
6798 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6799
6800 ins_cost(200); // XXX
6801 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6802 "movss $dst, $src\n"
6803 "skip:" %}
6804 ins_encode %{
6805 Label Lskip;
6806 // Invert sense of branch from sense of CMOV
6807 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6808 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6809 __ bind(Lskip);
6810 %}
6811 ins_pipe(pipe_slow);
6812 %}
6813
6814 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6815 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6816 ins_cost(200);
6817 expand %{
6818 cmovF_regU(cop, cr, dst, src);
6819 %}
6820 %}
6821
6822 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6823 %{
6824 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6825
6826 ins_cost(200); // XXX
6827 format %{ "jn$cop skip\t# signed cmove double\n\t"
6828 "movsd $dst, $src\n"
6829 "skip:" %}
6830 ins_encode %{
6831 Label Lskip;
6832 // Invert sense of branch from sense of CMOV
6833 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6834 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6835 __ bind(Lskip);
6836 %}
6837 ins_pipe(pipe_slow);
6838 %}
6839
6840 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6841 %{
6842 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6843
6844 ins_cost(200); // XXX
6845 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6846 "movsd $dst, $src\n"
6847 "skip:" %}
6848 ins_encode %{
6849 Label Lskip;
6850 // Invert sense of branch from sense of CMOV
6851 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6852 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6853 __ bind(Lskip);
6854 %}
6855 ins_pipe(pipe_slow);
6856 %}
6857
6858 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6859 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6860 ins_cost(200);
6861 expand %{
6862 cmovD_regU(cop, cr, dst, src);
6863 %}
6864 %}
6865
6866 //----------Arithmetic Instructions--------------------------------------------
6867 //----------Addition Instructions----------------------------------------------
6868
6869 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6870 %{
6871 match(Set dst (AddI dst src));
6872 effect(KILL cr);
6873
6874 format %{ "addl $dst, $src\t# int" %}
6875 opcode(0x03);
6876 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6877 ins_pipe(ialu_reg_reg);
6878 %}
6879
6880 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6881 %{
6882 match(Set dst (AddI dst src));
6883 effect(KILL cr);
6884
6885 format %{ "addl $dst, $src\t# int" %}
6886 opcode(0x81, 0x00); /* /0 id */
6887 ins_encode(OpcSErm(dst, src), Con8or32(src));
6888 ins_pipe( ialu_reg );
6889 %}
6890
6891 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6892 %{
6893 match(Set dst (AddI dst (LoadI src)));
6894 effect(KILL cr);
6895
6896 ins_cost(125); // XXX
6897 format %{ "addl $dst, $src\t# int" %}
6898 opcode(0x03);
6899 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6900 ins_pipe(ialu_reg_mem);
6901 %}
6902
6903 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6904 %{
6905 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6906 effect(KILL cr);
6907
6908 ins_cost(150); // XXX
6909 format %{ "addl $dst, $src\t# int" %}
6910 opcode(0x01); /* Opcode 01 /r */
6911 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6912 ins_pipe(ialu_mem_reg);
6913 %}
6914
6915 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6916 %{
6917 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6918 effect(KILL cr);
6919
6920 ins_cost(125); // XXX
6921 format %{ "addl $dst, $src\t# int" %}
6922 opcode(0x81); /* Opcode 81 /0 id */
6923 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6924 ins_pipe(ialu_mem_imm);
6925 %}
6926
6927 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6928 %{
6929 predicate(UseIncDec);
6930 match(Set dst (AddI dst src));
6931 effect(KILL cr);
6932
6933 format %{ "incl $dst\t# int" %}
6934 opcode(0xFF, 0x00); // FF /0
6935 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6936 ins_pipe(ialu_reg);
6937 %}
6938
6939 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6940 %{
6941 predicate(UseIncDec);
6942 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6943 effect(KILL cr);
6944
6945 ins_cost(125); // XXX
6946 format %{ "incl $dst\t# int" %}
6947 opcode(0xFF); /* Opcode FF /0 */
6948 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6949 ins_pipe(ialu_mem_imm);
6950 %}
6951
6952 // XXX why does that use AddI
6953 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6954 %{
6955 predicate(UseIncDec);
6956 match(Set dst (AddI dst src));
6957 effect(KILL cr);
6958
6959 format %{ "decl $dst\t# int" %}
6960 opcode(0xFF, 0x01); // FF /1
6961 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6962 ins_pipe(ialu_reg);
6963 %}
6964
6965 // XXX why does that use AddI
6966 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6967 %{
6968 predicate(UseIncDec);
6969 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6970 effect(KILL cr);
6971
6972 ins_cost(125); // XXX
6973 format %{ "decl $dst\t# int" %}
6974 opcode(0xFF); /* Opcode FF /1 */
6975 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6976 ins_pipe(ialu_mem_imm);
6977 %}
6978
6979 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6980 %{
6981 match(Set dst (AddI src0 src1));
6982
6983 ins_cost(110);
6984 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6985 opcode(0x8D); /* 0x8D /r */
6986 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6987 ins_pipe(ialu_reg_reg);
6988 %}
6989
6990 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6991 %{
6992 match(Set dst (AddL dst src));
6993 effect(KILL cr);
6994
6995 format %{ "addq $dst, $src\t# long" %}
6996 opcode(0x03);
6997 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6998 ins_pipe(ialu_reg_reg);
6999 %}
7000
7001 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7002 %{
7003 match(Set dst (AddL dst src));
7004 effect(KILL cr);
7005
7006 format %{ "addq $dst, $src\t# long" %}
7007 opcode(0x81, 0x00); /* /0 id */
7008 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7009 ins_pipe( ialu_reg );
7010 %}
7011
7012 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7013 %{
7014 match(Set dst (AddL dst (LoadL src)));
7015 effect(KILL cr);
7016
7017 ins_cost(125); // XXX
7018 format %{ "addq $dst, $src\t# long" %}
7019 opcode(0x03);
7020 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7021 ins_pipe(ialu_reg_mem);
7022 %}
7023
7024 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7025 %{
7026 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7027 effect(KILL cr);
7028
7029 ins_cost(150); // XXX
7030 format %{ "addq $dst, $src\t# long" %}
7031 opcode(0x01); /* Opcode 01 /r */
7032 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7033 ins_pipe(ialu_mem_reg);
7034 %}
7035
7036 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7037 %{
7038 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7039 effect(KILL cr);
7040
7041 ins_cost(125); // XXX
7042 format %{ "addq $dst, $src\t# long" %}
7043 opcode(0x81); /* Opcode 81 /0 id */
7044 ins_encode(REX_mem_wide(dst),
7045 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7046 ins_pipe(ialu_mem_imm);
7047 %}
7048
7049 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7050 %{
7051 predicate(UseIncDec);
7052 match(Set dst (AddL dst src));
7053 effect(KILL cr);
7054
7055 format %{ "incq $dst\t# long" %}
7056 opcode(0xFF, 0x00); // FF /0
7057 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7058 ins_pipe(ialu_reg);
7059 %}
7060
7061 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7062 %{
7063 predicate(UseIncDec);
7064 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7065 effect(KILL cr);
7066
7067 ins_cost(125); // XXX
7068 format %{ "incq $dst\t# long" %}
7069 opcode(0xFF); /* Opcode FF /0 */
7070 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7071 ins_pipe(ialu_mem_imm);
7072 %}
7073
7074 // XXX why does that use AddL
7075 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7076 %{
7077 predicate(UseIncDec);
7078 match(Set dst (AddL dst src));
7079 effect(KILL cr);
7080
7081 format %{ "decq $dst\t# long" %}
7082 opcode(0xFF, 0x01); // FF /1
7083 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7084 ins_pipe(ialu_reg);
7085 %}
7086
7087 // XXX why does that use AddL
7088 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7089 %{
7090 predicate(UseIncDec);
7091 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7092 effect(KILL cr);
7093
7094 ins_cost(125); // XXX
7095 format %{ "decq $dst\t# long" %}
7096 opcode(0xFF); /* Opcode FF /1 */
7097 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7098 ins_pipe(ialu_mem_imm);
7099 %}
7100
7101 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7102 %{
7103 match(Set dst (AddL src0 src1));
7104
7105 ins_cost(110);
7106 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7107 opcode(0x8D); /* 0x8D /r */
7108 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7109 ins_pipe(ialu_reg_reg);
7110 %}
7111
7112 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7113 %{
7114 match(Set dst (AddP dst src));
7115 effect(KILL cr);
7116
7117 format %{ "addq $dst, $src\t# ptr" %}
7118 opcode(0x03);
7119 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7120 ins_pipe(ialu_reg_reg);
7121 %}
7122
7123 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7124 %{
7125 match(Set dst (AddP dst src));
7126 effect(KILL cr);
7127
7128 format %{ "addq $dst, $src\t# ptr" %}
7129 opcode(0x81, 0x00); /* /0 id */
7130 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7131 ins_pipe( ialu_reg );
7132 %}
7133
7134 // XXX addP mem ops ????
7135
7136 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7137 %{
7138 match(Set dst (AddP src0 src1));
7139
7140 ins_cost(110);
7141 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7142 opcode(0x8D); /* 0x8D /r */
7143 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7144 ins_pipe(ialu_reg_reg);
7145 %}
7146
7147 instruct checkCastPP(rRegP dst)
7148 %{
7149 match(Set dst (CheckCastPP dst));
7150
7151 size(0);
7152 format %{ "# checkcastPP of $dst" %}
7153 ins_encode(/* empty encoding */);
7154 ins_pipe(empty);
7155 %}
7156
7157 instruct castPP(rRegP dst)
7158 %{
7159 match(Set dst (CastPP dst));
7160
7161 size(0);
7162 format %{ "# castPP of $dst" %}
7163 ins_encode(/* empty encoding */);
7164 ins_pipe(empty);
7165 %}
7166
7167 instruct castII(rRegI dst)
7168 %{
7169 match(Set dst (CastII dst));
7170
7171 size(0);
7172 format %{ "# castII of $dst" %}
7173 ins_encode(/* empty encoding */);
7174 ins_cost(0);
7175 ins_pipe(empty);
7176 %}
7177
7178 // LoadP-locked same as a regular LoadP when used with compare-swap
7179 instruct loadPLocked(rRegP dst, memory mem)
7180 %{
7181 match(Set dst (LoadPLocked mem));
7182
7183 ins_cost(125); // XXX
7184 format %{ "movq $dst, $mem\t# ptr locked" %}
7185 opcode(0x8B);
7186 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7187 ins_pipe(ialu_reg_mem); // XXX
7188 %}
7189
7190 // LoadL-locked - same as a regular LoadL when used with compare-swap
7191 instruct loadLLocked(rRegL dst, memory mem)
7192 %{
7193 match(Set dst (LoadLLocked mem));
7194
7195 ins_cost(125); // XXX
7196 format %{ "movq $dst, $mem\t# long locked" %}
7197 opcode(0x8B);
7198 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7199 ins_pipe(ialu_reg_mem); // XXX
7200 %}
7201
7202 // Conditional-store of the updated heap-top.
7203 // Used during allocation of the shared heap.
7204 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7205
7206 instruct storePConditional(memory heap_top_ptr,
7207 rax_RegP oldval, rRegP newval,
7208 rFlagsReg cr)
7209 %{
7210 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7211
7212 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7213 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7214 opcode(0x0F, 0xB1);
7215 ins_encode(lock_prefix,
7216 REX_reg_mem_wide(newval, heap_top_ptr),
7217 OpcP, OpcS,
7218 reg_mem(newval, heap_top_ptr));
7219 ins_pipe(pipe_cmpxchg);
7220 %}
7221
7222 // Conditional-store of an int value.
7223 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7224 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7225 %{
7226 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7227 effect(KILL oldval);
7228
7229 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7230 opcode(0x0F, 0xB1);
7231 ins_encode(lock_prefix,
7232 REX_reg_mem(newval, mem),
7233 OpcP, OpcS,
7234 reg_mem(newval, mem));
7235 ins_pipe(pipe_cmpxchg);
7236 %}
7237
7238 // Conditional-store of a long value.
7239 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7240 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7241 %{
7242 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7243 effect(KILL oldval);
7244
7245 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7246 opcode(0x0F, 0xB1);
7247 ins_encode(lock_prefix,
7248 REX_reg_mem_wide(newval, mem),
7249 OpcP, OpcS,
7250 reg_mem(newval, mem));
7251 ins_pipe(pipe_cmpxchg);
7252 %}
7253
7254
7255 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7256 instruct compareAndSwapP(rRegI res,
7257 memory mem_ptr,
7258 rax_RegP oldval, rRegP newval,
7259 rFlagsReg cr)
7260 %{
7261 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7262 effect(KILL cr, KILL oldval);
7263
7264 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7265 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7266 "sete $res\n\t"
7267 "movzbl $res, $res" %}
7268 opcode(0x0F, 0xB1);
7269 ins_encode(lock_prefix,
7270 REX_reg_mem_wide(newval, mem_ptr),
7271 OpcP, OpcS,
7272 reg_mem(newval, mem_ptr),
7273 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7274 REX_reg_breg(res, res), // movzbl
7275 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7276 ins_pipe( pipe_cmpxchg );
7277 %}
7278
7279 instruct compareAndSwapL(rRegI res,
7280 memory mem_ptr,
7281 rax_RegL oldval, rRegL newval,
7282 rFlagsReg cr)
7283 %{
7284 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7285 effect(KILL cr, KILL oldval);
7286
7287 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7288 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7289 "sete $res\n\t"
7290 "movzbl $res, $res" %}
7291 opcode(0x0F, 0xB1);
7292 ins_encode(lock_prefix,
7293 REX_reg_mem_wide(newval, mem_ptr),
7294 OpcP, OpcS,
7295 reg_mem(newval, mem_ptr),
7296 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7297 REX_reg_breg(res, res), // movzbl
7298 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7299 ins_pipe( pipe_cmpxchg );
7300 %}
7301
7302 instruct compareAndSwapI(rRegI res,
7303 memory mem_ptr,
7304 rax_RegI oldval, rRegI newval,
7305 rFlagsReg cr)
7306 %{
7307 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7308 effect(KILL cr, KILL oldval);
7309
7310 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7311 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7312 "sete $res\n\t"
7313 "movzbl $res, $res" %}
7314 opcode(0x0F, 0xB1);
7315 ins_encode(lock_prefix,
7316 REX_reg_mem(newval, mem_ptr),
7317 OpcP, OpcS,
7318 reg_mem(newval, mem_ptr),
7319 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7320 REX_reg_breg(res, res), // movzbl
7321 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7322 ins_pipe( pipe_cmpxchg );
7323 %}
7324
7325
7326 instruct compareAndSwapN(rRegI res,
7327 memory mem_ptr,
7328 rax_RegN oldval, rRegN newval,
7329 rFlagsReg cr) %{
7330 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7331 effect(KILL cr, KILL oldval);
7332
7333 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7334 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7335 "sete $res\n\t"
7336 "movzbl $res, $res" %}
7337 opcode(0x0F, 0xB1);
7338 ins_encode(lock_prefix,
7339 REX_reg_mem(newval, mem_ptr),
7340 OpcP, OpcS,
7341 reg_mem(newval, mem_ptr),
7342 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7343 REX_reg_breg(res, res), // movzbl
7344 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7345 ins_pipe( pipe_cmpxchg );
7346 %}
7347
7348 //----------Subtraction Instructions-------------------------------------------
7349
7350 // Integer Subtraction Instructions
7351 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7352 %{
7353 match(Set dst (SubI dst src));
7354 effect(KILL cr);
7355
7356 format %{ "subl $dst, $src\t# int" %}
7357 opcode(0x2B);
7358 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7359 ins_pipe(ialu_reg_reg);
7360 %}
7361
7362 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7363 %{
7364 match(Set dst (SubI dst src));
7365 effect(KILL cr);
7366
7367 format %{ "subl $dst, $src\t# int" %}
7368 opcode(0x81, 0x05); /* Opcode 81 /5 */
7369 ins_encode(OpcSErm(dst, src), Con8or32(src));
7370 ins_pipe(ialu_reg);
7371 %}
7372
7373 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7374 %{
7375 match(Set dst (SubI dst (LoadI src)));
7376 effect(KILL cr);
7377
7378 ins_cost(125);
7379 format %{ "subl $dst, $src\t# int" %}
7380 opcode(0x2B);
7381 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7382 ins_pipe(ialu_reg_mem);
7383 %}
7384
7385 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7386 %{
7387 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7388 effect(KILL cr);
7389
7390 ins_cost(150);
7391 format %{ "subl $dst, $src\t# int" %}
7392 opcode(0x29); /* Opcode 29 /r */
7393 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7394 ins_pipe(ialu_mem_reg);
7395 %}
7396
7397 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7398 %{
7399 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7400 effect(KILL cr);
7401
7402 ins_cost(125); // XXX
7403 format %{ "subl $dst, $src\t# int" %}
7404 opcode(0x81); /* Opcode 81 /5 id */
7405 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7406 ins_pipe(ialu_mem_imm);
7407 %}
7408
7409 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7410 %{
7411 match(Set dst (SubL dst src));
7412 effect(KILL cr);
7413
7414 format %{ "subq $dst, $src\t# long" %}
7415 opcode(0x2B);
7416 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7417 ins_pipe(ialu_reg_reg);
7418 %}
7419
7420 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7421 %{
7422 match(Set dst (SubL dst src));
7423 effect(KILL cr);
7424
7425 format %{ "subq $dst, $src\t# long" %}
7426 opcode(0x81, 0x05); /* Opcode 81 /5 */
7427 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7428 ins_pipe(ialu_reg);
7429 %}
7430
7431 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7432 %{
7433 match(Set dst (SubL dst (LoadL src)));
7434 effect(KILL cr);
7435
7436 ins_cost(125);
7437 format %{ "subq $dst, $src\t# long" %}
7438 opcode(0x2B);
7439 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7440 ins_pipe(ialu_reg_mem);
7441 %}
7442
7443 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7444 %{
7445 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7446 effect(KILL cr);
7447
7448 ins_cost(150);
7449 format %{ "subq $dst, $src\t# long" %}
7450 opcode(0x29); /* Opcode 29 /r */
7451 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7452 ins_pipe(ialu_mem_reg);
7453 %}
7454
7455 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7456 %{
7457 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7458 effect(KILL cr);
7459
7460 ins_cost(125); // XXX
7461 format %{ "subq $dst, $src\t# long" %}
7462 opcode(0x81); /* Opcode 81 /5 id */
7463 ins_encode(REX_mem_wide(dst),
7464 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7465 ins_pipe(ialu_mem_imm);
7466 %}
7467
7468 // Subtract from a pointer
7469 // XXX hmpf???
7470 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7471 %{
7472 match(Set dst (AddP dst (SubI zero src)));
7473 effect(KILL cr);
7474
7475 format %{ "subq $dst, $src\t# ptr - int" %}
7476 opcode(0x2B);
7477 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7478 ins_pipe(ialu_reg_reg);
7479 %}
7480
7481 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7482 %{
7483 match(Set dst (SubI zero dst));
7484 effect(KILL cr);
7485
7486 format %{ "negl $dst\t# int" %}
7487 opcode(0xF7, 0x03); // Opcode F7 /3
7488 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7489 ins_pipe(ialu_reg);
7490 %}
7491
7492 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7493 %{
7494 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7495 effect(KILL cr);
7496
7497 format %{ "negl $dst\t# int" %}
7498 opcode(0xF7, 0x03); // Opcode F7 /3
7499 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7500 ins_pipe(ialu_reg);
7501 %}
7502
7503 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7504 %{
7505 match(Set dst (SubL zero dst));
7506 effect(KILL cr);
7507
7508 format %{ "negq $dst\t# long" %}
7509 opcode(0xF7, 0x03); // Opcode F7 /3
7510 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7511 ins_pipe(ialu_reg);
7512 %}
7513
7514 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7515 %{
7516 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7517 effect(KILL cr);
7518
7519 format %{ "negq $dst\t# long" %}
7520 opcode(0xF7, 0x03); // Opcode F7 /3
7521 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7522 ins_pipe(ialu_reg);
7523 %}
7524
7525
7526 //----------Multiplication/Division Instructions-------------------------------
7527 // Integer Multiplication Instructions
7528 // Multiply Register
7529
7530 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7531 %{
7532 match(Set dst (MulI dst src));
7533 effect(KILL cr);
7534
7535 ins_cost(300);
7536 format %{ "imull $dst, $src\t# int" %}
7537 opcode(0x0F, 0xAF);
7538 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7539 ins_pipe(ialu_reg_reg_alu0);
7540 %}
7541
7542 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7543 %{
7544 match(Set dst (MulI src imm));
7545 effect(KILL cr);
7546
7547 ins_cost(300);
7548 format %{ "imull $dst, $src, $imm\t# int" %}
7549 opcode(0x69); /* 69 /r id */
7550 ins_encode(REX_reg_reg(dst, src),
7551 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7552 ins_pipe(ialu_reg_reg_alu0);
7553 %}
7554
7555 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7556 %{
7557 match(Set dst (MulI dst (LoadI src)));
7558 effect(KILL cr);
7559
7560 ins_cost(350);
7561 format %{ "imull $dst, $src\t# int" %}
7562 opcode(0x0F, 0xAF);
7563 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7564 ins_pipe(ialu_reg_mem_alu0);
7565 %}
7566
7567 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7568 %{
7569 match(Set dst (MulI (LoadI src) imm));
7570 effect(KILL cr);
7571
7572 ins_cost(300);
7573 format %{ "imull $dst, $src, $imm\t# int" %}
7574 opcode(0x69); /* 69 /r id */
7575 ins_encode(REX_reg_mem(dst, src),
7576 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7577 ins_pipe(ialu_reg_mem_alu0);
7578 %}
7579
7580 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7581 %{
7582 match(Set dst (MulL dst src));
7583 effect(KILL cr);
7584
7585 ins_cost(300);
7586 format %{ "imulq $dst, $src\t# long" %}
7587 opcode(0x0F, 0xAF);
7588 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7589 ins_pipe(ialu_reg_reg_alu0);
7590 %}
7591
7592 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7593 %{
7594 match(Set dst (MulL src imm));
7595 effect(KILL cr);
7596
7597 ins_cost(300);
7598 format %{ "imulq $dst, $src, $imm\t# long" %}
7599 opcode(0x69); /* 69 /r id */
7600 ins_encode(REX_reg_reg_wide(dst, src),
7601 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7602 ins_pipe(ialu_reg_reg_alu0);
7603 %}
7604
7605 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7606 %{
7607 match(Set dst (MulL dst (LoadL src)));
7608 effect(KILL cr);
7609
7610 ins_cost(350);
7611 format %{ "imulq $dst, $src\t# long" %}
7612 opcode(0x0F, 0xAF);
7613 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7614 ins_pipe(ialu_reg_mem_alu0);
7615 %}
7616
7617 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7618 %{
7619 match(Set dst (MulL (LoadL src) imm));
7620 effect(KILL cr);
7621
7622 ins_cost(300);
7623 format %{ "imulq $dst, $src, $imm\t# long" %}
7624 opcode(0x69); /* 69 /r id */
7625 ins_encode(REX_reg_mem_wide(dst, src),
7626 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7627 ins_pipe(ialu_reg_mem_alu0);
7628 %}
7629
7630 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7631 %{
7632 match(Set dst (MulHiL src rax));
7633 effect(USE_KILL rax, KILL cr);
7634
7635 ins_cost(300);
7636 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7637 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7638 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7639 ins_pipe(ialu_reg_reg_alu0);
7640 %}
7641
7642 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7643 rFlagsReg cr)
7644 %{
7645 match(Set rax (DivI rax div));
7646 effect(KILL rdx, KILL cr);
7647
7648 ins_cost(30*100+10*100); // XXX
7649 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7650 "jne,s normal\n\t"
7651 "xorl rdx, rdx\n\t"
7652 "cmpl $div, -1\n\t"
7653 "je,s done\n"
7654 "normal: cdql\n\t"
7655 "idivl $div\n"
7656 "done:" %}
7657 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7658 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7659 ins_pipe(ialu_reg_reg_alu0);
7660 %}
7661
7662 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7663 rFlagsReg cr)
7664 %{
7665 match(Set rax (DivL rax div));
7666 effect(KILL rdx, KILL cr);
7667
7668 ins_cost(30*100+10*100); // XXX
7669 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7670 "cmpq rax, rdx\n\t"
7671 "jne,s normal\n\t"
7672 "xorl rdx, rdx\n\t"
7673 "cmpq $div, -1\n\t"
7674 "je,s done\n"
7675 "normal: cdqq\n\t"
7676 "idivq $div\n"
7677 "done:" %}
7678 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7679 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7680 ins_pipe(ialu_reg_reg_alu0);
7681 %}
7682
7683 // Integer DIVMOD with Register, both quotient and mod results
7684 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7685 rFlagsReg cr)
7686 %{
7687 match(DivModI rax div);
7688 effect(KILL cr);
7689
7690 ins_cost(30*100+10*100); // XXX
7691 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7692 "jne,s normal\n\t"
7693 "xorl rdx, rdx\n\t"
7694 "cmpl $div, -1\n\t"
7695 "je,s done\n"
7696 "normal: cdql\n\t"
7697 "idivl $div\n"
7698 "done:" %}
7699 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7700 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7701 ins_pipe(pipe_slow);
7702 %}
7703
7704 // Long DIVMOD with Register, both quotient and mod results
7705 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7706 rFlagsReg cr)
7707 %{
7708 match(DivModL rax div);
7709 effect(KILL cr);
7710
7711 ins_cost(30*100+10*100); // XXX
7712 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7713 "cmpq rax, rdx\n\t"
7714 "jne,s normal\n\t"
7715 "xorl rdx, rdx\n\t"
7716 "cmpq $div, -1\n\t"
7717 "je,s done\n"
7718 "normal: cdqq\n\t"
7719 "idivq $div\n"
7720 "done:" %}
7721 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7722 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7723 ins_pipe(pipe_slow);
7724 %}
7725
7726 //----------- DivL-By-Constant-Expansions--------------------------------------
7727 // DivI cases are handled by the compiler
7728
7729 // Magic constant, reciprocal of 10
7730 instruct loadConL_0x6666666666666667(rRegL dst)
7731 %{
7732 effect(DEF dst);
7733
7734 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7735 ins_encode(load_immL(dst, 0x6666666666666667));
7736 ins_pipe(ialu_reg);
7737 %}
7738
7739 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7740 %{
7741 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7742
7743 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7744 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7745 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7746 ins_pipe(ialu_reg_reg_alu0);
7747 %}
7748
7749 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7750 %{
7751 effect(USE_DEF dst, KILL cr);
7752
7753 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7754 opcode(0xC1, 0x7); /* C1 /7 ib */
7755 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7756 ins_pipe(ialu_reg);
7757 %}
7758
7759 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7760 %{
7761 effect(USE_DEF dst, KILL cr);
7762
7763 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7764 opcode(0xC1, 0x7); /* C1 /7 ib */
7765 ins_encode(reg_opc_imm_wide(dst, 0x2));
7766 ins_pipe(ialu_reg);
7767 %}
7768
7769 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7770 %{
7771 match(Set dst (DivL src div));
7772
7773 ins_cost((5+8)*100);
7774 expand %{
7775 rax_RegL rax; // Killed temp
7776 rFlagsReg cr; // Killed
7777 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7778 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7779 sarL_rReg_63(src, cr); // sarq src, 63
7780 sarL_rReg_2(dst, cr); // sarq rdx, 2
7781 subL_rReg(dst, src, cr); // subl rdx, src
7782 %}
7783 %}
7784
7785 //-----------------------------------------------------------------------------
7786
7787 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7788 rFlagsReg cr)
7789 %{
7790 match(Set rdx (ModI rax div));
7791 effect(KILL rax, KILL cr);
7792
7793 ins_cost(300); // XXX
7794 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7795 "jne,s normal\n\t"
7796 "xorl rdx, rdx\n\t"
7797 "cmpl $div, -1\n\t"
7798 "je,s done\n"
7799 "normal: cdql\n\t"
7800 "idivl $div\n"
7801 "done:" %}
7802 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7803 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7804 ins_pipe(ialu_reg_reg_alu0);
7805 %}
7806
7807 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7808 rFlagsReg cr)
7809 %{
7810 match(Set rdx (ModL rax div));
7811 effect(KILL rax, KILL cr);
7812
7813 ins_cost(300); // XXX
7814 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7815 "cmpq rax, rdx\n\t"
7816 "jne,s normal\n\t"
7817 "xorl rdx, rdx\n\t"
7818 "cmpq $div, -1\n\t"
7819 "je,s done\n"
7820 "normal: cdqq\n\t"
7821 "idivq $div\n"
7822 "done:" %}
7823 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7824 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7825 ins_pipe(ialu_reg_reg_alu0);
7826 %}
7827
7828 // Integer Shift Instructions
7829 // Shift Left by one
7830 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7831 %{
7832 match(Set dst (LShiftI dst shift));
7833 effect(KILL cr);
7834
7835 format %{ "sall $dst, $shift" %}
7836 opcode(0xD1, 0x4); /* D1 /4 */
7837 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7838 ins_pipe(ialu_reg);
7839 %}
7840
7841 // Shift Left by one
7842 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7843 %{
7844 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7845 effect(KILL cr);
7846
7847 format %{ "sall $dst, $shift\t" %}
7848 opcode(0xD1, 0x4); /* D1 /4 */
7849 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7850 ins_pipe(ialu_mem_imm);
7851 %}
7852
7853 // Shift Left by 8-bit immediate
7854 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7855 %{
7856 match(Set dst (LShiftI dst shift));
7857 effect(KILL cr);
7858
7859 format %{ "sall $dst, $shift" %}
7860 opcode(0xC1, 0x4); /* C1 /4 ib */
7861 ins_encode(reg_opc_imm(dst, shift));
7862 ins_pipe(ialu_reg);
7863 %}
7864
7865 // Shift Left by 8-bit immediate
7866 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7867 %{
7868 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7869 effect(KILL cr);
7870
7871 format %{ "sall $dst, $shift" %}
7872 opcode(0xC1, 0x4); /* C1 /4 ib */
7873 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7874 ins_pipe(ialu_mem_imm);
7875 %}
7876
7877 // Shift Left by variable
7878 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7879 %{
7880 match(Set dst (LShiftI dst shift));
7881 effect(KILL cr);
7882
7883 format %{ "sall $dst, $shift" %}
7884 opcode(0xD3, 0x4); /* D3 /4 */
7885 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7886 ins_pipe(ialu_reg_reg);
7887 %}
7888
7889 // Shift Left by variable
7890 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7891 %{
7892 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7893 effect(KILL cr);
7894
7895 format %{ "sall $dst, $shift" %}
7896 opcode(0xD3, 0x4); /* D3 /4 */
7897 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7898 ins_pipe(ialu_mem_reg);
7899 %}
7900
7901 // Arithmetic shift right by one
7902 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7903 %{
7904 match(Set dst (RShiftI dst shift));
7905 effect(KILL cr);
7906
7907 format %{ "sarl $dst, $shift" %}
7908 opcode(0xD1, 0x7); /* D1 /7 */
7909 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7910 ins_pipe(ialu_reg);
7911 %}
7912
7913 // Arithmetic shift right by one
7914 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7915 %{
7916 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7917 effect(KILL cr);
7918
7919 format %{ "sarl $dst, $shift" %}
7920 opcode(0xD1, 0x7); /* D1 /7 */
7921 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7922 ins_pipe(ialu_mem_imm);
7923 %}
7924
7925 // Arithmetic Shift Right by 8-bit immediate
7926 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7927 %{
7928 match(Set dst (RShiftI dst shift));
7929 effect(KILL cr);
7930
7931 format %{ "sarl $dst, $shift" %}
7932 opcode(0xC1, 0x7); /* C1 /7 ib */
7933 ins_encode(reg_opc_imm(dst, shift));
7934 ins_pipe(ialu_mem_imm);
7935 %}
7936
7937 // Arithmetic Shift Right by 8-bit immediate
7938 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7939 %{
7940 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7941 effect(KILL cr);
7942
7943 format %{ "sarl $dst, $shift" %}
7944 opcode(0xC1, 0x7); /* C1 /7 ib */
7945 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7946 ins_pipe(ialu_mem_imm);
7947 %}
7948
7949 // Arithmetic Shift Right by variable
7950 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7951 %{
7952 match(Set dst (RShiftI dst shift));
7953 effect(KILL cr);
7954
7955 format %{ "sarl $dst, $shift" %}
7956 opcode(0xD3, 0x7); /* D3 /7 */
7957 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7958 ins_pipe(ialu_reg_reg);
7959 %}
7960
7961 // Arithmetic Shift Right by variable
7962 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7963 %{
7964 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7965 effect(KILL cr);
7966
7967 format %{ "sarl $dst, $shift" %}
7968 opcode(0xD3, 0x7); /* D3 /7 */
7969 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7970 ins_pipe(ialu_mem_reg);
7971 %}
7972
7973 // Logical shift right by one
7974 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7975 %{
7976 match(Set dst (URShiftI dst shift));
7977 effect(KILL cr);
7978
7979 format %{ "shrl $dst, $shift" %}
7980 opcode(0xD1, 0x5); /* D1 /5 */
7981 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7982 ins_pipe(ialu_reg);
7983 %}
7984
7985 // Logical shift right by one
7986 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7987 %{
7988 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7989 effect(KILL cr);
7990
7991 format %{ "shrl $dst, $shift" %}
7992 opcode(0xD1, 0x5); /* D1 /5 */
7993 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7994 ins_pipe(ialu_mem_imm);
7995 %}
7996
7997 // Logical Shift Right by 8-bit immediate
7998 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7999 %{
8000 match(Set dst (URShiftI dst shift));
8001 effect(KILL cr);
8002
8003 format %{ "shrl $dst, $shift" %}
8004 opcode(0xC1, 0x5); /* C1 /5 ib */
8005 ins_encode(reg_opc_imm(dst, shift));
8006 ins_pipe(ialu_reg);
8007 %}
8008
8009 // Logical Shift Right by 8-bit immediate
8010 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8011 %{
8012 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8013 effect(KILL cr);
8014
8015 format %{ "shrl $dst, $shift" %}
8016 opcode(0xC1, 0x5); /* C1 /5 ib */
8017 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8018 ins_pipe(ialu_mem_imm);
8019 %}
8020
8021 // Logical Shift Right by variable
8022 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8023 %{
8024 match(Set dst (URShiftI dst shift));
8025 effect(KILL cr);
8026
8027 format %{ "shrl $dst, $shift" %}
8028 opcode(0xD3, 0x5); /* D3 /5 */
8029 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8030 ins_pipe(ialu_reg_reg);
8031 %}
8032
8033 // Logical Shift Right by variable
8034 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8035 %{
8036 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8037 effect(KILL cr);
8038
8039 format %{ "shrl $dst, $shift" %}
8040 opcode(0xD3, 0x5); /* D3 /5 */
8041 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8042 ins_pipe(ialu_mem_reg);
8043 %}
8044
8045 // Long Shift Instructions
8046 // Shift Left by one
8047 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8048 %{
8049 match(Set dst (LShiftL dst shift));
8050 effect(KILL cr);
8051
8052 format %{ "salq $dst, $shift" %}
8053 opcode(0xD1, 0x4); /* D1 /4 */
8054 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8055 ins_pipe(ialu_reg);
8056 %}
8057
8058 // Shift Left by one
8059 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8060 %{
8061 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8062 effect(KILL cr);
8063
8064 format %{ "salq $dst, $shift" %}
8065 opcode(0xD1, 0x4); /* D1 /4 */
8066 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8067 ins_pipe(ialu_mem_imm);
8068 %}
8069
8070 // Shift Left by 8-bit immediate
8071 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8072 %{
8073 match(Set dst (LShiftL dst shift));
8074 effect(KILL cr);
8075
8076 format %{ "salq $dst, $shift" %}
8077 opcode(0xC1, 0x4); /* C1 /4 ib */
8078 ins_encode(reg_opc_imm_wide(dst, shift));
8079 ins_pipe(ialu_reg);
8080 %}
8081
8082 // Shift Left by 8-bit immediate
8083 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8084 %{
8085 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8086 effect(KILL cr);
8087
8088 format %{ "salq $dst, $shift" %}
8089 opcode(0xC1, 0x4); /* C1 /4 ib */
8090 ins_encode(REX_mem_wide(dst), OpcP,
8091 RM_opc_mem(secondary, dst), Con8or32(shift));
8092 ins_pipe(ialu_mem_imm);
8093 %}
8094
8095 // Shift Left by variable
8096 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8097 %{
8098 match(Set dst (LShiftL dst shift));
8099 effect(KILL cr);
8100
8101 format %{ "salq $dst, $shift" %}
8102 opcode(0xD3, 0x4); /* D3 /4 */
8103 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8104 ins_pipe(ialu_reg_reg);
8105 %}
8106
8107 // Shift Left by variable
8108 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8109 %{
8110 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8111 effect(KILL cr);
8112
8113 format %{ "salq $dst, $shift" %}
8114 opcode(0xD3, 0x4); /* D3 /4 */
8115 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8116 ins_pipe(ialu_mem_reg);
8117 %}
8118
8119 // Arithmetic shift right by one
8120 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8121 %{
8122 match(Set dst (RShiftL dst shift));
8123 effect(KILL cr);
8124
8125 format %{ "sarq $dst, $shift" %}
8126 opcode(0xD1, 0x7); /* D1 /7 */
8127 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8128 ins_pipe(ialu_reg);
8129 %}
8130
8131 // Arithmetic shift right by one
8132 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8133 %{
8134 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8135 effect(KILL cr);
8136
8137 format %{ "sarq $dst, $shift" %}
8138 opcode(0xD1, 0x7); /* D1 /7 */
8139 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8140 ins_pipe(ialu_mem_imm);
8141 %}
8142
8143 // Arithmetic Shift Right by 8-bit immediate
8144 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8145 %{
8146 match(Set dst (RShiftL dst shift));
8147 effect(KILL cr);
8148
8149 format %{ "sarq $dst, $shift" %}
8150 opcode(0xC1, 0x7); /* C1 /7 ib */
8151 ins_encode(reg_opc_imm_wide(dst, shift));
8152 ins_pipe(ialu_mem_imm);
8153 %}
8154
8155 // Arithmetic Shift Right by 8-bit immediate
8156 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8157 %{
8158 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8159 effect(KILL cr);
8160
8161 format %{ "sarq $dst, $shift" %}
8162 opcode(0xC1, 0x7); /* C1 /7 ib */
8163 ins_encode(REX_mem_wide(dst), OpcP,
8164 RM_opc_mem(secondary, dst), Con8or32(shift));
8165 ins_pipe(ialu_mem_imm);
8166 %}
8167
8168 // Arithmetic Shift Right by variable
8169 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8170 %{
8171 match(Set dst (RShiftL dst shift));
8172 effect(KILL cr);
8173
8174 format %{ "sarq $dst, $shift" %}
8175 opcode(0xD3, 0x7); /* D3 /7 */
8176 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8177 ins_pipe(ialu_reg_reg);
8178 %}
8179
8180 // Arithmetic Shift Right by variable
8181 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8182 %{
8183 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8184 effect(KILL cr);
8185
8186 format %{ "sarq $dst, $shift" %}
8187 opcode(0xD3, 0x7); /* D3 /7 */
8188 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8189 ins_pipe(ialu_mem_reg);
8190 %}
8191
8192 // Logical shift right by one
8193 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8194 %{
8195 match(Set dst (URShiftL dst shift));
8196 effect(KILL cr);
8197
8198 format %{ "shrq $dst, $shift" %}
8199 opcode(0xD1, 0x5); /* D1 /5 */
8200 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8201 ins_pipe(ialu_reg);
8202 %}
8203
8204 // Logical shift right by one
8205 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8206 %{
8207 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8208 effect(KILL cr);
8209
8210 format %{ "shrq $dst, $shift" %}
8211 opcode(0xD1, 0x5); /* D1 /5 */
8212 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8213 ins_pipe(ialu_mem_imm);
8214 %}
8215
8216 // Logical Shift Right by 8-bit immediate
8217 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8218 %{
8219 match(Set dst (URShiftL dst shift));
8220 effect(KILL cr);
8221
8222 format %{ "shrq $dst, $shift" %}
8223 opcode(0xC1, 0x5); /* C1 /5 ib */
8224 ins_encode(reg_opc_imm_wide(dst, shift));
8225 ins_pipe(ialu_reg);
8226 %}
8227
8228
8229 // Logical Shift Right by 8-bit immediate
8230 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8231 %{
8232 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8233 effect(KILL cr);
8234
8235 format %{ "shrq $dst, $shift" %}
8236 opcode(0xC1, 0x5); /* C1 /5 ib */
8237 ins_encode(REX_mem_wide(dst), OpcP,
8238 RM_opc_mem(secondary, dst), Con8or32(shift));
8239 ins_pipe(ialu_mem_imm);
8240 %}
8241
8242 // Logical Shift Right by variable
8243 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8244 %{
8245 match(Set dst (URShiftL dst shift));
8246 effect(KILL cr);
8247
8248 format %{ "shrq $dst, $shift" %}
8249 opcode(0xD3, 0x5); /* D3 /5 */
8250 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8251 ins_pipe(ialu_reg_reg);
8252 %}
8253
8254 // Logical Shift Right by variable
8255 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8256 %{
8257 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8258 effect(KILL cr);
8259
8260 format %{ "shrq $dst, $shift" %}
8261 opcode(0xD3, 0x5); /* D3 /5 */
8262 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8263 ins_pipe(ialu_mem_reg);
8264 %}
8265
8266 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8267 // This idiom is used by the compiler for the i2b bytecode.
8268 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8269 %{
8270 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8271
8272 format %{ "movsbl $dst, $src\t# i2b" %}
8273 opcode(0x0F, 0xBE);
8274 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8275 ins_pipe(ialu_reg_reg);
8276 %}
8277
8278 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8279 // This idiom is used by the compiler the i2s bytecode.
8280 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8281 %{
8282 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8283
8284 format %{ "movswl $dst, $src\t# i2s" %}
8285 opcode(0x0F, 0xBF);
8286 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8287 ins_pipe(ialu_reg_reg);
8288 %}
8289
8290 // ROL/ROR instructions
8291
8292 // ROL expand
8293 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8294 effect(KILL cr, USE_DEF dst);
8295
8296 format %{ "roll $dst" %}
8297 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8298 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8299 ins_pipe(ialu_reg);
8300 %}
8301
8302 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8303 effect(USE_DEF dst, USE shift, KILL cr);
8304
8305 format %{ "roll $dst, $shift" %}
8306 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8307 ins_encode( reg_opc_imm(dst, shift) );
8308 ins_pipe(ialu_reg);
8309 %}
8310
8311 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8312 %{
8313 effect(USE_DEF dst, USE shift, KILL cr);
8314
8315 format %{ "roll $dst, $shift" %}
8316 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8317 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8318 ins_pipe(ialu_reg_reg);
8319 %}
8320 // end of ROL expand
8321
8322 // Rotate Left by one
8323 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8324 %{
8325 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8326
8327 expand %{
8328 rolI_rReg_imm1(dst, cr);
8329 %}
8330 %}
8331
8332 // Rotate Left by 8-bit immediate
8333 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8334 %{
8335 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8336 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8337
8338 expand %{
8339 rolI_rReg_imm8(dst, lshift, cr);
8340 %}
8341 %}
8342
8343 // Rotate Left by variable
8344 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8345 %{
8346 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8347
8348 expand %{
8349 rolI_rReg_CL(dst, shift, cr);
8350 %}
8351 %}
8352
8353 // Rotate Left by variable
8354 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8355 %{
8356 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8357
8358 expand %{
8359 rolI_rReg_CL(dst, shift, cr);
8360 %}
8361 %}
8362
8363 // ROR expand
8364 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8365 %{
8366 effect(USE_DEF dst, KILL cr);
8367
8368 format %{ "rorl $dst" %}
8369 opcode(0xD1, 0x1); /* D1 /1 */
8370 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8371 ins_pipe(ialu_reg);
8372 %}
8373
8374 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8375 %{
8376 effect(USE_DEF dst, USE shift, KILL cr);
8377
8378 format %{ "rorl $dst, $shift" %}
8379 opcode(0xC1, 0x1); /* C1 /1 ib */
8380 ins_encode(reg_opc_imm(dst, shift));
8381 ins_pipe(ialu_reg);
8382 %}
8383
8384 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8385 %{
8386 effect(USE_DEF dst, USE shift, KILL cr);
8387
8388 format %{ "rorl $dst, $shift" %}
8389 opcode(0xD3, 0x1); /* D3 /1 */
8390 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8391 ins_pipe(ialu_reg_reg);
8392 %}
8393 // end of ROR expand
8394
8395 // Rotate Right by one
8396 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8397 %{
8398 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8399
8400 expand %{
8401 rorI_rReg_imm1(dst, cr);
8402 %}
8403 %}
8404
8405 // Rotate Right by 8-bit immediate
8406 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8407 %{
8408 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8409 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8410
8411 expand %{
8412 rorI_rReg_imm8(dst, rshift, cr);
8413 %}
8414 %}
8415
8416 // Rotate Right by variable
8417 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8418 %{
8419 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8420
8421 expand %{
8422 rorI_rReg_CL(dst, shift, cr);
8423 %}
8424 %}
8425
8426 // Rotate Right by variable
8427 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8428 %{
8429 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8430
8431 expand %{
8432 rorI_rReg_CL(dst, shift, cr);
8433 %}
8434 %}
8435
8436 // for long rotate
8437 // ROL expand
8438 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8439 effect(USE_DEF dst, KILL cr);
8440
8441 format %{ "rolq $dst" %}
8442 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8443 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8444 ins_pipe(ialu_reg);
8445 %}
8446
8447 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8448 effect(USE_DEF dst, USE shift, KILL cr);
8449
8450 format %{ "rolq $dst, $shift" %}
8451 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8452 ins_encode( reg_opc_imm_wide(dst, shift) );
8453 ins_pipe(ialu_reg);
8454 %}
8455
8456 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8457 %{
8458 effect(USE_DEF dst, USE shift, KILL cr);
8459
8460 format %{ "rolq $dst, $shift" %}
8461 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8462 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8463 ins_pipe(ialu_reg_reg);
8464 %}
8465 // end of ROL expand
8466
8467 // Rotate Left by one
8468 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8469 %{
8470 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8471
8472 expand %{
8473 rolL_rReg_imm1(dst, cr);
8474 %}
8475 %}
8476
8477 // Rotate Left by 8-bit immediate
8478 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8479 %{
8480 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8481 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8482
8483 expand %{
8484 rolL_rReg_imm8(dst, lshift, cr);
8485 %}
8486 %}
8487
8488 // Rotate Left by variable
8489 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8490 %{
8491 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8492
8493 expand %{
8494 rolL_rReg_CL(dst, shift, cr);
8495 %}
8496 %}
8497
8498 // Rotate Left by variable
8499 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8500 %{
8501 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8502
8503 expand %{
8504 rolL_rReg_CL(dst, shift, cr);
8505 %}
8506 %}
8507
8508 // ROR expand
8509 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8510 %{
8511 effect(USE_DEF dst, KILL cr);
8512
8513 format %{ "rorq $dst" %}
8514 opcode(0xD1, 0x1); /* D1 /1 */
8515 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8516 ins_pipe(ialu_reg);
8517 %}
8518
8519 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8520 %{
8521 effect(USE_DEF dst, USE shift, KILL cr);
8522
8523 format %{ "rorq $dst, $shift" %}
8524 opcode(0xC1, 0x1); /* C1 /1 ib */
8525 ins_encode(reg_opc_imm_wide(dst, shift));
8526 ins_pipe(ialu_reg);
8527 %}
8528
8529 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8530 %{
8531 effect(USE_DEF dst, USE shift, KILL cr);
8532
8533 format %{ "rorq $dst, $shift" %}
8534 opcode(0xD3, 0x1); /* D3 /1 */
8535 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8536 ins_pipe(ialu_reg_reg);
8537 %}
8538 // end of ROR expand
8539
8540 // Rotate Right by one
8541 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8542 %{
8543 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8544
8545 expand %{
8546 rorL_rReg_imm1(dst, cr);
8547 %}
8548 %}
8549
8550 // Rotate Right by 8-bit immediate
8551 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8552 %{
8553 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8554 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8555
8556 expand %{
8557 rorL_rReg_imm8(dst, rshift, cr);
8558 %}
8559 %}
8560
8561 // Rotate Right by variable
8562 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8563 %{
8564 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8565
8566 expand %{
8567 rorL_rReg_CL(dst, shift, cr);
8568 %}
8569 %}
8570
8571 // Rotate Right by variable
8572 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8573 %{
8574 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8575
8576 expand %{
8577 rorL_rReg_CL(dst, shift, cr);
8578 %}
8579 %}
8580
8581 // Logical Instructions
8582
8583 // Integer Logical Instructions
8584
8585 // And Instructions
8586 // And Register with Register
8587 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8588 %{
8589 match(Set dst (AndI dst src));
8590 effect(KILL cr);
8591
8592 format %{ "andl $dst, $src\t# int" %}
8593 opcode(0x23);
8594 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8595 ins_pipe(ialu_reg_reg);
8596 %}
8597
8598 // And Register with Immediate 255
8599 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8600 %{
8601 match(Set dst (AndI dst src));
8602
8603 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8604 opcode(0x0F, 0xB6);
8605 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8606 ins_pipe(ialu_reg);
8607 %}
8608
8609 // And Register with Immediate 255 and promote to long
8610 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8611 %{
8612 match(Set dst (ConvI2L (AndI src mask)));
8613
8614 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8615 opcode(0x0F, 0xB6);
8616 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8617 ins_pipe(ialu_reg);
8618 %}
8619
8620 // And Register with Immediate 65535
8621 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8622 %{
8623 match(Set dst (AndI dst src));
8624
8625 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8626 opcode(0x0F, 0xB7);
8627 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8628 ins_pipe(ialu_reg);
8629 %}
8630
8631 // And Register with Immediate 65535 and promote to long
8632 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8633 %{
8634 match(Set dst (ConvI2L (AndI src mask)));
8635
8636 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8637 opcode(0x0F, 0xB7);
8638 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8639 ins_pipe(ialu_reg);
8640 %}
8641
8642 // And Register with Immediate
8643 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8644 %{
8645 match(Set dst (AndI dst src));
8646 effect(KILL cr);
8647
8648 format %{ "andl $dst, $src\t# int" %}
8649 opcode(0x81, 0x04); /* Opcode 81 /4 */
8650 ins_encode(OpcSErm(dst, src), Con8or32(src));
8651 ins_pipe(ialu_reg);
8652 %}
8653
8654 // And Register with Memory
8655 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8656 %{
8657 match(Set dst (AndI dst (LoadI src)));
8658 effect(KILL cr);
8659
8660 ins_cost(125);
8661 format %{ "andl $dst, $src\t# int" %}
8662 opcode(0x23);
8663 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8664 ins_pipe(ialu_reg_mem);
8665 %}
8666
8667 // And Memory with Register
8668 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8669 %{
8670 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8671 effect(KILL cr);
8672
8673 ins_cost(150);
8674 format %{ "andl $dst, $src\t# int" %}
8675 opcode(0x21); /* Opcode 21 /r */
8676 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8677 ins_pipe(ialu_mem_reg);
8678 %}
8679
8680 // And Memory with Immediate
8681 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8682 %{
8683 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8684 effect(KILL cr);
8685
8686 ins_cost(125);
8687 format %{ "andl $dst, $src\t# int" %}
8688 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8689 ins_encode(REX_mem(dst), OpcSE(src),
8690 RM_opc_mem(secondary, dst), Con8or32(src));
8691 ins_pipe(ialu_mem_imm);
8692 %}
8693
8694 // Or Instructions
8695 // Or Register with Register
8696 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8697 %{
8698 match(Set dst (OrI dst src));
8699 effect(KILL cr);
8700
8701 format %{ "orl $dst, $src\t# int" %}
8702 opcode(0x0B);
8703 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8704 ins_pipe(ialu_reg_reg);
8705 %}
8706
8707 // Or Register with Immediate
8708 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8709 %{
8710 match(Set dst (OrI dst src));
8711 effect(KILL cr);
8712
8713 format %{ "orl $dst, $src\t# int" %}
8714 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8715 ins_encode(OpcSErm(dst, src), Con8or32(src));
8716 ins_pipe(ialu_reg);
8717 %}
8718
8719 // Or Register with Memory
8720 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8721 %{
8722 match(Set dst (OrI dst (LoadI src)));
8723 effect(KILL cr);
8724
8725 ins_cost(125);
8726 format %{ "orl $dst, $src\t# int" %}
8727 opcode(0x0B);
8728 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8729 ins_pipe(ialu_reg_mem);
8730 %}
8731
8732 // Or Memory with Register
8733 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8734 %{
8735 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8736 effect(KILL cr);
8737
8738 ins_cost(150);
8739 format %{ "orl $dst, $src\t# int" %}
8740 opcode(0x09); /* Opcode 09 /r */
8741 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8742 ins_pipe(ialu_mem_reg);
8743 %}
8744
8745 // Or Memory with Immediate
8746 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8747 %{
8748 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8749 effect(KILL cr);
8750
8751 ins_cost(125);
8752 format %{ "orl $dst, $src\t# int" %}
8753 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8754 ins_encode(REX_mem(dst), OpcSE(src),
8755 RM_opc_mem(secondary, dst), Con8or32(src));
8756 ins_pipe(ialu_mem_imm);
8757 %}
8758
8759 // Xor Instructions
8760 // Xor Register with Register
8761 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8762 %{
8763 match(Set dst (XorI dst src));
8764 effect(KILL cr);
8765
8766 format %{ "xorl $dst, $src\t# int" %}
8767 opcode(0x33);
8768 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8769 ins_pipe(ialu_reg_reg);
8770 %}
8771
8772 // Xor Register with Immediate -1
8773 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8774 match(Set dst (XorI dst imm));
8775
8776 format %{ "not $dst" %}
8777 ins_encode %{
8778 __ notl($dst$$Register);
8779 %}
8780 ins_pipe(ialu_reg);
8781 %}
8782
8783 // Xor Register with Immediate
8784 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8785 %{
8786 match(Set dst (XorI dst src));
8787 effect(KILL cr);
8788
8789 format %{ "xorl $dst, $src\t# int" %}
8790 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8791 ins_encode(OpcSErm(dst, src), Con8or32(src));
8792 ins_pipe(ialu_reg);
8793 %}
8794
8795 // Xor Register with Memory
8796 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8797 %{
8798 match(Set dst (XorI dst (LoadI src)));
8799 effect(KILL cr);
8800
8801 ins_cost(125);
8802 format %{ "xorl $dst, $src\t# int" %}
8803 opcode(0x33);
8804 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8805 ins_pipe(ialu_reg_mem);
8806 %}
8807
8808 // Xor Memory with Register
8809 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8810 %{
8811 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8812 effect(KILL cr);
8813
8814 ins_cost(150);
8815 format %{ "xorl $dst, $src\t# int" %}
8816 opcode(0x31); /* Opcode 31 /r */
8817 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8818 ins_pipe(ialu_mem_reg);
8819 %}
8820
8821 // Xor Memory with Immediate
8822 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8823 %{
8824 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8825 effect(KILL cr);
8826
8827 ins_cost(125);
8828 format %{ "xorl $dst, $src\t# int" %}
8829 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8830 ins_encode(REX_mem(dst), OpcSE(src),
8831 RM_opc_mem(secondary, dst), Con8or32(src));
8832 ins_pipe(ialu_mem_imm);
8833 %}
8834
8835
8836 // Long Logical Instructions
8837
8838 // And Instructions
8839 // And Register with Register
8840 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8841 %{
8842 match(Set dst (AndL dst src));
8843 effect(KILL cr);
8844
8845 format %{ "andq $dst, $src\t# long" %}
8846 opcode(0x23);
8847 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8848 ins_pipe(ialu_reg_reg);
8849 %}
8850
8851 // And Register with Immediate 255
8852 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8853 %{
8854 match(Set dst (AndL dst src));
8855
8856 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8857 opcode(0x0F, 0xB6);
8858 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8859 ins_pipe(ialu_reg);
8860 %}
8861
8862 // And Register with Immediate 65535
8863 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
8864 %{
8865 match(Set dst (AndL dst src));
8866
8867 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
8868 opcode(0x0F, 0xB7);
8869 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 // And Register with Immediate
8874 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8875 %{
8876 match(Set dst (AndL dst src));
8877 effect(KILL cr);
8878
8879 format %{ "andq $dst, $src\t# long" %}
8880 opcode(0x81, 0x04); /* Opcode 81 /4 */
8881 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8882 ins_pipe(ialu_reg);
8883 %}
8884
8885 // And Register with Memory
8886 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8887 %{
8888 match(Set dst (AndL dst (LoadL src)));
8889 effect(KILL cr);
8890
8891 ins_cost(125);
8892 format %{ "andq $dst, $src\t# long" %}
8893 opcode(0x23);
8894 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8895 ins_pipe(ialu_reg_mem);
8896 %}
8897
8898 // And Memory with Register
8899 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8900 %{
8901 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8902 effect(KILL cr);
8903
8904 ins_cost(150);
8905 format %{ "andq $dst, $src\t# long" %}
8906 opcode(0x21); /* Opcode 21 /r */
8907 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8908 ins_pipe(ialu_mem_reg);
8909 %}
8910
8911 // And Memory with Immediate
8912 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8913 %{
8914 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8915 effect(KILL cr);
8916
8917 ins_cost(125);
8918 format %{ "andq $dst, $src\t# long" %}
8919 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8920 ins_encode(REX_mem_wide(dst), OpcSE(src),
8921 RM_opc_mem(secondary, dst), Con8or32(src));
8922 ins_pipe(ialu_mem_imm);
8923 %}
8924
8925 // Or Instructions
8926 // Or Register with Register
8927 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8928 %{
8929 match(Set dst (OrL dst src));
8930 effect(KILL cr);
8931
8932 format %{ "orq $dst, $src\t# long" %}
8933 opcode(0x0B);
8934 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8935 ins_pipe(ialu_reg_reg);
8936 %}
8937
8938 // Use any_RegP to match R15 (TLS register) without spilling.
8939 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
8940 match(Set dst (OrL dst (CastP2X src)));
8941 effect(KILL cr);
8942
8943 format %{ "orq $dst, $src\t# long" %}
8944 opcode(0x0B);
8945 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8946 ins_pipe(ialu_reg_reg);
8947 %}
8948
8949
8950 // Or Register with Immediate
8951 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8952 %{
8953 match(Set dst (OrL dst src));
8954 effect(KILL cr);
8955
8956 format %{ "orq $dst, $src\t# long" %}
8957 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8958 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8959 ins_pipe(ialu_reg);
8960 %}
8961
8962 // Or Register with Memory
8963 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8964 %{
8965 match(Set dst (OrL dst (LoadL src)));
8966 effect(KILL cr);
8967
8968 ins_cost(125);
8969 format %{ "orq $dst, $src\t# long" %}
8970 opcode(0x0B);
8971 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8972 ins_pipe(ialu_reg_mem);
8973 %}
8974
8975 // Or Memory with Register
8976 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8977 %{
8978 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8979 effect(KILL cr);
8980
8981 ins_cost(150);
8982 format %{ "orq $dst, $src\t# long" %}
8983 opcode(0x09); /* Opcode 09 /r */
8984 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8985 ins_pipe(ialu_mem_reg);
8986 %}
8987
8988 // Or Memory with Immediate
8989 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8990 %{
8991 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8992 effect(KILL cr);
8993
8994 ins_cost(125);
8995 format %{ "orq $dst, $src\t# long" %}
8996 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8997 ins_encode(REX_mem_wide(dst), OpcSE(src),
8998 RM_opc_mem(secondary, dst), Con8or32(src));
8999 ins_pipe(ialu_mem_imm);
9000 %}
9001
9002 // Xor Instructions
9003 // Xor Register with Register
9004 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9005 %{
9006 match(Set dst (XorL dst src));
9007 effect(KILL cr);
9008
9009 format %{ "xorq $dst, $src\t# long" %}
9010 opcode(0x33);
9011 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9012 ins_pipe(ialu_reg_reg);
9013 %}
9014
9015 // Xor Register with Immediate -1
9016 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9017 match(Set dst (XorL dst imm));
9018
9019 format %{ "notq $dst" %}
9020 ins_encode %{
9021 __ notq($dst$$Register);
9022 %}
9023 ins_pipe(ialu_reg);
9024 %}
9025
9026 // Xor Register with Immediate
9027 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9028 %{
9029 match(Set dst (XorL dst src));
9030 effect(KILL cr);
9031
9032 format %{ "xorq $dst, $src\t# long" %}
9033 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9034 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9035 ins_pipe(ialu_reg);
9036 %}
9037
9038 // Xor Register with Memory
9039 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9040 %{
9041 match(Set dst (XorL dst (LoadL src)));
9042 effect(KILL cr);
9043
9044 ins_cost(125);
9045 format %{ "xorq $dst, $src\t# long" %}
9046 opcode(0x33);
9047 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9048 ins_pipe(ialu_reg_mem);
9049 %}
9050
9051 // Xor Memory with Register
9052 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9053 %{
9054 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9055 effect(KILL cr);
9056
9057 ins_cost(150);
9058 format %{ "xorq $dst, $src\t# long" %}
9059 opcode(0x31); /* Opcode 31 /r */
9060 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9061 ins_pipe(ialu_mem_reg);
9062 %}
9063
9064 // Xor Memory with Immediate
9065 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9066 %{
9067 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9068 effect(KILL cr);
9069
9070 ins_cost(125);
9071 format %{ "xorq $dst, $src\t# long" %}
9072 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9073 ins_encode(REX_mem_wide(dst), OpcSE(src),
9074 RM_opc_mem(secondary, dst), Con8or32(src));
9075 ins_pipe(ialu_mem_imm);
9076 %}
9077
9078 // Convert Int to Boolean
9079 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9080 %{
9081 match(Set dst (Conv2B src));
9082 effect(KILL cr);
9083
9084 format %{ "testl $src, $src\t# ci2b\n\t"
9085 "setnz $dst\n\t"
9086 "movzbl $dst, $dst" %}
9087 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9088 setNZ_reg(dst),
9089 REX_reg_breg(dst, dst), // movzbl
9090 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9091 ins_pipe(pipe_slow); // XXX
9092 %}
9093
9094 // Convert Pointer to Boolean
9095 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9096 %{
9097 match(Set dst (Conv2B src));
9098 effect(KILL cr);
9099
9100 format %{ "testq $src, $src\t# cp2b\n\t"
9101 "setnz $dst\n\t"
9102 "movzbl $dst, $dst" %}
9103 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9104 setNZ_reg(dst),
9105 REX_reg_breg(dst, dst), // movzbl
9106 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9107 ins_pipe(pipe_slow); // XXX
9108 %}
9109
9110 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9111 %{
9112 match(Set dst (CmpLTMask p q));
9113 effect(KILL cr);
9114
9115 ins_cost(400); // XXX
9116 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9117 "setlt $dst\n\t"
9118 "movzbl $dst, $dst\n\t"
9119 "negl $dst" %}
9120 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9121 setLT_reg(dst),
9122 REX_reg_breg(dst, dst), // movzbl
9123 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9124 neg_reg(dst));
9125 ins_pipe(pipe_slow);
9126 %}
9127
9128 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9129 %{
9130 match(Set dst (CmpLTMask dst zero));
9131 effect(KILL cr);
9132
9133 ins_cost(100); // XXX
9134 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9135 opcode(0xC1, 0x7); /* C1 /7 ib */
9136 ins_encode(reg_opc_imm(dst, 0x1F));
9137 ins_pipe(ialu_reg);
9138 %}
9139
9140
9141 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
9142 %{
9143 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9144 effect(TEMP tmp, KILL cr);
9145
9146 ins_cost(400); // XXX
9147 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9148 "sbbl $tmp, $tmp\n\t"
9149 "andl $tmp, $y\n\t"
9150 "addl $p, $tmp" %}
9151 ins_encode %{
9152 Register Rp = $p$$Register;
9153 Register Rq = $q$$Register;
9154 Register Ry = $y$$Register;
9155 Register Rt = $tmp$$Register;
9156 __ subl(Rp, Rq);
9157 __ sbbl(Rt, Rt);
9158 __ andl(Rt, Ry);
9159 __ addl(Rp, Rt);
9160 %}
9161 ins_pipe(pipe_cmplt);
9162 %}
9163
9164 //---------- FP Instructions------------------------------------------------
9165
9166 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9167 %{
9168 match(Set cr (CmpF src1 src2));
9169
9170 ins_cost(145);
9171 format %{ "ucomiss $src1, $src2\n\t"
9172 "jnp,s exit\n\t"
9173 "pushfq\t# saw NaN, set CF\n\t"
9174 "andq [rsp], #0xffffff2b\n\t"
9175 "popfq\n"
9176 "exit:" %}
9177 ins_encode %{
9178 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9179 emit_cmpfp_fixup(_masm);
9180 %}
9181 ins_pipe(pipe_slow);
9182 %}
9183
9184 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9185 match(Set cr (CmpF src1 src2));
9186
9187 ins_cost(100);
9188 format %{ "ucomiss $src1, $src2" %}
9189 ins_encode %{
9190 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9191 %}
9192 ins_pipe(pipe_slow);
9193 %}
9194
9195 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9196 %{
9197 match(Set cr (CmpF src1 (LoadF src2)));
9198
9199 ins_cost(145);
9200 format %{ "ucomiss $src1, $src2\n\t"
9201 "jnp,s exit\n\t"
9202 "pushfq\t# saw NaN, set CF\n\t"
9203 "andq [rsp], #0xffffff2b\n\t"
9204 "popfq\n"
9205 "exit:" %}
9206 ins_encode %{
9207 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9208 emit_cmpfp_fixup(_masm);
9209 %}
9210 ins_pipe(pipe_slow);
9211 %}
9212
9213 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9214 match(Set cr (CmpF src1 (LoadF src2)));
9215
9216 ins_cost(100);
9217 format %{ "ucomiss $src1, $src2" %}
9218 ins_encode %{
9219 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9220 %}
9221 ins_pipe(pipe_slow);
9222 %}
9223
9224 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9225 match(Set cr (CmpF src con));
9226
9227 ins_cost(145);
9228 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9229 "jnp,s exit\n\t"
9230 "pushfq\t# saw NaN, set CF\n\t"
9231 "andq [rsp], #0xffffff2b\n\t"
9232 "popfq\n"
9233 "exit:" %}
9234 ins_encode %{
9235 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9236 emit_cmpfp_fixup(_masm);
9237 %}
9238 ins_pipe(pipe_slow);
9239 %}
9240
9241 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9242 match(Set cr (CmpF src con));
9243 ins_cost(100);
9244 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9245 ins_encode %{
9246 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9247 %}
9248 ins_pipe(pipe_slow);
9249 %}
9250
9251 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9252 %{
9253 match(Set cr (CmpD src1 src2));
9254
9255 ins_cost(145);
9256 format %{ "ucomisd $src1, $src2\n\t"
9257 "jnp,s exit\n\t"
9258 "pushfq\t# saw NaN, set CF\n\t"
9259 "andq [rsp], #0xffffff2b\n\t"
9260 "popfq\n"
9261 "exit:" %}
9262 ins_encode %{
9263 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9264 emit_cmpfp_fixup(_masm);
9265 %}
9266 ins_pipe(pipe_slow);
9267 %}
9268
9269 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9270 match(Set cr (CmpD src1 src2));
9271
9272 ins_cost(100);
9273 format %{ "ucomisd $src1, $src2 test" %}
9274 ins_encode %{
9275 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9276 %}
9277 ins_pipe(pipe_slow);
9278 %}
9279
9280 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9281 %{
9282 match(Set cr (CmpD src1 (LoadD src2)));
9283
9284 ins_cost(145);
9285 format %{ "ucomisd $src1, $src2\n\t"
9286 "jnp,s exit\n\t"
9287 "pushfq\t# saw NaN, set CF\n\t"
9288 "andq [rsp], #0xffffff2b\n\t"
9289 "popfq\n"
9290 "exit:" %}
9291 ins_encode %{
9292 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9293 emit_cmpfp_fixup(_masm);
9294 %}
9295 ins_pipe(pipe_slow);
9296 %}
9297
9298 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9299 match(Set cr (CmpD src1 (LoadD src2)));
9300
9301 ins_cost(100);
9302 format %{ "ucomisd $src1, $src2" %}
9303 ins_encode %{
9304 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9305 %}
9306 ins_pipe(pipe_slow);
9307 %}
9308
9309 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9310 match(Set cr (CmpD src con));
9311
9312 ins_cost(145);
9313 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9314 "jnp,s exit\n\t"
9315 "pushfq\t# saw NaN, set CF\n\t"
9316 "andq [rsp], #0xffffff2b\n\t"
9317 "popfq\n"
9318 "exit:" %}
9319 ins_encode %{
9320 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9321 emit_cmpfp_fixup(_masm);
9322 %}
9323 ins_pipe(pipe_slow);
9324 %}
9325
9326 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9327 match(Set cr (CmpD src con));
9328 ins_cost(100);
9329 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9330 ins_encode %{
9331 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9332 %}
9333 ins_pipe(pipe_slow);
9334 %}
9335
9336 // Compare into -1,0,1
9337 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9338 %{
9339 match(Set dst (CmpF3 src1 src2));
9340 effect(KILL cr);
9341
9342 ins_cost(275);
9343 format %{ "ucomiss $src1, $src2\n\t"
9344 "movl $dst, #-1\n\t"
9345 "jp,s done\n\t"
9346 "jb,s done\n\t"
9347 "setne $dst\n\t"
9348 "movzbl $dst, $dst\n"
9349 "done:" %}
9350 ins_encode %{
9351 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9352 emit_cmpfp3(_masm, $dst$$Register);
9353 %}
9354 ins_pipe(pipe_slow);
9355 %}
9356
9357 // Compare into -1,0,1
9358 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9359 %{
9360 match(Set dst (CmpF3 src1 (LoadF src2)));
9361 effect(KILL cr);
9362
9363 ins_cost(275);
9364 format %{ "ucomiss $src1, $src2\n\t"
9365 "movl $dst, #-1\n\t"
9366 "jp,s done\n\t"
9367 "jb,s done\n\t"
9368 "setne $dst\n\t"
9369 "movzbl $dst, $dst\n"
9370 "done:" %}
9371 ins_encode %{
9372 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9373 emit_cmpfp3(_masm, $dst$$Register);
9374 %}
9375 ins_pipe(pipe_slow);
9376 %}
9377
9378 // Compare into -1,0,1
9379 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9380 match(Set dst (CmpF3 src con));
9381 effect(KILL cr);
9382
9383 ins_cost(275);
9384 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9385 "movl $dst, #-1\n\t"
9386 "jp,s done\n\t"
9387 "jb,s done\n\t"
9388 "setne $dst\n\t"
9389 "movzbl $dst, $dst\n"
9390 "done:" %}
9391 ins_encode %{
9392 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9393 emit_cmpfp3(_masm, $dst$$Register);
9394 %}
9395 ins_pipe(pipe_slow);
9396 %}
9397
9398 // Compare into -1,0,1
9399 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9400 %{
9401 match(Set dst (CmpD3 src1 src2));
9402 effect(KILL cr);
9403
9404 ins_cost(275);
9405 format %{ "ucomisd $src1, $src2\n\t"
9406 "movl $dst, #-1\n\t"
9407 "jp,s done\n\t"
9408 "jb,s done\n\t"
9409 "setne $dst\n\t"
9410 "movzbl $dst, $dst\n"
9411 "done:" %}
9412 ins_encode %{
9413 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9414 emit_cmpfp3(_masm, $dst$$Register);
9415 %}
9416 ins_pipe(pipe_slow);
9417 %}
9418
9419 // Compare into -1,0,1
9420 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9421 %{
9422 match(Set dst (CmpD3 src1 (LoadD src2)));
9423 effect(KILL cr);
9424
9425 ins_cost(275);
9426 format %{ "ucomisd $src1, $src2\n\t"
9427 "movl $dst, #-1\n\t"
9428 "jp,s done\n\t"
9429 "jb,s done\n\t"
9430 "setne $dst\n\t"
9431 "movzbl $dst, $dst\n"
9432 "done:" %}
9433 ins_encode %{
9434 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9435 emit_cmpfp3(_masm, $dst$$Register);
9436 %}
9437 ins_pipe(pipe_slow);
9438 %}
9439
9440 // Compare into -1,0,1
9441 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9442 match(Set dst (CmpD3 src con));
9443 effect(KILL cr);
9444
9445 ins_cost(275);
9446 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9447 "movl $dst, #-1\n\t"
9448 "jp,s done\n\t"
9449 "jb,s done\n\t"
9450 "setne $dst\n\t"
9451 "movzbl $dst, $dst\n"
9452 "done:" %}
9453 ins_encode %{
9454 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9455 emit_cmpfp3(_masm, $dst$$Register);
9456 %}
9457 ins_pipe(pipe_slow);
9458 %}
9459
9460 // -----------Trig and Trancendental Instructions------------------------------
9461 instruct cosD_reg(regD dst) %{
9462 match(Set dst (CosD dst));
9463
9464 format %{ "dcos $dst\n\t" %}
9465 opcode(0xD9, 0xFF);
9466 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9467 ins_pipe( pipe_slow );
9468 %}
9469
9470 instruct sinD_reg(regD dst) %{
9471 match(Set dst (SinD dst));
9472
9473 format %{ "dsin $dst\n\t" %}
9474 opcode(0xD9, 0xFE);
9475 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9476 ins_pipe( pipe_slow );
9477 %}
9478
9479 instruct tanD_reg(regD dst) %{
9480 match(Set dst (TanD dst));
9481
9482 format %{ "dtan $dst\n\t" %}
9483 ins_encode( Push_SrcXD(dst),
9484 Opcode(0xD9), Opcode(0xF2), //fptan
9485 Opcode(0xDD), Opcode(0xD8), //fstp st
9486 Push_ResultXD(dst) );
9487 ins_pipe( pipe_slow );
9488 %}
9489
9490 instruct log10D_reg(regD dst) %{
9491 // The source and result Double operands in XMM registers
9492 match(Set dst (Log10D dst));
9493 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9494 // fyl2x ; compute log_10(2) * log_2(x)
9495 format %{ "fldlg2\t\t\t#Log10\n\t"
9496 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9497 %}
9498 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9499 Push_SrcXD(dst),
9500 Opcode(0xD9), Opcode(0xF1), // fyl2x
9501 Push_ResultXD(dst));
9502
9503 ins_pipe( pipe_slow );
9504 %}
9505
9506 instruct logD_reg(regD dst) %{
9507 // The source and result Double operands in XMM registers
9508 match(Set dst (LogD dst));
9509 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9510 // fyl2x ; compute log_e(2) * log_2(x)
9511 format %{ "fldln2\t\t\t#Log_e\n\t"
9512 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9513 %}
9514 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9515 Push_SrcXD(dst),
9516 Opcode(0xD9), Opcode(0xF1), // fyl2x
9517 Push_ResultXD(dst));
9518 ins_pipe( pipe_slow );
9519 %}
9520
9521 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9522 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9523 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9524 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9525 ins_encode %{
9526 __ subptr(rsp, 8);
9527 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9528 __ fld_d(Address(rsp, 0));
9529 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9530 __ fld_d(Address(rsp, 0));
9531 __ fast_pow();
9532 __ fstp_d(Address(rsp, 0));
9533 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9534 __ addptr(rsp, 8);
9535 %}
9536 ins_pipe( pipe_slow );
9537 %}
9538
9539 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9540 match(Set dst (ExpD src));
9541 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9542 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9543 ins_encode %{
9544 __ subptr(rsp, 8);
9545 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9546 __ fld_d(Address(rsp, 0));
9547 __ fast_exp();
9548 __ fstp_d(Address(rsp, 0));
9549 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9550 __ addptr(rsp, 8);
9551 %}
9552 ins_pipe( pipe_slow );
9553 %}
9554
9555 //----------Arithmetic Conversion Instructions---------------------------------
9556
9557 instruct roundFloat_nop(regF dst)
9558 %{
9559 match(Set dst (RoundFloat dst));
9560
9561 ins_cost(0);
9562 ins_encode();
9563 ins_pipe(empty);
9564 %}
9565
9566 instruct roundDouble_nop(regD dst)
9567 %{
9568 match(Set dst (RoundDouble dst));
9569
9570 ins_cost(0);
9571 ins_encode();
9572 ins_pipe(empty);
9573 %}
9574
9575 instruct convF2D_reg_reg(regD dst, regF src)
9576 %{
9577 match(Set dst (ConvF2D src));
9578
9579 format %{ "cvtss2sd $dst, $src" %}
9580 ins_encode %{
9581 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9582 %}
9583 ins_pipe(pipe_slow); // XXX
9584 %}
9585
9586 instruct convF2D_reg_mem(regD dst, memory src)
9587 %{
9588 match(Set dst (ConvF2D (LoadF src)));
9589
9590 format %{ "cvtss2sd $dst, $src" %}
9591 ins_encode %{
9592 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9593 %}
9594 ins_pipe(pipe_slow); // XXX
9595 %}
9596
9597 instruct convD2F_reg_reg(regF dst, regD src)
9598 %{
9599 match(Set dst (ConvD2F src));
9600
9601 format %{ "cvtsd2ss $dst, $src" %}
9602 ins_encode %{
9603 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9604 %}
9605 ins_pipe(pipe_slow); // XXX
9606 %}
9607
9608 instruct convD2F_reg_mem(regF dst, memory src)
9609 %{
9610 match(Set dst (ConvD2F (LoadD src)));
9611
9612 format %{ "cvtsd2ss $dst, $src" %}
9613 ins_encode %{
9614 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9615 %}
9616 ins_pipe(pipe_slow); // XXX
9617 %}
9618
9619 // XXX do mem variants
9620 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9621 %{
9622 match(Set dst (ConvF2I src));
9623 effect(KILL cr);
9624
9625 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9626 "cmpl $dst, #0x80000000\n\t"
9627 "jne,s done\n\t"
9628 "subq rsp, #8\n\t"
9629 "movss [rsp], $src\n\t"
9630 "call f2i_fixup\n\t"
9631 "popq $dst\n"
9632 "done: "%}
9633 ins_encode %{
9634 Label done;
9635 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9636 __ cmpl($dst$$Register, 0x80000000);
9637 __ jccb(Assembler::notEqual, done);
9638 __ subptr(rsp, 8);
9639 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9640 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9641 __ pop($dst$$Register);
9642 __ bind(done);
9643 %}
9644 ins_pipe(pipe_slow);
9645 %}
9646
9647 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9648 %{
9649 match(Set dst (ConvF2L src));
9650 effect(KILL cr);
9651
9652 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9653 "cmpq $dst, [0x8000000000000000]\n\t"
9654 "jne,s done\n\t"
9655 "subq rsp, #8\n\t"
9656 "movss [rsp], $src\n\t"
9657 "call f2l_fixup\n\t"
9658 "popq $dst\n"
9659 "done: "%}
9660 ins_encode %{
9661 Label done;
9662 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9663 __ cmp64($dst$$Register,
9664 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9665 __ jccb(Assembler::notEqual, done);
9666 __ subptr(rsp, 8);
9667 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9668 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9669 __ pop($dst$$Register);
9670 __ bind(done);
9671 %}
9672 ins_pipe(pipe_slow);
9673 %}
9674
9675 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9676 %{
9677 match(Set dst (ConvD2I src));
9678 effect(KILL cr);
9679
9680 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9681 "cmpl $dst, #0x80000000\n\t"
9682 "jne,s done\n\t"
9683 "subq rsp, #8\n\t"
9684 "movsd [rsp], $src\n\t"
9685 "call d2i_fixup\n\t"
9686 "popq $dst\n"
9687 "done: "%}
9688 ins_encode %{
9689 Label done;
9690 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9691 __ cmpl($dst$$Register, 0x80000000);
9692 __ jccb(Assembler::notEqual, done);
9693 __ subptr(rsp, 8);
9694 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9695 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9696 __ pop($dst$$Register);
9697 __ bind(done);
9698 %}
9699 ins_pipe(pipe_slow);
9700 %}
9701
9702 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9703 %{
9704 match(Set dst (ConvD2L src));
9705 effect(KILL cr);
9706
9707 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9708 "cmpq $dst, [0x8000000000000000]\n\t"
9709 "jne,s done\n\t"
9710 "subq rsp, #8\n\t"
9711 "movsd [rsp], $src\n\t"
9712 "call d2l_fixup\n\t"
9713 "popq $dst\n"
9714 "done: "%}
9715 ins_encode %{
9716 Label done;
9717 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
9718 __ cmp64($dst$$Register,
9719 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9720 __ jccb(Assembler::notEqual, done);
9721 __ subptr(rsp, 8);
9722 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9723 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9724 __ pop($dst$$Register);
9725 __ bind(done);
9726 %}
9727 ins_pipe(pipe_slow);
9728 %}
9729
9730 instruct convI2F_reg_reg(regF dst, rRegI src)
9731 %{
9732 predicate(!UseXmmI2F);
9733 match(Set dst (ConvI2F src));
9734
9735 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9736 ins_encode %{
9737 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
9738 %}
9739 ins_pipe(pipe_slow); // XXX
9740 %}
9741
9742 instruct convI2F_reg_mem(regF dst, memory src)
9743 %{
9744 match(Set dst (ConvI2F (LoadI src)));
9745
9746 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9747 ins_encode %{
9748 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
9749 %}
9750 ins_pipe(pipe_slow); // XXX
9751 %}
9752
9753 instruct convI2D_reg_reg(regD dst, rRegI src)
9754 %{
9755 predicate(!UseXmmI2D);
9756 match(Set dst (ConvI2D src));
9757
9758 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9759 ins_encode %{
9760 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
9761 %}
9762 ins_pipe(pipe_slow); // XXX
9763 %}
9764
9765 instruct convI2D_reg_mem(regD dst, memory src)
9766 %{
9767 match(Set dst (ConvI2D (LoadI src)));
9768
9769 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9770 ins_encode %{
9771 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
9772 %}
9773 ins_pipe(pipe_slow); // XXX
9774 %}
9775
9776 instruct convXI2F_reg(regF dst, rRegI src)
9777 %{
9778 predicate(UseXmmI2F);
9779 match(Set dst (ConvI2F src));
9780
9781 format %{ "movdl $dst, $src\n\t"
9782 "cvtdq2psl $dst, $dst\t# i2f" %}
9783 ins_encode %{
9784 __ movdl($dst$$XMMRegister, $src$$Register);
9785 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
9786 %}
9787 ins_pipe(pipe_slow); // XXX
9788 %}
9789
9790 instruct convXI2D_reg(regD dst, rRegI src)
9791 %{
9792 predicate(UseXmmI2D);
9793 match(Set dst (ConvI2D src));
9794
9795 format %{ "movdl $dst, $src\n\t"
9796 "cvtdq2pdl $dst, $dst\t# i2d" %}
9797 ins_encode %{
9798 __ movdl($dst$$XMMRegister, $src$$Register);
9799 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
9800 %}
9801 ins_pipe(pipe_slow); // XXX
9802 %}
9803
9804 instruct convL2F_reg_reg(regF dst, rRegL src)
9805 %{
9806 match(Set dst (ConvL2F src));
9807
9808 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9809 ins_encode %{
9810 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
9811 %}
9812 ins_pipe(pipe_slow); // XXX
9813 %}
9814
9815 instruct convL2F_reg_mem(regF dst, memory src)
9816 %{
9817 match(Set dst (ConvL2F (LoadL src)));
9818
9819 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9820 ins_encode %{
9821 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
9822 %}
9823 ins_pipe(pipe_slow); // XXX
9824 %}
9825
9826 instruct convL2D_reg_reg(regD dst, rRegL src)
9827 %{
9828 match(Set dst (ConvL2D src));
9829
9830 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9831 ins_encode %{
9832 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
9833 %}
9834 ins_pipe(pipe_slow); // XXX
9835 %}
9836
9837 instruct convL2D_reg_mem(regD dst, memory src)
9838 %{
9839 match(Set dst (ConvL2D (LoadL src)));
9840
9841 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9842 ins_encode %{
9843 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
9844 %}
9845 ins_pipe(pipe_slow); // XXX
9846 %}
9847
9848 instruct convI2L_reg_reg(rRegL dst, rRegI src)
9849 %{
9850 match(Set dst (ConvI2L src));
9851
9852 ins_cost(125);
9853 format %{ "movslq $dst, $src\t# i2l" %}
9854 ins_encode %{
9855 __ movslq($dst$$Register, $src$$Register);
9856 %}
9857 ins_pipe(ialu_reg_reg);
9858 %}
9859
9860 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
9861 // %{
9862 // match(Set dst (ConvI2L src));
9863 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
9864 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
9865 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
9866 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
9867 // ((const TypeNode*) n)->type()->is_long()->_lo ==
9868 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
9869
9870 // format %{ "movl $dst, $src\t# unsigned i2l" %}
9871 // ins_encode(enc_copy(dst, src));
9872 // // opcode(0x63); // needs REX.W
9873 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
9874 // ins_pipe(ialu_reg_reg);
9875 // %}
9876
9877 // Zero-extend convert int to long
9878 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
9879 %{
9880 match(Set dst (AndL (ConvI2L src) mask));
9881
9882 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9883 ins_encode %{
9884 if ($dst$$reg != $src$$reg) {
9885 __ movl($dst$$Register, $src$$Register);
9886 }
9887 %}
9888 ins_pipe(ialu_reg_reg);
9889 %}
9890
9891 // Zero-extend convert int to long
9892 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
9893 %{
9894 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
9895
9896 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9897 ins_encode %{
9898 __ movl($dst$$Register, $src$$Address);
9899 %}
9900 ins_pipe(ialu_reg_mem);
9901 %}
9902
9903 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
9904 %{
9905 match(Set dst (AndL src mask));
9906
9907 format %{ "movl $dst, $src\t# zero-extend long" %}
9908 ins_encode %{
9909 __ movl($dst$$Register, $src$$Register);
9910 %}
9911 ins_pipe(ialu_reg_reg);
9912 %}
9913
9914 instruct convL2I_reg_reg(rRegI dst, rRegL src)
9915 %{
9916 match(Set dst (ConvL2I src));
9917
9918 format %{ "movl $dst, $src\t# l2i" %}
9919 ins_encode %{
9920 __ movl($dst$$Register, $src$$Register);
9921 %}
9922 ins_pipe(ialu_reg_reg);
9923 %}
9924
9925
9926 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
9927 match(Set dst (MoveF2I src));
9928 effect(DEF dst, USE src);
9929
9930 ins_cost(125);
9931 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
9932 ins_encode %{
9933 __ movl($dst$$Register, Address(rsp, $src$$disp));
9934 %}
9935 ins_pipe(ialu_reg_mem);
9936 %}
9937
9938 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
9939 match(Set dst (MoveI2F src));
9940 effect(DEF dst, USE src);
9941
9942 ins_cost(125);
9943 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
9944 ins_encode %{
9945 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
9946 %}
9947 ins_pipe(pipe_slow);
9948 %}
9949
9950 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
9951 match(Set dst (MoveD2L src));
9952 effect(DEF dst, USE src);
9953
9954 ins_cost(125);
9955 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
9956 ins_encode %{
9957 __ movq($dst$$Register, Address(rsp, $src$$disp));
9958 %}
9959 ins_pipe(ialu_reg_mem);
9960 %}
9961
9962 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
9963 predicate(!UseXmmLoadAndClearUpper);
9964 match(Set dst (MoveL2D src));
9965 effect(DEF dst, USE src);
9966
9967 ins_cost(125);
9968 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
9969 ins_encode %{
9970 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9971 %}
9972 ins_pipe(pipe_slow);
9973 %}
9974
9975 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
9976 predicate(UseXmmLoadAndClearUpper);
9977 match(Set dst (MoveL2D src));
9978 effect(DEF dst, USE src);
9979
9980 ins_cost(125);
9981 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
9982 ins_encode %{
9983 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9984 %}
9985 ins_pipe(pipe_slow);
9986 %}
9987
9988
9989 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
9990 match(Set dst (MoveF2I src));
9991 effect(DEF dst, USE src);
9992
9993 ins_cost(95); // XXX
9994 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
9995 ins_encode %{
9996 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
9997 %}
9998 ins_pipe(pipe_slow);
9999 %}
10000
10001 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10002 match(Set dst (MoveI2F src));
10003 effect(DEF dst, USE src);
10004
10005 ins_cost(100);
10006 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10007 ins_encode %{
10008 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10009 %}
10010 ins_pipe( ialu_mem_reg );
10011 %}
10012
10013 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10014 match(Set dst (MoveD2L src));
10015 effect(DEF dst, USE src);
10016
10017 ins_cost(95); // XXX
10018 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10019 ins_encode %{
10020 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10021 %}
10022 ins_pipe(pipe_slow);
10023 %}
10024
10025 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10026 match(Set dst (MoveL2D src));
10027 effect(DEF dst, USE src);
10028
10029 ins_cost(100);
10030 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10031 ins_encode %{
10032 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10033 %}
10034 ins_pipe(ialu_mem_reg);
10035 %}
10036
10037 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10038 match(Set dst (MoveF2I src));
10039 effect(DEF dst, USE src);
10040 ins_cost(85);
10041 format %{ "movd $dst,$src\t# MoveF2I" %}
10042 ins_encode %{
10043 __ movdl($dst$$Register, $src$$XMMRegister);
10044 %}
10045 ins_pipe( pipe_slow );
10046 %}
10047
10048 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10049 match(Set dst (MoveD2L src));
10050 effect(DEF dst, USE src);
10051 ins_cost(85);
10052 format %{ "movd $dst,$src\t# MoveD2L" %}
10053 ins_encode %{
10054 __ movdq($dst$$Register, $src$$XMMRegister);
10055 %}
10056 ins_pipe( pipe_slow );
10057 %}
10058
10059 // The next instructions have long latency and use Int unit. Set high cost.
10060 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10061 match(Set dst (MoveI2F src));
10062 effect(DEF dst, USE src);
10063 ins_cost(300);
10064 format %{ "movd $dst,$src\t# MoveI2F" %}
10065 ins_encode %{
10066 __ movdl($dst$$XMMRegister, $src$$Register);
10067 %}
10068 ins_pipe( pipe_slow );
10069 %}
10070
10071 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10072 match(Set dst (MoveL2D src));
10073 effect(DEF dst, USE src);
10074 ins_cost(300);
10075 format %{ "movd $dst,$src\t# MoveL2D" %}
10076 ins_encode %{
10077 __ movdq($dst$$XMMRegister, $src$$Register);
10078 %}
10079 ins_pipe( pipe_slow );
10080 %}
10081
10082
10083 // =======================================================================
10084 // fast clearing of an array
10085 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10086 rFlagsReg cr)
10087 %{
10088 match(Set dummy (ClearArray cnt base));
10089 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10090
10091 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10092 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10093 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10094 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10095 ins_pipe(pipe_slow);
10096 %}
10097
10098 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10099 rax_RegI result, regD tmp1, rFlagsReg cr)
10100 %{
10101 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10102 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10103
10104 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10105 ins_encode %{
10106 __ string_compare($str1$$Register, $str2$$Register,
10107 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10108 $tmp1$$XMMRegister);
10109 %}
10110 ins_pipe( pipe_slow );
10111 %}
10112
10113 // fast search of substring with known size.
10114 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10115 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10116 %{
10117 predicate(UseSSE42Intrinsics);
10118 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10119 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10120
10121 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10122 ins_encode %{
10123 int icnt2 = (int)$int_cnt2$$constant;
10124 if (icnt2 >= 8) {
10125 // IndexOf for constant substrings with size >= 8 elements
10126 // which don't need to be loaded through stack.
10127 __ string_indexofC8($str1$$Register, $str2$$Register,
10128 $cnt1$$Register, $cnt2$$Register,
10129 icnt2, $result$$Register,
10130 $vec$$XMMRegister, $tmp$$Register);
10131 } else {
10132 // Small strings are loaded through stack if they cross page boundary.
10133 __ string_indexof($str1$$Register, $str2$$Register,
10134 $cnt1$$Register, $cnt2$$Register,
10135 icnt2, $result$$Register,
10136 $vec$$XMMRegister, $tmp$$Register);
10137 }
10138 %}
10139 ins_pipe( pipe_slow );
10140 %}
10141
10142 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10143 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10144 %{
10145 predicate(UseSSE42Intrinsics);
10146 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10147 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10148
10149 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10150 ins_encode %{
10151 __ string_indexof($str1$$Register, $str2$$Register,
10152 $cnt1$$Register, $cnt2$$Register,
10153 (-1), $result$$Register,
10154 $vec$$XMMRegister, $tmp$$Register);
10155 %}
10156 ins_pipe( pipe_slow );
10157 %}
10158
10159 // fast string equals
10160 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10161 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10162 %{
10163 match(Set result (StrEquals (Binary str1 str2) cnt));
10164 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10165
10166 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10167 ins_encode %{
10168 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10169 $cnt$$Register, $result$$Register, $tmp3$$Register,
10170 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10171 %}
10172 ins_pipe( pipe_slow );
10173 %}
10174
10175 // fast array equals
10176 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10177 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10178 %{
10179 match(Set result (AryEq ary1 ary2));
10180 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10181 //ins_cost(300);
10182
10183 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10184 ins_encode %{
10185 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10186 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10187 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10188 %}
10189 ins_pipe( pipe_slow );
10190 %}
10191
10192 //----------Control Flow Instructions------------------------------------------
10193 // Signed compare Instructions
10194
10195 // XXX more variants!!
10196 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10197 %{
10198 match(Set cr (CmpI op1 op2));
10199 effect(DEF cr, USE op1, USE op2);
10200
10201 format %{ "cmpl $op1, $op2" %}
10202 opcode(0x3B); /* Opcode 3B /r */
10203 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10204 ins_pipe(ialu_cr_reg_reg);
10205 %}
10206
10207 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10208 %{
10209 match(Set cr (CmpI op1 op2));
10210
10211 format %{ "cmpl $op1, $op2" %}
10212 opcode(0x81, 0x07); /* Opcode 81 /7 */
10213 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10214 ins_pipe(ialu_cr_reg_imm);
10215 %}
10216
10217 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10218 %{
10219 match(Set cr (CmpI op1 (LoadI op2)));
10220
10221 ins_cost(500); // XXX
10222 format %{ "cmpl $op1, $op2" %}
10223 opcode(0x3B); /* Opcode 3B /r */
10224 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10225 ins_pipe(ialu_cr_reg_mem);
10226 %}
10227
10228 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10229 %{
10230 match(Set cr (CmpI src zero));
10231
10232 format %{ "testl $src, $src" %}
10233 opcode(0x85);
10234 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10235 ins_pipe(ialu_cr_reg_imm);
10236 %}
10237
10238 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10239 %{
10240 match(Set cr (CmpI (AndI src con) zero));
10241
10242 format %{ "testl $src, $con" %}
10243 opcode(0xF7, 0x00);
10244 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10245 ins_pipe(ialu_cr_reg_imm);
10246 %}
10247
10248 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10249 %{
10250 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10251
10252 format %{ "testl $src, $mem" %}
10253 opcode(0x85);
10254 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10255 ins_pipe(ialu_cr_reg_mem);
10256 %}
10257
10258 // Unsigned compare Instructions; really, same as signed except they
10259 // produce an rFlagsRegU instead of rFlagsReg.
10260 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10261 %{
10262 match(Set cr (CmpU op1 op2));
10263
10264 format %{ "cmpl $op1, $op2\t# unsigned" %}
10265 opcode(0x3B); /* Opcode 3B /r */
10266 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10267 ins_pipe(ialu_cr_reg_reg);
10268 %}
10269
10270 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10271 %{
10272 match(Set cr (CmpU op1 op2));
10273
10274 format %{ "cmpl $op1, $op2\t# unsigned" %}
10275 opcode(0x81,0x07); /* Opcode 81 /7 */
10276 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10277 ins_pipe(ialu_cr_reg_imm);
10278 %}
10279
10280 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10281 %{
10282 match(Set cr (CmpU op1 (LoadI op2)));
10283
10284 ins_cost(500); // XXX
10285 format %{ "cmpl $op1, $op2\t# unsigned" %}
10286 opcode(0x3B); /* Opcode 3B /r */
10287 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10288 ins_pipe(ialu_cr_reg_mem);
10289 %}
10290
10291 // // // Cisc-spilled version of cmpU_rReg
10292 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10293 // //%{
10294 // // match(Set cr (CmpU (LoadI op1) op2));
10295 // //
10296 // // format %{ "CMPu $op1,$op2" %}
10297 // // ins_cost(500);
10298 // // opcode(0x39); /* Opcode 39 /r */
10299 // // ins_encode( OpcP, reg_mem( op1, op2) );
10300 // //%}
10301
10302 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10303 %{
10304 match(Set cr (CmpU src zero));
10305
10306 format %{ "testl $src, $src\t# unsigned" %}
10307 opcode(0x85);
10308 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10309 ins_pipe(ialu_cr_reg_imm);
10310 %}
10311
10312 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10313 %{
10314 match(Set cr (CmpP op1 op2));
10315
10316 format %{ "cmpq $op1, $op2\t# ptr" %}
10317 opcode(0x3B); /* Opcode 3B /r */
10318 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10319 ins_pipe(ialu_cr_reg_reg);
10320 %}
10321
10322 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10323 %{
10324 match(Set cr (CmpP op1 (LoadP op2)));
10325
10326 ins_cost(500); // XXX
10327 format %{ "cmpq $op1, $op2\t# ptr" %}
10328 opcode(0x3B); /* Opcode 3B /r */
10329 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10330 ins_pipe(ialu_cr_reg_mem);
10331 %}
10332
10333 // // // Cisc-spilled version of cmpP_rReg
10334 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10335 // //%{
10336 // // match(Set cr (CmpP (LoadP op1) op2));
10337 // //
10338 // // format %{ "CMPu $op1,$op2" %}
10339 // // ins_cost(500);
10340 // // opcode(0x39); /* Opcode 39 /r */
10341 // // ins_encode( OpcP, reg_mem( op1, op2) );
10342 // //%}
10343
10344 // XXX this is generalized by compP_rReg_mem???
10345 // Compare raw pointer (used in out-of-heap check).
10346 // Only works because non-oop pointers must be raw pointers
10347 // and raw pointers have no anti-dependencies.
10348 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10349 %{
10350 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
10351 match(Set cr (CmpP op1 (LoadP op2)));
10352
10353 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10354 opcode(0x3B); /* Opcode 3B /r */
10355 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10356 ins_pipe(ialu_cr_reg_mem);
10357 %}
10358
10359 // This will generate a signed flags result. This should be OK since
10360 // any compare to a zero should be eq/neq.
10361 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10362 %{
10363 match(Set cr (CmpP src zero));
10364
10365 format %{ "testq $src, $src\t# ptr" %}
10366 opcode(0x85);
10367 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10368 ins_pipe(ialu_cr_reg_imm);
10369 %}
10370
10371 // This will generate a signed flags result. This should be OK since
10372 // any compare to a zero should be eq/neq.
10373 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10374 %{
10375 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10376 match(Set cr (CmpP (LoadP op) zero));
10377
10378 ins_cost(500); // XXX
10379 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10380 opcode(0xF7); /* Opcode F7 /0 */
10381 ins_encode(REX_mem_wide(op),
10382 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10383 ins_pipe(ialu_cr_reg_imm);
10384 %}
10385
10386 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10387 %{
10388 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
10389 match(Set cr (CmpP (LoadP mem) zero));
10390
10391 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10392 ins_encode %{
10393 __ cmpq(r12, $mem$$Address);
10394 %}
10395 ins_pipe(ialu_cr_reg_mem);
10396 %}
10397
10398 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10399 %{
10400 match(Set cr (CmpN op1 op2));
10401
10402 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10403 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10404 ins_pipe(ialu_cr_reg_reg);
10405 %}
10406
10407 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10408 %{
10409 match(Set cr (CmpN src (LoadN mem)));
10410
10411 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10412 ins_encode %{
10413 __ cmpl($src$$Register, $mem$$Address);
10414 %}
10415 ins_pipe(ialu_cr_reg_mem);
10416 %}
10417
10418 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10419 match(Set cr (CmpN op1 op2));
10420
10421 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10422 ins_encode %{
10423 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10424 %}
10425 ins_pipe(ialu_cr_reg_imm);
10426 %}
10427
10428 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10429 %{
10430 match(Set cr (CmpN src (LoadN mem)));
10431
10432 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10433 ins_encode %{
10434 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10435 %}
10436 ins_pipe(ialu_cr_reg_mem);
10437 %}
10438
10439 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10440 match(Set cr (CmpN src zero));
10441
10442 format %{ "testl $src, $src\t# compressed ptr" %}
10443 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10444 ins_pipe(ialu_cr_reg_imm);
10445 %}
10446
10447 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10448 %{
10449 predicate(Universe::narrow_oop_base() != NULL);
10450 match(Set cr (CmpN (LoadN mem) zero));
10451
10452 ins_cost(500); // XXX
10453 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10454 ins_encode %{
10455 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10456 %}
10457 ins_pipe(ialu_cr_reg_mem);
10458 %}
10459
10460 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10461 %{
10462 predicate(Universe::narrow_oop_base() == NULL);
10463 match(Set cr (CmpN (LoadN mem) zero));
10464
10465 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10466 ins_encode %{
10467 __ cmpl(r12, $mem$$Address);
10468 %}
10469 ins_pipe(ialu_cr_reg_mem);
10470 %}
10471
10472 // Yanked all unsigned pointer compare operations.
10473 // Pointer compares are done with CmpP which is already unsigned.
10474
10475 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10476 %{
10477 match(Set cr (CmpL op1 op2));
10478
10479 format %{ "cmpq $op1, $op2" %}
10480 opcode(0x3B); /* Opcode 3B /r */
10481 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10482 ins_pipe(ialu_cr_reg_reg);
10483 %}
10484
10485 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10486 %{
10487 match(Set cr (CmpL op1 op2));
10488
10489 format %{ "cmpq $op1, $op2" %}
10490 opcode(0x81, 0x07); /* Opcode 81 /7 */
10491 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10492 ins_pipe(ialu_cr_reg_imm);
10493 %}
10494
10495 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10496 %{
10497 match(Set cr (CmpL op1 (LoadL op2)));
10498
10499 format %{ "cmpq $op1, $op2" %}
10500 opcode(0x3B); /* Opcode 3B /r */
10501 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10502 ins_pipe(ialu_cr_reg_mem);
10503 %}
10504
10505 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10506 %{
10507 match(Set cr (CmpL src zero));
10508
10509 format %{ "testq $src, $src" %}
10510 opcode(0x85);
10511 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10512 ins_pipe(ialu_cr_reg_imm);
10513 %}
10514
10515 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10516 %{
10517 match(Set cr (CmpL (AndL src con) zero));
10518
10519 format %{ "testq $src, $con\t# long" %}
10520 opcode(0xF7, 0x00);
10521 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10522 ins_pipe(ialu_cr_reg_imm);
10523 %}
10524
10525 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
10526 %{
10527 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
10528
10529 format %{ "testq $src, $mem" %}
10530 opcode(0x85);
10531 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
10532 ins_pipe(ialu_cr_reg_mem);
10533 %}
10534
10535 // Manifest a CmpL result in an integer register. Very painful.
10536 // This is the test to avoid.
10537 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10538 %{
10539 match(Set dst (CmpL3 src1 src2));
10540 effect(KILL flags);
10541
10542 ins_cost(275); // XXX
10543 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10544 "movl $dst, -1\n\t"
10545 "jl,s done\n\t"
10546 "setne $dst\n\t"
10547 "movzbl $dst, $dst\n\t"
10548 "done:" %}
10549 ins_encode(cmpl3_flag(src1, src2, dst));
10550 ins_pipe(pipe_slow);
10551 %}
10552
10553 //----------Max and Min--------------------------------------------------------
10554 // Min Instructions
10555
10556 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10557 %{
10558 effect(USE_DEF dst, USE src, USE cr);
10559
10560 format %{ "cmovlgt $dst, $src\t# min" %}
10561 opcode(0x0F, 0x4F);
10562 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10563 ins_pipe(pipe_cmov_reg);
10564 %}
10565
10566
10567 instruct minI_rReg(rRegI dst, rRegI src)
10568 %{
10569 match(Set dst (MinI dst src));
10570
10571 ins_cost(200);
10572 expand %{
10573 rFlagsReg cr;
10574 compI_rReg(cr, dst, src);
10575 cmovI_reg_g(dst, src, cr);
10576 %}
10577 %}
10578
10579 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
10580 %{
10581 effect(USE_DEF dst, USE src, USE cr);
10582
10583 format %{ "cmovllt $dst, $src\t# max" %}
10584 opcode(0x0F, 0x4C);
10585 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10586 ins_pipe(pipe_cmov_reg);
10587 %}
10588
10589
10590 instruct maxI_rReg(rRegI dst, rRegI src)
10591 %{
10592 match(Set dst (MaxI dst src));
10593
10594 ins_cost(200);
10595 expand %{
10596 rFlagsReg cr;
10597 compI_rReg(cr, dst, src);
10598 cmovI_reg_l(dst, src, cr);
10599 %}
10600 %}
10601
10602 // ============================================================================
10603 // Branch Instructions
10604
10605 // Jump Direct - Label defines a relative address from JMP+1
10606 instruct jmpDir(label labl)
10607 %{
10608 match(Goto);
10609 effect(USE labl);
10610
10611 ins_cost(300);
10612 format %{ "jmp $labl" %}
10613 size(5);
10614 ins_encode %{
10615 Label* L = $labl$$label;
10616 __ jmp(*L, false); // Always long jump
10617 %}
10618 ins_pipe(pipe_jmp);
10619 %}
10620
10621 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10622 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
10623 %{
10624 match(If cop cr);
10625 effect(USE labl);
10626
10627 ins_cost(300);
10628 format %{ "j$cop $labl" %}
10629 size(6);
10630 ins_encode %{
10631 Label* L = $labl$$label;
10632 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10633 %}
10634 ins_pipe(pipe_jcc);
10635 %}
10636
10637 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10638 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
10639 %{
10640 match(CountedLoopEnd cop cr);
10641 effect(USE labl);
10642
10643 ins_cost(300);
10644 format %{ "j$cop $labl\t# loop end" %}
10645 size(6);
10646 ins_encode %{
10647 Label* L = $labl$$label;
10648 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10649 %}
10650 ins_pipe(pipe_jcc);
10651 %}
10652
10653 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10654 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10655 match(CountedLoopEnd cop cmp);
10656 effect(USE labl);
10657
10658 ins_cost(300);
10659 format %{ "j$cop,u $labl\t# loop end" %}
10660 size(6);
10661 ins_encode %{
10662 Label* L = $labl$$label;
10663 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10664 %}
10665 ins_pipe(pipe_jcc);
10666 %}
10667
10668 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10669 match(CountedLoopEnd cop cmp);
10670 effect(USE labl);
10671
10672 ins_cost(200);
10673 format %{ "j$cop,u $labl\t# loop end" %}
10674 size(6);
10675 ins_encode %{
10676 Label* L = $labl$$label;
10677 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10678 %}
10679 ins_pipe(pipe_jcc);
10680 %}
10681
10682 // Jump Direct Conditional - using unsigned comparison
10683 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10684 match(If cop cmp);
10685 effect(USE labl);
10686
10687 ins_cost(300);
10688 format %{ "j$cop,u $labl" %}
10689 size(6);
10690 ins_encode %{
10691 Label* L = $labl$$label;
10692 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10693 %}
10694 ins_pipe(pipe_jcc);
10695 %}
10696
10697 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10698 match(If cop cmp);
10699 effect(USE labl);
10700
10701 ins_cost(200);
10702 format %{ "j$cop,u $labl" %}
10703 size(6);
10704 ins_encode %{
10705 Label* L = $labl$$label;
10706 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10707 %}
10708 ins_pipe(pipe_jcc);
10709 %}
10710
10711 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10712 match(If cop cmp);
10713 effect(USE labl);
10714
10715 ins_cost(200);
10716 format %{ $$template
10717 if ($cop$$cmpcode == Assembler::notEqual) {
10718 $$emit$$"jp,u $labl\n\t"
10719 $$emit$$"j$cop,u $labl"
10720 } else {
10721 $$emit$$"jp,u done\n\t"
10722 $$emit$$"j$cop,u $labl\n\t"
10723 $$emit$$"done:"
10724 }
10725 %}
10726 ins_encode %{
10727 Label* l = $labl$$label;
10728 if ($cop$$cmpcode == Assembler::notEqual) {
10729 __ jcc(Assembler::parity, *l, false);
10730 __ jcc(Assembler::notEqual, *l, false);
10731 } else if ($cop$$cmpcode == Assembler::equal) {
10732 Label done;
10733 __ jccb(Assembler::parity, done);
10734 __ jcc(Assembler::equal, *l, false);
10735 __ bind(done);
10736 } else {
10737 ShouldNotReachHere();
10738 }
10739 %}
10740 ins_pipe(pipe_jcc);
10741 %}
10742
10743 // ============================================================================
10744 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
10745 // superklass array for an instance of the superklass. Set a hidden
10746 // internal cache on a hit (cache is checked with exposed code in
10747 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
10748 // encoding ALSO sets flags.
10749
10750 instruct partialSubtypeCheck(rdi_RegP result,
10751 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10752 rFlagsReg cr)
10753 %{
10754 match(Set result (PartialSubtypeCheck sub super));
10755 effect(KILL rcx, KILL cr);
10756
10757 ins_cost(1100); // slightly larger than the next version
10758 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10759 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
10760 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
10761 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
10762 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
10763 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10764 "xorq $result, $result\t\t Hit: rdi zero\n\t"
10765 "miss:\t" %}
10766
10767 opcode(0x1); // Force a XOR of RDI
10768 ins_encode(enc_PartialSubtypeCheck());
10769 ins_pipe(pipe_slow);
10770 %}
10771
10772 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
10773 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10774 immP0 zero,
10775 rdi_RegP result)
10776 %{
10777 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10778 effect(KILL rcx, KILL result);
10779
10780 ins_cost(1000);
10781 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10782 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
10783 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
10784 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
10785 "jne,s miss\t\t# Missed: flags nz\n\t"
10786 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10787 "miss:\t" %}
10788
10789 opcode(0x0); // No need to XOR RDI
10790 ins_encode(enc_PartialSubtypeCheck());
10791 ins_pipe(pipe_slow);
10792 %}
10793
10794 // ============================================================================
10795 // Branch Instructions -- short offset versions
10796 //
10797 // These instructions are used to replace jumps of a long offset (the default
10798 // match) with jumps of a shorter offset. These instructions are all tagged
10799 // with the ins_short_branch attribute, which causes the ADLC to suppress the
10800 // match rules in general matching. Instead, the ADLC generates a conversion
10801 // method in the MachNode which can be used to do in-place replacement of the
10802 // long variant with the shorter variant. The compiler will determine if a
10803 // branch can be taken by the is_short_branch_offset() predicate in the machine
10804 // specific code section of the file.
10805
10806 // Jump Direct - Label defines a relative address from JMP+1
10807 instruct jmpDir_short(label labl) %{
10808 match(Goto);
10809 effect(USE labl);
10810
10811 ins_cost(300);
10812 format %{ "jmp,s $labl" %}
10813 size(2);
10814 ins_encode %{
10815 Label* L = $labl$$label;
10816 __ jmpb(*L);
10817 %}
10818 ins_pipe(pipe_jmp);
10819 ins_short_branch(1);
10820 %}
10821
10822 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10823 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
10824 match(If cop cr);
10825 effect(USE labl);
10826
10827 ins_cost(300);
10828 format %{ "j$cop,s $labl" %}
10829 size(2);
10830 ins_encode %{
10831 Label* L = $labl$$label;
10832 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10833 %}
10834 ins_pipe(pipe_jcc);
10835 ins_short_branch(1);
10836 %}
10837
10838 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10839 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
10840 match(CountedLoopEnd cop cr);
10841 effect(USE labl);
10842
10843 ins_cost(300);
10844 format %{ "j$cop,s $labl\t# loop end" %}
10845 size(2);
10846 ins_encode %{
10847 Label* L = $labl$$label;
10848 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10849 %}
10850 ins_pipe(pipe_jcc);
10851 ins_short_branch(1);
10852 %}
10853
10854 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10855 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10856 match(CountedLoopEnd cop cmp);
10857 effect(USE labl);
10858
10859 ins_cost(300);
10860 format %{ "j$cop,us $labl\t# loop end" %}
10861 size(2);
10862 ins_encode %{
10863 Label* L = $labl$$label;
10864 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10865 %}
10866 ins_pipe(pipe_jcc);
10867 ins_short_branch(1);
10868 %}
10869
10870 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10871 match(CountedLoopEnd cop cmp);
10872 effect(USE labl);
10873
10874 ins_cost(300);
10875 format %{ "j$cop,us $labl\t# loop end" %}
10876 size(2);
10877 ins_encode %{
10878 Label* L = $labl$$label;
10879 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10880 %}
10881 ins_pipe(pipe_jcc);
10882 ins_short_branch(1);
10883 %}
10884
10885 // Jump Direct Conditional - using unsigned comparison
10886 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10887 match(If cop cmp);
10888 effect(USE labl);
10889
10890 ins_cost(300);
10891 format %{ "j$cop,us $labl" %}
10892 size(2);
10893 ins_encode %{
10894 Label* L = $labl$$label;
10895 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10896 %}
10897 ins_pipe(pipe_jcc);
10898 ins_short_branch(1);
10899 %}
10900
10901 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10902 match(If cop cmp);
10903 effect(USE labl);
10904
10905 ins_cost(300);
10906 format %{ "j$cop,us $labl" %}
10907 size(2);
10908 ins_encode %{
10909 Label* L = $labl$$label;
10910 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10911 %}
10912 ins_pipe(pipe_jcc);
10913 ins_short_branch(1);
10914 %}
10915
10916 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10917 match(If cop cmp);
10918 effect(USE labl);
10919
10920 ins_cost(300);
10921 format %{ $$template
10922 if ($cop$$cmpcode == Assembler::notEqual) {
10923 $$emit$$"jp,u,s $labl\n\t"
10924 $$emit$$"j$cop,u,s $labl"
10925 } else {
10926 $$emit$$"jp,u,s done\n\t"
10927 $$emit$$"j$cop,u,s $labl\n\t"
10928 $$emit$$"done:"
10929 }
10930 %}
10931 size(4);
10932 ins_encode %{
10933 Label* l = $labl$$label;
10934 if ($cop$$cmpcode == Assembler::notEqual) {
10935 __ jccb(Assembler::parity, *l);
10936 __ jccb(Assembler::notEqual, *l);
10937 } else if ($cop$$cmpcode == Assembler::equal) {
10938 Label done;
10939 __ jccb(Assembler::parity, done);
10940 __ jccb(Assembler::equal, *l);
10941 __ bind(done);
10942 } else {
10943 ShouldNotReachHere();
10944 }
10945 %}
10946 ins_pipe(pipe_jcc);
10947 ins_short_branch(1);
10948 %}
10949
10950 // ============================================================================
10951 // inlined locking and unlocking
10952
10953 instruct cmpFastLock(rFlagsReg cr,
10954 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
10955 %{
10956 match(Set cr (FastLock object box));
10957 effect(TEMP tmp, TEMP scr, USE_KILL box);
10958
10959 ins_cost(300);
10960 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
10961 ins_encode(Fast_Lock(object, box, tmp, scr));
10962 ins_pipe(pipe_slow);
10963 %}
10964
10965 instruct cmpFastUnlock(rFlagsReg cr,
10966 rRegP object, rax_RegP box, rRegP tmp)
10967 %{
10968 match(Set cr (FastUnlock object box));
10969 effect(TEMP tmp, USE_KILL box);
10970
10971 ins_cost(300);
10972 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
10973 ins_encode(Fast_Unlock(object, box, tmp));
10974 ins_pipe(pipe_slow);
10975 %}
10976
10977
10978 // ============================================================================
10979 // Safepoint Instructions
10980 instruct safePoint_poll(rFlagsReg cr)
10981 %{
10982 predicate(!Assembler::is_polling_page_far());
10983 match(SafePoint);
10984 effect(KILL cr);
10985
10986 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
10987 "# Safepoint: poll for GC" %}
10988 ins_cost(125);
10989 ins_encode %{
10990 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
10991 __ testl(rax, addr);
10992 %}
10993 ins_pipe(ialu_reg_mem);
10994 %}
10995
10996 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
10997 %{
10998 predicate(Assembler::is_polling_page_far());
10999 match(SafePoint poll);
11000 effect(KILL cr, USE poll);
11001
11002 format %{ "testl rax, [$poll]\t"
11003 "# Safepoint: poll for GC" %}
11004 ins_cost(125);
11005 ins_encode %{
11006 __ relocate(relocInfo::poll_type);
11007 __ testl(rax, Address($poll$$Register, 0));
11008 %}
11009 ins_pipe(ialu_reg_mem);
11010 %}
11011
11012 // ============================================================================
11013 // Procedure Call/Return Instructions
11014 // Call Java Static Instruction
11015 // Note: If this code changes, the corresponding ret_addr_offset() and
11016 // compute_padding() functions will have to be adjusted.
11017 instruct CallStaticJavaDirect(method meth) %{
11018 match(CallStaticJava);
11019 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11020 effect(USE meth);
11021
11022 ins_cost(300);
11023 format %{ "call,static " %}
11024 opcode(0xE8); /* E8 cd */
11025 ins_encode(Java_Static_Call(meth), call_epilog);
11026 ins_pipe(pipe_slow);
11027 ins_alignment(4);
11028 %}
11029
11030 // Call Java Static Instruction (method handle version)
11031 // Note: If this code changes, the corresponding ret_addr_offset() and
11032 // compute_padding() functions will have to be adjusted.
11033 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11034 match(CallStaticJava);
11035 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11036 effect(USE meth);
11037 // RBP is saved by all callees (for interpreter stack correction).
11038 // We use it here for a similar purpose, in {preserve,restore}_SP.
11039
11040 ins_cost(300);
11041 format %{ "call,static/MethodHandle " %}
11042 opcode(0xE8); /* E8 cd */
11043 ins_encode(preserve_SP,
11044 Java_Static_Call(meth),
11045 restore_SP,
11046 call_epilog);
11047 ins_pipe(pipe_slow);
11048 ins_alignment(4);
11049 %}
11050
11051 // Call Java Dynamic Instruction
11052 // Note: If this code changes, the corresponding ret_addr_offset() and
11053 // compute_padding() functions will have to be adjusted.
11054 instruct CallDynamicJavaDirect(method meth)
11055 %{
11056 match(CallDynamicJava);
11057 effect(USE meth);
11058
11059 ins_cost(300);
11060 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11061 "call,dynamic " %}
11062 opcode(0xE8); /* E8 cd */
11063 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11064 ins_pipe(pipe_slow);
11065 ins_alignment(4);
11066 %}
11067
11068 // Call Runtime Instruction
11069 instruct CallRuntimeDirect(method meth)
11070 %{
11071 match(CallRuntime);
11072 effect(USE meth);
11073
11074 ins_cost(300);
11075 format %{ "call,runtime " %}
11076 opcode(0xE8); /* E8 cd */
11077 ins_encode(Java_To_Runtime(meth));
11078 ins_pipe(pipe_slow);
11079 %}
11080
11081 // Call runtime without safepoint
11082 instruct CallLeafDirect(method meth)
11083 %{
11084 match(CallLeaf);
11085 effect(USE meth);
11086
11087 ins_cost(300);
11088 format %{ "call_leaf,runtime " %}
11089 opcode(0xE8); /* E8 cd */
11090 ins_encode(Java_To_Runtime(meth));
11091 ins_pipe(pipe_slow);
11092 %}
11093
11094 // Call runtime without safepoint
11095 instruct CallLeafNoFPDirect(method meth)
11096 %{
11097 match(CallLeafNoFP);
11098 effect(USE meth);
11099
11100 ins_cost(300);
11101 format %{ "call_leaf_nofp,runtime " %}
11102 opcode(0xE8); /* E8 cd */
11103 ins_encode(Java_To_Runtime(meth));
11104 ins_pipe(pipe_slow);
11105 %}
11106
11107 // Return Instruction
11108 // Remove the return address & jump to it.
11109 // Notice: We always emit a nop after a ret to make sure there is room
11110 // for safepoint patching
11111 instruct Ret()
11112 %{
11113 match(Return);
11114
11115 format %{ "ret" %}
11116 opcode(0xC3);
11117 ins_encode(OpcP);
11118 ins_pipe(pipe_jmp);
11119 %}
11120
11121 // Tail Call; Jump from runtime stub to Java code.
11122 // Also known as an 'interprocedural jump'.
11123 // Target of jump will eventually return to caller.
11124 // TailJump below removes the return address.
11125 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11126 %{
11127 match(TailCall jump_target method_oop);
11128
11129 ins_cost(300);
11130 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11131 opcode(0xFF, 0x4); /* Opcode FF /4 */
11132 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11133 ins_pipe(pipe_jmp);
11134 %}
11135
11136 // Tail Jump; remove the return address; jump to target.
11137 // TailCall above leaves the return address around.
11138 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11139 %{
11140 match(TailJump jump_target ex_oop);
11141
11142 ins_cost(300);
11143 format %{ "popq rdx\t# pop return address\n\t"
11144 "jmp $jump_target" %}
11145 opcode(0xFF, 0x4); /* Opcode FF /4 */
11146 ins_encode(Opcode(0x5a), // popq rdx
11147 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11148 ins_pipe(pipe_jmp);
11149 %}
11150
11151 // Create exception oop: created by stack-crawling runtime code.
11152 // Created exception is now available to this handler, and is setup
11153 // just prior to jumping to this handler. No code emitted.
11154 instruct CreateException(rax_RegP ex_oop)
11155 %{
11156 match(Set ex_oop (CreateEx));
11157
11158 size(0);
11159 // use the following format syntax
11160 format %{ "# exception oop is in rax; no code emitted" %}
11161 ins_encode();
11162 ins_pipe(empty);
11163 %}
11164
11165 // Rethrow exception:
11166 // The exception oop will come in the first argument position.
11167 // Then JUMP (not call) to the rethrow stub code.
11168 instruct RethrowException()
11169 %{
11170 match(Rethrow);
11171
11172 // use the following format syntax
11173 format %{ "jmp rethrow_stub" %}
11174 ins_encode(enc_rethrow);
11175 ins_pipe(pipe_jmp);
11176 %}
11177
11178
11179 // ============================================================================
11180 // This name is KNOWN by the ADLC and cannot be changed.
11181 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11182 // for this guy.
11183 instruct tlsLoadP(r15_RegP dst) %{
11184 match(Set dst (ThreadLocal));
11185 effect(DEF dst);
11186
11187 size(0);
11188 format %{ "# TLS is in R15" %}
11189 ins_encode( /*empty encoding*/ );
11190 ins_pipe(ialu_reg_reg);
11191 %}
11192
11193
11194 //----------PEEPHOLE RULES-----------------------------------------------------
11195 // These must follow all instruction definitions as they use the names
11196 // defined in the instructions definitions.
11197 //
11198 // peepmatch ( root_instr_name [preceding_instruction]* );
11199 //
11200 // peepconstraint %{
11201 // (instruction_number.operand_name relational_op instruction_number.operand_name
11202 // [, ...] );
11203 // // instruction numbers are zero-based using left to right order in peepmatch
11204 //
11205 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11206 // // provide an instruction_number.operand_name for each operand that appears
11207 // // in the replacement instruction's match rule
11208 //
11209 // ---------VM FLAGS---------------------------------------------------------
11210 //
11211 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11212 //
11213 // Each peephole rule is given an identifying number starting with zero and
11214 // increasing by one in the order seen by the parser. An individual peephole
11215 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11216 // on the command-line.
11217 //
11218 // ---------CURRENT LIMITATIONS----------------------------------------------
11219 //
11220 // Only match adjacent instructions in same basic block
11221 // Only equality constraints
11222 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11223 // Only one replacement instruction
11224 //
11225 // ---------EXAMPLE----------------------------------------------------------
11226 //
11227 // // pertinent parts of existing instructions in architecture description
11228 // instruct movI(rRegI dst, rRegI src)
11229 // %{
11230 // match(Set dst (CopyI src));
11231 // %}
11232 //
11233 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11234 // %{
11235 // match(Set dst (AddI dst src));
11236 // effect(KILL cr);
11237 // %}
11238 //
11239 // // Change (inc mov) to lea
11240 // peephole %{
11241 // // increment preceeded by register-register move
11242 // peepmatch ( incI_rReg movI );
11243 // // require that the destination register of the increment
11244 // // match the destination register of the move
11245 // peepconstraint ( 0.dst == 1.dst );
11246 // // construct a replacement instruction that sets
11247 // // the destination to ( move's source register + one )
11248 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11249 // %}
11250 //
11251
11252 // Implementation no longer uses movX instructions since
11253 // machine-independent system no longer uses CopyX nodes.
11254 //
11255 // peephole
11256 // %{
11257 // peepmatch (incI_rReg movI);
11258 // peepconstraint (0.dst == 1.dst);
11259 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11260 // %}
11261
11262 // peephole
11263 // %{
11264 // peepmatch (decI_rReg movI);
11265 // peepconstraint (0.dst == 1.dst);
11266 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11267 // %}
11268
11269 // peephole
11270 // %{
11271 // peepmatch (addI_rReg_imm movI);
11272 // peepconstraint (0.dst == 1.dst);
11273 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11274 // %}
11275
11276 // peephole
11277 // %{
11278 // peepmatch (incL_rReg movL);
11279 // peepconstraint (0.dst == 1.dst);
11280 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11281 // %}
11282
11283 // peephole
11284 // %{
11285 // peepmatch (decL_rReg movL);
11286 // peepconstraint (0.dst == 1.dst);
11287 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11288 // %}
11289
11290 // peephole
11291 // %{
11292 // peepmatch (addL_rReg_imm movL);
11293 // peepconstraint (0.dst == 1.dst);
11294 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11295 // %}
11296
11297 // peephole
11298 // %{
11299 // peepmatch (addP_rReg_imm movP);
11300 // peepconstraint (0.dst == 1.dst);
11301 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11302 // %}
11303
11304 // // Change load of spilled value to only a spill
11305 // instruct storeI(memory mem, rRegI src)
11306 // %{
11307 // match(Set mem (StoreI mem src));
11308 // %}
11309 //
11310 // instruct loadI(rRegI dst, memory mem)
11311 // %{
11312 // match(Set dst (LoadI mem));
11313 // %}
11314 //
11315
11316 peephole
11317 %{
11318 peepmatch (loadI storeI);
11319 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11320 peepreplace (storeI(1.mem 1.mem 1.src));
11321 %}
11322
11323 peephole
11324 %{
11325 peepmatch (loadL storeL);
11326 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11327 peepreplace (storeL(1.mem 1.mem 1.src));
11328 %}
11329
11330 //----------SMARTSPILL RULES---------------------------------------------------
11331 // These must follow all instruction definitions as they use the names
11332 // defined in the instructions definitions.