1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #ifdef TARGET_ARCH_MODEL_x86_32
42 # include "adfiles/ad_x86_32.hpp"
43 #endif
44 #ifdef TARGET_ARCH_MODEL_x86_64
45 # include "adfiles/ad_x86_64.hpp"
46 #endif
47 #ifdef TARGET_ARCH_MODEL_sparc
48 # include "adfiles/ad_sparc.hpp"
49 #endif
50 #ifdef TARGET_ARCH_MODEL_zero
51 # include "adfiles/ad_zero.hpp"
52 #endif
53 #ifdef TARGET_ARCH_MODEL_arm
54 # include "adfiles/ad_arm.hpp"
55 #endif
56 #ifdef TARGET_ARCH_MODEL_ppc
57 # include "adfiles/ad_ppc.hpp"
58 #endif
59
60 OptoReg::Name OptoReg::c_frame_pointer;
61
62 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
63 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
64 RegMask Matcher::STACK_ONLY_mask;
65 RegMask Matcher::c_frame_ptr_mask;
66 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
67 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
68
69 //---------------------------Matcher-------------------------------------------
70 Matcher::Matcher( Node_List &proj_list ) :
71 PhaseTransform( Phase::Ins_Select ),
72 #ifdef ASSERT
73 _old2new_map(C->comp_arena()),
74 _new2old_map(C->comp_arena()),
75 #endif
76 _shared_nodes(C->comp_arena()),
77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
78 _swallowed(swallowed),
79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
80 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
81 _must_clone(must_clone), _proj_list(proj_list),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type),
85 _ruleName(ruleName),
86 _allocation_started(false),
87 _states_arena(Chunk::medium_size),
88 _visited(&_states_arena),
89 _shared(&_states_arena),
90 _dontcare(&_states_arena) {
91 C->set_matcher(this);
92
93 idealreg2spillmask [Op_RegI] = NULL;
94 idealreg2spillmask [Op_RegN] = NULL;
95 idealreg2spillmask [Op_RegL] = NULL;
96 idealreg2spillmask [Op_RegF] = NULL;
97 idealreg2spillmask [Op_RegD] = NULL;
98 idealreg2spillmask [Op_RegP] = NULL;
99 idealreg2spillmask [Op_VecS] = NULL;
100 idealreg2spillmask [Op_VecD] = NULL;
101 idealreg2spillmask [Op_VecX] = NULL;
102 idealreg2spillmask [Op_VecY] = NULL;
103
104 idealreg2debugmask [Op_RegI] = NULL;
105 idealreg2debugmask [Op_RegN] = NULL;
106 idealreg2debugmask [Op_RegL] = NULL;
107 idealreg2debugmask [Op_RegF] = NULL;
108 idealreg2debugmask [Op_RegD] = NULL;
109 idealreg2debugmask [Op_RegP] = NULL;
110 idealreg2debugmask [Op_VecS] = NULL;
111 idealreg2debugmask [Op_VecD] = NULL;
112 idealreg2debugmask [Op_VecX] = NULL;
113 idealreg2debugmask [Op_VecY] = NULL;
114
115 idealreg2mhdebugmask[Op_RegI] = NULL;
116 idealreg2mhdebugmask[Op_RegN] = NULL;
117 idealreg2mhdebugmask[Op_RegL] = NULL;
118 idealreg2mhdebugmask[Op_RegF] = NULL;
119 idealreg2mhdebugmask[Op_RegD] = NULL;
120 idealreg2mhdebugmask[Op_RegP] = NULL;
121 idealreg2mhdebugmask[Op_VecS] = NULL;
122 idealreg2mhdebugmask[Op_VecD] = NULL;
123 idealreg2mhdebugmask[Op_VecX] = NULL;
124 idealreg2mhdebugmask[Op_VecY] = NULL;
125
126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
127 }
128
129 //------------------------------warp_incoming_stk_arg------------------------
130 // This warps a VMReg into an OptoReg::Name
131 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
132 OptoReg::Name warped;
133 if( reg->is_stack() ) { // Stack slot argument?
134 warped = OptoReg::add(_old_SP, reg->reg2stack() );
135 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
136 if( warped >= _in_arg_limit )
137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
138 if (!RegMask::can_represent_arg(warped)) {
139 // the compiler cannot represent this method's calling sequence
140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
141 return OptoReg::Bad;
142 }
143 return warped;
144 }
145 return OptoReg::as_OptoReg(reg);
146 }
147
148 //---------------------------compute_old_SP------------------------------------
149 OptoReg::Name Compile::compute_old_SP() {
150 int fixed = fixed_slots();
151 int preserve = in_preserve_stack_slots();
152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
153 }
154
155
156
157 #ifdef ASSERT
158 void Matcher::verify_new_nodes_only(Node* xroot) {
159 // Make sure that the new graph only references new nodes
160 ResourceMark rm;
161 Unique_Node_List worklist;
162 VectorSet visited(Thread::current()->resource_area());
163 worklist.push(xroot);
164 while (worklist.size() > 0) {
165 Node* n = worklist.pop();
166 visited <<= n->_idx;
167 assert(C->node_arena()->contains(n), "dead node");
168 for (uint j = 0; j < n->req(); j++) {
169 Node* in = n->in(j);
170 if (in != NULL) {
171 assert(C->node_arena()->contains(in), "dead node");
172 if (!visited.test(in->_idx)) {
173 worklist.push(in);
174 }
175 }
176 }
177 }
178 }
179 #endif
180
181
182 //---------------------------match---------------------------------------------
183 void Matcher::match( ) {
184 if( MaxLabelRootDepth < 100 ) { // Too small?
185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
186 MaxLabelRootDepth = 100;
187 }
188 // One-time initialization of some register masks.
189 init_spill_mask( C->root()->in(1) );
190 _return_addr_mask = return_addr();
191 #ifdef _LP64
192 // Pointers take 2 slots in 64-bit land
193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
194 #endif
195
196 // Map a Java-signature return type into return register-value
197 // machine registers for 0, 1 and 2 returned values.
198 const TypeTuple *range = C->tf()->range();
199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
200 // Get ideal-register return type
201 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
202 // Get machine return register
203 uint sop = C->start()->Opcode();
204 OptoRegPair regs = return_value(ireg, false);
205
206 // And mask for same
207 _return_value_mask = RegMask(regs.first());
208 if( OptoReg::is_valid(regs.second()) )
209 _return_value_mask.Insert(regs.second());
210 }
211
212 // ---------------
213 // Frame Layout
214
215 // Need the method signature to determine the incoming argument types,
216 // because the types determine which registers the incoming arguments are
217 // in, and this affects the matched code.
218 const TypeTuple *domain = C->tf()->domain();
219 uint argcnt = domain->cnt() - TypeFunc::Parms;
220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
224 uint i;
225 for( i = 0; i<argcnt; i++ ) {
226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
227 }
228
229 // Pass array of ideal registers and length to USER code (from the AD file)
230 // that will convert this to an array of register numbers.
231 const StartNode *start = C->start();
232 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
233 #ifdef ASSERT
234 // Sanity check users' calling convention. Real handy while trying to
235 // get the initial port correct.
236 { for (uint i = 0; i<argcnt; i++) {
237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
239 _parm_regs[i].set_bad();
240 continue;
241 }
242 VMReg parm_reg = vm_parm_regs[i].first();
243 assert(parm_reg->is_valid(), "invalid arg?");
244 if (parm_reg->is_reg()) {
245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
246 assert(can_be_java_arg(opto_parm_reg) ||
247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
248 opto_parm_reg == inline_cache_reg(),
249 "parameters in register must be preserved by runtime stubs");
250 }
251 for (uint j = 0; j < i; j++) {
252 assert(parm_reg != vm_parm_regs[j].first(),
253 "calling conv. must produce distinct regs");
254 }
255 }
256 }
257 #endif
258
259 // Do some initial frame layout.
260
261 // Compute the old incoming SP (may be called FP) as
262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
263 _old_SP = C->compute_old_SP();
264 assert( is_even(_old_SP), "must be even" );
265
266 // Compute highest incoming stack argument as
267 // _old_SP + out_preserve_stack_slots + incoming argument size.
268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
269 assert( is_even(_in_arg_limit), "out_preserve must be even" );
270 for( i = 0; i < argcnt; i++ ) {
271 // Permit args to have no register
272 _calling_convention_mask[i].Clear();
273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
274 continue;
275 }
276 // calling_convention returns stack arguments as a count of
277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
278 // the allocators point of view, taking into account all the
279 // preserve area, locks & pad2.
280
281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
282 if( OptoReg::is_valid(reg1))
283 _calling_convention_mask[i].Insert(reg1);
284
285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
286 if( OptoReg::is_valid(reg2))
287 _calling_convention_mask[i].Insert(reg2);
288
289 // Saved biased stack-slot register number
290 _parm_regs[i].set_pair(reg2, reg1);
291 }
292
293 // Finally, make sure the incoming arguments take up an even number of
294 // words, in case the arguments or locals need to contain doubleword stack
295 // slots. The rest of the system assumes that stack slot pairs (in
296 // particular, in the spill area) which look aligned will in fact be
297 // aligned relative to the stack pointer in the target machine. Double
298 // stack slots will always be allocated aligned.
299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
300
301 // Compute highest outgoing stack argument as
302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
304 assert( is_even(_out_arg_limit), "out_preserve must be even" );
305
306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
307 // the compiler cannot represent this method's calling sequence
308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
309 }
310
311 if (C->failing()) return; // bailed out on incoming arg failure
312
313 // ---------------
314 // Collect roots of matcher trees. Every node for which
315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
316 // can be a valid interior of some tree.
317 find_shared( C->root() );
318 find_shared( C->top() );
319
320 C->print_method("Before Matching");
321
322 // Create new ideal node ConP #NULL even if it does exist in old space
323 // to avoid false sharing if the corresponding mach node is not used.
324 // The corresponding mach node is only used in rare cases for derived
325 // pointers.
326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
327
328 // Swap out to old-space; emptying new-space
329 Arena *old = C->node_arena()->move_contents(C->old_arena());
330
331 // Save debug and profile information for nodes in old space:
332 _old_node_note_array = C->node_note_array();
333 if (_old_node_note_array != NULL) {
334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
335 (C->comp_arena(), _old_node_note_array->length(),
336 0, NULL));
337 }
338
339 // Pre-size the new_node table to avoid the need for range checks.
340 grow_new_node_array(C->unique());
341
342 // Reset node counter so MachNodes start with _idx at 0
343 int nodes = C->unique(); // save value
344 C->set_unique(0);
345
346 // Recursively match trees from old space into new space.
347 // Correct leaves of new-space Nodes; they point to old-space.
348 _visited.Clear(); // Clear visit bits for xform call
349 C->set_cached_top_node(xform( C->top(), nodes ));
350 if (!C->failing()) {
351 Node* xroot = xform( C->root(), 1 );
352 if (xroot == NULL) {
353 Matcher::soft_match_failure(); // recursive matching process failed
354 C->record_method_not_compilable("instruction match failed");
355 } else {
356 // During matching shared constants were attached to C->root()
357 // because xroot wasn't available yet, so transfer the uses to
358 // the xroot.
359 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
360 Node* n = C->root()->fast_out(j);
361 if (C->node_arena()->contains(n)) {
362 assert(n->in(0) == C->root(), "should be control user");
363 n->set_req(0, xroot);
364 --j;
365 --jmax;
366 }
367 }
368
369 // Generate new mach node for ConP #NULL
370 assert(new_ideal_null != NULL, "sanity");
371 _mach_null = match_tree(new_ideal_null);
372 // Don't set control, it will confuse GCM since there are no uses.
373 // The control will be set when this node is used first time
374 // in find_base_for_derived().
375 assert(_mach_null != NULL, "");
376
377 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
378
379 #ifdef ASSERT
380 verify_new_nodes_only(xroot);
381 #endif
382 }
383 }
384 if (C->top() == NULL || C->root() == NULL) {
385 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
386 }
387 if (C->failing()) {
388 // delete old;
389 old->destruct_contents();
390 return;
391 }
392 assert( C->top(), "" );
393 assert( C->root(), "" );
394 validate_null_checks();
395
396 // Now smoke old-space
397 NOT_DEBUG( old->destruct_contents() );
398
399 // ------------------------
400 // Set up save-on-entry registers
401 Fixup_Save_On_Entry( );
402 }
403
404
405 //------------------------------Fixup_Save_On_Entry----------------------------
406 // The stated purpose of this routine is to take care of save-on-entry
407 // registers. However, the overall goal of the Match phase is to convert into
408 // machine-specific instructions which have RegMasks to guide allocation.
409 // So what this procedure really does is put a valid RegMask on each input
410 // to the machine-specific variations of all Return, TailCall and Halt
411 // instructions. It also adds edgs to define the save-on-entry values (and of
412 // course gives them a mask).
413
414 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
415 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
416 // Do all the pre-defined register masks
417 rms[TypeFunc::Control ] = RegMask::Empty;
418 rms[TypeFunc::I_O ] = RegMask::Empty;
419 rms[TypeFunc::Memory ] = RegMask::Empty;
420 rms[TypeFunc::ReturnAdr] = ret_adr;
421 rms[TypeFunc::FramePtr ] = fp;
422 return rms;
423 }
424
425 //---------------------------init_first_stack_mask-----------------------------
426 // Create the initial stack mask used by values spilling to the stack.
427 // Disallow any debug info in outgoing argument areas by setting the
428 // initial mask accordingly.
429 void Matcher::init_first_stack_mask() {
430
431 // Allocate storage for spill masks as masks for the appropriate load type.
432 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
433
434 idealreg2spillmask [Op_RegN] = &rms[0];
435 idealreg2spillmask [Op_RegI] = &rms[1];
436 idealreg2spillmask [Op_RegL] = &rms[2];
437 idealreg2spillmask [Op_RegF] = &rms[3];
438 idealreg2spillmask [Op_RegD] = &rms[4];
439 idealreg2spillmask [Op_RegP] = &rms[5];
440
441 idealreg2debugmask [Op_RegN] = &rms[6];
442 idealreg2debugmask [Op_RegI] = &rms[7];
443 idealreg2debugmask [Op_RegL] = &rms[8];
444 idealreg2debugmask [Op_RegF] = &rms[9];
445 idealreg2debugmask [Op_RegD] = &rms[10];
446 idealreg2debugmask [Op_RegP] = &rms[11];
447
448 idealreg2mhdebugmask[Op_RegN] = &rms[12];
449 idealreg2mhdebugmask[Op_RegI] = &rms[13];
450 idealreg2mhdebugmask[Op_RegL] = &rms[14];
451 idealreg2mhdebugmask[Op_RegF] = &rms[15];
452 idealreg2mhdebugmask[Op_RegD] = &rms[16];
453 idealreg2mhdebugmask[Op_RegP] = &rms[17];
454
455 idealreg2spillmask [Op_VecS] = &rms[18];
456 idealreg2spillmask [Op_VecD] = &rms[19];
457 idealreg2spillmask [Op_VecX] = &rms[20];
458 idealreg2spillmask [Op_VecY] = &rms[21];
459
460 OptoReg::Name i;
461
462 // At first, start with the empty mask
463 C->FIRST_STACK_mask().Clear();
464
465 // Add in the incoming argument area
466 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
467 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
468 C->FIRST_STACK_mask().Insert(i);
469
470 // Add in all bits past the outgoing argument area
471 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
472 "must be able to represent all call arguments in reg mask");
473 init = _out_arg_limit;
474 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
475 C->FIRST_STACK_mask().Insert(i);
476
477 // Finally, set the "infinite stack" bit.
478 C->FIRST_STACK_mask().set_AllStack();
479
480 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
481 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
482 // Keep spill masks aligned.
483 aligned_stack_mask.clear_to_pairs();
484 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
485
486 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
487 #ifdef _LP64
488 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
489 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
490 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
491 #else
492 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
493 #endif
494 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
495 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
496 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
497 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
498 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
499 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
500 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
501 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
502
503 if (Matcher::vector_size_supported(T_BYTE,4)) {
504 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
505 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
506 }
507 if (Matcher::vector_size_supported(T_FLOAT,2)) {
508 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
509 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
510 }
511 if (Matcher::vector_size_supported(T_FLOAT,4)) {
512 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
513 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
514 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
515 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
516 }
517 if (Matcher::vector_size_supported(T_FLOAT,8)) {
518 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
519 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
520 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
521 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
522 }
523 if (UseFPUForSpilling) {
524 // This mask logic assumes that the spill operations are
525 // symmetric and that the registers involved are the same size.
526 // On sparc for instance we may have to use 64 bit moves will
527 // kill 2 registers when used with F0-F31.
528 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
529 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
530 #ifdef _LP64
531 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
532 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
533 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
534 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
535 #else
536 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
537 #ifdef ARM
538 // ARM has support for moving 64bit values between a pair of
539 // integer registers and a double register
540 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
541 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
542 #endif
543 #endif
544 }
545
546 // Make up debug masks. Any spill slot plus callee-save registers.
547 // Caller-save registers are assumed to be trashable by the various
548 // inline-cache fixup routines.
549 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
550 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
551 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
552 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
553 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
554 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
555
556 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
557 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
558 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
559 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
560 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
561 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
562
563 // Prevent stub compilations from attempting to reference
564 // callee-saved registers from debug info
565 bool exclude_soe = !Compile::current()->is_method_compilation();
566
567 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
568 // registers the caller has to save do not work
569 if( _register_save_policy[i] == 'C' ||
570 _register_save_policy[i] == 'A' ||
571 (_register_save_policy[i] == 'E' && exclude_soe) ) {
572 idealreg2debugmask [Op_RegN]->Remove(i);
573 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
574 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
575 idealreg2debugmask [Op_RegF]->Remove(i); // masks
576 idealreg2debugmask [Op_RegD]->Remove(i);
577 idealreg2debugmask [Op_RegP]->Remove(i);
578
579 idealreg2mhdebugmask[Op_RegN]->Remove(i);
580 idealreg2mhdebugmask[Op_RegI]->Remove(i);
581 idealreg2mhdebugmask[Op_RegL]->Remove(i);
582 idealreg2mhdebugmask[Op_RegF]->Remove(i);
583 idealreg2mhdebugmask[Op_RegD]->Remove(i);
584 idealreg2mhdebugmask[Op_RegP]->Remove(i);
585 }
586 }
587
588 // Subtract the register we use to save the SP for MethodHandle
589 // invokes to from the debug mask.
590 const RegMask save_mask = method_handle_invoke_SP_save_mask();
591 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
592 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
593 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
594 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
595 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
596 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
597 }
598
599 //---------------------------is_save_on_entry----------------------------------
600 bool Matcher::is_save_on_entry( int reg ) {
601 return
602 _register_save_policy[reg] == 'E' ||
603 _register_save_policy[reg] == 'A' || // Save-on-entry register?
604 // Also save argument registers in the trampolining stubs
605 (C->save_argument_registers() && is_spillable_arg(reg));
606 }
607
608 //---------------------------Fixup_Save_On_Entry-------------------------------
609 void Matcher::Fixup_Save_On_Entry( ) {
610 init_first_stack_mask();
611
612 Node *root = C->root(); // Short name for root
613 // Count number of save-on-entry registers.
614 uint soe_cnt = number_of_saved_registers();
615 uint i;
616
617 // Find the procedure Start Node
618 StartNode *start = C->start();
619 assert( start, "Expect a start node" );
620
621 // Save argument registers in the trampolining stubs
622 if( C->save_argument_registers() )
623 for( i = 0; i < _last_Mach_Reg; i++ )
624 if( is_spillable_arg(i) )
625 soe_cnt++;
626
627 // Input RegMask array shared by all Returns.
628 // The type for doubles and longs has a count of 2, but
629 // there is only 1 returned value
630 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
631 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
632 // Returns have 0 or 1 returned values depending on call signature.
633 // Return register is specified by return_value in the AD file.
634 if (ret_edge_cnt > TypeFunc::Parms)
635 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
636
637 // Input RegMask array shared by all Rethrows.
638 uint reth_edge_cnt = TypeFunc::Parms+1;
639 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
640 // Rethrow takes exception oop only, but in the argument 0 slot.
641 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
642 #ifdef _LP64
643 // Need two slots for ptrs in 64-bit land
644 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
645 #endif
646
647 // Input RegMask array shared by all TailCalls
648 uint tail_call_edge_cnt = TypeFunc::Parms+2;
649 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
650
651 // Input RegMask array shared by all TailJumps
652 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
653 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
654
655 // TailCalls have 2 returned values (target & moop), whose masks come
656 // from the usual MachNode/MachOper mechanism. Find a sample
657 // TailCall to extract these masks and put the correct masks into
658 // the tail_call_rms array.
659 for( i=1; i < root->req(); i++ ) {
660 MachReturnNode *m = root->in(i)->as_MachReturn();
661 if( m->ideal_Opcode() == Op_TailCall ) {
662 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
663 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
664 break;
665 }
666 }
667
668 // TailJumps have 2 returned values (target & ex_oop), whose masks come
669 // from the usual MachNode/MachOper mechanism. Find a sample
670 // TailJump to extract these masks and put the correct masks into
671 // the tail_jump_rms array.
672 for( i=1; i < root->req(); i++ ) {
673 MachReturnNode *m = root->in(i)->as_MachReturn();
674 if( m->ideal_Opcode() == Op_TailJump ) {
675 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
676 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
677 break;
678 }
679 }
680
681 // Input RegMask array shared by all Halts
682 uint halt_edge_cnt = TypeFunc::Parms;
683 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
684
685 // Capture the return input masks into each exit flavor
686 for( i=1; i < root->req(); i++ ) {
687 MachReturnNode *exit = root->in(i)->as_MachReturn();
688 switch( exit->ideal_Opcode() ) {
689 case Op_Return : exit->_in_rms = ret_rms; break;
690 case Op_Rethrow : exit->_in_rms = reth_rms; break;
691 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
692 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
693 case Op_Halt : exit->_in_rms = halt_rms; break;
694 default : ShouldNotReachHere();
695 }
696 }
697
698 // Next unused projection number from Start.
699 int proj_cnt = C->tf()->domain()->cnt();
700
701 // Do all the save-on-entry registers. Make projections from Start for
702 // them, and give them a use at the exit points. To the allocator, they
703 // look like incoming register arguments.
704 for( i = 0; i < _last_Mach_Reg; i++ ) {
705 if( is_save_on_entry(i) ) {
706
707 // Add the save-on-entry to the mask array
708 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
709 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
710 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
711 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
712 // Halts need the SOE registers, but only in the stack as debug info.
713 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
714 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
715
716 Node *mproj;
717
718 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
719 // into a single RegD.
720 if( (i&1) == 0 &&
721 _register_save_type[i ] == Op_RegF &&
722 _register_save_type[i+1] == Op_RegF &&
723 is_save_on_entry(i+1) ) {
724 // Add other bit for double
725 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
726 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
727 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
728 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
729 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
730 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
731 proj_cnt += 2; // Skip 2 for doubles
732 }
733 else if( (i&1) == 1 && // Else check for high half of double
734 _register_save_type[i-1] == Op_RegF &&
735 _register_save_type[i ] == Op_RegF &&
736 is_save_on_entry(i-1) ) {
737 ret_rms [ ret_edge_cnt] = RegMask::Empty;
738 reth_rms [ reth_edge_cnt] = RegMask::Empty;
739 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
740 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
741 halt_rms [ halt_edge_cnt] = RegMask::Empty;
742 mproj = C->top();
743 }
744 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
745 // into a single RegL.
746 else if( (i&1) == 0 &&
747 _register_save_type[i ] == Op_RegI &&
748 _register_save_type[i+1] == Op_RegI &&
749 is_save_on_entry(i+1) ) {
750 // Add other bit for long
751 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
752 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
753 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
754 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
755 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
756 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
757 proj_cnt += 2; // Skip 2 for longs
758 }
759 else if( (i&1) == 1 && // Else check for high half of long
760 _register_save_type[i-1] == Op_RegI &&
761 _register_save_type[i ] == Op_RegI &&
762 is_save_on_entry(i-1) ) {
763 ret_rms [ ret_edge_cnt] = RegMask::Empty;
764 reth_rms [ reth_edge_cnt] = RegMask::Empty;
765 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
766 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
767 halt_rms [ halt_edge_cnt] = RegMask::Empty;
768 mproj = C->top();
769 } else {
770 // Make a projection for it off the Start
771 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
772 }
773
774 ret_edge_cnt ++;
775 reth_edge_cnt ++;
776 tail_call_edge_cnt ++;
777 tail_jump_edge_cnt ++;
778 halt_edge_cnt ++;
779
780 // Add a use of the SOE register to all exit paths
781 for( uint j=1; j < root->req(); j++ )
782 root->in(j)->add_req(mproj);
783 } // End of if a save-on-entry register
784 } // End of for all machine registers
785 }
786
787 //------------------------------init_spill_mask--------------------------------
788 void Matcher::init_spill_mask( Node *ret ) {
789 if( idealreg2regmask[Op_RegI] ) return; // One time only init
790
791 OptoReg::c_frame_pointer = c_frame_pointer();
792 c_frame_ptr_mask = c_frame_pointer();
793 #ifdef _LP64
794 // pointers are twice as big
795 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
796 #endif
797
798 // Start at OptoReg::stack0()
799 STACK_ONLY_mask.Clear();
800 OptoReg::Name init = OptoReg::stack2reg(0);
801 // STACK_ONLY_mask is all stack bits
802 OptoReg::Name i;
803 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
804 STACK_ONLY_mask.Insert(i);
805 // Also set the "infinite stack" bit.
806 STACK_ONLY_mask.set_AllStack();
807
808 // Copy the register names over into the shared world
809 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
810 // SharedInfo::regName[i] = regName[i];
811 // Handy RegMasks per machine register
812 mreg2regmask[i].Insert(i);
813 }
814
815 // Grab the Frame Pointer
816 Node *fp = ret->in(TypeFunc::FramePtr);
817 Node *mem = ret->in(TypeFunc::Memory);
818 const TypePtr* atp = TypePtr::BOTTOM;
819 // Share frame pointer while making spill ops
820 set_shared(fp);
821
822 // Compute generic short-offset Loads
823 #ifdef _LP64
824 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
825 #endif
826 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
827 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
828 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
829 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
830 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
831 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
832 spillD != NULL && spillP != NULL, "");
833
834 // Get the ADLC notion of the right regmask, for each basic type.
835 #ifdef _LP64
836 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
837 #endif
838 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
839 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
840 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
841 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
842 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
843
844 // Vector regmasks.
845 if (Matcher::vector_size_supported(T_BYTE,4)) {
846 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
847 MachNode *spillVectS = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
848 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
849 }
850 if (Matcher::vector_size_supported(T_FLOAT,2)) {
851 MachNode *spillVectD = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
852 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
853 }
854 if (Matcher::vector_size_supported(T_FLOAT,4)) {
855 MachNode *spillVectX = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
856 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
857 }
858 if (Matcher::vector_size_supported(T_FLOAT,8)) {
859 MachNode *spillVectY = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
860 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
861 }
862 }
863
864 #ifdef ASSERT
865 static void match_alias_type(Compile* C, Node* n, Node* m) {
866 if (!VerifyAliases) return; // do not go looking for trouble by default
867 const TypePtr* nat = n->adr_type();
868 const TypePtr* mat = m->adr_type();
869 int nidx = C->get_alias_index(nat);
870 int midx = C->get_alias_index(mat);
871 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
872 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
873 for (uint i = 1; i < n->req(); i++) {
874 Node* n1 = n->in(i);
875 const TypePtr* n1at = n1->adr_type();
876 if (n1at != NULL) {
877 nat = n1at;
878 nidx = C->get_alias_index(n1at);
879 }
880 }
881 }
882 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
883 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
884 switch (n->Opcode()) {
885 case Op_PrefetchRead:
886 case Op_PrefetchWrite:
887 case Op_PrefetchAllocation:
888 nidx = Compile::AliasIdxRaw;
889 nat = TypeRawPtr::BOTTOM;
890 break;
891 }
892 }
893 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
894 switch (n->Opcode()) {
895 case Op_ClearArray:
896 midx = Compile::AliasIdxRaw;
897 mat = TypeRawPtr::BOTTOM;
898 break;
899 }
900 }
901 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
902 switch (n->Opcode()) {
903 case Op_Return:
904 case Op_Rethrow:
905 case Op_Halt:
906 case Op_TailCall:
907 case Op_TailJump:
908 nidx = Compile::AliasIdxBot;
909 nat = TypePtr::BOTTOM;
910 break;
911 }
912 }
913 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
914 switch (n->Opcode()) {
915 case Op_StrComp:
916 case Op_StrEquals:
917 case Op_StrIndexOf:
918 case Op_AryEq:
919 case Op_MemBarVolatile:
920 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
921 nidx = Compile::AliasIdxTop;
922 nat = NULL;
923 break;
924 }
925 }
926 if (nidx != midx) {
927 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
928 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
929 n->dump();
930 m->dump();
931 }
932 assert(C->subsume_loads() && C->must_alias(nat, midx),
933 "must not lose alias info when matching");
934 }
935 }
936 #endif
937
938
939 //------------------------------MStack-----------------------------------------
940 // State and MStack class used in xform() and find_shared() iterative methods.
941 enum Node_State { Pre_Visit, // node has to be pre-visited
942 Visit, // visit node
943 Post_Visit, // post-visit node
944 Alt_Post_Visit // alternative post-visit path
945 };
946
947 class MStack: public Node_Stack {
948 public:
949 MStack(int size) : Node_Stack(size) { }
950
951 void push(Node *n, Node_State ns) {
952 Node_Stack::push(n, (uint)ns);
953 }
954 void push(Node *n, Node_State ns, Node *parent, int indx) {
955 ++_inode_top;
956 if ((_inode_top + 1) >= _inode_max) grow();
957 _inode_top->node = parent;
958 _inode_top->indx = (uint)indx;
959 ++_inode_top;
960 _inode_top->node = n;
961 _inode_top->indx = (uint)ns;
962 }
963 Node *parent() {
964 pop();
965 return node();
966 }
967 Node_State state() const {
968 return (Node_State)index();
969 }
970 void set_state(Node_State ns) {
971 set_index((uint)ns);
972 }
973 };
974
975
976 //------------------------------xform------------------------------------------
977 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
978 // Node in new-space. Given a new-space Node, recursively walk his children.
979 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
980 Node *Matcher::xform( Node *n, int max_stack ) {
981 // Use one stack to keep both: child's node/state and parent's node/index
982 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
983 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
984
985 while (mstack.is_nonempty()) {
986 n = mstack.node(); // Leave node on stack
987 Node_State nstate = mstack.state();
988 if (nstate == Visit) {
989 mstack.set_state(Post_Visit);
990 Node *oldn = n;
991 // Old-space or new-space check
992 if (!C->node_arena()->contains(n)) {
993 // Old space!
994 Node* m;
995 if (has_new_node(n)) { // Not yet Label/Reduced
996 m = new_node(n);
997 } else {
998 if (!is_dontcare(n)) { // Matcher can match this guy
999 // Calls match special. They match alone with no children.
1000 // Their children, the incoming arguments, match normally.
1001 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1002 if (C->failing()) return NULL;
1003 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1004 } else { // Nothing the matcher cares about
1005 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1006 // Convert to machine-dependent projection
1007 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1008 #ifdef ASSERT
1009 _new2old_map.map(m->_idx, n);
1010 #endif
1011 if (m->in(0) != NULL) // m might be top
1012 collect_null_checks(m, n);
1013 } else { // Else just a regular 'ol guy
1014 m = n->clone(); // So just clone into new-space
1015 #ifdef ASSERT
1016 _new2old_map.map(m->_idx, n);
1017 #endif
1018 // Def-Use edges will be added incrementally as Uses
1019 // of this node are matched.
1020 assert(m->outcnt() == 0, "no Uses of this clone yet");
1021 }
1022 }
1023
1024 set_new_node(n, m); // Map old to new
1025 if (_old_node_note_array != NULL) {
1026 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1027 n->_idx);
1028 C->set_node_notes_at(m->_idx, nn);
1029 }
1030 debug_only(match_alias_type(C, n, m));
1031 }
1032 n = m; // n is now a new-space node
1033 mstack.set_node(n);
1034 }
1035
1036 // New space!
1037 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1038
1039 int i;
1040 // Put precedence edges on stack first (match them last).
1041 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1042 Node *m = oldn->in(i);
1043 if (m == NULL) break;
1044 // set -1 to call add_prec() instead of set_req() during Step1
1045 mstack.push(m, Visit, n, -1);
1046 }
1047
1048 // For constant debug info, I'd rather have unmatched constants.
1049 int cnt = n->req();
1050 JVMState* jvms = n->jvms();
1051 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1052
1053 // Now do only debug info. Clone constants rather than matching.
1054 // Constants are represented directly in the debug info without
1055 // the need for executable machine instructions.
1056 // Monitor boxes are also represented directly.
1057 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1058 Node *m = n->in(i); // Get input
1059 int op = m->Opcode();
1060 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1061 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
1062 op == Op_ConF || op == Op_ConD || op == Op_ConL
1063 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1064 ) {
1065 m = m->clone();
1066 #ifdef ASSERT
1067 _new2old_map.map(m->_idx, n);
1068 #endif
1069 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1070 mstack.push(m->in(0), Visit, m, 0);
1071 } else {
1072 mstack.push(m, Visit, n, i);
1073 }
1074 }
1075
1076 // And now walk his children, and convert his inputs to new-space.
1077 for( ; i >= 0; --i ) { // For all normal inputs do
1078 Node *m = n->in(i); // Get input
1079 if(m != NULL)
1080 mstack.push(m, Visit, n, i);
1081 }
1082
1083 }
1084 else if (nstate == Post_Visit) {
1085 // Set xformed input
1086 Node *p = mstack.parent();
1087 if (p != NULL) { // root doesn't have parent
1088 int i = (int)mstack.index();
1089 if (i >= 0)
1090 p->set_req(i, n); // required input
1091 else if (i == -1)
1092 p->add_prec(n); // precedence input
1093 else
1094 ShouldNotReachHere();
1095 }
1096 mstack.pop(); // remove processed node from stack
1097 }
1098 else {
1099 ShouldNotReachHere();
1100 }
1101 } // while (mstack.is_nonempty())
1102 return n; // Return new-space Node
1103 }
1104
1105 //------------------------------warp_outgoing_stk_arg------------------------
1106 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1107 // Convert outgoing argument location to a pre-biased stack offset
1108 if (reg->is_stack()) {
1109 OptoReg::Name warped = reg->reg2stack();
1110 // Adjust the stack slot offset to be the register number used
1111 // by the allocator.
1112 warped = OptoReg::add(begin_out_arg_area, warped);
1113 // Keep track of the largest numbered stack slot used for an arg.
1114 // Largest used slot per call-site indicates the amount of stack
1115 // that is killed by the call.
1116 if( warped >= out_arg_limit_per_call )
1117 out_arg_limit_per_call = OptoReg::add(warped,1);
1118 if (!RegMask::can_represent_arg(warped)) {
1119 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1120 return OptoReg::Bad;
1121 }
1122 return warped;
1123 }
1124 return OptoReg::as_OptoReg(reg);
1125 }
1126
1127
1128 //------------------------------match_sfpt-------------------------------------
1129 // Helper function to match call instructions. Calls match special.
1130 // They match alone with no children. Their children, the incoming
1131 // arguments, match normally.
1132 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1133 MachSafePointNode *msfpt = NULL;
1134 MachCallNode *mcall = NULL;
1135 uint cnt;
1136 // Split out case for SafePoint vs Call
1137 CallNode *call;
1138 const TypeTuple *domain;
1139 ciMethod* method = NULL;
1140 bool is_method_handle_invoke = false; // for special kill effects
1141 if( sfpt->is_Call() ) {
1142 call = sfpt->as_Call();
1143 domain = call->tf()->domain();
1144 cnt = domain->cnt();
1145
1146 // Match just the call, nothing else
1147 MachNode *m = match_tree(call);
1148 if (C->failing()) return NULL;
1149 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1150
1151 // Copy data from the Ideal SafePoint to the machine version
1152 mcall = m->as_MachCall();
1153
1154 mcall->set_tf( call->tf());
1155 mcall->set_entry_point(call->entry_point());
1156 mcall->set_cnt( call->cnt());
1157
1158 if( mcall->is_MachCallJava() ) {
1159 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1160 const CallJavaNode *call_java = call->as_CallJava();
1161 method = call_java->method();
1162 mcall_java->_method = method;
1163 mcall_java->_bci = call_java->_bci;
1164 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1165 is_method_handle_invoke = call_java->is_method_handle_invoke();
1166 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1167 if (is_method_handle_invoke) {
1168 C->set_has_method_handle_invokes(true);
1169 }
1170 if( mcall_java->is_MachCallStaticJava() )
1171 mcall_java->as_MachCallStaticJava()->_name =
1172 call_java->as_CallStaticJava()->_name;
1173 if( mcall_java->is_MachCallDynamicJava() )
1174 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1175 call_java->as_CallDynamicJava()->_vtable_index;
1176 }
1177 else if( mcall->is_MachCallRuntime() ) {
1178 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1179 }
1180 msfpt = mcall;
1181 }
1182 // This is a non-call safepoint
1183 else {
1184 call = NULL;
1185 domain = NULL;
1186 MachNode *mn = match_tree(sfpt);
1187 if (C->failing()) return NULL;
1188 msfpt = mn->as_MachSafePoint();
1189 cnt = TypeFunc::Parms;
1190 }
1191
1192 // Advertise the correct memory effects (for anti-dependence computation).
1193 msfpt->set_adr_type(sfpt->adr_type());
1194
1195 // Allocate a private array of RegMasks. These RegMasks are not shared.
1196 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1197 // Empty them all.
1198 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1199
1200 // Do all the pre-defined non-Empty register masks
1201 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1202 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1203
1204 // Place first outgoing argument can possibly be put.
1205 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1206 assert( is_even(begin_out_arg_area), "" );
1207 // Compute max outgoing register number per call site.
1208 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1209 // Calls to C may hammer extra stack slots above and beyond any arguments.
1210 // These are usually backing store for register arguments for varargs.
1211 if( call != NULL && call->is_CallRuntime() )
1212 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1213
1214
1215 // Do the normal argument list (parameters) register masks
1216 int argcnt = cnt - TypeFunc::Parms;
1217 if( argcnt > 0 ) { // Skip it all if we have no args
1218 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1219 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1220 int i;
1221 for( i = 0; i < argcnt; i++ ) {
1222 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1223 }
1224 // V-call to pick proper calling convention
1225 call->calling_convention( sig_bt, parm_regs, argcnt );
1226
1227 #ifdef ASSERT
1228 // Sanity check users' calling convention. Really handy during
1229 // the initial porting effort. Fairly expensive otherwise.
1230 { for (int i = 0; i<argcnt; i++) {
1231 if( !parm_regs[i].first()->is_valid() &&
1232 !parm_regs[i].second()->is_valid() ) continue;
1233 VMReg reg1 = parm_regs[i].first();
1234 VMReg reg2 = parm_regs[i].second();
1235 for (int j = 0; j < i; j++) {
1236 if( !parm_regs[j].first()->is_valid() &&
1237 !parm_regs[j].second()->is_valid() ) continue;
1238 VMReg reg3 = parm_regs[j].first();
1239 VMReg reg4 = parm_regs[j].second();
1240 if( !reg1->is_valid() ) {
1241 assert( !reg2->is_valid(), "valid halvsies" );
1242 } else if( !reg3->is_valid() ) {
1243 assert( !reg4->is_valid(), "valid halvsies" );
1244 } else {
1245 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1246 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1247 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1248 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1249 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1250 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1251 }
1252 }
1253 }
1254 }
1255 #endif
1256
1257 // Visit each argument. Compute its outgoing register mask.
1258 // Return results now can have 2 bits returned.
1259 // Compute max over all outgoing arguments both per call-site
1260 // and over the entire method.
1261 for( i = 0; i < argcnt; i++ ) {
1262 // Address of incoming argument mask to fill in
1263 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1264 if( !parm_regs[i].first()->is_valid() &&
1265 !parm_regs[i].second()->is_valid() ) {
1266 continue; // Avoid Halves
1267 }
1268 // Grab first register, adjust stack slots and insert in mask.
1269 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1270 if (OptoReg::is_valid(reg1))
1271 rm->Insert( reg1 );
1272 // Grab second register (if any), adjust stack slots and insert in mask.
1273 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1274 if (OptoReg::is_valid(reg2))
1275 rm->Insert( reg2 );
1276 } // End of for all arguments
1277
1278 // Compute number of stack slots needed to restore stack in case of
1279 // Pascal-style argument popping.
1280 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1281 }
1282
1283 if (is_method_handle_invoke) {
1284 // Kill some extra stack space in case method handles want to do
1285 // a little in-place argument insertion.
1286 int regs_per_word = NOT_LP64(1) LP64_ONLY(2); // %%% make a global const!
1287 out_arg_limit_per_call += MethodHandlePushLimit * regs_per_word;
1288 // Do not update mcall->_argsize because (a) the extra space is not
1289 // pushed as arguments and (b) _argsize is dead (not used anywhere).
1290 }
1291
1292 // Compute the max stack slot killed by any call. These will not be
1293 // available for debug info, and will be used to adjust FIRST_STACK_mask
1294 // after all call sites have been visited.
1295 if( _out_arg_limit < out_arg_limit_per_call)
1296 _out_arg_limit = out_arg_limit_per_call;
1297
1298 if (mcall) {
1299 // Kill the outgoing argument area, including any non-argument holes and
1300 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1301 // Since the max-per-method covers the max-per-call-site and debug info
1302 // is excluded on the max-per-method basis, debug info cannot land in
1303 // this killed area.
1304 uint r_cnt = mcall->tf()->range()->cnt();
1305 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1306 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1307 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1308 } else {
1309 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1310 proj->_rout.Insert(OptoReg::Name(i));
1311 }
1312 if( proj->_rout.is_NotEmpty() )
1313 _proj_list.push(proj);
1314 }
1315 // Transfer the safepoint information from the call to the mcall
1316 // Move the JVMState list
1317 msfpt->set_jvms(sfpt->jvms());
1318 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1319 jvms->set_map(sfpt);
1320 }
1321
1322 // Debug inputs begin just after the last incoming parameter
1323 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1324 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1325
1326 // Move the OopMap
1327 msfpt->_oop_map = sfpt->_oop_map;
1328
1329 // Registers killed by the call are set in the local scheduling pass
1330 // of Global Code Motion.
1331 return msfpt;
1332 }
1333
1334 //---------------------------match_tree----------------------------------------
1335 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1336 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1337 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1338 // a Load's result RegMask for memoization in idealreg2regmask[]
1339 MachNode *Matcher::match_tree( const Node *n ) {
1340 assert( n->Opcode() != Op_Phi, "cannot match" );
1341 assert( !n->is_block_start(), "cannot match" );
1342 // Set the mark for all locally allocated State objects.
1343 // When this call returns, the _states_arena arena will be reset
1344 // freeing all State objects.
1345 ResourceMark rm( &_states_arena );
1346
1347 LabelRootDepth = 0;
1348
1349 // StoreNodes require their Memory input to match any LoadNodes
1350 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1351 #ifdef ASSERT
1352 Node* save_mem_node = _mem_node;
1353 _mem_node = n->is_Store() ? (Node*)n : NULL;
1354 #endif
1355 // State object for root node of match tree
1356 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1357 State *s = new (&_states_arena) State;
1358 s->_kids[0] = NULL;
1359 s->_kids[1] = NULL;
1360 s->_leaf = (Node*)n;
1361 // Label the input tree, allocating labels from top-level arena
1362 Label_Root( n, s, n->in(0), mem );
1363 if (C->failing()) return NULL;
1364
1365 // The minimum cost match for the whole tree is found at the root State
1366 uint mincost = max_juint;
1367 uint cost = max_juint;
1368 uint i;
1369 for( i = 0; i < NUM_OPERANDS; i++ ) {
1370 if( s->valid(i) && // valid entry and
1371 s->_cost[i] < cost && // low cost and
1372 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1373 cost = s->_cost[mincost=i];
1374 }
1375 if (mincost == max_juint) {
1376 #ifndef PRODUCT
1377 tty->print("No matching rule for:");
1378 s->dump();
1379 #endif
1380 Matcher::soft_match_failure();
1381 return NULL;
1382 }
1383 // Reduce input tree based upon the state labels to machine Nodes
1384 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1385 #ifdef ASSERT
1386 _old2new_map.map(n->_idx, m);
1387 _new2old_map.map(m->_idx, (Node*)n);
1388 #endif
1389
1390 // Add any Matcher-ignored edges
1391 uint cnt = n->req();
1392 uint start = 1;
1393 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1394 if( n->is_AddP() ) {
1395 assert( mem == (Node*)1, "" );
1396 start = AddPNode::Base+1;
1397 }
1398 for( i = start; i < cnt; i++ ) {
1399 if( !n->match_edge(i) ) {
1400 if( i < m->req() )
1401 m->ins_req( i, n->in(i) );
1402 else
1403 m->add_req( n->in(i) );
1404 }
1405 }
1406
1407 debug_only( _mem_node = save_mem_node; )
1408 return m;
1409 }
1410
1411
1412 //------------------------------match_into_reg---------------------------------
1413 // Choose to either match this Node in a register or part of the current
1414 // match tree. Return true for requiring a register and false for matching
1415 // as part of the current match tree.
1416 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1417
1418 const Type *t = m->bottom_type();
1419
1420 if (t->singleton()) {
1421 // Never force constants into registers. Allow them to match as
1422 // constants or registers. Copies of the same value will share
1423 // the same register. See find_shared_node.
1424 return false;
1425 } else { // Not a constant
1426 // Stop recursion if they have different Controls.
1427 Node* m_control = m->in(0);
1428 // Control of load's memory can post-dominates load's control.
1429 // So use it since load can't float above its memory.
1430 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1431 if (control && m_control && control != m_control && control != mem_control) {
1432
1433 // Actually, we can live with the most conservative control we
1434 // find, if it post-dominates the others. This allows us to
1435 // pick up load/op/store trees where the load can float a little
1436 // above the store.
1437 Node *x = control;
1438 const uint max_scan = 6; // Arbitrary scan cutoff
1439 uint j;
1440 for (j=0; j<max_scan; j++) {
1441 if (x->is_Region()) // Bail out at merge points
1442 return true;
1443 x = x->in(0);
1444 if (x == m_control) // Does 'control' post-dominate
1445 break; // m->in(0)? If so, we can use it
1446 if (x == mem_control) // Does 'control' post-dominate
1447 break; // mem_control? If so, we can use it
1448 }
1449 if (j == max_scan) // No post-domination before scan end?
1450 return true; // Then break the match tree up
1451 }
1452 if (m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) {
1453 // These are commonly used in address expressions and can
1454 // efficiently fold into them on X64 in some cases.
1455 return false;
1456 }
1457 }
1458
1459 // Not forceable cloning. If shared, put it into a register.
1460 return shared;
1461 }
1462
1463
1464 //------------------------------Instruction Selection--------------------------
1465 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1466 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1467 // things the Matcher does not match (e.g., Memory), and things with different
1468 // Controls (hence forced into different blocks). We pass in the Control
1469 // selected for this entire State tree.
1470
1471 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1472 // Store and the Load must have identical Memories (as well as identical
1473 // pointers). Since the Matcher does not have anything for Memory (and
1474 // does not handle DAGs), I have to match the Memory input myself. If the
1475 // Tree root is a Store, I require all Loads to have the identical memory.
1476 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1477 // Since Label_Root is a recursive function, its possible that we might run
1478 // out of stack space. See bugs 6272980 & 6227033 for more info.
1479 LabelRootDepth++;
1480 if (LabelRootDepth > MaxLabelRootDepth) {
1481 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1482 return NULL;
1483 }
1484 uint care = 0; // Edges matcher cares about
1485 uint cnt = n->req();
1486 uint i = 0;
1487
1488 // Examine children for memory state
1489 // Can only subsume a child into your match-tree if that child's memory state
1490 // is not modified along the path to another input.
1491 // It is unsafe even if the other inputs are separate roots.
1492 Node *input_mem = NULL;
1493 for( i = 1; i < cnt; i++ ) {
1494 if( !n->match_edge(i) ) continue;
1495 Node *m = n->in(i); // Get ith input
1496 assert( m, "expect non-null children" );
1497 if( m->is_Load() ) {
1498 if( input_mem == NULL ) {
1499 input_mem = m->in(MemNode::Memory);
1500 } else if( input_mem != m->in(MemNode::Memory) ) {
1501 input_mem = NodeSentinel;
1502 }
1503 }
1504 }
1505
1506 for( i = 1; i < cnt; i++ ){// For my children
1507 if( !n->match_edge(i) ) continue;
1508 Node *m = n->in(i); // Get ith input
1509 // Allocate states out of a private arena
1510 State *s = new (&_states_arena) State;
1511 svec->_kids[care++] = s;
1512 assert( care <= 2, "binary only for now" );
1513
1514 // Recursively label the State tree.
1515 s->_kids[0] = NULL;
1516 s->_kids[1] = NULL;
1517 s->_leaf = m;
1518
1519 // Check for leaves of the State Tree; things that cannot be a part of
1520 // the current tree. If it finds any, that value is matched as a
1521 // register operand. If not, then the normal matching is used.
1522 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1523 //
1524 // Stop recursion if this is LoadNode and the root of this tree is a
1525 // StoreNode and the load & store have different memories.
1526 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1527 // Can NOT include the match of a subtree when its memory state
1528 // is used by any of the other subtrees
1529 (input_mem == NodeSentinel) ) {
1530 #ifndef PRODUCT
1531 // Print when we exclude matching due to different memory states at input-loads
1532 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1533 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1534 tty->print_cr("invalid input_mem");
1535 }
1536 #endif
1537 // Switch to a register-only opcode; this value must be in a register
1538 // and cannot be subsumed as part of a larger instruction.
1539 s->DFA( m->ideal_reg(), m );
1540
1541 } else {
1542 // If match tree has no control and we do, adopt it for entire tree
1543 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1544 control = m->in(0); // Pick up control
1545 // Else match as a normal part of the match tree.
1546 control = Label_Root(m,s,control,mem);
1547 if (C->failing()) return NULL;
1548 }
1549 }
1550
1551
1552 // Call DFA to match this node, and return
1553 svec->DFA( n->Opcode(), n );
1554
1555 #ifdef ASSERT
1556 uint x;
1557 for( x = 0; x < _LAST_MACH_OPER; x++ )
1558 if( svec->valid(x) )
1559 break;
1560
1561 if (x >= _LAST_MACH_OPER) {
1562 n->dump();
1563 svec->dump();
1564 assert( false, "bad AD file" );
1565 }
1566 #endif
1567 return control;
1568 }
1569
1570
1571 // Con nodes reduced using the same rule can share their MachNode
1572 // which reduces the number of copies of a constant in the final
1573 // program. The register allocator is free to split uses later to
1574 // split live ranges.
1575 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1576 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1577
1578 // See if this Con has already been reduced using this rule.
1579 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1580 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1581 if (last != NULL && rule == last->rule()) {
1582 // Don't expect control change for DecodeN
1583 if (leaf->is_DecodeN())
1584 return last;
1585 // Get the new space root.
1586 Node* xroot = new_node(C->root());
1587 if (xroot == NULL) {
1588 // This shouldn't happen give the order of matching.
1589 return NULL;
1590 }
1591
1592 // Shared constants need to have their control be root so they
1593 // can be scheduled properly.
1594 Node* control = last->in(0);
1595 if (control != xroot) {
1596 if (control == NULL || control == C->root()) {
1597 last->set_req(0, xroot);
1598 } else {
1599 assert(false, "unexpected control");
1600 return NULL;
1601 }
1602 }
1603 return last;
1604 }
1605 return NULL;
1606 }
1607
1608
1609 //------------------------------ReduceInst-------------------------------------
1610 // Reduce a State tree (with given Control) into a tree of MachNodes.
1611 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1612 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1613 // Each MachNode has a number of complicated MachOper operands; each
1614 // MachOper also covers a further tree of Ideal Nodes.
1615
1616 // The root of the Ideal match tree is always an instruction, so we enter
1617 // the recursion here. After building the MachNode, we need to recurse
1618 // the tree checking for these cases:
1619 // (1) Child is an instruction -
1620 // Build the instruction (recursively), add it as an edge.
1621 // Build a simple operand (register) to hold the result of the instruction.
1622 // (2) Child is an interior part of an instruction -
1623 // Skip over it (do nothing)
1624 // (3) Child is the start of a operand -
1625 // Build the operand, place it inside the instruction
1626 // Call ReduceOper.
1627 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1628 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1629
1630 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1631 if (shared_node != NULL) {
1632 return shared_node;
1633 }
1634
1635 // Build the object to represent this state & prepare for recursive calls
1636 MachNode *mach = s->MachNodeGenerator( rule, C );
1637 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1638 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1639 Node *leaf = s->_leaf;
1640 // Check for instruction or instruction chain rule
1641 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1642 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1643 "duplicating node that's already been matched");
1644 // Instruction
1645 mach->add_req( leaf->in(0) ); // Set initial control
1646 // Reduce interior of complex instruction
1647 ReduceInst_Interior( s, rule, mem, mach, 1 );
1648 } else {
1649 // Instruction chain rules are data-dependent on their inputs
1650 mach->add_req(0); // Set initial control to none
1651 ReduceInst_Chain_Rule( s, rule, mem, mach );
1652 }
1653
1654 // If a Memory was used, insert a Memory edge
1655 if( mem != (Node*)1 ) {
1656 mach->ins_req(MemNode::Memory,mem);
1657 #ifdef ASSERT
1658 // Verify adr type after matching memory operation
1659 const MachOper* oper = mach->memory_operand();
1660 if (oper != NULL && oper != (MachOper*)-1) {
1661 // It has a unique memory operand. Find corresponding ideal mem node.
1662 Node* m = NULL;
1663 if (leaf->is_Mem()) {
1664 m = leaf;
1665 } else {
1666 m = _mem_node;
1667 assert(m != NULL && m->is_Mem(), "expecting memory node");
1668 }
1669 const Type* mach_at = mach->adr_type();
1670 // DecodeN node consumed by an address may have different type
1671 // then its input. Don't compare types for such case.
1672 if (m->adr_type() != mach_at &&
1673 (m->in(MemNode::Address)->is_DecodeN() ||
1674 m->in(MemNode::Address)->is_AddP() &&
1675 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() ||
1676 m->in(MemNode::Address)->is_AddP() &&
1677 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1678 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) {
1679 mach_at = m->adr_type();
1680 }
1681 if (m->adr_type() != mach_at) {
1682 m->dump();
1683 tty->print_cr("mach:");
1684 mach->dump(1);
1685 }
1686 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1687 }
1688 #endif
1689 }
1690
1691 // If the _leaf is an AddP, insert the base edge
1692 if( leaf->is_AddP() )
1693 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1694
1695 uint num_proj = _proj_list.size();
1696
1697 // Perform any 1-to-many expansions required
1698 MachNode *ex = mach->Expand(s,_proj_list, mem);
1699 if( ex != mach ) {
1700 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1701 if( ex->in(1)->is_Con() )
1702 ex->in(1)->set_req(0, C->root());
1703 // Remove old node from the graph
1704 for( uint i=0; i<mach->req(); i++ ) {
1705 mach->set_req(i,NULL);
1706 }
1707 #ifdef ASSERT
1708 _new2old_map.map(ex->_idx, s->_leaf);
1709 #endif
1710 }
1711
1712 // PhaseChaitin::fixup_spills will sometimes generate spill code
1713 // via the matcher. By the time, nodes have been wired into the CFG,
1714 // and any further nodes generated by expand rules will be left hanging
1715 // in space, and will not get emitted as output code. Catch this.
1716 // Also, catch any new register allocation constraints ("projections")
1717 // generated belatedly during spill code generation.
1718 if (_allocation_started) {
1719 guarantee(ex == mach, "no expand rules during spill generation");
1720 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1721 }
1722
1723 if (leaf->is_Con() || leaf->is_DecodeN()) {
1724 // Record the con for sharing
1725 _shared_nodes.map(leaf->_idx, ex);
1726 }
1727
1728 return ex;
1729 }
1730
1731 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1732 // 'op' is what I am expecting to receive
1733 int op = _leftOp[rule];
1734 // Operand type to catch childs result
1735 // This is what my child will give me.
1736 int opnd_class_instance = s->_rule[op];
1737 // Choose between operand class or not.
1738 // This is what I will receive.
1739 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1740 // New rule for child. Chase operand classes to get the actual rule.
1741 int newrule = s->_rule[catch_op];
1742
1743 if( newrule < NUM_OPERANDS ) {
1744 // Chain from operand or operand class, may be output of shared node
1745 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1746 "Bad AD file: Instruction chain rule must chain from operand");
1747 // Insert operand into array of operands for this instruction
1748 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1749
1750 ReduceOper( s, newrule, mem, mach );
1751 } else {
1752 // Chain from the result of an instruction
1753 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1754 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1755 Node *mem1 = (Node*)1;
1756 debug_only(Node *save_mem_node = _mem_node;)
1757 mach->add_req( ReduceInst(s, newrule, mem1) );
1758 debug_only(_mem_node = save_mem_node;)
1759 }
1760 return;
1761 }
1762
1763
1764 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1765 if( s->_leaf->is_Load() ) {
1766 Node *mem2 = s->_leaf->in(MemNode::Memory);
1767 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1768 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1769 mem = mem2;
1770 }
1771 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1772 if( mach->in(0) == NULL )
1773 mach->set_req(0, s->_leaf->in(0));
1774 }
1775
1776 // Now recursively walk the state tree & add operand list.
1777 for( uint i=0; i<2; i++ ) { // binary tree
1778 State *newstate = s->_kids[i];
1779 if( newstate == NULL ) break; // Might only have 1 child
1780 // 'op' is what I am expecting to receive
1781 int op;
1782 if( i == 0 ) {
1783 op = _leftOp[rule];
1784 } else {
1785 op = _rightOp[rule];
1786 }
1787 // Operand type to catch childs result
1788 // This is what my child will give me.
1789 int opnd_class_instance = newstate->_rule[op];
1790 // Choose between operand class or not.
1791 // This is what I will receive.
1792 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1793 // New rule for child. Chase operand classes to get the actual rule.
1794 int newrule = newstate->_rule[catch_op];
1795
1796 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1797 // Operand/operandClass
1798 // Insert operand into array of operands for this instruction
1799 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1800 ReduceOper( newstate, newrule, mem, mach );
1801
1802 } else { // Child is internal operand or new instruction
1803 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1804 // internal operand --> call ReduceInst_Interior
1805 // Interior of complex instruction. Do nothing but recurse.
1806 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1807 } else {
1808 // instruction --> call build operand( ) to catch result
1809 // --> ReduceInst( newrule )
1810 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1811 Node *mem1 = (Node*)1;
1812 debug_only(Node *save_mem_node = _mem_node;)
1813 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1814 debug_only(_mem_node = save_mem_node;)
1815 }
1816 }
1817 assert( mach->_opnds[num_opnds-1], "" );
1818 }
1819 return num_opnds;
1820 }
1821
1822 // This routine walks the interior of possible complex operands.
1823 // At each point we check our children in the match tree:
1824 // (1) No children -
1825 // We are a leaf; add _leaf field as an input to the MachNode
1826 // (2) Child is an internal operand -
1827 // Skip over it ( do nothing )
1828 // (3) Child is an instruction -
1829 // Call ReduceInst recursively and
1830 // and instruction as an input to the MachNode
1831 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1832 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1833 State *kid = s->_kids[0];
1834 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1835
1836 // Leaf? And not subsumed?
1837 if( kid == NULL && !_swallowed[rule] ) {
1838 mach->add_req( s->_leaf ); // Add leaf pointer
1839 return; // Bail out
1840 }
1841
1842 if( s->_leaf->is_Load() ) {
1843 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1844 mem = s->_leaf->in(MemNode::Memory);
1845 debug_only(_mem_node = s->_leaf;)
1846 }
1847 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1848 if( !mach->in(0) )
1849 mach->set_req(0,s->_leaf->in(0));
1850 else {
1851 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1852 }
1853 }
1854
1855 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1856 int newrule;
1857 if( i == 0 )
1858 newrule = kid->_rule[_leftOp[rule]];
1859 else
1860 newrule = kid->_rule[_rightOp[rule]];
1861
1862 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1863 // Internal operand; recurse but do nothing else
1864 ReduceOper( kid, newrule, mem, mach );
1865
1866 } else { // Child is a new instruction
1867 // Reduce the instruction, and add a direct pointer from this
1868 // machine instruction to the newly reduced one.
1869 Node *mem1 = (Node*)1;
1870 debug_only(Node *save_mem_node = _mem_node;)
1871 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1872 debug_only(_mem_node = save_mem_node;)
1873 }
1874 }
1875 }
1876
1877
1878 // -------------------------------------------------------------------------
1879 // Java-Java calling convention
1880 // (what you use when Java calls Java)
1881
1882 //------------------------------find_receiver----------------------------------
1883 // For a given signature, return the OptoReg for parameter 0.
1884 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1885 VMRegPair regs;
1886 BasicType sig_bt = T_OBJECT;
1887 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1888 // Return argument 0 register. In the LP64 build pointers
1889 // take 2 registers, but the VM wants only the 'main' name.
1890 return OptoReg::as_OptoReg(regs.first());
1891 }
1892
1893 // A method-klass-holder may be passed in the inline_cache_reg
1894 // and then expanded into the inline_cache_reg and a method_oop register
1895 // defined in ad_<arch>.cpp
1896
1897
1898 //------------------------------find_shared------------------------------------
1899 // Set bits if Node is shared or otherwise a root
1900 void Matcher::find_shared( Node *n ) {
1901 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1902 MStack mstack(C->unique() * 2);
1903 // Mark nodes as address_visited if they are inputs to an address expression
1904 VectorSet address_visited(Thread::current()->resource_area());
1905 mstack.push(n, Visit); // Don't need to pre-visit root node
1906 while (mstack.is_nonempty()) {
1907 n = mstack.node(); // Leave node on stack
1908 Node_State nstate = mstack.state();
1909 uint nop = n->Opcode();
1910 if (nstate == Pre_Visit) {
1911 if (address_visited.test(n->_idx)) { // Visited in address already?
1912 // Flag as visited and shared now.
1913 set_visited(n);
1914 }
1915 if (is_visited(n)) { // Visited already?
1916 // Node is shared and has no reason to clone. Flag it as shared.
1917 // This causes it to match into a register for the sharing.
1918 set_shared(n); // Flag as shared and
1919 mstack.pop(); // remove node from stack
1920 continue;
1921 }
1922 nstate = Visit; // Not already visited; so visit now
1923 }
1924 if (nstate == Visit) {
1925 mstack.set_state(Post_Visit);
1926 set_visited(n); // Flag as visited now
1927 bool mem_op = false;
1928
1929 switch( nop ) { // Handle some opcodes special
1930 case Op_Phi: // Treat Phis as shared roots
1931 case Op_Parm:
1932 case Op_Proj: // All handled specially during matching
1933 case Op_SafePointScalarObject:
1934 set_shared(n);
1935 set_dontcare(n);
1936 break;
1937 case Op_If:
1938 case Op_CountedLoopEnd:
1939 mstack.set_state(Alt_Post_Visit); // Alternative way
1940 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1941 // with matching cmp/branch in 1 instruction. The Matcher needs the
1942 // Bool and CmpX side-by-side, because it can only get at constants
1943 // that are at the leaves of Match trees, and the Bool's condition acts
1944 // as a constant here.
1945 mstack.push(n->in(1), Visit); // Clone the Bool
1946 mstack.push(n->in(0), Pre_Visit); // Visit control input
1947 continue; // while (mstack.is_nonempty())
1948 case Op_ConvI2D: // These forms efficiently match with a prior
1949 case Op_ConvI2F: // Load but not a following Store
1950 if( n->in(1)->is_Load() && // Prior load
1951 n->outcnt() == 1 && // Not already shared
1952 n->unique_out()->is_Store() ) // Following store
1953 set_shared(n); // Force it to be a root
1954 break;
1955 case Op_ReverseBytesI:
1956 case Op_ReverseBytesL:
1957 if( n->in(1)->is_Load() && // Prior load
1958 n->outcnt() == 1 ) // Not already shared
1959 set_shared(n); // Force it to be a root
1960 break;
1961 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1962 case Op_IfFalse:
1963 case Op_IfTrue:
1964 case Op_MachProj:
1965 case Op_MergeMem:
1966 case Op_Catch:
1967 case Op_CatchProj:
1968 case Op_CProj:
1969 case Op_JumpProj:
1970 case Op_JProj:
1971 case Op_NeverBranch:
1972 set_dontcare(n);
1973 break;
1974 case Op_Jump:
1975 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
1976 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1977 continue; // while (mstack.is_nonempty())
1978 case Op_StrComp:
1979 case Op_StrEquals:
1980 case Op_StrIndexOf:
1981 case Op_AryEq:
1982 set_shared(n); // Force result into register (it will be anyways)
1983 break;
1984 case Op_ConP: { // Convert pointers above the centerline to NUL
1985 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1986 const TypePtr* tp = tn->type()->is_ptr();
1987 if (tp->_ptr == TypePtr::AnyNull) {
1988 tn->set_type(TypePtr::NULL_PTR);
1989 }
1990 break;
1991 }
1992 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1993 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1994 const TypePtr* tp = tn->type()->make_ptr();
1995 if (tp && tp->_ptr == TypePtr::AnyNull) {
1996 tn->set_type(TypeNarrowOop::NULL_PTR);
1997 }
1998 break;
1999 }
2000 case Op_Binary: // These are introduced in the Post_Visit state.
2001 ShouldNotReachHere();
2002 break;
2003 case Op_ClearArray:
2004 case Op_SafePoint:
2005 mem_op = true;
2006 break;
2007 default:
2008 if( n->is_Store() ) {
2009 // Do match stores, despite no ideal reg
2010 mem_op = true;
2011 break;
2012 }
2013 if( n->is_Mem() ) { // Loads and LoadStores
2014 mem_op = true;
2015 // Loads must be root of match tree due to prior load conflict
2016 if( C->subsume_loads() == false )
2017 set_shared(n);
2018 }
2019 // Fall into default case
2020 if( !n->ideal_reg() )
2021 set_dontcare(n); // Unmatchable Nodes
2022 } // end_switch
2023
2024 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2025 Node *m = n->in(i); // Get ith input
2026 if (m == NULL) continue; // Ignore NULLs
2027 uint mop = m->Opcode();
2028
2029 // Must clone all producers of flags, or we will not match correctly.
2030 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2031 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2032 // are also there, so we may match a float-branch to int-flags and
2033 // expect the allocator to haul the flags from the int-side to the
2034 // fp-side. No can do.
2035 if( _must_clone[mop] ) {
2036 mstack.push(m, Visit);
2037 continue; // for(int i = ...)
2038 }
2039
2040 if( mop == Op_AddP && m->in(AddPNode::Base)->Opcode() == Op_DecodeN ) {
2041 // Bases used in addresses must be shared but since
2042 // they are shared through a DecodeN they may appear
2043 // to have a single use so force sharing here.
2044 set_shared(m->in(AddPNode::Base)->in(1));
2045 }
2046
2047 // Clone addressing expressions as they are "free" in memory access instructions
2048 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2049 // Some inputs for address expression are not put on stack
2050 // to avoid marking them as shared and forcing them into register
2051 // if they are used only in address expressions.
2052 // But they should be marked as shared if there are other uses
2053 // besides address expressions.
2054
2055 Node *off = m->in(AddPNode::Offset);
2056 if( off->is_Con() &&
2057 // When there are other uses besides address expressions
2058 // put it on stack and mark as shared.
2059 !is_visited(m) ) {
2060 address_visited.test_set(m->_idx); // Flag as address_visited
2061 Node *adr = m->in(AddPNode::Address);
2062
2063 // Intel, ARM and friends can handle 2 adds in addressing mode
2064 if( clone_shift_expressions && adr->is_AddP() &&
2065 // AtomicAdd is not an addressing expression.
2066 // Cheap to find it by looking for screwy base.
2067 !adr->in(AddPNode::Base)->is_top() &&
2068 // Are there other uses besides address expressions?
2069 !is_visited(adr) ) {
2070 address_visited.set(adr->_idx); // Flag as address_visited
2071 Node *shift = adr->in(AddPNode::Offset);
2072 // Check for shift by small constant as well
2073 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2074 shift->in(2)->get_int() <= 3 &&
2075 // Are there other uses besides address expressions?
2076 !is_visited(shift) ) {
2077 address_visited.set(shift->_idx); // Flag as address_visited
2078 mstack.push(shift->in(2), Visit);
2079 Node *conv = shift->in(1);
2080 #ifdef _LP64
2081 // Allow Matcher to match the rule which bypass
2082 // ConvI2L operation for an array index on LP64
2083 // if the index value is positive.
2084 if( conv->Opcode() == Op_ConvI2L &&
2085 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2086 // Are there other uses besides address expressions?
2087 !is_visited(conv) ) {
2088 address_visited.set(conv->_idx); // Flag as address_visited
2089 mstack.push(conv->in(1), Pre_Visit);
2090 } else
2091 #endif
2092 mstack.push(conv, Pre_Visit);
2093 } else {
2094 mstack.push(shift, Pre_Visit);
2095 }
2096 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2097 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2098 } else { // Sparc, Alpha, PPC and friends
2099 mstack.push(adr, Pre_Visit);
2100 }
2101
2102 // Clone X+offset as it also folds into most addressing expressions
2103 mstack.push(off, Visit);
2104 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2105 continue; // for(int i = ...)
2106 } // if( off->is_Con() )
2107 } // if( mem_op &&
2108 mstack.push(m, Pre_Visit);
2109 } // for(int i = ...)
2110 }
2111 else if (nstate == Alt_Post_Visit) {
2112 mstack.pop(); // Remove node from stack
2113 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2114 // shared and all users of the Bool need to move the Cmp in parallel.
2115 // This leaves both the Bool and the If pointing at the Cmp. To
2116 // prevent the Matcher from trying to Match the Cmp along both paths
2117 // BoolNode::match_edge always returns a zero.
2118
2119 // We reorder the Op_If in a pre-order manner, so we can visit without
2120 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2121 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2122 }
2123 else if (nstate == Post_Visit) {
2124 mstack.pop(); // Remove node from stack
2125
2126 // Now hack a few special opcodes
2127 switch( n->Opcode() ) { // Handle some opcodes special
2128 case Op_StorePConditional:
2129 case Op_StoreIConditional:
2130 case Op_StoreLConditional:
2131 case Op_CompareAndSwapI:
2132 case Op_CompareAndSwapL:
2133 case Op_CompareAndSwapP:
2134 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2135 Node *newval = n->in(MemNode::ValueIn );
2136 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
2137 Node *pair = new (C, 3) BinaryNode( oldval, newval );
2138 n->set_req(MemNode::ValueIn,pair);
2139 n->del_req(LoadStoreNode::ExpectedIn);
2140 break;
2141 }
2142 case Op_CMoveD: // Convert trinary to binary-tree
2143 case Op_CMoveF:
2144 case Op_CMoveI:
2145 case Op_CMoveL:
2146 case Op_CMoveN:
2147 case Op_CMoveP: {
2148 // Restructure into a binary tree for Matching. It's possible that
2149 // we could move this code up next to the graph reshaping for IfNodes
2150 // or vice-versa, but I do not want to debug this for Ladybird.
2151 // 10/2/2000 CNC.
2152 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
2153 n->set_req(1,pair1);
2154 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2155 n->set_req(2,pair2);
2156 n->del_req(3);
2157 break;
2158 }
2159 case Op_LoopLimit: {
2160 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(2));
2161 n->set_req(1,pair1);
2162 n->set_req(2,n->in(3));
2163 n->del_req(3);
2164 break;
2165 }
2166 case Op_StrEquals: {
2167 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2168 n->set_req(2,pair1);
2169 n->set_req(3,n->in(4));
2170 n->del_req(4);
2171 break;
2172 }
2173 case Op_StrComp:
2174 case Op_StrIndexOf: {
2175 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2176 n->set_req(2,pair1);
2177 Node *pair2 = new (C, 3) BinaryNode(n->in(4),n->in(5));
2178 n->set_req(3,pair2);
2179 n->del_req(5);
2180 n->del_req(4);
2181 break;
2182 }
2183 default:
2184 break;
2185 }
2186 }
2187 else {
2188 ShouldNotReachHere();
2189 }
2190 } // end of while (mstack.is_nonempty())
2191 }
2192
2193 #ifdef ASSERT
2194 // machine-independent root to machine-dependent root
2195 void Matcher::dump_old2new_map() {
2196 _old2new_map.dump();
2197 }
2198 #endif
2199
2200 //---------------------------collect_null_checks-------------------------------
2201 // Find null checks in the ideal graph; write a machine-specific node for
2202 // it. Used by later implicit-null-check handling. Actually collects
2203 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2204 // value being tested.
2205 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2206 Node *iff = proj->in(0);
2207 if( iff->Opcode() == Op_If ) {
2208 // During matching If's have Bool & Cmp side-by-side
2209 BoolNode *b = iff->in(1)->as_Bool();
2210 Node *cmp = iff->in(2);
2211 int opc = cmp->Opcode();
2212 if (opc != Op_CmpP && opc != Op_CmpN) return;
2213
2214 const Type* ct = cmp->in(2)->bottom_type();
2215 if (ct == TypePtr::NULL_PTR ||
2216 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2217
2218 bool push_it = false;
2219 if( proj->Opcode() == Op_IfTrue ) {
2220 extern int all_null_checks_found;
2221 all_null_checks_found++;
2222 if( b->_test._test == BoolTest::ne ) {
2223 push_it = true;
2224 }
2225 } else {
2226 assert( proj->Opcode() == Op_IfFalse, "" );
2227 if( b->_test._test == BoolTest::eq ) {
2228 push_it = true;
2229 }
2230 }
2231 if( push_it ) {
2232 _null_check_tests.push(proj);
2233 Node* val = cmp->in(1);
2234 #ifdef _LP64
2235 if (val->bottom_type()->isa_narrowoop() &&
2236 !Matcher::narrow_oop_use_complex_address()) {
2237 //
2238 // Look for DecodeN node which should be pinned to orig_proj.
2239 // On platforms (Sparc) which can not handle 2 adds
2240 // in addressing mode we have to keep a DecodeN node and
2241 // use it to do implicit NULL check in address.
2242 //
2243 // DecodeN node was pinned to non-null path (orig_proj) during
2244 // CastPP transformation in final_graph_reshaping_impl().
2245 //
2246 uint cnt = orig_proj->outcnt();
2247 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2248 Node* d = orig_proj->raw_out(i);
2249 if (d->is_DecodeN() && d->in(1) == val) {
2250 val = d;
2251 val->set_req(0, NULL); // Unpin now.
2252 // Mark this as special case to distinguish from
2253 // a regular case: CmpP(DecodeN, NULL).
2254 val = (Node*)(((intptr_t)val) | 1);
2255 break;
2256 }
2257 }
2258 }
2259 #endif
2260 _null_check_tests.push(val);
2261 }
2262 }
2263 }
2264 }
2265
2266 //---------------------------validate_null_checks------------------------------
2267 // Its possible that the value being NULL checked is not the root of a match
2268 // tree. If so, I cannot use the value in an implicit null check.
2269 void Matcher::validate_null_checks( ) {
2270 uint cnt = _null_check_tests.size();
2271 for( uint i=0; i < cnt; i+=2 ) {
2272 Node *test = _null_check_tests[i];
2273 Node *val = _null_check_tests[i+1];
2274 bool is_decoden = ((intptr_t)val) & 1;
2275 val = (Node*)(((intptr_t)val) & ~1);
2276 if (has_new_node(val)) {
2277 Node* new_val = new_node(val);
2278 if (is_decoden) {
2279 assert(val->is_DecodeN() && val->in(0) == NULL, "sanity");
2280 // Note: new_val may have a control edge if
2281 // the original ideal node DecodeN was matched before
2282 // it was unpinned in Matcher::collect_null_checks().
2283 // Unpin the mach node and mark it.
2284 new_val->set_req(0, NULL);
2285 new_val = (Node*)(((intptr_t)new_val) | 1);
2286 }
2287 // Is a match-tree root, so replace with the matched value
2288 _null_check_tests.map(i+1, new_val);
2289 } else {
2290 // Yank from candidate list
2291 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2292 _null_check_tests.map(i,_null_check_tests[--cnt]);
2293 _null_check_tests.pop();
2294 _null_check_tests.pop();
2295 i-=2;
2296 }
2297 }
2298 }
2299
2300 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2301 // atomic instruction acting as a store_load barrier without any
2302 // intervening volatile load, and thus we don't need a barrier here.
2303 // We retain the Node to act as a compiler ordering barrier.
2304 bool Matcher::post_store_load_barrier(const Node *vmb) {
2305 Compile *C = Compile::current();
2306 assert( vmb->is_MemBar(), "" );
2307 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2308 const MemBarNode *mem = (const MemBarNode*)vmb;
2309
2310 // Get the Proj node, ctrl, that can be used to iterate forward
2311 Node *ctrl = NULL;
2312 DUIterator_Fast imax, i = mem->fast_outs(imax);
2313 while( true ) {
2314 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2315 assert( ctrl->is_Proj(), "only projections here" );
2316 ProjNode *proj = (ProjNode*)ctrl;
2317 if( proj->_con == TypeFunc::Control &&
2318 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2319 break;
2320 i++;
2321 }
2322
2323 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2324 Node *x = ctrl->fast_out(j);
2325 int xop = x->Opcode();
2326
2327 // We don't need current barrier if we see another or a lock
2328 // before seeing volatile load.
2329 //
2330 // Op_Fastunlock previously appeared in the Op_* list below.
2331 // With the advent of 1-0 lock operations we're no longer guaranteed
2332 // that a monitor exit operation contains a serializing instruction.
2333
2334 if (xop == Op_MemBarVolatile ||
2335 xop == Op_FastLock ||
2336 xop == Op_CompareAndSwapL ||
2337 xop == Op_CompareAndSwapP ||
2338 xop == Op_CompareAndSwapN ||
2339 xop == Op_CompareAndSwapI)
2340 return true;
2341
2342 if (x->is_MemBar()) {
2343 // We must retain this membar if there is an upcoming volatile
2344 // load, which will be preceded by acquire membar.
2345 if (xop == Op_MemBarAcquire)
2346 return false;
2347 // For other kinds of barriers, check by pretending we
2348 // are them, and seeing if we can be removed.
2349 else
2350 return post_store_load_barrier((const MemBarNode*)x);
2351 }
2352
2353 // Delicate code to detect case of an upcoming fastlock block
2354 if( x->is_If() && x->req() > 1 &&
2355 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2356 Node *iff = x;
2357 Node *bol = iff->in(1);
2358 // The iff might be some random subclass of If or bol might be Con-Top
2359 if (!bol->is_Bool()) return false;
2360 assert( bol->req() > 1, "" );
2361 return (bol->in(1)->Opcode() == Op_FastUnlock);
2362 }
2363 // probably not necessary to check for these
2364 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2365 return false;
2366 }
2367 return false;
2368 }
2369
2370 //=============================================================================
2371 //---------------------------State---------------------------------------------
2372 State::State(void) {
2373 #ifdef ASSERT
2374 _id = 0;
2375 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2376 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2377 //memset(_cost, -1, sizeof(_cost));
2378 //memset(_rule, -1, sizeof(_rule));
2379 #endif
2380 memset(_valid, 0, sizeof(_valid));
2381 }
2382
2383 #ifdef ASSERT
2384 State::~State() {
2385 _id = 99;
2386 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2387 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2388 memset(_cost, -3, sizeof(_cost));
2389 memset(_rule, -3, sizeof(_rule));
2390 }
2391 #endif
2392
2393 #ifndef PRODUCT
2394 //---------------------------dump----------------------------------------------
2395 void State::dump() {
2396 tty->print("\n");
2397 dump(0);
2398 }
2399
2400 void State::dump(int depth) {
2401 for( int j = 0; j < depth; j++ )
2402 tty->print(" ");
2403 tty->print("--N: ");
2404 _leaf->dump();
2405 uint i;
2406 for( i = 0; i < _LAST_MACH_OPER; i++ )
2407 // Check for valid entry
2408 if( valid(i) ) {
2409 for( int j = 0; j < depth; j++ )
2410 tty->print(" ");
2411 assert(_cost[i] != max_juint, "cost must be a valid value");
2412 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2413 tty->print_cr("%s %d %s",
2414 ruleName[i], _cost[i], ruleName[_rule[i]] );
2415 }
2416 tty->print_cr("");
2417
2418 for( i=0; i<2; i++ )
2419 if( _kids[i] )
2420 _kids[i]->dump(depth+1);
2421 }
2422 #endif