1 /* 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "libadt/vectset.hpp" 27 #include "memory/allocation.inline.hpp" 28 #include "opto/addnode.hpp" 29 #include "opto/c2compiler.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/cfgnode.hpp" 32 #include "opto/chaitin.hpp" 33 #include "opto/loopnode.hpp" 34 #include "opto/machnode.hpp" 35 36 //------------------------------Split-------------------------------------- 37 // Walk the graph in RPO and for each lrg which spills, propagate reaching 38 // definitions. During propagation, split the live range around regions of 39 // High Register Pressure (HRP). If a Def is in a region of Low Register 40 // Pressure (LRP), it will not get spilled until we encounter a region of 41 // HRP between it and one of its uses. We will spill at the transition 42 // point between LRP and HRP. Uses in the HRP region will use the spilled 43 // Def. The first Use outside the HRP region will generate a SpillCopy to 44 // hoist the live range back up into a register, and all subsequent uses 45 // will use that new Def until another HRP region is encountered. Defs in 46 // HRP regions will get trailing SpillCopies to push the LRG down into the 47 // stack immediately. 48 // 49 // As a side effect, unlink from (hence make dead) coalesced copies. 50 // 51 52 static const char out_of_nodes[] = "out of nodes during split"; 53 54 //------------------------------get_spillcopy_wide----------------------------- 55 // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the 56 // wide ideal-register spill-mask if possible. If the 'wide-mask' does 57 // not cover the input (or output), use the input (or output) mask instead. 58 Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { 59 // If ideal reg doesn't exist we've got a bad schedule happening 60 // that is forcing us to spill something that isn't spillable. 61 // Bail rather than abort 62 int ireg = def->ideal_reg(); 63 if( ireg == 0 || ireg == Op_RegFlags ) { 64 assert(false, "attempted to spill a non-spillable item"); 65 C->record_method_not_compilable("attempted to spill a non-spillable item"); 66 return NULL; 67 } 68 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 69 return NULL; 70 } 71 const RegMask *i_mask = &def->out_RegMask(); 72 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg]; 73 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask; 74 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask; 75 const RegMask *w_o_mask; 76 77 int num_regs = RegMask::num_registers(ireg); 78 bool is_vect = RegMask::is_vector(ireg); 79 if( w_mask->overlap( *o_mask ) && // Overlap AND 80 ((num_regs == 1) // Single use or aligned 81 || is_vect // or vector 82 || !is_vect && o_mask->is_aligned_pairs()) ) { 83 assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned"); 84 // Don't come here for mis-aligned doubles 85 w_o_mask = w_mask; 86 } else { // wide ideal mask does not overlap with o_mask 87 // Mis-aligned doubles come here and XMM->FPR moves on x86. 88 w_o_mask = o_mask; // Must target desired registers 89 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use 90 // a reg-reg move or do I need a trip across register classes 91 // (and thus through memory)? 92 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() ) 93 // Here we assume a trip through memory is required. 94 w_i_mask = &C->FIRST_STACK_mask(); 95 } 96 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); 97 } 98 99 //------------------------------insert_proj------------------------------------ 100 // Insert the spill at chosen location. Skip over any intervening Proj's or 101 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block 102 // instead. Update high-pressure indices. Create a new live range. 103 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) { 104 // Skip intervening ProjNodes. Do not insert between a ProjNode and 105 // its definer. 106 while( i < b->_nodes.size() && 107 (b->_nodes[i]->is_Proj() || 108 b->_nodes[i]->is_Phi() ) ) 109 i++; 110 111 // Do not insert between a call and his Catch 112 if( b->_nodes[i]->is_Catch() ) { 113 // Put the instruction at the top of the fall-thru block. 114 // Find the fall-thru projection 115 while( 1 ) { 116 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj(); 117 if( cp->_con == CatchProjNode::fall_through_index ) 118 break; 119 } 120 int sidx = i - b->end_idx()-1; 121 b = b->_succs[sidx]; // Switch to successor block 122 i = 1; // Right at start of block 123 } 124 125 b->_nodes.insert(i,spill); // Insert node in block 126 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect 127 // Adjust the point where we go hi-pressure 128 if( i <= b->_ihrp_index ) b->_ihrp_index++; 129 if( i <= b->_fhrp_index ) b->_fhrp_index++; 130 131 // Assign a new Live Range Number to the SpillCopy and grow 132 // the node->live range mapping. 133 new_lrg(spill,maxlrg); 134 } 135 136 //------------------------------split_DEF-------------------------------------- 137 // There are four categories of Split; UP/DOWN x DEF/USE 138 // Only three of these really occur as DOWN/USE will always color 139 // Any Split with a DEF cannot CISC-Spill now. Thus we need 140 // two helper routines, one for Split DEFS (insert after instruction), 141 // one for Split USES (insert before instruction). DEF insertion 142 // happens inside Split, where the Leaveblock array is updated. 143 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) { 144 #ifdef ASSERT 145 // Increment the counter for this lrg 146 splits.at_put(slidx, splits.at(slidx)+1); 147 #endif 148 // If we are spilling the memory op for an implicit null check, at the 149 // null check location (ie - null check is in HRP block) we need to do 150 // the null-check first, then spill-down in the following block. 151 // (The implicit_null_check function ensures the use is also dominated 152 // by the branch-not-taken block.) 153 Node *be = b->end(); 154 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) { 155 // Spill goes in the branch-not-taken block 156 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue]; 157 loc = 0; // Just past the Region 158 } 159 assert( loc >= 0, "must insert past block head" ); 160 161 // Get a def-side SpillCopy 162 Node *spill = get_spillcopy_wide(def,NULL,0); 163 // Did we fail to split?, then bail 164 if (!spill) { 165 return 0; 166 } 167 168 // Insert the spill at chosen location 169 insert_proj( b, loc+1, spill, maxlrg++); 170 171 // Insert new node into Reaches array 172 Reachblock[slidx] = spill; 173 // Update debug list of reaching down definitions by adding this one 174 debug_defs[slidx] = spill; 175 176 // return updated count of live ranges 177 return maxlrg; 178 } 179 180 //------------------------------split_USE-------------------------------------- 181 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there. 182 // Debug uses want to know if def is already stack enabled. 183 uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) { 184 #ifdef ASSERT 185 // Increment the counter for this lrg 186 splits.at_put(slidx, splits.at(slidx)+1); 187 #endif 188 189 // Some setup stuff for handling debug node uses 190 JVMState* jvms = use->jvms(); 191 uint debug_start = jvms ? jvms->debug_start() : 999999; 192 uint debug_end = jvms ? jvms->debug_end() : 999999; 193 194 //------------------------------------------- 195 // Check for use of debug info 196 if (useidx >= debug_start && useidx < debug_end) { 197 // Actually it's perfectly legal for constant debug info to appear 198 // just unlikely. In this case the optimizer left a ConI of a 4 199 // as both inputs to a Phi with only a debug use. It's a single-def 200 // live range of a rematerializable value. The live range spills, 201 // rematerializes and now the ConI directly feeds into the debug info. 202 // assert(!def->is_Con(), "constant debug info already constructed directly"); 203 204 // Special split handling for Debug Info 205 // If DEF is DOWN, just hook the edge and return 206 // If DEF is UP, Split it DOWN for this USE. 207 if( def->is_Mach() ) { 208 if( def_down ) { 209 // DEF is DOWN, so connect USE directly to the DEF 210 use->set_req(useidx, def); 211 } else { 212 // Block and index where the use occurs. 213 Block *b = _cfg._bbs[use->_idx]; 214 // Put the clone just prior to use 215 int bindex = b->find_node(use); 216 // DEF is UP, so must copy it DOWN and hook in USE 217 // Insert SpillCopy before the USE, which uses DEF as its input, 218 // and defs a new live range, which is used by this node. 219 Node *spill = get_spillcopy_wide(def,use,useidx); 220 // did we fail to split? 221 if (!spill) { 222 // Bail 223 return 0; 224 } 225 // insert into basic block 226 insert_proj( b, bindex, spill, maxlrg++ ); 227 // Use the new split 228 use->set_req(useidx,spill); 229 } 230 // No further split handling needed for this use 231 return maxlrg; 232 } // End special splitting for debug info live range 233 } // If debug info 234 235 // CISC-SPILLING 236 // Finally, check to see if USE is CISC-Spillable, and if so, 237 // gather_lrg_masks will add the flags bit to its mask, and 238 // no use side copy is needed. This frees up the live range 239 // register choices without causing copy coalescing, etc. 240 if( UseCISCSpill && cisc_sp ) { 241 int inp = use->cisc_operand(); 242 if( inp != AdlcVMDeps::Not_cisc_spillable ) 243 // Convert operand number to edge index number 244 inp = use->as_Mach()->operand_index(inp); 245 if( inp == (int)useidx ) { 246 use->set_req(useidx, def); 247 #ifndef PRODUCT 248 if( TraceCISCSpill ) { 249 tty->print(" set_split: "); 250 use->dump(); 251 } 252 #endif 253 return maxlrg; 254 } 255 } 256 257 //------------------------------------------- 258 // Insert a Copy before the use 259 260 // Block and index where the use occurs. 261 int bindex; 262 // Phi input spill-copys belong at the end of the prior block 263 if( use->is_Phi() ) { 264 b = _cfg._bbs[b->pred(useidx)->_idx]; 265 bindex = b->end_idx(); 266 } else { 267 // Put the clone just prior to use 268 bindex = b->find_node(use); 269 } 270 271 Node *spill = get_spillcopy_wide( def, use, useidx ); 272 if( !spill ) return 0; // Bailed out 273 // Insert SpillCopy before the USE, which uses the reaching DEF as 274 // its input, and defs a new live range, which is used by this node. 275 insert_proj( b, bindex, spill, maxlrg++ ); 276 // Use the spill/clone 277 use->set_req(useidx,spill); 278 279 // return updated live range count 280 return maxlrg; 281 } 282 283 //------------------------------clone_node---------------------------- 284 // Clone node with anti dependence check. 285 Node* clone_node(Node* def, Block *b, Compile* C) { 286 if (def->needs_anti_dependence_check()) { 287 #ifdef ASSERT 288 if (Verbose) { 289 tty->print_cr("RA attempts to clone node with anti_dependence:"); 290 def->dump(-1); tty->cr(); 291 tty->print_cr("into block:"); 292 b->dump(); 293 } 294 #endif 295 if (C->subsume_loads() == true && !C->failing()) { 296 // Retry with subsume_loads == false 297 // If this is the first failure, the sentinel string will "stick" 298 // to the Compile object, and the C2Compiler will see it and retry. 299 C->record_failure(C2Compiler::retry_no_subsuming_loads()); 300 } else { 301 // Bailout without retry 302 C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence"); 303 } 304 return 0; 305 } 306 return def->clone(); 307 } 308 309 //------------------------------split_Rematerialize---------------------------- 310 // Clone a local copy of the def. 311 Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) { 312 // The input live ranges will be stretched to the site of the new 313 // instruction. They might be stretched past a def and will thus 314 // have the old and new values of the same live range alive at the 315 // same time - a definite no-no. Split out private copies of 316 // the inputs. 317 if( def->req() > 1 ) { 318 for( uint i = 1; i < def->req(); i++ ) { 319 Node *in = def->in(i); 320 // Check for single-def (LRG cannot redefined) 321 uint lidx = n2lidx(in); 322 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy 323 if (lrgs(lidx).is_singledef()) continue; 324 325 Block *b_def = _cfg._bbs[def->_idx]; 326 int idx_def = b_def->find_node(def); 327 Node *in_spill = get_spillcopy_wide( in, def, i ); 328 if( !in_spill ) return 0; // Bailed out 329 insert_proj(b_def,idx_def,in_spill,maxlrg++); 330 if( b_def == b ) 331 insidx++; 332 def->set_req(i,in_spill); 333 } 334 } 335 336 Node *spill = clone_node(def, b, C); 337 if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 338 // Check when generating nodes 339 return 0; 340 } 341 342 // See if any inputs are currently being spilled, and take the 343 // latest copy of spilled inputs. 344 if( spill->req() > 1 ) { 345 for( uint i = 1; i < spill->req(); i++ ) { 346 Node *in = spill->in(i); 347 uint lidx = Find_id(in); 348 349 // Walk backwards thru spill copy node intermediates 350 if (walkThru) { 351 while ( in->is_SpillCopy() && lidx >= _maxlrg ) { 352 in = in->in(1); 353 lidx = Find_id(in); 354 } 355 356 if (lidx < _maxlrg && lrgs(lidx).is_multidef()) { 357 // walkThru found a multidef LRG, which is unsafe to use, so 358 // just keep the original def used in the clone. 359 in = spill->in(i); 360 lidx = Find_id(in); 361 } 362 } 363 364 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) { 365 Node *rdef = Reachblock[lrg2reach[lidx]]; 366 if( rdef ) spill->set_req(i,rdef); 367 } 368 } 369 } 370 371 372 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" ); 373 // Rematerialized op is def->spilled+1 374 set_was_spilled(spill); 375 if( _spilled_once.test(def->_idx) ) 376 set_was_spilled(spill); 377 378 insert_proj( b, insidx, spill, maxlrg++ ); 379 #ifdef ASSERT 380 // Increment the counter for this lrg 381 splits.at_put(slidx, splits.at(slidx)+1); 382 #endif 383 // See if the cloned def kills any flags, and copy those kills as well 384 uint i = insidx+1; 385 if( clone_projs( b, i, def, spill, maxlrg ) ) { 386 // Adjust the point where we go hi-pressure 387 if( i <= b->_ihrp_index ) b->_ihrp_index++; 388 if( i <= b->_fhrp_index ) b->_fhrp_index++; 389 } 390 391 return spill; 392 } 393 394 //------------------------------is_high_pressure------------------------------- 395 // Function to compute whether or not this live range is "high pressure" 396 // in this block - whether it spills eagerly or not. 397 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) { 398 if( lrg->_was_spilled1 ) return true; 399 // Forced spilling due to conflict? Then split only at binding uses 400 // or defs, not for supposed capacity problems. 401 // CNC - Turned off 7/8/99, causes too much spilling 402 // if( lrg->_is_bound ) return false; 403 404 // Use float pressure numbers for vectors. 405 bool is_float_or_vector = lrg->_is_float || lrg->_is_vector; 406 // Not yet reached the high-pressure cutoff point, so low pressure 407 uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index; 408 if( insidx < hrp_idx ) return false; 409 // Register pressure for the block as a whole depends on reg class 410 int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure; 411 // Bound live ranges will split at the binding points first; 412 // Intermediate splits should assume the live range's register set 413 // got "freed up" and that num_regs will become INT_PRESSURE. 414 int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE; 415 // Effective register pressure limit. 416 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs()) 417 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres; 418 // High pressure if block pressure requires more register freedom 419 // than live range has. 420 return block_pres >= lrg_pres; 421 } 422 423 424 //------------------------------prompt_use--------------------------------- 425 // True if lidx is used before any real register is def'd in the block 426 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) { 427 if( lrgs(lidx)._was_spilled2 ) return false; 428 429 // Scan block for 1st use. 430 for( uint i = 1; i <= b->end_idx(); i++ ) { 431 Node *n = b->_nodes[i]; 432 // Ignore PHI use, these can be up or down 433 if( n->is_Phi() ) continue; 434 for( uint j = 1; j < n->req(); j++ ) 435 if( Find_id(n->in(j)) == lidx ) 436 return true; // Found 1st use! 437 if( n->out_RegMask().is_NotEmpty() ) return false; 438 } 439 return false; 440 } 441 442 //------------------------------Split-------------------------------------- 443 //----------Split Routine---------- 444 // ***** NEW SPLITTING HEURISTIC ***** 445 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there. 446 // Else, no split unless there is a HRP block between a DEF and 447 // one of its uses, and then split at the HRP block. 448 // 449 // USES: If USE is in HRP, split at use to leave main LRG on stack. 450 // Else, hoist LRG back up to register only (ie - split is also DEF) 451 // We will compute a new maxlrg as we go 452 uint PhaseChaitin::Split( uint maxlrg ) { 453 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); ) 454 455 uint bidx, pidx, slidx, insidx, inpidx, twoidx; 456 uint non_phi = 1, spill_cnt = 0; 457 Node **Reachblock; 458 Node *n1, *n2, *n3; 459 Node_List *defs,*phis; 460 bool *UPblock; 461 bool u1, u2, u3; 462 Block *b, *pred; 463 PhiNode *phi; 464 GrowableArray<uint> lidxs; 465 466 // Array of counters to count splits per live range 467 GrowableArray<uint> splits; 468 469 //----------Setup Code---------- 470 // Create a convenient mapping from lrg numbers to reaches/leaves indices 471 uint *lrg2reach = NEW_RESOURCE_ARRAY( uint, _maxlrg ); 472 // Keep track of DEFS & Phis for later passes 473 defs = new Node_List(); 474 phis = new Node_List(); 475 // Gather info on which LRG's are spilling, and build maps 476 for( bidx = 1; bidx < _maxlrg; bidx++ ) { 477 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { 478 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color"); 479 lrg2reach[bidx] = spill_cnt; 480 spill_cnt++; 481 lidxs.append(bidx); 482 #ifdef ASSERT 483 // Initialize the split counts to zero 484 splits.append(0); 485 #endif 486 #ifndef PRODUCT 487 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 ) 488 tty->print_cr("Warning, 2nd spill of L%d",bidx); 489 #endif 490 } 491 } 492 493 // Create side arrays for propagating reaching defs info. 494 // Each block needs a node pointer for each spilling live range for the 495 // Def which is live into the block. Phi nodes handle multiple input 496 // Defs by querying the output of their predecessor blocks and resolving 497 // them to a single Def at the phi. The pointer is updated for each 498 // Def in the block, and then becomes the output for the block when 499 // processing of the block is complete. We also need to track whether 500 // a Def is UP or DOWN. UP means that it should get a register (ie - 501 // it is always in LRP regions), and DOWN means that it is probably 502 // on the stack (ie - it crosses HRP regions). 503 Node ***Reaches = NEW_RESOURCE_ARRAY( Node**, _cfg._num_blocks+1 ); 504 bool **UP = NEW_RESOURCE_ARRAY( bool*, _cfg._num_blocks+1 ); 505 Node **debug_defs = NEW_RESOURCE_ARRAY( Node*, spill_cnt ); 506 VectorSet **UP_entry= NEW_RESOURCE_ARRAY( VectorSet*, spill_cnt ); 507 508 // Initialize Reaches & UP 509 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) { 510 Reaches[bidx] = NEW_RESOURCE_ARRAY( Node*, spill_cnt ); 511 UP[bidx] = NEW_RESOURCE_ARRAY( bool, spill_cnt ); 512 Node **Reachblock = Reaches[bidx]; 513 bool *UPblock = UP[bidx]; 514 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 515 UPblock[slidx] = true; // Assume they start in registers 516 Reachblock[slidx] = NULL; // Assume that no def is present 517 } 518 } 519 520 // Initialize to array of empty vectorsets 521 for( slidx = 0; slidx < spill_cnt; slidx++ ) 522 UP_entry[slidx] = new VectorSet(Thread::current()->resource_area()); 523 524 //----------PASS 1---------- 525 //----------Propagation & Node Insertion Code---------- 526 // Walk the Blocks in RPO for DEF & USE info 527 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 528 529 if (C->check_node_count(spill_cnt, out_of_nodes)) { 530 return 0; 531 } 532 533 b = _cfg._blocks[bidx]; 534 // Reaches & UP arrays for this block 535 Reachblock = Reaches[b->_pre_order]; 536 UPblock = UP[b->_pre_order]; 537 // Reset counter of start of non-Phi nodes in block 538 non_phi = 1; 539 //----------Block Entry Handling---------- 540 // Check for need to insert a new phi 541 // Cycle through this block's predecessors, collecting Reaches 542 // info for each spilled LRG. If they are identical, no phi is 543 // needed. If they differ, check for a phi, and insert if missing, 544 // or update edges if present. Set current block's Reaches set to 545 // be either the phi's or the reaching def, as appropriate. 546 // If no Phi is needed, check if the LRG needs to spill on entry 547 // to the block due to HRP. 548 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 549 // Grab the live range number 550 uint lidx = lidxs.at(slidx); 551 // Do not bother splitting or putting in Phis for single-def 552 // rematerialized live ranges. This happens alot to constants 553 // with long live ranges. 554 if( lrgs(lidx).is_singledef() && 555 lrgs(lidx)._def->rematerialize() ) { 556 // reset the Reaches & UP entries 557 Reachblock[slidx] = lrgs(lidx)._def; 558 UPblock[slidx] = true; 559 // Record following instruction in case 'n' rematerializes and 560 // kills flags 561 Block *pred1 = _cfg._bbs[b->pred(1)->_idx]; 562 continue; 563 } 564 565 // Initialize needs_phi and needs_split 566 bool needs_phi = false; 567 bool needs_split = false; 568 bool has_phi = false; 569 // Walk the predecessor blocks to check inputs for that live range 570 // Grab predecessor block header 571 n1 = b->pred(1); 572 // Grab the appropriate reaching def info for inpidx 573 pred = _cfg._bbs[n1->_idx]; 574 pidx = pred->_pre_order; 575 Node **Ltmp = Reaches[pidx]; 576 bool *Utmp = UP[pidx]; 577 n1 = Ltmp[slidx]; 578 u1 = Utmp[slidx]; 579 // Initialize node for saving type info 580 n3 = n1; 581 u3 = u1; 582 583 // Compare inputs to see if a Phi is needed 584 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) { 585 // Grab predecessor block headers 586 n2 = b->pred(inpidx); 587 // Grab the appropriate reaching def info for inpidx 588 pred = _cfg._bbs[n2->_idx]; 589 pidx = pred->_pre_order; 590 Ltmp = Reaches[pidx]; 591 Utmp = UP[pidx]; 592 n2 = Ltmp[slidx]; 593 u2 = Utmp[slidx]; 594 // For each LRG, decide if a phi is necessary 595 if( n1 != n2 ) { 596 needs_phi = true; 597 } 598 // See if the phi has mismatched inputs, UP vs. DOWN 599 if( n1 && n2 && (u1 != u2) ) { 600 needs_split = true; 601 } 602 // Move n2/u2 to n1/u1 for next iteration 603 n1 = n2; 604 u1 = u2; 605 // Preserve a non-NULL predecessor for later type referencing 606 if( (n3 == NULL) && (n2 != NULL) ){ 607 n3 = n2; 608 u3 = u2; 609 } 610 } // End for all potential Phi inputs 611 612 // check block for appropriate phinode & update edges 613 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 614 n1 = b->_nodes[insidx]; 615 // bail if this is not a phi 616 phi = n1->is_Phi() ? n1->as_Phi() : NULL; 617 if( phi == NULL ) { 618 // Keep track of index of first non-PhiNode instruction in block 619 non_phi = insidx; 620 // break out of the for loop as we have handled all phi nodes 621 break; 622 } 623 // must be looking at a phi 624 if( Find_id(n1) == lidxs.at(slidx) ) { 625 // found the necessary phi 626 needs_phi = false; 627 has_phi = true; 628 // initialize the Reaches entry for this LRG 629 Reachblock[slidx] = phi; 630 break; 631 } // end if found correct phi 632 } // end for all phi's 633 634 // If a phi is needed or exist, check for it 635 if( needs_phi || has_phi ) { 636 // add new phinode if one not already found 637 if( needs_phi ) { 638 // create a new phi node and insert it into the block 639 // type is taken from left over pointer to a predecessor 640 assert(n3,"No non-NULL reaching DEF for a Phi"); 641 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type()); 642 // initialize the Reaches entry for this LRG 643 Reachblock[slidx] = phi; 644 645 // add node to block & node_to_block mapping 646 insert_proj( b, insidx++, phi, maxlrg++ ); 647 non_phi++; 648 // Reset new phi's mapping to be the spilling live range 649 _names.map(phi->_idx, lidx); 650 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping"); 651 } // end if not found correct phi 652 // Here you have either found or created the Phi, so record it 653 assert(phi != NULL,"Must have a Phi Node here"); 654 phis->push(phi); 655 // PhiNodes should either force the LRG UP or DOWN depending 656 // on its inputs and the register pressure in the Phi's block. 657 UPblock[slidx] = true; // Assume new DEF is UP 658 // If entering a high-pressure area with no immediate use, 659 // assume Phi is DOWN 660 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) ) 661 UPblock[slidx] = false; 662 // If we are not split up/down and all inputs are down, then we 663 // are down 664 if( !needs_split && !u3 ) 665 UPblock[slidx] = false; 666 } // end if phi is needed 667 668 // Do not need a phi, so grab the reaching DEF 669 else { 670 // Grab predecessor block header 671 n1 = b->pred(1); 672 // Grab the appropriate reaching def info for k 673 pred = _cfg._bbs[n1->_idx]; 674 pidx = pred->_pre_order; 675 Node **Ltmp = Reaches[pidx]; 676 bool *Utmp = UP[pidx]; 677 // reset the Reaches & UP entries 678 Reachblock[slidx] = Ltmp[slidx]; 679 UPblock[slidx] = Utmp[slidx]; 680 } // end else no Phi is needed 681 } // end for all spilling live ranges 682 // DEBUG 683 #ifndef PRODUCT 684 if(trace_spilling()) { 685 tty->print("/`\nBlock %d: ", b->_pre_order); 686 tty->print("Reaching Definitions after Phi handling\n"); 687 for( uint x = 0; x < spill_cnt; x++ ) { 688 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]); 689 if( Reachblock[x] ) 690 Reachblock[x]->dump(); 691 else 692 tty->print("Undefined\n"); 693 } 694 } 695 #endif 696 697 //----------Non-Phi Node Splitting---------- 698 // Since phi-nodes have now been handled, the Reachblock array for this 699 // block is initialized with the correct starting value for the defs which 700 // reach non-phi instructions in this block. Thus, process non-phi 701 // instructions normally, inserting SpillCopy nodes for all spill 702 // locations. 703 704 // Memoize any DOWN reaching definitions for use as DEBUG info 705 for( insidx = 0; insidx < spill_cnt; insidx++ ) { 706 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx]; 707 if( UPblock[insidx] ) // Memoize UP decision at block start 708 UP_entry[insidx]->set( b->_pre_order ); 709 } 710 711 //----------Walk Instructions in the Block and Split---------- 712 // For all non-phi instructions in the block 713 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 714 Node *n = b->_nodes[insidx]; 715 // Find the defining Node's live range index 716 uint defidx = Find_id(n); 717 uint cnt = n->req(); 718 719 if( n->is_Phi() ) { 720 // Skip phi nodes after removing dead copies. 721 if( defidx < _maxlrg ) { 722 // Check for useless Phis. These appear if we spill, then 723 // coalesce away copies. Dont touch Phis in spilling live 724 // ranges; they are busy getting modifed in this pass. 725 if( lrgs(defidx).reg() < LRG::SPILL_REG ) { 726 uint i; 727 Node *u = NULL; 728 // Look for the Phi merging 2 unique inputs 729 for( i = 1; i < cnt; i++ ) { 730 // Ignore repeats and self 731 if( n->in(i) != u && n->in(i) != n ) { 732 // Found a unique input 733 if( u != NULL ) // If it's the 2nd, bail out 734 break; 735 u = n->in(i); // Else record it 736 } 737 } 738 assert( u, "at least 1 valid input expected" ); 739 if( i >= cnt ) { // Found one unique input 740 assert(Find_id(n) == Find_id(u), "should be the same lrg"); 741 n->replace_by(u); // Then replace with unique input 742 n->disconnect_inputs(NULL); 743 b->_nodes.remove(insidx); 744 insidx--; 745 b->_ihrp_index--; 746 b->_fhrp_index--; 747 } 748 } 749 } 750 continue; 751 } 752 assert( insidx > b->_ihrp_index || 753 (b->_reg_pressure < (uint)INTPRESSURE) || 754 b->_ihrp_index > 4000000 || 755 b->_ihrp_index >= b->end_idx() || 756 !b->_nodes[b->_ihrp_index]->is_Proj(), "" ); 757 assert( insidx > b->_fhrp_index || 758 (b->_freg_pressure < (uint)FLOATPRESSURE) || 759 b->_fhrp_index > 4000000 || 760 b->_fhrp_index >= b->end_idx() || 761 !b->_nodes[b->_fhrp_index]->is_Proj(), "" ); 762 763 // ********** Handle Crossing HRP Boundry ********** 764 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) { 765 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 766 // Check for need to split at HRP boundary - split if UP 767 n1 = Reachblock[slidx]; 768 // bail out if no reaching DEF 769 if( n1 == NULL ) continue; 770 // bail out if live range is 'isolated' around inner loop 771 uint lidx = lidxs.at(slidx); 772 // If live range is currently UP 773 if( UPblock[slidx] ) { 774 // set location to insert spills at 775 // SPLIT DOWN HERE - NO CISC SPILL 776 if( is_high_pressure( b, &lrgs(lidx), insidx ) && 777 !n1->rematerialize() ) { 778 // If there is already a valid stack definition available, use it 779 if( debug_defs[slidx] != NULL ) { 780 Reachblock[slidx] = debug_defs[slidx]; 781 } 782 else { 783 // Insert point is just past last use or def in the block 784 int insert_point = insidx-1; 785 while( insert_point > 0 ) { 786 Node *n = b->_nodes[insert_point]; 787 // Hit top of block? Quit going backwards 788 if( n->is_Phi() ) break; 789 // Found a def? Better split after it. 790 if( n2lidx(n) == lidx ) break; 791 // Look for a use 792 uint i; 793 for( i = 1; i < n->req(); i++ ) 794 if( n2lidx(n->in(i)) == lidx ) 795 break; 796 // Found a use? Better split after it. 797 if( i < n->req() ) break; 798 insert_point--; 799 } 800 uint orig_eidx = b->end_idx(); 801 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx); 802 // If it wasn't split bail 803 if (!maxlrg) { 804 return 0; 805 } 806 // Spill of NULL check mem op goes into the following block. 807 if (b->end_idx() > orig_eidx) 808 insidx++; 809 } 810 // This is a new DEF, so update UP 811 UPblock[slidx] = false; 812 #ifndef PRODUCT 813 // DEBUG 814 if( trace_spilling() ) { 815 tty->print("\nNew Split DOWN DEF of Spill Idx "); 816 tty->print("%d, UP %d:\n",slidx,false); 817 n1->dump(); 818 } 819 #endif 820 } 821 } // end if LRG is UP 822 } // end for all spilling live ranges 823 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" ); 824 } // end if crossing HRP Boundry 825 826 // If the LRG index is oob, then this is a new spillcopy, skip it. 827 if( defidx >= _maxlrg ) { 828 continue; 829 } 830 LRG &deflrg = lrgs(defidx); 831 uint copyidx = n->is_Copy(); 832 // Remove coalesced copy from CFG 833 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) { 834 n->replace_by( n->in(copyidx) ); 835 n->set_req( copyidx, NULL ); 836 b->_nodes.remove(insidx--); 837 b->_ihrp_index--; // Adjust the point where we go hi-pressure 838 b->_fhrp_index--; 839 continue; 840 } 841 842 #define DERIVED 0 843 844 // ********** Handle USES ********** 845 bool nullcheck = false; 846 // Implicit null checks never use the spilled value 847 if( n->is_MachNullCheck() ) 848 nullcheck = true; 849 if( !nullcheck ) { 850 // Search all inputs for a Spill-USE 851 JVMState* jvms = n->jvms(); 852 uint oopoff = jvms ? jvms->oopoff() : cnt; 853 uint old_last = cnt - 1; 854 for( inpidx = 1; inpidx < cnt; inpidx++ ) { 855 // Derived/base pairs may be added to our inputs during this loop. 856 // If inpidx > old_last, then one of these new inputs is being 857 // handled. Skip the derived part of the pair, but process 858 // the base like any other input. 859 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) { 860 continue; // skip derived_debug added below 861 } 862 // Get lidx of input 863 uint useidx = Find_id(n->in(inpidx)); 864 // Not a brand-new split, and it is a spill use 865 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) { 866 // Check for valid reaching DEF 867 slidx = lrg2reach[useidx]; 868 Node *def = Reachblock[slidx]; 869 assert( def != NULL, "Using Undefined Value in Split()\n"); 870 871 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp 872 // monitor references do not care where they live, so just hook 873 if ( jvms && jvms->is_monitor_use(inpidx) ) { 874 // The effect of this clone is to drop the node out of the block, 875 // so that the allocator does not see it anymore, and therefore 876 // does not attempt to assign it a register. 877 def = clone_node(def, b, C); 878 if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 879 return 0; 880 } 881 _names.extend(def->_idx,0); 882 _cfg._bbs.map(def->_idx,b); 883 n->set_req(inpidx, def); 884 continue; 885 } 886 887 // Rematerializable? Then clone def at use site instead 888 // of store/load 889 if( def->rematerialize() ) { 890 int old_size = b->_nodes.size(); 891 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true ); 892 if( !def ) return 0; // Bail out 893 insidx += b->_nodes.size()-old_size; 894 } 895 896 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL; 897 // Base pointers and oopmap references do not care where they live. 898 if ((inpidx >= oopoff) || 899 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) { 900 if (def->rematerialize() && lrgs(useidx)._was_spilled2) { 901 // This def has been rematerialized a couple of times without 902 // progress. It doesn't care if it lives UP or DOWN, so 903 // spill it down now. 904 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); 905 // If it wasn't split bail 906 if (!maxlrg) { 907 return 0; 908 } 909 insidx++; // Reset iterator to skip USE side split 910 } else { 911 // Just hook the def edge 912 n->set_req(inpidx, def); 913 } 914 915 if (inpidx >= oopoff) { 916 // After oopoff, we have derived/base pairs. We must mention all 917 // derived pointers here as derived/base pairs for GC. If the 918 // derived value is spilling and we have a copy both in Reachblock 919 // (called here 'def') and debug_defs[slidx] we need to mention 920 // both in derived/base pairs or kill one. 921 Node *derived_debug = debug_defs[slidx]; 922 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base? 923 mach && mach->ideal_Opcode() != Op_Halt && 924 derived_debug != NULL && 925 derived_debug != def ) { // Actual 2nd value appears 926 // We have already set 'def' as a derived value. 927 // Also set debug_defs[slidx] as a derived value. 928 uint k; 929 for( k = oopoff; k < cnt; k += 2 ) 930 if( n->in(k) == derived_debug ) 931 break; // Found an instance of debug derived 932 if( k == cnt ) {// No instance of debug_defs[slidx] 933 // Add a derived/base pair to cover the debug info. 934 // We have to process the added base later since it is not 935 // handled yet at this point but skip derived part. 936 assert(((n->req() - oopoff) & 1) == DERIVED, 937 "must match skip condition above"); 938 n->add_req( derived_debug ); // this will be skipped above 939 n->add_req( n->in(inpidx+1) ); // this will be processed 940 // Increment cnt to handle added input edges on 941 // subsequent iterations. 942 cnt += 2; 943 } 944 } 945 } 946 continue; 947 } 948 // Special logic for DEBUG info 949 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) { 950 uint debug_start = jvms->debug_start(); 951 // If this is debug info use & there is a reaching DOWN def 952 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) { 953 assert(inpidx < oopoff, "handle only debug info here"); 954 // Just hook it in & move on 955 n->set_req(inpidx, debug_defs[slidx]); 956 // (Note that this can make two sides of a split live at the 957 // same time: The debug def on stack, and another def in a 958 // register. The GC needs to know about both of them, but any 959 // derived pointers after oopoff will refer to only one of the 960 // two defs and the GC would therefore miss the other. Thus 961 // this hack is only allowed for debug info which is Java state 962 // and therefore never a derived pointer.) 963 continue; 964 } 965 } 966 // Grab register mask info 967 const RegMask &dmask = def->out_RegMask(); 968 const RegMask &umask = n->in_RegMask(inpidx); 969 bool is_vect = RegMask::is_vector(def->ideal_reg()); 970 assert(inpidx < oopoff, "cannot use-split oop map info"); 971 972 bool dup = UPblock[slidx]; 973 bool uup = umask.is_UP(); 974 975 // Need special logic to handle bound USES. Insert a split at this 976 // bound use if we can't rematerialize the def, or if we need the 977 // split to form a misaligned pair. 978 if( !umask.is_AllStack() && 979 (int)umask.Size() <= lrgs(useidx).num_regs() && 980 (!def->rematerialize() || 981 !is_vect && umask.is_misaligned_pair())) { 982 // These need a Split regardless of overlap or pressure 983 // SPLIT - NO DEF - NO CISC SPILL 984 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); 985 // If it wasn't split bail 986 if (!maxlrg) { 987 return 0; 988 } 989 insidx++; // Reset iterator to skip USE side split 990 continue; 991 } 992 993 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) { 994 // The use at the call can force the def down so insert 995 // a split before the use to allow the def more freedom. 996 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); 997 // If it wasn't split bail 998 if (!maxlrg) { 999 return 0; 1000 } 1001 insidx++; // Reset iterator to skip USE side split 1002 continue; 1003 } 1004 1005 // Here is the logic chart which describes USE Splitting: 1006 // 0 = false or DOWN, 1 = true or UP 1007 // 1008 // Overlap | DEF | USE | Action 1009 //------------------------------------------------------- 1010 // 0 | 0 | 0 | Copy - mem -> mem 1011 // 0 | 0 | 1 | Split-UP - Check HRP 1012 // 0 | 1 | 0 | Split-DOWN - Debug Info? 1013 // 0 | 1 | 1 | Copy - reg -> reg 1014 // 1 | 0 | 0 | Reset Input Edge (no Split) 1015 // 1 | 0 | 1 | Split-UP - Check HRP 1016 // 1 | 1 | 0 | Split-DOWN - Debug Info? 1017 // 1 | 1 | 1 | Reset Input Edge (no Split) 1018 // 1019 // So, if (dup == uup), then overlap test determines action, 1020 // with true being no split, and false being copy. Else, 1021 // if DEF is DOWN, Split-UP, and check HRP to decide on 1022 // resetting DEF. Finally if DEF is UP, Split-DOWN, with 1023 // special handling for Debug Info. 1024 if( dup == uup ) { 1025 if( dmask.overlap(umask) ) { 1026 // Both are either up or down, and there is overlap, No Split 1027 n->set_req(inpidx, def); 1028 } 1029 else { // Both are either up or down, and there is no overlap 1030 if( dup ) { // If UP, reg->reg copy 1031 // COPY ACROSS HERE - NO DEF - NO CISC SPILL 1032 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 1033 // If it wasn't split bail 1034 if (!maxlrg) { 1035 return 0; 1036 } 1037 insidx++; // Reset iterator to skip USE side split 1038 } 1039 else { // DOWN, mem->mem copy 1040 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL 1041 // First Split-UP to move value into Register 1042 uint def_ideal = def->ideal_reg(); 1043 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; 1044 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); 1045 insert_proj( b, insidx, spill, maxlrg ); 1046 // Then Split-DOWN as if previous Split was DEF 1047 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); 1048 // If it wasn't split bail 1049 if (!maxlrg) { 1050 return 0; 1051 } 1052 insidx += 2; // Reset iterator to skip USE side splits 1053 } 1054 } // End else no overlap 1055 } // End if dup == uup 1056 // dup != uup, so check dup for direction of Split 1057 else { 1058 if( dup ) { // If UP, Split-DOWN and check Debug Info 1059 // If this node is already a SpillCopy, just patch the edge 1060 // except the case of spilling to stack. 1061 if( n->is_SpillCopy() ) { 1062 RegMask tmp_rm(umask); 1063 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask); 1064 if( dmask.overlap(tmp_rm) ) { 1065 if( def != n->in(inpidx) ) { 1066 n->set_req(inpidx, def); 1067 } 1068 continue; 1069 } 1070 } 1071 // COPY DOWN HERE - NO DEF - NO CISC SPILL 1072 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 1073 // If it wasn't split bail 1074 if (!maxlrg) { 1075 return 0; 1076 } 1077 insidx++; // Reset iterator to skip USE side split 1078 // Check for debug-info split. Capture it for later 1079 // debug splits of the same value 1080 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff) 1081 debug_defs[slidx] = n->in(inpidx); 1082 1083 } 1084 else { // DOWN, Split-UP and check register pressure 1085 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { 1086 // COPY UP HERE - NO DEF - CISC SPILL 1087 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); 1088 // If it wasn't split bail 1089 if (!maxlrg) { 1090 return 0; 1091 } 1092 insidx++; // Reset iterator to skip USE side split 1093 } else { // LRP 1094 // COPY UP HERE - WITH DEF - NO CISC SPILL 1095 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); 1096 // If it wasn't split bail 1097 if (!maxlrg) { 1098 return 0; 1099 } 1100 // Flag this lift-up in a low-pressure block as 1101 // already-spilled, so if it spills again it will 1102 // spill hard (instead of not spilling hard and 1103 // coalescing away). 1104 set_was_spilled(n->in(inpidx)); 1105 // Since this is a new DEF, update Reachblock & UP 1106 Reachblock[slidx] = n->in(inpidx); 1107 UPblock[slidx] = true; 1108 insidx++; // Reset iterator to skip USE side split 1109 } 1110 } // End else DOWN 1111 } // End dup != uup 1112 } // End if Spill USE 1113 } // End For All Inputs 1114 } // End If not nullcheck 1115 1116 // ********** Handle DEFS ********** 1117 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or 1118 // just reset the Reaches info in LRP regions. DEFS must always update 1119 // UP info. 1120 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled? 1121 uint slidx = lrg2reach[defidx]; 1122 // Add to defs list for later assignment of new live range number 1123 defs->push(n); 1124 // Set a flag on the Node indicating it has already spilled. 1125 // Only do it for capacity spills not conflict spills. 1126 if( !deflrg._direct_conflict ) 1127 set_was_spilled(n); 1128 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list"); 1129 // Grab UP info for DEF 1130 const RegMask &dmask = n->out_RegMask(); 1131 bool defup = dmask.is_UP(); 1132 int ireg = n->ideal_reg(); 1133 bool is_vect = RegMask::is_vector(ireg); 1134 // Only split at Def if this is a HRP block or bound (and spilled once) 1135 if( !n->rematerialize() && 1136 (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) && 1137 (deflrg._direct_conflict || deflrg._must_spill)) || 1138 // Check for LRG being up in a register and we are inside a high 1139 // pressure area. Spill it down immediately. 1140 (defup && is_high_pressure(b,&deflrg,insidx))) ) { 1141 assert( !n->rematerialize(), "" ); 1142 assert( !n->is_SpillCopy(), "" ); 1143 // Do a split at the def site. 1144 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx ); 1145 // If it wasn't split bail 1146 if (!maxlrg) { 1147 return 0; 1148 } 1149 // Split DEF's Down 1150 UPblock[slidx] = 0; 1151 #ifndef PRODUCT 1152 // DEBUG 1153 if( trace_spilling() ) { 1154 tty->print("\nNew Split DOWN DEF of Spill Idx "); 1155 tty->print("%d, UP %d:\n",slidx,false); 1156 n->dump(); 1157 } 1158 #endif 1159 } 1160 else { // Neither bound nor HRP, must be LRP 1161 // otherwise, just record the def 1162 Reachblock[slidx] = n; 1163 // UP should come from the outRegmask() of the DEF 1164 UPblock[slidx] = defup; 1165 // Update debug list of reaching down definitions, kill if DEF is UP 1166 debug_defs[slidx] = defup ? NULL : n; 1167 #ifndef PRODUCT 1168 // DEBUG 1169 if( trace_spilling() ) { 1170 tty->print("\nNew DEF of Spill Idx "); 1171 tty->print("%d, UP %d:\n",slidx,defup); 1172 n->dump(); 1173 } 1174 #endif 1175 } // End else LRP 1176 } // End if spill def 1177 1178 // ********** Split Left Over Mem-Mem Moves ********** 1179 // Check for mem-mem copies and split them now. Do not do this 1180 // to copies about to be spilled; they will be Split shortly. 1181 if( copyidx ) { 1182 Node *use = n->in(copyidx); 1183 uint useidx = Find_id(use); 1184 if( useidx < _maxlrg && // This is not a new split 1185 OptoReg::is_stack(deflrg.reg()) && 1186 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack 1187 LRG &uselrg = lrgs(useidx); 1188 if( OptoReg::is_stack(uselrg.reg()) && 1189 uselrg.reg() < LRG::SPILL_REG && // USE is from stack 1190 deflrg.reg() != uselrg.reg() ) { // Not trivially removed 1191 uint def_ideal_reg = Matcher::base2reg[n->bottom_type()->base()]; 1192 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg]; 1193 const RegMask &use_rm = n->in_RegMask(copyidx); 1194 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL 1195 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes 1196 return 0; 1197 } 1198 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); 1199 n->set_req(copyidx,spill); 1200 n->as_MachSpillCopy()->set_in_RegMask(def_rm); 1201 // Put the spill just before the copy 1202 insert_proj( b, insidx++, spill, maxlrg++ ); 1203 } 1204 } 1205 } 1206 } 1207 } // End For All Instructions in Block - Non-PHI Pass 1208 1209 // Check if each LRG is live out of this block so as not to propagate 1210 // beyond the last use of a LRG. 1211 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1212 uint defidx = lidxs.at(slidx); 1213 IndexSet *liveout = _live->live(b); 1214 if( !liveout->member(defidx) ) { 1215 #ifdef ASSERT 1216 // The index defidx is not live. Check the liveout array to ensure that 1217 // it contains no members which compress to defidx. Finding such an 1218 // instance may be a case to add liveout adjustment in compress_uf_map(). 1219 // See 5063219. 1220 uint member; 1221 IndexSetIterator isi(liveout); 1222 while ((member = isi.next()) != 0) { 1223 assert(defidx != Find_const(member), "Live out member has not been compressed"); 1224 } 1225 #endif 1226 Reachblock[slidx] = NULL; 1227 } else { 1228 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value"); 1229 } 1230 } 1231 #ifndef PRODUCT 1232 if( trace_spilling() ) 1233 b->dump(); 1234 #endif 1235 } // End For All Blocks 1236 1237 //----------PASS 2---------- 1238 // Reset all DEF live range numbers here 1239 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1240 // Grab the def 1241 n1 = defs->at(insidx); 1242 // Set new lidx for DEF 1243 new_lrg(n1, maxlrg++); 1244 } 1245 //----------Phi Node Splitting---------- 1246 // Clean up a phi here, and assign a new live range number 1247 // Cycle through this block's predecessors, collecting Reaches 1248 // info for each spilled LRG and update edges. 1249 // Walk the phis list to patch inputs, split phis, and name phis 1250 uint lrgs_before_phi_split = maxlrg; 1251 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1252 Node *phi = phis->at(insidx); 1253 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1254 Block *b = _cfg._bbs[phi->_idx]; 1255 // Grab the live range number 1256 uint lidx = Find_id(phi); 1257 uint slidx = lrg2reach[lidx]; 1258 // Update node to lidx map 1259 new_lrg(phi, maxlrg++); 1260 // Get PASS1's up/down decision for the block. 1261 int phi_up = !!UP_entry[slidx]->test(b->_pre_order); 1262 1263 // Force down if double-spilling live range 1264 if( lrgs(lidx)._was_spilled1 ) 1265 phi_up = false; 1266 1267 // When splitting a Phi we an split it normal or "inverted". 1268 // An inverted split makes the splits target the Phi's UP/DOWN 1269 // sense inverted; then the Phi is followed by a final def-side 1270 // split to invert back. It changes which blocks the spill code 1271 // goes in. 1272 1273 // Walk the predecessor blocks and assign the reaching def to the Phi. 1274 // Split Phi nodes by placing USE side splits wherever the reaching 1275 // DEF has the wrong UP/DOWN value. 1276 for( uint i = 1; i < b->num_preds(); i++ ) { 1277 // Get predecessor block pre-order number 1278 Block *pred = _cfg._bbs[b->pred(i)->_idx]; 1279 pidx = pred->_pre_order; 1280 // Grab reaching def 1281 Node *def = Reaches[pidx][slidx]; 1282 assert( def, "must have reaching def" ); 1283 // If input up/down sense and reg-pressure DISagree 1284 if( def->rematerialize() ) { 1285 // Place the rematerialized node above any MSCs created during 1286 // phi node splitting. end_idx points at the insertion point 1287 // so look at the node before it. 1288 int insert = pred->end_idx(); 1289 while (insert >= 1 && 1290 pred->_nodes[insert - 1]->is_SpillCopy() && 1291 Find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) { 1292 insert--; 1293 } 1294 def = split_Rematerialize( def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false ); 1295 if( !def ) return 0; // Bail out 1296 } 1297 // Update the Phi's input edge array 1298 phi->set_req(i,def); 1299 // Grab the UP/DOWN sense for the input 1300 u1 = UP[pidx][slidx]; 1301 if( u1 != (phi_up != 0)) { 1302 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); 1303 // If it wasn't split bail 1304 if (!maxlrg) { 1305 return 0; 1306 } 1307 } 1308 } // End for all inputs to the Phi 1309 } // End for all Phi Nodes 1310 // Update _maxlrg to save Union asserts 1311 _maxlrg = maxlrg; 1312 1313 1314 //----------PASS 3---------- 1315 // Pass over all Phi's to union the live ranges 1316 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1317 Node *phi = phis->at(insidx); 1318 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1319 // Walk all inputs to Phi and Union input live range with Phi live range 1320 for( uint i = 1; i < phi->req(); i++ ) { 1321 // Grab the input node 1322 Node *n = phi->in(i); 1323 assert( n, "" ); 1324 uint lidx = Find(n); 1325 uint pidx = Find(phi); 1326 if( lidx < pidx ) 1327 Union(n, phi); 1328 else if( lidx > pidx ) 1329 Union(phi, n); 1330 } // End for all inputs to the Phi Node 1331 } // End for all Phi Nodes 1332 // Now union all two address instructions 1333 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1334 // Grab the def 1335 n1 = defs->at(insidx); 1336 // Set new lidx for DEF & handle 2-addr instructions 1337 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) { 1338 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index"); 1339 // Union the input and output live ranges 1340 uint lr1 = Find(n1); 1341 uint lr2 = Find(n1->in(twoidx)); 1342 if( lr1 < lr2 ) 1343 Union(n1, n1->in(twoidx)); 1344 else if( lr1 > lr2 ) 1345 Union(n1->in(twoidx), n1); 1346 } // End if two address 1347 } // End for all defs 1348 // DEBUG 1349 #ifdef ASSERT 1350 // Validate all live range index assignments 1351 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 1352 b = _cfg._blocks[bidx]; 1353 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) { 1354 Node *n = b->_nodes[insidx]; 1355 uint defidx = Find(n); 1356 assert(defidx < _maxlrg,"Bad live range index in Split"); 1357 assert(defidx < maxlrg,"Bad live range index in Split"); 1358 } 1359 } 1360 // Issue a warning if splitting made no progress 1361 int noprogress = 0; 1362 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1363 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) { 1364 tty->print_cr("Failed to split live range %d", lidxs.at(slidx)); 1365 //BREAKPOINT; 1366 } 1367 else { 1368 noprogress++; 1369 } 1370 } 1371 if(!noprogress) { 1372 tty->print_cr("Failed to make progress in Split"); 1373 //BREAKPOINT; 1374 } 1375 #endif 1376 // Return updated count of live ranges 1377 return maxlrg; 1378 }