*** old/src/share/vm/opto/reg_split.cpp	Sat Jun  2 20:04:19 2012
--- new/src/share/vm/opto/reg_split.cpp	Sat Jun  2 20:04:19 2012

*** 1,7 ****
--- 1,7 ----
  /*
!  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
!  * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.

*** 72,87 ****
--- 72,88 ----
    const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
    const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
    const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
    const RegMask *w_o_mask;
  
+   int num_regs = RegMask::num_registers(ireg);
+   bool is_vect = RegMask::is_vector(ireg);
    if( w_mask->overlap( *o_mask ) && // Overlap AND
!       ((ireg != Op_RegL && ireg != Op_RegD // Single use or aligned
  #ifdef _LP64
          && ireg != Op_RegP
  #endif
           ) || o_mask->is_aligned_Pairs()) ) {
!       ((num_regs == 1) // Single use or aligned
+         ||  is_vect    // or vector
+         || !is_vect && o_mask->is_aligned_pairs()) ) {
+     assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
      // Don't come here for mis-aligned doubles
      w_o_mask = w_mask;
    } else {                      // wide ideal mask does not overlap with o_mask
      // Mis-aligned doubles come here and XMM->FPR moves on x86.
      w_o_mask = o_mask;          // Must target desired registers

*** 398,416 ****
--- 399,419 ----
    // Forced spilling due to conflict?  Then split only at binding uses
    // or defs, not for supposed capacity problems.
    // CNC - Turned off 7/8/99, causes too much spilling
    // if( lrg->_is_bound ) return false;
  
+   // Use float pressure numbers for vectors.
+   bool is_float_or_vector = lrg->_is_float || lrg->_is_vector;
    // Not yet reached the high-pressure cutoff point, so low pressure
!   uint hrp_idx = lrg->_is_float ? b->_fhrp_index : b->_ihrp_index;
!   uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index;
    if( insidx < hrp_idx ) return false;
    // Register pressure for the block as a whole depends on reg class
!   int block_pres = lrg->_is_float ? b->_freg_pressure : b->_reg_pressure;
!   int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure;
    // Bound live ranges will split at the binding points first;
    // Intermediate splits should assume the live range's register set
    // got "freed up" and that num_regs will become INT_PRESSURE.
!   int bound_pres = lrg->_is_float ? FLOATPRESSURE : INTPRESSURE;
!   int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE;
    // Effective register pressure limit.
    int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
      ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
    // High pressure if block pressure requires more register freedom
    // than live range has.

*** 792,806 ****
--- 795,812 ----
                        break;
                    // Found a use?  Better split after it.
                    if( i < n->req() ) break;
                    insert_point--;
                  }
+                 uint orig_eidx = b->end_idx();
                  maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
                  // If it wasn't split bail
                  if (!maxlrg) {
                    return 0;
                  }
+                 // Spill of NULL check mem op goes into the following block.
+                 if (b->end_idx() > orig_eidx)
                    insidx++;
                }
                // This is a new DEF, so update UP
                UPblock[slidx] = false;
  #ifndef PRODUCT

*** 958,968 ****
--- 964,974 ----
                }
              }
              // Grab register mask info
              const RegMask &dmask = def->out_RegMask();
              const RegMask &umask = n->in_RegMask(inpidx);
  
+             bool is_vect = RegMask::is_vector(def->ideal_reg());
              assert(inpidx < oopoff, "cannot use-split oop map info");
  
              bool dup = UPblock[slidx];
              bool uup = umask.is_UP();
  

*** 970,980 ****
--- 976,986 ----
              // bound use if we can't rematerialize the def, or if we need the
              // split to form a misaligned pair.
              if( !umask.is_AllStack() &&
                  (int)umask.Size() <= lrgs(useidx).num_regs() &&
                  (!def->rematerialize() ||
!                  umask.is_misaligned_Pair())) {
!                  !is_vect && umask.is_misaligned_pair())) {
                // These need a Split regardless of overlap or pressure
                // SPLIT - NO DEF - NO CISC SPILL
                maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
                // If it wasn't split bail
                if (!maxlrg) {

*** 1121,1133 ****
--- 1127,1141 ----
            set_was_spilled(n);
          assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
          // Grab UP info for DEF
          const RegMask &dmask = n->out_RegMask();
          bool defup = dmask.is_UP();
+         int ireg = n->ideal_reg();
+         bool is_vect = RegMask::is_vector(ireg);
          // Only split at Def if this is a HRP block or bound (and spilled once)
          if( !n->rematerialize() &&
!             (((dmask.is_bound1() || dmask.is_bound2() || dmask.is_misaligned_Pair()) &&
!             (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) &&
                (deflrg._direct_conflict || deflrg._must_spill)) ||
               // Check for LRG being up in a register and we are inside a high
               // pressure area.  Spill it down immediately.
               (defup && is_high_pressure(b,&deflrg,insidx))) ) {
            assert( !n->rematerialize(), "" );