1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef SHARE_VM_OPTO_REGMASK_HPP
26 #define SHARE_VM_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "libadt/port.hpp"
30 #include "opto/optoreg.hpp"
31 #ifdef TARGET_ARCH_MODEL_x86_32
32 # include "adfiles/adGlobals_x86_32.hpp"
33 #endif
34 #ifdef TARGET_ARCH_MODEL_x86_64
35 # include "adfiles/adGlobals_x86_64.hpp"
36 #endif
37 #ifdef TARGET_ARCH_MODEL_sparc
38 # include "adfiles/adGlobals_sparc.hpp"
39 #endif
40 #ifdef TARGET_ARCH_MODEL_zero
41 # include "adfiles/adGlobals_zero.hpp"
42 #endif
43 #ifdef TARGET_ARCH_MODEL_arm
44 # include "adfiles/adGlobals_arm.hpp"
45 #endif
46 #ifdef TARGET_ARCH_MODEL_ppc
47 # include "adfiles/adGlobals_ppc.hpp"
48 #endif
49
50 // Some fun naming (textual) substitutions:
51 //
52 // RegMask::get_low_elem() ==> RegMask::find_first_elem()
53 // RegMask::Special ==> RegMask::Empty
54 // RegMask::_flags ==> RegMask::is_AllStack()
55 // RegMask::operator<<=() ==> RegMask::Insert()
56 // RegMask::operator>>=() ==> RegMask::Remove()
57 // RegMask::Union() ==> RegMask::OR
58 // RegMask::Inter() ==> RegMask::AND
59 //
60 // OptoRegister::RegName ==> OptoReg::Name
61 //
62 // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version
63 //
64 // numregs in chaitin ==> proper degree in chaitin
65
66 //-------------Non-zero bit search methods used by RegMask---------------------
67 // Find lowest 1, or return 32 if empty
68 int find_lowest_bit( uint32 mask );
69 // Find highest 1, or return 32 if empty
70 int find_hihghest_bit( uint32 mask );
71
72 //------------------------------RegMask----------------------------------------
73 // The ADL file describes how to print the machine-specific registers, as well
74 // as any notion of register classes. We provide a register mask, which is
75 // just a collection of Register numbers.
76
77 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
78 // RM_SIZE is the size of a register mask in words.
79 // FORALL_BODY replicates a BODY macro once per word in the register mask.
80 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
81 // However, it means the ADLC can redefine the unroll macro and all loops
82 // over register masks will be unrolled by the correct amount.
83
84 class RegMask VALUE_OBJ_CLASS_SPEC {
85 union {
86 double _dummy_force_double_alignment[RM_SIZE>>1];
87 // Array of Register Mask bits. This array is large enough to cover
88 // all the machine registers and all parameters that need to be passed
89 // on the stack (stack registers) up to some interesting limit. Methods
90 // that need more parameters will NOT be compiled. On Intel, the limit
91 // is something like 90+ parameters.
92 int _A[RM_SIZE];
93 };
94
95 enum {
96 _WordBits = BitsPerInt,
97 _LogWordBits = LogBitsPerInt,
98 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
99 };
100
101 public:
102 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
103
104 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
105 // Also, consider the maximum alignment size for a normally allocated
106 // value. Since we allocate register pairs but not register quads (at
107 // present), this alignment is SlotsPerLong (== 2). A normally
108 // aligned allocated register is either a single register, or a pair
109 // of adjacent registers, the lower-numbered being even.
110 // See also is_aligned_Pairs() below, and the padding added before
111 // Matcher::_new_SP to keep allocated pairs aligned properly.
112 // If we ever go to quad-word allocations, SlotsPerQuad will become
113 // the controlling alignment constraint. Note that this alignment
114 // requirement is internal to the allocator, and independent of any
115 // particular platform.
116 enum { SlotsPerLong = 2,
117 SlotsPerVecS = 1,
118 SlotsPerVecD = 2,
119 SlotsPerVecX = 4,
120 SlotsPerVecY = 8 };
121
122 // A constructor only used by the ADLC output. All mask fields are filled
123 // in directly. Calls to this look something like RM(1,2,3,4);
124 RegMask(
125 # define BODY(I) int a##I,
126 FORALL_BODY
127 # undef BODY
128 int dummy = 0 ) {
129 # define BODY(I) _A[I] = a##I;
130 FORALL_BODY
131 # undef BODY
132 }
133
134 // Handy copying constructor
135 RegMask( RegMask *rm ) {
136 # define BODY(I) _A[I] = rm->_A[I];
137 FORALL_BODY
138 # undef BODY
139 }
140
141 // Construct an empty mask
142 RegMask( ) { Clear(); }
143
144 // Construct a mask with a single bit
145 RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
146
147 // Check for register being in mask
148 int Member( OptoReg::Name reg ) const {
149 assert( reg < CHUNK_SIZE, "" );
150 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
151 }
152
153 // The last bit in the register mask indicates that the mask should repeat
154 // indefinitely with ONE bits. Returns TRUE if mask is infinite or
155 // unbounded in size. Returns FALSE if mask is finite size.
156 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
157
158 // Work around an -xO3 optimization problme in WS6U1. The old way:
159 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
160 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
161 // follows an Insert() loop, like the one found in init_spill_mask(). Using
162 // Insert() instead works because the index into _A in computed instead of
163 // constant. See bug 4665841.
164 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
165
166 // Test for being a not-empty mask.
167 int is_NotEmpty( ) const {
168 int tmp = 0;
169 # define BODY(I) tmp |= _A[I];
170 FORALL_BODY
171 # undef BODY
172 return tmp;
173 }
174
175 // Find lowest-numbered register from mask, or BAD if mask is empty.
176 OptoReg::Name find_first_elem() const {
177 int base, bits;
178 # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
179 FORALL_BODY
180 # undef BODY
181 { base = OptoReg::Bad; bits = 1<<0; }
182 return OptoReg::Name(base + find_lowest_bit(bits));
183 }
184 // Get highest-numbered register from mask, or BAD if mask is empty.
185 OptoReg::Name find_last_elem() const {
186 int base, bits;
187 # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
188 FORALL_BODY
189 # undef BODY
190 { base = OptoReg::Bad; bits = 1<<0; }
191 return OptoReg::Name(base + find_hihghest_bit(bits));
192 }
193
194 // Find the lowest-numbered register pair in the mask. Return the
195 // HIGHEST register number in the pair, or BAD if no pairs.
196 // Assert that the mask contains only bit pairs.
197 OptoReg::Name find_first_pair() const;
198
199 // Clear out partial bits; leave only aligned adjacent bit pairs.
200 void clear_to_pairs();
201 // Smear out partial bits; leave only aligned adjacent bit pairs.
202 void smear_to_pairs();
203 // Verify that the mask contains only aligned adjacent bit pairs
204 void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
205 // Test that the mask contains only aligned adjacent bit pairs
206 bool is_aligned_pairs() const;
207
208 // mask is a pair of misaligned registers
209 bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
210 // Test for single register
211 int is_bound1() const;
212 // Test for a single adjacent pair
213 int is_bound_pair() const;
214 // Test for a single adjacent set of ideal register's size.
215 int is_bound(uint ireg) const {
216 if (is_vector(ireg)) {
217 if (is_bound_set(num_registers(ireg)))
218 return true;
219 } else if (is_bound1() || is_bound_pair()) {
220 return true;
221 }
222 return false;
223 }
224
225 // Find the lowest-numbered register set in the mask. Return the
226 // HIGHEST register number in the set, or BAD if no sets.
227 // Assert that the mask contains only bit sets.
228 OptoReg::Name find_first_set(int size) const;
229
230 // Clear out partial bits; leave only aligned adjacent bit sets of size.
231 void clear_to_sets(int size);
232 // Smear out partial bits to aligned adjacent bit sets.
233 void smear_to_sets(int size);
234 // Verify that the mask contains only aligned adjacent bit sets
235 void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
236 // Test that the mask contains only aligned adjacent bit sets
237 bool is_aligned_sets(int size) const;
238
239 // mask is a set of misaligned registers
240 bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
241
242 // Test for a single adjacent set
243 int is_bound_set(int size) const;
244
245 static bool is_vector(uint ireg);
246 static int num_registers(uint ireg);
247
248 // Fast overlap test. Non-zero if any registers in common.
249 int overlap( const RegMask &rm ) const {
250 return
251 # define BODY(I) (_A[I] & rm._A[I]) |
252 FORALL_BODY
253 # undef BODY
254 0 ;
255 }
256
257 // Special test for register pressure based splitting
258 // UP means register only, Register plus stack, or stack only is DOWN
259 bool is_UP() const;
260
261 // Clear a register mask
262 void Clear( ) {
263 # define BODY(I) _A[I] = 0;
264 FORALL_BODY
265 # undef BODY
266 }
267
268 // Fill a register mask with 1's
269 void Set_All( ) {
270 # define BODY(I) _A[I] = -1;
271 FORALL_BODY
272 # undef BODY
273 }
274
275 // Insert register into mask
276 void Insert( OptoReg::Name reg ) {
277 assert( reg < CHUNK_SIZE, "" );
278 _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
279 }
280
281 // Remove register from mask
282 void Remove( OptoReg::Name reg ) {
283 assert( reg < CHUNK_SIZE, "" );
284 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
285 }
286
287 // OR 'rm' into 'this'
288 void OR( const RegMask &rm ) {
289 # define BODY(I) this->_A[I] |= rm._A[I];
290 FORALL_BODY
291 # undef BODY
292 }
293
294 // AND 'rm' into 'this'
295 void AND( const RegMask &rm ) {
296 # define BODY(I) this->_A[I] &= rm._A[I];
297 FORALL_BODY
298 # undef BODY
299 }
300
301 // Subtract 'rm' from 'this'
302 void SUBTRACT( const RegMask &rm ) {
303 # define BODY(I) _A[I] &= ~rm._A[I];
304 FORALL_BODY
305 # undef BODY
306 }
307
308 // Compute size of register mask: number of bits
309 uint Size() const;
310
311 #ifndef PRODUCT
312 void print() const { dump(); }
313 void dump() const; // Print a mask
314 #endif
315
316 static const RegMask Empty; // Common empty mask
317
318 static bool can_represent(OptoReg::Name reg) {
319 // NOTE: -1 in computation reflects the usage of the last
320 // bit of the regmask as an infinite stack flag and
321 // -7 is to keep mask aligned for largest value (VecY).
322 return (int)reg < (int)(CHUNK_SIZE-1);
323 }
324 static bool can_represent_arg(OptoReg::Name reg) {
325 // NOTE: -SlotsPerVecY in computation reflects the need
326 // to keep mask aligned for largest value (VecY).
327 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY);
328 }
329 };
330
331 // Do not use this constant directly in client code!
332 #undef RM_SIZE
333
334 #endif // SHARE_VM_OPTO_REGMASK_HPP