572 void prefix(Address adr, Register reg, bool byteinst = false);
573 void prefix(Address adr, XMMRegister reg);
574 void prefixq(Address adr, Register reg);
575 void prefixq(Address adr, XMMRegister reg);
576
577 void prefetch_prefix(Address src);
578
579 void rex_prefix(Address adr, XMMRegister xreg,
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
581 int rex_prefix_and_encode(int dst_enc, int src_enc,
582 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
583
584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
585 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
586 bool vector256);
587
588 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
589 VexSimdPrefix pre, VexOpcode opc,
590 bool vex_w, bool vector256);
591
592 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
593 VexSimdPrefix pre, VexOpcode opc,
594 bool vex_w, bool vector256);
595
596
597 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
598 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
599 bool rex_w = false, bool vector256 = false);
600
601 void simd_prefix(XMMRegister dst, Address src,
602 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
603 simd_prefix(dst, xnoreg, src, pre, opc);
604 }
605 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
606 simd_prefix(src, dst, pre);
607 }
608 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
609 VexSimdPrefix pre) {
610 bool rex_w = true;
611 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
612 }
613
614
615 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
1557 emit_byte(0x0F);
1558 emit_byte(0x01);
1559 emit_byte(0xD0);
1560 }
1561
1562 void xorl(Register dst, int32_t imm32);
1563 void xorl(Register dst, Address src);
1564 void xorl(Register dst, Register src);
1565
1566 void xorq(Register dst, Address src);
1567 void xorq(Register dst, Register src);
1568
1569 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1570 void xorpd(XMMRegister dst, XMMRegister src);
1571
1572 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1573 void xorps(XMMRegister dst, XMMRegister src);
1574
1575 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1576
1577 protected:
1578 // Next instructions require address alignment 16 bytes SSE mode.
1579 // They should be called only from corresponding MacroAssembler instructions.
1580 void andpd(XMMRegister dst, Address src);
1581 void andps(XMMRegister dst, Address src);
1582 void xorpd(XMMRegister dst, Address src);
1583 void xorps(XMMRegister dst, Address src);
1584
1585 };
1586
1587
1588 // MacroAssembler extends Assembler by frequently used macros.
1589 //
1590 // Instructions for which a 'better' code sequence exists depending
1591 // on arguments should also go in here.
1592
1593 class MacroAssembler: public Assembler {
1594 friend class LIR_Assembler;
1595 friend class Runtime1; // as_Address()
1596
2405 void subss(XMMRegister dst, AddressLiteral src);
2406
2407 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2408 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2409 void ucomiss(XMMRegister dst, AddressLiteral src);
2410
2411 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2412 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2413 void ucomisd(XMMRegister dst, AddressLiteral src);
2414
2415 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2416 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2417 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2418 void xorpd(XMMRegister dst, AddressLiteral src);
2419
2420 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2421 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2422 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2423 void xorps(XMMRegister dst, AddressLiteral src);
2424
2425 // Data
2426
2427 void cmov32( Condition cc, Register dst, Address src);
2428 void cmov32( Condition cc, Register dst, Register src);
2429
2430 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2431
2432 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2433 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2434
2435 void movoop(Register dst, jobject obj);
2436 void movoop(Address dst, jobject obj);
2437
2438 void movptr(ArrayAddress dst, Register src);
2439 // can this do an lea?
2440 void movptr(Register dst, ArrayAddress src);
2441
2442 void movptr(Register dst, Address src);
2443
2444 void movptr(Register dst, AddressLiteral src);
|
572 void prefix(Address adr, Register reg, bool byteinst = false);
573 void prefix(Address adr, XMMRegister reg);
574 void prefixq(Address adr, Register reg);
575 void prefixq(Address adr, XMMRegister reg);
576
577 void prefetch_prefix(Address src);
578
579 void rex_prefix(Address adr, XMMRegister xreg,
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
581 int rex_prefix_and_encode(int dst_enc, int src_enc,
582 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
583
584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
585 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
586 bool vector256);
587
588 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
589 VexSimdPrefix pre, VexOpcode opc,
590 bool vex_w, bool vector256);
591
592 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
593 VexSimdPrefix pre, bool vector256 = false) {
594 vex_prefix(src, nds->encoding(), dst->encoding(),
595 pre, VEX_OPCODE_0F, false, vector256);
596 }
597
598 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
599 VexSimdPrefix pre, VexOpcode opc,
600 bool vex_w, bool vector256);
601
602 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
603 VexSimdPrefix pre, bool vector256 = false) {
604 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
605 pre, VEX_OPCODE_0F, false, vector256);
606 }
607
608 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
609 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
610 bool rex_w = false, bool vector256 = false);
611
612 void simd_prefix(XMMRegister dst, Address src,
613 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
614 simd_prefix(dst, xnoreg, src, pre, opc);
615 }
616 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
617 simd_prefix(src, dst, pre);
618 }
619 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
620 VexSimdPrefix pre) {
621 bool rex_w = true;
622 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
623 }
624
625
626 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
1568 emit_byte(0x0F);
1569 emit_byte(0x01);
1570 emit_byte(0xD0);
1571 }
1572
1573 void xorl(Register dst, int32_t imm32);
1574 void xorl(Register dst, Address src);
1575 void xorl(Register dst, Register src);
1576
1577 void xorq(Register dst, Address src);
1578 void xorq(Register dst, Register src);
1579
1580 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1581 void xorpd(XMMRegister dst, XMMRegister src);
1582
1583 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1584 void xorps(XMMRegister dst, XMMRegister src);
1585
1586 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1587
1588 // AVX 3-operands instructions (encoded with VEX prefix)
1589 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1590 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1591 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1592 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1593 void vandpd(XMMRegister dst, XMMRegister nds, Address src);
1594 void vandps(XMMRegister dst, XMMRegister nds, Address src);
1595 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1596 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1597 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1598 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1599 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1600 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1601 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1602 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1603 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1604 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1605 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1606 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1607 void vxorpd(XMMRegister dst, XMMRegister nds, Address src);
1608 void vxorps(XMMRegister dst, XMMRegister nds, Address src);
1609
1610
1611 protected:
1612 // Next instructions require address alignment 16 bytes SSE mode.
1613 // They should be called only from corresponding MacroAssembler instructions.
1614 void andpd(XMMRegister dst, Address src);
1615 void andps(XMMRegister dst, Address src);
1616 void xorpd(XMMRegister dst, Address src);
1617 void xorps(XMMRegister dst, Address src);
1618
1619 };
1620
1621
1622 // MacroAssembler extends Assembler by frequently used macros.
1623 //
1624 // Instructions for which a 'better' code sequence exists depending
1625 // on arguments should also go in here.
1626
1627 class MacroAssembler: public Assembler {
1628 friend class LIR_Assembler;
1629 friend class Runtime1; // as_Address()
1630
2439 void subss(XMMRegister dst, AddressLiteral src);
2440
2441 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2442 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2443 void ucomiss(XMMRegister dst, AddressLiteral src);
2444
2445 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2446 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2447 void ucomisd(XMMRegister dst, AddressLiteral src);
2448
2449 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2450 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2451 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2452 void xorpd(XMMRegister dst, AddressLiteral src);
2453
2454 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2455 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2456 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2457 void xorps(XMMRegister dst, AddressLiteral src);
2458
2459 // AVX 3-operands instructions
2460
2461 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2462 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
2463 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2464
2465 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2466 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2467 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2468
2469 void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); }
2470 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2471
2472 void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); }
2473 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2474
2475 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2476 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2477 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2478
2479 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2480 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
2481 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2482
2483 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2484 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
2485 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2486
2487 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2488 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
2489 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2490
2491 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2492 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
2493 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2494
2495 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2496 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
2497 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2498
2499 void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); }
2500 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2501
2502 void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); }
2503 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2504
2505
2506 // Data
2507
2508 void cmov32( Condition cc, Register dst, Address src);
2509 void cmov32( Condition cc, Register dst, Register src);
2510
2511 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2512
2513 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2514 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2515
2516 void movoop(Register dst, jobject obj);
2517 void movoop(Address dst, jobject obj);
2518
2519 void movptr(ArrayAddress dst, Register src);
2520 // can this do an lea?
2521 void movptr(Register dst, ArrayAddress src);
2522
2523 void movptr(Register dst, Address src);
2524
2525 void movptr(Register dst, AddressLiteral src);
|