1 // 2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // X86 Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 32 register %{ 33 //----------Architecture Description Register Definitions---------------------- 34 // General Registers 35 // "reg_def" name ( register save type, C convention save type, 36 // ideal register type, encoding ); 37 // Register Save Types: 38 // 39 // NS = No-Save: The register allocator assumes that these registers 40 // can be used without saving upon entry to the method, & 41 // that they do not need to be saved at call sites. 42 // 43 // SOC = Save-On-Call: The register allocator assumes that these registers 44 // can be used without saving upon entry to the method, 45 // but that they must be saved at call sites. 46 // 47 // SOE = Save-On-Entry: The register allocator assumes that these registers 48 // must be saved before using them upon entry to the 49 // method, but they do not need to be saved at call 50 // sites. 51 // 52 // AS = Always-Save: The register allocator assumes that these registers 53 // must be saved before using them upon entry to the 54 // method, & that they must be saved at call sites. 55 // 56 // Ideal Register Type is used to determine how to save & restore a 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59 // 60 // The encoding number is the actual bit-pattern placed into the opcodes. 61 62 // General Registers 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. 66 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 76 77 // Special Registers 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); 79 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the 81 // allocator, and only shows up in the encodings. 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 84 // Ok so here's the trick FPR1 is really st(0) except in the midst 85 // of emission of assembly for a machnode. During the emission the fpu stack 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint 87 // the stack will not have this element so FPR1 == st(0) from the 88 // oopMap viewpoint. This same weirdness with numbering causes 89 // instruction encoding to have to play games with the register 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation 91 // where it does flt->flt moves to see an example 92 // 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 107 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. 109 // Word a in each register holds a Float, words ab hold a Double. 110 // We currently do not use the SIMD capabilities, so registers cd 111 // are unused at the moment. 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); 128 129 // Specify priority of register selection within phases of register 130 // allocation. Highest priority is first. A useful heuristic is to 131 // give registers a low priority when they are required by machine 132 // instructions, like EAX and EDX. Registers which are used as 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). 134 // For the Intel integer registers, the equivalent Long pairs are 135 // EDX:EAX, EBX:ECX, and EDI:EBP. 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 139 FPR6L, FPR6H, FPR7L, FPR7H ); 140 141 alloc_class chunk1( XMM0a, XMM0b, 142 XMM1a, XMM1b, 143 XMM2a, XMM2b, 144 XMM3a, XMM3b, 145 XMM4a, XMM4b, 146 XMM5a, XMM5b, 147 XMM6a, XMM6b, 148 XMM7a, XMM7b, EFLAGS); 149 150 151 //----------Architecture Description Register Classes-------------------------- 152 // Several register classes are automatically defined based upon information in 153 // this architecture description. 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 158 // 159 // Class for all registers 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 161 // Class for general registers 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 163 // Class for general registers which may be used for implicit null checks on win95 164 // Also safe for use by tailjump. We don't want to allocate in rbp, 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 166 // Class of "X" registers 167 reg_class x_reg(EBX, ECX, EDX, EAX); 168 // Class of registers that can appear in an address with no offset. 169 // EBP and ESP require an extra instruction byte for zero offset. 170 // Used in fast-unlock 171 reg_class p_reg(EDX, EDI, ESI, EBX); 172 // Class for general registers not including ECX 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); 174 // Class for general registers not including EAX 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); 176 // Class for general registers not including EAX or EBX. 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); 178 // Class of EAX (for multiply and divide operations) 179 reg_class eax_reg(EAX); 180 // Class of EBX (for atomic add) 181 reg_class ebx_reg(EBX); 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) 183 reg_class ecx_reg(ECX); 184 // Class of EDX (for multiply and divide operations) 185 reg_class edx_reg(EDX); 186 // Class of EDI (for synchronization) 187 reg_class edi_reg(EDI); 188 // Class of ESI (for synchronization) 189 reg_class esi_reg(ESI); 190 // Singleton class for interpreter's stack pointer 191 reg_class ebp_reg(EBP); 192 // Singleton class for stack pointer 193 reg_class sp_reg(ESP); 194 // Singleton class for instruction pointer 195 // reg_class ip_reg(EIP); 196 // Singleton class for condition codes 197 reg_class int_flags(EFLAGS); 198 // Class of integer register pairs 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 200 // Class of integer register pairs that aligns with calling convention 201 reg_class eadx_reg( EAX,EDX ); 202 reg_class ebcx_reg( ECX,EBX ); 203 // Not AX or DX, used in divides 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 205 206 // Floating point registers. Notice FPR0 is not a choice. 207 // FPR0 is not ever allocated; we use clever encodings to fake 208 // a 2-address instructions out of Intels FP stack. 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 210 211 // make a register class for SSE registers 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); 213 214 // make a double register class for SSE2 registers 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); 217 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 220 FPR7L,FPR7H ); 221 222 reg_class flt_reg0( FPR1L ); 223 reg_class dbl_reg0( FPR1L,FPR1H ); 224 reg_class dbl_reg1( FPR2L,FPR2H ); 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); 227 228 // XMM6 and XMM7 could be used as temporary registers for long, float and 229 // double values for SSE2. 230 reg_class xdb_reg6( XMM6a,XMM6b ); 231 reg_class xdb_reg7( XMM7a,XMM7b ); 232 %} 233 234 235 //----------SOURCE BLOCK------------------------------------------------------- 236 // This is a block of C++ code which provides values, functions, and 237 // definitions necessary in the rest of the architecture description 238 source_hpp %{ 239 // Must be visible to the DFA in dfa_x86_32.cpp 240 extern bool is_operand_hi32_zero(Node* n); 241 %} 242 243 source %{ 244 #define RELOC_IMM32 Assembler::imm_operand 245 #define RELOC_DISP32 Assembler::disp32_operand 246 247 #define __ _masm. 248 249 // How to find the high register of a Long pair, given the low register 250 #define HIGH_FROM_LOW(x) ((x)+2) 251 252 // These masks are used to provide 128-bit aligned bitmasks to the XMM 253 // instructions, to allow sign-masking or sign-bit flipping. They allow 254 // fast versions of NegF/NegD and AbsF/AbsD. 255 256 // Note: 'double' and 'long long' have 32-bits alignment on x86. 257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 259 // of 128-bits operands for SSE instructions. 260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); 261 // Store the value to a 128-bits operand. 262 operand[0] = lo; 263 operand[1] = hi; 264 return operand; 265 } 266 267 // Buffer for 128-bits masks used by SSE instructions. 268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 269 270 // Static initialization during VM startup. 271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 275 276 // Offset hacking within calls. 277 static int pre_call_FPU_size() { 278 if (Compile::current()->in_24_bit_fp_mode()) 279 return 6; // fldcw 280 return 0; 281 } 282 283 static int preserve_SP_size() { 284 return 2; // op, rm(reg/reg) 285 } 286 287 // !!!!! Special hack to get all type of calls to specify the byte offset 288 // from the start of the call to the point where the return address 289 // will point. 290 int MachCallStaticJavaNode::ret_addr_offset() { 291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points 292 if (_method_handle_invoke) 293 offset += preserve_SP_size(); 294 return offset; 295 } 296 297 int MachCallDynamicJavaNode::ret_addr_offset() { 298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points 299 } 300 301 static int sizeof_FFree_Float_Stack_All = -1; 302 303 int MachCallRuntimeNode::ret_addr_offset() { 304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); 305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); 306 } 307 308 // Indicate if the safepoint node needs the polling page as an input. 309 // Since x86 does have absolute addressing, it doesn't. 310 bool SafePointNode::needs_polling_address_input() { 311 return false; 312 } 313 314 // 315 // Compute padding required for nodes which need alignment 316 // 317 318 // The address of the call instruction needs to be 4-byte aligned to 319 // ensure that it does not span a cache line so that it can be patched. 320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { 321 current_offset += pre_call_FPU_size(); // skip fldcw, if any 322 current_offset += 1; // skip call opcode byte 323 return round_to(current_offset, alignment_required()) - current_offset; 324 } 325 326 // The address of the call instruction needs to be 4-byte aligned to 327 // ensure that it does not span a cache line so that it can be patched. 328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { 329 current_offset += pre_call_FPU_size(); // skip fldcw, if any 330 current_offset += preserve_SP_size(); // skip mov rbp, rsp 331 current_offset += 1; // skip call opcode byte 332 return round_to(current_offset, alignment_required()) - current_offset; 333 } 334 335 // The address of the call instruction needs to be 4-byte aligned to 336 // ensure that it does not span a cache line so that it can be patched. 337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { 338 current_offset += pre_call_FPU_size(); // skip fldcw, if any 339 current_offset += 5; // skip MOV instruction 340 current_offset += 1; // skip call opcode byte 341 return round_to(current_offset, alignment_required()) - current_offset; 342 } 343 344 #ifndef PRODUCT 345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { 346 st->print("INT3"); 347 } 348 #endif 349 350 // EMIT_RM() 351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 353 cbuf.insts()->emit_int8(c); 354 } 355 356 // EMIT_CC() 357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { 358 unsigned char c = (unsigned char)( f1 | f2 ); 359 cbuf.insts()->emit_int8(c); 360 } 361 362 // EMIT_OPCODE() 363 void emit_opcode(CodeBuffer &cbuf, int code) { 364 cbuf.insts()->emit_int8((unsigned char) code); 365 } 366 367 // EMIT_OPCODE() w/ relocation information 368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { 369 cbuf.relocate(cbuf.insts_mark() + offset, reloc); 370 emit_opcode(cbuf, code); 371 } 372 373 // EMIT_D8() 374 void emit_d8(CodeBuffer &cbuf, int d8) { 375 cbuf.insts()->emit_int8((unsigned char) d8); 376 } 377 378 // EMIT_D16() 379 void emit_d16(CodeBuffer &cbuf, int d16) { 380 cbuf.insts()->emit_int16(d16); 381 } 382 383 // EMIT_D32() 384 void emit_d32(CodeBuffer &cbuf, int d32) { 385 cbuf.insts()->emit_int32(d32); 386 } 387 388 // emit 32 bit value and construct relocation entry from relocInfo::relocType 389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, 390 int format) { 391 cbuf.relocate(cbuf.insts_mark(), reloc, format); 392 cbuf.insts()->emit_int32(d32); 393 } 394 395 // emit 32 bit value and construct relocation entry from RelocationHolder 396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, 397 int format) { 398 #ifdef ASSERT 399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { 400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); 401 } 402 #endif 403 cbuf.relocate(cbuf.insts_mark(), rspec, format); 404 cbuf.insts()->emit_int32(d32); 405 } 406 407 // Access stack slot for load or store 408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { 409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) 410 if( -128 <= disp && disp <= 127 ) { 411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte 412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 413 emit_d8 (cbuf, disp); // Displacement // R/M byte 414 } else { 415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte 416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 417 emit_d32(cbuf, disp); // Displacement // R/M byte 418 } 419 } 420 421 // eRegI ereg, memory mem) %{ // emit_reg_mem 422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 423 // There is no index & no scale, use form without SIB byte 424 if ((index == 0x4) && 425 (scale == 0) && (base != ESP_enc)) { 426 // If no displacement, mode is 0x0; unless base is [EBP] 427 if ( (displace == 0) && (base != EBP_enc) ) { 428 emit_rm(cbuf, 0x0, reg_encoding, base); 429 } 430 else { // If 8-bit displacement, mode 0x1 431 if ((displace >= -128) && (displace <= 127) 432 && !(displace_is_oop) ) { 433 emit_rm(cbuf, 0x1, reg_encoding, base); 434 emit_d8(cbuf, displace); 435 } 436 else { // If 32-bit displacement 437 if (base == -1) { // Special flag for absolute address 438 emit_rm(cbuf, 0x0, reg_encoding, 0x5); 439 // (manual lies; no SIB needed here) 440 if ( displace_is_oop ) { 441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 442 } else { 443 emit_d32 (cbuf, displace); 444 } 445 } 446 else { // Normal base + offset 447 emit_rm(cbuf, 0x2, reg_encoding, base); 448 if ( displace_is_oop ) { 449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 450 } else { 451 emit_d32 (cbuf, displace); 452 } 453 } 454 } 455 } 456 } 457 else { // Else, encode with the SIB byte 458 // If no displacement, mode is 0x0; unless base is [EBP] 459 if (displace == 0 && (base != EBP_enc)) { // If no displacement 460 emit_rm(cbuf, 0x0, reg_encoding, 0x4); 461 emit_rm(cbuf, scale, index, base); 462 } 463 else { // If 8-bit displacement, mode 0x1 464 if ((displace >= -128) && (displace <= 127) 465 && !(displace_is_oop) ) { 466 emit_rm(cbuf, 0x1, reg_encoding, 0x4); 467 emit_rm(cbuf, scale, index, base); 468 emit_d8(cbuf, displace); 469 } 470 else { // If 32-bit displacement 471 if (base == 0x04 ) { 472 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 473 emit_rm(cbuf, scale, index, 0x04); 474 } else { 475 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 476 emit_rm(cbuf, scale, index, base); 477 } 478 if ( displace_is_oop ) { 479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 480 } else { 481 emit_d32 (cbuf, displace); 482 } 483 } 484 } 485 } 486 } 487 488 489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 490 if( dst_encoding == src_encoding ) { 491 // reg-reg copy, use an empty encoding 492 } else { 493 emit_opcode( cbuf, 0x8B ); 494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); 495 } 496 } 497 498 void emit_cmpfp_fixup(MacroAssembler& _masm) { 499 Label exit; 500 __ jccb(Assembler::noParity, exit); 501 __ pushf(); 502 // 503 // comiss/ucomiss instructions set ZF,PF,CF flags and 504 // zero OF,AF,SF for NaN values. 505 // Fixup flags by zeroing ZF,PF so that compare of NaN 506 // values returns 'less than' result (CF is set). 507 // Leave the rest of flags unchanged. 508 // 509 // 7 6 5 4 3 2 1 0 510 // |S|Z|r|A|r|P|r|C| (r - reserved bit) 511 // 0 0 1 0 1 0 1 1 (0x2B) 512 // 513 __ andl(Address(rsp, 0), 0xffffff2b); 514 __ popf(); 515 __ bind(exit); 516 } 517 518 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { 519 Label done; 520 __ movl(dst, -1); 521 __ jcc(Assembler::parity, done); 522 __ jcc(Assembler::below, done); 523 __ setb(Assembler::notEqual, dst); 524 __ movzbl(dst, dst); 525 __ bind(done); 526 } 527 528 529 //============================================================================= 530 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; 531 532 int Compile::ConstantTable::calculate_table_base_offset() const { 533 return 0; // absolute addressing, no offset 534 } 535 536 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 537 // Empty encoding 538 } 539 540 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 541 return 0; 542 } 543 544 #ifndef PRODUCT 545 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 546 st->print("# MachConstantBaseNode (empty encoding)"); 547 } 548 #endif 549 550 551 //============================================================================= 552 #ifndef PRODUCT 553 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 554 Compile* C = ra_->C; 555 if( C->in_24_bit_fp_mode() ) { 556 st->print("FLDCW 24 bit fpu control word"); 557 st->print_cr(""); st->print("\t"); 558 } 559 560 int framesize = C->frame_slots() << LogBytesPerInt; 561 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 562 // Remove two words for return addr and rbp, 563 framesize -= 2*wordSize; 564 565 // Calls to C2R adapters often do not accept exceptional returns. 566 // We require that their callers must bang for them. But be careful, because 567 // some VM calls (such as call site linkage) can use several kilobytes of 568 // stack. But the stack safety zone should account for that. 569 // See bugs 4446381, 4468289, 4497237. 570 if (C->need_stack_bang(framesize)) { 571 st->print_cr("# stack bang"); st->print("\t"); 572 } 573 st->print_cr("PUSHL EBP"); st->print("\t"); 574 575 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 576 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); 577 st->print_cr(""); st->print("\t"); 578 framesize -= wordSize; 579 } 580 581 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 582 if (framesize) { 583 st->print("SUB ESP,%d\t# Create frame",framesize); 584 } 585 } else { 586 st->print("SUB ESP,%d\t# Create frame",framesize); 587 } 588 } 589 #endif 590 591 592 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 593 Compile* C = ra_->C; 594 595 if (UseSSE >= 2 && VerifyFPU) { 596 MacroAssembler masm(&cbuf); 597 masm.verify_FPU(0, "FPU stack must be clean on entry"); 598 } 599 600 // WARNING: Initial instruction MUST be 5 bytes or longer so that 601 // NativeJump::patch_verified_entry will be able to patch out the entry 602 // code safely. The fldcw is ok at 6 bytes, the push to verify stack 603 // depth is ok at 5 bytes, the frame allocation can be either 3 or 604 // 6 bytes. So if we don't do the fldcw or the push then we must 605 // use the 6 byte frame allocation even if we have no frame. :-( 606 // If method sets FPU control word do it now 607 if( C->in_24_bit_fp_mode() ) { 608 MacroAssembler masm(&cbuf); 609 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 610 } 611 612 int framesize = C->frame_slots() << LogBytesPerInt; 613 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 614 // Remove two words for return addr and rbp, 615 framesize -= 2*wordSize; 616 617 // Calls to C2R adapters often do not accept exceptional returns. 618 // We require that their callers must bang for them. But be careful, because 619 // some VM calls (such as call site linkage) can use several kilobytes of 620 // stack. But the stack safety zone should account for that. 621 // See bugs 4446381, 4468289, 4497237. 622 if (C->need_stack_bang(framesize)) { 623 MacroAssembler masm(&cbuf); 624 masm.generate_stack_overflow_check(framesize); 625 } 626 627 // We always push rbp, so that on return to interpreter rbp, will be 628 // restored correctly and we can correct the stack. 629 emit_opcode(cbuf, 0x50 | EBP_enc); 630 631 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 632 emit_opcode(cbuf, 0x68); // push 0xbadb100d 633 emit_d32(cbuf, 0xbadb100d); 634 framesize -= wordSize; 635 } 636 637 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 638 if (framesize) { 639 emit_opcode(cbuf, 0x83); // sub SP,#framesize 640 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 641 emit_d8(cbuf, framesize); 642 } 643 } else { 644 emit_opcode(cbuf, 0x81); // sub SP,#framesize 645 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 646 emit_d32(cbuf, framesize); 647 } 648 C->set_frame_complete(cbuf.insts_size()); 649 650 #ifdef ASSERT 651 if (VerifyStackAtCalls) { 652 Label L; 653 MacroAssembler masm(&cbuf); 654 masm.push(rax); 655 masm.mov(rax, rsp); 656 masm.andptr(rax, StackAlignmentInBytes-1); 657 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); 658 masm.pop(rax); 659 masm.jcc(Assembler::equal, L); 660 masm.stop("Stack is not properly aligned!"); 661 masm.bind(L); 662 } 663 #endif 664 665 if (C->has_mach_constant_base_node()) { 666 // NOTE: We set the table base offset here because users might be 667 // emitted before MachConstantBaseNode. 668 Compile::ConstantTable& constant_table = C->constant_table(); 669 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 670 } 671 } 672 673 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 674 return MachNode::size(ra_); // too many variables; just compute it the hard way 675 } 676 677 int MachPrologNode::reloc() const { 678 return 0; // a large enough number 679 } 680 681 //============================================================================= 682 #ifndef PRODUCT 683 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 684 Compile *C = ra_->C; 685 int framesize = C->frame_slots() << LogBytesPerInt; 686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 687 // Remove two words for return addr and rbp, 688 framesize -= 2*wordSize; 689 690 if( C->in_24_bit_fp_mode() ) { 691 st->print("FLDCW standard control word"); 692 st->cr(); st->print("\t"); 693 } 694 if( framesize ) { 695 st->print("ADD ESP,%d\t# Destroy frame",framesize); 696 st->cr(); st->print("\t"); 697 } 698 st->print_cr("POPL EBP"); st->print("\t"); 699 if( do_polling() && C->is_method_compilation() ) { 700 st->print("TEST PollPage,EAX\t! Poll Safepoint"); 701 st->cr(); st->print("\t"); 702 } 703 } 704 #endif 705 706 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 707 Compile *C = ra_->C; 708 709 // If method set FPU control word, restore to standard control word 710 if( C->in_24_bit_fp_mode() ) { 711 MacroAssembler masm(&cbuf); 712 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 713 } 714 715 int framesize = C->frame_slots() << LogBytesPerInt; 716 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 717 // Remove two words for return addr and rbp, 718 framesize -= 2*wordSize; 719 720 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 721 722 if( framesize >= 128 ) { 723 emit_opcode(cbuf, 0x81); // add SP, #framesize 724 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 725 emit_d32(cbuf, framesize); 726 } 727 else if( framesize ) { 728 emit_opcode(cbuf, 0x83); // add SP, #framesize 729 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 730 emit_d8(cbuf, framesize); 731 } 732 733 emit_opcode(cbuf, 0x58 | EBP_enc); 734 735 if( do_polling() && C->is_method_compilation() ) { 736 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); 737 emit_opcode(cbuf,0x85); 738 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX 739 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 740 } 741 } 742 743 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 744 Compile *C = ra_->C; 745 // If method set FPU control word, restore to standard control word 746 int size = C->in_24_bit_fp_mode() ? 6 : 0; 747 if( do_polling() && C->is_method_compilation() ) size += 6; 748 749 int framesize = C->frame_slots() << LogBytesPerInt; 750 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 751 // Remove two words for return addr and rbp, 752 framesize -= 2*wordSize; 753 754 size++; // popl rbp, 755 756 if( framesize >= 128 ) { 757 size += 6; 758 } else { 759 size += framesize ? 3 : 0; 760 } 761 return size; 762 } 763 764 int MachEpilogNode::reloc() const { 765 return 0; // a large enough number 766 } 767 768 const Pipeline * MachEpilogNode::pipeline() const { 769 return MachNode::pipeline_class(); 770 } 771 772 int MachEpilogNode::safepoint_offset() const { return 0; } 773 774 //============================================================================= 775 776 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; 777 static enum RC rc_class( OptoReg::Name reg ) { 778 779 if( !OptoReg::is_valid(reg) ) return rc_bad; 780 if (OptoReg::is_stack(reg)) return rc_stack; 781 782 VMReg r = OptoReg::as_VMReg(reg); 783 if (r->is_Register()) return rc_int; 784 if (r->is_FloatRegister()) { 785 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); 786 return rc_float; 787 } 788 assert(r->is_XMMRegister(), "must be"); 789 return rc_xmm; 790 } 791 792 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, 793 int opcode, const char *op_str, int size, outputStream* st ) { 794 if( cbuf ) { 795 emit_opcode (*cbuf, opcode ); 796 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); 797 #ifndef PRODUCT 798 } else if( !do_size ) { 799 if( size != 0 ) st->print("\n\t"); 800 if( opcode == 0x8B || opcode == 0x89 ) { // MOV 801 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 802 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); 803 } else { // FLD, FST, PUSH, POP 804 st->print("%s [ESP + #%d]",op_str,offset); 805 } 806 #endif 807 } 808 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 809 return size+3+offset_size; 810 } 811 812 // Helper for XMM registers. Extra opcode bits, limited syntax. 813 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, 814 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { 815 if (cbuf) { 816 MacroAssembler _masm(cbuf); 817 if (reg_lo+1 == reg_hi) { // double move? 818 if (is_load) { 819 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); 820 } else { 821 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); 822 } 823 } else { 824 if (is_load) { 825 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); 826 } else { 827 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); 828 } 829 } 830 #ifndef PRODUCT 831 } else if (!do_size) { 832 if (size != 0) st->print("\n\t"); 833 if (reg_lo+1 == reg_hi) { // double move? 834 if (is_load) st->print("%s %s,[ESP + #%d]", 835 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", 836 Matcher::regName[reg_lo], offset); 837 else st->print("MOVSD [ESP + #%d],%s", 838 offset, Matcher::regName[reg_lo]); 839 } else { 840 if (is_load) st->print("MOVSS %s,[ESP + #%d]", 841 Matcher::regName[reg_lo], offset); 842 else st->print("MOVSS [ESP + #%d],%s", 843 offset, Matcher::regName[reg_lo]); 844 } 845 #endif 846 } 847 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 848 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes. 849 return size+5+offset_size; 850 } 851 852 853 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 854 int src_hi, int dst_hi, int size, outputStream* st ) { 855 if (cbuf) { 856 MacroAssembler _masm(cbuf); 857 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? 858 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), 859 as_XMMRegister(Matcher::_regEncode[src_lo])); 860 } else { 861 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), 862 as_XMMRegister(Matcher::_regEncode[src_lo])); 863 } 864 #ifndef PRODUCT 865 } else if (!do_size) { 866 if (size != 0) st->print("\n\t"); 867 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers 868 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? 869 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 870 } else { 871 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 872 } 873 } else { 874 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 875 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 876 } else { 877 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 878 } 879 } 880 #endif 881 } 882 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes. 883 // Only MOVAPS SSE prefix uses 1 byte. 884 int sz = 4; 885 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && 886 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; 887 return size + sz; 888 } 889 890 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 891 int src_hi, int dst_hi, int size, outputStream* st ) { 892 // 32-bit 893 if (cbuf) { 894 MacroAssembler _masm(cbuf); 895 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), 896 as_Register(Matcher::_regEncode[src_lo])); 897 #ifndef PRODUCT 898 } else if (!do_size) { 899 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 900 #endif 901 } 902 return 4; 903 } 904 905 906 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 907 int src_hi, int dst_hi, int size, outputStream* st ) { 908 // 32-bit 909 if (cbuf) { 910 MacroAssembler _masm(cbuf); 911 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), 912 as_XMMRegister(Matcher::_regEncode[src_lo])); 913 #ifndef PRODUCT 914 } else if (!do_size) { 915 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 916 #endif 917 } 918 return 4; 919 } 920 921 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { 922 if( cbuf ) { 923 emit_opcode(*cbuf, 0x8B ); 924 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); 925 #ifndef PRODUCT 926 } else if( !do_size ) { 927 if( size != 0 ) st->print("\n\t"); 928 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); 929 #endif 930 } 931 return size+2; 932 } 933 934 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, 935 int offset, int size, outputStream* st ) { 936 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there 937 if( cbuf ) { 938 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) 939 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); 940 #ifndef PRODUCT 941 } else if( !do_size ) { 942 if( size != 0 ) st->print("\n\t"); 943 st->print("FLD %s",Matcher::regName[src_lo]); 944 #endif 945 } 946 size += 2; 947 } 948 949 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; 950 const char *op_str; 951 int op; 952 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? 953 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; 954 op = 0xDD; 955 } else { // 32-bit store 956 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; 957 op = 0xD9; 958 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); 959 } 960 961 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); 962 } 963 964 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 965 // Get registers to move 966 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 967 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 968 OptoReg::Name dst_second = ra_->get_reg_second(this ); 969 OptoReg::Name dst_first = ra_->get_reg_first(this ); 970 971 enum RC src_second_rc = rc_class(src_second); 972 enum RC src_first_rc = rc_class(src_first); 973 enum RC dst_second_rc = rc_class(dst_second); 974 enum RC dst_first_rc = rc_class(dst_first); 975 976 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 977 978 // Generate spill code! 979 int size = 0; 980 981 if( src_first == dst_first && src_second == dst_second ) 982 return size; // Self copy, no move 983 984 // -------------------------------------- 985 // Check for mem-mem move. push/pop to move. 986 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 987 if( src_second == dst_first ) { // overlapping stack copy ranges 988 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); 989 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 990 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 991 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits 992 } 993 // move low bits 994 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); 995 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); 996 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits 997 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 998 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 999 } 1000 return size; 1001 } 1002 1003 // -------------------------------------- 1004 // Check for integer reg-reg copy 1005 if( src_first_rc == rc_int && dst_first_rc == rc_int ) 1006 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); 1007 1008 // Check for integer store 1009 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) 1010 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); 1011 1012 // Check for integer load 1013 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) 1014 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); 1015 1016 // Check for integer reg-xmm reg copy 1017 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { 1018 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), 1019 "no 64 bit integer-float reg moves" ); 1020 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1021 } 1022 // -------------------------------------- 1023 // Check for float reg-reg copy 1024 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1025 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 1026 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); 1027 if( cbuf ) { 1028 1029 // Note the mucking with the register encode to compensate for the 0/1 1030 // indexing issue mentioned in a comment in the reg_def sections 1031 // for FPR registers many lines above here. 1032 1033 if( src_first != FPR1L_num ) { 1034 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) 1035 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); 1036 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 1037 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 1038 } else { 1039 emit_opcode (*cbuf, 0xDD ); // FST ST(i) 1040 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); 1041 } 1042 #ifndef PRODUCT 1043 } else if( !do_size ) { 1044 if( size != 0 ) st->print("\n\t"); 1045 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); 1046 else st->print( "FST %s", Matcher::regName[dst_first]); 1047 #endif 1048 } 1049 return size + ((src_first != FPR1L_num) ? 2+2 : 2); 1050 } 1051 1052 // Check for float store 1053 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1054 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); 1055 } 1056 1057 // Check for float load 1058 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1059 int offset = ra_->reg2offset(src_first); 1060 const char *op_str; 1061 int op; 1062 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? 1063 op_str = "FLD_D"; 1064 op = 0xDD; 1065 } else { // 32-bit load 1066 op_str = "FLD_S"; 1067 op = 0xD9; 1068 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 1069 } 1070 if( cbuf ) { 1071 emit_opcode (*cbuf, op ); 1072 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); 1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 1075 #ifndef PRODUCT 1076 } else if( !do_size ) { 1077 if( size != 0 ) st->print("\n\t"); 1078 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); 1079 #endif 1080 } 1081 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 1082 return size + 3+offset_size+2; 1083 } 1084 1085 // Check for xmm reg-reg copy 1086 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 1087 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 1088 (src_first+1 == src_second && dst_first+1 == dst_second), 1089 "no non-adjacent float-moves" ); 1090 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1091 } 1092 1093 // Check for xmm reg-integer reg copy 1094 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { 1095 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), 1096 "no 64 bit float-integer reg moves" ); 1097 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1098 } 1099 1100 // Check for xmm store 1101 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 1102 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); 1103 } 1104 1105 // Check for float xmm load 1106 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { 1107 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); 1108 } 1109 1110 // Copy from float reg to xmm reg 1111 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { 1112 // copy to the top of stack from floating point reg 1113 // and use LEA to preserve flags 1114 if( cbuf ) { 1115 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] 1116 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1117 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1118 emit_d8(*cbuf,0xF8); 1119 #ifndef PRODUCT 1120 } else if( !do_size ) { 1121 if( size != 0 ) st->print("\n\t"); 1122 st->print("LEA ESP,[ESP-8]"); 1123 #endif 1124 } 1125 size += 4; 1126 1127 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); 1128 1129 // Copy from the temp memory to the xmm reg. 1130 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); 1131 1132 if( cbuf ) { 1133 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] 1134 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1135 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1136 emit_d8(*cbuf,0x08); 1137 #ifndef PRODUCT 1138 } else if( !do_size ) { 1139 if( size != 0 ) st->print("\n\t"); 1140 st->print("LEA ESP,[ESP+8]"); 1141 #endif 1142 } 1143 size += 4; 1144 return size; 1145 } 1146 1147 assert( size > 0, "missed a case" ); 1148 1149 // -------------------------------------------------------------------- 1150 // Check for second bits still needing moving. 1151 if( src_second == dst_second ) 1152 return size; // Self copy; no move 1153 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1154 1155 // Check for second word int-int move 1156 if( src_second_rc == rc_int && dst_second_rc == rc_int ) 1157 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); 1158 1159 // Check for second word integer store 1160 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1161 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); 1162 1163 // Check for second word integer load 1164 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1165 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); 1166 1167 1168 Unimplemented(); 1169 } 1170 1171 #ifndef PRODUCT 1172 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1173 implementation( NULL, ra_, false, st ); 1174 } 1175 #endif 1176 1177 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1178 implementation( &cbuf, ra_, false, NULL ); 1179 } 1180 1181 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1182 return implementation( NULL, ra_, true, NULL ); 1183 } 1184 1185 //============================================================================= 1186 #ifndef PRODUCT 1187 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { 1188 st->print("NOP \t# %d bytes pad for loops and calls", _count); 1189 } 1190 #endif 1191 1192 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1193 MacroAssembler _masm(&cbuf); 1194 __ nop(_count); 1195 } 1196 1197 uint MachNopNode::size(PhaseRegAlloc *) const { 1198 return _count; 1199 } 1200 1201 1202 //============================================================================= 1203 #ifndef PRODUCT 1204 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1206 int reg = ra_->get_reg_first(this); 1207 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); 1208 } 1209 #endif 1210 1211 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1212 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1213 int reg = ra_->get_encode(this); 1214 if( offset >= 128 ) { 1215 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1216 emit_rm(cbuf, 0x2, reg, 0x04); 1217 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1218 emit_d32(cbuf, offset); 1219 } 1220 else { 1221 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1222 emit_rm(cbuf, 0x1, reg, 0x04); 1223 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1224 emit_d8(cbuf, offset); 1225 } 1226 } 1227 1228 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1229 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1230 if( offset >= 128 ) { 1231 return 7; 1232 } 1233 else { 1234 return 4; 1235 } 1236 } 1237 1238 //============================================================================= 1239 1240 // emit call stub, compiled java to interpreter 1241 void emit_java_to_interp(CodeBuffer &cbuf ) { 1242 // Stub is fixed up when the corresponding call is converted from calling 1243 // compiled code to calling interpreted code. 1244 // mov rbx,0 1245 // jmp -1 1246 1247 address mark = cbuf.insts_mark(); // get mark within main instrs section 1248 1249 // Note that the code buffer's insts_mark is always relative to insts. 1250 // That's why we must use the macroassembler to generate a stub. 1251 MacroAssembler _masm(&cbuf); 1252 1253 address base = 1254 __ start_a_stub(Compile::MAX_stubs_size); 1255 if (base == NULL) return; // CodeBuffer::expand failed 1256 // static stub relocation stores the instruction address of the call 1257 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1258 // static stub relocation also tags the methodOop in the code-stream. 1259 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time 1260 // This is recognized as unresolved by relocs/nativeInst/ic code 1261 __ jump(RuntimeAddress(__ pc())); 1262 1263 __ end_a_stub(); 1264 // Update current stubs pointer and restore insts_end. 1265 } 1266 // size of call stub, compiled java to interpretor 1267 uint size_java_to_interp() { 1268 return 10; // movl; jmp 1269 } 1270 // relocation entries for call stub, compiled java to interpretor 1271 uint reloc_java_to_interp() { 1272 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call 1273 } 1274 1275 //============================================================================= 1276 #ifndef PRODUCT 1277 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1278 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); 1279 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); 1280 st->print_cr("\tNOP"); 1281 st->print_cr("\tNOP"); 1282 if( !OptoBreakpoint ) 1283 st->print_cr("\tNOP"); 1284 } 1285 #endif 1286 1287 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1288 MacroAssembler masm(&cbuf); 1289 #ifdef ASSERT 1290 uint insts_size = cbuf.insts_size(); 1291 #endif 1292 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); 1293 masm.jump_cc(Assembler::notEqual, 1294 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1295 /* WARNING these NOPs are critical so that verified entry point is properly 1296 aligned for patching by NativeJump::patch_verified_entry() */ 1297 int nops_cnt = 2; 1298 if( !OptoBreakpoint ) // Leave space for int3 1299 nops_cnt += 1; 1300 masm.nop(nops_cnt); 1301 1302 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); 1303 } 1304 1305 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1306 return OptoBreakpoint ? 11 : 12; 1307 } 1308 1309 1310 //============================================================================= 1311 uint size_exception_handler() { 1312 // NativeCall instruction size is the same as NativeJump. 1313 // exception handler starts out as jump and can be patched to 1314 // a call be deoptimization. (4932387) 1315 // Note that this value is also credited (in output.cpp) to 1316 // the size of the code section. 1317 return NativeJump::instruction_size; 1318 } 1319 1320 // Emit exception handler code. Stuff framesize into a register 1321 // and call a VM stub routine. 1322 int emit_exception_handler(CodeBuffer& cbuf) { 1323 1324 // Note that the code buffer's insts_mark is always relative to insts. 1325 // That's why we must use the macroassembler to generate a handler. 1326 MacroAssembler _masm(&cbuf); 1327 address base = 1328 __ start_a_stub(size_exception_handler()); 1329 if (base == NULL) return 0; // CodeBuffer::expand failed 1330 int offset = __ offset(); 1331 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); 1332 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1333 __ end_a_stub(); 1334 return offset; 1335 } 1336 1337 uint size_deopt_handler() { 1338 // NativeCall instruction size is the same as NativeJump. 1339 // exception handler starts out as jump and can be patched to 1340 // a call be deoptimization. (4932387) 1341 // Note that this value is also credited (in output.cpp) to 1342 // the size of the code section. 1343 return 5 + NativeJump::instruction_size; // pushl(); jmp; 1344 } 1345 1346 // Emit deopt handler code. 1347 int emit_deopt_handler(CodeBuffer& cbuf) { 1348 1349 // Note that the code buffer's insts_mark is always relative to insts. 1350 // That's why we must use the macroassembler to generate a handler. 1351 MacroAssembler _masm(&cbuf); 1352 address base = 1353 __ start_a_stub(size_exception_handler()); 1354 if (base == NULL) return 0; // CodeBuffer::expand failed 1355 int offset = __ offset(); 1356 InternalAddress here(__ pc()); 1357 __ pushptr(here.addr()); 1358 1359 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 1360 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1361 __ end_a_stub(); 1362 return offset; 1363 } 1364 1365 1366 const bool Matcher::match_rule_supported(int opcode) { 1367 if (!has_match_rule(opcode)) 1368 return false; 1369 1370 return true; // Per default match rules are supported. 1371 } 1372 1373 int Matcher::regnum_to_fpu_offset(int regnum) { 1374 return regnum - 32; // The FP registers are in the second chunk 1375 } 1376 1377 // This is UltraSparc specific, true just means we have fast l2f conversion 1378 const bool Matcher::convL2FSupported(void) { 1379 return true; 1380 } 1381 1382 // Vector width in bytes 1383 const uint Matcher::vector_width_in_bytes(void) { 1384 return UseSSE >= 2 ? 8 : 0; 1385 } 1386 1387 // Vector ideal reg 1388 const uint Matcher::vector_ideal_reg(void) { 1389 return Op_RegD; 1390 } 1391 1392 // Is this branch offset short enough that a short branch can be used? 1393 // 1394 // NOTE: If the platform does not provide any short branch variants, then 1395 // this method should return false for offset 0. 1396 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1397 // The passed offset is relative to address of the branch. 1398 // On 86 a branch displacement is calculated relative to address 1399 // of a next instruction. 1400 offset -= br_size; 1401 1402 // the short version of jmpConUCF2 contains multiple branches, 1403 // making the reach slightly less 1404 if (rule == jmpConUCF2_rule) 1405 return (-126 <= offset && offset <= 125); 1406 return (-128 <= offset && offset <= 127); 1407 } 1408 1409 const bool Matcher::isSimpleConstant64(jlong value) { 1410 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1411 return false; 1412 } 1413 1414 // The ecx parameter to rep stos for the ClearArray node is in dwords. 1415 const bool Matcher::init_array_count_is_in_bytes = false; 1416 1417 // Threshold size for cleararray. 1418 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1419 1420 // Needs 2 CMOV's for longs. 1421 const int Matcher::long_cmove_cost() { return 1; } 1422 1423 // No CMOVF/CMOVD with SSE/SSE2 1424 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } 1425 1426 // Should the Matcher clone shifts on addressing modes, expecting them to 1427 // be subsumed into complex addressing expressions or compute them into 1428 // registers? True for Intel but false for most RISCs 1429 const bool Matcher::clone_shift_expressions = true; 1430 1431 // Do we need to mask the count passed to shift instructions or does 1432 // the cpu only look at the lower 5/6 bits anyway? 1433 const bool Matcher::need_masked_shift_count = false; 1434 1435 bool Matcher::narrow_oop_use_complex_address() { 1436 ShouldNotCallThis(); 1437 return true; 1438 } 1439 1440 1441 // Is it better to copy float constants, or load them directly from memory? 1442 // Intel can load a float constant from a direct address, requiring no 1443 // extra registers. Most RISCs will have to materialize an address into a 1444 // register first, so they would do better to copy the constant from stack. 1445 const bool Matcher::rematerialize_float_constants = true; 1446 1447 // If CPU can load and store mis-aligned doubles directly then no fixup is 1448 // needed. Else we split the double into 2 integer pieces and move it 1449 // piece-by-piece. Only happens when passing doubles into C code as the 1450 // Java calling convention forces doubles to be aligned. 1451 const bool Matcher::misaligned_doubles_ok = true; 1452 1453 1454 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1455 // Get the memory operand from the node 1456 uint numopnds = node->num_opnds(); // Virtual call for number of operands 1457 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far 1458 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); 1459 uint opcnt = 1; // First operand 1460 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand 1461 while( idx >= skipped+num_edges ) { 1462 skipped += num_edges; 1463 opcnt++; // Bump operand count 1464 assert( opcnt < numopnds, "Accessing non-existent operand" ); 1465 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand 1466 } 1467 1468 MachOper *memory = node->_opnds[opcnt]; 1469 MachOper *new_memory = NULL; 1470 switch (memory->opcode()) { 1471 case DIRECT: 1472 case INDOFFSET32X: 1473 // No transformation necessary. 1474 return; 1475 case INDIRECT: 1476 new_memory = new (C) indirect_win95_safeOper( ); 1477 break; 1478 case INDOFFSET8: 1479 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); 1480 break; 1481 case INDOFFSET32: 1482 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); 1483 break; 1484 case INDINDEXOFFSET: 1485 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); 1486 break; 1487 case INDINDEXSCALE: 1488 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); 1489 break; 1490 case INDINDEXSCALEOFFSET: 1491 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); 1492 break; 1493 case LOAD_LONG_INDIRECT: 1494 case LOAD_LONG_INDOFFSET32: 1495 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} 1496 return; 1497 default: 1498 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); 1499 return; 1500 } 1501 node->_opnds[opcnt] = new_memory; 1502 } 1503 1504 // Advertise here if the CPU requires explicit rounding operations 1505 // to implement the UseStrictFP mode. 1506 const bool Matcher::strict_fp_requires_explicit_rounding = true; 1507 1508 // Are floats conerted to double when stored to stack during deoptimization? 1509 // On x32 it is stored with convertion only when FPU is used for floats. 1510 bool Matcher::float_in_double() { return (UseSSE == 0); } 1511 1512 // Do ints take an entire long register or just half? 1513 const bool Matcher::int_in_long = false; 1514 1515 // Return whether or not this register is ever used as an argument. This 1516 // function is used on startup to build the trampoline stubs in generateOptoStub. 1517 // Registers not mentioned will be killed by the VM call in the trampoline, and 1518 // arguments in those registers not be available to the callee. 1519 bool Matcher::can_be_java_arg( int reg ) { 1520 if( reg == ECX_num || reg == EDX_num ) return true; 1521 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; 1522 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1523 return false; 1524 } 1525 1526 bool Matcher::is_spillable_arg( int reg ) { 1527 return can_be_java_arg(reg); 1528 } 1529 1530 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1531 // Use hardware integer DIV instruction when 1532 // it is faster than a code which use multiply. 1533 // Only when constant divisor fits into 32 bit 1534 // (min_jint is excluded to get only correct 1535 // positive 32 bit values from negative). 1536 return VM_Version::has_fast_idiv() && 1537 (divisor == (int)divisor && divisor != min_jint); 1538 } 1539 1540 // Register for DIVI projection of divmodI 1541 RegMask Matcher::divI_proj_mask() { 1542 return EAX_REG_mask(); 1543 } 1544 1545 // Register for MODI projection of divmodI 1546 RegMask Matcher::modI_proj_mask() { 1547 return EDX_REG_mask(); 1548 } 1549 1550 // Register for DIVL projection of divmodL 1551 RegMask Matcher::divL_proj_mask() { 1552 ShouldNotReachHere(); 1553 return RegMask(); 1554 } 1555 1556 // Register for MODL projection of divmodL 1557 RegMask Matcher::modL_proj_mask() { 1558 ShouldNotReachHere(); 1559 return RegMask(); 1560 } 1561 1562 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1563 return EBP_REG_mask(); 1564 } 1565 1566 // Returns true if the high 32 bits of the value is known to be zero. 1567 bool is_operand_hi32_zero(Node* n) { 1568 int opc = n->Opcode(); 1569 if (opc == Op_LoadUI2L) { 1570 return true; 1571 } 1572 if (opc == Op_AndL) { 1573 Node* o2 = n->in(2); 1574 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { 1575 return true; 1576 } 1577 } 1578 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { 1579 return true; 1580 } 1581 return false; 1582 } 1583 1584 %} 1585 1586 //----------ENCODING BLOCK----------------------------------------------------- 1587 // This block specifies the encoding classes used by the compiler to output 1588 // byte streams. Encoding classes generate functions which are called by 1589 // Machine Instruction Nodes in order to generate the bit encoding of the 1590 // instruction. Operands specify their base encoding interface with the 1591 // interface keyword. There are currently supported four interfaces, 1592 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1593 // operand to generate a function which returns its register number when 1594 // queried. CONST_INTER causes an operand to generate a function which 1595 // returns the value of the constant when queried. MEMORY_INTER causes an 1596 // operand to generate four functions which return the Base Register, the 1597 // Index Register, the Scale Value, and the Offset Value of the operand when 1598 // queried. COND_INTER causes an operand to generate six functions which 1599 // return the encoding code (ie - encoding bits for the instruction) 1600 // associated with each basic boolean condition for a conditional instruction. 1601 // Instructions specify two basic values for encoding. They use the 1602 // ins_encode keyword to specify their encoding class (which must be one of 1603 // the class names specified in the encoding block), and they use the 1604 // opcode keyword to specify, in order, their primary, secondary, and 1605 // tertiary opcode. Only the opcode sections which a particular instruction 1606 // needs for encoding need to be specified. 1607 encode %{ 1608 // Build emit functions for each basic byte or larger field in the intel 1609 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ 1610 // code in the enc_class source block. Emit functions will live in the 1611 // main source block for now. In future, we can generalize this by 1612 // adding a syntax that specifies the sizes of fields in an order, 1613 // so that the adlc can build the emit functions automagically 1614 1615 // Emit primary opcode 1616 enc_class OpcP %{ 1617 emit_opcode(cbuf, $primary); 1618 %} 1619 1620 // Emit secondary opcode 1621 enc_class OpcS %{ 1622 emit_opcode(cbuf, $secondary); 1623 %} 1624 1625 // Emit opcode directly 1626 enc_class Opcode(immI d8) %{ 1627 emit_opcode(cbuf, $d8$$constant); 1628 %} 1629 1630 enc_class SizePrefix %{ 1631 emit_opcode(cbuf,0x66); 1632 %} 1633 1634 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 1635 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1636 %} 1637 1638 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) 1639 emit_opcode(cbuf,$opcode$$constant); 1640 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1641 %} 1642 1643 enc_class mov_r32_imm0( eRegI dst ) %{ 1644 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1645 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1646 %} 1647 1648 enc_class cdq_enc %{ 1649 // Full implementation of Java idiv and irem; checks for 1650 // special case as described in JVM spec., p.243 & p.271. 1651 // 1652 // normal case special case 1653 // 1654 // input : rax,: dividend min_int 1655 // reg: divisor -1 1656 // 1657 // output: rax,: quotient (= rax, idiv reg) min_int 1658 // rdx: remainder (= rax, irem reg) 0 1659 // 1660 // Code sequnce: 1661 // 1662 // 81 F8 00 00 00 80 cmp rax,80000000h 1663 // 0F 85 0B 00 00 00 jne normal_case 1664 // 33 D2 xor rdx,edx 1665 // 83 F9 FF cmp rcx,0FFh 1666 // 0F 84 03 00 00 00 je done 1667 // normal_case: 1668 // 99 cdq 1669 // F7 F9 idiv rax,ecx 1670 // done: 1671 // 1672 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); 1673 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); 1674 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h 1675 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); 1676 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); 1677 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case 1678 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx 1679 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh 1680 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); 1681 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); 1682 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done 1683 // normal_case: 1684 emit_opcode(cbuf,0x99); // cdq 1685 // idiv (note: must be emitted by the user of this rule) 1686 // normal: 1687 %} 1688 1689 // Dense encoding for older common ops 1690 enc_class Opc_plus(immI opcode, eRegI reg) %{ 1691 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1692 %} 1693 1694 1695 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1696 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit 1697 // Check for 8-bit immediate, and set sign extend bit in opcode 1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1699 emit_opcode(cbuf, $primary | 0x02); 1700 } 1701 else { // If 32-bit immediate 1702 emit_opcode(cbuf, $primary); 1703 } 1704 %} 1705 1706 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m 1707 // Emit primary opcode and set sign-extend bit 1708 // Check for 8-bit immediate, and set sign extend bit in opcode 1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1710 emit_opcode(cbuf, $primary | 0x02); } 1711 else { // If 32-bit immediate 1712 emit_opcode(cbuf, $primary); 1713 } 1714 // Emit r/m byte with secondary opcode, after primary opcode. 1715 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1716 %} 1717 1718 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits 1719 // Check for 8-bit immediate, and set sign extend bit in opcode 1720 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1721 $$$emit8$imm$$constant; 1722 } 1723 else { // If 32-bit immediate 1724 // Output immediate 1725 $$$emit32$imm$$constant; 1726 } 1727 %} 1728 1729 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ 1730 // Emit primary opcode and set sign-extend bit 1731 // Check for 8-bit immediate, and set sign extend bit in opcode 1732 int con = (int)$imm$$constant; // Throw away top bits 1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1734 // Emit r/m byte with secondary opcode, after primary opcode. 1735 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1737 else emit_d32(cbuf,con); 1738 %} 1739 1740 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ 1741 // Emit primary opcode and set sign-extend bit 1742 // Check for 8-bit immediate, and set sign extend bit in opcode 1743 int con = (int)($imm$$constant >> 32); // Throw away bottom bits 1744 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1745 // Emit r/m byte with tertiary opcode, after primary opcode. 1746 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1747 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1748 else emit_d32(cbuf,con); 1749 %} 1750 1751 enc_class OpcSReg (eRegI dst) %{ // BSWAP 1752 emit_cc(cbuf, $secondary, $dst$$reg ); 1753 %} 1754 1755 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1756 int destlo = $dst$$reg; 1757 int desthi = HIGH_FROM_LOW(destlo); 1758 // bswap lo 1759 emit_opcode(cbuf, 0x0F); 1760 emit_cc(cbuf, 0xC8, destlo); 1761 // bswap hi 1762 emit_opcode(cbuf, 0x0F); 1763 emit_cc(cbuf, 0xC8, desthi); 1764 // xchg lo and hi 1765 emit_opcode(cbuf, 0x87); 1766 emit_rm(cbuf, 0x3, destlo, desthi); 1767 %} 1768 1769 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1770 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1771 %} 1772 1773 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1774 $$$emit8$primary; 1775 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1776 %} 1777 1778 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV 1779 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); 1780 emit_d8(cbuf, op >> 8 ); 1781 emit_d8(cbuf, op & 255); 1782 %} 1783 1784 // emulate a CMOV with a conditional branch around a MOV 1785 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV 1786 // Invert sense of branch from sense of CMOV 1787 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); 1788 emit_d8( cbuf, $brOffs$$constant ); 1789 %} 1790 1791 enc_class enc_PartialSubtypeCheck( ) %{ 1792 Register Redi = as_Register(EDI_enc); // result register 1793 Register Reax = as_Register(EAX_enc); // super class 1794 Register Recx = as_Register(ECX_enc); // killed 1795 Register Resi = as_Register(ESI_enc); // sub class 1796 Label miss; 1797 1798 MacroAssembler _masm(&cbuf); 1799 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, 1800 NULL, &miss, 1801 /*set_cond_codes:*/ true); 1802 if ($primary) { 1803 __ xorptr(Redi, Redi); 1804 } 1805 __ bind(miss); 1806 %} 1807 1808 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All 1809 MacroAssembler masm(&cbuf); 1810 int start = masm.offset(); 1811 if (UseSSE >= 2) { 1812 if (VerifyFPU) { 1813 masm.verify_FPU(0, "must be empty in SSE2+ mode"); 1814 } 1815 } else { 1816 // External c_calling_convention expects the FPU stack to be 'clean'. 1817 // Compiled code leaves it dirty. Do cleanup now. 1818 masm.empty_FPU_stack(); 1819 } 1820 if (sizeof_FFree_Float_Stack_All == -1) { 1821 sizeof_FFree_Float_Stack_All = masm.offset() - start; 1822 } else { 1823 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); 1824 } 1825 %} 1826 1827 enc_class Verify_FPU_For_Leaf %{ 1828 if( VerifyFPU ) { 1829 MacroAssembler masm(&cbuf); 1830 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); 1831 } 1832 %} 1833 1834 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf 1835 // This is the instruction starting address for relocation info. 1836 cbuf.set_insts_mark(); 1837 $$$emit8$primary; 1838 // CALL directly to the runtime 1839 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1840 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1841 1842 if (UseSSE >= 2) { 1843 MacroAssembler _masm(&cbuf); 1844 BasicType rt = tf()->return_type(); 1845 1846 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { 1847 // A C runtime call where the return value is unused. In SSE2+ 1848 // mode the result needs to be removed from the FPU stack. It's 1849 // likely that this function call could be removed by the 1850 // optimizer if the C function is a pure function. 1851 __ ffree(0); 1852 } else if (rt == T_FLOAT) { 1853 __ lea(rsp, Address(rsp, -4)); 1854 __ fstp_s(Address(rsp, 0)); 1855 __ movflt(xmm0, Address(rsp, 0)); 1856 __ lea(rsp, Address(rsp, 4)); 1857 } else if (rt == T_DOUBLE) { 1858 __ lea(rsp, Address(rsp, -8)); 1859 __ fstp_d(Address(rsp, 0)); 1860 __ movdbl(xmm0, Address(rsp, 0)); 1861 __ lea(rsp, Address(rsp, 8)); 1862 } 1863 } 1864 %} 1865 1866 1867 enc_class pre_call_FPU %{ 1868 // If method sets FPU control word restore it here 1869 debug_only(int off0 = cbuf.insts_size()); 1870 if( Compile::current()->in_24_bit_fp_mode() ) { 1871 MacroAssembler masm(&cbuf); 1872 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1873 } 1874 debug_only(int off1 = cbuf.insts_size()); 1875 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); 1876 %} 1877 1878 enc_class post_call_FPU %{ 1879 // If method sets FPU control word do it here also 1880 if( Compile::current()->in_24_bit_fp_mode() ) { 1881 MacroAssembler masm(&cbuf); 1882 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1883 } 1884 %} 1885 1886 enc_class preserve_SP %{ 1887 debug_only(int off0 = cbuf.insts_size()); 1888 MacroAssembler _masm(&cbuf); 1889 // RBP is preserved across all calls, even compiled calls. 1890 // Use it to preserve RSP in places where the callee might change the SP. 1891 __ movptr(rbp_mh_SP_save, rsp); 1892 debug_only(int off1 = cbuf.insts_size()); 1893 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); 1894 %} 1895 1896 enc_class restore_SP %{ 1897 MacroAssembler _masm(&cbuf); 1898 __ movptr(rsp, rbp_mh_SP_save); 1899 %} 1900 1901 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1902 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1903 // who we intended to call. 1904 cbuf.set_insts_mark(); 1905 $$$emit8$primary; 1906 if ( !_method ) { 1907 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1908 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1909 } else if(_optimized_virtual) { 1910 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1911 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); 1912 } else { 1913 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1914 static_call_Relocation::spec(), RELOC_IMM32 ); 1915 } 1916 if( _method ) { // Emit stub for static call 1917 emit_java_to_interp(cbuf); 1918 } 1919 %} 1920 1921 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1922 // !!!!! 1923 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info 1924 // emit_call_dynamic_prologue( cbuf ); 1925 cbuf.set_insts_mark(); 1926 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 1927 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); 1928 address virtual_call_oop_addr = cbuf.insts_mark(); 1929 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1930 // who we intended to call. 1931 cbuf.set_insts_mark(); 1932 $$$emit8$primary; 1933 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1934 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); 1935 %} 1936 1937 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1938 int disp = in_bytes(methodOopDesc::from_compiled_offset()); 1939 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1940 1941 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] 1942 cbuf.set_insts_mark(); 1943 $$$emit8$primary; 1944 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1945 emit_d8(cbuf, disp); // Displacement 1946 1947 %} 1948 1949 // Following encoding is no longer used, but may be restored if calling 1950 // convention changes significantly. 1951 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) 1952 // 1953 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL 1954 // // int ic_reg = Matcher::inline_cache_reg(); 1955 // // int ic_encode = Matcher::_regEncode[ic_reg]; 1956 // // int imo_reg = Matcher::interpreter_method_oop_reg(); 1957 // // int imo_encode = Matcher::_regEncode[imo_reg]; 1958 // 1959 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, 1960 // // // so we load it immediately before the call 1961 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop 1962 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte 1963 // 1964 // // xor rbp,ebp 1965 // emit_opcode(cbuf, 0x33); 1966 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); 1967 // 1968 // // CALL to interpreter. 1969 // cbuf.set_insts_mark(); 1970 // $$$emit8$primary; 1971 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), 1972 // runtime_call_Relocation::spec(), RELOC_IMM32 ); 1973 // %} 1974 1975 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1976 $$$emit8$primary; 1977 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1978 $$$emit8$shift$$constant; 1979 %} 1980 1981 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate 1982 // Load immediate does not have a zero or sign extended version 1983 // for 8-bit immediates 1984 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1985 $$$emit32$src$$constant; 1986 %} 1987 1988 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate 1989 // Load immediate does not have a zero or sign extended version 1990 // for 8-bit immediates 1991 emit_opcode(cbuf, $primary + $dst$$reg); 1992 $$$emit32$src$$constant; 1993 %} 1994 1995 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate 1996 // Load immediate does not have a zero or sign extended version 1997 // for 8-bit immediates 1998 int dst_enc = $dst$$reg; 1999 int src_con = $src$$constant & 0x0FFFFFFFFL; 2000 if (src_con == 0) { 2001 // xor dst, dst 2002 emit_opcode(cbuf, 0x33); 2003 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 2004 } else { 2005 emit_opcode(cbuf, $primary + dst_enc); 2006 emit_d32(cbuf, src_con); 2007 } 2008 %} 2009 2010 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate 2011 // Load immediate does not have a zero or sign extended version 2012 // for 8-bit immediates 2013 int dst_enc = $dst$$reg + 2; 2014 int src_con = ((julong)($src$$constant)) >> 32; 2015 if (src_con == 0) { 2016 // xor dst, dst 2017 emit_opcode(cbuf, 0x33); 2018 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 2019 } else { 2020 emit_opcode(cbuf, $primary + dst_enc); 2021 emit_d32(cbuf, src_con); 2022 } 2023 %} 2024 2025 2026 // Encode a reg-reg copy. If it is useless, then empty encoding. 2027 enc_class enc_Copy( eRegI dst, eRegI src ) %{ 2028 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2029 %} 2030 2031 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ 2032 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2033 %} 2034 2035 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 2036 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2037 %} 2038 2039 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2040 $$$emit8$primary; 2041 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2042 %} 2043 2044 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) 2045 $$$emit8$secondary; 2046 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2047 %} 2048 2049 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) 2050 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2051 %} 2052 2053 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2054 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2055 %} 2056 2057 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ 2058 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2059 %} 2060 2061 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2062 // Output immediate 2063 $$$emit32$src$$constant; 2064 %} 2065 2066 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm 2067 // Output Float immediate bits 2068 jfloat jf = $src$$constant; 2069 int jf_as_bits = jint_cast( jf ); 2070 emit_d32(cbuf, jf_as_bits); 2071 %} 2072 2073 enc_class Con32F_as_bits(immF src) %{ // storeX_imm 2074 // Output Float immediate bits 2075 jfloat jf = $src$$constant; 2076 int jf_as_bits = jint_cast( jf ); 2077 emit_d32(cbuf, jf_as_bits); 2078 %} 2079 2080 enc_class Con16 (immI src) %{ // Con16(storeImmI) 2081 // Output immediate 2082 $$$emit16$src$$constant; 2083 %} 2084 2085 enc_class Con_d32(immI src) %{ 2086 emit_d32(cbuf,$src$$constant); 2087 %} 2088 2089 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) 2090 // Output immediate memory reference 2091 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2092 emit_d32(cbuf, 0x00); 2093 %} 2094 2095 enc_class lock_prefix( ) %{ 2096 if( os::is_MP() ) 2097 emit_opcode(cbuf,0xF0); // [Lock] 2098 %} 2099 2100 // Cmp-xchg long value. 2101 // Note: we need to swap rbx, and rcx before and after the 2102 // cmpxchg8 instruction because the instruction uses 2103 // rcx as the high order word of the new value to store but 2104 // our register encoding uses rbx,. 2105 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ 2106 2107 // XCHG rbx,ecx 2108 emit_opcode(cbuf,0x87); 2109 emit_opcode(cbuf,0xD9); 2110 // [Lock] 2111 if( os::is_MP() ) 2112 emit_opcode(cbuf,0xF0); 2113 // CMPXCHG8 [Eptr] 2114 emit_opcode(cbuf,0x0F); 2115 emit_opcode(cbuf,0xC7); 2116 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2117 // XCHG rbx,ecx 2118 emit_opcode(cbuf,0x87); 2119 emit_opcode(cbuf,0xD9); 2120 %} 2121 2122 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ 2123 // [Lock] 2124 if( os::is_MP() ) 2125 emit_opcode(cbuf,0xF0); 2126 2127 // CMPXCHG [Eptr] 2128 emit_opcode(cbuf,0x0F); 2129 emit_opcode(cbuf,0xB1); 2130 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2131 %} 2132 2133 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ 2134 int res_encoding = $res$$reg; 2135 2136 // MOV res,0 2137 emit_opcode( cbuf, 0xB8 + res_encoding); 2138 emit_d32( cbuf, 0 ); 2139 // JNE,s fail 2140 emit_opcode(cbuf,0x75); 2141 emit_d8(cbuf, 5 ); 2142 // MOV res,1 2143 emit_opcode( cbuf, 0xB8 + res_encoding); 2144 emit_d32( cbuf, 1 ); 2145 // fail: 2146 %} 2147 2148 enc_class set_instruction_start( ) %{ 2149 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2150 %} 2151 2152 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem 2153 int reg_encoding = $ereg$$reg; 2154 int base = $mem$$base; 2155 int index = $mem$$index; 2156 int scale = $mem$$scale; 2157 int displace = $mem$$disp; 2158 bool disp_is_oop = $mem->disp_is_oop(); 2159 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2160 %} 2161 2162 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2163 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2164 int base = $mem$$base; 2165 int index = $mem$$index; 2166 int scale = $mem$$scale; 2167 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2168 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); 2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); 2170 %} 2171 2172 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2173 int r1, r2; 2174 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2175 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2176 emit_opcode(cbuf,0x0F); 2177 emit_opcode(cbuf,$tertiary); 2178 emit_rm(cbuf, 0x3, r1, r2); 2179 emit_d8(cbuf,$cnt$$constant); 2180 emit_d8(cbuf,$primary); 2181 emit_rm(cbuf, 0x3, $secondary, r1); 2182 emit_d8(cbuf,$cnt$$constant); 2183 %} 2184 2185 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ 2186 emit_opcode( cbuf, 0x8B ); // Move 2187 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2188 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2189 emit_d8(cbuf,$primary); 2190 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 2191 emit_d8(cbuf,$cnt$$constant-32); 2192 } 2193 emit_d8(cbuf,$primary); 2194 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); 2195 emit_d8(cbuf,31); 2196 %} 2197 2198 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ 2199 int r1, r2; 2200 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2201 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2202 2203 emit_opcode( cbuf, 0x8B ); // Move r1,r2 2204 emit_rm(cbuf, 0x3, r1, r2); 2205 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2206 emit_opcode(cbuf,$primary); 2207 emit_rm(cbuf, 0x3, $secondary, r1); 2208 emit_d8(cbuf,$cnt$$constant-32); 2209 } 2210 emit_opcode(cbuf,0x33); // XOR r2,r2 2211 emit_rm(cbuf, 0x3, r2, r2); 2212 %} 2213 2214 // Clone of RegMem but accepts an extra parameter to access each 2215 // half of a double in memory; it never needs relocation info. 2216 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ 2217 emit_opcode(cbuf,$opcode$$constant); 2218 int reg_encoding = $rm_reg$$reg; 2219 int base = $mem$$base; 2220 int index = $mem$$index; 2221 int scale = $mem$$scale; 2222 int displace = $mem$$disp + $disp_for_half$$constant; 2223 bool disp_is_oop = false; 2224 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2225 %} 2226 2227 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2228 // 2229 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2230 // and it never needs relocation information. 2231 // Frequently used to move data between FPU's Stack Top and memory. 2232 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ 2233 int rm_byte_opcode = $rm_opcode$$constant; 2234 int base = $mem$$base; 2235 int index = $mem$$index; 2236 int scale = $mem$$scale; 2237 int displace = $mem$$disp; 2238 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); 2239 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); 2240 %} 2241 2242 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2243 int rm_byte_opcode = $rm_opcode$$constant; 2244 int base = $mem$$base; 2245 int index = $mem$$index; 2246 int scale = $mem$$scale; 2247 int displace = $mem$$disp; 2248 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2249 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2250 %} 2251 2252 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea 2253 int reg_encoding = $dst$$reg; 2254 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2255 int index = 0x04; // 0x04 indicates no index 2256 int scale = 0x00; // 0x00 indicates no scale 2257 int displace = $src1$$constant; // 0x00 indicates no displacement 2258 bool disp_is_oop = false; 2259 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2260 %} 2261 2262 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN 2263 // Compare dst,src 2264 emit_opcode(cbuf,0x3B); 2265 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2266 // jmp dst < src around move 2267 emit_opcode(cbuf,0x7C); 2268 emit_d8(cbuf,2); 2269 // move dst,src 2270 emit_opcode(cbuf,0x8B); 2271 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2272 %} 2273 2274 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX 2275 // Compare dst,src 2276 emit_opcode(cbuf,0x3B); 2277 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2278 // jmp dst > src around move 2279 emit_opcode(cbuf,0x7F); 2280 emit_d8(cbuf,2); 2281 // move dst,src 2282 emit_opcode(cbuf,0x8B); 2283 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2284 %} 2285 2286 enc_class enc_FPR_store(memory mem, regDPR src) %{ 2287 // If src is FPR1, we can just FST to store it. 2288 // Else we need to FLD it to FPR1, then FSTP to store/pop it. 2289 int reg_encoding = 0x2; // Just store 2290 int base = $mem$$base; 2291 int index = $mem$$index; 2292 int scale = $mem$$scale; 2293 int displace = $mem$$disp; 2294 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2295 if( $src$$reg != FPR1L_enc ) { 2296 reg_encoding = 0x3; // Store & pop 2297 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2298 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2299 } 2300 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2301 emit_opcode(cbuf,$primary); 2302 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2303 %} 2304 2305 enc_class neg_reg(eRegI dst) %{ 2306 // NEG $dst 2307 emit_opcode(cbuf,0xF7); 2308 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2309 %} 2310 2311 enc_class setLT_reg(eCXRegI dst) %{ 2312 // SETLT $dst 2313 emit_opcode(cbuf,0x0F); 2314 emit_opcode(cbuf,0x9C); 2315 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); 2316 %} 2317 2318 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT 2319 int tmpReg = $tmp$$reg; 2320 2321 // SUB $p,$q 2322 emit_opcode(cbuf,0x2B); 2323 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2324 // SBB $tmp,$tmp 2325 emit_opcode(cbuf,0x1B); 2326 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2327 // AND $tmp,$y 2328 emit_opcode(cbuf,0x23); 2329 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); 2330 // ADD $p,$tmp 2331 emit_opcode(cbuf,0x03); 2332 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2333 %} 2334 2335 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2336 int tmpReg = $tmp$$reg; 2337 2338 // SUB $p,$q 2339 emit_opcode(cbuf,0x2B); 2340 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2341 // SBB $tmp,$tmp 2342 emit_opcode(cbuf,0x1B); 2343 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2344 // AND $tmp,$y 2345 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2346 emit_opcode(cbuf,0x23); 2347 int reg_encoding = tmpReg; 2348 int base = $mem$$base; 2349 int index = $mem$$index; 2350 int scale = $mem$$scale; 2351 int displace = $mem$$disp; 2352 bool disp_is_oop = $mem->disp_is_oop(); 2353 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2354 // ADD $p,$tmp 2355 emit_opcode(cbuf,0x03); 2356 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2357 %} 2358 2359 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ 2360 // TEST shift,32 2361 emit_opcode(cbuf,0xF7); 2362 emit_rm(cbuf, 0x3, 0, ECX_enc); 2363 emit_d32(cbuf,0x20); 2364 // JEQ,s small 2365 emit_opcode(cbuf, 0x74); 2366 emit_d8(cbuf, 0x04); 2367 // MOV $dst.hi,$dst.lo 2368 emit_opcode( cbuf, 0x8B ); 2369 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2370 // CLR $dst.lo 2371 emit_opcode(cbuf, 0x33); 2372 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 2373 // small: 2374 // SHLD $dst.hi,$dst.lo,$shift 2375 emit_opcode(cbuf,0x0F); 2376 emit_opcode(cbuf,0xA5); 2377 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2378 // SHL $dst.lo,$shift" 2379 emit_opcode(cbuf,0xD3); 2380 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); 2381 %} 2382 2383 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ 2384 // TEST shift,32 2385 emit_opcode(cbuf,0xF7); 2386 emit_rm(cbuf, 0x3, 0, ECX_enc); 2387 emit_d32(cbuf,0x20); 2388 // JEQ,s small 2389 emit_opcode(cbuf, 0x74); 2390 emit_d8(cbuf, 0x04); 2391 // MOV $dst.lo,$dst.hi 2392 emit_opcode( cbuf, 0x8B ); 2393 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2394 // CLR $dst.hi 2395 emit_opcode(cbuf, 0x33); 2396 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); 2397 // small: 2398 // SHRD $dst.lo,$dst.hi,$shift 2399 emit_opcode(cbuf,0x0F); 2400 emit_opcode(cbuf,0xAD); 2401 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2402 // SHR $dst.hi,$shift" 2403 emit_opcode(cbuf,0xD3); 2404 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); 2405 %} 2406 2407 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ 2408 // TEST shift,32 2409 emit_opcode(cbuf,0xF7); 2410 emit_rm(cbuf, 0x3, 0, ECX_enc); 2411 emit_d32(cbuf,0x20); 2412 // JEQ,s small 2413 emit_opcode(cbuf, 0x74); 2414 emit_d8(cbuf, 0x05); 2415 // MOV $dst.lo,$dst.hi 2416 emit_opcode( cbuf, 0x8B ); 2417 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2418 // SAR $dst.hi,31 2419 emit_opcode(cbuf, 0xC1); 2420 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); 2421 emit_d8(cbuf, 0x1F ); 2422 // small: 2423 // SHRD $dst.lo,$dst.hi,$shift 2424 emit_opcode(cbuf,0x0F); 2425 emit_opcode(cbuf,0xAD); 2426 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2427 // SAR $dst.hi,$shift" 2428 emit_opcode(cbuf,0xD3); 2429 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); 2430 %} 2431 2432 2433 // ----------------- Encodings for floating point unit ----------------- 2434 // May leave result in FPU-TOS or FPU reg depending on opcodes 2435 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV 2436 $$$emit8$primary; 2437 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); 2438 %} 2439 2440 // Pop argument in FPR0 with FSTP ST(0) 2441 enc_class PopFPU() %{ 2442 emit_opcode( cbuf, 0xDD ); 2443 emit_d8( cbuf, 0xD8 ); 2444 %} 2445 2446 // !!!!! equivalent to Pop_Reg_F 2447 enc_class Pop_Reg_DPR( regDPR dst ) %{ 2448 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2449 emit_d8( cbuf, 0xD8+$dst$$reg ); 2450 %} 2451 2452 enc_class Push_Reg_DPR( regDPR dst ) %{ 2453 emit_opcode( cbuf, 0xD9 ); 2454 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) 2455 %} 2456 2457 enc_class strictfp_bias1( regDPR dst ) %{ 2458 emit_opcode( cbuf, 0xDB ); // FLD m80real 2459 emit_opcode( cbuf, 0x2D ); 2460 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); 2461 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2462 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2463 %} 2464 2465 enc_class strictfp_bias2( regDPR dst ) %{ 2466 emit_opcode( cbuf, 0xDB ); // FLD m80real 2467 emit_opcode( cbuf, 0x2D ); 2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); 2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2470 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2471 %} 2472 2473 // Special case for moving an integer register to a stack slot. 2474 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2475 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2476 %} 2477 2478 // Special case for moving a register to a stack slot. 2479 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2480 // Opcode already emitted 2481 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2482 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2483 emit_d32(cbuf, $dst$$disp); // Displacement 2484 %} 2485 2486 // Push the integer in stackSlot 'src' onto FP-stack 2487 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] 2488 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); 2489 %} 2490 2491 // Push FPU's TOS float to a stack-slot, and pop FPU-stack 2492 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] 2493 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); 2494 %} 2495 2496 // Same as Pop_Mem_F except for opcode 2497 // Push FPU's TOS double to a stack-slot, and pop FPU-stack 2498 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] 2499 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); 2500 %} 2501 2502 enc_class Pop_Reg_FPR( regFPR dst ) %{ 2503 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2504 emit_d8( cbuf, 0xD8+$dst$$reg ); 2505 %} 2506 2507 enc_class Push_Reg_FPR( regFPR dst ) %{ 2508 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2509 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2510 %} 2511 2512 // Push FPU's float to a stack-slot, and pop FPU-stack 2513 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ 2514 int pop = 0x02; 2515 if ($src$$reg != FPR1L_enc) { 2516 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2517 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2518 pop = 0x03; 2519 } 2520 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] 2521 %} 2522 2523 // Push FPU's double to a stack-slot, and pop FPU-stack 2524 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ 2525 int pop = 0x02; 2526 if ($src$$reg != FPR1L_enc) { 2527 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2528 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2529 pop = 0x03; 2530 } 2531 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] 2532 %} 2533 2534 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack 2535 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ 2536 int pop = 0xD0 - 1; // -1 since we skip FLD 2537 if ($src$$reg != FPR1L_enc) { 2538 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) 2539 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2540 pop = 0xD8; 2541 } 2542 emit_opcode( cbuf, 0xDD ); 2543 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) 2544 %} 2545 2546 2547 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ 2548 // load dst in FPR0 2549 emit_opcode( cbuf, 0xD9 ); 2550 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2551 if ($src$$reg != FPR1L_enc) { 2552 // fincstp 2553 emit_opcode (cbuf, 0xD9); 2554 emit_opcode (cbuf, 0xF7); 2555 // swap src with FPR1: 2556 // FXCH FPR1 with src 2557 emit_opcode(cbuf, 0xD9); 2558 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2559 // fdecstp 2560 emit_opcode (cbuf, 0xD9); 2561 emit_opcode (cbuf, 0xF6); 2562 } 2563 %} 2564 2565 enc_class Push_ModD_encoding(regD src0, regD src1) %{ 2566 MacroAssembler _masm(&cbuf); 2567 __ subptr(rsp, 8); 2568 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); 2569 __ fld_d(Address(rsp, 0)); 2570 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); 2571 __ fld_d(Address(rsp, 0)); 2572 %} 2573 2574 enc_class Push_ModF_encoding(regF src0, regF src1) %{ 2575 MacroAssembler _masm(&cbuf); 2576 __ subptr(rsp, 4); 2577 __ movflt(Address(rsp, 0), $src1$$XMMRegister); 2578 __ fld_s(Address(rsp, 0)); 2579 __ movflt(Address(rsp, 0), $src0$$XMMRegister); 2580 __ fld_s(Address(rsp, 0)); 2581 %} 2582 2583 enc_class Push_ResultD(regD dst) %{ 2584 MacroAssembler _masm(&cbuf); 2585 __ fstp_d(Address(rsp, 0)); 2586 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); 2587 __ addptr(rsp, 8); 2588 %} 2589 2590 enc_class Push_ResultF(regF dst, immI d8) %{ 2591 MacroAssembler _masm(&cbuf); 2592 __ fstp_s(Address(rsp, 0)); 2593 __ movflt($dst$$XMMRegister, Address(rsp, 0)); 2594 __ addptr(rsp, $d8$$constant); 2595 %} 2596 2597 enc_class Push_SrcD(regD src) %{ 2598 MacroAssembler _masm(&cbuf); 2599 __ subptr(rsp, 8); 2600 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 2601 __ fld_d(Address(rsp, 0)); 2602 %} 2603 2604 enc_class push_stack_temp_qword() %{ 2605 MacroAssembler _masm(&cbuf); 2606 __ subptr(rsp, 8); 2607 %} 2608 2609 enc_class pop_stack_temp_qword() %{ 2610 MacroAssembler _masm(&cbuf); 2611 __ addptr(rsp, 8); 2612 %} 2613 2614 enc_class push_xmm_to_fpr1(regD src) %{ 2615 MacroAssembler _masm(&cbuf); 2616 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 2617 __ fld_d(Address(rsp, 0)); 2618 %} 2619 2620 // Compute X^Y using Intel's fast hardware instructions, if possible. 2621 // Otherwise return a NaN. 2622 enc_class pow_exp_core_encoding %{ 2623 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) 2624 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q 2625 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q 2626 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) 2627 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) 2628 emit_opcode(cbuf,0x1C); 2629 emit_d8(cbuf,0x24); 2630 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 2631 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 2632 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) 2633 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) 2634 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); 2635 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask 2636 emit_rm(cbuf, 0x3, 0x0, ECX_enc); 2637 emit_d32(cbuf,0xFFFFF800); 2638 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias 2639 emit_rm(cbuf, 0x3, 0x0, EAX_enc); 2640 emit_d32(cbuf,1023); 2641 emit_opcode(cbuf,0x8B); // mov rbx,eax 2642 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); 2643 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position 2644 emit_rm(cbuf,0x3,0x4,EAX_enc); 2645 emit_d8(cbuf,20); 2646 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow 2647 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); 2648 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX 2649 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); 2650 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word 2651 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); 2652 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) 2653 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2654 emit_d32(cbuf,0); 2655 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q 2656 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); 2657 %} 2658 2659 enc_class Push_Result_Mod_DPR( regDPR src) %{ 2660 if ($src$$reg != FPR1L_enc) { 2661 // fincstp 2662 emit_opcode (cbuf, 0xD9); 2663 emit_opcode (cbuf, 0xF7); 2664 // FXCH FPR1 with src 2665 emit_opcode(cbuf, 0xD9); 2666 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2667 // fdecstp 2668 emit_opcode (cbuf, 0xD9); 2669 emit_opcode (cbuf, 0xF6); 2670 } 2671 // // following asm replaced with Pop_Reg_F or Pop_Mem_F 2672 // // FSTP FPR$dst$$reg 2673 // emit_opcode( cbuf, 0xDD ); 2674 // emit_d8( cbuf, 0xD8+$dst$$reg ); 2675 %} 2676 2677 enc_class fnstsw_sahf_skip_parity() %{ 2678 // fnstsw ax 2679 emit_opcode( cbuf, 0xDF ); 2680 emit_opcode( cbuf, 0xE0 ); 2681 // sahf 2682 emit_opcode( cbuf, 0x9E ); 2683 // jnp ::skip 2684 emit_opcode( cbuf, 0x7B ); 2685 emit_opcode( cbuf, 0x05 ); 2686 %} 2687 2688 enc_class emitModDPR() %{ 2689 // fprem must be iterative 2690 // :: loop 2691 // fprem 2692 emit_opcode( cbuf, 0xD9 ); 2693 emit_opcode( cbuf, 0xF8 ); 2694 // wait 2695 emit_opcode( cbuf, 0x9b ); 2696 // fnstsw ax 2697 emit_opcode( cbuf, 0xDF ); 2698 emit_opcode( cbuf, 0xE0 ); 2699 // sahf 2700 emit_opcode( cbuf, 0x9E ); 2701 // jp ::loop 2702 emit_opcode( cbuf, 0x0F ); 2703 emit_opcode( cbuf, 0x8A ); 2704 emit_opcode( cbuf, 0xF4 ); 2705 emit_opcode( cbuf, 0xFF ); 2706 emit_opcode( cbuf, 0xFF ); 2707 emit_opcode( cbuf, 0xFF ); 2708 %} 2709 2710 enc_class fpu_flags() %{ 2711 // fnstsw_ax 2712 emit_opcode( cbuf, 0xDF); 2713 emit_opcode( cbuf, 0xE0); 2714 // test ax,0x0400 2715 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate 2716 emit_opcode( cbuf, 0xA9 ); 2717 emit_d16 ( cbuf, 0x0400 ); 2718 // // // This sequence works, but stalls for 12-16 cycles on PPro 2719 // // test rax,0x0400 2720 // emit_opcode( cbuf, 0xA9 ); 2721 // emit_d32 ( cbuf, 0x00000400 ); 2722 // 2723 // jz exit (no unordered comparison) 2724 emit_opcode( cbuf, 0x74 ); 2725 emit_d8 ( cbuf, 0x02 ); 2726 // mov ah,1 - treat as LT case (set carry flag) 2727 emit_opcode( cbuf, 0xB4 ); 2728 emit_d8 ( cbuf, 0x01 ); 2729 // sahf 2730 emit_opcode( cbuf, 0x9E); 2731 %} 2732 2733 enc_class cmpF_P6_fixup() %{ 2734 // Fixup the integer flags in case comparison involved a NaN 2735 // 2736 // JNP exit (no unordered comparison, P-flag is set by NaN) 2737 emit_opcode( cbuf, 0x7B ); 2738 emit_d8 ( cbuf, 0x03 ); 2739 // MOV AH,1 - treat as LT case (set carry flag) 2740 emit_opcode( cbuf, 0xB4 ); 2741 emit_d8 ( cbuf, 0x01 ); 2742 // SAHF 2743 emit_opcode( cbuf, 0x9E); 2744 // NOP // target for branch to avoid branch to branch 2745 emit_opcode( cbuf, 0x90); 2746 %} 2747 2748 // fnstsw_ax(); 2749 // sahf(); 2750 // movl(dst, nan_result); 2751 // jcc(Assembler::parity, exit); 2752 // movl(dst, less_result); 2753 // jcc(Assembler::below, exit); 2754 // movl(dst, equal_result); 2755 // jcc(Assembler::equal, exit); 2756 // movl(dst, greater_result); 2757 2758 // less_result = 1; 2759 // greater_result = -1; 2760 // equal_result = 0; 2761 // nan_result = -1; 2762 2763 enc_class CmpF_Result(eRegI dst) %{ 2764 // fnstsw_ax(); 2765 emit_opcode( cbuf, 0xDF); 2766 emit_opcode( cbuf, 0xE0); 2767 // sahf 2768 emit_opcode( cbuf, 0x9E); 2769 // movl(dst, nan_result); 2770 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2771 emit_d32( cbuf, -1 ); 2772 // jcc(Assembler::parity, exit); 2773 emit_opcode( cbuf, 0x7A ); 2774 emit_d8 ( cbuf, 0x13 ); 2775 // movl(dst, less_result); 2776 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2777 emit_d32( cbuf, -1 ); 2778 // jcc(Assembler::below, exit); 2779 emit_opcode( cbuf, 0x72 ); 2780 emit_d8 ( cbuf, 0x0C ); 2781 // movl(dst, equal_result); 2782 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2783 emit_d32( cbuf, 0 ); 2784 // jcc(Assembler::equal, exit); 2785 emit_opcode( cbuf, 0x74 ); 2786 emit_d8 ( cbuf, 0x05 ); 2787 // movl(dst, greater_result); 2788 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2789 emit_d32( cbuf, 1 ); 2790 %} 2791 2792 2793 // Compare the longs and set flags 2794 // BROKEN! Do Not use as-is 2795 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ 2796 // CMP $src1.hi,$src2.hi 2797 emit_opcode( cbuf, 0x3B ); 2798 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2799 // JNE,s done 2800 emit_opcode(cbuf,0x75); 2801 emit_d8(cbuf, 2 ); 2802 // CMP $src1.lo,$src2.lo 2803 emit_opcode( cbuf, 0x3B ); 2804 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2805 // done: 2806 %} 2807 2808 enc_class convert_int_long( regL dst, eRegI src ) %{ 2809 // mov $dst.lo,$src 2810 int dst_encoding = $dst$$reg; 2811 int src_encoding = $src$$reg; 2812 encode_Copy( cbuf, dst_encoding , src_encoding ); 2813 // mov $dst.hi,$src 2814 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); 2815 // sar $dst.hi,31 2816 emit_opcode( cbuf, 0xC1 ); 2817 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); 2818 emit_d8(cbuf, 0x1F ); 2819 %} 2820 2821 enc_class convert_long_double( eRegL src ) %{ 2822 // push $src.hi 2823 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2824 // push $src.lo 2825 emit_opcode(cbuf, 0x50+$src$$reg ); 2826 // fild 64-bits at [SP] 2827 emit_opcode(cbuf,0xdf); 2828 emit_d8(cbuf, 0x6C); 2829 emit_d8(cbuf, 0x24); 2830 emit_d8(cbuf, 0x00); 2831 // pop stack 2832 emit_opcode(cbuf, 0x83); // add SP, #8 2833 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2834 emit_d8(cbuf, 0x8); 2835 %} 2836 2837 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ 2838 // IMUL EDX:EAX,$src1 2839 emit_opcode( cbuf, 0xF7 ); 2840 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); 2841 // SAR EDX,$cnt-32 2842 int shift_count = ((int)$cnt$$constant) - 32; 2843 if (shift_count > 0) { 2844 emit_opcode(cbuf, 0xC1); 2845 emit_rm(cbuf, 0x3, 7, $dst$$reg ); 2846 emit_d8(cbuf, shift_count); 2847 } 2848 %} 2849 2850 // this version doesn't have add sp, 8 2851 enc_class convert_long_double2( eRegL src ) %{ 2852 // push $src.hi 2853 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2854 // push $src.lo 2855 emit_opcode(cbuf, 0x50+$src$$reg ); 2856 // fild 64-bits at [SP] 2857 emit_opcode(cbuf,0xdf); 2858 emit_d8(cbuf, 0x6C); 2859 emit_d8(cbuf, 0x24); 2860 emit_d8(cbuf, 0x00); 2861 %} 2862 2863 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ 2864 // Basic idea: long = (long)int * (long)int 2865 // IMUL EDX:EAX, src 2866 emit_opcode( cbuf, 0xF7 ); 2867 emit_rm( cbuf, 0x3, 0x5, $src$$reg); 2868 %} 2869 2870 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ 2871 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 2872 // MUL EDX:EAX, src 2873 emit_opcode( cbuf, 0xF7 ); 2874 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2875 %} 2876 2877 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ 2878 // Basic idea: lo(result) = lo(x_lo * y_lo) 2879 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2880 // MOV $tmp,$src.lo 2881 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2882 // IMUL $tmp,EDX 2883 emit_opcode( cbuf, 0x0F ); 2884 emit_opcode( cbuf, 0xAF ); 2885 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2886 // MOV EDX,$src.hi 2887 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); 2888 // IMUL EDX,EAX 2889 emit_opcode( cbuf, 0x0F ); 2890 emit_opcode( cbuf, 0xAF ); 2891 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2892 // ADD $tmp,EDX 2893 emit_opcode( cbuf, 0x03 ); 2894 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2895 // MUL EDX:EAX,$src.lo 2896 emit_opcode( cbuf, 0xF7 ); 2897 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); 2898 // ADD EDX,ESI 2899 emit_opcode( cbuf, 0x03 ); 2900 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 2901 %} 2902 2903 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ 2904 // Basic idea: lo(result) = lo(src * y_lo) 2905 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 2906 // IMUL $tmp,EDX,$src 2907 emit_opcode( cbuf, 0x6B ); 2908 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2909 emit_d8( cbuf, (int)$src$$constant ); 2910 // MOV EDX,$src 2911 emit_opcode(cbuf, 0xB8 + EDX_enc); 2912 emit_d32( cbuf, (int)$src$$constant ); 2913 // MUL EDX:EAX,EDX 2914 emit_opcode( cbuf, 0xF7 ); 2915 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); 2916 // ADD EDX,ESI 2917 emit_opcode( cbuf, 0x03 ); 2918 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); 2919 %} 2920 2921 enc_class long_div( eRegL src1, eRegL src2 ) %{ 2922 // PUSH src1.hi 2923 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 2924 // PUSH src1.lo 2925 emit_opcode(cbuf, 0x50+$src1$$reg ); 2926 // PUSH src2.hi 2927 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 2928 // PUSH src2.lo 2929 emit_opcode(cbuf, 0x50+$src2$$reg ); 2930 // CALL directly to the runtime 2931 cbuf.set_insts_mark(); 2932 emit_opcode(cbuf,0xE8); // Call into runtime 2933 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 2934 // Restore stack 2935 emit_opcode(cbuf, 0x83); // add SP, #framesize 2936 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2937 emit_d8(cbuf, 4*4); 2938 %} 2939 2940 enc_class long_mod( eRegL src1, eRegL src2 ) %{ 2941 // PUSH src1.hi 2942 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 2943 // PUSH src1.lo 2944 emit_opcode(cbuf, 0x50+$src1$$reg ); 2945 // PUSH src2.hi 2946 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 2947 // PUSH src2.lo 2948 emit_opcode(cbuf, 0x50+$src2$$reg ); 2949 // CALL directly to the runtime 2950 cbuf.set_insts_mark(); 2951 emit_opcode(cbuf,0xE8); // Call into runtime 2952 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 2953 // Restore stack 2954 emit_opcode(cbuf, 0x83); // add SP, #framesize 2955 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2956 emit_d8(cbuf, 4*4); 2957 %} 2958 2959 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ 2960 // MOV $tmp,$src.lo 2961 emit_opcode(cbuf, 0x8B); 2962 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2963 // OR $tmp,$src.hi 2964 emit_opcode(cbuf, 0x0B); 2965 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 2966 %} 2967 2968 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ 2969 // CMP $src1.lo,$src2.lo 2970 emit_opcode( cbuf, 0x3B ); 2971 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2972 // JNE,s skip 2973 emit_cc(cbuf, 0x70, 0x5); 2974 emit_d8(cbuf,2); 2975 // CMP $src1.hi,$src2.hi 2976 emit_opcode( cbuf, 0x3B ); 2977 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2978 %} 2979 2980 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ 2981 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 2982 emit_opcode( cbuf, 0x3B ); 2983 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2984 // MOV $tmp,$src1.hi 2985 emit_opcode( cbuf, 0x8B ); 2986 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); 2987 // SBB $tmp,$src2.hi\t! Compute flags for long compare 2988 emit_opcode( cbuf, 0x1B ); 2989 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 2990 %} 2991 2992 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ 2993 // XOR $tmp,$tmp 2994 emit_opcode(cbuf,0x33); // XOR 2995 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 2996 // CMP $tmp,$src.lo 2997 emit_opcode( cbuf, 0x3B ); 2998 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); 2999 // SBB $tmp,$src.hi 3000 emit_opcode( cbuf, 0x1B ); 3001 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); 3002 %} 3003 3004 // Sniff, sniff... smells like Gnu Superoptimizer 3005 enc_class neg_long( eRegL dst ) %{ 3006 emit_opcode(cbuf,0xF7); // NEG hi 3007 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3008 emit_opcode(cbuf,0xF7); // NEG lo 3009 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); 3010 emit_opcode(cbuf,0x83); // SBB hi,0 3011 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3012 emit_d8 (cbuf,0 ); 3013 %} 3014 3015 3016 // Because the transitions from emitted code to the runtime 3017 // monitorenter/exit helper stubs are so slow it's critical that 3018 // we inline both the stack-locking fast-path and the inflated fast path. 3019 // 3020 // See also: cmpFastLock and cmpFastUnlock. 3021 // 3022 // What follows is a specialized inline transliteration of the code 3023 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 3024 // another option would be to emit TrySlowEnter and TrySlowExit methods 3025 // at startup-time. These methods would accept arguments as 3026 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 3027 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 3028 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 3029 // In practice, however, the # of lock sites is bounded and is usually small. 3030 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 3031 // if the processor uses simple bimodal branch predictors keyed by EIP 3032 // Since the helper routines would be called from multiple synchronization 3033 // sites. 3034 // 3035 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 3036 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 3037 // to those specialized methods. That'd give us a mostly platform-independent 3038 // implementation that the JITs could optimize and inline at their pleasure. 3039 // Done correctly, the only time we'd need to cross to native could would be 3040 // to park() or unpark() threads. We'd also need a few more unsafe operators 3041 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 3042 // (b) explicit barriers or fence operations. 3043 // 3044 // TODO: 3045 // 3046 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 3047 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 3048 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 3049 // the lock operators would typically be faster than reifying Self. 3050 // 3051 // * Ideally I'd define the primitives as: 3052 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 3053 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 3054 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 3055 // Instead, we're stuck with a rather awkward and brittle register assignments below. 3056 // Furthermore the register assignments are overconstrained, possibly resulting in 3057 // sub-optimal code near the synchronization site. 3058 // 3059 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 3060 // Alternately, use a better sp-proximity test. 3061 // 3062 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 3063 // Either one is sufficient to uniquely identify a thread. 3064 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 3065 // 3066 // * Intrinsify notify() and notifyAll() for the common cases where the 3067 // object is locked by the calling thread but the waitlist is empty. 3068 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 3069 // 3070 // * use jccb and jmpb instead of jcc and jmp to improve code density. 3071 // But beware of excessive branch density on AMD Opterons. 3072 // 3073 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 3074 // or failure of the fast-path. If the fast-path fails then we pass 3075 // control to the slow-path, typically in C. In Fast_Lock and 3076 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 3077 // will emit a conditional branch immediately after the node. 3078 // So we have branches to branches and lots of ICC.ZF games. 3079 // Instead, it might be better to have C2 pass a "FailureLabel" 3080 // into Fast_Lock and Fast_Unlock. In the case of success, control 3081 // will drop through the node. ICC.ZF is undefined at exit. 3082 // In the case of failure, the node will branch directly to the 3083 // FailureLabel 3084 3085 3086 // obj: object to lock 3087 // box: on-stack box address (displaced header location) - KILLED 3088 // rax,: tmp -- KILLED 3089 // scr: tmp -- KILLED 3090 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ 3091 3092 Register objReg = as_Register($obj$$reg); 3093 Register boxReg = as_Register($box$$reg); 3094 Register tmpReg = as_Register($tmp$$reg); 3095 Register scrReg = as_Register($scr$$reg); 3096 3097 // Ensure the register assignents are disjoint 3098 guarantee (objReg != boxReg, "") ; 3099 guarantee (objReg != tmpReg, "") ; 3100 guarantee (objReg != scrReg, "") ; 3101 guarantee (boxReg != tmpReg, "") ; 3102 guarantee (boxReg != scrReg, "") ; 3103 guarantee (tmpReg == as_Register(EAX_enc), "") ; 3104 3105 MacroAssembler masm(&cbuf); 3106 3107 if (_counters != NULL) { 3108 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); 3109 } 3110 if (EmitSync & 1) { 3111 // set box->dhw = unused_mark (3) 3112 // Force all sync thru slow-path: slow_enter() and slow_exit() 3113 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; 3114 masm.cmpptr (rsp, (int32_t)0) ; 3115 } else 3116 if (EmitSync & 2) { 3117 Label DONE_LABEL ; 3118 if (UseBiasedLocking) { 3119 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. 3120 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3121 } 3122 3123 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword 3124 masm.orptr (tmpReg, 0x1); 3125 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3126 if (os::is_MP()) { masm.lock(); } 3127 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3128 masm.jcc(Assembler::equal, DONE_LABEL); 3129 // Recursive locking 3130 masm.subptr(tmpReg, rsp); 3131 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); 3132 masm.movptr(Address(boxReg, 0), tmpReg); 3133 masm.bind(DONE_LABEL) ; 3134 } else { 3135 // Possible cases that we'll encounter in fast_lock 3136 // ------------------------------------------------ 3137 // * Inflated 3138 // -- unlocked 3139 // -- Locked 3140 // = by self 3141 // = by other 3142 // * biased 3143 // -- by Self 3144 // -- by other 3145 // * neutral 3146 // * stack-locked 3147 // -- by self 3148 // = sp-proximity test hits 3149 // = sp-proximity test generates false-negative 3150 // -- by other 3151 // 3152 3153 Label IsInflated, DONE_LABEL, PopDone ; 3154 3155 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 3156 // order to reduce the number of conditional branches in the most common cases. 3157 // Beware -- there's a subtle invariant that fetch of the markword 3158 // at [FETCH], below, will never observe a biased encoding (*101b). 3159 // If this invariant is not held we risk exclusion (safety) failure. 3160 if (UseBiasedLocking && !UseOptoBiasInlining) { 3161 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3162 } 3163 3164 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] 3165 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) 3166 masm.jccb (Assembler::notZero, IsInflated) ; 3167 3168 // Attempt stack-locking ... 3169 masm.orptr (tmpReg, 0x1); 3170 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3171 if (os::is_MP()) { masm.lock(); } 3172 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3173 if (_counters != NULL) { 3174 masm.cond_inc32(Assembler::equal, 3175 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3176 } 3177 masm.jccb (Assembler::equal, DONE_LABEL); 3178 3179 // Recursive locking 3180 masm.subptr(tmpReg, rsp); 3181 masm.andptr(tmpReg, 0xFFFFF003 ); 3182 masm.movptr(Address(boxReg, 0), tmpReg); 3183 if (_counters != NULL) { 3184 masm.cond_inc32(Assembler::equal, 3185 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3186 } 3187 masm.jmp (DONE_LABEL) ; 3188 3189 masm.bind (IsInflated) ; 3190 3191 // The object is inflated. 3192 // 3193 // TODO-FIXME: eliminate the ugly use of manifest constants: 3194 // Use markOopDesc::monitor_value instead of "2". 3195 // use markOop::unused_mark() instead of "3". 3196 // The tmpReg value is an objectMonitor reference ORed with 3197 // markOopDesc::monitor_value (2). We can either convert tmpReg to an 3198 // objectmonitor pointer by masking off the "2" bit or we can just 3199 // use tmpReg as an objectmonitor pointer but bias the objectmonitor 3200 // field offsets with "-2" to compensate for and annul the low-order tag bit. 3201 // 3202 // I use the latter as it avoids AGI stalls. 3203 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" 3204 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". 3205 // 3206 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) 3207 3208 // boxReg refers to the on-stack BasicLock in the current frame. 3209 // We'd like to write: 3210 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. 3211 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 3212 // additional latency as we have another ST in the store buffer that must drain. 3213 3214 if (EmitSync & 8192) { 3215 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3216 masm.get_thread (scrReg) ; 3217 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3218 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov 3219 if (os::is_MP()) { masm.lock(); } 3220 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3221 } else 3222 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3223 masm.movptr(scrReg, boxReg) ; 3224 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3225 3226 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3227 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3228 // prefetchw [eax + Offset(_owner)-2] 3229 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3230 } 3231 3232 if ((EmitSync & 64) == 0) { 3233 // Optimistic form: consider XORL tmpReg,tmpReg 3234 masm.movptr(tmpReg, NULL_WORD) ; 3235 } else { 3236 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3237 // Test-And-CAS instead of CAS 3238 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3239 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3240 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3241 } 3242 3243 // Appears unlocked - try to swing _owner from null to non-null. 3244 // Ideally, I'd manifest "Self" with get_thread and then attempt 3245 // to CAS the register containing Self into m->Owner. 3246 // But we don't have enough registers, so instead we can either try to CAS 3247 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 3248 // we later store "Self" into m->Owner. Transiently storing a stack address 3249 // (rsp or the address of the box) into m->owner is harmless. 3250 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3251 if (os::is_MP()) { masm.lock(); } 3252 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3253 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 3254 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3255 masm.get_thread (scrReg) ; // beware: clobbers ICCs 3256 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 3257 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success 3258 3259 // If the CAS fails we can either retry or pass control to the slow-path. 3260 // We use the latter tactic. 3261 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3262 // If the CAS was successful ... 3263 // Self has acquired the lock 3264 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3265 // Intentional fall-through into DONE_LABEL ... 3266 } else { 3267 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3268 masm.movptr(boxReg, tmpReg) ; 3269 3270 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3271 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3272 // prefetchw [eax + Offset(_owner)-2] 3273 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3274 } 3275 3276 if ((EmitSync & 64) == 0) { 3277 // Optimistic form 3278 masm.xorptr (tmpReg, tmpReg) ; 3279 } else { 3280 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3281 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3282 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3283 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3284 } 3285 3286 // Appears unlocked - try to swing _owner from null to non-null. 3287 // Use either "Self" (in scr) or rsp as thread identity in _owner. 3288 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3289 masm.get_thread (scrReg) ; 3290 if (os::is_MP()) { masm.lock(); } 3291 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3292 3293 // If the CAS fails we can either retry or pass control to the slow-path. 3294 // We use the latter tactic. 3295 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3296 // If the CAS was successful ... 3297 // Self has acquired the lock 3298 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3299 // Intentional fall-through into DONE_LABEL ... 3300 } 3301 3302 // DONE_LABEL is a hot target - we'd really like to place it at the 3303 // start of cache line by padding with NOPs. 3304 // See the AMD and Intel software optimization manuals for the 3305 // most efficient "long" NOP encodings. 3306 // Unfortunately none of our alignment mechanisms suffice. 3307 masm.bind(DONE_LABEL); 3308 3309 // Avoid branch-to-branch on AMD processors 3310 // This appears to be superstition. 3311 if (EmitSync & 32) masm.nop() ; 3312 3313 3314 // At DONE_LABEL the icc ZFlag is set as follows ... 3315 // Fast_Unlock uses the same protocol. 3316 // ZFlag == 1 -> Success 3317 // ZFlag == 0 -> Failure - force control through the slow-path 3318 } 3319 %} 3320 3321 // obj: object to unlock 3322 // box: box address (displaced header location), killed. Must be EAX. 3323 // rbx,: killed tmp; cannot be obj nor box. 3324 // 3325 // Some commentary on balanced locking: 3326 // 3327 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 3328 // Methods that don't have provably balanced locking are forced to run in the 3329 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 3330 // The interpreter provides two properties: 3331 // I1: At return-time the interpreter automatically and quietly unlocks any 3332 // objects acquired the current activation (frame). Recall that the 3333 // interpreter maintains an on-stack list of locks currently held by 3334 // a frame. 3335 // I2: If a method attempts to unlock an object that is not held by the 3336 // the frame the interpreter throws IMSX. 3337 // 3338 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 3339 // B() doesn't have provably balanced locking so it runs in the interpreter. 3340 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 3341 // is still locked by A(). 3342 // 3343 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 3344 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 3345 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 3346 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 3347 3348 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ 3349 3350 Register objReg = as_Register($obj$$reg); 3351 Register boxReg = as_Register($box$$reg); 3352 Register tmpReg = as_Register($tmp$$reg); 3353 3354 guarantee (objReg != boxReg, "") ; 3355 guarantee (objReg != tmpReg, "") ; 3356 guarantee (boxReg != tmpReg, "") ; 3357 guarantee (boxReg == as_Register(EAX_enc), "") ; 3358 MacroAssembler masm(&cbuf); 3359 3360 if (EmitSync & 4) { 3361 // Disable - inhibit all inlining. Force control through the slow-path 3362 masm.cmpptr (rsp, 0) ; 3363 } else 3364 if (EmitSync & 8) { 3365 Label DONE_LABEL ; 3366 if (UseBiasedLocking) { 3367 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3368 } 3369 // classic stack-locking code ... 3370 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3371 masm.testptr(tmpReg, tmpReg) ; 3372 masm.jcc (Assembler::zero, DONE_LABEL) ; 3373 if (os::is_MP()) { masm.lock(); } 3374 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3375 masm.bind(DONE_LABEL); 3376 } else { 3377 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; 3378 3379 // Critically, the biased locking test must have precedence over 3380 // and appear before the (box->dhw == 0) recursive stack-lock test. 3381 if (UseBiasedLocking && !UseOptoBiasInlining) { 3382 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3383 } 3384 3385 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header 3386 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword 3387 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock 3388 3389 masm.testptr(tmpReg, 0x02) ; // Inflated? 3390 masm.jccb (Assembler::zero, Stacked) ; 3391 3392 masm.bind (Inflated) ; 3393 // It's inflated. 3394 // Despite our balanced locking property we still check that m->_owner == Self 3395 // as java routines or native JNI code called by this thread might 3396 // have released the lock. 3397 // Refer to the comments in synchronizer.cpp for how we might encode extra 3398 // state in _succ so we can avoid fetching EntryList|cxq. 3399 // 3400 // I'd like to add more cases in fast_lock() and fast_unlock() -- 3401 // such as recursive enter and exit -- but we have to be wary of 3402 // I$ bloat, T$ effects and BP$ effects. 3403 // 3404 // If there's no contention try a 1-0 exit. That is, exit without 3405 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 3406 // we detect and recover from the race that the 1-0 exit admits. 3407 // 3408 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 3409 // before it STs null into _owner, releasing the lock. Updates 3410 // to data protected by the critical section must be visible before 3411 // we drop the lock (and thus before any other thread could acquire 3412 // the lock and observe the fields protected by the lock). 3413 // IA32's memory-model is SPO, so STs are ordered with respect to 3414 // each other and there's no need for an explicit barrier (fence). 3415 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3416 3417 masm.get_thread (boxReg) ; 3418 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3419 // prefetchw [ebx + Offset(_owner)-2] 3420 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); 3421 } 3422 3423 // Note that we could employ various encoding schemes to reduce 3424 // the number of loads below (currently 4) to just 2 or 3. 3425 // Refer to the comments in synchronizer.cpp. 3426 // In practice the chain of fetches doesn't seem to impact performance, however. 3427 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 3428 // Attempt to reduce branch density - AMD's branch predictor. 3429 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3430 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3431 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3432 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3433 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3434 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3435 masm.jmpb (DONE_LABEL) ; 3436 } else { 3437 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3438 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3439 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3440 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3441 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3442 masm.jccb (Assembler::notZero, CheckSucc) ; 3443 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3444 masm.jmpb (DONE_LABEL) ; 3445 } 3446 3447 // The Following code fragment (EmitSync & 65536) improves the performance of 3448 // contended applications and contended synchronization microbenchmarks. 3449 // Unfortunately the emission of the code - even though not executed - causes regressions 3450 // in scimark and jetstream, evidently because of $ effects. Replacing the code 3451 // with an equal number of never-executed NOPs results in the same regression. 3452 // We leave it off by default. 3453 3454 if ((EmitSync & 65536) != 0) { 3455 Label LSuccess, LGoSlowPath ; 3456 3457 masm.bind (CheckSucc) ; 3458 3459 // Optional pre-test ... it's safe to elide this 3460 if ((EmitSync & 16) == 0) { 3461 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3462 masm.jccb (Assembler::zero, LGoSlowPath) ; 3463 } 3464 3465 // We have a classic Dekker-style idiom: 3466 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 3467 // There are a number of ways to implement the barrier: 3468 // (1) lock:andl &m->_owner, 0 3469 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 3470 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 3471 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 3472 // (2) If supported, an explicit MFENCE is appealing. 3473 // In older IA32 processors MFENCE is slower than lock:add or xchg 3474 // particularly if the write-buffer is full as might be the case if 3475 // if stores closely precede the fence or fence-equivalent instruction. 3476 // In more modern implementations MFENCE appears faster, however. 3477 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 3478 // The $lines underlying the top-of-stack should be in M-state. 3479 // The locked add instruction is serializing, of course. 3480 // (4) Use xchg, which is serializing 3481 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 3482 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 3483 // The integer condition codes will tell us if succ was 0. 3484 // Since _succ and _owner should reside in the same $line and 3485 // we just stored into _owner, it's likely that the $line 3486 // remains in M-state for the lock:orl. 3487 // 3488 // We currently use (3), although it's likely that switching to (2) 3489 // is correct for the future. 3490 3491 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3492 if (os::is_MP()) { 3493 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 3494 masm.mfence(); 3495 } else { 3496 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 3497 } 3498 } 3499 // Ratify _succ remains non-null 3500 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3501 masm.jccb (Assembler::notZero, LSuccess) ; 3502 3503 masm.xorptr(boxReg, boxReg) ; // box is really EAX 3504 if (os::is_MP()) { masm.lock(); } 3505 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); 3506 masm.jccb (Assembler::notEqual, LSuccess) ; 3507 // Since we're low on registers we installed rsp as a placeholding in _owner. 3508 // Now install Self over rsp. This is safe as we're transitioning from 3509 // non-null to non=null 3510 masm.get_thread (boxReg) ; 3511 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; 3512 // Intentional fall-through into LGoSlowPath ... 3513 3514 masm.bind (LGoSlowPath) ; 3515 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure 3516 masm.jmpb (DONE_LABEL) ; 3517 3518 masm.bind (LSuccess) ; 3519 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success 3520 masm.jmpb (DONE_LABEL) ; 3521 } 3522 3523 masm.bind (Stacked) ; 3524 // It's not inflated and it's not recursively stack-locked and it's not biased. 3525 // It must be stack-locked. 3526 // Try to reset the header to displaced header. 3527 // The "box" value on the stack is stable, so we can reload 3528 // and be assured we observe the same value as above. 3529 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3530 if (os::is_MP()) { masm.lock(); } 3531 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3532 // Intention fall-thru into DONE_LABEL 3533 3534 3535 // DONE_LABEL is a hot target - we'd really like to place it at the 3536 // start of cache line by padding with NOPs. 3537 // See the AMD and Intel software optimization manuals for the 3538 // most efficient "long" NOP encodings. 3539 // Unfortunately none of our alignment mechanisms suffice. 3540 if ((EmitSync & 65536) == 0) { 3541 masm.bind (CheckSucc) ; 3542 } 3543 masm.bind(DONE_LABEL); 3544 3545 // Avoid branch to branch on AMD processors 3546 if (EmitSync & 32768) { masm.nop() ; } 3547 } 3548 %} 3549 3550 3551 enc_class enc_pop_rdx() %{ 3552 emit_opcode(cbuf,0x5A); 3553 %} 3554 3555 enc_class enc_rethrow() %{ 3556 cbuf.set_insts_mark(); 3557 emit_opcode(cbuf, 0xE9); // jmp entry 3558 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, 3559 runtime_call_Relocation::spec(), RELOC_IMM32 ); 3560 %} 3561 3562 3563 // Convert a double to an int. Java semantics require we do complex 3564 // manglelations in the corner cases. So we set the rounding mode to 3565 // 'zero', store the darned double down as an int, and reset the 3566 // rounding mode to 'nearest'. The hardware throws an exception which 3567 // patches up the correct value directly to the stack. 3568 enc_class DPR2I_encoding( regDPR src ) %{ 3569 // Flip to round-to-zero mode. We attempted to allow invalid-op 3570 // exceptions here, so that a NAN or other corner-case value will 3571 // thrown an exception (but normal values get converted at full speed). 3572 // However, I2C adapters and other float-stack manglers leave pending 3573 // invalid-op exceptions hanging. We would have to clear them before 3574 // enabling them and that is more expensive than just testing for the 3575 // invalid value Intel stores down in the corner cases. 3576 emit_opcode(cbuf,0xD9); // FLDCW trunc 3577 emit_opcode(cbuf,0x2D); 3578 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3579 // Allocate a word 3580 emit_opcode(cbuf,0x83); // SUB ESP,4 3581 emit_opcode(cbuf,0xEC); 3582 emit_d8(cbuf,0x04); 3583 // Encoding assumes a double has been pushed into FPR0. 3584 // Store down the double as an int, popping the FPU stack 3585 emit_opcode(cbuf,0xDB); // FISTP [ESP] 3586 emit_opcode(cbuf,0x1C); 3587 emit_d8(cbuf,0x24); 3588 // Restore the rounding mode; mask the exception 3589 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3590 emit_opcode(cbuf,0x2D); 3591 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3592 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3593 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3594 3595 // Load the converted int; adjust CPU stack 3596 emit_opcode(cbuf,0x58); // POP EAX 3597 emit_opcode(cbuf,0x3D); // CMP EAX,imm 3598 emit_d32 (cbuf,0x80000000); // 0x80000000 3599 emit_opcode(cbuf,0x75); // JNE around_slow_call 3600 emit_d8 (cbuf,0x07); // Size of slow_call 3601 // Push src onto stack slow-path 3602 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3603 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3604 // CALL directly to the runtime 3605 cbuf.set_insts_mark(); 3606 emit_opcode(cbuf,0xE8); // Call into runtime 3607 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3608 // Carry on here... 3609 %} 3610 3611 enc_class DPR2L_encoding( regDPR src ) %{ 3612 emit_opcode(cbuf,0xD9); // FLDCW trunc 3613 emit_opcode(cbuf,0x2D); 3614 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3615 // Allocate a word 3616 emit_opcode(cbuf,0x83); // SUB ESP,8 3617 emit_opcode(cbuf,0xEC); 3618 emit_d8(cbuf,0x08); 3619 // Encoding assumes a double has been pushed into FPR0. 3620 // Store down the double as a long, popping the FPU stack 3621 emit_opcode(cbuf,0xDF); // FISTP [ESP] 3622 emit_opcode(cbuf,0x3C); 3623 emit_d8(cbuf,0x24); 3624 // Restore the rounding mode; mask the exception 3625 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3626 emit_opcode(cbuf,0x2D); 3627 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3628 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3629 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3630 3631 // Load the converted int; adjust CPU stack 3632 emit_opcode(cbuf,0x58); // POP EAX 3633 emit_opcode(cbuf,0x5A); // POP EDX 3634 emit_opcode(cbuf,0x81); // CMP EDX,imm 3635 emit_d8 (cbuf,0xFA); // rdx 3636 emit_d32 (cbuf,0x80000000); // 0x80000000 3637 emit_opcode(cbuf,0x75); // JNE around_slow_call 3638 emit_d8 (cbuf,0x07+4); // Size of slow_call 3639 emit_opcode(cbuf,0x85); // TEST EAX,EAX 3640 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 3641 emit_opcode(cbuf,0x75); // JNE around_slow_call 3642 emit_d8 (cbuf,0x07); // Size of slow_call 3643 // Push src onto stack slow-path 3644 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3645 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3646 // CALL directly to the runtime 3647 cbuf.set_insts_mark(); 3648 emit_opcode(cbuf,0xE8); // Call into runtime 3649 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3650 // Carry on here... 3651 %} 3652 3653 enc_class FMul_ST_reg( eRegFPR src1 ) %{ 3654 // Operand was loaded from memory into fp ST (stack top) 3655 // FMUL ST,$src /* D8 C8+i */ 3656 emit_opcode(cbuf, 0xD8); 3657 emit_opcode(cbuf, 0xC8 + $src1$$reg); 3658 %} 3659 3660 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ 3661 // FADDP ST,src2 /* D8 C0+i */ 3662 emit_opcode(cbuf, 0xD8); 3663 emit_opcode(cbuf, 0xC0 + $src2$$reg); 3664 //could use FADDP src2,fpST /* DE C0+i */ 3665 %} 3666 3667 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ 3668 // FADDP src2,ST /* DE C0+i */ 3669 emit_opcode(cbuf, 0xDE); 3670 emit_opcode(cbuf, 0xC0 + $src2$$reg); 3671 %} 3672 3673 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ 3674 // Operand has been loaded into fp ST (stack top) 3675 // FSUB ST,$src1 3676 emit_opcode(cbuf, 0xD8); 3677 emit_opcode(cbuf, 0xE0 + $src1$$reg); 3678 3679 // FDIV 3680 emit_opcode(cbuf, 0xD8); 3681 emit_opcode(cbuf, 0xF0 + $src2$$reg); 3682 %} 3683 3684 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ 3685 // Operand was loaded from memory into fp ST (stack top) 3686 // FADD ST,$src /* D8 C0+i */ 3687 emit_opcode(cbuf, 0xD8); 3688 emit_opcode(cbuf, 0xC0 + $src1$$reg); 3689 3690 // FMUL ST,src2 /* D8 C*+i */ 3691 emit_opcode(cbuf, 0xD8); 3692 emit_opcode(cbuf, 0xC8 + $src2$$reg); 3693 %} 3694 3695 3696 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ 3697 // Operand was loaded from memory into fp ST (stack top) 3698 // FADD ST,$src /* D8 C0+i */ 3699 emit_opcode(cbuf, 0xD8); 3700 emit_opcode(cbuf, 0xC0 + $src1$$reg); 3701 3702 // FMULP src2,ST /* DE C8+i */ 3703 emit_opcode(cbuf, 0xDE); 3704 emit_opcode(cbuf, 0xC8 + $src2$$reg); 3705 %} 3706 3707 // Atomically load the volatile long 3708 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ 3709 emit_opcode(cbuf,0xDF); 3710 int rm_byte_opcode = 0x05; 3711 int base = $mem$$base; 3712 int index = $mem$$index; 3713 int scale = $mem$$scale; 3714 int displace = $mem$$disp; 3715 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 3716 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 3717 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 3718 %} 3719 3720 // Volatile Store Long. Must be atomic, so move it into 3721 // the FP TOS and then do a 64-bit FIST. Has to probe the 3722 // target address before the store (for null-ptr checks) 3723 // so the memory operand is used twice in the encoding. 3724 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ 3725 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); 3726 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop 3727 emit_opcode(cbuf,0xDF); 3728 int rm_byte_opcode = 0x07; 3729 int base = $mem$$base; 3730 int index = $mem$$index; 3731 int scale = $mem$$scale; 3732 int displace = $mem$$disp; 3733 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 3734 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 3735 %} 3736 3737 // Safepoint Poll. This polls the safepoint page, and causes an 3738 // exception if it is not readable. Unfortunately, it kills the condition code 3739 // in the process 3740 // We current use TESTL [spp],EDI 3741 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 3742 3743 enc_class Safepoint_Poll() %{ 3744 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); 3745 emit_opcode(cbuf,0x85); 3746 emit_rm (cbuf, 0x0, 0x7, 0x5); 3747 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 3748 %} 3749 %} 3750 3751 3752 //----------FRAME-------------------------------------------------------------- 3753 // Definition of frame structure and management information. 3754 // 3755 // S T A C K L A Y O U T Allocators stack-slot number 3756 // | (to get allocators register number 3757 // G Owned by | | v add OptoReg::stack0()) 3758 // r CALLER | | 3759 // o | +--------+ pad to even-align allocators stack-slot 3760 // w V | pad0 | numbers; owned by CALLER 3761 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3762 // h ^ | in | 5 3763 // | | args | 4 Holes in incoming args owned by SELF 3764 // | | | | 3 3765 // | | +--------+ 3766 // V | | old out| Empty on Intel, window on Sparc 3767 // | old |preserve| Must be even aligned. 3768 // | SP-+--------+----> Matcher::_old_SP, even aligned 3769 // | | in | 3 area for Intel ret address 3770 // Owned by |preserve| Empty on Sparc. 3771 // SELF +--------+ 3772 // | | pad2 | 2 pad to align old SP 3773 // | +--------+ 1 3774 // | | locks | 0 3775 // | +--------+----> OptoReg::stack0(), even aligned 3776 // | | pad1 | 11 pad to align new SP 3777 // | +--------+ 3778 // | | | 10 3779 // | | spills | 9 spills 3780 // V | | 8 (pad0 slot for callee) 3781 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3782 // ^ | out | 7 3783 // | | args | 6 Holes in outgoing args owned by CALLEE 3784 // Owned by +--------+ 3785 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3786 // | new |preserve| Must be even-aligned. 3787 // | SP-+--------+----> Matcher::_new_SP, even aligned 3788 // | | | 3789 // 3790 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3791 // known from SELF's arguments and the Java calling convention. 3792 // Region 6-7 is determined per call site. 3793 // Note 2: If the calling convention leaves holes in the incoming argument 3794 // area, those holes are owned by SELF. Holes in the outgoing area 3795 // are owned by the CALLEE. Holes should not be nessecary in the 3796 // incoming area, as the Java calling convention is completely under 3797 // the control of the AD file. Doubles can be sorted and packed to 3798 // avoid holes. Holes in the outgoing arguments may be nessecary for 3799 // varargs C calling conventions. 3800 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3801 // even aligned with pad0 as needed. 3802 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3803 // region 6-11 is even aligned; it may be padded out more so that 3804 // the region from SP to FP meets the minimum stack alignment. 3805 3806 frame %{ 3807 // What direction does stack grow in (assumed to be same for C & Java) 3808 stack_direction(TOWARDS_LOW); 3809 3810 // These three registers define part of the calling convention 3811 // between compiled code and the interpreter. 3812 inline_cache_reg(EAX); // Inline Cache Register 3813 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter 3814 3815 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3816 cisc_spilling_operand_name(indOffset32); 3817 3818 // Number of stack slots consumed by locking an object 3819 sync_stack_slots(1); 3820 3821 // Compiled code's Frame Pointer 3822 frame_pointer(ESP); 3823 // Interpreter stores its frame pointer in a register which is 3824 // stored to the stack by I2CAdaptors. 3825 // I2CAdaptors convert from interpreted java to compiled java. 3826 interpreter_frame_pointer(EBP); 3827 3828 // Stack alignment requirement 3829 // Alignment size in bytes (128-bit -> 16 bytes) 3830 stack_alignment(StackAlignmentInBytes); 3831 3832 // Number of stack slots between incoming argument block and the start of 3833 // a new frame. The PROLOG must add this many slots to the stack. The 3834 // EPILOG must remove this many slots. Intel needs one slot for 3835 // return address and one for rbp, (must save rbp) 3836 in_preserve_stack_slots(2+VerifyStackAtCalls); 3837 3838 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3839 // for calls to C. Supports the var-args backing area for register parms. 3840 varargs_C_out_slots_killed(0); 3841 3842 // The after-PROLOG location of the return address. Location of 3843 // return address specifies a type (REG or STACK) and a number 3844 // representing the register number (i.e. - use a register name) or 3845 // stack slot. 3846 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 3847 // Otherwise, it is above the locks and verification slot and alignment word 3848 return_addr(STACK - 1 + 3849 round_to(1+VerifyStackAtCalls+ 3850 Compile::current()->fixed_slots(), 3851 (StackAlignmentInBytes/wordSize))); 3852 3853 // Body of function which returns an integer array locating 3854 // arguments either in registers or in stack slots. Passed an array 3855 // of ideal registers called "sig" and a "length" count. Stack-slot 3856 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3857 // arguments for a CALLEE. Incoming stack arguments are 3858 // automatically biased by the preserve_stack_slots field above. 3859 calling_convention %{ 3860 // No difference between ingoing/outgoing just pass false 3861 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3862 %} 3863 3864 3865 // Body of function which returns an integer array locating 3866 // arguments either in registers or in stack slots. Passed an array 3867 // of ideal registers called "sig" and a "length" count. Stack-slot 3868 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3869 // arguments for a CALLEE. Incoming stack arguments are 3870 // automatically biased by the preserve_stack_slots field above. 3871 c_calling_convention %{ 3872 // This is obviously always outgoing 3873 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3874 %} 3875 3876 // Location of C & interpreter return values 3877 c_return_value %{ 3878 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3879 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 3880 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3881 3882 // in SSE2+ mode we want to keep the FPU stack clean so pretend 3883 // that C functions return float and double results in XMM0. 3884 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3885 return OptoRegPair(XMM0b_num,XMM0a_num); 3886 if( ideal_reg == Op_RegF && UseSSE>=2 ) 3887 return OptoRegPair(OptoReg::Bad,XMM0a_num); 3888 3889 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3890 %} 3891 3892 // Location of return values 3893 return_value %{ 3894 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3895 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 3896 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3897 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3898 return OptoRegPair(XMM0b_num,XMM0a_num); 3899 if( ideal_reg == Op_RegF && UseSSE>=1 ) 3900 return OptoRegPair(OptoReg::Bad,XMM0a_num); 3901 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3902 %} 3903 3904 %} 3905 3906 //----------ATTRIBUTES--------------------------------------------------------- 3907 //----------Operand Attributes------------------------------------------------- 3908 op_attrib op_cost(0); // Required cost attribute 3909 3910 //----------Instruction Attributes--------------------------------------------- 3911 ins_attrib ins_cost(100); // Required cost attribute 3912 ins_attrib ins_size(8); // Required size attribute (in bits) 3913 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3914 // non-matching short branch variant of some 3915 // long branch? 3916 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) 3917 // specifies the alignment that some part of the instruction (not 3918 // necessarily the start) requires. If > 1, a compute_padding() 3919 // function must be provided for the instruction 3920 3921 //----------OPERANDS----------------------------------------------------------- 3922 // Operand definitions must precede instruction definitions for correct parsing 3923 // in the ADLC because operands constitute user defined types which are used in 3924 // instruction definitions. 3925 3926 //----------Simple Operands---------------------------------------------------- 3927 // Immediate Operands 3928 // Integer Immediate 3929 operand immI() %{ 3930 match(ConI); 3931 3932 op_cost(10); 3933 format %{ %} 3934 interface(CONST_INTER); 3935 %} 3936 3937 // Constant for test vs zero 3938 operand immI0() %{ 3939 predicate(n->get_int() == 0); 3940 match(ConI); 3941 3942 op_cost(0); 3943 format %{ %} 3944 interface(CONST_INTER); 3945 %} 3946 3947 // Constant for increment 3948 operand immI1() %{ 3949 predicate(n->get_int() == 1); 3950 match(ConI); 3951 3952 op_cost(0); 3953 format %{ %} 3954 interface(CONST_INTER); 3955 %} 3956 3957 // Constant for decrement 3958 operand immI_M1() %{ 3959 predicate(n->get_int() == -1); 3960 match(ConI); 3961 3962 op_cost(0); 3963 format %{ %} 3964 interface(CONST_INTER); 3965 %} 3966 3967 // Valid scale values for addressing modes 3968 operand immI2() %{ 3969 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 3970 match(ConI); 3971 3972 format %{ %} 3973 interface(CONST_INTER); 3974 %} 3975 3976 operand immI8() %{ 3977 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); 3978 match(ConI); 3979 3980 op_cost(5); 3981 format %{ %} 3982 interface(CONST_INTER); 3983 %} 3984 3985 operand immI16() %{ 3986 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 3987 match(ConI); 3988 3989 op_cost(10); 3990 format %{ %} 3991 interface(CONST_INTER); 3992 %} 3993 3994 // Constant for long shifts 3995 operand immI_32() %{ 3996 predicate( n->get_int() == 32 ); 3997 match(ConI); 3998 3999 op_cost(0); 4000 format %{ %} 4001 interface(CONST_INTER); 4002 %} 4003 4004 operand immI_1_31() %{ 4005 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 4006 match(ConI); 4007 4008 op_cost(0); 4009 format %{ %} 4010 interface(CONST_INTER); 4011 %} 4012 4013 operand immI_32_63() %{ 4014 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); 4015 match(ConI); 4016 op_cost(0); 4017 4018 format %{ %} 4019 interface(CONST_INTER); 4020 %} 4021 4022 operand immI_1() %{ 4023 predicate( n->get_int() == 1 ); 4024 match(ConI); 4025 4026 op_cost(0); 4027 format %{ %} 4028 interface(CONST_INTER); 4029 %} 4030 4031 operand immI_2() %{ 4032 predicate( n->get_int() == 2 ); 4033 match(ConI); 4034 4035 op_cost(0); 4036 format %{ %} 4037 interface(CONST_INTER); 4038 %} 4039 4040 operand immI_3() %{ 4041 predicate( n->get_int() == 3 ); 4042 match(ConI); 4043 4044 op_cost(0); 4045 format %{ %} 4046 interface(CONST_INTER); 4047 %} 4048 4049 // Pointer Immediate 4050 operand immP() %{ 4051 match(ConP); 4052 4053 op_cost(10); 4054 format %{ %} 4055 interface(CONST_INTER); 4056 %} 4057 4058 // NULL Pointer Immediate 4059 operand immP0() %{ 4060 predicate( n->get_ptr() == 0 ); 4061 match(ConP); 4062 op_cost(0); 4063 4064 format %{ %} 4065 interface(CONST_INTER); 4066 %} 4067 4068 // Long Immediate 4069 operand immL() %{ 4070 match(ConL); 4071 4072 op_cost(20); 4073 format %{ %} 4074 interface(CONST_INTER); 4075 %} 4076 4077 // Long Immediate zero 4078 operand immL0() %{ 4079 predicate( n->get_long() == 0L ); 4080 match(ConL); 4081 op_cost(0); 4082 4083 format %{ %} 4084 interface(CONST_INTER); 4085 %} 4086 4087 // Long Immediate zero 4088 operand immL_M1() %{ 4089 predicate( n->get_long() == -1L ); 4090 match(ConL); 4091 op_cost(0); 4092 4093 format %{ %} 4094 interface(CONST_INTER); 4095 %} 4096 4097 // Long immediate from 0 to 127. 4098 // Used for a shorter form of long mul by 10. 4099 operand immL_127() %{ 4100 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); 4101 match(ConL); 4102 op_cost(0); 4103 4104 format %{ %} 4105 interface(CONST_INTER); 4106 %} 4107 4108 // Long Immediate: low 32-bit mask 4109 operand immL_32bits() %{ 4110 predicate(n->get_long() == 0xFFFFFFFFL); 4111 match(ConL); 4112 op_cost(0); 4113 4114 format %{ %} 4115 interface(CONST_INTER); 4116 %} 4117 4118 // Long Immediate: low 32-bit mask 4119 operand immL32() %{ 4120 predicate(n->get_long() == (int)(n->get_long())); 4121 match(ConL); 4122 op_cost(20); 4123 4124 format %{ %} 4125 interface(CONST_INTER); 4126 %} 4127 4128 //Double Immediate zero 4129 operand immDPR0() %{ 4130 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4131 // bug that generates code such that NaNs compare equal to 0.0 4132 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); 4133 match(ConD); 4134 4135 op_cost(5); 4136 format %{ %} 4137 interface(CONST_INTER); 4138 %} 4139 4140 // Double Immediate one 4141 operand immDPR1() %{ 4142 predicate( UseSSE<=1 && n->getd() == 1.0 ); 4143 match(ConD); 4144 4145 op_cost(5); 4146 format %{ %} 4147 interface(CONST_INTER); 4148 %} 4149 4150 // Double Immediate 4151 operand immDPR() %{ 4152 predicate(UseSSE<=1); 4153 match(ConD); 4154 4155 op_cost(5); 4156 format %{ %} 4157 interface(CONST_INTER); 4158 %} 4159 4160 operand immD() %{ 4161 predicate(UseSSE>=2); 4162 match(ConD); 4163 4164 op_cost(5); 4165 format %{ %} 4166 interface(CONST_INTER); 4167 %} 4168 4169 // Double Immediate zero 4170 operand immD0() %{ 4171 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4172 // bug that generates code such that NaNs compare equal to 0.0 AND do not 4173 // compare equal to -0.0. 4174 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); 4175 match(ConD); 4176 4177 format %{ %} 4178 interface(CONST_INTER); 4179 %} 4180 4181 // Float Immediate zero 4182 operand immFPR0() %{ 4183 predicate(UseSSE == 0 && n->getf() == 0.0F); 4184 match(ConF); 4185 4186 op_cost(5); 4187 format %{ %} 4188 interface(CONST_INTER); 4189 %} 4190 4191 // Float Immediate one 4192 operand immFPR1() %{ 4193 predicate(UseSSE == 0 && n->getf() == 1.0F); 4194 match(ConF); 4195 4196 op_cost(5); 4197 format %{ %} 4198 interface(CONST_INTER); 4199 %} 4200 4201 // Float Immediate 4202 operand immFPR() %{ 4203 predicate( UseSSE == 0 ); 4204 match(ConF); 4205 4206 op_cost(5); 4207 format %{ %} 4208 interface(CONST_INTER); 4209 %} 4210 4211 // Float Immediate 4212 operand immF() %{ 4213 predicate(UseSSE >= 1); 4214 match(ConF); 4215 4216 op_cost(5); 4217 format %{ %} 4218 interface(CONST_INTER); 4219 %} 4220 4221 // Float Immediate zero. Zero and not -0.0 4222 operand immF0() %{ 4223 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); 4224 match(ConF); 4225 4226 op_cost(5); 4227 format %{ %} 4228 interface(CONST_INTER); 4229 %} 4230 4231 // Immediates for special shifts (sign extend) 4232 4233 // Constants for increment 4234 operand immI_16() %{ 4235 predicate( n->get_int() == 16 ); 4236 match(ConI); 4237 4238 format %{ %} 4239 interface(CONST_INTER); 4240 %} 4241 4242 operand immI_24() %{ 4243 predicate( n->get_int() == 24 ); 4244 match(ConI); 4245 4246 format %{ %} 4247 interface(CONST_INTER); 4248 %} 4249 4250 // Constant for byte-wide masking 4251 operand immI_255() %{ 4252 predicate( n->get_int() == 255 ); 4253 match(ConI); 4254 4255 format %{ %} 4256 interface(CONST_INTER); 4257 %} 4258 4259 // Constant for short-wide masking 4260 operand immI_65535() %{ 4261 predicate(n->get_int() == 65535); 4262 match(ConI); 4263 4264 format %{ %} 4265 interface(CONST_INTER); 4266 %} 4267 4268 // Register Operands 4269 // Integer Register 4270 operand eRegI() %{ 4271 constraint(ALLOC_IN_RC(e_reg)); 4272 match(RegI); 4273 match(xRegI); 4274 match(eAXRegI); 4275 match(eBXRegI); 4276 match(eCXRegI); 4277 match(eDXRegI); 4278 match(eDIRegI); 4279 match(eSIRegI); 4280 4281 format %{ %} 4282 interface(REG_INTER); 4283 %} 4284 4285 // Subset of Integer Register 4286 operand xRegI(eRegI reg) %{ 4287 constraint(ALLOC_IN_RC(x_reg)); 4288 match(reg); 4289 match(eAXRegI); 4290 match(eBXRegI); 4291 match(eCXRegI); 4292 match(eDXRegI); 4293 4294 format %{ %} 4295 interface(REG_INTER); 4296 %} 4297 4298 // Special Registers 4299 operand eAXRegI(xRegI reg) %{ 4300 constraint(ALLOC_IN_RC(eax_reg)); 4301 match(reg); 4302 match(eRegI); 4303 4304 format %{ "EAX" %} 4305 interface(REG_INTER); 4306 %} 4307 4308 // Special Registers 4309 operand eBXRegI(xRegI reg) %{ 4310 constraint(ALLOC_IN_RC(ebx_reg)); 4311 match(reg); 4312 match(eRegI); 4313 4314 format %{ "EBX" %} 4315 interface(REG_INTER); 4316 %} 4317 4318 operand eCXRegI(xRegI reg) %{ 4319 constraint(ALLOC_IN_RC(ecx_reg)); 4320 match(reg); 4321 match(eRegI); 4322 4323 format %{ "ECX" %} 4324 interface(REG_INTER); 4325 %} 4326 4327 operand eDXRegI(xRegI reg) %{ 4328 constraint(ALLOC_IN_RC(edx_reg)); 4329 match(reg); 4330 match(eRegI); 4331 4332 format %{ "EDX" %} 4333 interface(REG_INTER); 4334 %} 4335 4336 operand eDIRegI(xRegI reg) %{ 4337 constraint(ALLOC_IN_RC(edi_reg)); 4338 match(reg); 4339 match(eRegI); 4340 4341 format %{ "EDI" %} 4342 interface(REG_INTER); 4343 %} 4344 4345 operand naxRegI() %{ 4346 constraint(ALLOC_IN_RC(nax_reg)); 4347 match(RegI); 4348 match(eCXRegI); 4349 match(eDXRegI); 4350 match(eSIRegI); 4351 match(eDIRegI); 4352 4353 format %{ %} 4354 interface(REG_INTER); 4355 %} 4356 4357 operand nadxRegI() %{ 4358 constraint(ALLOC_IN_RC(nadx_reg)); 4359 match(RegI); 4360 match(eBXRegI); 4361 match(eCXRegI); 4362 match(eSIRegI); 4363 match(eDIRegI); 4364 4365 format %{ %} 4366 interface(REG_INTER); 4367 %} 4368 4369 operand ncxRegI() %{ 4370 constraint(ALLOC_IN_RC(ncx_reg)); 4371 match(RegI); 4372 match(eAXRegI); 4373 match(eDXRegI); 4374 match(eSIRegI); 4375 match(eDIRegI); 4376 4377 format %{ %} 4378 interface(REG_INTER); 4379 %} 4380 4381 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 4382 // // 4383 operand eSIRegI(xRegI reg) %{ 4384 constraint(ALLOC_IN_RC(esi_reg)); 4385 match(reg); 4386 match(eRegI); 4387 4388 format %{ "ESI" %} 4389 interface(REG_INTER); 4390 %} 4391 4392 // Pointer Register 4393 operand anyRegP() %{ 4394 constraint(ALLOC_IN_RC(any_reg)); 4395 match(RegP); 4396 match(eAXRegP); 4397 match(eBXRegP); 4398 match(eCXRegP); 4399 match(eDIRegP); 4400 match(eRegP); 4401 4402 format %{ %} 4403 interface(REG_INTER); 4404 %} 4405 4406 operand eRegP() %{ 4407 constraint(ALLOC_IN_RC(e_reg)); 4408 match(RegP); 4409 match(eAXRegP); 4410 match(eBXRegP); 4411 match(eCXRegP); 4412 match(eDIRegP); 4413 4414 format %{ %} 4415 interface(REG_INTER); 4416 %} 4417 4418 // On windows95, EBP is not safe to use for implicit null tests. 4419 operand eRegP_no_EBP() %{ 4420 constraint(ALLOC_IN_RC(e_reg_no_rbp)); 4421 match(RegP); 4422 match(eAXRegP); 4423 match(eBXRegP); 4424 match(eCXRegP); 4425 match(eDIRegP); 4426 4427 op_cost(100); 4428 format %{ %} 4429 interface(REG_INTER); 4430 %} 4431 4432 operand naxRegP() %{ 4433 constraint(ALLOC_IN_RC(nax_reg)); 4434 match(RegP); 4435 match(eBXRegP); 4436 match(eDXRegP); 4437 match(eCXRegP); 4438 match(eSIRegP); 4439 match(eDIRegP); 4440 4441 format %{ %} 4442 interface(REG_INTER); 4443 %} 4444 4445 operand nabxRegP() %{ 4446 constraint(ALLOC_IN_RC(nabx_reg)); 4447 match(RegP); 4448 match(eCXRegP); 4449 match(eDXRegP); 4450 match(eSIRegP); 4451 match(eDIRegP); 4452 4453 format %{ %} 4454 interface(REG_INTER); 4455 %} 4456 4457 operand pRegP() %{ 4458 constraint(ALLOC_IN_RC(p_reg)); 4459 match(RegP); 4460 match(eBXRegP); 4461 match(eDXRegP); 4462 match(eSIRegP); 4463 match(eDIRegP); 4464 4465 format %{ %} 4466 interface(REG_INTER); 4467 %} 4468 4469 // Special Registers 4470 // Return a pointer value 4471 operand eAXRegP(eRegP reg) %{ 4472 constraint(ALLOC_IN_RC(eax_reg)); 4473 match(reg); 4474 format %{ "EAX" %} 4475 interface(REG_INTER); 4476 %} 4477 4478 // Used in AtomicAdd 4479 operand eBXRegP(eRegP reg) %{ 4480 constraint(ALLOC_IN_RC(ebx_reg)); 4481 match(reg); 4482 format %{ "EBX" %} 4483 interface(REG_INTER); 4484 %} 4485 4486 // Tail-call (interprocedural jump) to interpreter 4487 operand eCXRegP(eRegP reg) %{ 4488 constraint(ALLOC_IN_RC(ecx_reg)); 4489 match(reg); 4490 format %{ "ECX" %} 4491 interface(REG_INTER); 4492 %} 4493 4494 operand eSIRegP(eRegP reg) %{ 4495 constraint(ALLOC_IN_RC(esi_reg)); 4496 match(reg); 4497 format %{ "ESI" %} 4498 interface(REG_INTER); 4499 %} 4500 4501 // Used in rep stosw 4502 operand eDIRegP(eRegP reg) %{ 4503 constraint(ALLOC_IN_RC(edi_reg)); 4504 match(reg); 4505 format %{ "EDI" %} 4506 interface(REG_INTER); 4507 %} 4508 4509 operand eBPRegP() %{ 4510 constraint(ALLOC_IN_RC(ebp_reg)); 4511 match(RegP); 4512 format %{ "EBP" %} 4513 interface(REG_INTER); 4514 %} 4515 4516 operand eRegL() %{ 4517 constraint(ALLOC_IN_RC(long_reg)); 4518 match(RegL); 4519 match(eADXRegL); 4520 4521 format %{ %} 4522 interface(REG_INTER); 4523 %} 4524 4525 operand eADXRegL( eRegL reg ) %{ 4526 constraint(ALLOC_IN_RC(eadx_reg)); 4527 match(reg); 4528 4529 format %{ "EDX:EAX" %} 4530 interface(REG_INTER); 4531 %} 4532 4533 operand eBCXRegL( eRegL reg ) %{ 4534 constraint(ALLOC_IN_RC(ebcx_reg)); 4535 match(reg); 4536 4537 format %{ "EBX:ECX" %} 4538 interface(REG_INTER); 4539 %} 4540 4541 // Special case for integer high multiply 4542 operand eADXRegL_low_only() %{ 4543 constraint(ALLOC_IN_RC(eadx_reg)); 4544 match(RegL); 4545 4546 format %{ "EAX" %} 4547 interface(REG_INTER); 4548 %} 4549 4550 // Flags register, used as output of compare instructions 4551 operand eFlagsReg() %{ 4552 constraint(ALLOC_IN_RC(int_flags)); 4553 match(RegFlags); 4554 4555 format %{ "EFLAGS" %} 4556 interface(REG_INTER); 4557 %} 4558 4559 // Flags register, used as output of FLOATING POINT compare instructions 4560 operand eFlagsRegU() %{ 4561 constraint(ALLOC_IN_RC(int_flags)); 4562 match(RegFlags); 4563 4564 format %{ "EFLAGS_U" %} 4565 interface(REG_INTER); 4566 %} 4567 4568 operand eFlagsRegUCF() %{ 4569 constraint(ALLOC_IN_RC(int_flags)); 4570 match(RegFlags); 4571 predicate(false); 4572 4573 format %{ "EFLAGS_U_CF" %} 4574 interface(REG_INTER); 4575 %} 4576 4577 // Condition Code Register used by long compare 4578 operand flagsReg_long_LTGE() %{ 4579 constraint(ALLOC_IN_RC(int_flags)); 4580 match(RegFlags); 4581 format %{ "FLAGS_LTGE" %} 4582 interface(REG_INTER); 4583 %} 4584 operand flagsReg_long_EQNE() %{ 4585 constraint(ALLOC_IN_RC(int_flags)); 4586 match(RegFlags); 4587 format %{ "FLAGS_EQNE" %} 4588 interface(REG_INTER); 4589 %} 4590 operand flagsReg_long_LEGT() %{ 4591 constraint(ALLOC_IN_RC(int_flags)); 4592 match(RegFlags); 4593 format %{ "FLAGS_LEGT" %} 4594 interface(REG_INTER); 4595 %} 4596 4597 // Float register operands 4598 operand regDPR() %{ 4599 predicate( UseSSE < 2 ); 4600 constraint(ALLOC_IN_RC(dbl_reg)); 4601 match(RegD); 4602 match(regDPR1); 4603 match(regDPR2); 4604 format %{ %} 4605 interface(REG_INTER); 4606 %} 4607 4608 operand regDPR1(regDPR reg) %{ 4609 predicate( UseSSE < 2 ); 4610 constraint(ALLOC_IN_RC(dbl_reg0)); 4611 match(reg); 4612 format %{ "FPR1" %} 4613 interface(REG_INTER); 4614 %} 4615 4616 operand regDPR2(regDPR reg) %{ 4617 predicate( UseSSE < 2 ); 4618 constraint(ALLOC_IN_RC(dbl_reg1)); 4619 match(reg); 4620 format %{ "FPR2" %} 4621 interface(REG_INTER); 4622 %} 4623 4624 operand regnotDPR1(regDPR reg) %{ 4625 predicate( UseSSE < 2 ); 4626 constraint(ALLOC_IN_RC(dbl_notreg0)); 4627 match(reg); 4628 format %{ %} 4629 interface(REG_INTER); 4630 %} 4631 4632 // XMM Double register operands 4633 operand regD() %{ 4634 predicate( UseSSE>=2 ); 4635 constraint(ALLOC_IN_RC(xdb_reg)); 4636 match(RegD); 4637 match(regD6); 4638 match(regD7); 4639 format %{ %} 4640 interface(REG_INTER); 4641 %} 4642 4643 // XMM6 double register operands 4644 operand regD6(regD reg) %{ 4645 predicate( UseSSE>=2 ); 4646 constraint(ALLOC_IN_RC(xdb_reg6)); 4647 match(reg); 4648 format %{ "XMM6" %} 4649 interface(REG_INTER); 4650 %} 4651 4652 // XMM7 double register operands 4653 operand regD7(regD reg) %{ 4654 predicate( UseSSE>=2 ); 4655 constraint(ALLOC_IN_RC(xdb_reg7)); 4656 match(reg); 4657 format %{ "XMM7" %} 4658 interface(REG_INTER); 4659 %} 4660 4661 // Float register operands 4662 operand regFPR() %{ 4663 predicate( UseSSE < 2 ); 4664 constraint(ALLOC_IN_RC(flt_reg)); 4665 match(RegF); 4666 match(regFPR1); 4667 format %{ %} 4668 interface(REG_INTER); 4669 %} 4670 4671 // Float register operands 4672 operand regFPR1(regFPR reg) %{ 4673 predicate( UseSSE < 2 ); 4674 constraint(ALLOC_IN_RC(flt_reg0)); 4675 match(reg); 4676 format %{ "FPR1" %} 4677 interface(REG_INTER); 4678 %} 4679 4680 // XMM register operands 4681 operand regF() %{ 4682 predicate( UseSSE>=1 ); 4683 constraint(ALLOC_IN_RC(xmm_reg)); 4684 match(RegF); 4685 format %{ %} 4686 interface(REG_INTER); 4687 %} 4688 4689 4690 //----------Memory Operands---------------------------------------------------- 4691 // Direct Memory Operand 4692 operand direct(immP addr) %{ 4693 match(addr); 4694 4695 format %{ "[$addr]" %} 4696 interface(MEMORY_INTER) %{ 4697 base(0xFFFFFFFF); 4698 index(0x4); 4699 scale(0x0); 4700 disp($addr); 4701 %} 4702 %} 4703 4704 // Indirect Memory Operand 4705 operand indirect(eRegP reg) %{ 4706 constraint(ALLOC_IN_RC(e_reg)); 4707 match(reg); 4708 4709 format %{ "[$reg]" %} 4710 interface(MEMORY_INTER) %{ 4711 base($reg); 4712 index(0x4); 4713 scale(0x0); 4714 disp(0x0); 4715 %} 4716 %} 4717 4718 // Indirect Memory Plus Short Offset Operand 4719 operand indOffset8(eRegP reg, immI8 off) %{ 4720 match(AddP reg off); 4721 4722 format %{ "[$reg + $off]" %} 4723 interface(MEMORY_INTER) %{ 4724 base($reg); 4725 index(0x4); 4726 scale(0x0); 4727 disp($off); 4728 %} 4729 %} 4730 4731 // Indirect Memory Plus Long Offset Operand 4732 operand indOffset32(eRegP reg, immI off) %{ 4733 match(AddP reg off); 4734 4735 format %{ "[$reg + $off]" %} 4736 interface(MEMORY_INTER) %{ 4737 base($reg); 4738 index(0x4); 4739 scale(0x0); 4740 disp($off); 4741 %} 4742 %} 4743 4744 // Indirect Memory Plus Long Offset Operand 4745 operand indOffset32X(eRegI reg, immP off) %{ 4746 match(AddP off reg); 4747 4748 format %{ "[$reg + $off]" %} 4749 interface(MEMORY_INTER) %{ 4750 base($reg); 4751 index(0x4); 4752 scale(0x0); 4753 disp($off); 4754 %} 4755 %} 4756 4757 // Indirect Memory Plus Index Register Plus Offset Operand 4758 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ 4759 match(AddP (AddP reg ireg) off); 4760 4761 op_cost(10); 4762 format %{"[$reg + $off + $ireg]" %} 4763 interface(MEMORY_INTER) %{ 4764 base($reg); 4765 index($ireg); 4766 scale(0x0); 4767 disp($off); 4768 %} 4769 %} 4770 4771 // Indirect Memory Plus Index Register Plus Offset Operand 4772 operand indIndex(eRegP reg, eRegI ireg) %{ 4773 match(AddP reg ireg); 4774 4775 op_cost(10); 4776 format %{"[$reg + $ireg]" %} 4777 interface(MEMORY_INTER) %{ 4778 base($reg); 4779 index($ireg); 4780 scale(0x0); 4781 disp(0x0); 4782 %} 4783 %} 4784 4785 // // ------------------------------------------------------------------------- 4786 // // 486 architecture doesn't support "scale * index + offset" with out a base 4787 // // ------------------------------------------------------------------------- 4788 // // Scaled Memory Operands 4789 // // Indirect Memory Times Scale Plus Offset Operand 4790 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ 4791 // match(AddP off (LShiftI ireg scale)); 4792 // 4793 // op_cost(10); 4794 // format %{"[$off + $ireg << $scale]" %} 4795 // interface(MEMORY_INTER) %{ 4796 // base(0x4); 4797 // index($ireg); 4798 // scale($scale); 4799 // disp($off); 4800 // %} 4801 // %} 4802 4803 // Indirect Memory Times Scale Plus Index Register 4804 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ 4805 match(AddP reg (LShiftI ireg scale)); 4806 4807 op_cost(10); 4808 format %{"[$reg + $ireg << $scale]" %} 4809 interface(MEMORY_INTER) %{ 4810 base($reg); 4811 index($ireg); 4812 scale($scale); 4813 disp(0x0); 4814 %} 4815 %} 4816 4817 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4818 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ 4819 match(AddP (AddP reg (LShiftI ireg scale)) off); 4820 4821 op_cost(10); 4822 format %{"[$reg + $off + $ireg << $scale]" %} 4823 interface(MEMORY_INTER) %{ 4824 base($reg); 4825 index($ireg); 4826 scale($scale); 4827 disp($off); 4828 %} 4829 %} 4830 4831 //----------Load Long Memory Operands------------------------------------------ 4832 // The load-long idiom will use it's address expression again after loading 4833 // the first word of the long. If the load-long destination overlaps with 4834 // registers used in the addressing expression, the 2nd half will be loaded 4835 // from a clobbered address. Fix this by requiring that load-long use 4836 // address registers that do not overlap with the load-long target. 4837 4838 // load-long support 4839 operand load_long_RegP() %{ 4840 constraint(ALLOC_IN_RC(esi_reg)); 4841 match(RegP); 4842 match(eSIRegP); 4843 op_cost(100); 4844 format %{ %} 4845 interface(REG_INTER); 4846 %} 4847 4848 // Indirect Memory Operand Long 4849 operand load_long_indirect(load_long_RegP reg) %{ 4850 constraint(ALLOC_IN_RC(esi_reg)); 4851 match(reg); 4852 4853 format %{ "[$reg]" %} 4854 interface(MEMORY_INTER) %{ 4855 base($reg); 4856 index(0x4); 4857 scale(0x0); 4858 disp(0x0); 4859 %} 4860 %} 4861 4862 // Indirect Memory Plus Long Offset Operand 4863 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ 4864 match(AddP reg off); 4865 4866 format %{ "[$reg + $off]" %} 4867 interface(MEMORY_INTER) %{ 4868 base($reg); 4869 index(0x4); 4870 scale(0x0); 4871 disp($off); 4872 %} 4873 %} 4874 4875 opclass load_long_memory(load_long_indirect, load_long_indOffset32); 4876 4877 4878 //----------Special Memory Operands-------------------------------------------- 4879 // Stack Slot Operand - This operand is used for loading and storing temporary 4880 // values on the stack where a match requires a value to 4881 // flow through memory. 4882 operand stackSlotP(sRegP reg) %{ 4883 constraint(ALLOC_IN_RC(stack_slots)); 4884 // No match rule because this operand is only generated in matching 4885 format %{ "[$reg]" %} 4886 interface(MEMORY_INTER) %{ 4887 base(0x4); // ESP 4888 index(0x4); // No Index 4889 scale(0x0); // No Scale 4890 disp($reg); // Stack Offset 4891 %} 4892 %} 4893 4894 operand stackSlotI(sRegI reg) %{ 4895 constraint(ALLOC_IN_RC(stack_slots)); 4896 // No match rule because this operand is only generated in matching 4897 format %{ "[$reg]" %} 4898 interface(MEMORY_INTER) %{ 4899 base(0x4); // ESP 4900 index(0x4); // No Index 4901 scale(0x0); // No Scale 4902 disp($reg); // Stack Offset 4903 %} 4904 %} 4905 4906 operand stackSlotF(sRegF reg) %{ 4907 constraint(ALLOC_IN_RC(stack_slots)); 4908 // No match rule because this operand is only generated in matching 4909 format %{ "[$reg]" %} 4910 interface(MEMORY_INTER) %{ 4911 base(0x4); // ESP 4912 index(0x4); // No Index 4913 scale(0x0); // No Scale 4914 disp($reg); // Stack Offset 4915 %} 4916 %} 4917 4918 operand stackSlotD(sRegD reg) %{ 4919 constraint(ALLOC_IN_RC(stack_slots)); 4920 // No match rule because this operand is only generated in matching 4921 format %{ "[$reg]" %} 4922 interface(MEMORY_INTER) %{ 4923 base(0x4); // ESP 4924 index(0x4); // No Index 4925 scale(0x0); // No Scale 4926 disp($reg); // Stack Offset 4927 %} 4928 %} 4929 4930 operand stackSlotL(sRegL reg) %{ 4931 constraint(ALLOC_IN_RC(stack_slots)); 4932 // No match rule because this operand is only generated in matching 4933 format %{ "[$reg]" %} 4934 interface(MEMORY_INTER) %{ 4935 base(0x4); // ESP 4936 index(0x4); // No Index 4937 scale(0x0); // No Scale 4938 disp($reg); // Stack Offset 4939 %} 4940 %} 4941 4942 //----------Memory Operands - Win95 Implicit Null Variants---------------- 4943 // Indirect Memory Operand 4944 operand indirect_win95_safe(eRegP_no_EBP reg) 4945 %{ 4946 constraint(ALLOC_IN_RC(e_reg)); 4947 match(reg); 4948 4949 op_cost(100); 4950 format %{ "[$reg]" %} 4951 interface(MEMORY_INTER) %{ 4952 base($reg); 4953 index(0x4); 4954 scale(0x0); 4955 disp(0x0); 4956 %} 4957 %} 4958 4959 // Indirect Memory Plus Short Offset Operand 4960 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) 4961 %{ 4962 match(AddP reg off); 4963 4964 op_cost(100); 4965 format %{ "[$reg + $off]" %} 4966 interface(MEMORY_INTER) %{ 4967 base($reg); 4968 index(0x4); 4969 scale(0x0); 4970 disp($off); 4971 %} 4972 %} 4973 4974 // Indirect Memory Plus Long Offset Operand 4975 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) 4976 %{ 4977 match(AddP reg off); 4978 4979 op_cost(100); 4980 format %{ "[$reg + $off]" %} 4981 interface(MEMORY_INTER) %{ 4982 base($reg); 4983 index(0x4); 4984 scale(0x0); 4985 disp($off); 4986 %} 4987 %} 4988 4989 // Indirect Memory Plus Index Register Plus Offset Operand 4990 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) 4991 %{ 4992 match(AddP (AddP reg ireg) off); 4993 4994 op_cost(100); 4995 format %{"[$reg + $off + $ireg]" %} 4996 interface(MEMORY_INTER) %{ 4997 base($reg); 4998 index($ireg); 4999 scale(0x0); 5000 disp($off); 5001 %} 5002 %} 5003 5004 // Indirect Memory Times Scale Plus Index Register 5005 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) 5006 %{ 5007 match(AddP reg (LShiftI ireg scale)); 5008 5009 op_cost(100); 5010 format %{"[$reg + $ireg << $scale]" %} 5011 interface(MEMORY_INTER) %{ 5012 base($reg); 5013 index($ireg); 5014 scale($scale); 5015 disp(0x0); 5016 %} 5017 %} 5018 5019 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5020 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) 5021 %{ 5022 match(AddP (AddP reg (LShiftI ireg scale)) off); 5023 5024 op_cost(100); 5025 format %{"[$reg + $off + $ireg << $scale]" %} 5026 interface(MEMORY_INTER) %{ 5027 base($reg); 5028 index($ireg); 5029 scale($scale); 5030 disp($off); 5031 %} 5032 %} 5033 5034 //----------Conditional Branch Operands---------------------------------------- 5035 // Comparison Op - This is the operation of the comparison, and is limited to 5036 // the following set of codes: 5037 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 5038 // 5039 // Other attributes of the comparison, such as unsignedness, are specified 5040 // by the comparison instruction that sets a condition code flags register. 5041 // That result is represented by a flags operand whose subtype is appropriate 5042 // to the unsignedness (etc.) of the comparison. 5043 // 5044 // Later, the instruction which matches both the Comparison Op (a Bool) and 5045 // the flags (produced by the Cmp) specifies the coding of the comparison op 5046 // by matching a specific subtype of Bool operand below, such as cmpOpU. 5047 5048 // Comparision Code 5049 operand cmpOp() %{ 5050 match(Bool); 5051 5052 format %{ "" %} 5053 interface(COND_INTER) %{ 5054 equal(0x4, "e"); 5055 not_equal(0x5, "ne"); 5056 less(0xC, "l"); 5057 greater_equal(0xD, "ge"); 5058 less_equal(0xE, "le"); 5059 greater(0xF, "g"); 5060 %} 5061 %} 5062 5063 // Comparison Code, unsigned compare. Used by FP also, with 5064 // C2 (unordered) turned into GT or LT already. The other bits 5065 // C0 and C3 are turned into Carry & Zero flags. 5066 operand cmpOpU() %{ 5067 match(Bool); 5068 5069 format %{ "" %} 5070 interface(COND_INTER) %{ 5071 equal(0x4, "e"); 5072 not_equal(0x5, "ne"); 5073 less(0x2, "b"); 5074 greater_equal(0x3, "nb"); 5075 less_equal(0x6, "be"); 5076 greater(0x7, "nbe"); 5077 %} 5078 %} 5079 5080 // Floating comparisons that don't require any fixup for the unordered case 5081 operand cmpOpUCF() %{ 5082 match(Bool); 5083 predicate(n->as_Bool()->_test._test == BoolTest::lt || 5084 n->as_Bool()->_test._test == BoolTest::ge || 5085 n->as_Bool()->_test._test == BoolTest::le || 5086 n->as_Bool()->_test._test == BoolTest::gt); 5087 format %{ "" %} 5088 interface(COND_INTER) %{ 5089 equal(0x4, "e"); 5090 not_equal(0x5, "ne"); 5091 less(0x2, "b"); 5092 greater_equal(0x3, "nb"); 5093 less_equal(0x6, "be"); 5094 greater(0x7, "nbe"); 5095 %} 5096 %} 5097 5098 5099 // Floating comparisons that can be fixed up with extra conditional jumps 5100 operand cmpOpUCF2() %{ 5101 match(Bool); 5102 predicate(n->as_Bool()->_test._test == BoolTest::ne || 5103 n->as_Bool()->_test._test == BoolTest::eq); 5104 format %{ "" %} 5105 interface(COND_INTER) %{ 5106 equal(0x4, "e"); 5107 not_equal(0x5, "ne"); 5108 less(0x2, "b"); 5109 greater_equal(0x3, "nb"); 5110 less_equal(0x6, "be"); 5111 greater(0x7, "nbe"); 5112 %} 5113 %} 5114 5115 // Comparison Code for FP conditional move 5116 operand cmpOp_fcmov() %{ 5117 match(Bool); 5118 5119 format %{ "" %} 5120 interface(COND_INTER) %{ 5121 equal (0x0C8); 5122 not_equal (0x1C8); 5123 less (0x0C0); 5124 greater_equal(0x1C0); 5125 less_equal (0x0D0); 5126 greater (0x1D0); 5127 %} 5128 %} 5129 5130 // Comparision Code used in long compares 5131 operand cmpOp_commute() %{ 5132 match(Bool); 5133 5134 format %{ "" %} 5135 interface(COND_INTER) %{ 5136 equal(0x4, "e"); 5137 not_equal(0x5, "ne"); 5138 less(0xF, "g"); 5139 greater_equal(0xE, "le"); 5140 less_equal(0xD, "ge"); 5141 greater(0xC, "l"); 5142 %} 5143 %} 5144 5145 //----------OPERAND CLASSES---------------------------------------------------- 5146 // Operand Classes are groups of operands that are used as to simplify 5147 // instruction definitions by not requiring the AD writer to specify separate 5148 // instructions for every form of operand when the instruction accepts 5149 // multiple operand types with the same basic encoding and format. The classic 5150 // case of this is memory operands. 5151 5152 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 5153 indIndex, indIndexScale, indIndexScaleOffset); 5154 5155 // Long memory operations are encoded in 2 instructions and a +4 offset. 5156 // This means some kind of offset is always required and you cannot use 5157 // an oop as the offset (done when working on static globals). 5158 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, 5159 indIndex, indIndexScale, indIndexScaleOffset); 5160 5161 5162 //----------PIPELINE----------------------------------------------------------- 5163 // Rules which define the behavior of the target architectures pipeline. 5164 pipeline %{ 5165 5166 //----------ATTRIBUTES--------------------------------------------------------- 5167 attributes %{ 5168 variable_size_instructions; // Fixed size instructions 5169 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 5170 instruction_unit_size = 1; // An instruction is 1 bytes long 5171 instruction_fetch_unit_size = 16; // The processor fetches one line 5172 instruction_fetch_units = 1; // of 16 bytes 5173 5174 // List of nop instructions 5175 nops( MachNop ); 5176 %} 5177 5178 //----------RESOURCES---------------------------------------------------------- 5179 // Resources are the functional units available to the machine 5180 5181 // Generic P2/P3 pipeline 5182 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of 5183 // 3 instructions decoded per cycle. 5184 // 2 load/store ops per cycle, 1 branch, 1 FPU, 5185 // 2 ALU op, only ALU0 handles mul/div instructions. 5186 resources( D0, D1, D2, DECODE = D0 | D1 | D2, 5187 MS0, MS1, MEM = MS0 | MS1, 5188 BR, FPU, 5189 ALU0, ALU1, ALU = ALU0 | ALU1 ); 5190 5191 //----------PIPELINE DESCRIPTION----------------------------------------------- 5192 // Pipeline Description specifies the stages in the machine's pipeline 5193 5194 // Generic P2/P3 pipeline 5195 pipe_desc(S0, S1, S2, S3, S4, S5); 5196 5197 //----------PIPELINE CLASSES--------------------------------------------------- 5198 // Pipeline Classes describe the stages in which input and output are 5199 // referenced by the hardware pipeline. 5200 5201 // Naming convention: ialu or fpu 5202 // Then: _reg 5203 // Then: _reg if there is a 2nd register 5204 // Then: _long if it's a pair of instructions implementing a long 5205 // Then: _fat if it requires the big decoder 5206 // Or: _mem if it requires the big decoder and a memory unit. 5207 5208 // Integer ALU reg operation 5209 pipe_class ialu_reg(eRegI dst) %{ 5210 single_instruction; 5211 dst : S4(write); 5212 dst : S3(read); 5213 DECODE : S0; // any decoder 5214 ALU : S3; // any alu 5215 %} 5216 5217 // Long ALU reg operation 5218 pipe_class ialu_reg_long(eRegL dst) %{ 5219 instruction_count(2); 5220 dst : S4(write); 5221 dst : S3(read); 5222 DECODE : S0(2); // any 2 decoders 5223 ALU : S3(2); // both alus 5224 %} 5225 5226 // Integer ALU reg operation using big decoder 5227 pipe_class ialu_reg_fat(eRegI dst) %{ 5228 single_instruction; 5229 dst : S4(write); 5230 dst : S3(read); 5231 D0 : S0; // big decoder only 5232 ALU : S3; // any alu 5233 %} 5234 5235 // Long ALU reg operation using big decoder 5236 pipe_class ialu_reg_long_fat(eRegL dst) %{ 5237 instruction_count(2); 5238 dst : S4(write); 5239 dst : S3(read); 5240 D0 : S0(2); // big decoder only; twice 5241 ALU : S3(2); // any 2 alus 5242 %} 5243 5244 // Integer ALU reg-reg operation 5245 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ 5246 single_instruction; 5247 dst : S4(write); 5248 src : S3(read); 5249 DECODE : S0; // any decoder 5250 ALU : S3; // any alu 5251 %} 5252 5253 // Long ALU reg-reg operation 5254 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ 5255 instruction_count(2); 5256 dst : S4(write); 5257 src : S3(read); 5258 DECODE : S0(2); // any 2 decoders 5259 ALU : S3(2); // both alus 5260 %} 5261 5262 // Integer ALU reg-reg operation 5263 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ 5264 single_instruction; 5265 dst : S4(write); 5266 src : S3(read); 5267 D0 : S0; // big decoder only 5268 ALU : S3; // any alu 5269 %} 5270 5271 // Long ALU reg-reg operation 5272 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ 5273 instruction_count(2); 5274 dst : S4(write); 5275 src : S3(read); 5276 D0 : S0(2); // big decoder only; twice 5277 ALU : S3(2); // both alus 5278 %} 5279 5280 // Integer ALU reg-mem operation 5281 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ 5282 single_instruction; 5283 dst : S5(write); 5284 mem : S3(read); 5285 D0 : S0; // big decoder only 5286 ALU : S4; // any alu 5287 MEM : S3; // any mem 5288 %} 5289 5290 // Long ALU reg-mem operation 5291 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ 5292 instruction_count(2); 5293 dst : S5(write); 5294 mem : S3(read); 5295 D0 : S0(2); // big decoder only; twice 5296 ALU : S4(2); // any 2 alus 5297 MEM : S3(2); // both mems 5298 %} 5299 5300 // Integer mem operation (prefetch) 5301 pipe_class ialu_mem(memory mem) 5302 %{ 5303 single_instruction; 5304 mem : S3(read); 5305 D0 : S0; // big decoder only 5306 MEM : S3; // any mem 5307 %} 5308 5309 // Integer Store to Memory 5310 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ 5311 single_instruction; 5312 mem : S3(read); 5313 src : S5(read); 5314 D0 : S0; // big decoder only 5315 ALU : S4; // any alu 5316 MEM : S3; 5317 %} 5318 5319 // Long Store to Memory 5320 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ 5321 instruction_count(2); 5322 mem : S3(read); 5323 src : S5(read); 5324 D0 : S0(2); // big decoder only; twice 5325 ALU : S4(2); // any 2 alus 5326 MEM : S3(2); // Both mems 5327 %} 5328 5329 // Integer Store to Memory 5330 pipe_class ialu_mem_imm(memory mem) %{ 5331 single_instruction; 5332 mem : S3(read); 5333 D0 : S0; // big decoder only 5334 ALU : S4; // any alu 5335 MEM : S3; 5336 %} 5337 5338 // Integer ALU0 reg-reg operation 5339 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ 5340 single_instruction; 5341 dst : S4(write); 5342 src : S3(read); 5343 D0 : S0; // Big decoder only 5344 ALU0 : S3; // only alu0 5345 %} 5346 5347 // Integer ALU0 reg-mem operation 5348 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ 5349 single_instruction; 5350 dst : S5(write); 5351 mem : S3(read); 5352 D0 : S0; // big decoder only 5353 ALU0 : S4; // ALU0 only 5354 MEM : S3; // any mem 5355 %} 5356 5357 // Integer ALU reg-reg operation 5358 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ 5359 single_instruction; 5360 cr : S4(write); 5361 src1 : S3(read); 5362 src2 : S3(read); 5363 DECODE : S0; // any decoder 5364 ALU : S3; // any alu 5365 %} 5366 5367 // Integer ALU reg-imm operation 5368 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ 5369 single_instruction; 5370 cr : S4(write); 5371 src1 : S3(read); 5372 DECODE : S0; // any decoder 5373 ALU : S3; // any alu 5374 %} 5375 5376 // Integer ALU reg-mem operation 5377 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ 5378 single_instruction; 5379 cr : S4(write); 5380 src1 : S3(read); 5381 src2 : S3(read); 5382 D0 : S0; // big decoder only 5383 ALU : S4; // any alu 5384 MEM : S3; 5385 %} 5386 5387 // Conditional move reg-reg 5388 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ 5389 instruction_count(4); 5390 y : S4(read); 5391 q : S3(read); 5392 p : S3(read); 5393 DECODE : S0(4); // any decoder 5394 %} 5395 5396 // Conditional move reg-reg 5397 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ 5398 single_instruction; 5399 dst : S4(write); 5400 src : S3(read); 5401 cr : S3(read); 5402 DECODE : S0; // any decoder 5403 %} 5404 5405 // Conditional move reg-mem 5406 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ 5407 single_instruction; 5408 dst : S4(write); 5409 src : S3(read); 5410 cr : S3(read); 5411 DECODE : S0; // any decoder 5412 MEM : S3; 5413 %} 5414 5415 // Conditional move reg-reg long 5416 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ 5417 single_instruction; 5418 dst : S4(write); 5419 src : S3(read); 5420 cr : S3(read); 5421 DECODE : S0(2); // any 2 decoders 5422 %} 5423 5424 // Conditional move double reg-reg 5425 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ 5426 single_instruction; 5427 dst : S4(write); 5428 src : S3(read); 5429 cr : S3(read); 5430 DECODE : S0; // any decoder 5431 %} 5432 5433 // Float reg-reg operation 5434 pipe_class fpu_reg(regDPR dst) %{ 5435 instruction_count(2); 5436 dst : S3(read); 5437 DECODE : S0(2); // any 2 decoders 5438 FPU : S3; 5439 %} 5440 5441 // Float reg-reg operation 5442 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ 5443 instruction_count(2); 5444 dst : S4(write); 5445 src : S3(read); 5446 DECODE : S0(2); // any 2 decoders 5447 FPU : S3; 5448 %} 5449 5450 // Float reg-reg operation 5451 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ 5452 instruction_count(3); 5453 dst : S4(write); 5454 src1 : S3(read); 5455 src2 : S3(read); 5456 DECODE : S0(3); // any 3 decoders 5457 FPU : S3(2); 5458 %} 5459 5460 // Float reg-reg operation 5461 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ 5462 instruction_count(4); 5463 dst : S4(write); 5464 src1 : S3(read); 5465 src2 : S3(read); 5466 src3 : S3(read); 5467 DECODE : S0(4); // any 3 decoders 5468 FPU : S3(2); 5469 %} 5470 5471 // Float reg-reg operation 5472 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ 5473 instruction_count(4); 5474 dst : S4(write); 5475 src1 : S3(read); 5476 src2 : S3(read); 5477 src3 : S3(read); 5478 DECODE : S1(3); // any 3 decoders 5479 D0 : S0; // Big decoder only 5480 FPU : S3(2); 5481 MEM : S3; 5482 %} 5483 5484 // Float reg-mem operation 5485 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ 5486 instruction_count(2); 5487 dst : S5(write); 5488 mem : S3(read); 5489 D0 : S0; // big decoder only 5490 DECODE : S1; // any decoder for FPU POP 5491 FPU : S4; 5492 MEM : S3; // any mem 5493 %} 5494 5495 // Float reg-mem operation 5496 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ 5497 instruction_count(3); 5498 dst : S5(write); 5499 src1 : S3(read); 5500 mem : S3(read); 5501 D0 : S0; // big decoder only 5502 DECODE : S1(2); // any decoder for FPU POP 5503 FPU : S4; 5504 MEM : S3; // any mem 5505 %} 5506 5507 // Float mem-reg operation 5508 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ 5509 instruction_count(2); 5510 src : S5(read); 5511 mem : S3(read); 5512 DECODE : S0; // any decoder for FPU PUSH 5513 D0 : S1; // big decoder only 5514 FPU : S4; 5515 MEM : S3; // any mem 5516 %} 5517 5518 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ 5519 instruction_count(3); 5520 src1 : S3(read); 5521 src2 : S3(read); 5522 mem : S3(read); 5523 DECODE : S0(2); // any decoder for FPU PUSH 5524 D0 : S1; // big decoder only 5525 FPU : S4; 5526 MEM : S3; // any mem 5527 %} 5528 5529 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ 5530 instruction_count(3); 5531 src1 : S3(read); 5532 src2 : S3(read); 5533 mem : S4(read); 5534 DECODE : S0; // any decoder for FPU PUSH 5535 D0 : S0(2); // big decoder only 5536 FPU : S4; 5537 MEM : S3(2); // any mem 5538 %} 5539 5540 pipe_class fpu_mem_mem(memory dst, memory src1) %{ 5541 instruction_count(2); 5542 src1 : S3(read); 5543 dst : S4(read); 5544 D0 : S0(2); // big decoder only 5545 MEM : S3(2); // any mem 5546 %} 5547 5548 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ 5549 instruction_count(3); 5550 src1 : S3(read); 5551 src2 : S3(read); 5552 dst : S4(read); 5553 D0 : S0(3); // big decoder only 5554 FPU : S4; 5555 MEM : S3(3); // any mem 5556 %} 5557 5558 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ 5559 instruction_count(3); 5560 src1 : S4(read); 5561 mem : S4(read); 5562 DECODE : S0; // any decoder for FPU PUSH 5563 D0 : S0(2); // big decoder only 5564 FPU : S4; 5565 MEM : S3(2); // any mem 5566 %} 5567 5568 // Float load constant 5569 pipe_class fpu_reg_con(regDPR dst) %{ 5570 instruction_count(2); 5571 dst : S5(write); 5572 D0 : S0; // big decoder only for the load 5573 DECODE : S1; // any decoder for FPU POP 5574 FPU : S4; 5575 MEM : S3; // any mem 5576 %} 5577 5578 // Float load constant 5579 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ 5580 instruction_count(3); 5581 dst : S5(write); 5582 src : S3(read); 5583 D0 : S0; // big decoder only for the load 5584 DECODE : S1(2); // any decoder for FPU POP 5585 FPU : S4; 5586 MEM : S3; // any mem 5587 %} 5588 5589 // UnConditional branch 5590 pipe_class pipe_jmp( label labl ) %{ 5591 single_instruction; 5592 BR : S3; 5593 %} 5594 5595 // Conditional branch 5596 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ 5597 single_instruction; 5598 cr : S1(read); 5599 BR : S3; 5600 %} 5601 5602 // Allocation idiom 5603 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ 5604 instruction_count(1); force_serialization; 5605 fixed_latency(6); 5606 heap_ptr : S3(read); 5607 DECODE : S0(3); 5608 D0 : S2; 5609 MEM : S3; 5610 ALU : S3(2); 5611 dst : S5(write); 5612 BR : S5; 5613 %} 5614 5615 // Generic big/slow expanded idiom 5616 pipe_class pipe_slow( ) %{ 5617 instruction_count(10); multiple_bundles; force_serialization; 5618 fixed_latency(100); 5619 D0 : S0(2); 5620 MEM : S3(2); 5621 %} 5622 5623 // The real do-nothing guy 5624 pipe_class empty( ) %{ 5625 instruction_count(0); 5626 %} 5627 5628 // Define the class for the Nop node 5629 define %{ 5630 MachNop = empty; 5631 %} 5632 5633 %} 5634 5635 //----------INSTRUCTIONS------------------------------------------------------- 5636 // 5637 // match -- States which machine-independent subtree may be replaced 5638 // by this instruction. 5639 // ins_cost -- The estimated cost of this instruction is used by instruction 5640 // selection to identify a minimum cost tree of machine 5641 // instructions that matches a tree of machine-independent 5642 // instructions. 5643 // format -- A string providing the disassembly for this instruction. 5644 // The value of an instruction's operand may be inserted 5645 // by referring to it with a '$' prefix. 5646 // opcode -- Three instruction opcodes may be provided. These are referred 5647 // to within an encode class as $primary, $secondary, and $tertiary 5648 // respectively. The primary opcode is commonly used to 5649 // indicate the type of machine instruction, while secondary 5650 // and tertiary are often used for prefix options or addressing 5651 // modes. 5652 // ins_encode -- A list of encode classes with parameters. The encode class 5653 // name must have been defined in an 'enc_class' specification 5654 // in the encode section of the architecture description. 5655 5656 //----------BSWAP-Instruction-------------------------------------------------- 5657 instruct bytes_reverse_int(eRegI dst) %{ 5658 match(Set dst (ReverseBytesI dst)); 5659 5660 format %{ "BSWAP $dst" %} 5661 opcode(0x0F, 0xC8); 5662 ins_encode( OpcP, OpcSReg(dst) ); 5663 ins_pipe( ialu_reg ); 5664 %} 5665 5666 instruct bytes_reverse_long(eRegL dst) %{ 5667 match(Set dst (ReverseBytesL dst)); 5668 5669 format %{ "BSWAP $dst.lo\n\t" 5670 "BSWAP $dst.hi\n\t" 5671 "XCHG $dst.lo $dst.hi" %} 5672 5673 ins_cost(125); 5674 ins_encode( bswap_long_bytes(dst) ); 5675 ins_pipe( ialu_reg_reg); 5676 %} 5677 5678 instruct bytes_reverse_unsigned_short(eRegI dst) %{ 5679 match(Set dst (ReverseBytesUS dst)); 5680 5681 format %{ "BSWAP $dst\n\t" 5682 "SHR $dst,16\n\t" %} 5683 ins_encode %{ 5684 __ bswapl($dst$$Register); 5685 __ shrl($dst$$Register, 16); 5686 %} 5687 ins_pipe( ialu_reg ); 5688 %} 5689 5690 instruct bytes_reverse_short(eRegI dst) %{ 5691 match(Set dst (ReverseBytesS dst)); 5692 5693 format %{ "BSWAP $dst\n\t" 5694 "SAR $dst,16\n\t" %} 5695 ins_encode %{ 5696 __ bswapl($dst$$Register); 5697 __ sarl($dst$$Register, 16); 5698 %} 5699 ins_pipe( ialu_reg ); 5700 %} 5701 5702 5703 //---------- Zeros Count Instructions ------------------------------------------ 5704 5705 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ 5706 predicate(UseCountLeadingZerosInstruction); 5707 match(Set dst (CountLeadingZerosI src)); 5708 effect(KILL cr); 5709 5710 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} 5711 ins_encode %{ 5712 __ lzcntl($dst$$Register, $src$$Register); 5713 %} 5714 ins_pipe(ialu_reg); 5715 %} 5716 5717 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ 5718 predicate(!UseCountLeadingZerosInstruction); 5719 match(Set dst (CountLeadingZerosI src)); 5720 effect(KILL cr); 5721 5722 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" 5723 "JNZ skip\n\t" 5724 "MOV $dst, -1\n" 5725 "skip:\n\t" 5726 "NEG $dst\n\t" 5727 "ADD $dst, 31" %} 5728 ins_encode %{ 5729 Register Rdst = $dst$$Register; 5730 Register Rsrc = $src$$Register; 5731 Label skip; 5732 __ bsrl(Rdst, Rsrc); 5733 __ jccb(Assembler::notZero, skip); 5734 __ movl(Rdst, -1); 5735 __ bind(skip); 5736 __ negl(Rdst); 5737 __ addl(Rdst, BitsPerInt - 1); 5738 %} 5739 ins_pipe(ialu_reg); 5740 %} 5741 5742 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ 5743 predicate(UseCountLeadingZerosInstruction); 5744 match(Set dst (CountLeadingZerosL src)); 5745 effect(TEMP dst, KILL cr); 5746 5747 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" 5748 "JNC done\n\t" 5749 "LZCNT $dst, $src.lo\n\t" 5750 "ADD $dst, 32\n" 5751 "done:" %} 5752 ins_encode %{ 5753 Register Rdst = $dst$$Register; 5754 Register Rsrc = $src$$Register; 5755 Label done; 5756 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); 5757 __ jccb(Assembler::carryClear, done); 5758 __ lzcntl(Rdst, Rsrc); 5759 __ addl(Rdst, BitsPerInt); 5760 __ bind(done); 5761 %} 5762 ins_pipe(ialu_reg); 5763 %} 5764 5765 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ 5766 predicate(!UseCountLeadingZerosInstruction); 5767 match(Set dst (CountLeadingZerosL src)); 5768 effect(TEMP dst, KILL cr); 5769 5770 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" 5771 "JZ msw_is_zero\n\t" 5772 "ADD $dst, 32\n\t" 5773 "JMP not_zero\n" 5774 "msw_is_zero:\n\t" 5775 "BSR $dst, $src.lo\n\t" 5776 "JNZ not_zero\n\t" 5777 "MOV $dst, -1\n" 5778 "not_zero:\n\t" 5779 "NEG $dst\n\t" 5780 "ADD $dst, 63\n" %} 5781 ins_encode %{ 5782 Register Rdst = $dst$$Register; 5783 Register Rsrc = $src$$Register; 5784 Label msw_is_zero; 5785 Label not_zero; 5786 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); 5787 __ jccb(Assembler::zero, msw_is_zero); 5788 __ addl(Rdst, BitsPerInt); 5789 __ jmpb(not_zero); 5790 __ bind(msw_is_zero); 5791 __ bsrl(Rdst, Rsrc); 5792 __ jccb(Assembler::notZero, not_zero); 5793 __ movl(Rdst, -1); 5794 __ bind(not_zero); 5795 __ negl(Rdst); 5796 __ addl(Rdst, BitsPerLong - 1); 5797 %} 5798 ins_pipe(ialu_reg); 5799 %} 5800 5801 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ 5802 match(Set dst (CountTrailingZerosI src)); 5803 effect(KILL cr); 5804 5805 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" 5806 "JNZ done\n\t" 5807 "MOV $dst, 32\n" 5808 "done:" %} 5809 ins_encode %{ 5810 Register Rdst = $dst$$Register; 5811 Label done; 5812 __ bsfl(Rdst, $src$$Register); 5813 __ jccb(Assembler::notZero, done); 5814 __ movl(Rdst, BitsPerInt); 5815 __ bind(done); 5816 %} 5817 ins_pipe(ialu_reg); 5818 %} 5819 5820 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ 5821 match(Set dst (CountTrailingZerosL src)); 5822 effect(TEMP dst, KILL cr); 5823 5824 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" 5825 "JNZ done\n\t" 5826 "BSF $dst, $src.hi\n\t" 5827 "JNZ msw_not_zero\n\t" 5828 "MOV $dst, 32\n" 5829 "msw_not_zero:\n\t" 5830 "ADD $dst, 32\n" 5831 "done:" %} 5832 ins_encode %{ 5833 Register Rdst = $dst$$Register; 5834 Register Rsrc = $src$$Register; 5835 Label msw_not_zero; 5836 Label done; 5837 __ bsfl(Rdst, Rsrc); 5838 __ jccb(Assembler::notZero, done); 5839 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); 5840 __ jccb(Assembler::notZero, msw_not_zero); 5841 __ movl(Rdst, BitsPerInt); 5842 __ bind(msw_not_zero); 5843 __ addl(Rdst, BitsPerInt); 5844 __ bind(done); 5845 %} 5846 ins_pipe(ialu_reg); 5847 %} 5848 5849 5850 //---------- Population Count Instructions ------------------------------------- 5851 5852 instruct popCountI(eRegI dst, eRegI src) %{ 5853 predicate(UsePopCountInstruction); 5854 match(Set dst (PopCountI src)); 5855 5856 format %{ "POPCNT $dst, $src" %} 5857 ins_encode %{ 5858 __ popcntl($dst$$Register, $src$$Register); 5859 %} 5860 ins_pipe(ialu_reg); 5861 %} 5862 5863 instruct popCountI_mem(eRegI dst, memory mem) %{ 5864 predicate(UsePopCountInstruction); 5865 match(Set dst (PopCountI (LoadI mem))); 5866 5867 format %{ "POPCNT $dst, $mem" %} 5868 ins_encode %{ 5869 __ popcntl($dst$$Register, $mem$$Address); 5870 %} 5871 ins_pipe(ialu_reg); 5872 %} 5873 5874 // Note: Long.bitCount(long) returns an int. 5875 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 5876 predicate(UsePopCountInstruction); 5877 match(Set dst (PopCountL src)); 5878 effect(KILL cr, TEMP tmp, TEMP dst); 5879 5880 format %{ "POPCNT $dst, $src.lo\n\t" 5881 "POPCNT $tmp, $src.hi\n\t" 5882 "ADD $dst, $tmp" %} 5883 ins_encode %{ 5884 __ popcntl($dst$$Register, $src$$Register); 5885 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); 5886 __ addl($dst$$Register, $tmp$$Register); 5887 %} 5888 ins_pipe(ialu_reg); 5889 %} 5890 5891 // Note: Long.bitCount(long) returns an int. 5892 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ 5893 predicate(UsePopCountInstruction); 5894 match(Set dst (PopCountL (LoadL mem))); 5895 effect(KILL cr, TEMP tmp, TEMP dst); 5896 5897 format %{ "POPCNT $dst, $mem\n\t" 5898 "POPCNT $tmp, $mem+4\n\t" 5899 "ADD $dst, $tmp" %} 5900 ins_encode %{ 5901 //__ popcntl($dst$$Register, $mem$$Address$$first); 5902 //__ popcntl($tmp$$Register, $mem$$Address$$second); 5903 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); 5904 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); 5905 __ addl($dst$$Register, $tmp$$Register); 5906 %} 5907 ins_pipe(ialu_reg); 5908 %} 5909 5910 5911 //----------Load/Store/Move Instructions--------------------------------------- 5912 //----------Load Instructions-------------------------------------------------- 5913 // Load Byte (8bit signed) 5914 instruct loadB(xRegI dst, memory mem) %{ 5915 match(Set dst (LoadB mem)); 5916 5917 ins_cost(125); 5918 format %{ "MOVSX8 $dst,$mem\t# byte" %} 5919 5920 ins_encode %{ 5921 __ movsbl($dst$$Register, $mem$$Address); 5922 %} 5923 5924 ins_pipe(ialu_reg_mem); 5925 %} 5926 5927 // Load Byte (8bit signed) into Long Register 5928 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ 5929 match(Set dst (ConvI2L (LoadB mem))); 5930 effect(KILL cr); 5931 5932 ins_cost(375); 5933 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" 5934 "MOV $dst.hi,$dst.lo\n\t" 5935 "SAR $dst.hi,7" %} 5936 5937 ins_encode %{ 5938 __ movsbl($dst$$Register, $mem$$Address); 5939 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 5940 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. 5941 %} 5942 5943 ins_pipe(ialu_reg_mem); 5944 %} 5945 5946 // Load Unsigned Byte (8bit UNsigned) 5947 instruct loadUB(xRegI dst, memory mem) %{ 5948 match(Set dst (LoadUB mem)); 5949 5950 ins_cost(125); 5951 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} 5952 5953 ins_encode %{ 5954 __ movzbl($dst$$Register, $mem$$Address); 5955 %} 5956 5957 ins_pipe(ialu_reg_mem); 5958 %} 5959 5960 // Load Unsigned Byte (8 bit UNsigned) into Long Register 5961 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ 5962 match(Set dst (ConvI2L (LoadUB mem))); 5963 effect(KILL cr); 5964 5965 ins_cost(250); 5966 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" 5967 "XOR $dst.hi,$dst.hi" %} 5968 5969 ins_encode %{ 5970 Register Rdst = $dst$$Register; 5971 __ movzbl(Rdst, $mem$$Address); 5972 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5973 %} 5974 5975 ins_pipe(ialu_reg_mem); 5976 %} 5977 5978 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register 5979 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ 5980 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5981 effect(KILL cr); 5982 5983 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" 5984 "XOR $dst.hi,$dst.hi\n\t" 5985 "AND $dst.lo,$mask" %} 5986 ins_encode %{ 5987 Register Rdst = $dst$$Register; 5988 __ movzbl(Rdst, $mem$$Address); 5989 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5990 __ andl(Rdst, $mask$$constant); 5991 %} 5992 ins_pipe(ialu_reg_mem); 5993 %} 5994 5995 // Load Short (16bit signed) 5996 instruct loadS(eRegI dst, memory mem) %{ 5997 match(Set dst (LoadS mem)); 5998 5999 ins_cost(125); 6000 format %{ "MOVSX $dst,$mem\t# short" %} 6001 6002 ins_encode %{ 6003 __ movswl($dst$$Register, $mem$$Address); 6004 %} 6005 6006 ins_pipe(ialu_reg_mem); 6007 %} 6008 6009 // Load Short (16 bit signed) to Byte (8 bit signed) 6010 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 6011 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 6012 6013 ins_cost(125); 6014 format %{ "MOVSX $dst, $mem\t# short -> byte" %} 6015 ins_encode %{ 6016 __ movsbl($dst$$Register, $mem$$Address); 6017 %} 6018 ins_pipe(ialu_reg_mem); 6019 %} 6020 6021 // Load Short (16bit signed) into Long Register 6022 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6023 match(Set dst (ConvI2L (LoadS mem))); 6024 effect(KILL cr); 6025 6026 ins_cost(375); 6027 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" 6028 "MOV $dst.hi,$dst.lo\n\t" 6029 "SAR $dst.hi,15" %} 6030 6031 ins_encode %{ 6032 __ movswl($dst$$Register, $mem$$Address); 6033 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 6034 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. 6035 %} 6036 6037 ins_pipe(ialu_reg_mem); 6038 %} 6039 6040 // Load Unsigned Short/Char (16bit unsigned) 6041 instruct loadUS(eRegI dst, memory mem) %{ 6042 match(Set dst (LoadUS mem)); 6043 6044 ins_cost(125); 6045 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} 6046 6047 ins_encode %{ 6048 __ movzwl($dst$$Register, $mem$$Address); 6049 %} 6050 6051 ins_pipe(ialu_reg_mem); 6052 %} 6053 6054 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 6055 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 6056 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 6057 6058 ins_cost(125); 6059 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} 6060 ins_encode %{ 6061 __ movsbl($dst$$Register, $mem$$Address); 6062 %} 6063 ins_pipe(ialu_reg_mem); 6064 %} 6065 6066 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register 6067 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6068 match(Set dst (ConvI2L (LoadUS mem))); 6069 effect(KILL cr); 6070 6071 ins_cost(250); 6072 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" 6073 "XOR $dst.hi,$dst.hi" %} 6074 6075 ins_encode %{ 6076 __ movzwl($dst$$Register, $mem$$Address); 6077 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6078 %} 6079 6080 ins_pipe(ialu_reg_mem); 6081 %} 6082 6083 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register 6084 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ 6085 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 6086 effect(KILL cr); 6087 6088 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" 6089 "XOR $dst.hi,$dst.hi" %} 6090 ins_encode %{ 6091 Register Rdst = $dst$$Register; 6092 __ movzbl(Rdst, $mem$$Address); 6093 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6094 %} 6095 ins_pipe(ialu_reg_mem); 6096 %} 6097 6098 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register 6099 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ 6100 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 6101 effect(KILL cr); 6102 6103 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" 6104 "XOR $dst.hi,$dst.hi\n\t" 6105 "AND $dst.lo,$mask" %} 6106 ins_encode %{ 6107 Register Rdst = $dst$$Register; 6108 __ movzwl(Rdst, $mem$$Address); 6109 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6110 __ andl(Rdst, $mask$$constant); 6111 %} 6112 ins_pipe(ialu_reg_mem); 6113 %} 6114 6115 // Load Integer 6116 instruct loadI(eRegI dst, memory mem) %{ 6117 match(Set dst (LoadI mem)); 6118 6119 ins_cost(125); 6120 format %{ "MOV $dst,$mem\t# int" %} 6121 6122 ins_encode %{ 6123 __ movl($dst$$Register, $mem$$Address); 6124 %} 6125 6126 ins_pipe(ialu_reg_mem); 6127 %} 6128 6129 // Load Integer (32 bit signed) to Byte (8 bit signed) 6130 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ 6131 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 6132 6133 ins_cost(125); 6134 format %{ "MOVSX $dst, $mem\t# int -> byte" %} 6135 ins_encode %{ 6136 __ movsbl($dst$$Register, $mem$$Address); 6137 %} 6138 ins_pipe(ialu_reg_mem); 6139 %} 6140 6141 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) 6142 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ 6143 match(Set dst (AndI (LoadI mem) mask)); 6144 6145 ins_cost(125); 6146 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} 6147 ins_encode %{ 6148 __ movzbl($dst$$Register, $mem$$Address); 6149 %} 6150 ins_pipe(ialu_reg_mem); 6151 %} 6152 6153 // Load Integer (32 bit signed) to Short (16 bit signed) 6154 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ 6155 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 6156 6157 ins_cost(125); 6158 format %{ "MOVSX $dst, $mem\t# int -> short" %} 6159 ins_encode %{ 6160 __ movswl($dst$$Register, $mem$$Address); 6161 %} 6162 ins_pipe(ialu_reg_mem); 6163 %} 6164 6165 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) 6166 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ 6167 match(Set dst (AndI (LoadI mem) mask)); 6168 6169 ins_cost(125); 6170 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} 6171 ins_encode %{ 6172 __ movzwl($dst$$Register, $mem$$Address); 6173 %} 6174 ins_pipe(ialu_reg_mem); 6175 %} 6176 6177 // Load Integer into Long Register 6178 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6179 match(Set dst (ConvI2L (LoadI mem))); 6180 effect(KILL cr); 6181 6182 ins_cost(375); 6183 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" 6184 "MOV $dst.hi,$dst.lo\n\t" 6185 "SAR $dst.hi,31" %} 6186 6187 ins_encode %{ 6188 __ movl($dst$$Register, $mem$$Address); 6189 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 6190 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); 6191 %} 6192 6193 ins_pipe(ialu_reg_mem); 6194 %} 6195 6196 // Load Integer with mask 0xFF into Long Register 6197 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ 6198 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6199 effect(KILL cr); 6200 6201 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" 6202 "XOR $dst.hi,$dst.hi" %} 6203 ins_encode %{ 6204 Register Rdst = $dst$$Register; 6205 __ movzbl(Rdst, $mem$$Address); 6206 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6207 %} 6208 ins_pipe(ialu_reg_mem); 6209 %} 6210 6211 // Load Integer with mask 0xFFFF into Long Register 6212 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ 6213 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6214 effect(KILL cr); 6215 6216 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" 6217 "XOR $dst.hi,$dst.hi" %} 6218 ins_encode %{ 6219 Register Rdst = $dst$$Register; 6220 __ movzwl(Rdst, $mem$$Address); 6221 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6222 %} 6223 ins_pipe(ialu_reg_mem); 6224 %} 6225 6226 // Load Integer with 32-bit mask into Long Register 6227 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ 6228 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6229 effect(KILL cr); 6230 6231 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" 6232 "XOR $dst.hi,$dst.hi\n\t" 6233 "AND $dst.lo,$mask" %} 6234 ins_encode %{ 6235 Register Rdst = $dst$$Register; 6236 __ movl(Rdst, $mem$$Address); 6237 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6238 __ andl(Rdst, $mask$$constant); 6239 %} 6240 ins_pipe(ialu_reg_mem); 6241 %} 6242 6243 // Load Unsigned Integer into Long Register 6244 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6245 match(Set dst (LoadUI2L mem)); 6246 effect(KILL cr); 6247 6248 ins_cost(250); 6249 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" 6250 "XOR $dst.hi,$dst.hi" %} 6251 6252 ins_encode %{ 6253 __ movl($dst$$Register, $mem$$Address); 6254 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6255 %} 6256 6257 ins_pipe(ialu_reg_mem); 6258 %} 6259 6260 // Load Long. Cannot clobber address while loading, so restrict address 6261 // register to ESI 6262 instruct loadL(eRegL dst, load_long_memory mem) %{ 6263 predicate(!((LoadLNode*)n)->require_atomic_access()); 6264 match(Set dst (LoadL mem)); 6265 6266 ins_cost(250); 6267 format %{ "MOV $dst.lo,$mem\t# long\n\t" 6268 "MOV $dst.hi,$mem+4" %} 6269 6270 ins_encode %{ 6271 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); 6272 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); 6273 __ movl($dst$$Register, Amemlo); 6274 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); 6275 %} 6276 6277 ins_pipe(ialu_reg_long_mem); 6278 %} 6279 6280 // Volatile Load Long. Must be atomic, so do 64-bit FILD 6281 // then store it down to the stack and reload on the int 6282 // side. 6283 instruct loadL_volatile(stackSlotL dst, memory mem) %{ 6284 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); 6285 match(Set dst (LoadL mem)); 6286 6287 ins_cost(200); 6288 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 6289 "FISTp $dst" %} 6290 ins_encode(enc_loadL_volatile(mem,dst)); 6291 ins_pipe( fpu_reg_mem ); 6292 %} 6293 6294 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ 6295 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6296 match(Set dst (LoadL mem)); 6297 effect(TEMP tmp); 6298 ins_cost(180); 6299 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6300 "MOVSD $dst,$tmp" %} 6301 ins_encode %{ 6302 __ movdbl($tmp$$XMMRegister, $mem$$Address); 6303 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); 6304 %} 6305 ins_pipe( pipe_slow ); 6306 %} 6307 6308 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ 6309 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6310 match(Set dst (LoadL mem)); 6311 effect(TEMP tmp); 6312 ins_cost(160); 6313 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6314 "MOVD $dst.lo,$tmp\n\t" 6315 "PSRLQ $tmp,32\n\t" 6316 "MOVD $dst.hi,$tmp" %} 6317 ins_encode %{ 6318 __ movdbl($tmp$$XMMRegister, $mem$$Address); 6319 __ movdl($dst$$Register, $tmp$$XMMRegister); 6320 __ psrlq($tmp$$XMMRegister, 32); 6321 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); 6322 %} 6323 ins_pipe( pipe_slow ); 6324 %} 6325 6326 // Load Range 6327 instruct loadRange(eRegI dst, memory mem) %{ 6328 match(Set dst (LoadRange mem)); 6329 6330 ins_cost(125); 6331 format %{ "MOV $dst,$mem" %} 6332 opcode(0x8B); 6333 ins_encode( OpcP, RegMem(dst,mem)); 6334 ins_pipe( ialu_reg_mem ); 6335 %} 6336 6337 6338 // Load Pointer 6339 instruct loadP(eRegP dst, memory mem) %{ 6340 match(Set dst (LoadP mem)); 6341 6342 ins_cost(125); 6343 format %{ "MOV $dst,$mem" %} 6344 opcode(0x8B); 6345 ins_encode( OpcP, RegMem(dst,mem)); 6346 ins_pipe( ialu_reg_mem ); 6347 %} 6348 6349 // Load Klass Pointer 6350 instruct loadKlass(eRegP dst, memory mem) %{ 6351 match(Set dst (LoadKlass mem)); 6352 6353 ins_cost(125); 6354 format %{ "MOV $dst,$mem" %} 6355 opcode(0x8B); 6356 ins_encode( OpcP, RegMem(dst,mem)); 6357 ins_pipe( ialu_reg_mem ); 6358 %} 6359 6360 // Load Double 6361 instruct loadDPR(regDPR dst, memory mem) %{ 6362 predicate(UseSSE<=1); 6363 match(Set dst (LoadD mem)); 6364 6365 ins_cost(150); 6366 format %{ "FLD_D ST,$mem\n\t" 6367 "FSTP $dst" %} 6368 opcode(0xDD); /* DD /0 */ 6369 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6370 Pop_Reg_DPR(dst) ); 6371 ins_pipe( fpu_reg_mem ); 6372 %} 6373 6374 // Load Double to XMM 6375 instruct loadD(regD dst, memory mem) %{ 6376 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 6377 match(Set dst (LoadD mem)); 6378 ins_cost(145); 6379 format %{ "MOVSD $dst,$mem" %} 6380 ins_encode %{ 6381 __ movdbl ($dst$$XMMRegister, $mem$$Address); 6382 %} 6383 ins_pipe( pipe_slow ); 6384 %} 6385 6386 instruct loadD_partial(regD dst, memory mem) %{ 6387 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 6388 match(Set dst (LoadD mem)); 6389 ins_cost(145); 6390 format %{ "MOVLPD $dst,$mem" %} 6391 ins_encode %{ 6392 __ movdbl ($dst$$XMMRegister, $mem$$Address); 6393 %} 6394 ins_pipe( pipe_slow ); 6395 %} 6396 6397 // Load to XMM register (single-precision floating point) 6398 // MOVSS instruction 6399 instruct loadF(regF dst, memory mem) %{ 6400 predicate(UseSSE>=1); 6401 match(Set dst (LoadF mem)); 6402 ins_cost(145); 6403 format %{ "MOVSS $dst,$mem" %} 6404 ins_encode %{ 6405 __ movflt ($dst$$XMMRegister, $mem$$Address); 6406 %} 6407 ins_pipe( pipe_slow ); 6408 %} 6409 6410 // Load Float 6411 instruct loadFPR(regFPR dst, memory mem) %{ 6412 predicate(UseSSE==0); 6413 match(Set dst (LoadF mem)); 6414 6415 ins_cost(150); 6416 format %{ "FLD_S ST,$mem\n\t" 6417 "FSTP $dst" %} 6418 opcode(0xD9); /* D9 /0 */ 6419 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6420 Pop_Reg_FPR(dst) ); 6421 ins_pipe( fpu_reg_mem ); 6422 %} 6423 6424 // Load Aligned Packed Byte to XMM register 6425 instruct loadA8B(regD dst, memory mem) %{ 6426 predicate(UseSSE>=1); 6427 match(Set dst (Load8B mem)); 6428 ins_cost(125); 6429 format %{ "MOVQ $dst,$mem\t! packed8B" %} 6430 ins_encode %{ 6431 __ movq($dst$$XMMRegister, $mem$$Address); 6432 %} 6433 ins_pipe( pipe_slow ); 6434 %} 6435 6436 // Load Aligned Packed Short to XMM register 6437 instruct loadA4S(regD dst, memory mem) %{ 6438 predicate(UseSSE>=1); 6439 match(Set dst (Load4S mem)); 6440 ins_cost(125); 6441 format %{ "MOVQ $dst,$mem\t! packed4S" %} 6442 ins_encode %{ 6443 __ movq($dst$$XMMRegister, $mem$$Address); 6444 %} 6445 ins_pipe( pipe_slow ); 6446 %} 6447 6448 // Load Aligned Packed Char to XMM register 6449 instruct loadA4C(regD dst, memory mem) %{ 6450 predicate(UseSSE>=1); 6451 match(Set dst (Load4C mem)); 6452 ins_cost(125); 6453 format %{ "MOVQ $dst,$mem\t! packed4C" %} 6454 ins_encode %{ 6455 __ movq($dst$$XMMRegister, $mem$$Address); 6456 %} 6457 ins_pipe( pipe_slow ); 6458 %} 6459 6460 // Load Aligned Packed Integer to XMM register 6461 instruct load2IU(regD dst, memory mem) %{ 6462 predicate(UseSSE>=1); 6463 match(Set dst (Load2I mem)); 6464 ins_cost(125); 6465 format %{ "MOVQ $dst,$mem\t! packed2I" %} 6466 ins_encode %{ 6467 __ movq($dst$$XMMRegister, $mem$$Address); 6468 %} 6469 ins_pipe( pipe_slow ); 6470 %} 6471 6472 // Load Aligned Packed Single to XMM 6473 instruct loadA2F(regD dst, memory mem) %{ 6474 predicate(UseSSE>=1); 6475 match(Set dst (Load2F mem)); 6476 ins_cost(145); 6477 format %{ "MOVQ $dst,$mem\t! packed2F" %} 6478 ins_encode %{ 6479 __ movq($dst$$XMMRegister, $mem$$Address); 6480 %} 6481 ins_pipe( pipe_slow ); 6482 %} 6483 6484 // Load Effective Address 6485 instruct leaP8(eRegP dst, indOffset8 mem) %{ 6486 match(Set dst mem); 6487 6488 ins_cost(110); 6489 format %{ "LEA $dst,$mem" %} 6490 opcode(0x8D); 6491 ins_encode( OpcP, RegMem(dst,mem)); 6492 ins_pipe( ialu_reg_reg_fat ); 6493 %} 6494 6495 instruct leaP32(eRegP dst, indOffset32 mem) %{ 6496 match(Set dst mem); 6497 6498 ins_cost(110); 6499 format %{ "LEA $dst,$mem" %} 6500 opcode(0x8D); 6501 ins_encode( OpcP, RegMem(dst,mem)); 6502 ins_pipe( ialu_reg_reg_fat ); 6503 %} 6504 6505 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ 6506 match(Set dst mem); 6507 6508 ins_cost(110); 6509 format %{ "LEA $dst,$mem" %} 6510 opcode(0x8D); 6511 ins_encode( OpcP, RegMem(dst,mem)); 6512 ins_pipe( ialu_reg_reg_fat ); 6513 %} 6514 6515 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ 6516 match(Set dst mem); 6517 6518 ins_cost(110); 6519 format %{ "LEA $dst,$mem" %} 6520 opcode(0x8D); 6521 ins_encode( OpcP, RegMem(dst,mem)); 6522 ins_pipe( ialu_reg_reg_fat ); 6523 %} 6524 6525 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ 6526 match(Set dst mem); 6527 6528 ins_cost(110); 6529 format %{ "LEA $dst,$mem" %} 6530 opcode(0x8D); 6531 ins_encode( OpcP, RegMem(dst,mem)); 6532 ins_pipe( ialu_reg_reg_fat ); 6533 %} 6534 6535 // Load Constant 6536 instruct loadConI(eRegI dst, immI src) %{ 6537 match(Set dst src); 6538 6539 format %{ "MOV $dst,$src" %} 6540 ins_encode( LdImmI(dst, src) ); 6541 ins_pipe( ialu_reg_fat ); 6542 %} 6543 6544 // Load Constant zero 6545 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ 6546 match(Set dst src); 6547 effect(KILL cr); 6548 6549 ins_cost(50); 6550 format %{ "XOR $dst,$dst" %} 6551 opcode(0x33); /* + rd */ 6552 ins_encode( OpcP, RegReg( dst, dst ) ); 6553 ins_pipe( ialu_reg ); 6554 %} 6555 6556 instruct loadConP(eRegP dst, immP src) %{ 6557 match(Set dst src); 6558 6559 format %{ "MOV $dst,$src" %} 6560 opcode(0xB8); /* + rd */ 6561 ins_encode( LdImmP(dst, src) ); 6562 ins_pipe( ialu_reg_fat ); 6563 %} 6564 6565 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ 6566 match(Set dst src); 6567 effect(KILL cr); 6568 ins_cost(200); 6569 format %{ "MOV $dst.lo,$src.lo\n\t" 6570 "MOV $dst.hi,$src.hi" %} 6571 opcode(0xB8); 6572 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); 6573 ins_pipe( ialu_reg_long_fat ); 6574 %} 6575 6576 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ 6577 match(Set dst src); 6578 effect(KILL cr); 6579 ins_cost(150); 6580 format %{ "XOR $dst.lo,$dst.lo\n\t" 6581 "XOR $dst.hi,$dst.hi" %} 6582 opcode(0x33,0x33); 6583 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); 6584 ins_pipe( ialu_reg_long ); 6585 %} 6586 6587 // The instruction usage is guarded by predicate in operand immFPR(). 6588 instruct loadConFPR(regFPR dst, immFPR con) %{ 6589 match(Set dst con); 6590 ins_cost(125); 6591 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" 6592 "FSTP $dst" %} 6593 ins_encode %{ 6594 __ fld_s($constantaddress($con)); 6595 __ fstp_d($dst$$reg); 6596 %} 6597 ins_pipe(fpu_reg_con); 6598 %} 6599 6600 // The instruction usage is guarded by predicate in operand immFPR0(). 6601 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ 6602 match(Set dst con); 6603 ins_cost(125); 6604 format %{ "FLDZ ST\n\t" 6605 "FSTP $dst" %} 6606 ins_encode %{ 6607 __ fldz(); 6608 __ fstp_d($dst$$reg); 6609 %} 6610 ins_pipe(fpu_reg_con); 6611 %} 6612 6613 // The instruction usage is guarded by predicate in operand immFPR1(). 6614 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ 6615 match(Set dst con); 6616 ins_cost(125); 6617 format %{ "FLD1 ST\n\t" 6618 "FSTP $dst" %} 6619 ins_encode %{ 6620 __ fld1(); 6621 __ fstp_d($dst$$reg); 6622 %} 6623 ins_pipe(fpu_reg_con); 6624 %} 6625 6626 // The instruction usage is guarded by predicate in operand immF(). 6627 instruct loadConF(regF dst, immF con) %{ 6628 match(Set dst con); 6629 ins_cost(125); 6630 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} 6631 ins_encode %{ 6632 __ movflt($dst$$XMMRegister, $constantaddress($con)); 6633 %} 6634 ins_pipe(pipe_slow); 6635 %} 6636 6637 // The instruction usage is guarded by predicate in operand immF0(). 6638 instruct loadConF0(regF dst, immF0 src) %{ 6639 match(Set dst src); 6640 ins_cost(100); 6641 format %{ "XORPS $dst,$dst\t# float 0.0" %} 6642 ins_encode %{ 6643 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); 6644 %} 6645 ins_pipe(pipe_slow); 6646 %} 6647 6648 // The instruction usage is guarded by predicate in operand immDPR(). 6649 instruct loadConDPR(regDPR dst, immDPR con) %{ 6650 match(Set dst con); 6651 ins_cost(125); 6652 6653 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" 6654 "FSTP $dst" %} 6655 ins_encode %{ 6656 __ fld_d($constantaddress($con)); 6657 __ fstp_d($dst$$reg); 6658 %} 6659 ins_pipe(fpu_reg_con); 6660 %} 6661 6662 // The instruction usage is guarded by predicate in operand immDPR0(). 6663 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ 6664 match(Set dst con); 6665 ins_cost(125); 6666 6667 format %{ "FLDZ ST\n\t" 6668 "FSTP $dst" %} 6669 ins_encode %{ 6670 __ fldz(); 6671 __ fstp_d($dst$$reg); 6672 %} 6673 ins_pipe(fpu_reg_con); 6674 %} 6675 6676 // The instruction usage is guarded by predicate in operand immDPR1(). 6677 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ 6678 match(Set dst con); 6679 ins_cost(125); 6680 6681 format %{ "FLD1 ST\n\t" 6682 "FSTP $dst" %} 6683 ins_encode %{ 6684 __ fld1(); 6685 __ fstp_d($dst$$reg); 6686 %} 6687 ins_pipe(fpu_reg_con); 6688 %} 6689 6690 // The instruction usage is guarded by predicate in operand immD(). 6691 instruct loadConD(regD dst, immD con) %{ 6692 match(Set dst con); 6693 ins_cost(125); 6694 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} 6695 ins_encode %{ 6696 __ movdbl($dst$$XMMRegister, $constantaddress($con)); 6697 %} 6698 ins_pipe(pipe_slow); 6699 %} 6700 6701 // The instruction usage is guarded by predicate in operand immD0(). 6702 instruct loadConD0(regD dst, immD0 src) %{ 6703 match(Set dst src); 6704 ins_cost(100); 6705 format %{ "XORPD $dst,$dst\t# double 0.0" %} 6706 ins_encode %{ 6707 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); 6708 %} 6709 ins_pipe( pipe_slow ); 6710 %} 6711 6712 // Load Stack Slot 6713 instruct loadSSI(eRegI dst, stackSlotI src) %{ 6714 match(Set dst src); 6715 ins_cost(125); 6716 6717 format %{ "MOV $dst,$src" %} 6718 opcode(0x8B); 6719 ins_encode( OpcP, RegMem(dst,src)); 6720 ins_pipe( ialu_reg_mem ); 6721 %} 6722 6723 instruct loadSSL(eRegL dst, stackSlotL src) %{ 6724 match(Set dst src); 6725 6726 ins_cost(200); 6727 format %{ "MOV $dst,$src.lo\n\t" 6728 "MOV $dst+4,$src.hi" %} 6729 opcode(0x8B, 0x8B); 6730 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); 6731 ins_pipe( ialu_mem_long_reg ); 6732 %} 6733 6734 // Load Stack Slot 6735 instruct loadSSP(eRegP dst, stackSlotP src) %{ 6736 match(Set dst src); 6737 ins_cost(125); 6738 6739 format %{ "MOV $dst,$src" %} 6740 opcode(0x8B); 6741 ins_encode( OpcP, RegMem(dst,src)); 6742 ins_pipe( ialu_reg_mem ); 6743 %} 6744 6745 // Load Stack Slot 6746 instruct loadSSF(regFPR dst, stackSlotF src) %{ 6747 match(Set dst src); 6748 ins_cost(125); 6749 6750 format %{ "FLD_S $src\n\t" 6751 "FSTP $dst" %} 6752 opcode(0xD9); /* D9 /0, FLD m32real */ 6753 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6754 Pop_Reg_FPR(dst) ); 6755 ins_pipe( fpu_reg_mem ); 6756 %} 6757 6758 // Load Stack Slot 6759 instruct loadSSD(regDPR dst, stackSlotD src) %{ 6760 match(Set dst src); 6761 ins_cost(125); 6762 6763 format %{ "FLD_D $src\n\t" 6764 "FSTP $dst" %} 6765 opcode(0xDD); /* DD /0, FLD m64real */ 6766 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6767 Pop_Reg_DPR(dst) ); 6768 ins_pipe( fpu_reg_mem ); 6769 %} 6770 6771 // Prefetch instructions. 6772 // Must be safe to execute with invalid address (cannot fault). 6773 6774 instruct prefetchr0( memory mem ) %{ 6775 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); 6776 match(PrefetchRead mem); 6777 ins_cost(0); 6778 size(0); 6779 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 6780 ins_encode(); 6781 ins_pipe(empty); 6782 %} 6783 6784 instruct prefetchr( memory mem ) %{ 6785 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); 6786 match(PrefetchRead mem); 6787 ins_cost(100); 6788 6789 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 6790 ins_encode %{ 6791 __ prefetchr($mem$$Address); 6792 %} 6793 ins_pipe(ialu_mem); 6794 %} 6795 6796 instruct prefetchrNTA( memory mem ) %{ 6797 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 6798 match(PrefetchRead mem); 6799 ins_cost(100); 6800 6801 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 6802 ins_encode %{ 6803 __ prefetchnta($mem$$Address); 6804 %} 6805 ins_pipe(ialu_mem); 6806 %} 6807 6808 instruct prefetchrT0( memory mem ) %{ 6809 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 6810 match(PrefetchRead mem); 6811 ins_cost(100); 6812 6813 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 6814 ins_encode %{ 6815 __ prefetcht0($mem$$Address); 6816 %} 6817 ins_pipe(ialu_mem); 6818 %} 6819 6820 instruct prefetchrT2( memory mem ) %{ 6821 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 6822 match(PrefetchRead mem); 6823 ins_cost(100); 6824 6825 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 6826 ins_encode %{ 6827 __ prefetcht2($mem$$Address); 6828 %} 6829 ins_pipe(ialu_mem); 6830 %} 6831 6832 instruct prefetchw0( memory mem ) %{ 6833 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); 6834 match(PrefetchWrite mem); 6835 ins_cost(0); 6836 size(0); 6837 format %{ "Prefetch (non-SSE is empty encoding)" %} 6838 ins_encode(); 6839 ins_pipe(empty); 6840 %} 6841 6842 instruct prefetchw( memory mem ) %{ 6843 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); 6844 match( PrefetchWrite mem ); 6845 ins_cost(100); 6846 6847 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 6848 ins_encode %{ 6849 __ prefetchw($mem$$Address); 6850 %} 6851 ins_pipe(ialu_mem); 6852 %} 6853 6854 instruct prefetchwNTA( memory mem ) %{ 6855 predicate(UseSSE>=1); 6856 match(PrefetchWrite mem); 6857 ins_cost(100); 6858 6859 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 6860 ins_encode %{ 6861 __ prefetchnta($mem$$Address); 6862 %} 6863 ins_pipe(ialu_mem); 6864 %} 6865 6866 // Prefetch instructions for allocation. 6867 6868 instruct prefetchAlloc0( memory mem ) %{ 6869 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); 6870 match(PrefetchAllocation mem); 6871 ins_cost(0); 6872 size(0); 6873 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} 6874 ins_encode(); 6875 ins_pipe(empty); 6876 %} 6877 6878 instruct prefetchAlloc( memory mem ) %{ 6879 predicate(AllocatePrefetchInstr==3); 6880 match( PrefetchAllocation mem ); 6881 ins_cost(100); 6882 6883 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} 6884 ins_encode %{ 6885 __ prefetchw($mem$$Address); 6886 %} 6887 ins_pipe(ialu_mem); 6888 %} 6889 6890 instruct prefetchAllocNTA( memory mem ) %{ 6891 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 6892 match(PrefetchAllocation mem); 6893 ins_cost(100); 6894 6895 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} 6896 ins_encode %{ 6897 __ prefetchnta($mem$$Address); 6898 %} 6899 ins_pipe(ialu_mem); 6900 %} 6901 6902 instruct prefetchAllocT0( memory mem ) %{ 6903 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 6904 match(PrefetchAllocation mem); 6905 ins_cost(100); 6906 6907 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} 6908 ins_encode %{ 6909 __ prefetcht0($mem$$Address); 6910 %} 6911 ins_pipe(ialu_mem); 6912 %} 6913 6914 instruct prefetchAllocT2( memory mem ) %{ 6915 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 6916 match(PrefetchAllocation mem); 6917 ins_cost(100); 6918 6919 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} 6920 ins_encode %{ 6921 __ prefetcht2($mem$$Address); 6922 %} 6923 ins_pipe(ialu_mem); 6924 %} 6925 6926 //----------Store Instructions------------------------------------------------- 6927 6928 // Store Byte 6929 instruct storeB(memory mem, xRegI src) %{ 6930 match(Set mem (StoreB mem src)); 6931 6932 ins_cost(125); 6933 format %{ "MOV8 $mem,$src" %} 6934 opcode(0x88); 6935 ins_encode( OpcP, RegMem( src, mem ) ); 6936 ins_pipe( ialu_mem_reg ); 6937 %} 6938 6939 // Store Char/Short 6940 instruct storeC(memory mem, eRegI src) %{ 6941 match(Set mem (StoreC mem src)); 6942 6943 ins_cost(125); 6944 format %{ "MOV16 $mem,$src" %} 6945 opcode(0x89, 0x66); 6946 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 6947 ins_pipe( ialu_mem_reg ); 6948 %} 6949 6950 // Store Integer 6951 instruct storeI(memory mem, eRegI src) %{ 6952 match(Set mem (StoreI mem src)); 6953 6954 ins_cost(125); 6955 format %{ "MOV $mem,$src" %} 6956 opcode(0x89); 6957 ins_encode( OpcP, RegMem( src, mem ) ); 6958 ins_pipe( ialu_mem_reg ); 6959 %} 6960 6961 // Store Long 6962 instruct storeL(long_memory mem, eRegL src) %{ 6963 predicate(!((StoreLNode*)n)->require_atomic_access()); 6964 match(Set mem (StoreL mem src)); 6965 6966 ins_cost(200); 6967 format %{ "MOV $mem,$src.lo\n\t" 6968 "MOV $mem+4,$src.hi" %} 6969 opcode(0x89, 0x89); 6970 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 6971 ins_pipe( ialu_mem_long_reg ); 6972 %} 6973 6974 // Store Long to Integer 6975 instruct storeL2I(memory mem, eRegL src) %{ 6976 match(Set mem (StoreI mem (ConvL2I src))); 6977 6978 format %{ "MOV $mem,$src.lo\t# long -> int" %} 6979 ins_encode %{ 6980 __ movl($mem$$Address, $src$$Register); 6981 %} 6982 ins_pipe(ialu_mem_reg); 6983 %} 6984 6985 // Volatile Store Long. Must be atomic, so move it into 6986 // the FP TOS and then do a 64-bit FIST. Has to probe the 6987 // target address before the store (for null-ptr checks) 6988 // so the memory operand is used twice in the encoding. 6989 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ 6990 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); 6991 match(Set mem (StoreL mem src)); 6992 effect( KILL cr ); 6993 ins_cost(400); 6994 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6995 "FILD $src\n\t" 6996 "FISTp $mem\t # 64-bit atomic volatile long store" %} 6997 opcode(0x3B); 6998 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); 6999 ins_pipe( fpu_reg_mem ); 7000 %} 7001 7002 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ 7003 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 7004 match(Set mem (StoreL mem src)); 7005 effect( TEMP tmp, KILL cr ); 7006 ins_cost(380); 7007 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7008 "MOVSD $tmp,$src\n\t" 7009 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 7010 ins_encode %{ 7011 __ cmpl(rax, $mem$$Address); 7012 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); 7013 __ movdbl($mem$$Address, $tmp$$XMMRegister); 7014 %} 7015 ins_pipe( pipe_slow ); 7016 %} 7017 7018 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ 7019 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 7020 match(Set mem (StoreL mem src)); 7021 effect( TEMP tmp2 , TEMP tmp, KILL cr ); 7022 ins_cost(360); 7023 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7024 "MOVD $tmp,$src.lo\n\t" 7025 "MOVD $tmp2,$src.hi\n\t" 7026 "PUNPCKLDQ $tmp,$tmp2\n\t" 7027 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 7028 ins_encode %{ 7029 __ cmpl(rax, $mem$$Address); 7030 __ movdl($tmp$$XMMRegister, $src$$Register); 7031 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); 7032 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); 7033 __ movdbl($mem$$Address, $tmp$$XMMRegister); 7034 %} 7035 ins_pipe( pipe_slow ); 7036 %} 7037 7038 // Store Pointer; for storing unknown oops and raw pointers 7039 instruct storeP(memory mem, anyRegP src) %{ 7040 match(Set mem (StoreP mem src)); 7041 7042 ins_cost(125); 7043 format %{ "MOV $mem,$src" %} 7044 opcode(0x89); 7045 ins_encode( OpcP, RegMem( src, mem ) ); 7046 ins_pipe( ialu_mem_reg ); 7047 %} 7048 7049 // Store Integer Immediate 7050 instruct storeImmI(memory mem, immI src) %{ 7051 match(Set mem (StoreI mem src)); 7052 7053 ins_cost(150); 7054 format %{ "MOV $mem,$src" %} 7055 opcode(0xC7); /* C7 /0 */ 7056 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7057 ins_pipe( ialu_mem_imm ); 7058 %} 7059 7060 // Store Short/Char Immediate 7061 instruct storeImmI16(memory mem, immI16 src) %{ 7062 predicate(UseStoreImmI16); 7063 match(Set mem (StoreC mem src)); 7064 7065 ins_cost(150); 7066 format %{ "MOV16 $mem,$src" %} 7067 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 7068 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); 7069 ins_pipe( ialu_mem_imm ); 7070 %} 7071 7072 // Store Pointer Immediate; null pointers or constant oops that do not 7073 // need card-mark barriers. 7074 instruct storeImmP(memory mem, immP src) %{ 7075 match(Set mem (StoreP mem src)); 7076 7077 ins_cost(150); 7078 format %{ "MOV $mem,$src" %} 7079 opcode(0xC7); /* C7 /0 */ 7080 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7081 ins_pipe( ialu_mem_imm ); 7082 %} 7083 7084 // Store Byte Immediate 7085 instruct storeImmB(memory mem, immI8 src) %{ 7086 match(Set mem (StoreB mem src)); 7087 7088 ins_cost(150); 7089 format %{ "MOV8 $mem,$src" %} 7090 opcode(0xC6); /* C6 /0 */ 7091 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7092 ins_pipe( ialu_mem_imm ); 7093 %} 7094 7095 // Store Aligned Packed Byte XMM register to memory 7096 instruct storeA8B(memory mem, regD src) %{ 7097 predicate(UseSSE>=1); 7098 match(Set mem (Store8B mem src)); 7099 ins_cost(145); 7100 format %{ "MOVQ $mem,$src\t! packed8B" %} 7101 ins_encode %{ 7102 __ movq($mem$$Address, $src$$XMMRegister); 7103 %} 7104 ins_pipe( pipe_slow ); 7105 %} 7106 7107 // Store Aligned Packed Char/Short XMM register to memory 7108 instruct storeA4C(memory mem, regD src) %{ 7109 predicate(UseSSE>=1); 7110 match(Set mem (Store4C mem src)); 7111 ins_cost(145); 7112 format %{ "MOVQ $mem,$src\t! packed4C" %} 7113 ins_encode %{ 7114 __ movq($mem$$Address, $src$$XMMRegister); 7115 %} 7116 ins_pipe( pipe_slow ); 7117 %} 7118 7119 // Store Aligned Packed Integer XMM register to memory 7120 instruct storeA2I(memory mem, regD src) %{ 7121 predicate(UseSSE>=1); 7122 match(Set mem (Store2I mem src)); 7123 ins_cost(145); 7124 format %{ "MOVQ $mem,$src\t! packed2I" %} 7125 ins_encode %{ 7126 __ movq($mem$$Address, $src$$XMMRegister); 7127 %} 7128 ins_pipe( pipe_slow ); 7129 %} 7130 7131 // Store CMS card-mark Immediate 7132 instruct storeImmCM(memory mem, immI8 src) %{ 7133 match(Set mem (StoreCM mem src)); 7134 7135 ins_cost(150); 7136 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 7137 opcode(0xC6); /* C6 /0 */ 7138 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7139 ins_pipe( ialu_mem_imm ); 7140 %} 7141 7142 // Store Double 7143 instruct storeDPR( memory mem, regDPR1 src) %{ 7144 predicate(UseSSE<=1); 7145 match(Set mem (StoreD mem src)); 7146 7147 ins_cost(100); 7148 format %{ "FST_D $mem,$src" %} 7149 opcode(0xDD); /* DD /2 */ 7150 ins_encode( enc_FPR_store(mem,src) ); 7151 ins_pipe( fpu_mem_reg ); 7152 %} 7153 7154 // Store double does rounding on x86 7155 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ 7156 predicate(UseSSE<=1); 7157 match(Set mem (StoreD mem (RoundDouble src))); 7158 7159 ins_cost(100); 7160 format %{ "FST_D $mem,$src\t# round" %} 7161 opcode(0xDD); /* DD /2 */ 7162 ins_encode( enc_FPR_store(mem,src) ); 7163 ins_pipe( fpu_mem_reg ); 7164 %} 7165 7166 // Store XMM register to memory (double-precision floating points) 7167 // MOVSD instruction 7168 instruct storeD(memory mem, regD src) %{ 7169 predicate(UseSSE>=2); 7170 match(Set mem (StoreD mem src)); 7171 ins_cost(95); 7172 format %{ "MOVSD $mem,$src" %} 7173 ins_encode %{ 7174 __ movdbl($mem$$Address, $src$$XMMRegister); 7175 %} 7176 ins_pipe( pipe_slow ); 7177 %} 7178 7179 // Store XMM register to memory (single-precision floating point) 7180 // MOVSS instruction 7181 instruct storeF(memory mem, regF src) %{ 7182 predicate(UseSSE>=1); 7183 match(Set mem (StoreF mem src)); 7184 ins_cost(95); 7185 format %{ "MOVSS $mem,$src" %} 7186 ins_encode %{ 7187 __ movflt($mem$$Address, $src$$XMMRegister); 7188 %} 7189 ins_pipe( pipe_slow ); 7190 %} 7191 7192 // Store Aligned Packed Single Float XMM register to memory 7193 instruct storeA2F(memory mem, regD src) %{ 7194 predicate(UseSSE>=1); 7195 match(Set mem (Store2F mem src)); 7196 ins_cost(145); 7197 format %{ "MOVQ $mem,$src\t! packed2F" %} 7198 ins_encode %{ 7199 __ movq($mem$$Address, $src$$XMMRegister); 7200 %} 7201 ins_pipe( pipe_slow ); 7202 %} 7203 7204 // Store Float 7205 instruct storeFPR( memory mem, regFPR1 src) %{ 7206 predicate(UseSSE==0); 7207 match(Set mem (StoreF mem src)); 7208 7209 ins_cost(100); 7210 format %{ "FST_S $mem,$src" %} 7211 opcode(0xD9); /* D9 /2 */ 7212 ins_encode( enc_FPR_store(mem,src) ); 7213 ins_pipe( fpu_mem_reg ); 7214 %} 7215 7216 // Store Float does rounding on x86 7217 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ 7218 predicate(UseSSE==0); 7219 match(Set mem (StoreF mem (RoundFloat src))); 7220 7221 ins_cost(100); 7222 format %{ "FST_S $mem,$src\t# round" %} 7223 opcode(0xD9); /* D9 /2 */ 7224 ins_encode( enc_FPR_store(mem,src) ); 7225 ins_pipe( fpu_mem_reg ); 7226 %} 7227 7228 // Store Float does rounding on x86 7229 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ 7230 predicate(UseSSE<=1); 7231 match(Set mem (StoreF mem (ConvD2F src))); 7232 7233 ins_cost(100); 7234 format %{ "FST_S $mem,$src\t# D-round" %} 7235 opcode(0xD9); /* D9 /2 */ 7236 ins_encode( enc_FPR_store(mem,src) ); 7237 ins_pipe( fpu_mem_reg ); 7238 %} 7239 7240 // Store immediate Float value (it is faster than store from FPU register) 7241 // The instruction usage is guarded by predicate in operand immFPR(). 7242 instruct storeFPR_imm( memory mem, immFPR src) %{ 7243 match(Set mem (StoreF mem src)); 7244 7245 ins_cost(50); 7246 format %{ "MOV $mem,$src\t# store float" %} 7247 opcode(0xC7); /* C7 /0 */ 7248 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); 7249 ins_pipe( ialu_mem_imm ); 7250 %} 7251 7252 // Store immediate Float value (it is faster than store from XMM register) 7253 // The instruction usage is guarded by predicate in operand immF(). 7254 instruct storeF_imm( memory mem, immF src) %{ 7255 match(Set mem (StoreF mem src)); 7256 7257 ins_cost(50); 7258 format %{ "MOV $mem,$src\t# store float" %} 7259 opcode(0xC7); /* C7 /0 */ 7260 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7261 ins_pipe( ialu_mem_imm ); 7262 %} 7263 7264 // Store Integer to stack slot 7265 instruct storeSSI(stackSlotI dst, eRegI src) %{ 7266 match(Set dst src); 7267 7268 ins_cost(100); 7269 format %{ "MOV $dst,$src" %} 7270 opcode(0x89); 7271 ins_encode( OpcPRegSS( dst, src ) ); 7272 ins_pipe( ialu_mem_reg ); 7273 %} 7274 7275 // Store Integer to stack slot 7276 instruct storeSSP(stackSlotP dst, eRegP src) %{ 7277 match(Set dst src); 7278 7279 ins_cost(100); 7280 format %{ "MOV $dst,$src" %} 7281 opcode(0x89); 7282 ins_encode( OpcPRegSS( dst, src ) ); 7283 ins_pipe( ialu_mem_reg ); 7284 %} 7285 7286 // Store Long to stack slot 7287 instruct storeSSL(stackSlotL dst, eRegL src) %{ 7288 match(Set dst src); 7289 7290 ins_cost(200); 7291 format %{ "MOV $dst,$src.lo\n\t" 7292 "MOV $dst+4,$src.hi" %} 7293 opcode(0x89, 0x89); 7294 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 7295 ins_pipe( ialu_mem_long_reg ); 7296 %} 7297 7298 //----------MemBar Instructions----------------------------------------------- 7299 // Memory barrier flavors 7300 7301 instruct membar_acquire() %{ 7302 match(MemBarAcquire); 7303 ins_cost(400); 7304 7305 size(0); 7306 format %{ "MEMBAR-acquire ! (empty encoding)" %} 7307 ins_encode(); 7308 ins_pipe(empty); 7309 %} 7310 7311 instruct membar_acquire_lock() %{ 7312 match(MemBarAcquireLock); 7313 ins_cost(0); 7314 7315 size(0); 7316 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 7317 ins_encode( ); 7318 ins_pipe(empty); 7319 %} 7320 7321 instruct membar_release() %{ 7322 match(MemBarRelease); 7323 ins_cost(400); 7324 7325 size(0); 7326 format %{ "MEMBAR-release ! (empty encoding)" %} 7327 ins_encode( ); 7328 ins_pipe(empty); 7329 %} 7330 7331 instruct membar_release_lock() %{ 7332 match(MemBarReleaseLock); 7333 ins_cost(0); 7334 7335 size(0); 7336 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 7337 ins_encode( ); 7338 ins_pipe(empty); 7339 %} 7340 7341 instruct membar_volatile(eFlagsReg cr) %{ 7342 match(MemBarVolatile); 7343 effect(KILL cr); 7344 ins_cost(400); 7345 7346 format %{ 7347 $$template 7348 if (os::is_MP()) { 7349 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" 7350 } else { 7351 $$emit$$"MEMBAR-volatile ! (empty encoding)" 7352 } 7353 %} 7354 ins_encode %{ 7355 __ membar(Assembler::StoreLoad); 7356 %} 7357 ins_pipe(pipe_slow); 7358 %} 7359 7360 instruct unnecessary_membar_volatile() %{ 7361 match(MemBarVolatile); 7362 predicate(Matcher::post_store_load_barrier(n)); 7363 ins_cost(0); 7364 7365 size(0); 7366 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 7367 ins_encode( ); 7368 ins_pipe(empty); 7369 %} 7370 7371 //----------Move Instructions-------------------------------------------------- 7372 instruct castX2P(eAXRegP dst, eAXRegI src) %{ 7373 match(Set dst (CastX2P src)); 7374 format %{ "# X2P $dst, $src" %} 7375 ins_encode( /*empty encoding*/ ); 7376 ins_cost(0); 7377 ins_pipe(empty); 7378 %} 7379 7380 instruct castP2X(eRegI dst, eRegP src ) %{ 7381 match(Set dst (CastP2X src)); 7382 ins_cost(50); 7383 format %{ "MOV $dst, $src\t# CastP2X" %} 7384 ins_encode( enc_Copy( dst, src) ); 7385 ins_pipe( ialu_reg_reg ); 7386 %} 7387 7388 //----------Conditional Move--------------------------------------------------- 7389 // Conditional move 7390 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{ 7391 predicate(!VM_Version::supports_cmov() ); 7392 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7393 ins_cost(200); 7394 format %{ "J$cop,us skip\t# signed cmove\n\t" 7395 "MOV $dst,$src\n" 7396 "skip:" %} 7397 ins_encode %{ 7398 Label Lskip; 7399 // Invert sense of branch from sense of CMOV 7400 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7401 __ movl($dst$$Register, $src$$Register); 7402 __ bind(Lskip); 7403 %} 7404 ins_pipe( pipe_cmov_reg ); 7405 %} 7406 7407 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{ 7408 predicate(!VM_Version::supports_cmov() ); 7409 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7410 ins_cost(200); 7411 format %{ "J$cop,us skip\t# unsigned cmove\n\t" 7412 "MOV $dst,$src\n" 7413 "skip:" %} 7414 ins_encode %{ 7415 Label Lskip; 7416 // Invert sense of branch from sense of CMOV 7417 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7418 __ movl($dst$$Register, $src$$Register); 7419 __ bind(Lskip); 7420 %} 7421 ins_pipe( pipe_cmov_reg ); 7422 %} 7423 7424 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ 7425 predicate(VM_Version::supports_cmov() ); 7426 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7427 ins_cost(200); 7428 format %{ "CMOV$cop $dst,$src" %} 7429 opcode(0x0F,0x40); 7430 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7431 ins_pipe( pipe_cmov_reg ); 7432 %} 7433 7434 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ 7435 predicate(VM_Version::supports_cmov() ); 7436 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7437 ins_cost(200); 7438 format %{ "CMOV$cop $dst,$src" %} 7439 opcode(0x0F,0x40); 7440 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7441 ins_pipe( pipe_cmov_reg ); 7442 %} 7443 7444 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ 7445 predicate(VM_Version::supports_cmov() ); 7446 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7447 ins_cost(200); 7448 expand %{ 7449 cmovI_regU(cop, cr, dst, src); 7450 %} 7451 %} 7452 7453 // Conditional move 7454 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ 7455 predicate(VM_Version::supports_cmov() ); 7456 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7457 ins_cost(250); 7458 format %{ "CMOV$cop $dst,$src" %} 7459 opcode(0x0F,0x40); 7460 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7461 ins_pipe( pipe_cmov_mem ); 7462 %} 7463 7464 // Conditional move 7465 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ 7466 predicate(VM_Version::supports_cmov() ); 7467 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7468 ins_cost(250); 7469 format %{ "CMOV$cop $dst,$src" %} 7470 opcode(0x0F,0x40); 7471 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7472 ins_pipe( pipe_cmov_mem ); 7473 %} 7474 7475 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ 7476 predicate(VM_Version::supports_cmov() ); 7477 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7478 ins_cost(250); 7479 expand %{ 7480 cmovI_memU(cop, cr, dst, src); 7481 %} 7482 %} 7483 7484 // Conditional move 7485 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7486 predicate(VM_Version::supports_cmov() ); 7487 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7488 ins_cost(200); 7489 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7490 opcode(0x0F,0x40); 7491 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7492 ins_pipe( pipe_cmov_reg ); 7493 %} 7494 7495 // Conditional move (non-P6 version) 7496 // Note: a CMoveP is generated for stubs and native wrappers 7497 // regardless of whether we are on a P6, so we 7498 // emulate a cmov here 7499 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7500 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7501 ins_cost(300); 7502 format %{ "Jn$cop skip\n\t" 7503 "MOV $dst,$src\t# pointer\n" 7504 "skip:" %} 7505 opcode(0x8b); 7506 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); 7507 ins_pipe( pipe_cmov_reg ); 7508 %} 7509 7510 // Conditional move 7511 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ 7512 predicate(VM_Version::supports_cmov() ); 7513 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7514 ins_cost(200); 7515 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7516 opcode(0x0F,0x40); 7517 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7518 ins_pipe( pipe_cmov_reg ); 7519 %} 7520 7521 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ 7522 predicate(VM_Version::supports_cmov() ); 7523 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7524 ins_cost(200); 7525 expand %{ 7526 cmovP_regU(cop, cr, dst, src); 7527 %} 7528 %} 7529 7530 // DISABLED: Requires the ADLC to emit a bottom_type call that 7531 // correctly meets the two pointer arguments; one is an incoming 7532 // register but the other is a memory operand. ALSO appears to 7533 // be buggy with implicit null checks. 7534 // 7535 //// Conditional move 7536 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ 7537 // predicate(VM_Version::supports_cmov() ); 7538 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7539 // ins_cost(250); 7540 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 7541 // opcode(0x0F,0x40); 7542 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7543 // ins_pipe( pipe_cmov_mem ); 7544 //%} 7545 // 7546 //// Conditional move 7547 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ 7548 // predicate(VM_Version::supports_cmov() ); 7549 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7550 // ins_cost(250); 7551 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 7552 // opcode(0x0F,0x40); 7553 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7554 // ins_pipe( pipe_cmov_mem ); 7555 //%} 7556 7557 // Conditional move 7558 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ 7559 predicate(UseSSE<=1); 7560 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7561 ins_cost(200); 7562 format %{ "FCMOV$cop $dst,$src\t# double" %} 7563 opcode(0xDA); 7564 ins_encode( enc_cmov_dpr(cop,src) ); 7565 ins_pipe( pipe_cmovDPR_reg ); 7566 %} 7567 7568 // Conditional move 7569 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ 7570 predicate(UseSSE==0); 7571 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7572 ins_cost(200); 7573 format %{ "FCMOV$cop $dst,$src\t# float" %} 7574 opcode(0xDA); 7575 ins_encode( enc_cmov_dpr(cop,src) ); 7576 ins_pipe( pipe_cmovDPR_reg ); 7577 %} 7578 7579 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7580 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ 7581 predicate(UseSSE<=1); 7582 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7583 ins_cost(200); 7584 format %{ "Jn$cop skip\n\t" 7585 "MOV $dst,$src\t# double\n" 7586 "skip:" %} 7587 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7588 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); 7589 ins_pipe( pipe_cmovDPR_reg ); 7590 %} 7591 7592 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7593 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ 7594 predicate(UseSSE==0); 7595 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7596 ins_cost(200); 7597 format %{ "Jn$cop skip\n\t" 7598 "MOV $dst,$src\t# float\n" 7599 "skip:" %} 7600 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7601 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); 7602 ins_pipe( pipe_cmovDPR_reg ); 7603 %} 7604 7605 // No CMOVE with SSE/SSE2 7606 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ 7607 predicate (UseSSE>=1); 7608 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7609 ins_cost(200); 7610 format %{ "Jn$cop skip\n\t" 7611 "MOVSS $dst,$src\t# float\n" 7612 "skip:" %} 7613 ins_encode %{ 7614 Label skip; 7615 // Invert sense of branch from sense of CMOV 7616 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7617 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7618 __ bind(skip); 7619 %} 7620 ins_pipe( pipe_slow ); 7621 %} 7622 7623 // No CMOVE with SSE/SSE2 7624 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ 7625 predicate (UseSSE>=2); 7626 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7627 ins_cost(200); 7628 format %{ "Jn$cop skip\n\t" 7629 "MOVSD $dst,$src\t# float\n" 7630 "skip:" %} 7631 ins_encode %{ 7632 Label skip; 7633 // Invert sense of branch from sense of CMOV 7634 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7635 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7636 __ bind(skip); 7637 %} 7638 ins_pipe( pipe_slow ); 7639 %} 7640 7641 // unsigned version 7642 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ 7643 predicate (UseSSE>=1); 7644 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7645 ins_cost(200); 7646 format %{ "Jn$cop skip\n\t" 7647 "MOVSS $dst,$src\t# float\n" 7648 "skip:" %} 7649 ins_encode %{ 7650 Label skip; 7651 // Invert sense of branch from sense of CMOV 7652 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7653 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7654 __ bind(skip); 7655 %} 7656 ins_pipe( pipe_slow ); 7657 %} 7658 7659 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ 7660 predicate (UseSSE>=1); 7661 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7662 ins_cost(200); 7663 expand %{ 7664 fcmovF_regU(cop, cr, dst, src); 7665 %} 7666 %} 7667 7668 // unsigned version 7669 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ 7670 predicate (UseSSE>=2); 7671 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7672 ins_cost(200); 7673 format %{ "Jn$cop skip\n\t" 7674 "MOVSD $dst,$src\t# float\n" 7675 "skip:" %} 7676 ins_encode %{ 7677 Label skip; 7678 // Invert sense of branch from sense of CMOV 7679 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7680 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7681 __ bind(skip); 7682 %} 7683 ins_pipe( pipe_slow ); 7684 %} 7685 7686 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ 7687 predicate (UseSSE>=2); 7688 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7689 ins_cost(200); 7690 expand %{ 7691 fcmovD_regU(cop, cr, dst, src); 7692 %} 7693 %} 7694 7695 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ 7696 predicate(VM_Version::supports_cmov() ); 7697 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7698 ins_cost(200); 7699 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7700 "CMOV$cop $dst.hi,$src.hi" %} 7701 opcode(0x0F,0x40); 7702 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7703 ins_pipe( pipe_cmov_reg_long ); 7704 %} 7705 7706 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ 7707 predicate(VM_Version::supports_cmov() ); 7708 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7709 ins_cost(200); 7710 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7711 "CMOV$cop $dst.hi,$src.hi" %} 7712 opcode(0x0F,0x40); 7713 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7714 ins_pipe( pipe_cmov_reg_long ); 7715 %} 7716 7717 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ 7718 predicate(VM_Version::supports_cmov() ); 7719 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7720 ins_cost(200); 7721 expand %{ 7722 cmovL_regU(cop, cr, dst, src); 7723 %} 7724 %} 7725 7726 //----------Arithmetic Instructions-------------------------------------------- 7727 //----------Addition Instructions---------------------------------------------- 7728 // Integer Addition Instructions 7729 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7730 match(Set dst (AddI dst src)); 7731 effect(KILL cr); 7732 7733 size(2); 7734 format %{ "ADD $dst,$src" %} 7735 opcode(0x03); 7736 ins_encode( OpcP, RegReg( dst, src) ); 7737 ins_pipe( ialu_reg_reg ); 7738 %} 7739 7740 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7741 match(Set dst (AddI dst src)); 7742 effect(KILL cr); 7743 7744 format %{ "ADD $dst,$src" %} 7745 opcode(0x81, 0x00); /* /0 id */ 7746 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7747 ins_pipe( ialu_reg ); 7748 %} 7749 7750 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 7751 predicate(UseIncDec); 7752 match(Set dst (AddI dst src)); 7753 effect(KILL cr); 7754 7755 size(1); 7756 format %{ "INC $dst" %} 7757 opcode(0x40); /* */ 7758 ins_encode( Opc_plus( primary, dst ) ); 7759 ins_pipe( ialu_reg ); 7760 %} 7761 7762 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ 7763 match(Set dst (AddI src0 src1)); 7764 ins_cost(110); 7765 7766 format %{ "LEA $dst,[$src0 + $src1]" %} 7767 opcode(0x8D); /* 0x8D /r */ 7768 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7769 ins_pipe( ialu_reg_reg ); 7770 %} 7771 7772 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ 7773 match(Set dst (AddP src0 src1)); 7774 ins_cost(110); 7775 7776 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} 7777 opcode(0x8D); /* 0x8D /r */ 7778 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7779 ins_pipe( ialu_reg_reg ); 7780 %} 7781 7782 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ 7783 predicate(UseIncDec); 7784 match(Set dst (AddI dst src)); 7785 effect(KILL cr); 7786 7787 size(1); 7788 format %{ "DEC $dst" %} 7789 opcode(0x48); /* */ 7790 ins_encode( Opc_plus( primary, dst ) ); 7791 ins_pipe( ialu_reg ); 7792 %} 7793 7794 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ 7795 match(Set dst (AddP dst src)); 7796 effect(KILL cr); 7797 7798 size(2); 7799 format %{ "ADD $dst,$src" %} 7800 opcode(0x03); 7801 ins_encode( OpcP, RegReg( dst, src) ); 7802 ins_pipe( ialu_reg_reg ); 7803 %} 7804 7805 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ 7806 match(Set dst (AddP dst src)); 7807 effect(KILL cr); 7808 7809 format %{ "ADD $dst,$src" %} 7810 opcode(0x81,0x00); /* Opcode 81 /0 id */ 7811 // ins_encode( RegImm( dst, src) ); 7812 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7813 ins_pipe( ialu_reg ); 7814 %} 7815 7816 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7817 match(Set dst (AddI dst (LoadI src))); 7818 effect(KILL cr); 7819 7820 ins_cost(125); 7821 format %{ "ADD $dst,$src" %} 7822 opcode(0x03); 7823 ins_encode( OpcP, RegMem( dst, src) ); 7824 ins_pipe( ialu_reg_mem ); 7825 %} 7826 7827 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7828 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7829 effect(KILL cr); 7830 7831 ins_cost(150); 7832 format %{ "ADD $dst,$src" %} 7833 opcode(0x01); /* Opcode 01 /r */ 7834 ins_encode( OpcP, RegMem( src, dst ) ); 7835 ins_pipe( ialu_mem_reg ); 7836 %} 7837 7838 // Add Memory with Immediate 7839 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 7840 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7841 effect(KILL cr); 7842 7843 ins_cost(125); 7844 format %{ "ADD $dst,$src" %} 7845 opcode(0x81); /* Opcode 81 /0 id */ 7846 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); 7847 ins_pipe( ialu_mem_imm ); 7848 %} 7849 7850 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ 7851 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7852 effect(KILL cr); 7853 7854 ins_cost(125); 7855 format %{ "INC $dst" %} 7856 opcode(0xFF); /* Opcode FF /0 */ 7857 ins_encode( OpcP, RMopc_Mem(0x00,dst)); 7858 ins_pipe( ialu_mem_imm ); 7859 %} 7860 7861 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ 7862 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7863 effect(KILL cr); 7864 7865 ins_cost(125); 7866 format %{ "DEC $dst" %} 7867 opcode(0xFF); /* Opcode FF /1 */ 7868 ins_encode( OpcP, RMopc_Mem(0x01,dst)); 7869 ins_pipe( ialu_mem_imm ); 7870 %} 7871 7872 7873 instruct checkCastPP( eRegP dst ) %{ 7874 match(Set dst (CheckCastPP dst)); 7875 7876 size(0); 7877 format %{ "#checkcastPP of $dst" %} 7878 ins_encode( /*empty encoding*/ ); 7879 ins_pipe( empty ); 7880 %} 7881 7882 instruct castPP( eRegP dst ) %{ 7883 match(Set dst (CastPP dst)); 7884 format %{ "#castPP of $dst" %} 7885 ins_encode( /*empty encoding*/ ); 7886 ins_pipe( empty ); 7887 %} 7888 7889 instruct castII( eRegI dst ) %{ 7890 match(Set dst (CastII dst)); 7891 format %{ "#castII of $dst" %} 7892 ins_encode( /*empty encoding*/ ); 7893 ins_cost(0); 7894 ins_pipe( empty ); 7895 %} 7896 7897 7898 // Load-locked - same as a regular pointer load when used with compare-swap 7899 instruct loadPLocked(eRegP dst, memory mem) %{ 7900 match(Set dst (LoadPLocked mem)); 7901 7902 ins_cost(125); 7903 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 7904 opcode(0x8B); 7905 ins_encode( OpcP, RegMem(dst,mem)); 7906 ins_pipe( ialu_reg_mem ); 7907 %} 7908 7909 // LoadLong-locked - same as a volatile long load when used with compare-swap 7910 instruct loadLLocked(stackSlotL dst, memory mem) %{ 7911 predicate(UseSSE<=1); 7912 match(Set dst (LoadLLocked mem)); 7913 7914 ins_cost(200); 7915 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 7916 "FISTp $dst" %} 7917 ins_encode(enc_loadL_volatile(mem,dst)); 7918 ins_pipe( fpu_reg_mem ); 7919 %} 7920 7921 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{ 7922 predicate(UseSSE>=2); 7923 match(Set dst (LoadLLocked mem)); 7924 effect(TEMP tmp); 7925 ins_cost(180); 7926 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7927 "MOVSD $dst,$tmp" %} 7928 ins_encode %{ 7929 __ movdbl($tmp$$XMMRegister, $mem$$Address); 7930 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); 7931 %} 7932 ins_pipe( pipe_slow ); 7933 %} 7934 7935 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{ 7936 predicate(UseSSE>=2); 7937 match(Set dst (LoadLLocked mem)); 7938 effect(TEMP tmp); 7939 ins_cost(160); 7940 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7941 "MOVD $dst.lo,$tmp\n\t" 7942 "PSRLQ $tmp,32\n\t" 7943 "MOVD $dst.hi,$tmp" %} 7944 ins_encode %{ 7945 __ movdbl($tmp$$XMMRegister, $mem$$Address); 7946 __ movdl($dst$$Register, $tmp$$XMMRegister); 7947 __ psrlq($tmp$$XMMRegister, 32); 7948 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); 7949 %} 7950 ins_pipe( pipe_slow ); 7951 %} 7952 7953 // Conditional-store of the updated heap-top. 7954 // Used during allocation of the shared heap. 7955 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7956 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ 7957 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 7958 // EAX is killed if there is contention, but then it's also unused. 7959 // In the common case of no contention, EAX holds the new oop address. 7960 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} 7961 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); 7962 ins_pipe( pipe_cmpxchg ); 7963 %} 7964 7965 // Conditional-store of an int value. 7966 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. 7967 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ 7968 match(Set cr (StoreIConditional mem (Binary oldval newval))); 7969 effect(KILL oldval); 7970 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} 7971 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); 7972 ins_pipe( pipe_cmpxchg ); 7973 %} 7974 7975 // Conditional-store of a long value. 7976 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. 7977 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7978 match(Set cr (StoreLConditional mem (Binary oldval newval))); 7979 effect(KILL oldval); 7980 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" 7981 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" 7982 "XCHG EBX,ECX" 7983 %} 7984 ins_encode %{ 7985 // Note: we need to swap rbx, and rcx before and after the 7986 // cmpxchg8 instruction because the instruction uses 7987 // rcx as the high order word of the new value to store but 7988 // our register encoding uses rbx. 7989 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 7990 if( os::is_MP() ) 7991 __ lock(); 7992 __ cmpxchg8($mem$$Address); 7993 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 7994 %} 7995 ins_pipe( pipe_cmpxchg ); 7996 %} 7997 7998 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7999 8000 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 8001 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 8002 effect(KILL cr, KILL oldval); 8003 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8004 "MOV $res,0\n\t" 8005 "JNE,s fail\n\t" 8006 "MOV $res,1\n" 8007 "fail:" %} 8008 ins_encode( enc_cmpxchg8(mem_ptr), 8009 enc_flags_ne_to_boolean(res) ); 8010 ins_pipe( pipe_cmpxchg ); 8011 %} 8012 8013 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 8014 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 8015 effect(KILL cr, KILL oldval); 8016 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8017 "MOV $res,0\n\t" 8018 "JNE,s fail\n\t" 8019 "MOV $res,1\n" 8020 "fail:" %} 8021 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 8022 ins_pipe( pipe_cmpxchg ); 8023 %} 8024 8025 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 8026 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 8027 effect(KILL cr, KILL oldval); 8028 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 8029 "MOV $res,0\n\t" 8030 "JNE,s fail\n\t" 8031 "MOV $res,1\n" 8032 "fail:" %} 8033 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 8034 ins_pipe( pipe_cmpxchg ); 8035 %} 8036 8037 //----------Subtraction Instructions------------------------------------------- 8038 // Integer Subtraction Instructions 8039 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8040 match(Set dst (SubI dst src)); 8041 effect(KILL cr); 8042 8043 size(2); 8044 format %{ "SUB $dst,$src" %} 8045 opcode(0x2B); 8046 ins_encode( OpcP, RegReg( dst, src) ); 8047 ins_pipe( ialu_reg_reg ); 8048 %} 8049 8050 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8051 match(Set dst (SubI dst src)); 8052 effect(KILL cr); 8053 8054 format %{ "SUB $dst,$src" %} 8055 opcode(0x81,0x05); /* Opcode 81 /5 */ 8056 // ins_encode( RegImm( dst, src) ); 8057 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8058 ins_pipe( ialu_reg ); 8059 %} 8060 8061 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8062 match(Set dst (SubI dst (LoadI src))); 8063 effect(KILL cr); 8064 8065 ins_cost(125); 8066 format %{ "SUB $dst,$src" %} 8067 opcode(0x2B); 8068 ins_encode( OpcP, RegMem( dst, src) ); 8069 ins_pipe( ialu_reg_mem ); 8070 %} 8071 8072 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8073 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 8074 effect(KILL cr); 8075 8076 ins_cost(150); 8077 format %{ "SUB $dst,$src" %} 8078 opcode(0x29); /* Opcode 29 /r */ 8079 ins_encode( OpcP, RegMem( src, dst ) ); 8080 ins_pipe( ialu_mem_reg ); 8081 %} 8082 8083 // Subtract from a pointer 8084 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ 8085 match(Set dst (AddP dst (SubI zero src))); 8086 effect(KILL cr); 8087 8088 size(2); 8089 format %{ "SUB $dst,$src" %} 8090 opcode(0x2B); 8091 ins_encode( OpcP, RegReg( dst, src) ); 8092 ins_pipe( ialu_reg_reg ); 8093 %} 8094 8095 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ 8096 match(Set dst (SubI zero dst)); 8097 effect(KILL cr); 8098 8099 size(2); 8100 format %{ "NEG $dst" %} 8101 opcode(0xF7,0x03); // Opcode F7 /3 8102 ins_encode( OpcP, RegOpc( dst ) ); 8103 ins_pipe( ialu_reg ); 8104 %} 8105 8106 8107 //----------Multiplication/Division Instructions------------------------------- 8108 // Integer Multiplication Instructions 8109 // Multiply Register 8110 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8111 match(Set dst (MulI dst src)); 8112 effect(KILL cr); 8113 8114 size(3); 8115 ins_cost(300); 8116 format %{ "IMUL $dst,$src" %} 8117 opcode(0xAF, 0x0F); 8118 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 8119 ins_pipe( ialu_reg_reg_alu0 ); 8120 %} 8121 8122 // Multiply 32-bit Immediate 8123 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ 8124 match(Set dst (MulI src imm)); 8125 effect(KILL cr); 8126 8127 ins_cost(300); 8128 format %{ "IMUL $dst,$src,$imm" %} 8129 opcode(0x69); /* 69 /r id */ 8130 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); 8131 ins_pipe( ialu_reg_reg_alu0 ); 8132 %} 8133 8134 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ 8135 match(Set dst src); 8136 effect(KILL cr); 8137 8138 // Note that this is artificially increased to make it more expensive than loadConL 8139 ins_cost(250); 8140 format %{ "MOV EAX,$src\t// low word only" %} 8141 opcode(0xB8); 8142 ins_encode( LdImmL_Lo(dst, src) ); 8143 ins_pipe( ialu_reg_fat ); 8144 %} 8145 8146 // Multiply by 32-bit Immediate, taking the shifted high order results 8147 // (special case for shift by 32) 8148 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ 8149 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8150 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8151 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8152 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8153 effect(USE src1, KILL cr); 8154 8155 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8156 ins_cost(0*100 + 1*400 - 150); 8157 format %{ "IMUL EDX:EAX,$src1" %} 8158 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8159 ins_pipe( pipe_slow ); 8160 %} 8161 8162 // Multiply by 32-bit Immediate, taking the shifted high order results 8163 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ 8164 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8165 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8166 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8167 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8168 effect(USE src1, KILL cr); 8169 8170 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8171 ins_cost(1*100 + 1*400 - 150); 8172 format %{ "IMUL EDX:EAX,$src1\n\t" 8173 "SAR EDX,$cnt-32" %} 8174 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8175 ins_pipe( pipe_slow ); 8176 %} 8177 8178 // Multiply Memory 32-bit Immediate 8179 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ 8180 match(Set dst (MulI (LoadI src) imm)); 8181 effect(KILL cr); 8182 8183 ins_cost(300); 8184 format %{ "IMUL $dst,$src,$imm" %} 8185 opcode(0x69); /* 69 /r id */ 8186 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 8187 ins_pipe( ialu_reg_mem_alu0 ); 8188 %} 8189 8190 // Multiply Memory 8191 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ 8192 match(Set dst (MulI dst (LoadI src))); 8193 effect(KILL cr); 8194 8195 ins_cost(350); 8196 format %{ "IMUL $dst,$src" %} 8197 opcode(0xAF, 0x0F); 8198 ins_encode( OpcS, OpcP, RegMem( dst, src) ); 8199 ins_pipe( ialu_reg_mem_alu0 ); 8200 %} 8201 8202 // Multiply Register Int to Long 8203 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ 8204 // Basic Idea: long = (long)int * (long)int 8205 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); 8206 effect(DEF dst, USE src, USE src1, KILL flags); 8207 8208 ins_cost(300); 8209 format %{ "IMUL $dst,$src1" %} 8210 8211 ins_encode( long_int_multiply( dst, src1 ) ); 8212 ins_pipe( ialu_reg_reg_alu0 ); 8213 %} 8214 8215 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ 8216 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 8217 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); 8218 effect(KILL flags); 8219 8220 ins_cost(300); 8221 format %{ "MUL $dst,$src1" %} 8222 8223 ins_encode( long_uint_multiply(dst, src1) ); 8224 ins_pipe( ialu_reg_reg_alu0 ); 8225 %} 8226 8227 // Multiply Register Long 8228 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8229 match(Set dst (MulL dst src)); 8230 effect(KILL cr, TEMP tmp); 8231 ins_cost(4*100+3*400); 8232 // Basic idea: lo(result) = lo(x_lo * y_lo) 8233 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 8234 format %{ "MOV $tmp,$src.lo\n\t" 8235 "IMUL $tmp,EDX\n\t" 8236 "MOV EDX,$src.hi\n\t" 8237 "IMUL EDX,EAX\n\t" 8238 "ADD $tmp,EDX\n\t" 8239 "MUL EDX:EAX,$src.lo\n\t" 8240 "ADD EDX,$tmp" %} 8241 ins_encode( long_multiply( dst, src, tmp ) ); 8242 ins_pipe( pipe_slow ); 8243 %} 8244 8245 // Multiply Register Long where the left operand's high 32 bits are zero 8246 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8247 predicate(is_operand_hi32_zero(n->in(1))); 8248 match(Set dst (MulL dst src)); 8249 effect(KILL cr, TEMP tmp); 8250 ins_cost(2*100+2*400); 8251 // Basic idea: lo(result) = lo(x_lo * y_lo) 8252 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 8253 format %{ "MOV $tmp,$src.hi\n\t" 8254 "IMUL $tmp,EAX\n\t" 8255 "MUL EDX:EAX,$src.lo\n\t" 8256 "ADD EDX,$tmp" %} 8257 ins_encode %{ 8258 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); 8259 __ imull($tmp$$Register, rax); 8260 __ mull($src$$Register); 8261 __ addl(rdx, $tmp$$Register); 8262 %} 8263 ins_pipe( pipe_slow ); 8264 %} 8265 8266 // Multiply Register Long where the right operand's high 32 bits are zero 8267 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8268 predicate(is_operand_hi32_zero(n->in(2))); 8269 match(Set dst (MulL dst src)); 8270 effect(KILL cr, TEMP tmp); 8271 ins_cost(2*100+2*400); 8272 // Basic idea: lo(result) = lo(x_lo * y_lo) 8273 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 8274 format %{ "MOV $tmp,$src.lo\n\t" 8275 "IMUL $tmp,EDX\n\t" 8276 "MUL EDX:EAX,$src.lo\n\t" 8277 "ADD EDX,$tmp" %} 8278 ins_encode %{ 8279 __ movl($tmp$$Register, $src$$Register); 8280 __ imull($tmp$$Register, rdx); 8281 __ mull($src$$Register); 8282 __ addl(rdx, $tmp$$Register); 8283 %} 8284 ins_pipe( pipe_slow ); 8285 %} 8286 8287 // Multiply Register Long where the left and the right operands' high 32 bits are zero 8288 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ 8289 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); 8290 match(Set dst (MulL dst src)); 8291 effect(KILL cr); 8292 ins_cost(1*400); 8293 // Basic idea: lo(result) = lo(x_lo * y_lo) 8294 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 8295 format %{ "MUL EDX:EAX,$src.lo\n\t" %} 8296 ins_encode %{ 8297 __ mull($src$$Register); 8298 %} 8299 ins_pipe( pipe_slow ); 8300 %} 8301 8302 // Multiply Register Long by small constant 8303 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ 8304 match(Set dst (MulL dst src)); 8305 effect(KILL cr, TEMP tmp); 8306 ins_cost(2*100+2*400); 8307 size(12); 8308 // Basic idea: lo(result) = lo(src * EAX) 8309 // hi(result) = hi(src * EAX) + lo(src * EDX) 8310 format %{ "IMUL $tmp,EDX,$src\n\t" 8311 "MOV EDX,$src\n\t" 8312 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8313 "ADD EDX,$tmp" %} 8314 ins_encode( long_multiply_con( dst, src, tmp ) ); 8315 ins_pipe( pipe_slow ); 8316 %} 8317 8318 // Integer DIV with Register 8319 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8320 match(Set rax (DivI rax div)); 8321 effect(KILL rdx, KILL cr); 8322 size(26); 8323 ins_cost(30*100+10*100); 8324 format %{ "CMP EAX,0x80000000\n\t" 8325 "JNE,s normal\n\t" 8326 "XOR EDX,EDX\n\t" 8327 "CMP ECX,-1\n\t" 8328 "JE,s done\n" 8329 "normal: CDQ\n\t" 8330 "IDIV $div\n\t" 8331 "done:" %} 8332 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8333 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8334 ins_pipe( ialu_reg_reg_alu0 ); 8335 %} 8336 8337 // Divide Register Long 8338 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8339 match(Set dst (DivL src1 src2)); 8340 effect( KILL cr, KILL cx, KILL bx ); 8341 ins_cost(10000); 8342 format %{ "PUSH $src1.hi\n\t" 8343 "PUSH $src1.lo\n\t" 8344 "PUSH $src2.hi\n\t" 8345 "PUSH $src2.lo\n\t" 8346 "CALL SharedRuntime::ldiv\n\t" 8347 "ADD ESP,16" %} 8348 ins_encode( long_div(src1,src2) ); 8349 ins_pipe( pipe_slow ); 8350 %} 8351 8352 // Integer DIVMOD with Register, both quotient and mod results 8353 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8354 match(DivModI rax div); 8355 effect(KILL cr); 8356 size(26); 8357 ins_cost(30*100+10*100); 8358 format %{ "CMP EAX,0x80000000\n\t" 8359 "JNE,s normal\n\t" 8360 "XOR EDX,EDX\n\t" 8361 "CMP ECX,-1\n\t" 8362 "JE,s done\n" 8363 "normal: CDQ\n\t" 8364 "IDIV $div\n\t" 8365 "done:" %} 8366 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8367 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8368 ins_pipe( pipe_slow ); 8369 %} 8370 8371 // Integer MOD with Register 8372 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ 8373 match(Set rdx (ModI rax div)); 8374 effect(KILL rax, KILL cr); 8375 8376 size(26); 8377 ins_cost(300); 8378 format %{ "CDQ\n\t" 8379 "IDIV $div" %} 8380 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8381 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8382 ins_pipe( ialu_reg_reg_alu0 ); 8383 %} 8384 8385 // Remainder Register Long 8386 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8387 match(Set dst (ModL src1 src2)); 8388 effect( KILL cr, KILL cx, KILL bx ); 8389 ins_cost(10000); 8390 format %{ "PUSH $src1.hi\n\t" 8391 "PUSH $src1.lo\n\t" 8392 "PUSH $src2.hi\n\t" 8393 "PUSH $src2.lo\n\t" 8394 "CALL SharedRuntime::lrem\n\t" 8395 "ADD ESP,16" %} 8396 ins_encode( long_mod(src1,src2) ); 8397 ins_pipe( pipe_slow ); 8398 %} 8399 8400 // Divide Register Long (no special case since divisor != -1) 8401 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ 8402 match(Set dst (DivL dst imm)); 8403 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8404 ins_cost(1000); 8405 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" 8406 "XOR $tmp2,$tmp2\n\t" 8407 "CMP $tmp,EDX\n\t" 8408 "JA,s fast\n\t" 8409 "MOV $tmp2,EAX\n\t" 8410 "MOV EAX,EDX\n\t" 8411 "MOV EDX,0\n\t" 8412 "JLE,s pos\n\t" 8413 "LNEG EAX : $tmp2\n\t" 8414 "DIV $tmp # unsigned division\n\t" 8415 "XCHG EAX,$tmp2\n\t" 8416 "DIV $tmp\n\t" 8417 "LNEG $tmp2 : EAX\n\t" 8418 "JMP,s done\n" 8419 "pos:\n\t" 8420 "DIV $tmp\n\t" 8421 "XCHG EAX,$tmp2\n" 8422 "fast:\n\t" 8423 "DIV $tmp\n" 8424 "done:\n\t" 8425 "MOV EDX,$tmp2\n\t" 8426 "NEG EDX:EAX # if $imm < 0" %} 8427 ins_encode %{ 8428 int con = (int)$imm$$constant; 8429 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); 8430 int pcon = (con > 0) ? con : -con; 8431 Label Lfast, Lpos, Ldone; 8432 8433 __ movl($tmp$$Register, pcon); 8434 __ xorl($tmp2$$Register,$tmp2$$Register); 8435 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); 8436 __ jccb(Assembler::above, Lfast); // result fits into 32 bit 8437 8438 __ movl($tmp2$$Register, $dst$$Register); // save 8439 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8440 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags 8441 __ jccb(Assembler::lessEqual, Lpos); // result is positive 8442 8443 // Negative dividend. 8444 // convert value to positive to use unsigned division 8445 __ lneg($dst$$Register, $tmp2$$Register); 8446 __ divl($tmp$$Register); 8447 __ xchgl($dst$$Register, $tmp2$$Register); 8448 __ divl($tmp$$Register); 8449 // revert result back to negative 8450 __ lneg($tmp2$$Register, $dst$$Register); 8451 __ jmpb(Ldone); 8452 8453 __ bind(Lpos); 8454 __ divl($tmp$$Register); // Use unsigned division 8455 __ xchgl($dst$$Register, $tmp2$$Register); 8456 // Fallthrow for final divide, tmp2 has 32 bit hi result 8457 8458 __ bind(Lfast); 8459 // fast path: src is positive 8460 __ divl($tmp$$Register); // Use unsigned division 8461 8462 __ bind(Ldone); 8463 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); 8464 if (con < 0) { 8465 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); 8466 } 8467 %} 8468 ins_pipe( pipe_slow ); 8469 %} 8470 8471 // Remainder Register Long (remainder fit into 32 bits) 8472 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ 8473 match(Set dst (ModL dst imm)); 8474 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8475 ins_cost(1000); 8476 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" 8477 "CMP $tmp,EDX\n\t" 8478 "JA,s fast\n\t" 8479 "MOV $tmp2,EAX\n\t" 8480 "MOV EAX,EDX\n\t" 8481 "MOV EDX,0\n\t" 8482 "JLE,s pos\n\t" 8483 "LNEG EAX : $tmp2\n\t" 8484 "DIV $tmp # unsigned division\n\t" 8485 "MOV EAX,$tmp2\n\t" 8486 "DIV $tmp\n\t" 8487 "NEG EDX\n\t" 8488 "JMP,s done\n" 8489 "pos:\n\t" 8490 "DIV $tmp\n\t" 8491 "MOV EAX,$tmp2\n" 8492 "fast:\n\t" 8493 "DIV $tmp\n" 8494 "done:\n\t" 8495 "MOV EAX,EDX\n\t" 8496 "SAR EDX,31\n\t" %} 8497 ins_encode %{ 8498 int con = (int)$imm$$constant; 8499 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); 8500 int pcon = (con > 0) ? con : -con; 8501 Label Lfast, Lpos, Ldone; 8502 8503 __ movl($tmp$$Register, pcon); 8504 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); 8505 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit 8506 8507 __ movl($tmp2$$Register, $dst$$Register); // save 8508 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8509 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags 8510 __ jccb(Assembler::lessEqual, Lpos); // result is positive 8511 8512 // Negative dividend. 8513 // convert value to positive to use unsigned division 8514 __ lneg($dst$$Register, $tmp2$$Register); 8515 __ divl($tmp$$Register); 8516 __ movl($dst$$Register, $tmp2$$Register); 8517 __ divl($tmp$$Register); 8518 // revert remainder back to negative 8519 __ negl(HIGH_FROM_LOW($dst$$Register)); 8520 __ jmpb(Ldone); 8521 8522 __ bind(Lpos); 8523 __ divl($tmp$$Register); 8524 __ movl($dst$$Register, $tmp2$$Register); 8525 8526 __ bind(Lfast); 8527 // fast path: src is positive 8528 __ divl($tmp$$Register); 8529 8530 __ bind(Ldone); 8531 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8532 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign 8533 8534 %} 8535 ins_pipe( pipe_slow ); 8536 %} 8537 8538 // Integer Shift Instructions 8539 // Shift Left by one 8540 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8541 match(Set dst (LShiftI dst shift)); 8542 effect(KILL cr); 8543 8544 size(2); 8545 format %{ "SHL $dst,$shift" %} 8546 opcode(0xD1, 0x4); /* D1 /4 */ 8547 ins_encode( OpcP, RegOpc( dst ) ); 8548 ins_pipe( ialu_reg ); 8549 %} 8550 8551 // Shift Left by 8-bit immediate 8552 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8553 match(Set dst (LShiftI dst shift)); 8554 effect(KILL cr); 8555 8556 size(3); 8557 format %{ "SHL $dst,$shift" %} 8558 opcode(0xC1, 0x4); /* C1 /4 ib */ 8559 ins_encode( RegOpcImm( dst, shift) ); 8560 ins_pipe( ialu_reg ); 8561 %} 8562 8563 // Shift Left by variable 8564 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8565 match(Set dst (LShiftI dst shift)); 8566 effect(KILL cr); 8567 8568 size(2); 8569 format %{ "SHL $dst,$shift" %} 8570 opcode(0xD3, 0x4); /* D3 /4 */ 8571 ins_encode( OpcP, RegOpc( dst ) ); 8572 ins_pipe( ialu_reg_reg ); 8573 %} 8574 8575 // Arithmetic shift right by one 8576 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8577 match(Set dst (RShiftI dst shift)); 8578 effect(KILL cr); 8579 8580 size(2); 8581 format %{ "SAR $dst,$shift" %} 8582 opcode(0xD1, 0x7); /* D1 /7 */ 8583 ins_encode( OpcP, RegOpc( dst ) ); 8584 ins_pipe( ialu_reg ); 8585 %} 8586 8587 // Arithmetic shift right by one 8588 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ 8589 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8590 effect(KILL cr); 8591 format %{ "SAR $dst,$shift" %} 8592 opcode(0xD1, 0x7); /* D1 /7 */ 8593 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8594 ins_pipe( ialu_mem_imm ); 8595 %} 8596 8597 // Arithmetic Shift Right by 8-bit immediate 8598 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8599 match(Set dst (RShiftI dst shift)); 8600 effect(KILL cr); 8601 8602 size(3); 8603 format %{ "SAR $dst,$shift" %} 8604 opcode(0xC1, 0x7); /* C1 /7 ib */ 8605 ins_encode( RegOpcImm( dst, shift ) ); 8606 ins_pipe( ialu_mem_imm ); 8607 %} 8608 8609 // Arithmetic Shift Right by 8-bit immediate 8610 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ 8611 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8612 effect(KILL cr); 8613 8614 format %{ "SAR $dst,$shift" %} 8615 opcode(0xC1, 0x7); /* C1 /7 ib */ 8616 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8617 ins_pipe( ialu_mem_imm ); 8618 %} 8619 8620 // Arithmetic Shift Right by variable 8621 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8622 match(Set dst (RShiftI dst shift)); 8623 effect(KILL cr); 8624 8625 size(2); 8626 format %{ "SAR $dst,$shift" %} 8627 opcode(0xD3, 0x7); /* D3 /7 */ 8628 ins_encode( OpcP, RegOpc( dst ) ); 8629 ins_pipe( ialu_reg_reg ); 8630 %} 8631 8632 // Logical shift right by one 8633 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8634 match(Set dst (URShiftI dst shift)); 8635 effect(KILL cr); 8636 8637 size(2); 8638 format %{ "SHR $dst,$shift" %} 8639 opcode(0xD1, 0x5); /* D1 /5 */ 8640 ins_encode( OpcP, RegOpc( dst ) ); 8641 ins_pipe( ialu_reg ); 8642 %} 8643 8644 // Logical Shift Right by 8-bit immediate 8645 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8646 match(Set dst (URShiftI dst shift)); 8647 effect(KILL cr); 8648 8649 size(3); 8650 format %{ "SHR $dst,$shift" %} 8651 opcode(0xC1, 0x5); /* C1 /5 ib */ 8652 ins_encode( RegOpcImm( dst, shift) ); 8653 ins_pipe( ialu_reg ); 8654 %} 8655 8656 8657 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8658 // This idiom is used by the compiler for the i2b bytecode. 8659 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ 8660 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8661 8662 size(3); 8663 format %{ "MOVSX $dst,$src :8" %} 8664 ins_encode %{ 8665 __ movsbl($dst$$Register, $src$$Register); 8666 %} 8667 ins_pipe(ialu_reg_reg); 8668 %} 8669 8670 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8671 // This idiom is used by the compiler the i2s bytecode. 8672 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ 8673 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8674 8675 size(3); 8676 format %{ "MOVSX $dst,$src :16" %} 8677 ins_encode %{ 8678 __ movswl($dst$$Register, $src$$Register); 8679 %} 8680 ins_pipe(ialu_reg_reg); 8681 %} 8682 8683 8684 // Logical Shift Right by variable 8685 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8686 match(Set dst (URShiftI dst shift)); 8687 effect(KILL cr); 8688 8689 size(2); 8690 format %{ "SHR $dst,$shift" %} 8691 opcode(0xD3, 0x5); /* D3 /5 */ 8692 ins_encode( OpcP, RegOpc( dst ) ); 8693 ins_pipe( ialu_reg_reg ); 8694 %} 8695 8696 8697 //----------Logical Instructions----------------------------------------------- 8698 //----------Integer Logical Instructions--------------------------------------- 8699 // And Instructions 8700 // And Register with Register 8701 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8702 match(Set dst (AndI dst src)); 8703 effect(KILL cr); 8704 8705 size(2); 8706 format %{ "AND $dst,$src" %} 8707 opcode(0x23); 8708 ins_encode( OpcP, RegReg( dst, src) ); 8709 ins_pipe( ialu_reg_reg ); 8710 %} 8711 8712 // And Register with Immediate 8713 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8714 match(Set dst (AndI dst src)); 8715 effect(KILL cr); 8716 8717 format %{ "AND $dst,$src" %} 8718 opcode(0x81,0x04); /* Opcode 81 /4 */ 8719 // ins_encode( RegImm( dst, src) ); 8720 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8721 ins_pipe( ialu_reg ); 8722 %} 8723 8724 // And Register with Memory 8725 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8726 match(Set dst (AndI dst (LoadI src))); 8727 effect(KILL cr); 8728 8729 ins_cost(125); 8730 format %{ "AND $dst,$src" %} 8731 opcode(0x23); 8732 ins_encode( OpcP, RegMem( dst, src) ); 8733 ins_pipe( ialu_reg_mem ); 8734 %} 8735 8736 // And Memory with Register 8737 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8738 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8739 effect(KILL cr); 8740 8741 ins_cost(150); 8742 format %{ "AND $dst,$src" %} 8743 opcode(0x21); /* Opcode 21 /r */ 8744 ins_encode( OpcP, RegMem( src, dst ) ); 8745 ins_pipe( ialu_mem_reg ); 8746 %} 8747 8748 // And Memory with Immediate 8749 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8750 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8751 effect(KILL cr); 8752 8753 ins_cost(125); 8754 format %{ "AND $dst,$src" %} 8755 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 8756 // ins_encode( MemImm( dst, src) ); 8757 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8758 ins_pipe( ialu_mem_imm ); 8759 %} 8760 8761 // Or Instructions 8762 // Or Register with Register 8763 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8764 match(Set dst (OrI dst src)); 8765 effect(KILL cr); 8766 8767 size(2); 8768 format %{ "OR $dst,$src" %} 8769 opcode(0x0B); 8770 ins_encode( OpcP, RegReg( dst, src) ); 8771 ins_pipe( ialu_reg_reg ); 8772 %} 8773 8774 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ 8775 match(Set dst (OrI dst (CastP2X src))); 8776 effect(KILL cr); 8777 8778 size(2); 8779 format %{ "OR $dst,$src" %} 8780 opcode(0x0B); 8781 ins_encode( OpcP, RegReg( dst, src) ); 8782 ins_pipe( ialu_reg_reg ); 8783 %} 8784 8785 8786 // Or Register with Immediate 8787 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8788 match(Set dst (OrI dst src)); 8789 effect(KILL cr); 8790 8791 format %{ "OR $dst,$src" %} 8792 opcode(0x81,0x01); /* Opcode 81 /1 id */ 8793 // ins_encode( RegImm( dst, src) ); 8794 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8795 ins_pipe( ialu_reg ); 8796 %} 8797 8798 // Or Register with Memory 8799 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8800 match(Set dst (OrI dst (LoadI src))); 8801 effect(KILL cr); 8802 8803 ins_cost(125); 8804 format %{ "OR $dst,$src" %} 8805 opcode(0x0B); 8806 ins_encode( OpcP, RegMem( dst, src) ); 8807 ins_pipe( ialu_reg_mem ); 8808 %} 8809 8810 // Or Memory with Register 8811 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8812 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8813 effect(KILL cr); 8814 8815 ins_cost(150); 8816 format %{ "OR $dst,$src" %} 8817 opcode(0x09); /* Opcode 09 /r */ 8818 ins_encode( OpcP, RegMem( src, dst ) ); 8819 ins_pipe( ialu_mem_reg ); 8820 %} 8821 8822 // Or Memory with Immediate 8823 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8824 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8825 effect(KILL cr); 8826 8827 ins_cost(125); 8828 format %{ "OR $dst,$src" %} 8829 opcode(0x81,0x1); /* Opcode 81 /1 id */ 8830 // ins_encode( MemImm( dst, src) ); 8831 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8832 ins_pipe( ialu_mem_imm ); 8833 %} 8834 8835 // ROL/ROR 8836 // ROL expand 8837 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8838 effect(USE_DEF dst, USE shift, KILL cr); 8839 8840 format %{ "ROL $dst, $shift" %} 8841 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 8842 ins_encode( OpcP, RegOpc( dst )); 8843 ins_pipe( ialu_reg ); 8844 %} 8845 8846 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8847 effect(USE_DEF dst, USE shift, KILL cr); 8848 8849 format %{ "ROL $dst, $shift" %} 8850 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 8851 ins_encode( RegOpcImm(dst, shift) ); 8852 ins_pipe(ialu_reg); 8853 %} 8854 8855 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8856 effect(USE_DEF dst, USE shift, KILL cr); 8857 8858 format %{ "ROL $dst, $shift" %} 8859 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 8860 ins_encode(OpcP, RegOpc(dst)); 8861 ins_pipe( ialu_reg_reg ); 8862 %} 8863 // end of ROL expand 8864 8865 // ROL 32bit by one once 8866 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 8867 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8868 8869 expand %{ 8870 rolI_eReg_imm1(dst, lshift, cr); 8871 %} 8872 %} 8873 8874 // ROL 32bit var by imm8 once 8875 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 8876 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8877 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8878 8879 expand %{ 8880 rolI_eReg_imm8(dst, lshift, cr); 8881 %} 8882 %} 8883 8884 // ROL 32bit var by var once 8885 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8886 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 8887 8888 expand %{ 8889 rolI_eReg_CL(dst, shift, cr); 8890 %} 8891 %} 8892 8893 // ROL 32bit var by var once 8894 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8895 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 8896 8897 expand %{ 8898 rolI_eReg_CL(dst, shift, cr); 8899 %} 8900 %} 8901 8902 // ROR expand 8903 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8904 effect(USE_DEF dst, USE shift, KILL cr); 8905 8906 format %{ "ROR $dst, $shift" %} 8907 opcode(0xD1,0x1); /* Opcode D1 /1 */ 8908 ins_encode( OpcP, RegOpc( dst ) ); 8909 ins_pipe( ialu_reg ); 8910 %} 8911 8912 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8913 effect (USE_DEF dst, USE shift, KILL cr); 8914 8915 format %{ "ROR $dst, $shift" %} 8916 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 8917 ins_encode( RegOpcImm(dst, shift) ); 8918 ins_pipe( ialu_reg ); 8919 %} 8920 8921 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ 8922 effect(USE_DEF dst, USE shift, KILL cr); 8923 8924 format %{ "ROR $dst, $shift" %} 8925 opcode(0xD3, 0x1); /* Opcode D3 /1 */ 8926 ins_encode(OpcP, RegOpc(dst)); 8927 ins_pipe( ialu_reg_reg ); 8928 %} 8929 // end of ROR expand 8930 8931 // ROR right once 8932 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 8933 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8934 8935 expand %{ 8936 rorI_eReg_imm1(dst, rshift, cr); 8937 %} 8938 %} 8939 8940 // ROR 32bit by immI8 once 8941 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 8942 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8943 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8944 8945 expand %{ 8946 rorI_eReg_imm8(dst, rshift, cr); 8947 %} 8948 %} 8949 8950 // ROR 32bit var by var once 8951 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8952 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 8953 8954 expand %{ 8955 rorI_eReg_CL(dst, shift, cr); 8956 %} 8957 %} 8958 8959 // ROR 32bit var by var once 8960 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8961 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 8962 8963 expand %{ 8964 rorI_eReg_CL(dst, shift, cr); 8965 %} 8966 %} 8967 8968 // Xor Instructions 8969 // Xor Register with Register 8970 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8971 match(Set dst (XorI dst src)); 8972 effect(KILL cr); 8973 8974 size(2); 8975 format %{ "XOR $dst,$src" %} 8976 opcode(0x33); 8977 ins_encode( OpcP, RegReg( dst, src) ); 8978 ins_pipe( ialu_reg_reg ); 8979 %} 8980 8981 // Xor Register with Immediate -1 8982 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ 8983 match(Set dst (XorI dst imm)); 8984 8985 size(2); 8986 format %{ "NOT $dst" %} 8987 ins_encode %{ 8988 __ notl($dst$$Register); 8989 %} 8990 ins_pipe( ialu_reg ); 8991 %} 8992 8993 // Xor Register with Immediate 8994 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8995 match(Set dst (XorI dst src)); 8996 effect(KILL cr); 8997 8998 format %{ "XOR $dst,$src" %} 8999 opcode(0x81,0x06); /* Opcode 81 /6 id */ 9000 // ins_encode( RegImm( dst, src) ); 9001 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 9002 ins_pipe( ialu_reg ); 9003 %} 9004 9005 // Xor Register with Memory 9006 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 9007 match(Set dst (XorI dst (LoadI src))); 9008 effect(KILL cr); 9009 9010 ins_cost(125); 9011 format %{ "XOR $dst,$src" %} 9012 opcode(0x33); 9013 ins_encode( OpcP, RegMem(dst, src) ); 9014 ins_pipe( ialu_reg_mem ); 9015 %} 9016 9017 // Xor Memory with Register 9018 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 9019 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9020 effect(KILL cr); 9021 9022 ins_cost(150); 9023 format %{ "XOR $dst,$src" %} 9024 opcode(0x31); /* Opcode 31 /r */ 9025 ins_encode( OpcP, RegMem( src, dst ) ); 9026 ins_pipe( ialu_mem_reg ); 9027 %} 9028 9029 // Xor Memory with Immediate 9030 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 9031 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 9032 effect(KILL cr); 9033 9034 ins_cost(125); 9035 format %{ "XOR $dst,$src" %} 9036 opcode(0x81,0x6); /* Opcode 81 /6 id */ 9037 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 9038 ins_pipe( ialu_mem_imm ); 9039 %} 9040 9041 //----------Convert Int to Boolean--------------------------------------------- 9042 9043 instruct movI_nocopy(eRegI dst, eRegI src) %{ 9044 effect( DEF dst, USE src ); 9045 format %{ "MOV $dst,$src" %} 9046 ins_encode( enc_Copy( dst, src) ); 9047 ins_pipe( ialu_reg_reg ); 9048 %} 9049 9050 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ 9051 effect( USE_DEF dst, USE src, KILL cr ); 9052 9053 size(4); 9054 format %{ "NEG $dst\n\t" 9055 "ADC $dst,$src" %} 9056 ins_encode( neg_reg(dst), 9057 OpcRegReg(0x13,dst,src) ); 9058 ins_pipe( ialu_reg_reg_long ); 9059 %} 9060 9061 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ 9062 match(Set dst (Conv2B src)); 9063 9064 expand %{ 9065 movI_nocopy(dst,src); 9066 ci2b(dst,src,cr); 9067 %} 9068 %} 9069 9070 instruct movP_nocopy(eRegI dst, eRegP src) %{ 9071 effect( DEF dst, USE src ); 9072 format %{ "MOV $dst,$src" %} 9073 ins_encode( enc_Copy( dst, src) ); 9074 ins_pipe( ialu_reg_reg ); 9075 %} 9076 9077 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ 9078 effect( USE_DEF dst, USE src, KILL cr ); 9079 format %{ "NEG $dst\n\t" 9080 "ADC $dst,$src" %} 9081 ins_encode( neg_reg(dst), 9082 OpcRegReg(0x13,dst,src) ); 9083 ins_pipe( ialu_reg_reg_long ); 9084 %} 9085 9086 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ 9087 match(Set dst (Conv2B src)); 9088 9089 expand %{ 9090 movP_nocopy(dst,src); 9091 cp2b(dst,src,cr); 9092 %} 9093 %} 9094 9095 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ 9096 match(Set dst (CmpLTMask p q)); 9097 effect( KILL cr ); 9098 ins_cost(400); 9099 9100 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination 9101 format %{ "XOR $dst,$dst\n\t" 9102 "CMP $p,$q\n\t" 9103 "SETlt $dst\n\t" 9104 "NEG $dst" %} 9105 ins_encode( OpcRegReg(0x33,dst,dst), 9106 OpcRegReg(0x3B,p,q), 9107 setLT_reg(dst), neg_reg(dst) ); 9108 ins_pipe( pipe_slow ); 9109 %} 9110 9111 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ 9112 match(Set dst (CmpLTMask dst zero)); 9113 effect( DEF dst, KILL cr ); 9114 ins_cost(100); 9115 9116 format %{ "SAR $dst,31" %} 9117 opcode(0xC1, 0x7); /* C1 /7 ib */ 9118 ins_encode( RegOpcImm( dst, 0x1F ) ); 9119 ins_pipe( ialu_reg ); 9120 %} 9121 9122 9123 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ 9124 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 9125 effect( KILL tmp, KILL cr ); 9126 ins_cost(400); 9127 // annoyingly, $tmp has no edges so you cant ask for it in 9128 // any format or encoding 9129 format %{ "SUB $p,$q\n\t" 9130 "SBB ECX,ECX\n\t" 9131 "AND ECX,$y\n\t" 9132 "ADD $p,ECX" %} 9133 ins_encode( enc_cmpLTP(p,q,y,tmp) ); 9134 ins_pipe( pipe_cmplt ); 9135 %} 9136 9137 /* If I enable this, I encourage spilling in the inner loop of compress. 9138 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ 9139 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); 9140 effect( USE_KILL tmp, KILL cr ); 9141 ins_cost(400); 9142 9143 format %{ "SUB $p,$q\n\t" 9144 "SBB ECX,ECX\n\t" 9145 "AND ECX,$y\n\t" 9146 "ADD $p,ECX" %} 9147 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); 9148 %} 9149 */ 9150 9151 //----------Long Instructions------------------------------------------------ 9152 // Add Long Register with Register 9153 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9154 match(Set dst (AddL dst src)); 9155 effect(KILL cr); 9156 ins_cost(200); 9157 format %{ "ADD $dst.lo,$src.lo\n\t" 9158 "ADC $dst.hi,$src.hi" %} 9159 opcode(0x03, 0x13); 9160 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9161 ins_pipe( ialu_reg_reg_long ); 9162 %} 9163 9164 // Add Long Register with Immediate 9165 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9166 match(Set dst (AddL dst src)); 9167 effect(KILL cr); 9168 format %{ "ADD $dst.lo,$src.lo\n\t" 9169 "ADC $dst.hi,$src.hi" %} 9170 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ 9171 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9172 ins_pipe( ialu_reg_long ); 9173 %} 9174 9175 // Add Long Register with Memory 9176 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9177 match(Set dst (AddL dst (LoadL mem))); 9178 effect(KILL cr); 9179 ins_cost(125); 9180 format %{ "ADD $dst.lo,$mem\n\t" 9181 "ADC $dst.hi,$mem+4" %} 9182 opcode(0x03, 0x13); 9183 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9184 ins_pipe( ialu_reg_long_mem ); 9185 %} 9186 9187 // Subtract Long Register with Register. 9188 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9189 match(Set dst (SubL dst src)); 9190 effect(KILL cr); 9191 ins_cost(200); 9192 format %{ "SUB $dst.lo,$src.lo\n\t" 9193 "SBB $dst.hi,$src.hi" %} 9194 opcode(0x2B, 0x1B); 9195 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9196 ins_pipe( ialu_reg_reg_long ); 9197 %} 9198 9199 // Subtract Long Register with Immediate 9200 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9201 match(Set dst (SubL dst src)); 9202 effect(KILL cr); 9203 format %{ "SUB $dst.lo,$src.lo\n\t" 9204 "SBB $dst.hi,$src.hi" %} 9205 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ 9206 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9207 ins_pipe( ialu_reg_long ); 9208 %} 9209 9210 // Subtract Long Register with Memory 9211 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9212 match(Set dst (SubL dst (LoadL mem))); 9213 effect(KILL cr); 9214 ins_cost(125); 9215 format %{ "SUB $dst.lo,$mem\n\t" 9216 "SBB $dst.hi,$mem+4" %} 9217 opcode(0x2B, 0x1B); 9218 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9219 ins_pipe( ialu_reg_long_mem ); 9220 %} 9221 9222 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ 9223 match(Set dst (SubL zero dst)); 9224 effect(KILL cr); 9225 ins_cost(300); 9226 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} 9227 ins_encode( neg_long(dst) ); 9228 ins_pipe( ialu_reg_reg_long ); 9229 %} 9230 9231 // And Long Register with Register 9232 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9233 match(Set dst (AndL dst src)); 9234 effect(KILL cr); 9235 format %{ "AND $dst.lo,$src.lo\n\t" 9236 "AND $dst.hi,$src.hi" %} 9237 opcode(0x23,0x23); 9238 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9239 ins_pipe( ialu_reg_reg_long ); 9240 %} 9241 9242 // And Long Register with Immediate 9243 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9244 match(Set dst (AndL dst src)); 9245 effect(KILL cr); 9246 format %{ "AND $dst.lo,$src.lo\n\t" 9247 "AND $dst.hi,$src.hi" %} 9248 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ 9249 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9250 ins_pipe( ialu_reg_long ); 9251 %} 9252 9253 // And Long Register with Memory 9254 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9255 match(Set dst (AndL dst (LoadL mem))); 9256 effect(KILL cr); 9257 ins_cost(125); 9258 format %{ "AND $dst.lo,$mem\n\t" 9259 "AND $dst.hi,$mem+4" %} 9260 opcode(0x23, 0x23); 9261 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9262 ins_pipe( ialu_reg_long_mem ); 9263 %} 9264 9265 // Or Long Register with Register 9266 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9267 match(Set dst (OrL dst src)); 9268 effect(KILL cr); 9269 format %{ "OR $dst.lo,$src.lo\n\t" 9270 "OR $dst.hi,$src.hi" %} 9271 opcode(0x0B,0x0B); 9272 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9273 ins_pipe( ialu_reg_reg_long ); 9274 %} 9275 9276 // Or Long Register with Immediate 9277 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9278 match(Set dst (OrL dst src)); 9279 effect(KILL cr); 9280 format %{ "OR $dst.lo,$src.lo\n\t" 9281 "OR $dst.hi,$src.hi" %} 9282 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ 9283 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9284 ins_pipe( ialu_reg_long ); 9285 %} 9286 9287 // Or Long Register with Memory 9288 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9289 match(Set dst (OrL dst (LoadL mem))); 9290 effect(KILL cr); 9291 ins_cost(125); 9292 format %{ "OR $dst.lo,$mem\n\t" 9293 "OR $dst.hi,$mem+4" %} 9294 opcode(0x0B,0x0B); 9295 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9296 ins_pipe( ialu_reg_long_mem ); 9297 %} 9298 9299 // Xor Long Register with Register 9300 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9301 match(Set dst (XorL dst src)); 9302 effect(KILL cr); 9303 format %{ "XOR $dst.lo,$src.lo\n\t" 9304 "XOR $dst.hi,$src.hi" %} 9305 opcode(0x33,0x33); 9306 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9307 ins_pipe( ialu_reg_reg_long ); 9308 %} 9309 9310 // Xor Long Register with Immediate -1 9311 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ 9312 match(Set dst (XorL dst imm)); 9313 format %{ "NOT $dst.lo\n\t" 9314 "NOT $dst.hi" %} 9315 ins_encode %{ 9316 __ notl($dst$$Register); 9317 __ notl(HIGH_FROM_LOW($dst$$Register)); 9318 %} 9319 ins_pipe( ialu_reg_long ); 9320 %} 9321 9322 // Xor Long Register with Immediate 9323 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9324 match(Set dst (XorL dst src)); 9325 effect(KILL cr); 9326 format %{ "XOR $dst.lo,$src.lo\n\t" 9327 "XOR $dst.hi,$src.hi" %} 9328 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ 9329 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9330 ins_pipe( ialu_reg_long ); 9331 %} 9332 9333 // Xor Long Register with Memory 9334 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9335 match(Set dst (XorL dst (LoadL mem))); 9336 effect(KILL cr); 9337 ins_cost(125); 9338 format %{ "XOR $dst.lo,$mem\n\t" 9339 "XOR $dst.hi,$mem+4" %} 9340 opcode(0x33,0x33); 9341 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9342 ins_pipe( ialu_reg_long_mem ); 9343 %} 9344 9345 // Shift Left Long by 1 9346 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ 9347 predicate(UseNewLongLShift); 9348 match(Set dst (LShiftL dst cnt)); 9349 effect(KILL cr); 9350 ins_cost(100); 9351 format %{ "ADD $dst.lo,$dst.lo\n\t" 9352 "ADC $dst.hi,$dst.hi" %} 9353 ins_encode %{ 9354 __ addl($dst$$Register,$dst$$Register); 9355 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9356 %} 9357 ins_pipe( ialu_reg_long ); 9358 %} 9359 9360 // Shift Left Long by 2 9361 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ 9362 predicate(UseNewLongLShift); 9363 match(Set dst (LShiftL dst cnt)); 9364 effect(KILL cr); 9365 ins_cost(100); 9366 format %{ "ADD $dst.lo,$dst.lo\n\t" 9367 "ADC $dst.hi,$dst.hi\n\t" 9368 "ADD $dst.lo,$dst.lo\n\t" 9369 "ADC $dst.hi,$dst.hi" %} 9370 ins_encode %{ 9371 __ addl($dst$$Register,$dst$$Register); 9372 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9373 __ addl($dst$$Register,$dst$$Register); 9374 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9375 %} 9376 ins_pipe( ialu_reg_long ); 9377 %} 9378 9379 // Shift Left Long by 3 9380 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ 9381 predicate(UseNewLongLShift); 9382 match(Set dst (LShiftL dst cnt)); 9383 effect(KILL cr); 9384 ins_cost(100); 9385 format %{ "ADD $dst.lo,$dst.lo\n\t" 9386 "ADC $dst.hi,$dst.hi\n\t" 9387 "ADD $dst.lo,$dst.lo\n\t" 9388 "ADC $dst.hi,$dst.hi\n\t" 9389 "ADD $dst.lo,$dst.lo\n\t" 9390 "ADC $dst.hi,$dst.hi" %} 9391 ins_encode %{ 9392 __ addl($dst$$Register,$dst$$Register); 9393 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9394 __ addl($dst$$Register,$dst$$Register); 9395 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9396 __ addl($dst$$Register,$dst$$Register); 9397 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9398 %} 9399 ins_pipe( ialu_reg_long ); 9400 %} 9401 9402 // Shift Left Long by 1-31 9403 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9404 match(Set dst (LShiftL dst cnt)); 9405 effect(KILL cr); 9406 ins_cost(200); 9407 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" 9408 "SHL $dst.lo,$cnt" %} 9409 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ 9410 ins_encode( move_long_small_shift(dst,cnt) ); 9411 ins_pipe( ialu_reg_long ); 9412 %} 9413 9414 // Shift Left Long by 32-63 9415 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9416 match(Set dst (LShiftL dst cnt)); 9417 effect(KILL cr); 9418 ins_cost(300); 9419 format %{ "MOV $dst.hi,$dst.lo\n" 9420 "\tSHL $dst.hi,$cnt-32\n" 9421 "\tXOR $dst.lo,$dst.lo" %} 9422 opcode(0xC1, 0x4); /* C1 /4 ib */ 9423 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9424 ins_pipe( ialu_reg_long ); 9425 %} 9426 9427 // Shift Left Long by variable 9428 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9429 match(Set dst (LShiftL dst shift)); 9430 effect(KILL cr); 9431 ins_cost(500+200); 9432 size(17); 9433 format %{ "TEST $shift,32\n\t" 9434 "JEQ,s small\n\t" 9435 "MOV $dst.hi,$dst.lo\n\t" 9436 "XOR $dst.lo,$dst.lo\n" 9437 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" 9438 "SHL $dst.lo,$shift" %} 9439 ins_encode( shift_left_long( dst, shift ) ); 9440 ins_pipe( pipe_slow ); 9441 %} 9442 9443 // Shift Right Long by 1-31 9444 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9445 match(Set dst (URShiftL dst cnt)); 9446 effect(KILL cr); 9447 ins_cost(200); 9448 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9449 "SHR $dst.hi,$cnt" %} 9450 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ 9451 ins_encode( move_long_small_shift(dst,cnt) ); 9452 ins_pipe( ialu_reg_long ); 9453 %} 9454 9455 // Shift Right Long by 32-63 9456 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9457 match(Set dst (URShiftL dst cnt)); 9458 effect(KILL cr); 9459 ins_cost(300); 9460 format %{ "MOV $dst.lo,$dst.hi\n" 9461 "\tSHR $dst.lo,$cnt-32\n" 9462 "\tXOR $dst.hi,$dst.hi" %} 9463 opcode(0xC1, 0x5); /* C1 /5 ib */ 9464 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9465 ins_pipe( ialu_reg_long ); 9466 %} 9467 9468 // Shift Right Long by variable 9469 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9470 match(Set dst (URShiftL dst shift)); 9471 effect(KILL cr); 9472 ins_cost(600); 9473 size(17); 9474 format %{ "TEST $shift,32\n\t" 9475 "JEQ,s small\n\t" 9476 "MOV $dst.lo,$dst.hi\n\t" 9477 "XOR $dst.hi,$dst.hi\n" 9478 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9479 "SHR $dst.hi,$shift" %} 9480 ins_encode( shift_right_long( dst, shift ) ); 9481 ins_pipe( pipe_slow ); 9482 %} 9483 9484 // Shift Right Long by 1-31 9485 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9486 match(Set dst (RShiftL dst cnt)); 9487 effect(KILL cr); 9488 ins_cost(200); 9489 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9490 "SAR $dst.hi,$cnt" %} 9491 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ 9492 ins_encode( move_long_small_shift(dst,cnt) ); 9493 ins_pipe( ialu_reg_long ); 9494 %} 9495 9496 // Shift Right Long by 32-63 9497 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9498 match(Set dst (RShiftL dst cnt)); 9499 effect(KILL cr); 9500 ins_cost(300); 9501 format %{ "MOV $dst.lo,$dst.hi\n" 9502 "\tSAR $dst.lo,$cnt-32\n" 9503 "\tSAR $dst.hi,31" %} 9504 opcode(0xC1, 0x7); /* C1 /7 ib */ 9505 ins_encode( move_long_big_shift_sign(dst,cnt) ); 9506 ins_pipe( ialu_reg_long ); 9507 %} 9508 9509 // Shift Right arithmetic Long by variable 9510 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9511 match(Set dst (RShiftL dst shift)); 9512 effect(KILL cr); 9513 ins_cost(600); 9514 size(18); 9515 format %{ "TEST $shift,32\n\t" 9516 "JEQ,s small\n\t" 9517 "MOV $dst.lo,$dst.hi\n\t" 9518 "SAR $dst.hi,31\n" 9519 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9520 "SAR $dst.hi,$shift" %} 9521 ins_encode( shift_right_arith_long( dst, shift ) ); 9522 ins_pipe( pipe_slow ); 9523 %} 9524 9525 9526 //----------Double Instructions------------------------------------------------ 9527 // Double Math 9528 9529 // Compare & branch 9530 9531 // P6 version of float compare, sets condition codes in EFLAGS 9532 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ 9533 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9534 match(Set cr (CmpD src1 src2)); 9535 effect(KILL rax); 9536 ins_cost(150); 9537 format %{ "FLD $src1\n\t" 9538 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9539 "JNP exit\n\t" 9540 "MOV ah,1 // saw a NaN, set CF\n\t" 9541 "SAHF\n" 9542 "exit:\tNOP // avoid branch to branch" %} 9543 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9544 ins_encode( Push_Reg_DPR(src1), 9545 OpcP, RegOpc(src2), 9546 cmpF_P6_fixup ); 9547 ins_pipe( pipe_slow ); 9548 %} 9549 9550 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ 9551 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9552 match(Set cr (CmpD src1 src2)); 9553 ins_cost(150); 9554 format %{ "FLD $src1\n\t" 9555 "FUCOMIP ST,$src2 // P6 instruction" %} 9556 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9557 ins_encode( Push_Reg_DPR(src1), 9558 OpcP, RegOpc(src2)); 9559 ins_pipe( pipe_slow ); 9560 %} 9561 9562 // Compare & branch 9563 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ 9564 predicate(UseSSE<=1); 9565 match(Set cr (CmpD src1 src2)); 9566 effect(KILL rax); 9567 ins_cost(200); 9568 format %{ "FLD $src1\n\t" 9569 "FCOMp $src2\n\t" 9570 "FNSTSW AX\n\t" 9571 "TEST AX,0x400\n\t" 9572 "JZ,s flags\n\t" 9573 "MOV AH,1\t# unordered treat as LT\n" 9574 "flags:\tSAHF" %} 9575 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9576 ins_encode( Push_Reg_DPR(src1), 9577 OpcP, RegOpc(src2), 9578 fpu_flags); 9579 ins_pipe( pipe_slow ); 9580 %} 9581 9582 // Compare vs zero into -1,0,1 9583 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 9584 predicate(UseSSE<=1); 9585 match(Set dst (CmpD3 src1 zero)); 9586 effect(KILL cr, KILL rax); 9587 ins_cost(280); 9588 format %{ "FTSTD $dst,$src1" %} 9589 opcode(0xE4, 0xD9); 9590 ins_encode( Push_Reg_DPR(src1), 9591 OpcS, OpcP, PopFPU, 9592 CmpF_Result(dst)); 9593 ins_pipe( pipe_slow ); 9594 %} 9595 9596 // Compare into -1,0,1 9597 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ 9598 predicate(UseSSE<=1); 9599 match(Set dst (CmpD3 src1 src2)); 9600 effect(KILL cr, KILL rax); 9601 ins_cost(300); 9602 format %{ "FCMPD $dst,$src1,$src2" %} 9603 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9604 ins_encode( Push_Reg_DPR(src1), 9605 OpcP, RegOpc(src2), 9606 CmpF_Result(dst)); 9607 ins_pipe( pipe_slow ); 9608 %} 9609 9610 // float compare and set condition codes in EFLAGS by XMM regs 9611 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ 9612 predicate(UseSSE>=2); 9613 match(Set cr (CmpD src1 src2)); 9614 ins_cost(145); 9615 format %{ "UCOMISD $src1,$src2\n\t" 9616 "JNP,s exit\n\t" 9617 "PUSHF\t# saw NaN, set CF\n\t" 9618 "AND [rsp], #0xffffff2b\n\t" 9619 "POPF\n" 9620 "exit:" %} 9621 ins_encode %{ 9622 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9623 emit_cmpfp_fixup(_masm); 9624 %} 9625 ins_pipe( pipe_slow ); 9626 %} 9627 9628 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ 9629 predicate(UseSSE>=2); 9630 match(Set cr (CmpD src1 src2)); 9631 ins_cost(100); 9632 format %{ "UCOMISD $src1,$src2" %} 9633 ins_encode %{ 9634 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9635 %} 9636 ins_pipe( pipe_slow ); 9637 %} 9638 9639 // float compare and set condition codes in EFLAGS by XMM regs 9640 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ 9641 predicate(UseSSE>=2); 9642 match(Set cr (CmpD src1 (LoadD src2))); 9643 ins_cost(145); 9644 format %{ "UCOMISD $src1,$src2\n\t" 9645 "JNP,s exit\n\t" 9646 "PUSHF\t# saw NaN, set CF\n\t" 9647 "AND [rsp], #0xffffff2b\n\t" 9648 "POPF\n" 9649 "exit:" %} 9650 ins_encode %{ 9651 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9652 emit_cmpfp_fixup(_masm); 9653 %} 9654 ins_pipe( pipe_slow ); 9655 %} 9656 9657 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ 9658 predicate(UseSSE>=2); 9659 match(Set cr (CmpD src1 (LoadD src2))); 9660 ins_cost(100); 9661 format %{ "UCOMISD $src1,$src2" %} 9662 ins_encode %{ 9663 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9664 %} 9665 ins_pipe( pipe_slow ); 9666 %} 9667 9668 // Compare into -1,0,1 in XMM 9669 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ 9670 predicate(UseSSE>=2); 9671 match(Set dst (CmpD3 src1 src2)); 9672 effect(KILL cr); 9673 ins_cost(255); 9674 format %{ "UCOMISD $src1, $src2\n\t" 9675 "MOV $dst, #-1\n\t" 9676 "JP,s done\n\t" 9677 "JB,s done\n\t" 9678 "SETNE $dst\n\t" 9679 "MOVZB $dst, $dst\n" 9680 "done:" %} 9681 ins_encode %{ 9682 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9683 emit_cmpfp3(_masm, $dst$$Register); 9684 %} 9685 ins_pipe( pipe_slow ); 9686 %} 9687 9688 // Compare into -1,0,1 in XMM and memory 9689 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ 9690 predicate(UseSSE>=2); 9691 match(Set dst (CmpD3 src1 (LoadD src2))); 9692 effect(KILL cr); 9693 ins_cost(275); 9694 format %{ "UCOMISD $src1, $src2\n\t" 9695 "MOV $dst, #-1\n\t" 9696 "JP,s done\n\t" 9697 "JB,s done\n\t" 9698 "SETNE $dst\n\t" 9699 "MOVZB $dst, $dst\n" 9700 "done:" %} 9701 ins_encode %{ 9702 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9703 emit_cmpfp3(_masm, $dst$$Register); 9704 %} 9705 ins_pipe( pipe_slow ); 9706 %} 9707 9708 9709 instruct subDPR_reg(regDPR dst, regDPR src) %{ 9710 predicate (UseSSE <=1); 9711 match(Set dst (SubD dst src)); 9712 9713 format %{ "FLD $src\n\t" 9714 "DSUBp $dst,ST" %} 9715 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 9716 ins_cost(150); 9717 ins_encode( Push_Reg_DPR(src), 9718 OpcP, RegOpc(dst) ); 9719 ins_pipe( fpu_reg_reg ); 9720 %} 9721 9722 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 9723 predicate (UseSSE <=1); 9724 match(Set dst (RoundDouble (SubD src1 src2))); 9725 ins_cost(250); 9726 9727 format %{ "FLD $src2\n\t" 9728 "DSUB ST,$src1\n\t" 9729 "FSTP_D $dst\t# D-round" %} 9730 opcode(0xD8, 0x5); 9731 ins_encode( Push_Reg_DPR(src2), 9732 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); 9733 ins_pipe( fpu_mem_reg_reg ); 9734 %} 9735 9736 9737 instruct subDPR_reg_mem(regDPR dst, memory src) %{ 9738 predicate (UseSSE <=1); 9739 match(Set dst (SubD dst (LoadD src))); 9740 ins_cost(150); 9741 9742 format %{ "FLD $src\n\t" 9743 "DSUBp $dst,ST" %} 9744 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9745 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9746 OpcP, RegOpc(dst) ); 9747 ins_pipe( fpu_reg_mem ); 9748 %} 9749 9750 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ 9751 predicate (UseSSE<=1); 9752 match(Set dst (AbsD src)); 9753 ins_cost(100); 9754 format %{ "FABS" %} 9755 opcode(0xE1, 0xD9); 9756 ins_encode( OpcS, OpcP ); 9757 ins_pipe( fpu_reg_reg ); 9758 %} 9759 9760 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ 9761 predicate(UseSSE<=1); 9762 match(Set dst (NegD src)); 9763 ins_cost(100); 9764 format %{ "FCHS" %} 9765 opcode(0xE0, 0xD9); 9766 ins_encode( OpcS, OpcP ); 9767 ins_pipe( fpu_reg_reg ); 9768 %} 9769 9770 instruct addDPR_reg(regDPR dst, regDPR src) %{ 9771 predicate(UseSSE<=1); 9772 match(Set dst (AddD dst src)); 9773 format %{ "FLD $src\n\t" 9774 "DADD $dst,ST" %} 9775 size(4); 9776 ins_cost(150); 9777 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 9778 ins_encode( Push_Reg_DPR(src), 9779 OpcP, RegOpc(dst) ); 9780 ins_pipe( fpu_reg_reg ); 9781 %} 9782 9783 9784 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 9785 predicate(UseSSE<=1); 9786 match(Set dst (RoundDouble (AddD src1 src2))); 9787 ins_cost(250); 9788 9789 format %{ "FLD $src2\n\t" 9790 "DADD ST,$src1\n\t" 9791 "FSTP_D $dst\t# D-round" %} 9792 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ 9793 ins_encode( Push_Reg_DPR(src2), 9794 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); 9795 ins_pipe( fpu_mem_reg_reg ); 9796 %} 9797 9798 9799 instruct addDPR_reg_mem(regDPR dst, memory src) %{ 9800 predicate(UseSSE<=1); 9801 match(Set dst (AddD dst (LoadD src))); 9802 ins_cost(150); 9803 9804 format %{ "FLD $src\n\t" 9805 "DADDp $dst,ST" %} 9806 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9807 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9808 OpcP, RegOpc(dst) ); 9809 ins_pipe( fpu_reg_mem ); 9810 %} 9811 9812 // add-to-memory 9813 instruct addDPR_mem_reg(memory dst, regDPR src) %{ 9814 predicate(UseSSE<=1); 9815 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); 9816 ins_cost(150); 9817 9818 format %{ "FLD_D $dst\n\t" 9819 "DADD ST,$src\n\t" 9820 "FST_D $dst" %} 9821 opcode(0xDD, 0x0); 9822 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), 9823 Opcode(0xD8), RegOpc(src), 9824 set_instruction_start, 9825 Opcode(0xDD), RMopc_Mem(0x03,dst) ); 9826 ins_pipe( fpu_reg_mem ); 9827 %} 9828 9829 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ 9830 predicate(UseSSE<=1); 9831 match(Set dst (AddD dst con)); 9832 ins_cost(125); 9833 format %{ "FLD1\n\t" 9834 "DADDp $dst,ST" %} 9835 ins_encode %{ 9836 __ fld1(); 9837 __ faddp($dst$$reg); 9838 %} 9839 ins_pipe(fpu_reg); 9840 %} 9841 9842 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ 9843 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9844 match(Set dst (AddD dst con)); 9845 ins_cost(200); 9846 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9847 "DADDp $dst,ST" %} 9848 ins_encode %{ 9849 __ fld_d($constantaddress($con)); 9850 __ faddp($dst$$reg); 9851 %} 9852 ins_pipe(fpu_reg_mem); 9853 %} 9854 9855 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ 9856 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); 9857 match(Set dst (RoundDouble (AddD src con))); 9858 ins_cost(200); 9859 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9860 "DADD ST,$src\n\t" 9861 "FSTP_D $dst\t# D-round" %} 9862 ins_encode %{ 9863 __ fld_d($constantaddress($con)); 9864 __ fadd($src$$reg); 9865 __ fstp_d(Address(rsp, $dst$$disp)); 9866 %} 9867 ins_pipe(fpu_mem_reg_con); 9868 %} 9869 9870 instruct mulDPR_reg(regDPR dst, regDPR src) %{ 9871 predicate(UseSSE<=1); 9872 match(Set dst (MulD dst src)); 9873 format %{ "FLD $src\n\t" 9874 "DMULp $dst,ST" %} 9875 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9876 ins_cost(150); 9877 ins_encode( Push_Reg_DPR(src), 9878 OpcP, RegOpc(dst) ); 9879 ins_pipe( fpu_reg_reg ); 9880 %} 9881 9882 // Strict FP instruction biases argument before multiply then 9883 // biases result to avoid double rounding of subnormals. 9884 // 9885 // scale arg1 by multiplying arg1 by 2^(-15360) 9886 // load arg2 9887 // multiply scaled arg1 by arg2 9888 // rescale product by 2^(15360) 9889 // 9890 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ 9891 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9892 match(Set dst (MulD dst src)); 9893 ins_cost(1); // Select this instruction for all strict FP double multiplies 9894 9895 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9896 "DMULp $dst,ST\n\t" 9897 "FLD $src\n\t" 9898 "DMULp $dst,ST\n\t" 9899 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9900 "DMULp $dst,ST\n\t" %} 9901 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9902 ins_encode( strictfp_bias1(dst), 9903 Push_Reg_DPR(src), 9904 OpcP, RegOpc(dst), 9905 strictfp_bias2(dst) ); 9906 ins_pipe( fpu_reg_reg ); 9907 %} 9908 9909 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ 9910 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9911 match(Set dst (MulD dst con)); 9912 ins_cost(200); 9913 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9914 "DMULp $dst,ST" %} 9915 ins_encode %{ 9916 __ fld_d($constantaddress($con)); 9917 __ fmulp($dst$$reg); 9918 %} 9919 ins_pipe(fpu_reg_mem); 9920 %} 9921 9922 9923 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ 9924 predicate( UseSSE<=1 ); 9925 match(Set dst (MulD dst (LoadD src))); 9926 ins_cost(200); 9927 format %{ "FLD_D $src\n\t" 9928 "DMULp $dst,ST" %} 9929 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ 9930 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9931 OpcP, RegOpc(dst) ); 9932 ins_pipe( fpu_reg_mem ); 9933 %} 9934 9935 // 9936 // Cisc-alternate to reg-reg multiply 9937 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ 9938 predicate( UseSSE<=1 ); 9939 match(Set dst (MulD src (LoadD mem))); 9940 ins_cost(250); 9941 format %{ "FLD_D $mem\n\t" 9942 "DMUL ST,$src\n\t" 9943 "FSTP_D $dst" %} 9944 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ 9945 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), 9946 OpcReg_FPR(src), 9947 Pop_Reg_DPR(dst) ); 9948 ins_pipe( fpu_reg_reg_mem ); 9949 %} 9950 9951 9952 // MACRO3 -- addDPR a mulDPR 9953 // This instruction is a '2-address' instruction in that the result goes 9954 // back to src2. This eliminates a move from the macro; possibly the 9955 // register allocator will have to add it back (and maybe not). 9956 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ 9957 predicate( UseSSE<=1 ); 9958 match(Set src2 (AddD (MulD src0 src1) src2)); 9959 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9960 "DMUL ST,$src1\n\t" 9961 "DADDp $src2,ST" %} 9962 ins_cost(250); 9963 opcode(0xDD); /* LoadD DD /0 */ 9964 ins_encode( Push_Reg_FPR(src0), 9965 FMul_ST_reg(src1), 9966 FAddP_reg_ST(src2) ); 9967 ins_pipe( fpu_reg_reg_reg ); 9968 %} 9969 9970 9971 // MACRO3 -- subDPR a mulDPR 9972 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ 9973 predicate( UseSSE<=1 ); 9974 match(Set src2 (SubD (MulD src0 src1) src2)); 9975 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9976 "DMUL ST,$src1\n\t" 9977 "DSUBRp $src2,ST" %} 9978 ins_cost(250); 9979 ins_encode( Push_Reg_FPR(src0), 9980 FMul_ST_reg(src1), 9981 Opcode(0xDE), Opc_plus(0xE0,src2)); 9982 ins_pipe( fpu_reg_reg_reg ); 9983 %} 9984 9985 9986 instruct divDPR_reg(regDPR dst, regDPR src) %{ 9987 predicate( UseSSE<=1 ); 9988 match(Set dst (DivD dst src)); 9989 9990 format %{ "FLD $src\n\t" 9991 "FDIVp $dst,ST" %} 9992 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9993 ins_cost(150); 9994 ins_encode( Push_Reg_DPR(src), 9995 OpcP, RegOpc(dst) ); 9996 ins_pipe( fpu_reg_reg ); 9997 %} 9998 9999 // Strict FP instruction biases argument before division then 10000 // biases result, to avoid double rounding of subnormals. 10001 // 10002 // scale dividend by multiplying dividend by 2^(-15360) 10003 // load divisor 10004 // divide scaled dividend by divisor 10005 // rescale quotient by 2^(15360) 10006 // 10007 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ 10008 predicate (UseSSE<=1); 10009 match(Set dst (DivD dst src)); 10010 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 10011 ins_cost(01); 10012 10013 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 10014 "DMULp $dst,ST\n\t" 10015 "FLD $src\n\t" 10016 "FDIVp $dst,ST\n\t" 10017 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 10018 "DMULp $dst,ST\n\t" %} 10019 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10020 ins_encode( strictfp_bias1(dst), 10021 Push_Reg_DPR(src), 10022 OpcP, RegOpc(dst), 10023 strictfp_bias2(dst) ); 10024 ins_pipe( fpu_reg_reg ); 10025 %} 10026 10027 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 10028 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); 10029 match(Set dst (RoundDouble (DivD src1 src2))); 10030 10031 format %{ "FLD $src1\n\t" 10032 "FDIV ST,$src2\n\t" 10033 "FSTP_D $dst\t# D-round" %} 10034 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ 10035 ins_encode( Push_Reg_DPR(src1), 10036 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); 10037 ins_pipe( fpu_mem_reg_reg ); 10038 %} 10039 10040 10041 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ 10042 predicate(UseSSE<=1); 10043 match(Set dst (ModD dst src)); 10044 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 10045 10046 format %{ "DMOD $dst,$src" %} 10047 ins_cost(250); 10048 ins_encode(Push_Reg_Mod_DPR(dst, src), 10049 emitModDPR(), 10050 Push_Result_Mod_DPR(src), 10051 Pop_Reg_DPR(dst)); 10052 ins_pipe( pipe_slow ); 10053 %} 10054 10055 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ 10056 predicate(UseSSE>=2); 10057 match(Set dst (ModD src0 src1)); 10058 effect(KILL rax, KILL cr); 10059 10060 format %{ "SUB ESP,8\t # DMOD\n" 10061 "\tMOVSD [ESP+0],$src1\n" 10062 "\tFLD_D [ESP+0]\n" 10063 "\tMOVSD [ESP+0],$src0\n" 10064 "\tFLD_D [ESP+0]\n" 10065 "loop:\tFPREM\n" 10066 "\tFWAIT\n" 10067 "\tFNSTSW AX\n" 10068 "\tSAHF\n" 10069 "\tJP loop\n" 10070 "\tFSTP_D [ESP+0]\n" 10071 "\tMOVSD $dst,[ESP+0]\n" 10072 "\tADD ESP,8\n" 10073 "\tFSTP ST0\t # Restore FPU Stack" 10074 %} 10075 ins_cost(250); 10076 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); 10077 ins_pipe( pipe_slow ); 10078 %} 10079 10080 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ 10081 predicate (UseSSE<=1); 10082 match(Set dst (SinD src)); 10083 ins_cost(1800); 10084 format %{ "DSIN $dst" %} 10085 opcode(0xD9, 0xFE); 10086 ins_encode( OpcP, OpcS ); 10087 ins_pipe( pipe_slow ); 10088 %} 10089 10090 instruct sinD_reg(regD dst, eFlagsReg cr) %{ 10091 predicate (UseSSE>=2); 10092 match(Set dst (SinD dst)); 10093 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10094 ins_cost(1800); 10095 format %{ "DSIN $dst" %} 10096 opcode(0xD9, 0xFE); 10097 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); 10098 ins_pipe( pipe_slow ); 10099 %} 10100 10101 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ 10102 predicate (UseSSE<=1); 10103 match(Set dst (CosD src)); 10104 ins_cost(1800); 10105 format %{ "DCOS $dst" %} 10106 opcode(0xD9, 0xFF); 10107 ins_encode( OpcP, OpcS ); 10108 ins_pipe( pipe_slow ); 10109 %} 10110 10111 instruct cosD_reg(regD dst, eFlagsReg cr) %{ 10112 predicate (UseSSE>=2); 10113 match(Set dst (CosD dst)); 10114 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10115 ins_cost(1800); 10116 format %{ "DCOS $dst" %} 10117 opcode(0xD9, 0xFF); 10118 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); 10119 ins_pipe( pipe_slow ); 10120 %} 10121 10122 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ 10123 predicate (UseSSE<=1); 10124 match(Set dst(TanD src)); 10125 format %{ "DTAN $dst" %} 10126 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan 10127 Opcode(0xDD), Opcode(0xD8)); // fstp st 10128 ins_pipe( pipe_slow ); 10129 %} 10130 10131 instruct tanD_reg(regD dst, eFlagsReg cr) %{ 10132 predicate (UseSSE>=2); 10133 match(Set dst(TanD dst)); 10134 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10135 format %{ "DTAN $dst" %} 10136 ins_encode( Push_SrcD(dst), 10137 Opcode(0xD9), Opcode(0xF2), // fptan 10138 Opcode(0xDD), Opcode(0xD8), // fstp st 10139 Push_ResultD(dst) ); 10140 ins_pipe( pipe_slow ); 10141 %} 10142 10143 instruct atanDPR_reg(regDPR dst, regDPR src) %{ 10144 predicate (UseSSE<=1); 10145 match(Set dst(AtanD dst src)); 10146 format %{ "DATA $dst,$src" %} 10147 opcode(0xD9, 0xF3); 10148 ins_encode( Push_Reg_DPR(src), 10149 OpcP, OpcS, RegOpc(dst) ); 10150 ins_pipe( pipe_slow ); 10151 %} 10152 10153 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ 10154 predicate (UseSSE>=2); 10155 match(Set dst(AtanD dst src)); 10156 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10157 format %{ "DATA $dst,$src" %} 10158 opcode(0xD9, 0xF3); 10159 ins_encode( Push_SrcD(src), 10160 OpcP, OpcS, Push_ResultD(dst) ); 10161 ins_pipe( pipe_slow ); 10162 %} 10163 10164 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ 10165 predicate (UseSSE<=1); 10166 match(Set dst (SqrtD src)); 10167 format %{ "DSQRT $dst,$src" %} 10168 opcode(0xFA, 0xD9); 10169 ins_encode( Push_Reg_DPR(src), 10170 OpcS, OpcP, Pop_Reg_DPR(dst) ); 10171 ins_pipe( pipe_slow ); 10172 %} 10173 10174 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10175 predicate (UseSSE<=1); 10176 match(Set Y (PowD X Y)); // Raise X to the Yth power 10177 effect(KILL rax, KILL rbx, KILL rcx); 10178 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 10179 "FLD_D $X\n\t" 10180 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 10181 10182 "FDUP \t\t\t# Q Q\n\t" 10183 "FRNDINT\t\t\t# int(Q) Q\n\t" 10184 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10185 "FISTP dword [ESP]\n\t" 10186 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10187 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10188 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10189 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10190 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10191 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10192 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10193 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10194 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10195 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10196 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10197 "MOV [ESP+0],0\n\t" 10198 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10199 10200 "ADD ESP,8" 10201 %} 10202 ins_encode( push_stack_temp_qword, 10203 Push_Reg_DPR(X), 10204 Opcode(0xD9), Opcode(0xF1), // fyl2x 10205 pow_exp_core_encoding, 10206 pop_stack_temp_qword); 10207 ins_pipe( pipe_slow ); 10208 %} 10209 10210 instruct powD_reg(regD dst, regD src0, regD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ 10211 predicate (UseSSE>=2); 10212 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power 10213 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); 10214 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 10215 "MOVSD [ESP],$src1\n\t" 10216 "FLD FPR1,$src1\n\t" 10217 "MOVSD [ESP],$src0\n\t" 10218 "FLD FPR1,$src0\n\t" 10219 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 10220 10221 "FDUP \t\t\t# Q Q\n\t" 10222 "FRNDINT\t\t\t# int(Q) Q\n\t" 10223 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10224 "FISTP dword [ESP]\n\t" 10225 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10226 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10227 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10228 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10229 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10230 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10231 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10232 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10233 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10234 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10235 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10236 "MOV [ESP+0],0\n\t" 10237 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10238 10239 "FST_D [ESP]\n\t" 10240 "MOVSD $dst,[ESP]\n\t" 10241 "ADD ESP,8" 10242 %} 10243 ins_encode( push_stack_temp_qword, 10244 push_xmm_to_fpr1(src1), 10245 push_xmm_to_fpr1(src0), 10246 Opcode(0xD9), Opcode(0xF1), // fyl2x 10247 pow_exp_core_encoding, 10248 Push_ResultD(dst) ); 10249 ins_pipe( pipe_slow ); 10250 %} 10251 10252 10253 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10254 predicate (UseSSE<=1); 10255 match(Set dpr1 (ExpD dpr1)); 10256 effect(KILL rax, KILL rbx, KILL rcx); 10257 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" 10258 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 10259 "FMULP \t\t\t# Q=X*log2(e)\n\t" 10260 10261 "FDUP \t\t\t# Q Q\n\t" 10262 "FRNDINT\t\t\t# int(Q) Q\n\t" 10263 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10264 "FISTP dword [ESP]\n\t" 10265 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10266 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10267 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10268 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10269 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10270 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10271 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10272 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10273 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10274 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10275 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10276 "MOV [ESP+0],0\n\t" 10277 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10278 10279 "ADD ESP,8" 10280 %} 10281 ins_encode( push_stack_temp_qword, 10282 Opcode(0xD9), Opcode(0xEA), // fldl2e 10283 Opcode(0xDE), Opcode(0xC9), // fmulp 10284 pow_exp_core_encoding, 10285 pop_stack_temp_qword); 10286 ins_pipe( pipe_slow ); 10287 %} 10288 10289 instruct expD_reg(regD dst, regD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10290 predicate (UseSSE>=2); 10291 match(Set dst (ExpD src)); 10292 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); 10293 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" 10294 "MOVSD [ESP],$src\n\t" 10295 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 10296 "FMULP \t\t\t# Q=X*log2(e) X\n\t" 10297 10298 "FDUP \t\t\t# Q Q\n\t" 10299 "FRNDINT\t\t\t# int(Q) Q\n\t" 10300 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10301 "FISTP dword [ESP]\n\t" 10302 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10303 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10304 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10305 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10306 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10307 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10308 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10309 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10310 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10311 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10312 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10313 "MOV [ESP+0],0\n\t" 10314 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10315 10316 "FST_D [ESP]\n\t" 10317 "MOVSD $dst,[ESP]\n\t" 10318 "ADD ESP,8" 10319 %} 10320 ins_encode( Push_SrcD(src), 10321 Opcode(0xD9), Opcode(0xEA), // fldl2e 10322 Opcode(0xDE), Opcode(0xC9), // fmulp 10323 pow_exp_core_encoding, 10324 Push_ResultD(dst) ); 10325 ins_pipe( pipe_slow ); 10326 %} 10327 10328 10329 10330 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ 10331 predicate (UseSSE<=1); 10332 // The source Double operand on FPU stack 10333 match(Set dst (Log10D src)); 10334 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10335 // fxch ; swap ST(0) with ST(1) 10336 // fyl2x ; compute log_10(2) * log_2(x) 10337 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10338 "FXCH \n\t" 10339 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10340 %} 10341 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10342 Opcode(0xD9), Opcode(0xC9), // fxch 10343 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10344 10345 ins_pipe( pipe_slow ); 10346 %} 10347 10348 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ 10349 predicate (UseSSE>=2); 10350 effect(KILL cr); 10351 match(Set dst (Log10D src)); 10352 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10353 // fyl2x ; compute log_10(2) * log_2(x) 10354 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10355 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10356 %} 10357 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10358 Push_SrcD(src), 10359 Opcode(0xD9), Opcode(0xF1), // fyl2x 10360 Push_ResultD(dst)); 10361 10362 ins_pipe( pipe_slow ); 10363 %} 10364 10365 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ 10366 predicate (UseSSE<=1); 10367 // The source Double operand on FPU stack 10368 match(Set dst (LogD src)); 10369 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10370 // fxch ; swap ST(0) with ST(1) 10371 // fyl2x ; compute log_e(2) * log_2(x) 10372 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10373 "FXCH \n\t" 10374 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10375 %} 10376 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10377 Opcode(0xD9), Opcode(0xC9), // fxch 10378 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10379 10380 ins_pipe( pipe_slow ); 10381 %} 10382 10383 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ 10384 predicate (UseSSE>=2); 10385 effect(KILL cr); 10386 // The source and result Double operands in XMM registers 10387 match(Set dst (LogD src)); 10388 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10389 // fyl2x ; compute log_e(2) * log_2(x) 10390 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10391 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10392 %} 10393 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10394 Push_SrcD(src), 10395 Opcode(0xD9), Opcode(0xF1), // fyl2x 10396 Push_ResultD(dst)); 10397 ins_pipe( pipe_slow ); 10398 %} 10399 10400 //-------------Float Instructions------------------------------- 10401 // Float Math 10402 10403 // Code for float compare: 10404 // fcompp(); 10405 // fwait(); fnstsw_ax(); 10406 // sahf(); 10407 // movl(dst, unordered_result); 10408 // jcc(Assembler::parity, exit); 10409 // movl(dst, less_result); 10410 // jcc(Assembler::below, exit); 10411 // movl(dst, equal_result); 10412 // jcc(Assembler::equal, exit); 10413 // movl(dst, greater_result); 10414 // exit: 10415 10416 // P6 version of float compare, sets condition codes in EFLAGS 10417 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ 10418 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10419 match(Set cr (CmpF src1 src2)); 10420 effect(KILL rax); 10421 ins_cost(150); 10422 format %{ "FLD $src1\n\t" 10423 "FUCOMIP ST,$src2 // P6 instruction\n\t" 10424 "JNP exit\n\t" 10425 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" 10426 "SAHF\n" 10427 "exit:\tNOP // avoid branch to branch" %} 10428 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10429 ins_encode( Push_Reg_DPR(src1), 10430 OpcP, RegOpc(src2), 10431 cmpF_P6_fixup ); 10432 ins_pipe( pipe_slow ); 10433 %} 10434 10435 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ 10436 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10437 match(Set cr (CmpF src1 src2)); 10438 ins_cost(100); 10439 format %{ "FLD $src1\n\t" 10440 "FUCOMIP ST,$src2 // P6 instruction" %} 10441 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10442 ins_encode( Push_Reg_DPR(src1), 10443 OpcP, RegOpc(src2)); 10444 ins_pipe( pipe_slow ); 10445 %} 10446 10447 10448 // Compare & branch 10449 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ 10450 predicate(UseSSE == 0); 10451 match(Set cr (CmpF src1 src2)); 10452 effect(KILL rax); 10453 ins_cost(200); 10454 format %{ "FLD $src1\n\t" 10455 "FCOMp $src2\n\t" 10456 "FNSTSW AX\n\t" 10457 "TEST AX,0x400\n\t" 10458 "JZ,s flags\n\t" 10459 "MOV AH,1\t# unordered treat as LT\n" 10460 "flags:\tSAHF" %} 10461 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10462 ins_encode( Push_Reg_DPR(src1), 10463 OpcP, RegOpc(src2), 10464 fpu_flags); 10465 ins_pipe( pipe_slow ); 10466 %} 10467 10468 // Compare vs zero into -1,0,1 10469 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 10470 predicate(UseSSE == 0); 10471 match(Set dst (CmpF3 src1 zero)); 10472 effect(KILL cr, KILL rax); 10473 ins_cost(280); 10474 format %{ "FTSTF $dst,$src1" %} 10475 opcode(0xE4, 0xD9); 10476 ins_encode( Push_Reg_DPR(src1), 10477 OpcS, OpcP, PopFPU, 10478 CmpF_Result(dst)); 10479 ins_pipe( pipe_slow ); 10480 %} 10481 10482 // Compare into -1,0,1 10483 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ 10484 predicate(UseSSE == 0); 10485 match(Set dst (CmpF3 src1 src2)); 10486 effect(KILL cr, KILL rax); 10487 ins_cost(300); 10488 format %{ "FCMPF $dst,$src1,$src2" %} 10489 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10490 ins_encode( Push_Reg_DPR(src1), 10491 OpcP, RegOpc(src2), 10492 CmpF_Result(dst)); 10493 ins_pipe( pipe_slow ); 10494 %} 10495 10496 // float compare and set condition codes in EFLAGS by XMM regs 10497 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ 10498 predicate(UseSSE>=1); 10499 match(Set cr (CmpF src1 src2)); 10500 ins_cost(145); 10501 format %{ "UCOMISS $src1,$src2\n\t" 10502 "JNP,s exit\n\t" 10503 "PUSHF\t# saw NaN, set CF\n\t" 10504 "AND [rsp], #0xffffff2b\n\t" 10505 "POPF\n" 10506 "exit:" %} 10507 ins_encode %{ 10508 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10509 emit_cmpfp_fixup(_masm); 10510 %} 10511 ins_pipe( pipe_slow ); 10512 %} 10513 10514 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ 10515 predicate(UseSSE>=1); 10516 match(Set cr (CmpF src1 src2)); 10517 ins_cost(100); 10518 format %{ "UCOMISS $src1,$src2" %} 10519 ins_encode %{ 10520 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10521 %} 10522 ins_pipe( pipe_slow ); 10523 %} 10524 10525 // float compare and set condition codes in EFLAGS by XMM regs 10526 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ 10527 predicate(UseSSE>=1); 10528 match(Set cr (CmpF src1 (LoadF src2))); 10529 ins_cost(165); 10530 format %{ "UCOMISS $src1,$src2\n\t" 10531 "JNP,s exit\n\t" 10532 "PUSHF\t# saw NaN, set CF\n\t" 10533 "AND [rsp], #0xffffff2b\n\t" 10534 "POPF\n" 10535 "exit:" %} 10536 ins_encode %{ 10537 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10538 emit_cmpfp_fixup(_masm); 10539 %} 10540 ins_pipe( pipe_slow ); 10541 %} 10542 10543 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ 10544 predicate(UseSSE>=1); 10545 match(Set cr (CmpF src1 (LoadF src2))); 10546 ins_cost(100); 10547 format %{ "UCOMISS $src1,$src2" %} 10548 ins_encode %{ 10549 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10550 %} 10551 ins_pipe( pipe_slow ); 10552 %} 10553 10554 // Compare into -1,0,1 in XMM 10555 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ 10556 predicate(UseSSE>=1); 10557 match(Set dst (CmpF3 src1 src2)); 10558 effect(KILL cr); 10559 ins_cost(255); 10560 format %{ "UCOMISS $src1, $src2\n\t" 10561 "MOV $dst, #-1\n\t" 10562 "JP,s done\n\t" 10563 "JB,s done\n\t" 10564 "SETNE $dst\n\t" 10565 "MOVZB $dst, $dst\n" 10566 "done:" %} 10567 ins_encode %{ 10568 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10569 emit_cmpfp3(_masm, $dst$$Register); 10570 %} 10571 ins_pipe( pipe_slow ); 10572 %} 10573 10574 // Compare into -1,0,1 in XMM and memory 10575 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ 10576 predicate(UseSSE>=1); 10577 match(Set dst (CmpF3 src1 (LoadF src2))); 10578 effect(KILL cr); 10579 ins_cost(275); 10580 format %{ "UCOMISS $src1, $src2\n\t" 10581 "MOV $dst, #-1\n\t" 10582 "JP,s done\n\t" 10583 "JB,s done\n\t" 10584 "SETNE $dst\n\t" 10585 "MOVZB $dst, $dst\n" 10586 "done:" %} 10587 ins_encode %{ 10588 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10589 emit_cmpfp3(_masm, $dst$$Register); 10590 %} 10591 ins_pipe( pipe_slow ); 10592 %} 10593 10594 // Spill to obtain 24-bit precision 10595 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10596 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10597 match(Set dst (SubF src1 src2)); 10598 10599 format %{ "FSUB $dst,$src1 - $src2" %} 10600 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ 10601 ins_encode( Push_Reg_FPR(src1), 10602 OpcReg_FPR(src2), 10603 Pop_Mem_FPR(dst) ); 10604 ins_pipe( fpu_mem_reg_reg ); 10605 %} 10606 // 10607 // This instruction does not round to 24-bits 10608 instruct subFPR_reg(regFPR dst, regFPR src) %{ 10609 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10610 match(Set dst (SubF dst src)); 10611 10612 format %{ "FSUB $dst,$src" %} 10613 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 10614 ins_encode( Push_Reg_FPR(src), 10615 OpcP, RegOpc(dst) ); 10616 ins_pipe( fpu_reg_reg ); 10617 %} 10618 10619 // Spill to obtain 24-bit precision 10620 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10621 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10622 match(Set dst (AddF src1 src2)); 10623 10624 format %{ "FADD $dst,$src1,$src2" %} 10625 opcode(0xD8, 0x0); /* D8 C0+i */ 10626 ins_encode( Push_Reg_FPR(src2), 10627 OpcReg_FPR(src1), 10628 Pop_Mem_FPR(dst) ); 10629 ins_pipe( fpu_mem_reg_reg ); 10630 %} 10631 // 10632 // This instruction does not round to 24-bits 10633 instruct addFPR_reg(regFPR dst, regFPR src) %{ 10634 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10635 match(Set dst (AddF dst src)); 10636 10637 format %{ "FLD $src\n\t" 10638 "FADDp $dst,ST" %} 10639 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 10640 ins_encode( Push_Reg_FPR(src), 10641 OpcP, RegOpc(dst) ); 10642 ins_pipe( fpu_reg_reg ); 10643 %} 10644 10645 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ 10646 predicate(UseSSE==0); 10647 match(Set dst (AbsF src)); 10648 ins_cost(100); 10649 format %{ "FABS" %} 10650 opcode(0xE1, 0xD9); 10651 ins_encode( OpcS, OpcP ); 10652 ins_pipe( fpu_reg_reg ); 10653 %} 10654 10655 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ 10656 predicate(UseSSE==0); 10657 match(Set dst (NegF src)); 10658 ins_cost(100); 10659 format %{ "FCHS" %} 10660 opcode(0xE0, 0xD9); 10661 ins_encode( OpcS, OpcP ); 10662 ins_pipe( fpu_reg_reg ); 10663 %} 10664 10665 // Cisc-alternate to addFPR_reg 10666 // Spill to obtain 24-bit precision 10667 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ 10668 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10669 match(Set dst (AddF src1 (LoadF src2))); 10670 10671 format %{ "FLD $src2\n\t" 10672 "FADD ST,$src1\n\t" 10673 "FSTP_S $dst" %} 10674 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10675 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10676 OpcReg_FPR(src1), 10677 Pop_Mem_FPR(dst) ); 10678 ins_pipe( fpu_mem_reg_mem ); 10679 %} 10680 // 10681 // Cisc-alternate to addFPR_reg 10682 // This instruction does not round to 24-bits 10683 instruct addFPR_reg_mem(regFPR dst, memory src) %{ 10684 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10685 match(Set dst (AddF dst (LoadF src))); 10686 10687 format %{ "FADD $dst,$src" %} 10688 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ 10689 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10690 OpcP, RegOpc(dst) ); 10691 ins_pipe( fpu_reg_mem ); 10692 %} 10693 10694 // // Following two instructions for _222_mpegaudio 10695 // Spill to obtain 24-bit precision 10696 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ 10697 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10698 match(Set dst (AddF src1 src2)); 10699 10700 format %{ "FADD $dst,$src1,$src2" %} 10701 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10702 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), 10703 OpcReg_FPR(src2), 10704 Pop_Mem_FPR(dst) ); 10705 ins_pipe( fpu_mem_reg_mem ); 10706 %} 10707 10708 // Cisc-spill variant 10709 // Spill to obtain 24-bit precision 10710 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ 10711 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10712 match(Set dst (AddF src1 (LoadF src2))); 10713 10714 format %{ "FADD $dst,$src1,$src2 cisc" %} 10715 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10716 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10717 set_instruction_start, 10718 OpcP, RMopc_Mem(secondary,src1), 10719 Pop_Mem_FPR(dst) ); 10720 ins_pipe( fpu_mem_mem_mem ); 10721 %} 10722 10723 // Spill to obtain 24-bit precision 10724 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10725 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10726 match(Set dst (AddF src1 src2)); 10727 10728 format %{ "FADD $dst,$src1,$src2" %} 10729 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ 10730 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10731 set_instruction_start, 10732 OpcP, RMopc_Mem(secondary,src1), 10733 Pop_Mem_FPR(dst) ); 10734 ins_pipe( fpu_mem_mem_mem ); 10735 %} 10736 10737 10738 // Spill to obtain 24-bit precision 10739 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ 10740 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10741 match(Set dst (AddF src con)); 10742 format %{ "FLD $src\n\t" 10743 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10744 "FSTP_S $dst" %} 10745 ins_encode %{ 10746 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10747 __ fadd_s($constantaddress($con)); 10748 __ fstp_s(Address(rsp, $dst$$disp)); 10749 %} 10750 ins_pipe(fpu_mem_reg_con); 10751 %} 10752 // 10753 // This instruction does not round to 24-bits 10754 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ 10755 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10756 match(Set dst (AddF src con)); 10757 format %{ "FLD $src\n\t" 10758 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10759 "FSTP $dst" %} 10760 ins_encode %{ 10761 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10762 __ fadd_s($constantaddress($con)); 10763 __ fstp_d($dst$$reg); 10764 %} 10765 ins_pipe(fpu_reg_reg_con); 10766 %} 10767 10768 // Spill to obtain 24-bit precision 10769 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10770 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10771 match(Set dst (MulF src1 src2)); 10772 10773 format %{ "FLD $src1\n\t" 10774 "FMUL $src2\n\t" 10775 "FSTP_S $dst" %} 10776 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ 10777 ins_encode( Push_Reg_FPR(src1), 10778 OpcReg_FPR(src2), 10779 Pop_Mem_FPR(dst) ); 10780 ins_pipe( fpu_mem_reg_reg ); 10781 %} 10782 // 10783 // This instruction does not round to 24-bits 10784 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ 10785 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10786 match(Set dst (MulF src1 src2)); 10787 10788 format %{ "FLD $src1\n\t" 10789 "FMUL $src2\n\t" 10790 "FSTP_S $dst" %} 10791 opcode(0xD8, 0x1); /* D8 C8+i */ 10792 ins_encode( Push_Reg_FPR(src2), 10793 OpcReg_FPR(src1), 10794 Pop_Reg_FPR(dst) ); 10795 ins_pipe( fpu_reg_reg_reg ); 10796 %} 10797 10798 10799 // Spill to obtain 24-bit precision 10800 // Cisc-alternate to reg-reg multiply 10801 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ 10802 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10803 match(Set dst (MulF src1 (LoadF src2))); 10804 10805 format %{ "FLD_S $src2\n\t" 10806 "FMUL $src1\n\t" 10807 "FSTP_S $dst" %} 10808 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ 10809 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10810 OpcReg_FPR(src1), 10811 Pop_Mem_FPR(dst) ); 10812 ins_pipe( fpu_mem_reg_mem ); 10813 %} 10814 // 10815 // This instruction does not round to 24-bits 10816 // Cisc-alternate to reg-reg multiply 10817 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ 10818 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10819 match(Set dst (MulF src1 (LoadF src2))); 10820 10821 format %{ "FMUL $dst,$src1,$src2" %} 10822 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ 10823 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10824 OpcReg_FPR(src1), 10825 Pop_Reg_FPR(dst) ); 10826 ins_pipe( fpu_reg_reg_mem ); 10827 %} 10828 10829 // Spill to obtain 24-bit precision 10830 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10831 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10832 match(Set dst (MulF src1 src2)); 10833 10834 format %{ "FMUL $dst,$src1,$src2" %} 10835 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ 10836 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10837 set_instruction_start, 10838 OpcP, RMopc_Mem(secondary,src1), 10839 Pop_Mem_FPR(dst) ); 10840 ins_pipe( fpu_mem_mem_mem ); 10841 %} 10842 10843 // Spill to obtain 24-bit precision 10844 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ 10845 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10846 match(Set dst (MulF src con)); 10847 10848 format %{ "FLD $src\n\t" 10849 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10850 "FSTP_S $dst" %} 10851 ins_encode %{ 10852 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10853 __ fmul_s($constantaddress($con)); 10854 __ fstp_s(Address(rsp, $dst$$disp)); 10855 %} 10856 ins_pipe(fpu_mem_reg_con); 10857 %} 10858 // 10859 // This instruction does not round to 24-bits 10860 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ 10861 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10862 match(Set dst (MulF src con)); 10863 10864 format %{ "FLD $src\n\t" 10865 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10866 "FSTP $dst" %} 10867 ins_encode %{ 10868 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10869 __ fmul_s($constantaddress($con)); 10870 __ fstp_d($dst$$reg); 10871 %} 10872 ins_pipe(fpu_reg_reg_con); 10873 %} 10874 10875 10876 // 10877 // MACRO1 -- subsume unshared load into mulFPR 10878 // This instruction does not round to 24-bits 10879 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ 10880 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10881 match(Set dst (MulF (LoadF mem1) src)); 10882 10883 format %{ "FLD $mem1 ===MACRO1===\n\t" 10884 "FMUL ST,$src\n\t" 10885 "FSTP $dst" %} 10886 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ 10887 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), 10888 OpcReg_FPR(src), 10889 Pop_Reg_FPR(dst) ); 10890 ins_pipe( fpu_reg_reg_mem ); 10891 %} 10892 // 10893 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load 10894 // This instruction does not round to 24-bits 10895 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ 10896 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10897 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); 10898 ins_cost(95); 10899 10900 format %{ "FLD $mem1 ===MACRO2===\n\t" 10901 "FMUL ST,$src1 subsume mulFPR left load\n\t" 10902 "FADD ST,$src2\n\t" 10903 "FSTP $dst" %} 10904 opcode(0xD9); /* LoadF D9 /0 */ 10905 ins_encode( OpcP, RMopc_Mem(0x00,mem1), 10906 FMul_ST_reg(src1), 10907 FAdd_ST_reg(src2), 10908 Pop_Reg_FPR(dst) ); 10909 ins_pipe( fpu_reg_mem_reg_reg ); 10910 %} 10911 10912 // MACRO3 -- addFPR a mulFPR 10913 // This instruction does not round to 24-bits. It is a '2-address' 10914 // instruction in that the result goes back to src2. This eliminates 10915 // a move from the macro; possibly the register allocator will have 10916 // to add it back (and maybe not). 10917 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ 10918 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10919 match(Set src2 (AddF (MulF src0 src1) src2)); 10920 10921 format %{ "FLD $src0 ===MACRO3===\n\t" 10922 "FMUL ST,$src1\n\t" 10923 "FADDP $src2,ST" %} 10924 opcode(0xD9); /* LoadF D9 /0 */ 10925 ins_encode( Push_Reg_FPR(src0), 10926 FMul_ST_reg(src1), 10927 FAddP_reg_ST(src2) ); 10928 ins_pipe( fpu_reg_reg_reg ); 10929 %} 10930 10931 // MACRO4 -- divFPR subFPR 10932 // This instruction does not round to 24-bits 10933 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ 10934 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10935 match(Set dst (DivF (SubF src2 src1) src3)); 10936 10937 format %{ "FLD $src2 ===MACRO4===\n\t" 10938 "FSUB ST,$src1\n\t" 10939 "FDIV ST,$src3\n\t" 10940 "FSTP $dst" %} 10941 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10942 ins_encode( Push_Reg_FPR(src2), 10943 subFPR_divFPR_encode(src1,src3), 10944 Pop_Reg_FPR(dst) ); 10945 ins_pipe( fpu_reg_reg_reg_reg ); 10946 %} 10947 10948 // Spill to obtain 24-bit precision 10949 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10950 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10951 match(Set dst (DivF src1 src2)); 10952 10953 format %{ "FDIV $dst,$src1,$src2" %} 10954 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ 10955 ins_encode( Push_Reg_FPR(src1), 10956 OpcReg_FPR(src2), 10957 Pop_Mem_FPR(dst) ); 10958 ins_pipe( fpu_mem_reg_reg ); 10959 %} 10960 // 10961 // This instruction does not round to 24-bits 10962 instruct divFPR_reg(regFPR dst, regFPR src) %{ 10963 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10964 match(Set dst (DivF dst src)); 10965 10966 format %{ "FDIV $dst,$src" %} 10967 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10968 ins_encode( Push_Reg_FPR(src), 10969 OpcP, RegOpc(dst) ); 10970 ins_pipe( fpu_reg_reg ); 10971 %} 10972 10973 10974 // Spill to obtain 24-bit precision 10975 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ 10976 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 10977 match(Set dst (ModF src1 src2)); 10978 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 10979 10980 format %{ "FMOD $dst,$src1,$src2" %} 10981 ins_encode( Push_Reg_Mod_DPR(src1, src2), 10982 emitModDPR(), 10983 Push_Result_Mod_DPR(src2), 10984 Pop_Mem_FPR(dst)); 10985 ins_pipe( pipe_slow ); 10986 %} 10987 // 10988 // This instruction does not round to 24-bits 10989 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ 10990 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10991 match(Set dst (ModF dst src)); 10992 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 10993 10994 format %{ "FMOD $dst,$src" %} 10995 ins_encode(Push_Reg_Mod_DPR(dst, src), 10996 emitModDPR(), 10997 Push_Result_Mod_DPR(src), 10998 Pop_Reg_FPR(dst)); 10999 ins_pipe( pipe_slow ); 11000 %} 11001 11002 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ 11003 predicate(UseSSE>=1); 11004 match(Set dst (ModF src0 src1)); 11005 effect(KILL rax, KILL cr); 11006 format %{ "SUB ESP,4\t # FMOD\n" 11007 "\tMOVSS [ESP+0],$src1\n" 11008 "\tFLD_S [ESP+0]\n" 11009 "\tMOVSS [ESP+0],$src0\n" 11010 "\tFLD_S [ESP+0]\n" 11011 "loop:\tFPREM\n" 11012 "\tFWAIT\n" 11013 "\tFNSTSW AX\n" 11014 "\tSAHF\n" 11015 "\tJP loop\n" 11016 "\tFSTP_S [ESP+0]\n" 11017 "\tMOVSS $dst,[ESP+0]\n" 11018 "\tADD ESP,4\n" 11019 "\tFSTP ST0\t # Restore FPU Stack" 11020 %} 11021 ins_cost(250); 11022 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); 11023 ins_pipe( pipe_slow ); 11024 %} 11025 11026 11027 //----------Arithmetic Conversion Instructions--------------------------------- 11028 // The conversions operations are all Alpha sorted. Please keep it that way! 11029 11030 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ 11031 predicate(UseSSE==0); 11032 match(Set dst (RoundFloat src)); 11033 ins_cost(125); 11034 format %{ "FST_S $dst,$src\t# F-round" %} 11035 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); 11036 ins_pipe( fpu_mem_reg ); 11037 %} 11038 11039 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ 11040 predicate(UseSSE<=1); 11041 match(Set dst (RoundDouble src)); 11042 ins_cost(125); 11043 format %{ "FST_D $dst,$src\t# D-round" %} 11044 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); 11045 ins_pipe( fpu_mem_reg ); 11046 %} 11047 11048 // Force rounding to 24-bit precision and 6-bit exponent 11049 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ 11050 predicate(UseSSE==0); 11051 match(Set dst (ConvD2F src)); 11052 format %{ "FST_S $dst,$src\t# F-round" %} 11053 expand %{ 11054 roundFloat_mem_reg(dst,src); 11055 %} 11056 %} 11057 11058 // Force rounding to 24-bit precision and 6-bit exponent 11059 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ 11060 predicate(UseSSE==1); 11061 match(Set dst (ConvD2F src)); 11062 effect( KILL cr ); 11063 format %{ "SUB ESP,4\n\t" 11064 "FST_S [ESP],$src\t# F-round\n\t" 11065 "MOVSS $dst,[ESP]\n\t" 11066 "ADD ESP,4" %} 11067 ins_encode %{ 11068 __ subptr(rsp, 4); 11069 if ($src$$reg != FPR1L_enc) { 11070 __ fld_s($src$$reg-1); 11071 __ fstp_s(Address(rsp, 0)); 11072 } else { 11073 __ fst_s(Address(rsp, 0)); 11074 } 11075 __ movflt($dst$$XMMRegister, Address(rsp, 0)); 11076 __ addptr(rsp, 4); 11077 %} 11078 ins_pipe( pipe_slow ); 11079 %} 11080 11081 // Force rounding double precision to single precision 11082 instruct convD2F_reg(regF dst, regD src) %{ 11083 predicate(UseSSE>=2); 11084 match(Set dst (ConvD2F src)); 11085 format %{ "CVTSD2SS $dst,$src\t# F-round" %} 11086 ins_encode %{ 11087 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); 11088 %} 11089 ins_pipe( pipe_slow ); 11090 %} 11091 11092 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ 11093 predicate(UseSSE==0); 11094 match(Set dst (ConvF2D src)); 11095 format %{ "FST_S $dst,$src\t# D-round" %} 11096 ins_encode( Pop_Reg_Reg_DPR(dst, src)); 11097 ins_pipe( fpu_reg_reg ); 11098 %} 11099 11100 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ 11101 predicate(UseSSE==1); 11102 match(Set dst (ConvF2D src)); 11103 format %{ "FST_D $dst,$src\t# D-round" %} 11104 expand %{ 11105 roundDouble_mem_reg(dst,src); 11106 %} 11107 %} 11108 11109 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ 11110 predicate(UseSSE==1); 11111 match(Set dst (ConvF2D src)); 11112 effect( KILL cr ); 11113 format %{ "SUB ESP,4\n\t" 11114 "MOVSS [ESP] $src\n\t" 11115 "FLD_S [ESP]\n\t" 11116 "ADD ESP,4\n\t" 11117 "FSTP $dst\t# D-round" %} 11118 ins_encode %{ 11119 __ subptr(rsp, 4); 11120 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11121 __ fld_s(Address(rsp, 0)); 11122 __ addptr(rsp, 4); 11123 __ fstp_d($dst$$reg); 11124 %} 11125 ins_pipe( pipe_slow ); 11126 %} 11127 11128 instruct convF2D_reg(regD dst, regF src) %{ 11129 predicate(UseSSE>=2); 11130 match(Set dst (ConvF2D src)); 11131 format %{ "CVTSS2SD $dst,$src\t# D-round" %} 11132 ins_encode %{ 11133 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); 11134 %} 11135 ins_pipe( pipe_slow ); 11136 %} 11137 11138 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 11139 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ 11140 predicate(UseSSE<=1); 11141 match(Set dst (ConvD2I src)); 11142 effect( KILL tmp, KILL cr ); 11143 format %{ "FLD $src\t# Convert double to int \n\t" 11144 "FLDCW trunc mode\n\t" 11145 "SUB ESP,4\n\t" 11146 "FISTp [ESP + #0]\n\t" 11147 "FLDCW std/24-bit mode\n\t" 11148 "POP EAX\n\t" 11149 "CMP EAX,0x80000000\n\t" 11150 "JNE,s fast\n\t" 11151 "FLD_D $src\n\t" 11152 "CALL d2i_wrapper\n" 11153 "fast:" %} 11154 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); 11155 ins_pipe( pipe_slow ); 11156 %} 11157 11158 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 11159 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ 11160 predicate(UseSSE>=2); 11161 match(Set dst (ConvD2I src)); 11162 effect( KILL tmp, KILL cr ); 11163 format %{ "CVTTSD2SI $dst, $src\n\t" 11164 "CMP $dst,0x80000000\n\t" 11165 "JNE,s fast\n\t" 11166 "SUB ESP, 8\n\t" 11167 "MOVSD [ESP], $src\n\t" 11168 "FLD_D [ESP]\n\t" 11169 "ADD ESP, 8\n\t" 11170 "CALL d2i_wrapper\n" 11171 "fast:" %} 11172 ins_encode %{ 11173 Label fast; 11174 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); 11175 __ cmpl($dst$$Register, 0x80000000); 11176 __ jccb(Assembler::notEqual, fast); 11177 __ subptr(rsp, 8); 11178 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 11179 __ fld_d(Address(rsp, 0)); 11180 __ addptr(rsp, 8); 11181 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); 11182 __ bind(fast); 11183 %} 11184 ins_pipe( pipe_slow ); 11185 %} 11186 11187 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ 11188 predicate(UseSSE<=1); 11189 match(Set dst (ConvD2L src)); 11190 effect( KILL cr ); 11191 format %{ "FLD $src\t# Convert double to long\n\t" 11192 "FLDCW trunc mode\n\t" 11193 "SUB ESP,8\n\t" 11194 "FISTp [ESP + #0]\n\t" 11195 "FLDCW std/24-bit mode\n\t" 11196 "POP EAX\n\t" 11197 "POP EDX\n\t" 11198 "CMP EDX,0x80000000\n\t" 11199 "JNE,s fast\n\t" 11200 "TEST EAX,EAX\n\t" 11201 "JNE,s fast\n\t" 11202 "FLD $src\n\t" 11203 "CALL d2l_wrapper\n" 11204 "fast:" %} 11205 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); 11206 ins_pipe( pipe_slow ); 11207 %} 11208 11209 // XMM lacks a float/double->long conversion, so use the old FPU stack. 11210 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ 11211 predicate (UseSSE>=2); 11212 match(Set dst (ConvD2L src)); 11213 effect( KILL cr ); 11214 format %{ "SUB ESP,8\t# Convert double to long\n\t" 11215 "MOVSD [ESP],$src\n\t" 11216 "FLD_D [ESP]\n\t" 11217 "FLDCW trunc mode\n\t" 11218 "FISTp [ESP + #0]\n\t" 11219 "FLDCW std/24-bit mode\n\t" 11220 "POP EAX\n\t" 11221 "POP EDX\n\t" 11222 "CMP EDX,0x80000000\n\t" 11223 "JNE,s fast\n\t" 11224 "TEST EAX,EAX\n\t" 11225 "JNE,s fast\n\t" 11226 "SUB ESP,8\n\t" 11227 "MOVSD [ESP],$src\n\t" 11228 "FLD_D [ESP]\n\t" 11229 "ADD ESP,8\n\t" 11230 "CALL d2l_wrapper\n" 11231 "fast:" %} 11232 ins_encode %{ 11233 Label fast; 11234 __ subptr(rsp, 8); 11235 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 11236 __ fld_d(Address(rsp, 0)); 11237 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 11238 __ fistp_d(Address(rsp, 0)); 11239 // Restore the rounding mode, mask the exception 11240 if (Compile::current()->in_24_bit_fp_mode()) { 11241 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 11242 } else { 11243 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 11244 } 11245 // Load the converted long, adjust CPU stack 11246 __ pop(rax); 11247 __ pop(rdx); 11248 __ cmpl(rdx, 0x80000000); 11249 __ jccb(Assembler::notEqual, fast); 11250 __ testl(rax, rax); 11251 __ jccb(Assembler::notEqual, fast); 11252 __ subptr(rsp, 8); 11253 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 11254 __ fld_d(Address(rsp, 0)); 11255 __ addptr(rsp, 8); 11256 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); 11257 __ bind(fast); 11258 %} 11259 ins_pipe( pipe_slow ); 11260 %} 11261 11262 // Convert a double to an int. Java semantics require we do complex 11263 // manglations in the corner cases. So we set the rounding mode to 11264 // 'zero', store the darned double down as an int, and reset the 11265 // rounding mode to 'nearest'. The hardware stores a flag value down 11266 // if we would overflow or converted a NAN; we check for this and 11267 // and go the slow path if needed. 11268 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ 11269 predicate(UseSSE==0); 11270 match(Set dst (ConvF2I src)); 11271 effect( KILL tmp, KILL cr ); 11272 format %{ "FLD $src\t# Convert float to int \n\t" 11273 "FLDCW trunc mode\n\t" 11274 "SUB ESP,4\n\t" 11275 "FISTp [ESP + #0]\n\t" 11276 "FLDCW std/24-bit mode\n\t" 11277 "POP EAX\n\t" 11278 "CMP EAX,0x80000000\n\t" 11279 "JNE,s fast\n\t" 11280 "FLD $src\n\t" 11281 "CALL d2i_wrapper\n" 11282 "fast:" %} 11283 // DPR2I_encoding works for FPR2I 11284 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); 11285 ins_pipe( pipe_slow ); 11286 %} 11287 11288 // Convert a float in xmm to an int reg. 11289 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ 11290 predicate(UseSSE>=1); 11291 match(Set dst (ConvF2I src)); 11292 effect( KILL tmp, KILL cr ); 11293 format %{ "CVTTSS2SI $dst, $src\n\t" 11294 "CMP $dst,0x80000000\n\t" 11295 "JNE,s fast\n\t" 11296 "SUB ESP, 4\n\t" 11297 "MOVSS [ESP], $src\n\t" 11298 "FLD [ESP]\n\t" 11299 "ADD ESP, 4\n\t" 11300 "CALL d2i_wrapper\n" 11301 "fast:" %} 11302 ins_encode %{ 11303 Label fast; 11304 __ cvttss2sil($dst$$Register, $src$$XMMRegister); 11305 __ cmpl($dst$$Register, 0x80000000); 11306 __ jccb(Assembler::notEqual, fast); 11307 __ subptr(rsp, 4); 11308 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11309 __ fld_s(Address(rsp, 0)); 11310 __ addptr(rsp, 4); 11311 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); 11312 __ bind(fast); 11313 %} 11314 ins_pipe( pipe_slow ); 11315 %} 11316 11317 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ 11318 predicate(UseSSE==0); 11319 match(Set dst (ConvF2L src)); 11320 effect( KILL cr ); 11321 format %{ "FLD $src\t# Convert float to long\n\t" 11322 "FLDCW trunc mode\n\t" 11323 "SUB ESP,8\n\t" 11324 "FISTp [ESP + #0]\n\t" 11325 "FLDCW std/24-bit mode\n\t" 11326 "POP EAX\n\t" 11327 "POP EDX\n\t" 11328 "CMP EDX,0x80000000\n\t" 11329 "JNE,s fast\n\t" 11330 "TEST EAX,EAX\n\t" 11331 "JNE,s fast\n\t" 11332 "FLD $src\n\t" 11333 "CALL d2l_wrapper\n" 11334 "fast:" %} 11335 // DPR2L_encoding works for FPR2L 11336 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); 11337 ins_pipe( pipe_slow ); 11338 %} 11339 11340 // XMM lacks a float/double->long conversion, so use the old FPU stack. 11341 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ 11342 predicate (UseSSE>=1); 11343 match(Set dst (ConvF2L src)); 11344 effect( KILL cr ); 11345 format %{ "SUB ESP,8\t# Convert float to long\n\t" 11346 "MOVSS [ESP],$src\n\t" 11347 "FLD_S [ESP]\n\t" 11348 "FLDCW trunc mode\n\t" 11349 "FISTp [ESP + #0]\n\t" 11350 "FLDCW std/24-bit mode\n\t" 11351 "POP EAX\n\t" 11352 "POP EDX\n\t" 11353 "CMP EDX,0x80000000\n\t" 11354 "JNE,s fast\n\t" 11355 "TEST EAX,EAX\n\t" 11356 "JNE,s fast\n\t" 11357 "SUB ESP,4\t# Convert float to long\n\t" 11358 "MOVSS [ESP],$src\n\t" 11359 "FLD_S [ESP]\n\t" 11360 "ADD ESP,4\n\t" 11361 "CALL d2l_wrapper\n" 11362 "fast:" %} 11363 ins_encode %{ 11364 Label fast; 11365 __ subptr(rsp, 8); 11366 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11367 __ fld_s(Address(rsp, 0)); 11368 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 11369 __ fistp_d(Address(rsp, 0)); 11370 // Restore the rounding mode, mask the exception 11371 if (Compile::current()->in_24_bit_fp_mode()) { 11372 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 11373 } else { 11374 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 11375 } 11376 // Load the converted long, adjust CPU stack 11377 __ pop(rax); 11378 __ pop(rdx); 11379 __ cmpl(rdx, 0x80000000); 11380 __ jccb(Assembler::notEqual, fast); 11381 __ testl(rax, rax); 11382 __ jccb(Assembler::notEqual, fast); 11383 __ subptr(rsp, 4); 11384 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11385 __ fld_s(Address(rsp, 0)); 11386 __ addptr(rsp, 4); 11387 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); 11388 __ bind(fast); 11389 %} 11390 ins_pipe( pipe_slow ); 11391 %} 11392 11393 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ 11394 predicate( UseSSE<=1 ); 11395 match(Set dst (ConvI2D src)); 11396 format %{ "FILD $src\n\t" 11397 "FSTP $dst" %} 11398 opcode(0xDB, 0x0); /* DB /0 */ 11399 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); 11400 ins_pipe( fpu_reg_mem ); 11401 %} 11402 11403 instruct convI2D_reg(regD dst, eRegI src) %{ 11404 predicate( UseSSE>=2 && !UseXmmI2D ); 11405 match(Set dst (ConvI2D src)); 11406 format %{ "CVTSI2SD $dst,$src" %} 11407 ins_encode %{ 11408 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); 11409 %} 11410 ins_pipe( pipe_slow ); 11411 %} 11412 11413 instruct convI2D_mem(regD dst, memory mem) %{ 11414 predicate( UseSSE>=2 ); 11415 match(Set dst (ConvI2D (LoadI mem))); 11416 format %{ "CVTSI2SD $dst,$mem" %} 11417 ins_encode %{ 11418 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); 11419 %} 11420 ins_pipe( pipe_slow ); 11421 %} 11422 11423 instruct convXI2D_reg(regD dst, eRegI src) 11424 %{ 11425 predicate( UseSSE>=2 && UseXmmI2D ); 11426 match(Set dst (ConvI2D src)); 11427 11428 format %{ "MOVD $dst,$src\n\t" 11429 "CVTDQ2PD $dst,$dst\t# i2d" %} 11430 ins_encode %{ 11431 __ movdl($dst$$XMMRegister, $src$$Register); 11432 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 11433 %} 11434 ins_pipe(pipe_slow); // XXX 11435 %} 11436 11437 instruct convI2DPR_mem(regDPR dst, memory mem) %{ 11438 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11439 match(Set dst (ConvI2D (LoadI mem))); 11440 format %{ "FILD $mem\n\t" 11441 "FSTP $dst" %} 11442 opcode(0xDB); /* DB /0 */ 11443 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11444 Pop_Reg_DPR(dst)); 11445 ins_pipe( fpu_reg_mem ); 11446 %} 11447 11448 // Convert a byte to a float; no rounding step needed. 11449 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ 11450 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); 11451 match(Set dst (ConvI2F src)); 11452 format %{ "FILD $src\n\t" 11453 "FSTP $dst" %} 11454 11455 opcode(0xDB, 0x0); /* DB /0 */ 11456 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); 11457 ins_pipe( fpu_reg_mem ); 11458 %} 11459 11460 // In 24-bit mode, force exponent rounding by storing back out 11461 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ 11462 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11463 match(Set dst (ConvI2F src)); 11464 ins_cost(200); 11465 format %{ "FILD $src\n\t" 11466 "FSTP_S $dst" %} 11467 opcode(0xDB, 0x0); /* DB /0 */ 11468 ins_encode( Push_Mem_I(src), 11469 Pop_Mem_FPR(dst)); 11470 ins_pipe( fpu_mem_mem ); 11471 %} 11472 11473 // In 24-bit mode, force exponent rounding by storing back out 11474 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ 11475 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11476 match(Set dst (ConvI2F (LoadI mem))); 11477 ins_cost(200); 11478 format %{ "FILD $mem\n\t" 11479 "FSTP_S $dst" %} 11480 opcode(0xDB); /* DB /0 */ 11481 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11482 Pop_Mem_FPR(dst)); 11483 ins_pipe( fpu_mem_mem ); 11484 %} 11485 11486 // This instruction does not round to 24-bits 11487 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ 11488 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11489 match(Set dst (ConvI2F src)); 11490 format %{ "FILD $src\n\t" 11491 "FSTP $dst" %} 11492 opcode(0xDB, 0x0); /* DB /0 */ 11493 ins_encode( Push_Mem_I(src), 11494 Pop_Reg_FPR(dst)); 11495 ins_pipe( fpu_reg_mem ); 11496 %} 11497 11498 // This instruction does not round to 24-bits 11499 instruct convI2FPR_mem(regFPR dst, memory mem) %{ 11500 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11501 match(Set dst (ConvI2F (LoadI mem))); 11502 format %{ "FILD $mem\n\t" 11503 "FSTP $dst" %} 11504 opcode(0xDB); /* DB /0 */ 11505 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11506 Pop_Reg_FPR(dst)); 11507 ins_pipe( fpu_reg_mem ); 11508 %} 11509 11510 // Convert an int to a float in xmm; no rounding step needed. 11511 instruct convI2F_reg(regF dst, eRegI src) %{ 11512 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 11513 match(Set dst (ConvI2F src)); 11514 format %{ "CVTSI2SS $dst, $src" %} 11515 ins_encode %{ 11516 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); 11517 %} 11518 ins_pipe( pipe_slow ); 11519 %} 11520 11521 instruct convXI2F_reg(regF dst, eRegI src) 11522 %{ 11523 predicate( UseSSE>=2 && UseXmmI2F ); 11524 match(Set dst (ConvI2F src)); 11525 11526 format %{ "MOVD $dst,$src\n\t" 11527 "CVTDQ2PS $dst,$dst\t# i2f" %} 11528 ins_encode %{ 11529 __ movdl($dst$$XMMRegister, $src$$Register); 11530 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 11531 %} 11532 ins_pipe(pipe_slow); // XXX 11533 %} 11534 11535 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 11536 match(Set dst (ConvI2L src)); 11537 effect(KILL cr); 11538 ins_cost(375); 11539 format %{ "MOV $dst.lo,$src\n\t" 11540 "MOV $dst.hi,$src\n\t" 11541 "SAR $dst.hi,31" %} 11542 ins_encode(convert_int_long(dst,src)); 11543 ins_pipe( ialu_reg_reg_long ); 11544 %} 11545 11546 // Zero-extend convert int to long 11547 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ 11548 match(Set dst (AndL (ConvI2L src) mask) ); 11549 effect( KILL flags ); 11550 ins_cost(250); 11551 format %{ "MOV $dst.lo,$src\n\t" 11552 "XOR $dst.hi,$dst.hi" %} 11553 opcode(0x33); // XOR 11554 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11555 ins_pipe( ialu_reg_reg_long ); 11556 %} 11557 11558 // Zero-extend long 11559 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ 11560 match(Set dst (AndL src mask) ); 11561 effect( KILL flags ); 11562 ins_cost(250); 11563 format %{ "MOV $dst.lo,$src.lo\n\t" 11564 "XOR $dst.hi,$dst.hi\n\t" %} 11565 opcode(0x33); // XOR 11566 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11567 ins_pipe( ialu_reg_reg_long ); 11568 %} 11569 11570 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ 11571 predicate (UseSSE<=1); 11572 match(Set dst (ConvL2D src)); 11573 effect( KILL cr ); 11574 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11575 "PUSH $src.lo\n\t" 11576 "FILD ST,[ESP + #0]\n\t" 11577 "ADD ESP,8\n\t" 11578 "FSTP_D $dst\t# D-round" %} 11579 opcode(0xDF, 0x5); /* DF /5 */ 11580 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); 11581 ins_pipe( pipe_slow ); 11582 %} 11583 11584 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ 11585 predicate (UseSSE>=2); 11586 match(Set dst (ConvL2D src)); 11587 effect( KILL cr ); 11588 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11589 "PUSH $src.lo\n\t" 11590 "FILD_D [ESP]\n\t" 11591 "FSTP_D [ESP]\n\t" 11592 "MOVSD $dst,[ESP]\n\t" 11593 "ADD ESP,8" %} 11594 opcode(0xDF, 0x5); /* DF /5 */ 11595 ins_encode(convert_long_double2(src), Push_ResultD(dst)); 11596 ins_pipe( pipe_slow ); 11597 %} 11598 11599 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ 11600 predicate (UseSSE>=1); 11601 match(Set dst (ConvL2F src)); 11602 effect( KILL cr ); 11603 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11604 "PUSH $src.lo\n\t" 11605 "FILD_D [ESP]\n\t" 11606 "FSTP_S [ESP]\n\t" 11607 "MOVSS $dst,[ESP]\n\t" 11608 "ADD ESP,8" %} 11609 opcode(0xDF, 0x5); /* DF /5 */ 11610 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); 11611 ins_pipe( pipe_slow ); 11612 %} 11613 11614 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ 11615 match(Set dst (ConvL2F src)); 11616 effect( KILL cr ); 11617 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11618 "PUSH $src.lo\n\t" 11619 "FILD ST,[ESP + #0]\n\t" 11620 "ADD ESP,8\n\t" 11621 "FSTP_S $dst\t# F-round" %} 11622 opcode(0xDF, 0x5); /* DF /5 */ 11623 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); 11624 ins_pipe( pipe_slow ); 11625 %} 11626 11627 instruct convL2I_reg( eRegI dst, eRegL src ) %{ 11628 match(Set dst (ConvL2I src)); 11629 effect( DEF dst, USE src ); 11630 format %{ "MOV $dst,$src.lo" %} 11631 ins_encode(enc_CopyL_Lo(dst,src)); 11632 ins_pipe( ialu_reg_reg ); 11633 %} 11634 11635 11636 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ 11637 match(Set dst (MoveF2I src)); 11638 effect( DEF dst, USE src ); 11639 ins_cost(100); 11640 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 11641 ins_encode %{ 11642 __ movl($dst$$Register, Address(rsp, $src$$disp)); 11643 %} 11644 ins_pipe( ialu_reg_mem ); 11645 %} 11646 11647 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ 11648 predicate(UseSSE==0); 11649 match(Set dst (MoveF2I src)); 11650 effect( DEF dst, USE src ); 11651 11652 ins_cost(125); 11653 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} 11654 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); 11655 ins_pipe( fpu_mem_reg ); 11656 %} 11657 11658 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ 11659 predicate(UseSSE>=1); 11660 match(Set dst (MoveF2I src)); 11661 effect( DEF dst, USE src ); 11662 11663 ins_cost(95); 11664 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} 11665 ins_encode %{ 11666 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); 11667 %} 11668 ins_pipe( pipe_slow ); 11669 %} 11670 11671 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{ 11672 predicate(UseSSE>=2); 11673 match(Set dst (MoveF2I src)); 11674 effect( DEF dst, USE src ); 11675 ins_cost(85); 11676 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 11677 ins_encode %{ 11678 __ movdl($dst$$Register, $src$$XMMRegister); 11679 %} 11680 ins_pipe( pipe_slow ); 11681 %} 11682 11683 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ 11684 match(Set dst (MoveI2F src)); 11685 effect( DEF dst, USE src ); 11686 11687 ins_cost(100); 11688 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 11689 ins_encode %{ 11690 __ movl(Address(rsp, $dst$$disp), $src$$Register); 11691 %} 11692 ins_pipe( ialu_mem_reg ); 11693 %} 11694 11695 11696 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ 11697 predicate(UseSSE==0); 11698 match(Set dst (MoveI2F src)); 11699 effect(DEF dst, USE src); 11700 11701 ins_cost(125); 11702 format %{ "FLD_S $src\n\t" 11703 "FSTP $dst\t# MoveI2F_stack_reg" %} 11704 opcode(0xD9); /* D9 /0, FLD m32real */ 11705 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11706 Pop_Reg_FPR(dst) ); 11707 ins_pipe( fpu_reg_mem ); 11708 %} 11709 11710 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ 11711 predicate(UseSSE>=1); 11712 match(Set dst (MoveI2F src)); 11713 effect( DEF dst, USE src ); 11714 11715 ins_cost(95); 11716 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} 11717 ins_encode %{ 11718 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); 11719 %} 11720 ins_pipe( pipe_slow ); 11721 %} 11722 11723 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{ 11724 predicate(UseSSE>=2); 11725 match(Set dst (MoveI2F src)); 11726 effect( DEF dst, USE src ); 11727 11728 ins_cost(85); 11729 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} 11730 ins_encode %{ 11731 __ movdl($dst$$XMMRegister, $src$$Register); 11732 %} 11733 ins_pipe( pipe_slow ); 11734 %} 11735 11736 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ 11737 match(Set dst (MoveD2L src)); 11738 effect(DEF dst, USE src); 11739 11740 ins_cost(250); 11741 format %{ "MOV $dst.lo,$src\n\t" 11742 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} 11743 opcode(0x8B, 0x8B); 11744 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); 11745 ins_pipe( ialu_mem_long_reg ); 11746 %} 11747 11748 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ 11749 predicate(UseSSE<=1); 11750 match(Set dst (MoveD2L src)); 11751 effect(DEF dst, USE src); 11752 11753 ins_cost(125); 11754 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} 11755 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); 11756 ins_pipe( fpu_mem_reg ); 11757 %} 11758 11759 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ 11760 predicate(UseSSE>=2); 11761 match(Set dst (MoveD2L src)); 11762 effect(DEF dst, USE src); 11763 ins_cost(95); 11764 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} 11765 ins_encode %{ 11766 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); 11767 %} 11768 ins_pipe( pipe_slow ); 11769 %} 11770 11771 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ 11772 predicate(UseSSE>=2); 11773 match(Set dst (MoveD2L src)); 11774 effect(DEF dst, USE src, TEMP tmp); 11775 ins_cost(85); 11776 format %{ "MOVD $dst.lo,$src\n\t" 11777 "PSHUFLW $tmp,$src,0x4E\n\t" 11778 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} 11779 ins_encode %{ 11780 __ movdl($dst$$Register, $src$$XMMRegister); 11781 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); 11782 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); 11783 %} 11784 ins_pipe( pipe_slow ); 11785 %} 11786 11787 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ 11788 match(Set dst (MoveL2D src)); 11789 effect(DEF dst, USE src); 11790 11791 ins_cost(200); 11792 format %{ "MOV $dst,$src.lo\n\t" 11793 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} 11794 opcode(0x89, 0x89); 11795 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 11796 ins_pipe( ialu_mem_long_reg ); 11797 %} 11798 11799 11800 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ 11801 predicate(UseSSE<=1); 11802 match(Set dst (MoveL2D src)); 11803 effect(DEF dst, USE src); 11804 ins_cost(125); 11805 11806 format %{ "FLD_D $src\n\t" 11807 "FSTP $dst\t# MoveL2D_stack_reg" %} 11808 opcode(0xDD); /* DD /0, FLD m64real */ 11809 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11810 Pop_Reg_DPR(dst) ); 11811 ins_pipe( fpu_reg_mem ); 11812 %} 11813 11814 11815 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ 11816 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 11817 match(Set dst (MoveL2D src)); 11818 effect(DEF dst, USE src); 11819 11820 ins_cost(95); 11821 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11822 ins_encode %{ 11823 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 11824 %} 11825 ins_pipe( pipe_slow ); 11826 %} 11827 11828 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ 11829 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 11830 match(Set dst (MoveL2D src)); 11831 effect(DEF dst, USE src); 11832 11833 ins_cost(95); 11834 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11835 ins_encode %{ 11836 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 11837 %} 11838 ins_pipe( pipe_slow ); 11839 %} 11840 11841 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ 11842 predicate(UseSSE>=2); 11843 match(Set dst (MoveL2D src)); 11844 effect(TEMP dst, USE src, TEMP tmp); 11845 ins_cost(85); 11846 format %{ "MOVD $dst,$src.lo\n\t" 11847 "MOVD $tmp,$src.hi\n\t" 11848 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} 11849 ins_encode %{ 11850 __ movdl($dst$$XMMRegister, $src$$Register); 11851 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); 11852 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); 11853 %} 11854 ins_pipe( pipe_slow ); 11855 %} 11856 11857 // Replicate scalar to packed byte (1 byte) values in xmm 11858 instruct Repl8B_reg(regD dst, regD src) %{ 11859 predicate(UseSSE>=2); 11860 match(Set dst (Replicate8B src)); 11861 format %{ "MOVDQA $dst,$src\n\t" 11862 "PUNPCKLBW $dst,$dst\n\t" 11863 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11864 ins_encode %{ 11865 if ($dst$$reg != $src$$reg) { 11866 __ movdqa($dst$$XMMRegister, $src$$XMMRegister); 11867 } 11868 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); 11869 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); 11870 %} 11871 ins_pipe( pipe_slow ); 11872 %} 11873 11874 // Replicate scalar to packed byte (1 byte) values in xmm 11875 instruct Repl8B_eRegI(regD dst, eRegI src) %{ 11876 predicate(UseSSE>=2); 11877 match(Set dst (Replicate8B src)); 11878 format %{ "MOVD $dst,$src\n\t" 11879 "PUNPCKLBW $dst,$dst\n\t" 11880 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11881 ins_encode %{ 11882 __ movdl($dst$$XMMRegister, $src$$Register); 11883 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); 11884 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); 11885 %} 11886 ins_pipe( pipe_slow ); 11887 %} 11888 11889 // Replicate scalar zero to packed byte (1 byte) values in xmm 11890 instruct Repl8B_immI0(regD dst, immI0 zero) %{ 11891 predicate(UseSSE>=2); 11892 match(Set dst (Replicate8B zero)); 11893 format %{ "PXOR $dst,$dst\t! replicate8B" %} 11894 ins_encode %{ 11895 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); 11896 %} 11897 ins_pipe( fpu_reg_reg ); 11898 %} 11899 11900 // Replicate scalar to packed shore (2 byte) values in xmm 11901 instruct Repl4S_reg(regD dst, regD src) %{ 11902 predicate(UseSSE>=2); 11903 match(Set dst (Replicate4S src)); 11904 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} 11905 ins_encode %{ 11906 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); 11907 %} 11908 ins_pipe( fpu_reg_reg ); 11909 %} 11910 11911 // Replicate scalar to packed shore (2 byte) values in xmm 11912 instruct Repl4S_eRegI(regD dst, eRegI src) %{ 11913 predicate(UseSSE>=2); 11914 match(Set dst (Replicate4S src)); 11915 format %{ "MOVD $dst,$src\n\t" 11916 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} 11917 ins_encode %{ 11918 __ movdl($dst$$XMMRegister, $src$$Register); 11919 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); 11920 %} 11921 ins_pipe( fpu_reg_reg ); 11922 %} 11923 11924 // Replicate scalar zero to packed short (2 byte) values in xmm 11925 instruct Repl4S_immI0(regD dst, immI0 zero) %{ 11926 predicate(UseSSE>=2); 11927 match(Set dst (Replicate4S zero)); 11928 format %{ "PXOR $dst,$dst\t! replicate4S" %} 11929 ins_encode %{ 11930 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); 11931 %} 11932 ins_pipe( fpu_reg_reg ); 11933 %} 11934 11935 // Replicate scalar to packed char (2 byte) values in xmm 11936 instruct Repl4C_reg(regD dst, regD src) %{ 11937 predicate(UseSSE>=2); 11938 match(Set dst (Replicate4C src)); 11939 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} 11940 ins_encode %{ 11941 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); 11942 %} 11943 ins_pipe( fpu_reg_reg ); 11944 %} 11945 11946 // Replicate scalar to packed char (2 byte) values in xmm 11947 instruct Repl4C_eRegI(regD dst, eRegI src) %{ 11948 predicate(UseSSE>=2); 11949 match(Set dst (Replicate4C src)); 11950 format %{ "MOVD $dst,$src\n\t" 11951 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} 11952 ins_encode %{ 11953 __ movdl($dst$$XMMRegister, $src$$Register); 11954 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); 11955 %} 11956 ins_pipe( fpu_reg_reg ); 11957 %} 11958 11959 // Replicate scalar zero to packed char (2 byte) values in xmm 11960 instruct Repl4C_immI0(regD dst, immI0 zero) %{ 11961 predicate(UseSSE>=2); 11962 match(Set dst (Replicate4C zero)); 11963 format %{ "PXOR $dst,$dst\t! replicate4C" %} 11964 ins_encode %{ 11965 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); 11966 %} 11967 ins_pipe( fpu_reg_reg ); 11968 %} 11969 11970 // Replicate scalar to packed integer (4 byte) values in xmm 11971 instruct Repl2I_reg(regD dst, regD src) %{ 11972 predicate(UseSSE>=2); 11973 match(Set dst (Replicate2I src)); 11974 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} 11975 ins_encode %{ 11976 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); 11977 %} 11978 ins_pipe( fpu_reg_reg ); 11979 %} 11980 11981 // Replicate scalar to packed integer (4 byte) values in xmm 11982 instruct Repl2I_eRegI(regD dst, eRegI src) %{ 11983 predicate(UseSSE>=2); 11984 match(Set dst (Replicate2I src)); 11985 format %{ "MOVD $dst,$src\n\t" 11986 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} 11987 ins_encode %{ 11988 __ movdl($dst$$XMMRegister, $src$$Register); 11989 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); 11990 %} 11991 ins_pipe( fpu_reg_reg ); 11992 %} 11993 11994 // Replicate scalar zero to packed integer (2 byte) values in xmm 11995 instruct Repl2I_immI0(regD dst, immI0 zero) %{ 11996 predicate(UseSSE>=2); 11997 match(Set dst (Replicate2I zero)); 11998 format %{ "PXOR $dst,$dst\t! replicate2I" %} 11999 ins_encode %{ 12000 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); 12001 %} 12002 ins_pipe( fpu_reg_reg ); 12003 %} 12004 12005 // Replicate scalar to packed single precision floating point values in xmm 12006 instruct Repl2F_reg(regD dst, regD src) %{ 12007 predicate(UseSSE>=2); 12008 match(Set dst (Replicate2F src)); 12009 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 12010 ins_encode %{ 12011 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); 12012 %} 12013 ins_pipe( fpu_reg_reg ); 12014 %} 12015 12016 // Replicate scalar to packed single precision floating point values in xmm 12017 instruct Repl2F_regF(regD dst, regF src) %{ 12018 predicate(UseSSE>=2); 12019 match(Set dst (Replicate2F src)); 12020 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 12021 ins_encode %{ 12022 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); 12023 %} 12024 ins_pipe( fpu_reg_reg ); 12025 %} 12026 12027 // Replicate scalar to packed single precision floating point values in xmm 12028 instruct Repl2F_immF0(regD dst, immF0 zero) %{ 12029 predicate(UseSSE>=2); 12030 match(Set dst (Replicate2F zero)); 12031 format %{ "PXOR $dst,$dst\t! replicate2F" %} 12032 ins_encode %{ 12033 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); 12034 %} 12035 ins_pipe( fpu_reg_reg ); 12036 %} 12037 12038 // ======================================================================= 12039 // fast clearing of an array 12040 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 12041 match(Set dummy (ClearArray cnt base)); 12042 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); 12043 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" 12044 "XOR EAX,EAX\n\t" 12045 "REP STOS\t# store EAX into [EDI++] while ECX--" %} 12046 opcode(0,0x4); 12047 ins_encode( Opcode(0xD1), RegOpc(ECX), 12048 OpcRegReg(0x33,EAX,EAX), 12049 Opcode(0xF3), Opcode(0xAB) ); 12050 ins_pipe( pipe_slow ); 12051 %} 12052 12053 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, 12054 eAXRegI result, regD tmp1, eFlagsReg cr) %{ 12055 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 12056 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 12057 12058 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 12059 ins_encode %{ 12060 __ string_compare($str1$$Register, $str2$$Register, 12061 $cnt1$$Register, $cnt2$$Register, $result$$Register, 12062 $tmp1$$XMMRegister); 12063 %} 12064 ins_pipe( pipe_slow ); 12065 %} 12066 12067 // fast string equals 12068 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, 12069 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ 12070 match(Set result (StrEquals (Binary str1 str2) cnt)); 12071 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); 12072 12073 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} 12074 ins_encode %{ 12075 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, 12076 $cnt$$Register, $result$$Register, $tmp3$$Register, 12077 $tmp1$$XMMRegister, $tmp2$$XMMRegister); 12078 %} 12079 ins_pipe( pipe_slow ); 12080 %} 12081 12082 // fast search of substring with known size. 12083 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, 12084 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ 12085 predicate(UseSSE42Intrinsics); 12086 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); 12087 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); 12088 12089 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} 12090 ins_encode %{ 12091 int icnt2 = (int)$int_cnt2$$constant; 12092 if (icnt2 >= 8) { 12093 // IndexOf for constant substrings with size >= 8 elements 12094 // which don't need to be loaded through stack. 12095 __ string_indexofC8($str1$$Register, $str2$$Register, 12096 $cnt1$$Register, $cnt2$$Register, 12097 icnt2, $result$$Register, 12098 $vec$$XMMRegister, $tmp$$Register); 12099 } else { 12100 // Small strings are loaded through stack if they cross page boundary. 12101 __ string_indexof($str1$$Register, $str2$$Register, 12102 $cnt1$$Register, $cnt2$$Register, 12103 icnt2, $result$$Register, 12104 $vec$$XMMRegister, $tmp$$Register); 12105 } 12106 %} 12107 ins_pipe( pipe_slow ); 12108 %} 12109 12110 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, 12111 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ 12112 predicate(UseSSE42Intrinsics); 12113 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); 12114 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); 12115 12116 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} 12117 ins_encode %{ 12118 __ string_indexof($str1$$Register, $str2$$Register, 12119 $cnt1$$Register, $cnt2$$Register, 12120 (-1), $result$$Register, 12121 $vec$$XMMRegister, $tmp$$Register); 12122 %} 12123 ins_pipe( pipe_slow ); 12124 %} 12125 12126 // fast array equals 12127 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, 12128 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) 12129 %{ 12130 match(Set result (AryEq ary1 ary2)); 12131 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); 12132 //ins_cost(300); 12133 12134 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} 12135 ins_encode %{ 12136 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, 12137 $tmp3$$Register, $result$$Register, $tmp4$$Register, 12138 $tmp1$$XMMRegister, $tmp2$$XMMRegister); 12139 %} 12140 ins_pipe( pipe_slow ); 12141 %} 12142 12143 //----------Control Flow Instructions------------------------------------------ 12144 // Signed compare Instructions 12145 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ 12146 match(Set cr (CmpI op1 op2)); 12147 effect( DEF cr, USE op1, USE op2 ); 12148 format %{ "CMP $op1,$op2" %} 12149 opcode(0x3B); /* Opcode 3B /r */ 12150 ins_encode( OpcP, RegReg( op1, op2) ); 12151 ins_pipe( ialu_cr_reg_reg ); 12152 %} 12153 12154 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ 12155 match(Set cr (CmpI op1 op2)); 12156 effect( DEF cr, USE op1 ); 12157 format %{ "CMP $op1,$op2" %} 12158 opcode(0x81,0x07); /* Opcode 81 /7 */ 12159 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 12160 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12161 ins_pipe( ialu_cr_reg_imm ); 12162 %} 12163 12164 // Cisc-spilled version of cmpI_eReg 12165 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ 12166 match(Set cr (CmpI op1 (LoadI op2))); 12167 12168 format %{ "CMP $op1,$op2" %} 12169 ins_cost(500); 12170 opcode(0x3B); /* Opcode 3B /r */ 12171 ins_encode( OpcP, RegMem( op1, op2) ); 12172 ins_pipe( ialu_cr_reg_mem ); 12173 %} 12174 12175 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ 12176 match(Set cr (CmpI src zero)); 12177 effect( DEF cr, USE src ); 12178 12179 format %{ "TEST $src,$src" %} 12180 opcode(0x85); 12181 ins_encode( OpcP, RegReg( src, src ) ); 12182 ins_pipe( ialu_cr_reg_imm ); 12183 %} 12184 12185 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ 12186 match(Set cr (CmpI (AndI src con) zero)); 12187 12188 format %{ "TEST $src,$con" %} 12189 opcode(0xF7,0x00); 12190 ins_encode( OpcP, RegOpc(src), Con32(con) ); 12191 ins_pipe( ialu_cr_reg_imm ); 12192 %} 12193 12194 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ 12195 match(Set cr (CmpI (AndI src mem) zero)); 12196 12197 format %{ "TEST $src,$mem" %} 12198 opcode(0x85); 12199 ins_encode( OpcP, RegMem( src, mem ) ); 12200 ins_pipe( ialu_cr_reg_mem ); 12201 %} 12202 12203 // Unsigned compare Instructions; really, same as signed except they 12204 // produce an eFlagsRegU instead of eFlagsReg. 12205 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ 12206 match(Set cr (CmpU op1 op2)); 12207 12208 format %{ "CMPu $op1,$op2" %} 12209 opcode(0x3B); /* Opcode 3B /r */ 12210 ins_encode( OpcP, RegReg( op1, op2) ); 12211 ins_pipe( ialu_cr_reg_reg ); 12212 %} 12213 12214 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ 12215 match(Set cr (CmpU op1 op2)); 12216 12217 format %{ "CMPu $op1,$op2" %} 12218 opcode(0x81,0x07); /* Opcode 81 /7 */ 12219 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12220 ins_pipe( ialu_cr_reg_imm ); 12221 %} 12222 12223 // // Cisc-spilled version of cmpU_eReg 12224 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ 12225 match(Set cr (CmpU op1 (LoadI op2))); 12226 12227 format %{ "CMPu $op1,$op2" %} 12228 ins_cost(500); 12229 opcode(0x3B); /* Opcode 3B /r */ 12230 ins_encode( OpcP, RegMem( op1, op2) ); 12231 ins_pipe( ialu_cr_reg_mem ); 12232 %} 12233 12234 // // Cisc-spilled version of cmpU_eReg 12235 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ 12236 // match(Set cr (CmpU (LoadI op1) op2)); 12237 // 12238 // format %{ "CMPu $op1,$op2" %} 12239 // ins_cost(500); 12240 // opcode(0x39); /* Opcode 39 /r */ 12241 // ins_encode( OpcP, RegMem( op1, op2) ); 12242 //%} 12243 12244 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ 12245 match(Set cr (CmpU src zero)); 12246 12247 format %{ "TESTu $src,$src" %} 12248 opcode(0x85); 12249 ins_encode( OpcP, RegReg( src, src ) ); 12250 ins_pipe( ialu_cr_reg_imm ); 12251 %} 12252 12253 // Unsigned pointer compare Instructions 12254 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ 12255 match(Set cr (CmpP op1 op2)); 12256 12257 format %{ "CMPu $op1,$op2" %} 12258 opcode(0x3B); /* Opcode 3B /r */ 12259 ins_encode( OpcP, RegReg( op1, op2) ); 12260 ins_pipe( ialu_cr_reg_reg ); 12261 %} 12262 12263 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ 12264 match(Set cr (CmpP op1 op2)); 12265 12266 format %{ "CMPu $op1,$op2" %} 12267 opcode(0x81,0x07); /* Opcode 81 /7 */ 12268 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 12269 ins_pipe( ialu_cr_reg_imm ); 12270 %} 12271 12272 // // Cisc-spilled version of cmpP_eReg 12273 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ 12274 match(Set cr (CmpP op1 (LoadP op2))); 12275 12276 format %{ "CMPu $op1,$op2" %} 12277 ins_cost(500); 12278 opcode(0x3B); /* Opcode 3B /r */ 12279 ins_encode( OpcP, RegMem( op1, op2) ); 12280 ins_pipe( ialu_cr_reg_mem ); 12281 %} 12282 12283 // // Cisc-spilled version of cmpP_eReg 12284 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ 12285 // match(Set cr (CmpP (LoadP op1) op2)); 12286 // 12287 // format %{ "CMPu $op1,$op2" %} 12288 // ins_cost(500); 12289 // opcode(0x39); /* Opcode 39 /r */ 12290 // ins_encode( OpcP, RegMem( op1, op2) ); 12291 //%} 12292 12293 // Compare raw pointer (used in out-of-heap check). 12294 // Only works because non-oop pointers must be raw pointers 12295 // and raw pointers have no anti-dependencies. 12296 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 12297 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); 12298 match(Set cr (CmpP op1 (LoadP op2))); 12299 12300 format %{ "CMPu $op1,$op2" %} 12301 opcode(0x3B); /* Opcode 3B /r */ 12302 ins_encode( OpcP, RegMem( op1, op2) ); 12303 ins_pipe( ialu_cr_reg_mem ); 12304 %} 12305 12306 // 12307 // This will generate a signed flags result. This should be ok 12308 // since any compare to a zero should be eq/neq. 12309 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ 12310 match(Set cr (CmpP src zero)); 12311 12312 format %{ "TEST $src,$src" %} 12313 opcode(0x85); 12314 ins_encode( OpcP, RegReg( src, src ) ); 12315 ins_pipe( ialu_cr_reg_imm ); 12316 %} 12317 12318 // Cisc-spilled version of testP_reg 12319 // This will generate a signed flags result. This should be ok 12320 // since any compare to a zero should be eq/neq. 12321 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ 12322 match(Set cr (CmpP (LoadP op) zero)); 12323 12324 format %{ "TEST $op,0xFFFFFFFF" %} 12325 ins_cost(500); 12326 opcode(0xF7); /* Opcode F7 /0 */ 12327 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); 12328 ins_pipe( ialu_cr_reg_imm ); 12329 %} 12330 12331 // Yanked all unsigned pointer compare operations. 12332 // Pointer compares are done with CmpP which is already unsigned. 12333 12334 //----------Max and Min-------------------------------------------------------- 12335 // Min Instructions 12336 //// 12337 // *** Min and Max using the conditional move are slower than the 12338 // *** branch version on a Pentium III. 12339 // // Conditional move for min 12340 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 12341 // effect( USE_DEF op2, USE op1, USE cr ); 12342 // format %{ "CMOVlt $op2,$op1\t! min" %} 12343 // opcode(0x4C,0x0F); 12344 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 12345 // ins_pipe( pipe_cmov_reg ); 12346 //%} 12347 // 12348 //// Min Register with Register (P6 version) 12349 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ 12350 // predicate(VM_Version::supports_cmov() ); 12351 // match(Set op2 (MinI op1 op2)); 12352 // ins_cost(200); 12353 // expand %{ 12354 // eFlagsReg cr; 12355 // compI_eReg(cr,op1,op2); 12356 // cmovI_reg_lt(op2,op1,cr); 12357 // %} 12358 //%} 12359 12360 // Min Register with Register (generic version) 12361 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 12362 match(Set dst (MinI dst src)); 12363 effect(KILL flags); 12364 ins_cost(300); 12365 12366 format %{ "MIN $dst,$src" %} 12367 opcode(0xCC); 12368 ins_encode( min_enc(dst,src) ); 12369 ins_pipe( pipe_slow ); 12370 %} 12371 12372 // Max Register with Register 12373 // *** Min and Max using the conditional move are slower than the 12374 // *** branch version on a Pentium III. 12375 // // Conditional move for max 12376 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 12377 // effect( USE_DEF op2, USE op1, USE cr ); 12378 // format %{ "CMOVgt $op2,$op1\t! max" %} 12379 // opcode(0x4F,0x0F); 12380 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 12381 // ins_pipe( pipe_cmov_reg ); 12382 //%} 12383 // 12384 // // Max Register with Register (P6 version) 12385 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ 12386 // predicate(VM_Version::supports_cmov() ); 12387 // match(Set op2 (MaxI op1 op2)); 12388 // ins_cost(200); 12389 // expand %{ 12390 // eFlagsReg cr; 12391 // compI_eReg(cr,op1,op2); 12392 // cmovI_reg_gt(op2,op1,cr); 12393 // %} 12394 //%} 12395 12396 // Max Register with Register (generic version) 12397 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 12398 match(Set dst (MaxI dst src)); 12399 effect(KILL flags); 12400 ins_cost(300); 12401 12402 format %{ "MAX $dst,$src" %} 12403 opcode(0xCC); 12404 ins_encode( max_enc(dst,src) ); 12405 ins_pipe( pipe_slow ); 12406 %} 12407 12408 // ============================================================================ 12409 // Counted Loop limit node which represents exact final iterator value. 12410 // Note: the resulting value should fit into integer range since 12411 // counted loops have limit check on overflow. 12412 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ 12413 match(Set limit (LoopLimit (Binary init limit) stride)); 12414 effect(TEMP limit_hi, TEMP tmp, KILL flags); 12415 ins_cost(300); 12416 12417 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} 12418 ins_encode %{ 12419 int strd = (int)$stride$$constant; 12420 assert(strd != 1 && strd != -1, "sanity"); 12421 int m1 = (strd > 0) ? 1 : -1; 12422 // Convert limit to long (EAX:EDX) 12423 __ cdql(); 12424 // Convert init to long (init:tmp) 12425 __ movl($tmp$$Register, $init$$Register); 12426 __ sarl($tmp$$Register, 31); 12427 // $limit - $init 12428 __ subl($limit$$Register, $init$$Register); 12429 __ sbbl($limit_hi$$Register, $tmp$$Register); 12430 // + ($stride - 1) 12431 if (strd > 0) { 12432 __ addl($limit$$Register, (strd - 1)); 12433 __ adcl($limit_hi$$Register, 0); 12434 __ movl($tmp$$Register, strd); 12435 } else { 12436 __ addl($limit$$Register, (strd + 1)); 12437 __ adcl($limit_hi$$Register, -1); 12438 __ lneg($limit_hi$$Register, $limit$$Register); 12439 __ movl($tmp$$Register, -strd); 12440 } 12441 // signed devision: (EAX:EDX) / pos_stride 12442 __ idivl($tmp$$Register); 12443 if (strd < 0) { 12444 // restore sign 12445 __ negl($tmp$$Register); 12446 } 12447 // (EAX) * stride 12448 __ mull($tmp$$Register); 12449 // + init (ignore upper bits) 12450 __ addl($limit$$Register, $init$$Register); 12451 %} 12452 ins_pipe( pipe_slow ); 12453 %} 12454 12455 // ============================================================================ 12456 // Branch Instructions 12457 // Jump Table 12458 instruct jumpXtnd(eRegI switch_val) %{ 12459 match(Jump switch_val); 12460 ins_cost(350); 12461 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} 12462 ins_encode %{ 12463 // Jump to Address(table_base + switch_reg) 12464 Address index(noreg, $switch_val$$Register, Address::times_1); 12465 __ jump(ArrayAddress($constantaddress, index)); 12466 %} 12467 ins_pipe(pipe_jmp); 12468 %} 12469 12470 // Jump Direct - Label defines a relative address from JMP+1 12471 instruct jmpDir(label labl) %{ 12472 match(Goto); 12473 effect(USE labl); 12474 12475 ins_cost(300); 12476 format %{ "JMP $labl" %} 12477 size(5); 12478 ins_encode %{ 12479 Label* L = $labl$$label; 12480 __ jmp(*L, false); // Always long jump 12481 %} 12482 ins_pipe( pipe_jmp ); 12483 %} 12484 12485 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12486 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ 12487 match(If cop cr); 12488 effect(USE labl); 12489 12490 ins_cost(300); 12491 format %{ "J$cop $labl" %} 12492 size(6); 12493 ins_encode %{ 12494 Label* L = $labl$$label; 12495 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12496 %} 12497 ins_pipe( pipe_jcc ); 12498 %} 12499 12500 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12501 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ 12502 match(CountedLoopEnd cop cr); 12503 effect(USE labl); 12504 12505 ins_cost(300); 12506 format %{ "J$cop $labl\t# Loop end" %} 12507 size(6); 12508 ins_encode %{ 12509 Label* L = $labl$$label; 12510 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12511 %} 12512 ins_pipe( pipe_jcc ); 12513 %} 12514 12515 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12516 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12517 match(CountedLoopEnd cop cmp); 12518 effect(USE labl); 12519 12520 ins_cost(300); 12521 format %{ "J$cop,u $labl\t# Loop end" %} 12522 size(6); 12523 ins_encode %{ 12524 Label* L = $labl$$label; 12525 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12526 %} 12527 ins_pipe( pipe_jcc ); 12528 %} 12529 12530 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12531 match(CountedLoopEnd cop cmp); 12532 effect(USE labl); 12533 12534 ins_cost(200); 12535 format %{ "J$cop,u $labl\t# Loop end" %} 12536 size(6); 12537 ins_encode %{ 12538 Label* L = $labl$$label; 12539 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12540 %} 12541 ins_pipe( pipe_jcc ); 12542 %} 12543 12544 // Jump Direct Conditional - using unsigned comparison 12545 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12546 match(If cop cmp); 12547 effect(USE labl); 12548 12549 ins_cost(300); 12550 format %{ "J$cop,u $labl" %} 12551 size(6); 12552 ins_encode %{ 12553 Label* L = $labl$$label; 12554 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12555 %} 12556 ins_pipe(pipe_jcc); 12557 %} 12558 12559 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12560 match(If cop cmp); 12561 effect(USE labl); 12562 12563 ins_cost(200); 12564 format %{ "J$cop,u $labl" %} 12565 size(6); 12566 ins_encode %{ 12567 Label* L = $labl$$label; 12568 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12569 %} 12570 ins_pipe(pipe_jcc); 12571 %} 12572 12573 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 12574 match(If cop cmp); 12575 effect(USE labl); 12576 12577 ins_cost(200); 12578 format %{ $$template 12579 if ($cop$$cmpcode == Assembler::notEqual) { 12580 $$emit$$"JP,u $labl\n\t" 12581 $$emit$$"J$cop,u $labl" 12582 } else { 12583 $$emit$$"JP,u done\n\t" 12584 $$emit$$"J$cop,u $labl\n\t" 12585 $$emit$$"done:" 12586 } 12587 %} 12588 ins_encode %{ 12589 Label* l = $labl$$label; 12590 if ($cop$$cmpcode == Assembler::notEqual) { 12591 __ jcc(Assembler::parity, *l, false); 12592 __ jcc(Assembler::notEqual, *l, false); 12593 } else if ($cop$$cmpcode == Assembler::equal) { 12594 Label done; 12595 __ jccb(Assembler::parity, done); 12596 __ jcc(Assembler::equal, *l, false); 12597 __ bind(done); 12598 } else { 12599 ShouldNotReachHere(); 12600 } 12601 %} 12602 ins_pipe(pipe_jcc); 12603 %} 12604 12605 // ============================================================================ 12606 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 12607 // array for an instance of the superklass. Set a hidden internal cache on a 12608 // hit (cache is checked with exposed code in gen_subtype_check()). Return 12609 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. 12610 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ 12611 match(Set result (PartialSubtypeCheck sub super)); 12612 effect( KILL rcx, KILL cr ); 12613 12614 ins_cost(1100); // slightly larger than the next version 12615 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12616 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 12617 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12618 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12619 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" 12620 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" 12621 "XOR $result,$result\t\t Hit: EDI zero\n\t" 12622 "miss:\t" %} 12623 12624 opcode(0x1); // Force a XOR of EDI 12625 ins_encode( enc_PartialSubtypeCheck() ); 12626 ins_pipe( pipe_slow ); 12627 %} 12628 12629 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ 12630 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 12631 effect( KILL rcx, KILL result ); 12632 12633 ins_cost(1000); 12634 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12635 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 12636 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12637 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12638 "JNE,s miss\t\t# Missed: flags NZ\n\t" 12639 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" 12640 "miss:\t" %} 12641 12642 opcode(0x0); // No need to XOR EDI 12643 ins_encode( enc_PartialSubtypeCheck() ); 12644 ins_pipe( pipe_slow ); 12645 %} 12646 12647 // ============================================================================ 12648 // Branch Instructions -- short offset versions 12649 // 12650 // These instructions are used to replace jumps of a long offset (the default 12651 // match) with jumps of a shorter offset. These instructions are all tagged 12652 // with the ins_short_branch attribute, which causes the ADLC to suppress the 12653 // match rules in general matching. Instead, the ADLC generates a conversion 12654 // method in the MachNode which can be used to do in-place replacement of the 12655 // long variant with the shorter variant. The compiler will determine if a 12656 // branch can be taken by the is_short_branch_offset() predicate in the machine 12657 // specific code section of the file. 12658 12659 // Jump Direct - Label defines a relative address from JMP+1 12660 instruct jmpDir_short(label labl) %{ 12661 match(Goto); 12662 effect(USE labl); 12663 12664 ins_cost(300); 12665 format %{ "JMP,s $labl" %} 12666 size(2); 12667 ins_encode %{ 12668 Label* L = $labl$$label; 12669 __ jmpb(*L); 12670 %} 12671 ins_pipe( pipe_jmp ); 12672 ins_short_branch(1); 12673 %} 12674 12675 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12676 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12677 match(If cop cr); 12678 effect(USE labl); 12679 12680 ins_cost(300); 12681 format %{ "J$cop,s $labl" %} 12682 size(2); 12683 ins_encode %{ 12684 Label* L = $labl$$label; 12685 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12686 %} 12687 ins_pipe( pipe_jcc ); 12688 ins_short_branch(1); 12689 %} 12690 12691 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12692 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12693 match(CountedLoopEnd cop cr); 12694 effect(USE labl); 12695 12696 ins_cost(300); 12697 format %{ "J$cop,s $labl\t# Loop end" %} 12698 size(2); 12699 ins_encode %{ 12700 Label* L = $labl$$label; 12701 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12702 %} 12703 ins_pipe( pipe_jcc ); 12704 ins_short_branch(1); 12705 %} 12706 12707 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12708 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12709 match(CountedLoopEnd cop cmp); 12710 effect(USE labl); 12711 12712 ins_cost(300); 12713 format %{ "J$cop,us $labl\t# Loop end" %} 12714 size(2); 12715 ins_encode %{ 12716 Label* L = $labl$$label; 12717 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12718 %} 12719 ins_pipe( pipe_jcc ); 12720 ins_short_branch(1); 12721 %} 12722 12723 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12724 match(CountedLoopEnd cop cmp); 12725 effect(USE labl); 12726 12727 ins_cost(300); 12728 format %{ "J$cop,us $labl\t# Loop end" %} 12729 size(2); 12730 ins_encode %{ 12731 Label* L = $labl$$label; 12732 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12733 %} 12734 ins_pipe( pipe_jcc ); 12735 ins_short_branch(1); 12736 %} 12737 12738 // Jump Direct Conditional - using unsigned comparison 12739 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12740 match(If cop cmp); 12741 effect(USE labl); 12742 12743 ins_cost(300); 12744 format %{ "J$cop,us $labl" %} 12745 size(2); 12746 ins_encode %{ 12747 Label* L = $labl$$label; 12748 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12749 %} 12750 ins_pipe( pipe_jcc ); 12751 ins_short_branch(1); 12752 %} 12753 12754 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12755 match(If cop cmp); 12756 effect(USE labl); 12757 12758 ins_cost(300); 12759 format %{ "J$cop,us $labl" %} 12760 size(2); 12761 ins_encode %{ 12762 Label* L = $labl$$label; 12763 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12764 %} 12765 ins_pipe( pipe_jcc ); 12766 ins_short_branch(1); 12767 %} 12768 12769 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 12770 match(If cop cmp); 12771 effect(USE labl); 12772 12773 ins_cost(300); 12774 format %{ $$template 12775 if ($cop$$cmpcode == Assembler::notEqual) { 12776 $$emit$$"JP,u,s $labl\n\t" 12777 $$emit$$"J$cop,u,s $labl" 12778 } else { 12779 $$emit$$"JP,u,s done\n\t" 12780 $$emit$$"J$cop,u,s $labl\n\t" 12781 $$emit$$"done:" 12782 } 12783 %} 12784 size(4); 12785 ins_encode %{ 12786 Label* l = $labl$$label; 12787 if ($cop$$cmpcode == Assembler::notEqual) { 12788 __ jccb(Assembler::parity, *l); 12789 __ jccb(Assembler::notEqual, *l); 12790 } else if ($cop$$cmpcode == Assembler::equal) { 12791 Label done; 12792 __ jccb(Assembler::parity, done); 12793 __ jccb(Assembler::equal, *l); 12794 __ bind(done); 12795 } else { 12796 ShouldNotReachHere(); 12797 } 12798 %} 12799 ins_pipe(pipe_jcc); 12800 ins_short_branch(1); 12801 %} 12802 12803 // ============================================================================ 12804 // Long Compare 12805 // 12806 // Currently we hold longs in 2 registers. Comparing such values efficiently 12807 // is tricky. The flavor of compare used depends on whether we are testing 12808 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 12809 // The GE test is the negated LT test. The LE test can be had by commuting 12810 // the operands (yielding a GE test) and then negating; negate again for the 12811 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 12812 // NE test is negated from that. 12813 12814 // Due to a shortcoming in the ADLC, it mixes up expressions like: 12815 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 12816 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 12817 // are collapsed internally in the ADLC's dfa-gen code. The match for 12818 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 12819 // foo match ends up with the wrong leaf. One fix is to not match both 12820 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 12821 // both forms beat the trinary form of long-compare and both are very useful 12822 // on Intel which has so few registers. 12823 12824 // Manifest a CmpL result in an integer register. Very painful. 12825 // This is the test to avoid. 12826 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ 12827 match(Set dst (CmpL3 src1 src2)); 12828 effect( KILL flags ); 12829 ins_cost(1000); 12830 format %{ "XOR $dst,$dst\n\t" 12831 "CMP $src1.hi,$src2.hi\n\t" 12832 "JLT,s m_one\n\t" 12833 "JGT,s p_one\n\t" 12834 "CMP $src1.lo,$src2.lo\n\t" 12835 "JB,s m_one\n\t" 12836 "JEQ,s done\n" 12837 "p_one:\tINC $dst\n\t" 12838 "JMP,s done\n" 12839 "m_one:\tDEC $dst\n" 12840 "done:" %} 12841 ins_encode %{ 12842 Label p_one, m_one, done; 12843 __ xorptr($dst$$Register, $dst$$Register); 12844 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); 12845 __ jccb(Assembler::less, m_one); 12846 __ jccb(Assembler::greater, p_one); 12847 __ cmpl($src1$$Register, $src2$$Register); 12848 __ jccb(Assembler::below, m_one); 12849 __ jccb(Assembler::equal, done); 12850 __ bind(p_one); 12851 __ incrementl($dst$$Register); 12852 __ jmpb(done); 12853 __ bind(m_one); 12854 __ decrementl($dst$$Register); 12855 __ bind(done); 12856 %} 12857 ins_pipe( pipe_slow ); 12858 %} 12859 12860 //====== 12861 // Manifest a CmpL result in the normal flags. Only good for LT or GE 12862 // compares. Can be used for LE or GT compares by reversing arguments. 12863 // NOT GOOD FOR EQ/NE tests. 12864 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ 12865 match( Set flags (CmpL src zero )); 12866 ins_cost(100); 12867 format %{ "TEST $src.hi,$src.hi" %} 12868 opcode(0x85); 12869 ins_encode( OpcP, RegReg_Hi2( src, src ) ); 12870 ins_pipe( ialu_cr_reg_reg ); 12871 %} 12872 12873 // Manifest a CmpL result in the normal flags. Only good for LT or GE 12874 // compares. Can be used for LE or GT compares by reversing arguments. 12875 // NOT GOOD FOR EQ/NE tests. 12876 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12877 match( Set flags (CmpL src1 src2 )); 12878 effect( TEMP tmp ); 12879 ins_cost(300); 12880 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12881 "MOV $tmp,$src1.hi\n\t" 12882 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} 12883 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); 12884 ins_pipe( ialu_cr_reg_reg ); 12885 %} 12886 12887 // Long compares reg < zero/req OR reg >= zero/req. 12888 // Just a wrapper for a normal branch, plus the predicate test. 12889 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ 12890 match(If cmp flags); 12891 effect(USE labl); 12892 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12893 expand %{ 12894 jmpCon(cmp,flags,labl); // JLT or JGE... 12895 %} 12896 %} 12897 12898 // Compare 2 longs and CMOVE longs. 12899 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ 12900 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12901 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12902 ins_cost(400); 12903 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12904 "CMOV$cmp $dst.hi,$src.hi" %} 12905 opcode(0x0F,0x40); 12906 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12907 ins_pipe( pipe_cmov_reg_long ); 12908 %} 12909 12910 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ 12911 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12912 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12913 ins_cost(500); 12914 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12915 "CMOV$cmp $dst.hi,$src.hi" %} 12916 opcode(0x0F,0x40); 12917 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12918 ins_pipe( pipe_cmov_reg_long ); 12919 %} 12920 12921 // Compare 2 longs and CMOVE ints. 12922 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ 12923 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12924 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12925 ins_cost(200); 12926 format %{ "CMOV$cmp $dst,$src" %} 12927 opcode(0x0F,0x40); 12928 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12929 ins_pipe( pipe_cmov_reg ); 12930 %} 12931 12932 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ 12933 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12934 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12935 ins_cost(250); 12936 format %{ "CMOV$cmp $dst,$src" %} 12937 opcode(0x0F,0x40); 12938 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12939 ins_pipe( pipe_cmov_mem ); 12940 %} 12941 12942 // Compare 2 longs and CMOVE ints. 12943 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ 12944 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12945 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12946 ins_cost(200); 12947 format %{ "CMOV$cmp $dst,$src" %} 12948 opcode(0x0F,0x40); 12949 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12950 ins_pipe( pipe_cmov_reg ); 12951 %} 12952 12953 // Compare 2 longs and CMOVE doubles 12954 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ 12955 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12956 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12957 ins_cost(200); 12958 expand %{ 12959 fcmovDPR_regS(cmp,flags,dst,src); 12960 %} 12961 %} 12962 12963 // Compare 2 longs and CMOVE doubles 12964 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ 12965 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12966 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12967 ins_cost(200); 12968 expand %{ 12969 fcmovD_regS(cmp,flags,dst,src); 12970 %} 12971 %} 12972 12973 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ 12974 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12975 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12976 ins_cost(200); 12977 expand %{ 12978 fcmovFPR_regS(cmp,flags,dst,src); 12979 %} 12980 %} 12981 12982 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ 12983 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12984 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12985 ins_cost(200); 12986 expand %{ 12987 fcmovF_regS(cmp,flags,dst,src); 12988 %} 12989 %} 12990 12991 //====== 12992 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12993 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12994 match( Set flags (CmpL src zero )); 12995 effect(TEMP tmp); 12996 ins_cost(200); 12997 format %{ "MOV $tmp,$src.lo\n\t" 12998 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 12999 ins_encode( long_cmp_flags0( src, tmp ) ); 13000 ins_pipe( ialu_reg_reg_long ); 13001 %} 13002 13003 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 13004 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ 13005 match( Set flags (CmpL src1 src2 )); 13006 ins_cost(200+300); 13007 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 13008 "JNE,s skip\n\t" 13009 "CMP $src1.hi,$src2.hi\n\t" 13010 "skip:\t" %} 13011 ins_encode( long_cmp_flags1( src1, src2 ) ); 13012 ins_pipe( ialu_cr_reg_reg ); 13013 %} 13014 13015 // Long compare reg == zero/reg OR reg != zero/reg 13016 // Just a wrapper for a normal branch, plus the predicate test. 13017 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ 13018 match(If cmp flags); 13019 effect(USE labl); 13020 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13021 expand %{ 13022 jmpCon(cmp,flags,labl); // JEQ or JNE... 13023 %} 13024 %} 13025 13026 // Compare 2 longs and CMOVE longs. 13027 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ 13028 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 13029 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13030 ins_cost(400); 13031 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13032 "CMOV$cmp $dst.hi,$src.hi" %} 13033 opcode(0x0F,0x40); 13034 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 13035 ins_pipe( pipe_cmov_reg_long ); 13036 %} 13037 13038 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ 13039 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 13040 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13041 ins_cost(500); 13042 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13043 "CMOV$cmp $dst.hi,$src.hi" %} 13044 opcode(0x0F,0x40); 13045 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 13046 ins_pipe( pipe_cmov_reg_long ); 13047 %} 13048 13049 // Compare 2 longs and CMOVE ints. 13050 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ 13051 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13052 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 13053 ins_cost(200); 13054 format %{ "CMOV$cmp $dst,$src" %} 13055 opcode(0x0F,0x40); 13056 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13057 ins_pipe( pipe_cmov_reg ); 13058 %} 13059 13060 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ 13061 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13062 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 13063 ins_cost(250); 13064 format %{ "CMOV$cmp $dst,$src" %} 13065 opcode(0x0F,0x40); 13066 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 13067 ins_pipe( pipe_cmov_mem ); 13068 %} 13069 13070 // Compare 2 longs and CMOVE ints. 13071 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ 13072 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 13073 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 13074 ins_cost(200); 13075 format %{ "CMOV$cmp $dst,$src" %} 13076 opcode(0x0F,0x40); 13077 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13078 ins_pipe( pipe_cmov_reg ); 13079 %} 13080 13081 // Compare 2 longs and CMOVE doubles 13082 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ 13083 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13084 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13085 ins_cost(200); 13086 expand %{ 13087 fcmovDPR_regS(cmp,flags,dst,src); 13088 %} 13089 %} 13090 13091 // Compare 2 longs and CMOVE doubles 13092 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ 13093 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13094 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13095 ins_cost(200); 13096 expand %{ 13097 fcmovD_regS(cmp,flags,dst,src); 13098 %} 13099 %} 13100 13101 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ 13102 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13103 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13104 ins_cost(200); 13105 expand %{ 13106 fcmovFPR_regS(cmp,flags,dst,src); 13107 %} 13108 %} 13109 13110 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ 13111 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 13112 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13113 ins_cost(200); 13114 expand %{ 13115 fcmovF_regS(cmp,flags,dst,src); 13116 %} 13117 %} 13118 13119 //====== 13120 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 13121 // Same as cmpL_reg_flags_LEGT except must negate src 13122 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ 13123 match( Set flags (CmpL src zero )); 13124 effect( TEMP tmp ); 13125 ins_cost(300); 13126 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 13127 "CMP $tmp,$src.lo\n\t" 13128 "SBB $tmp,$src.hi\n\t" %} 13129 ins_encode( long_cmp_flags3(src, tmp) ); 13130 ins_pipe( ialu_reg_reg_long ); 13131 %} 13132 13133 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 13134 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 13135 // requires a commuted test to get the same result. 13136 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 13137 match( Set flags (CmpL src1 src2 )); 13138 effect( TEMP tmp ); 13139 ins_cost(300); 13140 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 13141 "MOV $tmp,$src2.hi\n\t" 13142 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} 13143 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); 13144 ins_pipe( ialu_cr_reg_reg ); 13145 %} 13146 13147 // Long compares reg < zero/req OR reg >= zero/req. 13148 // Just a wrapper for a normal branch, plus the predicate test 13149 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ 13150 match(If cmp flags); 13151 effect(USE labl); 13152 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); 13153 ins_cost(300); 13154 expand %{ 13155 jmpCon(cmp,flags,labl); // JGT or JLE... 13156 %} 13157 %} 13158 13159 // Compare 2 longs and CMOVE longs. 13160 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ 13161 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 13162 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13163 ins_cost(400); 13164 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13165 "CMOV$cmp $dst.hi,$src.hi" %} 13166 opcode(0x0F,0x40); 13167 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 13168 ins_pipe( pipe_cmov_reg_long ); 13169 %} 13170 13171 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ 13172 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 13173 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13174 ins_cost(500); 13175 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 13176 "CMOV$cmp $dst.hi,$src.hi+4" %} 13177 opcode(0x0F,0x40); 13178 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 13179 ins_pipe( pipe_cmov_reg_long ); 13180 %} 13181 13182 // Compare 2 longs and CMOVE ints. 13183 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ 13184 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13185 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 13186 ins_cost(200); 13187 format %{ "CMOV$cmp $dst,$src" %} 13188 opcode(0x0F,0x40); 13189 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13190 ins_pipe( pipe_cmov_reg ); 13191 %} 13192 13193 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ 13194 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13195 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 13196 ins_cost(250); 13197 format %{ "CMOV$cmp $dst,$src" %} 13198 opcode(0x0F,0x40); 13199 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 13200 ins_pipe( pipe_cmov_mem ); 13201 %} 13202 13203 // Compare 2 longs and CMOVE ptrs. 13204 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ 13205 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 13206 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 13207 ins_cost(200); 13208 format %{ "CMOV$cmp $dst,$src" %} 13209 opcode(0x0F,0x40); 13210 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 13211 ins_pipe( pipe_cmov_reg ); 13212 %} 13213 13214 // Compare 2 longs and CMOVE doubles 13215 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ 13216 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13217 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13218 ins_cost(200); 13219 expand %{ 13220 fcmovDPR_regS(cmp,flags,dst,src); 13221 %} 13222 %} 13223 13224 // Compare 2 longs and CMOVE doubles 13225 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ 13226 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13227 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 13228 ins_cost(200); 13229 expand %{ 13230 fcmovD_regS(cmp,flags,dst,src); 13231 %} 13232 %} 13233 13234 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ 13235 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13236 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13237 ins_cost(200); 13238 expand %{ 13239 fcmovFPR_regS(cmp,flags,dst,src); 13240 %} 13241 %} 13242 13243 13244 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ 13245 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 13246 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 13247 ins_cost(200); 13248 expand %{ 13249 fcmovF_regS(cmp,flags,dst,src); 13250 %} 13251 %} 13252 13253 13254 // ============================================================================ 13255 // Procedure Call/Return Instructions 13256 // Call Java Static Instruction 13257 // Note: If this code changes, the corresponding ret_addr_offset() and 13258 // compute_padding() functions will have to be adjusted. 13259 instruct CallStaticJavaDirect(method meth) %{ 13260 match(CallStaticJava); 13261 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 13262 effect(USE meth); 13263 13264 ins_cost(300); 13265 format %{ "CALL,static " %} 13266 opcode(0xE8); /* E8 cd */ 13267 ins_encode( pre_call_FPU, 13268 Java_Static_Call( meth ), 13269 call_epilog, 13270 post_call_FPU ); 13271 ins_pipe( pipe_slow ); 13272 ins_alignment(4); 13273 %} 13274 13275 // Call Java Static Instruction (method handle version) 13276 // Note: If this code changes, the corresponding ret_addr_offset() and 13277 // compute_padding() functions will have to be adjusted. 13278 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ 13279 match(CallStaticJava); 13280 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 13281 effect(USE meth); 13282 // EBP is saved by all callees (for interpreter stack correction). 13283 // We use it here for a similar purpose, in {preserve,restore}_SP. 13284 13285 ins_cost(300); 13286 format %{ "CALL,static/MethodHandle " %} 13287 opcode(0xE8); /* E8 cd */ 13288 ins_encode( pre_call_FPU, 13289 preserve_SP, 13290 Java_Static_Call( meth ), 13291 restore_SP, 13292 call_epilog, 13293 post_call_FPU ); 13294 ins_pipe( pipe_slow ); 13295 ins_alignment(4); 13296 %} 13297 13298 // Call Java Dynamic Instruction 13299 // Note: If this code changes, the corresponding ret_addr_offset() and 13300 // compute_padding() functions will have to be adjusted. 13301 instruct CallDynamicJavaDirect(method meth) %{ 13302 match(CallDynamicJava); 13303 effect(USE meth); 13304 13305 ins_cost(300); 13306 format %{ "MOV EAX,(oop)-1\n\t" 13307 "CALL,dynamic" %} 13308 opcode(0xE8); /* E8 cd */ 13309 ins_encode( pre_call_FPU, 13310 Java_Dynamic_Call( meth ), 13311 call_epilog, 13312 post_call_FPU ); 13313 ins_pipe( pipe_slow ); 13314 ins_alignment(4); 13315 %} 13316 13317 // Call Runtime Instruction 13318 instruct CallRuntimeDirect(method meth) %{ 13319 match(CallRuntime ); 13320 effect(USE meth); 13321 13322 ins_cost(300); 13323 format %{ "CALL,runtime " %} 13324 opcode(0xE8); /* E8 cd */ 13325 // Use FFREEs to clear entries in float stack 13326 ins_encode( pre_call_FPU, 13327 FFree_Float_Stack_All, 13328 Java_To_Runtime( meth ), 13329 post_call_FPU ); 13330 ins_pipe( pipe_slow ); 13331 %} 13332 13333 // Call runtime without safepoint 13334 instruct CallLeafDirect(method meth) %{ 13335 match(CallLeaf); 13336 effect(USE meth); 13337 13338 ins_cost(300); 13339 format %{ "CALL_LEAF,runtime " %} 13340 opcode(0xE8); /* E8 cd */ 13341 ins_encode( pre_call_FPU, 13342 FFree_Float_Stack_All, 13343 Java_To_Runtime( meth ), 13344 Verify_FPU_For_Leaf, post_call_FPU ); 13345 ins_pipe( pipe_slow ); 13346 %} 13347 13348 instruct CallLeafNoFPDirect(method meth) %{ 13349 match(CallLeafNoFP); 13350 effect(USE meth); 13351 13352 ins_cost(300); 13353 format %{ "CALL_LEAF_NOFP,runtime " %} 13354 opcode(0xE8); /* E8 cd */ 13355 ins_encode(Java_To_Runtime(meth)); 13356 ins_pipe( pipe_slow ); 13357 %} 13358 13359 13360 // Return Instruction 13361 // Remove the return address & jump to it. 13362 instruct Ret() %{ 13363 match(Return); 13364 format %{ "RET" %} 13365 opcode(0xC3); 13366 ins_encode(OpcP); 13367 ins_pipe( pipe_jmp ); 13368 %} 13369 13370 // Tail Call; Jump from runtime stub to Java code. 13371 // Also known as an 'interprocedural jump'. 13372 // Target of jump will eventually return to caller. 13373 // TailJump below removes the return address. 13374 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ 13375 match(TailCall jump_target method_oop ); 13376 ins_cost(300); 13377 format %{ "JMP $jump_target \t# EBX holds method oop" %} 13378 opcode(0xFF, 0x4); /* Opcode FF /4 */ 13379 ins_encode( OpcP, RegOpc(jump_target) ); 13380 ins_pipe( pipe_jmp ); 13381 %} 13382 13383 13384 // Tail Jump; remove the return address; jump to target. 13385 // TailCall above leaves the return address around. 13386 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ 13387 match( TailJump jump_target ex_oop ); 13388 ins_cost(300); 13389 format %{ "POP EDX\t# pop return address into dummy\n\t" 13390 "JMP $jump_target " %} 13391 opcode(0xFF, 0x4); /* Opcode FF /4 */ 13392 ins_encode( enc_pop_rdx, 13393 OpcP, RegOpc(jump_target) ); 13394 ins_pipe( pipe_jmp ); 13395 %} 13396 13397 // Create exception oop: created by stack-crawling runtime code. 13398 // Created exception is now available to this handler, and is setup 13399 // just prior to jumping to this handler. No code emitted. 13400 instruct CreateException( eAXRegP ex_oop ) 13401 %{ 13402 match(Set ex_oop (CreateEx)); 13403 13404 size(0); 13405 // use the following format syntax 13406 format %{ "# exception oop is in EAX; no code emitted" %} 13407 ins_encode(); 13408 ins_pipe( empty ); 13409 %} 13410 13411 13412 // Rethrow exception: 13413 // The exception oop will come in the first argument position. 13414 // Then JUMP (not call) to the rethrow stub code. 13415 instruct RethrowException() 13416 %{ 13417 match(Rethrow); 13418 13419 // use the following format syntax 13420 format %{ "JMP rethrow_stub" %} 13421 ins_encode(enc_rethrow); 13422 ins_pipe( pipe_jmp ); 13423 %} 13424 13425 // inlined locking and unlocking 13426 13427 13428 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ 13429 match( Set cr (FastLock object box) ); 13430 effect( TEMP tmp, TEMP scr ); 13431 ins_cost(300); 13432 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} 13433 ins_encode( Fast_Lock(object,box,tmp,scr) ); 13434 ins_pipe( pipe_slow ); 13435 %} 13436 13437 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ 13438 match( Set cr (FastUnlock object box) ); 13439 effect( TEMP tmp ); 13440 ins_cost(300); 13441 format %{ "FASTUNLOCK $object, $box, $tmp" %} 13442 ins_encode( Fast_Unlock(object,box,tmp) ); 13443 ins_pipe( pipe_slow ); 13444 %} 13445 13446 13447 13448 // ============================================================================ 13449 // Safepoint Instruction 13450 instruct safePoint_poll(eFlagsReg cr) %{ 13451 match(SafePoint); 13452 effect(KILL cr); 13453 13454 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. 13455 // On SPARC that might be acceptable as we can generate the address with 13456 // just a sethi, saving an or. By polling at offset 0 we can end up 13457 // putting additional pressure on the index-0 in the D$. Because of 13458 // alignment (just like the situation at hand) the lower indices tend 13459 // to see more traffic. It'd be better to change the polling address 13460 // to offset 0 of the last $line in the polling page. 13461 13462 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} 13463 ins_cost(125); 13464 size(6) ; 13465 ins_encode( Safepoint_Poll() ); 13466 ins_pipe( ialu_reg_mem ); 13467 %} 13468 13469 //----------PEEPHOLE RULES----------------------------------------------------- 13470 // These must follow all instruction definitions as they use the names 13471 // defined in the instructions definitions. 13472 // 13473 // peepmatch ( root_instr_name [preceding_instruction]* ); 13474 // 13475 // peepconstraint %{ 13476 // (instruction_number.operand_name relational_op instruction_number.operand_name 13477 // [, ...] ); 13478 // // instruction numbers are zero-based using left to right order in peepmatch 13479 // 13480 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 13481 // // provide an instruction_number.operand_name for each operand that appears 13482 // // in the replacement instruction's match rule 13483 // 13484 // ---------VM FLAGS--------------------------------------------------------- 13485 // 13486 // All peephole optimizations can be turned off using -XX:-OptoPeephole 13487 // 13488 // Each peephole rule is given an identifying number starting with zero and 13489 // increasing by one in the order seen by the parser. An individual peephole 13490 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 13491 // on the command-line. 13492 // 13493 // ---------CURRENT LIMITATIONS---------------------------------------------- 13494 // 13495 // Only match adjacent instructions in same basic block 13496 // Only equality constraints 13497 // Only constraints between operands, not (0.dest_reg == EAX_enc) 13498 // Only one replacement instruction 13499 // 13500 // ---------EXAMPLE---------------------------------------------------------- 13501 // 13502 // // pertinent parts of existing instructions in architecture description 13503 // instruct movI(eRegI dst, eRegI src) %{ 13504 // match(Set dst (CopyI src)); 13505 // %} 13506 // 13507 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 13508 // match(Set dst (AddI dst src)); 13509 // effect(KILL cr); 13510 // %} 13511 // 13512 // // Change (inc mov) to lea 13513 // peephole %{ 13514 // // increment preceeded by register-register move 13515 // peepmatch ( incI_eReg movI ); 13516 // // require that the destination register of the increment 13517 // // match the destination register of the move 13518 // peepconstraint ( 0.dst == 1.dst ); 13519 // // construct a replacement instruction that sets 13520 // // the destination to ( move's source register + one ) 13521 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13522 // %} 13523 // 13524 // Implementation no longer uses movX instructions since 13525 // machine-independent system no longer uses CopyX nodes. 13526 // 13527 // peephole %{ 13528 // peepmatch ( incI_eReg movI ); 13529 // peepconstraint ( 0.dst == 1.dst ); 13530 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13531 // %} 13532 // 13533 // peephole %{ 13534 // peepmatch ( decI_eReg movI ); 13535 // peepconstraint ( 0.dst == 1.dst ); 13536 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13537 // %} 13538 // 13539 // peephole %{ 13540 // peepmatch ( addI_eReg_imm movI ); 13541 // peepconstraint ( 0.dst == 1.dst ); 13542 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13543 // %} 13544 // 13545 // peephole %{ 13546 // peepmatch ( addP_eReg_imm movP ); 13547 // peepconstraint ( 0.dst == 1.dst ); 13548 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 13549 // %} 13550 13551 // // Change load of spilled value to only a spill 13552 // instruct storeI(memory mem, eRegI src) %{ 13553 // match(Set mem (StoreI mem src)); 13554 // %} 13555 // 13556 // instruct loadI(eRegI dst, memory mem) %{ 13557 // match(Set dst (LoadI mem)); 13558 // %} 13559 // 13560 peephole %{ 13561 peepmatch ( loadI storeI ); 13562 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 13563 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 13564 %} 13565 13566 //----------SMARTSPILL RULES--------------------------------------------------- 13567 // These must follow all instruction definitions as they use the names 13568 // defined in the instructions definitions.