1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "runtime/atomic.hpp"
39 #include "runtime/os.hpp"
40 #ifdef TARGET_ARCH_MODEL_x86_32
41 # include "adfiles/ad_x86_32.hpp"
42 #endif
43 #ifdef TARGET_ARCH_MODEL_x86_64
44 # include "adfiles/ad_x86_64.hpp"
45 #endif
46 #ifdef TARGET_ARCH_MODEL_sparc
47 # include "adfiles/ad_sparc.hpp"
48 #endif
49 #ifdef TARGET_ARCH_MODEL_zero
50 # include "adfiles/ad_zero.hpp"
51 #endif
52 #ifdef TARGET_ARCH_MODEL_arm
53 # include "adfiles/ad_arm.hpp"
54 #endif
55 #ifdef TARGET_ARCH_MODEL_ppc
56 # include "adfiles/ad_ppc.hpp"
57 #endif
58
59 OptoReg::Name OptoReg::c_frame_pointer;
60
61
62
63 const int Matcher::base2reg[Type::lastype] = {
64 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
65 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
66 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
67 0, 0/*abio*/,
68 Op_RegP /* Return address */, 0, /* the memories */
69 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
70 0 /*bottom*/
71 };
72
73 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
74 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
75 RegMask Matcher::STACK_ONLY_mask;
76 RegMask Matcher::c_frame_ptr_mask;
77 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
78 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
79
80 //---------------------------Matcher-------------------------------------------
81 Matcher::Matcher( Node_List &proj_list ) :
82 PhaseTransform( Phase::Ins_Select ),
83 #ifdef ASSERT
84 _old2new_map(C->comp_arena()),
85 _new2old_map(C->comp_arena()),
86 #endif
87 _shared_nodes(C->comp_arena()),
88 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
89 _swallowed(swallowed),
90 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
91 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
92 _must_clone(must_clone), _proj_list(proj_list),
93 _register_save_policy(register_save_policy),
94 _c_reg_save_policy(c_reg_save_policy),
95 _register_save_type(register_save_type),
96 _ruleName(ruleName),
97 _allocation_started(false),
98 _states_arena(Chunk::medium_size),
99 _visited(&_states_arena),
100 _shared(&_states_arena),
101 _dontcare(&_states_arena) {
102 C->set_matcher(this);
103
104 idealreg2spillmask [Op_RegI] = NULL;
105 idealreg2spillmask [Op_RegN] = NULL;
106 idealreg2spillmask [Op_RegL] = NULL;
107 idealreg2spillmask [Op_RegF] = NULL;
108 idealreg2spillmask [Op_RegD] = NULL;
109 idealreg2spillmask [Op_RegP] = NULL;
110
111 idealreg2debugmask [Op_RegI] = NULL;
112 idealreg2debugmask [Op_RegN] = NULL;
113 idealreg2debugmask [Op_RegL] = NULL;
114 idealreg2debugmask [Op_RegF] = NULL;
115 idealreg2debugmask [Op_RegD] = NULL;
116 idealreg2debugmask [Op_RegP] = NULL;
117
118 idealreg2mhdebugmask[Op_RegI] = NULL;
119 idealreg2mhdebugmask[Op_RegN] = NULL;
120 idealreg2mhdebugmask[Op_RegL] = NULL;
121 idealreg2mhdebugmask[Op_RegF] = NULL;
122 idealreg2mhdebugmask[Op_RegD] = NULL;
123 idealreg2mhdebugmask[Op_RegP] = NULL;
124
125 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
126 }
127
128 //------------------------------warp_incoming_stk_arg------------------------
129 // This warps a VMReg into an OptoReg::Name
130 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
131 OptoReg::Name warped;
132 if( reg->is_stack() ) { // Stack slot argument?
133 warped = OptoReg::add(_old_SP, reg->reg2stack() );
134 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
135 if( warped >= _in_arg_limit )
136 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
137 if (!RegMask::can_represent(warped)) {
138 // the compiler cannot represent this method's calling sequence
139 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
140 return OptoReg::Bad;
141 }
142 return warped;
143 }
144 return OptoReg::as_OptoReg(reg);
145 }
146
147 //---------------------------compute_old_SP------------------------------------
148 OptoReg::Name Compile::compute_old_SP() {
149 int fixed = fixed_slots();
150 int preserve = in_preserve_stack_slots();
151 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
152 }
153
154
155
156 #ifdef ASSERT
157 void Matcher::verify_new_nodes_only(Node* xroot) {
158 // Make sure that the new graph only references new nodes
159 ResourceMark rm;
160 Unique_Node_List worklist;
161 VectorSet visited(Thread::current()->resource_area());
162 worklist.push(xroot);
163 while (worklist.size() > 0) {
164 Node* n = worklist.pop();
165 visited <<= n->_idx;
166 assert(C->node_arena()->contains(n), "dead node");
167 for (uint j = 0; j < n->req(); j++) {
168 Node* in = n->in(j);
169 if (in != NULL) {
170 assert(C->node_arena()->contains(in), "dead node");
171 if (!visited.test(in->_idx)) {
172 worklist.push(in);
173 }
174 }
175 }
176 }
177 }
178 #endif
179
180
181 //---------------------------match---------------------------------------------
182 void Matcher::match( ) {
183 if( MaxLabelRootDepth < 100 ) { // Too small?
184 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
185 MaxLabelRootDepth = 100;
186 }
187 // One-time initialization of some register masks.
188 init_spill_mask( C->root()->in(1) );
189 _return_addr_mask = return_addr();
190 #ifdef _LP64
191 // Pointers take 2 slots in 64-bit land
192 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
193 #endif
194
195 // Map a Java-signature return type into return register-value
196 // machine registers for 0, 1 and 2 returned values.
197 const TypeTuple *range = C->tf()->range();
198 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
199 // Get ideal-register return type
200 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
201 // Get machine return register
202 uint sop = C->start()->Opcode();
203 OptoRegPair regs = return_value(ireg, false);
204
205 // And mask for same
206 _return_value_mask = RegMask(regs.first());
207 if( OptoReg::is_valid(regs.second()) )
208 _return_value_mask.Insert(regs.second());
209 }
210
211 // ---------------
212 // Frame Layout
213
214 // Need the method signature to determine the incoming argument types,
215 // because the types determine which registers the incoming arguments are
216 // in, and this affects the matched code.
217 const TypeTuple *domain = C->tf()->domain();
218 uint argcnt = domain->cnt() - TypeFunc::Parms;
219 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
220 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
221 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
222 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
223 uint i;
224 for( i = 0; i<argcnt; i++ ) {
225 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
226 }
227
228 // Pass array of ideal registers and length to USER code (from the AD file)
229 // that will convert this to an array of register numbers.
230 const StartNode *start = C->start();
231 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
232 #ifdef ASSERT
233 // Sanity check users' calling convention. Real handy while trying to
234 // get the initial port correct.
235 { for (uint i = 0; i<argcnt; i++) {
236 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
237 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
238 _parm_regs[i].set_bad();
239 continue;
240 }
241 VMReg parm_reg = vm_parm_regs[i].first();
242 assert(parm_reg->is_valid(), "invalid arg?");
243 if (parm_reg->is_reg()) {
244 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
245 assert(can_be_java_arg(opto_parm_reg) ||
246 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
247 opto_parm_reg == inline_cache_reg(),
248 "parameters in register must be preserved by runtime stubs");
249 }
250 for (uint j = 0; j < i; j++) {
251 assert(parm_reg != vm_parm_regs[j].first(),
252 "calling conv. must produce distinct regs");
253 }
254 }
255 }
256 #endif
257
258 // Do some initial frame layout.
259
260 // Compute the old incoming SP (may be called FP) as
261 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
262 _old_SP = C->compute_old_SP();
263 assert( is_even(_old_SP), "must be even" );
264
265 // Compute highest incoming stack argument as
266 // _old_SP + out_preserve_stack_slots + incoming argument size.
267 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
268 assert( is_even(_in_arg_limit), "out_preserve must be even" );
269 for( i = 0; i < argcnt; i++ ) {
270 // Permit args to have no register
271 _calling_convention_mask[i].Clear();
272 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
273 continue;
274 }
275 // calling_convention returns stack arguments as a count of
276 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
277 // the allocators point of view, taking into account all the
278 // preserve area, locks & pad2.
279
280 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
281 if( OptoReg::is_valid(reg1))
282 _calling_convention_mask[i].Insert(reg1);
283
284 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
285 if( OptoReg::is_valid(reg2))
286 _calling_convention_mask[i].Insert(reg2);
287
288 // Saved biased stack-slot register number
289 _parm_regs[i].set_pair(reg2, reg1);
290 }
291
292 // Finally, make sure the incoming arguments take up an even number of
293 // words, in case the arguments or locals need to contain doubleword stack
294 // slots. The rest of the system assumes that stack slot pairs (in
295 // particular, in the spill area) which look aligned will in fact be
296 // aligned relative to the stack pointer in the target machine. Double
297 // stack slots will always be allocated aligned.
298 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
299
300 // Compute highest outgoing stack argument as
301 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
302 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
303 assert( is_even(_out_arg_limit), "out_preserve must be even" );
304
305 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
306 // the compiler cannot represent this method's calling sequence
307 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
308 }
309
310 if (C->failing()) return; // bailed out on incoming arg failure
311
312 // ---------------
313 // Collect roots of matcher trees. Every node for which
314 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
315 // can be a valid interior of some tree.
316 find_shared( C->root() );
317 find_shared( C->top() );
318
319 C->print_method("Before Matching");
320
321 // Create new ideal node ConP #NULL even if it does exist in old space
322 // to avoid false sharing if the corresponding mach node is not used.
323 // The corresponding mach node is only used in rare cases for derived
324 // pointers.
325 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
326
327 // Swap out to old-space; emptying new-space
328 Arena *old = C->node_arena()->move_contents(C->old_arena());
329
330 // Save debug and profile information for nodes in old space:
331 _old_node_note_array = C->node_note_array();
332 if (_old_node_note_array != NULL) {
333 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
334 (C->comp_arena(), _old_node_note_array->length(),
335 0, NULL));
336 }
337
338 // Pre-size the new_node table to avoid the need for range checks.
339 grow_new_node_array(C->unique());
340
341 // Reset node counter so MachNodes start with _idx at 0
342 int nodes = C->unique(); // save value
343 C->set_unique(0);
344
345 // Recursively match trees from old space into new space.
346 // Correct leaves of new-space Nodes; they point to old-space.
347 _visited.Clear(); // Clear visit bits for xform call
348 C->set_cached_top_node(xform( C->top(), nodes ));
349 if (!C->failing()) {
350 Node* xroot = xform( C->root(), 1 );
351 if (xroot == NULL) {
352 Matcher::soft_match_failure(); // recursive matching process failed
353 C->record_method_not_compilable("instruction match failed");
354 } else {
355 // During matching shared constants were attached to C->root()
356 // because xroot wasn't available yet, so transfer the uses to
357 // the xroot.
358 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
359 Node* n = C->root()->fast_out(j);
360 if (C->node_arena()->contains(n)) {
361 assert(n->in(0) == C->root(), "should be control user");
362 n->set_req(0, xroot);
363 --j;
364 --jmax;
365 }
366 }
367
368 // Generate new mach node for ConP #NULL
369 assert(new_ideal_null != NULL, "sanity");
370 _mach_null = match_tree(new_ideal_null);
371 // Don't set control, it will confuse GCM since there are no uses.
372 // The control will be set when this node is used first time
373 // in find_base_for_derived().
374 assert(_mach_null != NULL, "");
375
376 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
377
378 #ifdef ASSERT
379 verify_new_nodes_only(xroot);
380 #endif
381 }
382 }
383 if (C->top() == NULL || C->root() == NULL) {
384 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
385 }
386 if (C->failing()) {
387 // delete old;
388 old->destruct_contents();
389 return;
390 }
391 assert( C->top(), "" );
392 assert( C->root(), "" );
393 validate_null_checks();
394
395 // Now smoke old-space
396 NOT_DEBUG( old->destruct_contents() );
397
398 // ------------------------
399 // Set up save-on-entry registers
400 Fixup_Save_On_Entry( );
401 }
402
403
404 //------------------------------Fixup_Save_On_Entry----------------------------
405 // The stated purpose of this routine is to take care of save-on-entry
406 // registers. However, the overall goal of the Match phase is to convert into
407 // machine-specific instructions which have RegMasks to guide allocation.
408 // So what this procedure really does is put a valid RegMask on each input
409 // to the machine-specific variations of all Return, TailCall and Halt
410 // instructions. It also adds edgs to define the save-on-entry values (and of
411 // course gives them a mask).
412
413 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
414 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
415 // Do all the pre-defined register masks
416 rms[TypeFunc::Control ] = RegMask::Empty;
417 rms[TypeFunc::I_O ] = RegMask::Empty;
418 rms[TypeFunc::Memory ] = RegMask::Empty;
419 rms[TypeFunc::ReturnAdr] = ret_adr;
420 rms[TypeFunc::FramePtr ] = fp;
421 return rms;
422 }
423
424 //---------------------------init_first_stack_mask-----------------------------
425 // Create the initial stack mask used by values spilling to the stack.
426 // Disallow any debug info in outgoing argument areas by setting the
427 // initial mask accordingly.
428 void Matcher::init_first_stack_mask() {
429
430 // Allocate storage for spill masks as masks for the appropriate load type.
431 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * 3*6);
432
433 idealreg2spillmask [Op_RegN] = &rms[0];
434 idealreg2spillmask [Op_RegI] = &rms[1];
435 idealreg2spillmask [Op_RegL] = &rms[2];
436 idealreg2spillmask [Op_RegF] = &rms[3];
437 idealreg2spillmask [Op_RegD] = &rms[4];
438 idealreg2spillmask [Op_RegP] = &rms[5];
439
440 idealreg2debugmask [Op_RegN] = &rms[6];
441 idealreg2debugmask [Op_RegI] = &rms[7];
442 idealreg2debugmask [Op_RegL] = &rms[8];
443 idealreg2debugmask [Op_RegF] = &rms[9];
444 idealreg2debugmask [Op_RegD] = &rms[10];
445 idealreg2debugmask [Op_RegP] = &rms[11];
446
447 idealreg2mhdebugmask[Op_RegN] = &rms[12];
448 idealreg2mhdebugmask[Op_RegI] = &rms[13];
449 idealreg2mhdebugmask[Op_RegL] = &rms[14];
450 idealreg2mhdebugmask[Op_RegF] = &rms[15];
451 idealreg2mhdebugmask[Op_RegD] = &rms[16];
452 idealreg2mhdebugmask[Op_RegP] = &rms[17];
453
454 OptoReg::Name i;
455
456 // At first, start with the empty mask
457 C->FIRST_STACK_mask().Clear();
458
459 // Add in the incoming argument area
460 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
461 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
462 C->FIRST_STACK_mask().Insert(i);
463
464 // Add in all bits past the outgoing argument area
465 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
466 "must be able to represent all call arguments in reg mask");
467 init = _out_arg_limit;
468 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
469 C->FIRST_STACK_mask().Insert(i);
470
471 // Finally, set the "infinite stack" bit.
472 C->FIRST_STACK_mask().set_AllStack();
473
474 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
475 #ifdef _LP64
476 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
477 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
478 #endif
479 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
480 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
481 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
482 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
483 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
484 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
486 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
488 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
489
490 if (UseFPUForSpilling) {
491 // This mask logic assumes that the spill operations are
492 // symmetric and that the registers involved are the same size.
493 // On sparc for instance we may have to use 64 bit moves will
494 // kill 2 registers when used with F0-F31.
495 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
496 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
497 #ifdef _LP64
498 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
499 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
500 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
501 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
502 #else
503 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
504 #ifdef ARM
505 // ARM has support for moving 64bit values between a pair of
506 // integer registers and a double register
507 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
508 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
509 #endif
510 #endif
511 }
512
513 // Make up debug masks. Any spill slot plus callee-save registers.
514 // Caller-save registers are assumed to be trashable by the various
515 // inline-cache fixup routines.
516 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
517 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
518 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
519 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
520 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
521 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
522
523 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
524 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
525 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
526 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
527 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
528 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
529
530 // Prevent stub compilations from attempting to reference
531 // callee-saved registers from debug info
532 bool exclude_soe = !Compile::current()->is_method_compilation();
533
534 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
535 // registers the caller has to save do not work
536 if( _register_save_policy[i] == 'C' ||
537 _register_save_policy[i] == 'A' ||
538 (_register_save_policy[i] == 'E' && exclude_soe) ) {
539 idealreg2debugmask [Op_RegN]->Remove(i);
540 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
541 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
542 idealreg2debugmask [Op_RegF]->Remove(i); // masks
543 idealreg2debugmask [Op_RegD]->Remove(i);
544 idealreg2debugmask [Op_RegP]->Remove(i);
545
546 idealreg2mhdebugmask[Op_RegN]->Remove(i);
547 idealreg2mhdebugmask[Op_RegI]->Remove(i);
548 idealreg2mhdebugmask[Op_RegL]->Remove(i);
549 idealreg2mhdebugmask[Op_RegF]->Remove(i);
550 idealreg2mhdebugmask[Op_RegD]->Remove(i);
551 idealreg2mhdebugmask[Op_RegP]->Remove(i);
552 }
553 }
554
555 // Subtract the register we use to save the SP for MethodHandle
556 // invokes to from the debug mask.
557 const RegMask save_mask = method_handle_invoke_SP_save_mask();
558 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
559 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
560 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
561 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
562 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
563 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
564 }
565
566 //---------------------------is_save_on_entry----------------------------------
567 bool Matcher::is_save_on_entry( int reg ) {
568 return
569 _register_save_policy[reg] == 'E' ||
570 _register_save_policy[reg] == 'A' || // Save-on-entry register?
571 // Also save argument registers in the trampolining stubs
572 (C->save_argument_registers() && is_spillable_arg(reg));
573 }
574
575 //---------------------------Fixup_Save_On_Entry-------------------------------
576 void Matcher::Fixup_Save_On_Entry( ) {
577 init_first_stack_mask();
578
579 Node *root = C->root(); // Short name for root
580 // Count number of save-on-entry registers.
581 uint soe_cnt = number_of_saved_registers();
582 uint i;
583
584 // Find the procedure Start Node
585 StartNode *start = C->start();
586 assert( start, "Expect a start node" );
587
588 // Save argument registers in the trampolining stubs
589 if( C->save_argument_registers() )
590 for( i = 0; i < _last_Mach_Reg; i++ )
591 if( is_spillable_arg(i) )
592 soe_cnt++;
593
594 // Input RegMask array shared by all Returns.
595 // The type for doubles and longs has a count of 2, but
596 // there is only 1 returned value
597 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
598 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
599 // Returns have 0 or 1 returned values depending on call signature.
600 // Return register is specified by return_value in the AD file.
601 if (ret_edge_cnt > TypeFunc::Parms)
602 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
603
604 // Input RegMask array shared by all Rethrows.
605 uint reth_edge_cnt = TypeFunc::Parms+1;
606 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
607 // Rethrow takes exception oop only, but in the argument 0 slot.
608 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
609 #ifdef _LP64
610 // Need two slots for ptrs in 64-bit land
611 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
612 #endif
613
614 // Input RegMask array shared by all TailCalls
615 uint tail_call_edge_cnt = TypeFunc::Parms+2;
616 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
617
618 // Input RegMask array shared by all TailJumps
619 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
620 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
621
622 // TailCalls have 2 returned values (target & moop), whose masks come
623 // from the usual MachNode/MachOper mechanism. Find a sample
624 // TailCall to extract these masks and put the correct masks into
625 // the tail_call_rms array.
626 for( i=1; i < root->req(); i++ ) {
627 MachReturnNode *m = root->in(i)->as_MachReturn();
628 if( m->ideal_Opcode() == Op_TailCall ) {
629 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
630 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
631 break;
632 }
633 }
634
635 // TailJumps have 2 returned values (target & ex_oop), whose masks come
636 // from the usual MachNode/MachOper mechanism. Find a sample
637 // TailJump to extract these masks and put the correct masks into
638 // the tail_jump_rms array.
639 for( i=1; i < root->req(); i++ ) {
640 MachReturnNode *m = root->in(i)->as_MachReturn();
641 if( m->ideal_Opcode() == Op_TailJump ) {
642 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
643 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
644 break;
645 }
646 }
647
648 // Input RegMask array shared by all Halts
649 uint halt_edge_cnt = TypeFunc::Parms;
650 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
651
652 // Capture the return input masks into each exit flavor
653 for( i=1; i < root->req(); i++ ) {
654 MachReturnNode *exit = root->in(i)->as_MachReturn();
655 switch( exit->ideal_Opcode() ) {
656 case Op_Return : exit->_in_rms = ret_rms; break;
657 case Op_Rethrow : exit->_in_rms = reth_rms; break;
658 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
659 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
660 case Op_Halt : exit->_in_rms = halt_rms; break;
661 default : ShouldNotReachHere();
662 }
663 }
664
665 // Next unused projection number from Start.
666 int proj_cnt = C->tf()->domain()->cnt();
667
668 // Do all the save-on-entry registers. Make projections from Start for
669 // them, and give them a use at the exit points. To the allocator, they
670 // look like incoming register arguments.
671 for( i = 0; i < _last_Mach_Reg; i++ ) {
672 if( is_save_on_entry(i) ) {
673
674 // Add the save-on-entry to the mask array
675 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
676 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
677 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
678 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
679 // Halts need the SOE registers, but only in the stack as debug info.
680 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
681 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
682
683 Node *mproj;
684
685 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
686 // into a single RegD.
687 if( (i&1) == 0 &&
688 _register_save_type[i ] == Op_RegF &&
689 _register_save_type[i+1] == Op_RegF &&
690 is_save_on_entry(i+1) ) {
691 // Add other bit for double
692 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
693 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
694 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
695 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
696 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
697 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
698 proj_cnt += 2; // Skip 2 for doubles
699 }
700 else if( (i&1) == 1 && // Else check for high half of double
701 _register_save_type[i-1] == Op_RegF &&
702 _register_save_type[i ] == Op_RegF &&
703 is_save_on_entry(i-1) ) {
704 ret_rms [ ret_edge_cnt] = RegMask::Empty;
705 reth_rms [ reth_edge_cnt] = RegMask::Empty;
706 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
707 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
708 halt_rms [ halt_edge_cnt] = RegMask::Empty;
709 mproj = C->top();
710 }
711 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
712 // into a single RegL.
713 else if( (i&1) == 0 &&
714 _register_save_type[i ] == Op_RegI &&
715 _register_save_type[i+1] == Op_RegI &&
716 is_save_on_entry(i+1) ) {
717 // Add other bit for long
718 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
719 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
720 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
721 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
722 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
723 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
724 proj_cnt += 2; // Skip 2 for longs
725 }
726 else if( (i&1) == 1 && // Else check for high half of long
727 _register_save_type[i-1] == Op_RegI &&
728 _register_save_type[i ] == Op_RegI &&
729 is_save_on_entry(i-1) ) {
730 ret_rms [ ret_edge_cnt] = RegMask::Empty;
731 reth_rms [ reth_edge_cnt] = RegMask::Empty;
732 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
733 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
734 halt_rms [ halt_edge_cnt] = RegMask::Empty;
735 mproj = C->top();
736 } else {
737 // Make a projection for it off the Start
738 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
739 }
740
741 ret_edge_cnt ++;
742 reth_edge_cnt ++;
743 tail_call_edge_cnt ++;
744 tail_jump_edge_cnt ++;
745 halt_edge_cnt ++;
746
747 // Add a use of the SOE register to all exit paths
748 for( uint j=1; j < root->req(); j++ )
749 root->in(j)->add_req(mproj);
750 } // End of if a save-on-entry register
751 } // End of for all machine registers
752 }
753
754 //------------------------------init_spill_mask--------------------------------
755 void Matcher::init_spill_mask( Node *ret ) {
756 if( idealreg2regmask[Op_RegI] ) return; // One time only init
757
758 OptoReg::c_frame_pointer = c_frame_pointer();
759 c_frame_ptr_mask = c_frame_pointer();
760 #ifdef _LP64
761 // pointers are twice as big
762 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
763 #endif
764
765 // Start at OptoReg::stack0()
766 STACK_ONLY_mask.Clear();
767 OptoReg::Name init = OptoReg::stack2reg(0);
768 // STACK_ONLY_mask is all stack bits
769 OptoReg::Name i;
770 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
771 STACK_ONLY_mask.Insert(i);
772 // Also set the "infinite stack" bit.
773 STACK_ONLY_mask.set_AllStack();
774
775 // Copy the register names over into the shared world
776 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
777 // SharedInfo::regName[i] = regName[i];
778 // Handy RegMasks per machine register
779 mreg2regmask[i].Insert(i);
780 }
781
782 // Grab the Frame Pointer
783 Node *fp = ret->in(TypeFunc::FramePtr);
784 Node *mem = ret->in(TypeFunc::Memory);
785 const TypePtr* atp = TypePtr::BOTTOM;
786 // Share frame pointer while making spill ops
787 set_shared(fp);
788
789 // Compute generic short-offset Loads
790 #ifdef _LP64
791 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
792 #endif
793 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
794 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
795 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
796 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
797 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
798 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
799 spillD != NULL && spillP != NULL, "");
800
801 // Get the ADLC notion of the right regmask, for each basic type.
802 #ifdef _LP64
803 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
804 #endif
805 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
806 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
807 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
808 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
809 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
810 }
811
812 #ifdef ASSERT
813 static void match_alias_type(Compile* C, Node* n, Node* m) {
814 if (!VerifyAliases) return; // do not go looking for trouble by default
815 const TypePtr* nat = n->adr_type();
816 const TypePtr* mat = m->adr_type();
817 int nidx = C->get_alias_index(nat);
818 int midx = C->get_alias_index(mat);
819 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
820 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
821 for (uint i = 1; i < n->req(); i++) {
822 Node* n1 = n->in(i);
823 const TypePtr* n1at = n1->adr_type();
824 if (n1at != NULL) {
825 nat = n1at;
826 nidx = C->get_alias_index(n1at);
827 }
828 }
829 }
830 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
831 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
832 switch (n->Opcode()) {
833 case Op_PrefetchRead:
834 case Op_PrefetchWrite:
835 case Op_PrefetchAllocation:
836 nidx = Compile::AliasIdxRaw;
837 nat = TypeRawPtr::BOTTOM;
838 break;
839 }
840 }
841 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
842 switch (n->Opcode()) {
843 case Op_ClearArray:
844 midx = Compile::AliasIdxRaw;
845 mat = TypeRawPtr::BOTTOM;
846 break;
847 }
848 }
849 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
850 switch (n->Opcode()) {
851 case Op_Return:
852 case Op_Rethrow:
853 case Op_Halt:
854 case Op_TailCall:
855 case Op_TailJump:
856 nidx = Compile::AliasIdxBot;
857 nat = TypePtr::BOTTOM;
858 break;
859 }
860 }
861 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
862 switch (n->Opcode()) {
863 case Op_StrComp:
864 case Op_StrEquals:
865 case Op_StrIndexOf:
866 case Op_AryEq:
867 case Op_MemBarVolatile:
868 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
869 nidx = Compile::AliasIdxTop;
870 nat = NULL;
871 break;
872 }
873 }
874 if (nidx != midx) {
875 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
876 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
877 n->dump();
878 m->dump();
879 }
880 assert(C->subsume_loads() && C->must_alias(nat, midx),
881 "must not lose alias info when matching");
882 }
883 }
884 #endif
885
886
887 //------------------------------MStack-----------------------------------------
888 // State and MStack class used in xform() and find_shared() iterative methods.
889 enum Node_State { Pre_Visit, // node has to be pre-visited
890 Visit, // visit node
891 Post_Visit, // post-visit node
892 Alt_Post_Visit // alternative post-visit path
893 };
894
895 class MStack: public Node_Stack {
896 public:
897 MStack(int size) : Node_Stack(size) { }
898
899 void push(Node *n, Node_State ns) {
900 Node_Stack::push(n, (uint)ns);
901 }
902 void push(Node *n, Node_State ns, Node *parent, int indx) {
903 ++_inode_top;
904 if ((_inode_top + 1) >= _inode_max) grow();
905 _inode_top->node = parent;
906 _inode_top->indx = (uint)indx;
907 ++_inode_top;
908 _inode_top->node = n;
909 _inode_top->indx = (uint)ns;
910 }
911 Node *parent() {
912 pop();
913 return node();
914 }
915 Node_State state() const {
916 return (Node_State)index();
917 }
918 void set_state(Node_State ns) {
919 set_index((uint)ns);
920 }
921 };
922
923
924 //------------------------------xform------------------------------------------
925 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
926 // Node in new-space. Given a new-space Node, recursively walk his children.
927 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
928 Node *Matcher::xform( Node *n, int max_stack ) {
929 // Use one stack to keep both: child's node/state and parent's node/index
930 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
931 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
932
933 while (mstack.is_nonempty()) {
934 n = mstack.node(); // Leave node on stack
935 Node_State nstate = mstack.state();
936 if (nstate == Visit) {
937 mstack.set_state(Post_Visit);
938 Node *oldn = n;
939 // Old-space or new-space check
940 if (!C->node_arena()->contains(n)) {
941 // Old space!
942 Node* m;
943 if (has_new_node(n)) { // Not yet Label/Reduced
944 m = new_node(n);
945 } else {
946 if (!is_dontcare(n)) { // Matcher can match this guy
947 // Calls match special. They match alone with no children.
948 // Their children, the incoming arguments, match normally.
949 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
950 if (C->failing()) return NULL;
951 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
952 } else { // Nothing the matcher cares about
953 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
954 // Convert to machine-dependent projection
955 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
956 #ifdef ASSERT
957 _new2old_map.map(m->_idx, n);
958 #endif
959 if (m->in(0) != NULL) // m might be top
960 collect_null_checks(m, n);
961 } else { // Else just a regular 'ol guy
962 m = n->clone(); // So just clone into new-space
963 #ifdef ASSERT
964 _new2old_map.map(m->_idx, n);
965 #endif
966 // Def-Use edges will be added incrementally as Uses
967 // of this node are matched.
968 assert(m->outcnt() == 0, "no Uses of this clone yet");
969 }
970 }
971
972 set_new_node(n, m); // Map old to new
973 if (_old_node_note_array != NULL) {
974 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
975 n->_idx);
976 C->set_node_notes_at(m->_idx, nn);
977 }
978 debug_only(match_alias_type(C, n, m));
979 }
980 n = m; // n is now a new-space node
981 mstack.set_node(n);
982 }
983
984 // New space!
985 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
986
987 int i;
988 // Put precedence edges on stack first (match them last).
989 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
990 Node *m = oldn->in(i);
991 if (m == NULL) break;
992 // set -1 to call add_prec() instead of set_req() during Step1
993 mstack.push(m, Visit, n, -1);
994 }
995
996 // For constant debug info, I'd rather have unmatched constants.
997 int cnt = n->req();
998 JVMState* jvms = n->jvms();
999 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1000
1001 // Now do only debug info. Clone constants rather than matching.
1002 // Constants are represented directly in the debug info without
1003 // the need for executable machine instructions.
1004 // Monitor boxes are also represented directly.
1005 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1006 Node *m = n->in(i); // Get input
1007 int op = m->Opcode();
1008 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1009 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
1010 op == Op_ConF || op == Op_ConD || op == Op_ConL
1011 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1012 ) {
1013 m = m->clone();
1014 #ifdef ASSERT
1015 _new2old_map.map(m->_idx, n);
1016 #endif
1017 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1018 mstack.push(m->in(0), Visit, m, 0);
1019 } else {
1020 mstack.push(m, Visit, n, i);
1021 }
1022 }
1023
1024 // And now walk his children, and convert his inputs to new-space.
1025 for( ; i >= 0; --i ) { // For all normal inputs do
1026 Node *m = n->in(i); // Get input
1027 if(m != NULL)
1028 mstack.push(m, Visit, n, i);
1029 }
1030
1031 }
1032 else if (nstate == Post_Visit) {
1033 // Set xformed input
1034 Node *p = mstack.parent();
1035 if (p != NULL) { // root doesn't have parent
1036 int i = (int)mstack.index();
1037 if (i >= 0)
1038 p->set_req(i, n); // required input
1039 else if (i == -1)
1040 p->add_prec(n); // precedence input
1041 else
1042 ShouldNotReachHere();
1043 }
1044 mstack.pop(); // remove processed node from stack
1045 }
1046 else {
1047 ShouldNotReachHere();
1048 }
1049 } // while (mstack.is_nonempty())
1050 return n; // Return new-space Node
1051 }
1052
1053 //------------------------------warp_outgoing_stk_arg------------------------
1054 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1055 // Convert outgoing argument location to a pre-biased stack offset
1056 if (reg->is_stack()) {
1057 OptoReg::Name warped = reg->reg2stack();
1058 // Adjust the stack slot offset to be the register number used
1059 // by the allocator.
1060 warped = OptoReg::add(begin_out_arg_area, warped);
1061 // Keep track of the largest numbered stack slot used for an arg.
1062 // Largest used slot per call-site indicates the amount of stack
1063 // that is killed by the call.
1064 if( warped >= out_arg_limit_per_call )
1065 out_arg_limit_per_call = OptoReg::add(warped,1);
1066 if (!RegMask::can_represent(warped)) {
1067 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1068 return OptoReg::Bad;
1069 }
1070 return warped;
1071 }
1072 return OptoReg::as_OptoReg(reg);
1073 }
1074
1075
1076 //------------------------------match_sfpt-------------------------------------
1077 // Helper function to match call instructions. Calls match special.
1078 // They match alone with no children. Their children, the incoming
1079 // arguments, match normally.
1080 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1081 MachSafePointNode *msfpt = NULL;
1082 MachCallNode *mcall = NULL;
1083 uint cnt;
1084 // Split out case for SafePoint vs Call
1085 CallNode *call;
1086 const TypeTuple *domain;
1087 ciMethod* method = NULL;
1088 bool is_method_handle_invoke = false; // for special kill effects
1089 if( sfpt->is_Call() ) {
1090 call = sfpt->as_Call();
1091 domain = call->tf()->domain();
1092 cnt = domain->cnt();
1093
1094 // Match just the call, nothing else
1095 MachNode *m = match_tree(call);
1096 if (C->failing()) return NULL;
1097 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1098
1099 // Copy data from the Ideal SafePoint to the machine version
1100 mcall = m->as_MachCall();
1101
1102 mcall->set_tf( call->tf());
1103 mcall->set_entry_point(call->entry_point());
1104 mcall->set_cnt( call->cnt());
1105
1106 if( mcall->is_MachCallJava() ) {
1107 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1108 const CallJavaNode *call_java = call->as_CallJava();
1109 method = call_java->method();
1110 mcall_java->_method = method;
1111 mcall_java->_bci = call_java->_bci;
1112 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1113 is_method_handle_invoke = call_java->is_method_handle_invoke();
1114 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1115 if (is_method_handle_invoke) {
1116 C->set_has_method_handle_invokes(true);
1117 }
1118 if( mcall_java->is_MachCallStaticJava() )
1119 mcall_java->as_MachCallStaticJava()->_name =
1120 call_java->as_CallStaticJava()->_name;
1121 if( mcall_java->is_MachCallDynamicJava() )
1122 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1123 call_java->as_CallDynamicJava()->_vtable_index;
1124 }
1125 else if( mcall->is_MachCallRuntime() ) {
1126 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1127 }
1128 msfpt = mcall;
1129 }
1130 // This is a non-call safepoint
1131 else {
1132 call = NULL;
1133 domain = NULL;
1134 MachNode *mn = match_tree(sfpt);
1135 if (C->failing()) return NULL;
1136 msfpt = mn->as_MachSafePoint();
1137 cnt = TypeFunc::Parms;
1138 }
1139
1140 // Advertise the correct memory effects (for anti-dependence computation).
1141 msfpt->set_adr_type(sfpt->adr_type());
1142
1143 // Allocate a private array of RegMasks. These RegMasks are not shared.
1144 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1145 // Empty them all.
1146 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1147
1148 // Do all the pre-defined non-Empty register masks
1149 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1150 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1151
1152 // Place first outgoing argument can possibly be put.
1153 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1154 assert( is_even(begin_out_arg_area), "" );
1155 // Compute max outgoing register number per call site.
1156 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1157 // Calls to C may hammer extra stack slots above and beyond any arguments.
1158 // These are usually backing store for register arguments for varargs.
1159 if( call != NULL && call->is_CallRuntime() )
1160 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1161
1162
1163 // Do the normal argument list (parameters) register masks
1164 int argcnt = cnt - TypeFunc::Parms;
1165 if( argcnt > 0 ) { // Skip it all if we have no args
1166 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1167 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1168 int i;
1169 for( i = 0; i < argcnt; i++ ) {
1170 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1171 }
1172 // V-call to pick proper calling convention
1173 call->calling_convention( sig_bt, parm_regs, argcnt );
1174
1175 #ifdef ASSERT
1176 // Sanity check users' calling convention. Really handy during
1177 // the initial porting effort. Fairly expensive otherwise.
1178 { for (int i = 0; i<argcnt; i++) {
1179 if( !parm_regs[i].first()->is_valid() &&
1180 !parm_regs[i].second()->is_valid() ) continue;
1181 VMReg reg1 = parm_regs[i].first();
1182 VMReg reg2 = parm_regs[i].second();
1183 for (int j = 0; j < i; j++) {
1184 if( !parm_regs[j].first()->is_valid() &&
1185 !parm_regs[j].second()->is_valid() ) continue;
1186 VMReg reg3 = parm_regs[j].first();
1187 VMReg reg4 = parm_regs[j].second();
1188 if( !reg1->is_valid() ) {
1189 assert( !reg2->is_valid(), "valid halvsies" );
1190 } else if( !reg3->is_valid() ) {
1191 assert( !reg4->is_valid(), "valid halvsies" );
1192 } else {
1193 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1194 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1195 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1196 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1197 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1198 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1199 }
1200 }
1201 }
1202 }
1203 #endif
1204
1205 // Visit each argument. Compute its outgoing register mask.
1206 // Return results now can have 2 bits returned.
1207 // Compute max over all outgoing arguments both per call-site
1208 // and over the entire method.
1209 for( i = 0; i < argcnt; i++ ) {
1210 // Address of incoming argument mask to fill in
1211 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1212 if( !parm_regs[i].first()->is_valid() &&
1213 !parm_regs[i].second()->is_valid() ) {
1214 continue; // Avoid Halves
1215 }
1216 // Grab first register, adjust stack slots and insert in mask.
1217 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1218 if (OptoReg::is_valid(reg1))
1219 rm->Insert( reg1 );
1220 // Grab second register (if any), adjust stack slots and insert in mask.
1221 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1222 if (OptoReg::is_valid(reg2))
1223 rm->Insert( reg2 );
1224 } // End of for all arguments
1225
1226 // Compute number of stack slots needed to restore stack in case of
1227 // Pascal-style argument popping.
1228 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1229 }
1230
1231 if (is_method_handle_invoke) {
1232 // Kill some extra stack space in case method handles want to do
1233 // a little in-place argument insertion.
1234 int regs_per_word = NOT_LP64(1) LP64_ONLY(2); // %%% make a global const!
1235 out_arg_limit_per_call += MethodHandlePushLimit * regs_per_word;
1236 // Do not update mcall->_argsize because (a) the extra space is not
1237 // pushed as arguments and (b) _argsize is dead (not used anywhere).
1238 }
1239
1240 // Compute the max stack slot killed by any call. These will not be
1241 // available for debug info, and will be used to adjust FIRST_STACK_mask
1242 // after all call sites have been visited.
1243 if( _out_arg_limit < out_arg_limit_per_call)
1244 _out_arg_limit = out_arg_limit_per_call;
1245
1246 if (mcall) {
1247 // Kill the outgoing argument area, including any non-argument holes and
1248 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1249 // Since the max-per-method covers the max-per-call-site and debug info
1250 // is excluded on the max-per-method basis, debug info cannot land in
1251 // this killed area.
1252 uint r_cnt = mcall->tf()->range()->cnt();
1253 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1254 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1255 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1256 } else {
1257 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1258 proj->_rout.Insert(OptoReg::Name(i));
1259 }
1260 if( proj->_rout.is_NotEmpty() )
1261 _proj_list.push(proj);
1262 }
1263 // Transfer the safepoint information from the call to the mcall
1264 // Move the JVMState list
1265 msfpt->set_jvms(sfpt->jvms());
1266 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1267 jvms->set_map(sfpt);
1268 }
1269
1270 // Debug inputs begin just after the last incoming parameter
1271 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1272 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1273
1274 // Move the OopMap
1275 msfpt->_oop_map = sfpt->_oop_map;
1276
1277 // Registers killed by the call are set in the local scheduling pass
1278 // of Global Code Motion.
1279 return msfpt;
1280 }
1281
1282 //---------------------------match_tree----------------------------------------
1283 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1284 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1285 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1286 // a Load's result RegMask for memoization in idealreg2regmask[]
1287 MachNode *Matcher::match_tree( const Node *n ) {
1288 assert( n->Opcode() != Op_Phi, "cannot match" );
1289 assert( !n->is_block_start(), "cannot match" );
1290 // Set the mark for all locally allocated State objects.
1291 // When this call returns, the _states_arena arena will be reset
1292 // freeing all State objects.
1293 ResourceMark rm( &_states_arena );
1294
1295 LabelRootDepth = 0;
1296
1297 // StoreNodes require their Memory input to match any LoadNodes
1298 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1299 #ifdef ASSERT
1300 Node* save_mem_node = _mem_node;
1301 _mem_node = n->is_Store() ? (Node*)n : NULL;
1302 #endif
1303 // State object for root node of match tree
1304 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1305 State *s = new (&_states_arena) State;
1306 s->_kids[0] = NULL;
1307 s->_kids[1] = NULL;
1308 s->_leaf = (Node*)n;
1309 // Label the input tree, allocating labels from top-level arena
1310 Label_Root( n, s, n->in(0), mem );
1311 if (C->failing()) return NULL;
1312
1313 // The minimum cost match for the whole tree is found at the root State
1314 uint mincost = max_juint;
1315 uint cost = max_juint;
1316 uint i;
1317 for( i = 0; i < NUM_OPERANDS; i++ ) {
1318 if( s->valid(i) && // valid entry and
1319 s->_cost[i] < cost && // low cost and
1320 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1321 cost = s->_cost[mincost=i];
1322 }
1323 if (mincost == max_juint) {
1324 #ifndef PRODUCT
1325 tty->print("No matching rule for:");
1326 s->dump();
1327 #endif
1328 Matcher::soft_match_failure();
1329 return NULL;
1330 }
1331 // Reduce input tree based upon the state labels to machine Nodes
1332 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1333 #ifdef ASSERT
1334 _old2new_map.map(n->_idx, m);
1335 _new2old_map.map(m->_idx, (Node*)n);
1336 #endif
1337
1338 // Add any Matcher-ignored edges
1339 uint cnt = n->req();
1340 uint start = 1;
1341 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1342 if( n->is_AddP() ) {
1343 assert( mem == (Node*)1, "" );
1344 start = AddPNode::Base+1;
1345 }
1346 for( i = start; i < cnt; i++ ) {
1347 if( !n->match_edge(i) ) {
1348 if( i < m->req() )
1349 m->ins_req( i, n->in(i) );
1350 else
1351 m->add_req( n->in(i) );
1352 }
1353 }
1354
1355 debug_only( _mem_node = save_mem_node; )
1356 return m;
1357 }
1358
1359
1360 //------------------------------match_into_reg---------------------------------
1361 // Choose to either match this Node in a register or part of the current
1362 // match tree. Return true for requiring a register and false for matching
1363 // as part of the current match tree.
1364 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1365
1366 const Type *t = m->bottom_type();
1367
1368 if (t->singleton()) {
1369 // Never force constants into registers. Allow them to match as
1370 // constants or registers. Copies of the same value will share
1371 // the same register. See find_shared_node.
1372 return false;
1373 } else { // Not a constant
1374 // Stop recursion if they have different Controls.
1375 Node* m_control = m->in(0);
1376 // Control of load's memory can post-dominates load's control.
1377 // So use it since load can't float above its memory.
1378 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1379 if (control && m_control && control != m_control && control != mem_control) {
1380
1381 // Actually, we can live with the most conservative control we
1382 // find, if it post-dominates the others. This allows us to
1383 // pick up load/op/store trees where the load can float a little
1384 // above the store.
1385 Node *x = control;
1386 const uint max_scan = 6; // Arbitrary scan cutoff
1387 uint j;
1388 for (j=0; j<max_scan; j++) {
1389 if (x->is_Region()) // Bail out at merge points
1390 return true;
1391 x = x->in(0);
1392 if (x == m_control) // Does 'control' post-dominate
1393 break; // m->in(0)? If so, we can use it
1394 if (x == mem_control) // Does 'control' post-dominate
1395 break; // mem_control? If so, we can use it
1396 }
1397 if (j == max_scan) // No post-domination before scan end?
1398 return true; // Then break the match tree up
1399 }
1400 if (m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) {
1401 // These are commonly used in address expressions and can
1402 // efficiently fold into them on X64 in some cases.
1403 return false;
1404 }
1405 }
1406
1407 // Not forceable cloning. If shared, put it into a register.
1408 return shared;
1409 }
1410
1411
1412 //------------------------------Instruction Selection--------------------------
1413 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1414 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1415 // things the Matcher does not match (e.g., Memory), and things with different
1416 // Controls (hence forced into different blocks). We pass in the Control
1417 // selected for this entire State tree.
1418
1419 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1420 // Store and the Load must have identical Memories (as well as identical
1421 // pointers). Since the Matcher does not have anything for Memory (and
1422 // does not handle DAGs), I have to match the Memory input myself. If the
1423 // Tree root is a Store, I require all Loads to have the identical memory.
1424 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1425 // Since Label_Root is a recursive function, its possible that we might run
1426 // out of stack space. See bugs 6272980 & 6227033 for more info.
1427 LabelRootDepth++;
1428 if (LabelRootDepth > MaxLabelRootDepth) {
1429 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1430 return NULL;
1431 }
1432 uint care = 0; // Edges matcher cares about
1433 uint cnt = n->req();
1434 uint i = 0;
1435
1436 // Examine children for memory state
1437 // Can only subsume a child into your match-tree if that child's memory state
1438 // is not modified along the path to another input.
1439 // It is unsafe even if the other inputs are separate roots.
1440 Node *input_mem = NULL;
1441 for( i = 1; i < cnt; i++ ) {
1442 if( !n->match_edge(i) ) continue;
1443 Node *m = n->in(i); // Get ith input
1444 assert( m, "expect non-null children" );
1445 if( m->is_Load() ) {
1446 if( input_mem == NULL ) {
1447 input_mem = m->in(MemNode::Memory);
1448 } else if( input_mem != m->in(MemNode::Memory) ) {
1449 input_mem = NodeSentinel;
1450 }
1451 }
1452 }
1453
1454 for( i = 1; i < cnt; i++ ){// For my children
1455 if( !n->match_edge(i) ) continue;
1456 Node *m = n->in(i); // Get ith input
1457 // Allocate states out of a private arena
1458 State *s = new (&_states_arena) State;
1459 svec->_kids[care++] = s;
1460 assert( care <= 2, "binary only for now" );
1461
1462 // Recursively label the State tree.
1463 s->_kids[0] = NULL;
1464 s->_kids[1] = NULL;
1465 s->_leaf = m;
1466
1467 // Check for leaves of the State Tree; things that cannot be a part of
1468 // the current tree. If it finds any, that value is matched as a
1469 // register operand. If not, then the normal matching is used.
1470 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1471 //
1472 // Stop recursion if this is LoadNode and the root of this tree is a
1473 // StoreNode and the load & store have different memories.
1474 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1475 // Can NOT include the match of a subtree when its memory state
1476 // is used by any of the other subtrees
1477 (input_mem == NodeSentinel) ) {
1478 #ifndef PRODUCT
1479 // Print when we exclude matching due to different memory states at input-loads
1480 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1481 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1482 tty->print_cr("invalid input_mem");
1483 }
1484 #endif
1485 // Switch to a register-only opcode; this value must be in a register
1486 // and cannot be subsumed as part of a larger instruction.
1487 s->DFA( m->ideal_reg(), m );
1488
1489 } else {
1490 // If match tree has no control and we do, adopt it for entire tree
1491 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1492 control = m->in(0); // Pick up control
1493 // Else match as a normal part of the match tree.
1494 control = Label_Root(m,s,control,mem);
1495 if (C->failing()) return NULL;
1496 }
1497 }
1498
1499
1500 // Call DFA to match this node, and return
1501 svec->DFA( n->Opcode(), n );
1502
1503 #ifdef ASSERT
1504 uint x;
1505 for( x = 0; x < _LAST_MACH_OPER; x++ )
1506 if( svec->valid(x) )
1507 break;
1508
1509 if (x >= _LAST_MACH_OPER) {
1510 n->dump();
1511 svec->dump();
1512 assert( false, "bad AD file" );
1513 }
1514 #endif
1515 return control;
1516 }
1517
1518
1519 // Con nodes reduced using the same rule can share their MachNode
1520 // which reduces the number of copies of a constant in the final
1521 // program. The register allocator is free to split uses later to
1522 // split live ranges.
1523 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1524 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1525
1526 // See if this Con has already been reduced using this rule.
1527 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1528 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1529 if (last != NULL && rule == last->rule()) {
1530 // Don't expect control change for DecodeN
1531 if (leaf->is_DecodeN())
1532 return last;
1533 // Get the new space root.
1534 Node* xroot = new_node(C->root());
1535 if (xroot == NULL) {
1536 // This shouldn't happen give the order of matching.
1537 return NULL;
1538 }
1539
1540 // Shared constants need to have their control be root so they
1541 // can be scheduled properly.
1542 Node* control = last->in(0);
1543 if (control != xroot) {
1544 if (control == NULL || control == C->root()) {
1545 last->set_req(0, xroot);
1546 } else {
1547 assert(false, "unexpected control");
1548 return NULL;
1549 }
1550 }
1551 return last;
1552 }
1553 return NULL;
1554 }
1555
1556
1557 //------------------------------ReduceInst-------------------------------------
1558 // Reduce a State tree (with given Control) into a tree of MachNodes.
1559 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1560 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1561 // Each MachNode has a number of complicated MachOper operands; each
1562 // MachOper also covers a further tree of Ideal Nodes.
1563
1564 // The root of the Ideal match tree is always an instruction, so we enter
1565 // the recursion here. After building the MachNode, we need to recurse
1566 // the tree checking for these cases:
1567 // (1) Child is an instruction -
1568 // Build the instruction (recursively), add it as an edge.
1569 // Build a simple operand (register) to hold the result of the instruction.
1570 // (2) Child is an interior part of an instruction -
1571 // Skip over it (do nothing)
1572 // (3) Child is the start of a operand -
1573 // Build the operand, place it inside the instruction
1574 // Call ReduceOper.
1575 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1576 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1577
1578 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1579 if (shared_node != NULL) {
1580 return shared_node;
1581 }
1582
1583 // Build the object to represent this state & prepare for recursive calls
1584 MachNode *mach = s->MachNodeGenerator( rule, C );
1585 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1586 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1587 Node *leaf = s->_leaf;
1588 // Check for instruction or instruction chain rule
1589 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1590 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1591 "duplicating node that's already been matched");
1592 // Instruction
1593 mach->add_req( leaf->in(0) ); // Set initial control
1594 // Reduce interior of complex instruction
1595 ReduceInst_Interior( s, rule, mem, mach, 1 );
1596 } else {
1597 // Instruction chain rules are data-dependent on their inputs
1598 mach->add_req(0); // Set initial control to none
1599 ReduceInst_Chain_Rule( s, rule, mem, mach );
1600 }
1601
1602 // If a Memory was used, insert a Memory edge
1603 if( mem != (Node*)1 ) {
1604 mach->ins_req(MemNode::Memory,mem);
1605 #ifdef ASSERT
1606 // Verify adr type after matching memory operation
1607 const MachOper* oper = mach->memory_operand();
1608 if (oper != NULL && oper != (MachOper*)-1) {
1609 // It has a unique memory operand. Find corresponding ideal mem node.
1610 Node* m = NULL;
1611 if (leaf->is_Mem()) {
1612 m = leaf;
1613 } else {
1614 m = _mem_node;
1615 assert(m != NULL && m->is_Mem(), "expecting memory node");
1616 }
1617 const Type* mach_at = mach->adr_type();
1618 // DecodeN node consumed by an address may have different type
1619 // then its input. Don't compare types for such case.
1620 if (m->adr_type() != mach_at &&
1621 (m->in(MemNode::Address)->is_DecodeN() ||
1622 m->in(MemNode::Address)->is_AddP() &&
1623 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() ||
1624 m->in(MemNode::Address)->is_AddP() &&
1625 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1626 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) {
1627 mach_at = m->adr_type();
1628 }
1629 if (m->adr_type() != mach_at) {
1630 m->dump();
1631 tty->print_cr("mach:");
1632 mach->dump(1);
1633 }
1634 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1635 }
1636 #endif
1637 }
1638
1639 // If the _leaf is an AddP, insert the base edge
1640 if( leaf->is_AddP() )
1641 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1642
1643 uint num_proj = _proj_list.size();
1644
1645 // Perform any 1-to-many expansions required
1646 MachNode *ex = mach->Expand(s,_proj_list, mem);
1647 if( ex != mach ) {
1648 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1649 if( ex->in(1)->is_Con() )
1650 ex->in(1)->set_req(0, C->root());
1651 // Remove old node from the graph
1652 for( uint i=0; i<mach->req(); i++ ) {
1653 mach->set_req(i,NULL);
1654 }
1655 #ifdef ASSERT
1656 _new2old_map.map(ex->_idx, s->_leaf);
1657 #endif
1658 }
1659
1660 // PhaseChaitin::fixup_spills will sometimes generate spill code
1661 // via the matcher. By the time, nodes have been wired into the CFG,
1662 // and any further nodes generated by expand rules will be left hanging
1663 // in space, and will not get emitted as output code. Catch this.
1664 // Also, catch any new register allocation constraints ("projections")
1665 // generated belatedly during spill code generation.
1666 if (_allocation_started) {
1667 guarantee(ex == mach, "no expand rules during spill generation");
1668 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1669 }
1670
1671 if (leaf->is_Con() || leaf->is_DecodeN()) {
1672 // Record the con for sharing
1673 _shared_nodes.map(leaf->_idx, ex);
1674 }
1675
1676 return ex;
1677 }
1678
1679 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1680 // 'op' is what I am expecting to receive
1681 int op = _leftOp[rule];
1682 // Operand type to catch childs result
1683 // This is what my child will give me.
1684 int opnd_class_instance = s->_rule[op];
1685 // Choose between operand class or not.
1686 // This is what I will receive.
1687 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1688 // New rule for child. Chase operand classes to get the actual rule.
1689 int newrule = s->_rule[catch_op];
1690
1691 if( newrule < NUM_OPERANDS ) {
1692 // Chain from operand or operand class, may be output of shared node
1693 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1694 "Bad AD file: Instruction chain rule must chain from operand");
1695 // Insert operand into array of operands for this instruction
1696 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1697
1698 ReduceOper( s, newrule, mem, mach );
1699 } else {
1700 // Chain from the result of an instruction
1701 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1702 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1703 Node *mem1 = (Node*)1;
1704 debug_only(Node *save_mem_node = _mem_node;)
1705 mach->add_req( ReduceInst(s, newrule, mem1) );
1706 debug_only(_mem_node = save_mem_node;)
1707 }
1708 return;
1709 }
1710
1711
1712 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1713 if( s->_leaf->is_Load() ) {
1714 Node *mem2 = s->_leaf->in(MemNode::Memory);
1715 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1716 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1717 mem = mem2;
1718 }
1719 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1720 if( mach->in(0) == NULL )
1721 mach->set_req(0, s->_leaf->in(0));
1722 }
1723
1724 // Now recursively walk the state tree & add operand list.
1725 for( uint i=0; i<2; i++ ) { // binary tree
1726 State *newstate = s->_kids[i];
1727 if( newstate == NULL ) break; // Might only have 1 child
1728 // 'op' is what I am expecting to receive
1729 int op;
1730 if( i == 0 ) {
1731 op = _leftOp[rule];
1732 } else {
1733 op = _rightOp[rule];
1734 }
1735 // Operand type to catch childs result
1736 // This is what my child will give me.
1737 int opnd_class_instance = newstate->_rule[op];
1738 // Choose between operand class or not.
1739 // This is what I will receive.
1740 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1741 // New rule for child. Chase operand classes to get the actual rule.
1742 int newrule = newstate->_rule[catch_op];
1743
1744 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1745 // Operand/operandClass
1746 // Insert operand into array of operands for this instruction
1747 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1748 ReduceOper( newstate, newrule, mem, mach );
1749
1750 } else { // Child is internal operand or new instruction
1751 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1752 // internal operand --> call ReduceInst_Interior
1753 // Interior of complex instruction. Do nothing but recurse.
1754 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1755 } else {
1756 // instruction --> call build operand( ) to catch result
1757 // --> ReduceInst( newrule )
1758 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1759 Node *mem1 = (Node*)1;
1760 debug_only(Node *save_mem_node = _mem_node;)
1761 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1762 debug_only(_mem_node = save_mem_node;)
1763 }
1764 }
1765 assert( mach->_opnds[num_opnds-1], "" );
1766 }
1767 return num_opnds;
1768 }
1769
1770 // This routine walks the interior of possible complex operands.
1771 // At each point we check our children in the match tree:
1772 // (1) No children -
1773 // We are a leaf; add _leaf field as an input to the MachNode
1774 // (2) Child is an internal operand -
1775 // Skip over it ( do nothing )
1776 // (3) Child is an instruction -
1777 // Call ReduceInst recursively and
1778 // and instruction as an input to the MachNode
1779 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1780 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1781 State *kid = s->_kids[0];
1782 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1783
1784 // Leaf? And not subsumed?
1785 if( kid == NULL && !_swallowed[rule] ) {
1786 mach->add_req( s->_leaf ); // Add leaf pointer
1787 return; // Bail out
1788 }
1789
1790 if( s->_leaf->is_Load() ) {
1791 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1792 mem = s->_leaf->in(MemNode::Memory);
1793 debug_only(_mem_node = s->_leaf;)
1794 }
1795 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1796 if( !mach->in(0) )
1797 mach->set_req(0,s->_leaf->in(0));
1798 else {
1799 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1800 }
1801 }
1802
1803 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1804 int newrule;
1805 if( i == 0 )
1806 newrule = kid->_rule[_leftOp[rule]];
1807 else
1808 newrule = kid->_rule[_rightOp[rule]];
1809
1810 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1811 // Internal operand; recurse but do nothing else
1812 ReduceOper( kid, newrule, mem, mach );
1813
1814 } else { // Child is a new instruction
1815 // Reduce the instruction, and add a direct pointer from this
1816 // machine instruction to the newly reduced one.
1817 Node *mem1 = (Node*)1;
1818 debug_only(Node *save_mem_node = _mem_node;)
1819 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1820 debug_only(_mem_node = save_mem_node;)
1821 }
1822 }
1823 }
1824
1825
1826 // -------------------------------------------------------------------------
1827 // Java-Java calling convention
1828 // (what you use when Java calls Java)
1829
1830 //------------------------------find_receiver----------------------------------
1831 // For a given signature, return the OptoReg for parameter 0.
1832 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1833 VMRegPair regs;
1834 BasicType sig_bt = T_OBJECT;
1835 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1836 // Return argument 0 register. In the LP64 build pointers
1837 // take 2 registers, but the VM wants only the 'main' name.
1838 return OptoReg::as_OptoReg(regs.first());
1839 }
1840
1841 // A method-klass-holder may be passed in the inline_cache_reg
1842 // and then expanded into the inline_cache_reg and a method_oop register
1843 // defined in ad_<arch>.cpp
1844
1845
1846 //------------------------------find_shared------------------------------------
1847 // Set bits if Node is shared or otherwise a root
1848 void Matcher::find_shared( Node *n ) {
1849 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1850 MStack mstack(C->unique() * 2);
1851 // Mark nodes as address_visited if they are inputs to an address expression
1852 VectorSet address_visited(Thread::current()->resource_area());
1853 mstack.push(n, Visit); // Don't need to pre-visit root node
1854 while (mstack.is_nonempty()) {
1855 n = mstack.node(); // Leave node on stack
1856 Node_State nstate = mstack.state();
1857 uint nop = n->Opcode();
1858 if (nstate == Pre_Visit) {
1859 if (address_visited.test(n->_idx)) { // Visited in address already?
1860 // Flag as visited and shared now.
1861 set_visited(n);
1862 }
1863 if (is_visited(n)) { // Visited already?
1864 // Node is shared and has no reason to clone. Flag it as shared.
1865 // This causes it to match into a register for the sharing.
1866 set_shared(n); // Flag as shared and
1867 mstack.pop(); // remove node from stack
1868 continue;
1869 }
1870 nstate = Visit; // Not already visited; so visit now
1871 }
1872 if (nstate == Visit) {
1873 mstack.set_state(Post_Visit);
1874 set_visited(n); // Flag as visited now
1875 bool mem_op = false;
1876
1877 switch( nop ) { // Handle some opcodes special
1878 case Op_Phi: // Treat Phis as shared roots
1879 case Op_Parm:
1880 case Op_Proj: // All handled specially during matching
1881 case Op_SafePointScalarObject:
1882 set_shared(n);
1883 set_dontcare(n);
1884 break;
1885 case Op_If:
1886 case Op_CountedLoopEnd:
1887 mstack.set_state(Alt_Post_Visit); // Alternative way
1888 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1889 // with matching cmp/branch in 1 instruction. The Matcher needs the
1890 // Bool and CmpX side-by-side, because it can only get at constants
1891 // that are at the leaves of Match trees, and the Bool's condition acts
1892 // as a constant here.
1893 mstack.push(n->in(1), Visit); // Clone the Bool
1894 mstack.push(n->in(0), Pre_Visit); // Visit control input
1895 continue; // while (mstack.is_nonempty())
1896 case Op_ConvI2D: // These forms efficiently match with a prior
1897 case Op_ConvI2F: // Load but not a following Store
1898 if( n->in(1)->is_Load() && // Prior load
1899 n->outcnt() == 1 && // Not already shared
1900 n->unique_out()->is_Store() ) // Following store
1901 set_shared(n); // Force it to be a root
1902 break;
1903 case Op_ReverseBytesI:
1904 case Op_ReverseBytesL:
1905 if( n->in(1)->is_Load() && // Prior load
1906 n->outcnt() == 1 ) // Not already shared
1907 set_shared(n); // Force it to be a root
1908 break;
1909 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1910 case Op_IfFalse:
1911 case Op_IfTrue:
1912 case Op_MachProj:
1913 case Op_MergeMem:
1914 case Op_Catch:
1915 case Op_CatchProj:
1916 case Op_CProj:
1917 case Op_JumpProj:
1918 case Op_JProj:
1919 case Op_NeverBranch:
1920 set_dontcare(n);
1921 break;
1922 case Op_Jump:
1923 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
1924 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1925 continue; // while (mstack.is_nonempty())
1926 case Op_StrComp:
1927 case Op_StrEquals:
1928 case Op_StrIndexOf:
1929 case Op_AryEq:
1930 set_shared(n); // Force result into register (it will be anyways)
1931 break;
1932 case Op_ConP: { // Convert pointers above the centerline to NUL
1933 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1934 const TypePtr* tp = tn->type()->is_ptr();
1935 if (tp->_ptr == TypePtr::AnyNull) {
1936 tn->set_type(TypePtr::NULL_PTR);
1937 }
1938 break;
1939 }
1940 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1941 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1942 const TypePtr* tp = tn->type()->make_ptr();
1943 if (tp && tp->_ptr == TypePtr::AnyNull) {
1944 tn->set_type(TypeNarrowOop::NULL_PTR);
1945 }
1946 break;
1947 }
1948 case Op_Binary: // These are introduced in the Post_Visit state.
1949 ShouldNotReachHere();
1950 break;
1951 case Op_ClearArray:
1952 case Op_SafePoint:
1953 mem_op = true;
1954 break;
1955 default:
1956 if( n->is_Store() ) {
1957 // Do match stores, despite no ideal reg
1958 mem_op = true;
1959 break;
1960 }
1961 if( n->is_Mem() ) { // Loads and LoadStores
1962 mem_op = true;
1963 // Loads must be root of match tree due to prior load conflict
1964 if( C->subsume_loads() == false )
1965 set_shared(n);
1966 }
1967 // Fall into default case
1968 if( !n->ideal_reg() )
1969 set_dontcare(n); // Unmatchable Nodes
1970 } // end_switch
1971
1972 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1973 Node *m = n->in(i); // Get ith input
1974 if (m == NULL) continue; // Ignore NULLs
1975 uint mop = m->Opcode();
1976
1977 // Must clone all producers of flags, or we will not match correctly.
1978 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1979 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1980 // are also there, so we may match a float-branch to int-flags and
1981 // expect the allocator to haul the flags from the int-side to the
1982 // fp-side. No can do.
1983 if( _must_clone[mop] ) {
1984 mstack.push(m, Visit);
1985 continue; // for(int i = ...)
1986 }
1987
1988 if( mop == Op_AddP && m->in(AddPNode::Base)->Opcode() == Op_DecodeN ) {
1989 // Bases used in addresses must be shared but since
1990 // they are shared through a DecodeN they may appear
1991 // to have a single use so force sharing here.
1992 set_shared(m->in(AddPNode::Base)->in(1));
1993 }
1994
1995 // Clone addressing expressions as they are "free" in memory access instructions
1996 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1997 // Some inputs for address expression are not put on stack
1998 // to avoid marking them as shared and forcing them into register
1999 // if they are used only in address expressions.
2000 // But they should be marked as shared if there are other uses
2001 // besides address expressions.
2002
2003 Node *off = m->in(AddPNode::Offset);
2004 if( off->is_Con() &&
2005 // When there are other uses besides address expressions
2006 // put it on stack and mark as shared.
2007 !is_visited(m) ) {
2008 address_visited.test_set(m->_idx); // Flag as address_visited
2009 Node *adr = m->in(AddPNode::Address);
2010
2011 // Intel, ARM and friends can handle 2 adds in addressing mode
2012 if( clone_shift_expressions && adr->is_AddP() &&
2013 // AtomicAdd is not an addressing expression.
2014 // Cheap to find it by looking for screwy base.
2015 !adr->in(AddPNode::Base)->is_top() &&
2016 // Are there other uses besides address expressions?
2017 !is_visited(adr) ) {
2018 address_visited.set(adr->_idx); // Flag as address_visited
2019 Node *shift = adr->in(AddPNode::Offset);
2020 // Check for shift by small constant as well
2021 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2022 shift->in(2)->get_int() <= 3 &&
2023 // Are there other uses besides address expressions?
2024 !is_visited(shift) ) {
2025 address_visited.set(shift->_idx); // Flag as address_visited
2026 mstack.push(shift->in(2), Visit);
2027 Node *conv = shift->in(1);
2028 #ifdef _LP64
2029 // Allow Matcher to match the rule which bypass
2030 // ConvI2L operation for an array index on LP64
2031 // if the index value is positive.
2032 if( conv->Opcode() == Op_ConvI2L &&
2033 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2034 // Are there other uses besides address expressions?
2035 !is_visited(conv) ) {
2036 address_visited.set(conv->_idx); // Flag as address_visited
2037 mstack.push(conv->in(1), Pre_Visit);
2038 } else
2039 #endif
2040 mstack.push(conv, Pre_Visit);
2041 } else {
2042 mstack.push(shift, Pre_Visit);
2043 }
2044 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2045 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2046 } else { // Sparc, Alpha, PPC and friends
2047 mstack.push(adr, Pre_Visit);
2048 }
2049
2050 // Clone X+offset as it also folds into most addressing expressions
2051 mstack.push(off, Visit);
2052 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2053 continue; // for(int i = ...)
2054 } // if( off->is_Con() )
2055 } // if( mem_op &&
2056 mstack.push(m, Pre_Visit);
2057 } // for(int i = ...)
2058 }
2059 else if (nstate == Alt_Post_Visit) {
2060 mstack.pop(); // Remove node from stack
2061 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2062 // shared and all users of the Bool need to move the Cmp in parallel.
2063 // This leaves both the Bool and the If pointing at the Cmp. To
2064 // prevent the Matcher from trying to Match the Cmp along both paths
2065 // BoolNode::match_edge always returns a zero.
2066
2067 // We reorder the Op_If in a pre-order manner, so we can visit without
2068 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2069 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2070 }
2071 else if (nstate == Post_Visit) {
2072 mstack.pop(); // Remove node from stack
2073
2074 // Now hack a few special opcodes
2075 switch( n->Opcode() ) { // Handle some opcodes special
2076 case Op_StorePConditional:
2077 case Op_StoreIConditional:
2078 case Op_StoreLConditional:
2079 case Op_CompareAndSwapI:
2080 case Op_CompareAndSwapL:
2081 case Op_CompareAndSwapP:
2082 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2083 Node *newval = n->in(MemNode::ValueIn );
2084 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
2085 Node *pair = new (C, 3) BinaryNode( oldval, newval );
2086 n->set_req(MemNode::ValueIn,pair);
2087 n->del_req(LoadStoreNode::ExpectedIn);
2088 break;
2089 }
2090 case Op_CMoveD: // Convert trinary to binary-tree
2091 case Op_CMoveF:
2092 case Op_CMoveI:
2093 case Op_CMoveL:
2094 case Op_CMoveN:
2095 case Op_CMoveP: {
2096 // Restructure into a binary tree for Matching. It's possible that
2097 // we could move this code up next to the graph reshaping for IfNodes
2098 // or vice-versa, but I do not want to debug this for Ladybird.
2099 // 10/2/2000 CNC.
2100 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
2101 n->set_req(1,pair1);
2102 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2103 n->set_req(2,pair2);
2104 n->del_req(3);
2105 break;
2106 }
2107 case Op_LoopLimit: {
2108 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(2));
2109 n->set_req(1,pair1);
2110 n->set_req(2,n->in(3));
2111 n->del_req(3);
2112 break;
2113 }
2114 case Op_StrEquals: {
2115 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2116 n->set_req(2,pair1);
2117 n->set_req(3,n->in(4));
2118 n->del_req(4);
2119 break;
2120 }
2121 case Op_StrComp:
2122 case Op_StrIndexOf: {
2123 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2124 n->set_req(2,pair1);
2125 Node *pair2 = new (C, 3) BinaryNode(n->in(4),n->in(5));
2126 n->set_req(3,pair2);
2127 n->del_req(5);
2128 n->del_req(4);
2129 break;
2130 }
2131 default:
2132 break;
2133 }
2134 }
2135 else {
2136 ShouldNotReachHere();
2137 }
2138 } // end of while (mstack.is_nonempty())
2139 }
2140
2141 #ifdef ASSERT
2142 // machine-independent root to machine-dependent root
2143 void Matcher::dump_old2new_map() {
2144 _old2new_map.dump();
2145 }
2146 #endif
2147
2148 //---------------------------collect_null_checks-------------------------------
2149 // Find null checks in the ideal graph; write a machine-specific node for
2150 // it. Used by later implicit-null-check handling. Actually collects
2151 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2152 // value being tested.
2153 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2154 Node *iff = proj->in(0);
2155 if( iff->Opcode() == Op_If ) {
2156 // During matching If's have Bool & Cmp side-by-side
2157 BoolNode *b = iff->in(1)->as_Bool();
2158 Node *cmp = iff->in(2);
2159 int opc = cmp->Opcode();
2160 if (opc != Op_CmpP && opc != Op_CmpN) return;
2161
2162 const Type* ct = cmp->in(2)->bottom_type();
2163 if (ct == TypePtr::NULL_PTR ||
2164 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2165
2166 bool push_it = false;
2167 if( proj->Opcode() == Op_IfTrue ) {
2168 extern int all_null_checks_found;
2169 all_null_checks_found++;
2170 if( b->_test._test == BoolTest::ne ) {
2171 push_it = true;
2172 }
2173 } else {
2174 assert( proj->Opcode() == Op_IfFalse, "" );
2175 if( b->_test._test == BoolTest::eq ) {
2176 push_it = true;
2177 }
2178 }
2179 if( push_it ) {
2180 _null_check_tests.push(proj);
2181 Node* val = cmp->in(1);
2182 #ifdef _LP64
2183 if (val->bottom_type()->isa_narrowoop() &&
2184 !Matcher::narrow_oop_use_complex_address()) {
2185 //
2186 // Look for DecodeN node which should be pinned to orig_proj.
2187 // On platforms (Sparc) which can not handle 2 adds
2188 // in addressing mode we have to keep a DecodeN node and
2189 // use it to do implicit NULL check in address.
2190 //
2191 // DecodeN node was pinned to non-null path (orig_proj) during
2192 // CastPP transformation in final_graph_reshaping_impl().
2193 //
2194 uint cnt = orig_proj->outcnt();
2195 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2196 Node* d = orig_proj->raw_out(i);
2197 if (d->is_DecodeN() && d->in(1) == val) {
2198 val = d;
2199 val->set_req(0, NULL); // Unpin now.
2200 // Mark this as special case to distinguish from
2201 // a regular case: CmpP(DecodeN, NULL).
2202 val = (Node*)(((intptr_t)val) | 1);
2203 break;
2204 }
2205 }
2206 }
2207 #endif
2208 _null_check_tests.push(val);
2209 }
2210 }
2211 }
2212 }
2213
2214 //---------------------------validate_null_checks------------------------------
2215 // Its possible that the value being NULL checked is not the root of a match
2216 // tree. If so, I cannot use the value in an implicit null check.
2217 void Matcher::validate_null_checks( ) {
2218 uint cnt = _null_check_tests.size();
2219 for( uint i=0; i < cnt; i+=2 ) {
2220 Node *test = _null_check_tests[i];
2221 Node *val = _null_check_tests[i+1];
2222 bool is_decoden = ((intptr_t)val) & 1;
2223 val = (Node*)(((intptr_t)val) & ~1);
2224 if (has_new_node(val)) {
2225 Node* new_val = new_node(val);
2226 if (is_decoden) {
2227 assert(val->is_DecodeN() && val->in(0) == NULL, "sanity");
2228 // Note: new_val may have a control edge if
2229 // the original ideal node DecodeN was matched before
2230 // it was unpinned in Matcher::collect_null_checks().
2231 // Unpin the mach node and mark it.
2232 new_val->set_req(0, NULL);
2233 new_val = (Node*)(((intptr_t)new_val) | 1);
2234 }
2235 // Is a match-tree root, so replace with the matched value
2236 _null_check_tests.map(i+1, new_val);
2237 } else {
2238 // Yank from candidate list
2239 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2240 _null_check_tests.map(i,_null_check_tests[--cnt]);
2241 _null_check_tests.pop();
2242 _null_check_tests.pop();
2243 i-=2;
2244 }
2245 }
2246 }
2247
2248 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2249 // atomic instruction acting as a store_load barrier without any
2250 // intervening volatile load, and thus we don't need a barrier here.
2251 // We retain the Node to act as a compiler ordering barrier.
2252 bool Matcher::post_store_load_barrier(const Node *vmb) {
2253 Compile *C = Compile::current();
2254 assert( vmb->is_MemBar(), "" );
2255 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2256 const MemBarNode *mem = (const MemBarNode*)vmb;
2257
2258 // Get the Proj node, ctrl, that can be used to iterate forward
2259 Node *ctrl = NULL;
2260 DUIterator_Fast imax, i = mem->fast_outs(imax);
2261 while( true ) {
2262 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2263 assert( ctrl->is_Proj(), "only projections here" );
2264 ProjNode *proj = (ProjNode*)ctrl;
2265 if( proj->_con == TypeFunc::Control &&
2266 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2267 break;
2268 i++;
2269 }
2270
2271 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2272 Node *x = ctrl->fast_out(j);
2273 int xop = x->Opcode();
2274
2275 // We don't need current barrier if we see another or a lock
2276 // before seeing volatile load.
2277 //
2278 // Op_Fastunlock previously appeared in the Op_* list below.
2279 // With the advent of 1-0 lock operations we're no longer guaranteed
2280 // that a monitor exit operation contains a serializing instruction.
2281
2282 if (xop == Op_MemBarVolatile ||
2283 xop == Op_FastLock ||
2284 xop == Op_CompareAndSwapL ||
2285 xop == Op_CompareAndSwapP ||
2286 xop == Op_CompareAndSwapN ||
2287 xop == Op_CompareAndSwapI)
2288 return true;
2289
2290 if (x->is_MemBar()) {
2291 // We must retain this membar if there is an upcoming volatile
2292 // load, which will be preceded by acquire membar.
2293 if (xop == Op_MemBarAcquire)
2294 return false;
2295 // For other kinds of barriers, check by pretending we
2296 // are them, and seeing if we can be removed.
2297 else
2298 return post_store_load_barrier((const MemBarNode*)x);
2299 }
2300
2301 // Delicate code to detect case of an upcoming fastlock block
2302 if( x->is_If() && x->req() > 1 &&
2303 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2304 Node *iff = x;
2305 Node *bol = iff->in(1);
2306 // The iff might be some random subclass of If or bol might be Con-Top
2307 if (!bol->is_Bool()) return false;
2308 assert( bol->req() > 1, "" );
2309 return (bol->in(1)->Opcode() == Op_FastUnlock);
2310 }
2311 // probably not necessary to check for these
2312 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2313 return false;
2314 }
2315 return false;
2316 }
2317
2318 //=============================================================================
2319 //---------------------------State---------------------------------------------
2320 State::State(void) {
2321 #ifdef ASSERT
2322 _id = 0;
2323 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2324 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2325 //memset(_cost, -1, sizeof(_cost));
2326 //memset(_rule, -1, sizeof(_rule));
2327 #endif
2328 memset(_valid, 0, sizeof(_valid));
2329 }
2330
2331 #ifdef ASSERT
2332 State::~State() {
2333 _id = 99;
2334 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2335 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2336 memset(_cost, -3, sizeof(_cost));
2337 memset(_rule, -3, sizeof(_rule));
2338 }
2339 #endif
2340
2341 #ifndef PRODUCT
2342 //---------------------------dump----------------------------------------------
2343 void State::dump() {
2344 tty->print("\n");
2345 dump(0);
2346 }
2347
2348 void State::dump(int depth) {
2349 for( int j = 0; j < depth; j++ )
2350 tty->print(" ");
2351 tty->print("--N: ");
2352 _leaf->dump();
2353 uint i;
2354 for( i = 0; i < _LAST_MACH_OPER; i++ )
2355 // Check for valid entry
2356 if( valid(i) ) {
2357 for( int j = 0; j < depth; j++ )
2358 tty->print(" ");
2359 assert(_cost[i] != max_juint, "cost must be a valid value");
2360 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2361 tty->print_cr("%s %d %s",
2362 ruleName[i], _cost[i], ruleName[_rule[i]] );
2363 }
2364 tty->print_cr("");
2365
2366 for( i=0; i<2; i++ )
2367 if( _kids[i] )
2368 _kids[i]->dump(depth+1);
2369 }
2370 #endif