1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "assembler_x86.inline.hpp" 27 #include "gc_interface/collectedHeap.inline.hpp" 28 #include "interpreter/interpreter.hpp" 29 #include "memory/cardTableModRefBS.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "prims/methodHandles.hpp" 32 #include "runtime/biasedLocking.hpp" 33 #include "runtime/interfaceSupport.hpp" 34 #include "runtime/objectMonitor.hpp" 35 #include "runtime/os.hpp" 36 #include "runtime/sharedRuntime.hpp" 37 #include "runtime/stubRoutines.hpp" 38 #ifndef SERIALGC 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" 41 #include "gc_implementation/g1/heapRegion.hpp" 42 #endif 43 44 // Implementation of AddressLiteral 45 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 47 _is_lval = false; 48 _target = target; 49 switch (rtype) { 50 case relocInfo::oop_type: 51 // Oops are a special case. Normally they would be their own section 52 // but in cases like icBuffer they are literals in the code stream that 53 // we don't have a section for. We use none so that we get a literal address 54 // which is always patchable. 55 break; 56 case relocInfo::external_word_type: 57 _rspec = external_word_Relocation::spec(target); 58 break; 59 case relocInfo::internal_word_type: 60 _rspec = internal_word_Relocation::spec(target); 61 break; 62 case relocInfo::opt_virtual_call_type: 63 _rspec = opt_virtual_call_Relocation::spec(); 64 break; 65 case relocInfo::static_call_type: 66 _rspec = static_call_Relocation::spec(); 67 break; 68 case relocInfo::runtime_call_type: 69 _rspec = runtime_call_Relocation::spec(); 70 break; 71 case relocInfo::poll_type: 72 case relocInfo::poll_return_type: 73 _rspec = Relocation::spec_simple(rtype); 74 break; 75 case relocInfo::none: 76 break; 77 default: 78 ShouldNotReachHere(); 79 break; 80 } 81 } 82 83 // Implementation of Address 84 85 #ifdef _LP64 86 87 Address Address::make_array(ArrayAddress adr) { 88 // Not implementable on 64bit machines 89 // Should have been handled higher up the call chain. 90 ShouldNotReachHere(); 91 return Address(); 92 } 93 94 // exceedingly dangerous constructor 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 96 _base = noreg; 97 _index = noreg; 98 _scale = no_scale; 99 _disp = disp; 100 switch (rtype) { 101 case relocInfo::external_word_type: 102 _rspec = external_word_Relocation::spec(loc); 103 break; 104 case relocInfo::internal_word_type: 105 _rspec = internal_word_Relocation::spec(loc); 106 break; 107 case relocInfo::runtime_call_type: 108 // HMM 109 _rspec = runtime_call_Relocation::spec(); 110 break; 111 case relocInfo::poll_type: 112 case relocInfo::poll_return_type: 113 _rspec = Relocation::spec_simple(rtype); 114 break; 115 case relocInfo::none: 116 break; 117 default: 118 ShouldNotReachHere(); 119 } 120 } 121 #else // LP64 122 123 Address Address::make_array(ArrayAddress adr) { 124 AddressLiteral base = adr.base(); 125 Address index = adr.index(); 126 assert(index._disp == 0, "must not have disp"); // maybe it can? 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 128 array._rspec = base._rspec; 129 return array; 130 } 131 132 // exceedingly dangerous constructor 133 Address::Address(address loc, RelocationHolder spec) { 134 _base = noreg; 135 _index = noreg; 136 _scale = no_scale; 137 _disp = (intptr_t) loc; 138 _rspec = spec; 139 } 140 141 #endif // _LP64 142 143 144 145 // Convert the raw encoding form into the form expected by the constructor for 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert 147 // that to noreg for the Address constructor. 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { 149 RelocationHolder rspec; 150 if (disp_is_oop) { 151 rspec = Relocation::spec_simple(relocInfo::oop_type); 152 } 153 bool valid_index = index != rsp->encoding(); 154 if (valid_index) { 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 156 madr._rspec = rspec; 157 return madr; 158 } else { 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 160 madr._rspec = rspec; 161 return madr; 162 } 163 } 164 165 // Implementation of Assembler 166 167 int AbstractAssembler::code_fill_byte() { 168 return (u_char)'\xF4'; // hlt 169 } 170 171 // make this go away someday 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 173 if (rtype == relocInfo::none) 174 emit_long(data); 175 else emit_data(data, Relocation::spec_simple(rtype), format); 176 } 177 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 179 assert(imm_operand == 0, "default format must be immediate in this file"); 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); 181 if (rspec.type() != relocInfo::none) { 182 #ifdef ASSERT 183 check_relocation(rspec, format); 184 #endif 185 // Do not use AbstractAssembler::relocate, which is not intended for 186 // embedded words. Instead, relocate to the enclosing instruction. 187 188 // hack. call32 is too wide for mask so use disp32 189 if (format == call32_operand) 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); 191 else 192 code_section()->relocate(inst_mark(), rspec, format); 193 } 194 emit_long(data); 195 } 196 197 static int encode(Register r) { 198 int enc = r->encoding(); 199 if (enc >= 8) { 200 enc -= 8; 201 } 202 return enc; 203 } 204 205 static int encode(XMMRegister r) { 206 int enc = r->encoding(); 207 if (enc >= 8) { 208 enc -= 8; 209 } 210 return enc; 211 } 212 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 214 assert(dst->has_byte_register(), "must have byte register"); 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); 216 assert(isByte(imm8), "not a byte"); 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); 218 emit_byte(op1); 219 emit_byte(op2 | encode(dst)); 220 emit_byte(imm8); 221 } 222 223 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 228 if (is8bit(imm32)) { 229 emit_byte(op1 | 0x02); // set sign bit 230 emit_byte(op2 | encode(dst)); 231 emit_byte(imm32 & 0xFF); 232 } else { 233 emit_byte(op1); 234 emit_byte(op2 | encode(dst)); 235 emit_long(imm32); 236 } 237 } 238 239 // immediate-to-memory forms 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 243 if (is8bit(imm32)) { 244 emit_byte(op1 | 0x02); // set sign bit 245 emit_operand(rm, adr, 1); 246 emit_byte(imm32 & 0xFF); 247 } else { 248 emit_byte(op1); 249 emit_operand(rm, adr, 4); 250 emit_long(imm32); 251 } 252 } 253 254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { 255 LP64_ONLY(ShouldNotReachHere()); 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); 257 assert((op1 & 0x01) == 1, "should be 32bit operation"); 258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 259 InstructionMark im(this); 260 emit_byte(op1); 261 emit_byte(op2 | encode(dst)); 262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); 263 } 264 265 266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 267 assert(isByte(op1) && isByte(op2), "wrong opcode"); 268 emit_byte(op1); 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); 270 } 271 272 273 void Assembler::emit_operand(Register reg, Register base, Register index, 274 Address::ScaleFactor scale, int disp, 275 RelocationHolder const& rspec, 276 int rip_relative_correction) { 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 278 279 // Encode the registers as needed in the fields they are used in 280 281 int regenc = encode(reg) << 3; 282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 283 int baseenc = base->is_valid() ? encode(base) : 0; 284 285 if (base->is_valid()) { 286 if (index->is_valid()) { 287 assert(scale != Address::no_scale, "inconsistent address"); 288 // [base + index*scale + disp] 289 if (disp == 0 && rtype == relocInfo::none && 290 base != rbp LP64_ONLY(&& base != r13)) { 291 // [base + index*scale] 292 // [00 reg 100][ss index base] 293 assert(index != rsp, "illegal addressing mode"); 294 emit_byte(0x04 | regenc); 295 emit_byte(scale << 6 | indexenc | baseenc); 296 } else if (is8bit(disp) && rtype == relocInfo::none) { 297 // [base + index*scale + imm8] 298 // [01 reg 100][ss index base] imm8 299 assert(index != rsp, "illegal addressing mode"); 300 emit_byte(0x44 | regenc); 301 emit_byte(scale << 6 | indexenc | baseenc); 302 emit_byte(disp & 0xFF); 303 } else { 304 // [base + index*scale + disp32] 305 // [10 reg 100][ss index base] disp32 306 assert(index != rsp, "illegal addressing mode"); 307 emit_byte(0x84 | regenc); 308 emit_byte(scale << 6 | indexenc | baseenc); 309 emit_data(disp, rspec, disp32_operand); 310 } 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { 312 // [rsp + disp] 313 if (disp == 0 && rtype == relocInfo::none) { 314 // [rsp] 315 // [00 reg 100][00 100 100] 316 emit_byte(0x04 | regenc); 317 emit_byte(0x24); 318 } else if (is8bit(disp) && rtype == relocInfo::none) { 319 // [rsp + imm8] 320 // [01 reg 100][00 100 100] disp8 321 emit_byte(0x44 | regenc); 322 emit_byte(0x24); 323 emit_byte(disp & 0xFF); 324 } else { 325 // [rsp + imm32] 326 // [10 reg 100][00 100 100] disp32 327 emit_byte(0x84 | regenc); 328 emit_byte(0x24); 329 emit_data(disp, rspec, disp32_operand); 330 } 331 } else { 332 // [base + disp] 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 334 if (disp == 0 && rtype == relocInfo::none && 335 base != rbp LP64_ONLY(&& base != r13)) { 336 // [base] 337 // [00 reg base] 338 emit_byte(0x00 | regenc | baseenc); 339 } else if (is8bit(disp) && rtype == relocInfo::none) { 340 // [base + disp8] 341 // [01 reg base] disp8 342 emit_byte(0x40 | regenc | baseenc); 343 emit_byte(disp & 0xFF); 344 } else { 345 // [base + disp32] 346 // [10 reg base] disp32 347 emit_byte(0x80 | regenc | baseenc); 348 emit_data(disp, rspec, disp32_operand); 349 } 350 } 351 } else { 352 if (index->is_valid()) { 353 assert(scale != Address::no_scale, "inconsistent address"); 354 // [index*scale + disp] 355 // [00 reg 100][ss index 101] disp32 356 assert(index != rsp, "illegal addressing mode"); 357 emit_byte(0x04 | regenc); 358 emit_byte(scale << 6 | indexenc | 0x05); 359 emit_data(disp, rspec, disp32_operand); 360 } else if (rtype != relocInfo::none ) { 361 // [disp] (64bit) RIP-RELATIVE (32bit) abs 362 // [00 000 101] disp32 363 364 emit_byte(0x05 | regenc); 365 // Note that the RIP-rel. correction applies to the generated 366 // disp field, but _not_ to the target address in the rspec. 367 368 // disp was created by converting the target address minus the pc 369 // at the start of the instruction. That needs more correction here. 370 // intptr_t disp = target - next_ip; 371 assert(inst_mark() != NULL, "must be inside InstructionMark"); 372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 373 int64_t adjusted = disp; 374 // Do rip-rel adjustment for 64bit 375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 376 assert(is_simm32(adjusted), 377 "must be 32bit offset (RIP relative address)"); 378 emit_data((int32_t) adjusted, rspec, disp32_operand); 379 380 } else { 381 // 32bit never did this, did everything as the rip-rel/disp code above 382 // [disp] ABSOLUTE 383 // [00 reg 100][00 100 101] disp32 384 emit_byte(0x04 | regenc); 385 emit_byte(0x25); 386 emit_data(disp, rspec, disp32_operand); 387 } 388 } 389 } 390 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 392 Address::ScaleFactor scale, int disp, 393 RelocationHolder const& rspec) { 394 emit_operand((Register)reg, base, index, scale, disp, rspec); 395 } 396 397 // Secret local extension to Assembler::WhichOperand: 398 #define end_pc_operand (_WhichOperand_limit) 399 400 address Assembler::locate_operand(address inst, WhichOperand which) { 401 // Decode the given instruction, and return the address of 402 // an embedded 32-bit operand word. 403 404 // If "which" is disp32_operand, selects the displacement portion 405 // of an effective address specifier. 406 // If "which" is imm64_operand, selects the trailing immediate constant. 407 // If "which" is call32_operand, selects the displacement of a call or jump. 408 // Caller is responsible for ensuring that there is such an operand, 409 // and that it is 32/64 bits wide. 410 411 // If "which" is end_pc_operand, find the end of the instruction. 412 413 address ip = inst; 414 bool is_64bit = false; 415 416 debug_only(bool has_disp32 = false); 417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 418 419 again_after_prefix: 420 switch (0xFF & *ip++) { 421 422 // These convenience macros generate groups of "case" labels for the switch. 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 426 #define REP16(x) REP8((x)+0): \ 427 case REP8((x)+8) 428 429 case CS_segment: 430 case SS_segment: 431 case DS_segment: 432 case ES_segment: 433 case FS_segment: 434 case GS_segment: 435 // Seems dubious 436 LP64_ONLY(assert(false, "shouldn't have that prefix")); 437 assert(ip == inst+1, "only one prefix allowed"); 438 goto again_after_prefix; 439 440 case 0x67: 441 case REX: 442 case REX_B: 443 case REX_X: 444 case REX_XB: 445 case REX_R: 446 case REX_RB: 447 case REX_RX: 448 case REX_RXB: 449 NOT_LP64(assert(false, "64bit prefixes")); 450 goto again_after_prefix; 451 452 case REX_W: 453 case REX_WB: 454 case REX_WX: 455 case REX_WXB: 456 case REX_WR: 457 case REX_WRB: 458 case REX_WRX: 459 case REX_WRXB: 460 NOT_LP64(assert(false, "64bit prefixes")); 461 is_64bit = true; 462 goto again_after_prefix; 463 464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 465 case 0x88: // movb a, r 466 case 0x89: // movl a, r 467 case 0x8A: // movb r, a 468 case 0x8B: // movl r, a 469 case 0x8F: // popl a 470 debug_only(has_disp32 = true); 471 break; 472 473 case 0x68: // pushq #32 474 if (which == end_pc_operand) { 475 return ip + 4; 476 } 477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 478 return ip; // not produced by emit_operand 479 480 case 0x66: // movw ... (size prefix) 481 again_after_size_prefix2: 482 switch (0xFF & *ip++) { 483 case REX: 484 case REX_B: 485 case REX_X: 486 case REX_XB: 487 case REX_R: 488 case REX_RB: 489 case REX_RX: 490 case REX_RXB: 491 case REX_W: 492 case REX_WB: 493 case REX_WX: 494 case REX_WXB: 495 case REX_WR: 496 case REX_WRB: 497 case REX_WRX: 498 case REX_WRXB: 499 NOT_LP64(assert(false, "64bit prefix found")); 500 goto again_after_size_prefix2; 501 case 0x8B: // movw r, a 502 case 0x89: // movw a, r 503 debug_only(has_disp32 = true); 504 break; 505 case 0xC7: // movw a, #16 506 debug_only(has_disp32 = true); 507 tail_size = 2; // the imm16 508 break; 509 case 0x0F: // several SSE/SSE2 variants 510 ip--; // reparse the 0x0F 511 goto again_after_prefix; 512 default: 513 ShouldNotReachHere(); 514 } 515 break; 516 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) 518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 519 // these asserts are somewhat nonsensical 520 #ifndef _LP64 521 assert(which == imm_operand || which == disp32_operand, ""); 522 #else 523 assert((which == call32_operand || which == imm_operand) && is_64bit || 524 which == narrow_oop_operand && !is_64bit, ""); 525 #endif // _LP64 526 return ip; 527 528 case 0x69: // imul r, a, #32 529 case 0xC7: // movl a, #32(oop?) 530 tail_size = 4; 531 debug_only(has_disp32 = true); // has both kinds of operands! 532 break; 533 534 case 0x0F: // movx..., etc. 535 switch (0xFF & *ip++) { 536 case 0x3A: // pcmpestri 537 tail_size = 1; 538 case 0x38: // ptest, pmovzxbw 539 ip++; // skip opcode 540 debug_only(has_disp32 = true); // has both kinds of operands! 541 break; 542 543 case 0x70: // pshufd r, r/a, #8 544 debug_only(has_disp32 = true); // has both kinds of operands! 545 case 0x73: // psrldq r, #8 546 tail_size = 1; 547 break; 548 549 case 0x12: // movlps 550 case 0x28: // movaps 551 case 0x2E: // ucomiss 552 case 0x2F: // comiss 553 case 0x54: // andps 554 case 0x55: // andnps 555 case 0x56: // orps 556 case 0x57: // xorps 557 case 0x6E: // movd 558 case 0x7E: // movd 559 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 560 debug_only(has_disp32 = true); 561 break; 562 563 case 0xAD: // shrd r, a, %cl 564 case 0xAF: // imul r, a 565 case 0xBE: // movsbl r, a (movsxb) 566 case 0xBF: // movswl r, a (movsxw) 567 case 0xB6: // movzbl r, a (movzxb) 568 case 0xB7: // movzwl r, a (movzxw) 569 case REP16(0x40): // cmovl cc, r, a 570 case 0xB0: // cmpxchgb 571 case 0xB1: // cmpxchg 572 case 0xC1: // xaddl 573 case 0xC7: // cmpxchg8 574 case REP16(0x90): // setcc a 575 debug_only(has_disp32 = true); 576 // fall out of the switch to decode the address 577 break; 578 579 case 0xC4: // pinsrw r, a, #8 580 debug_only(has_disp32 = true); 581 case 0xC5: // pextrw r, r, #8 582 tail_size = 1; // the imm8 583 break; 584 585 case 0xAC: // shrd r, a, #8 586 debug_only(has_disp32 = true); 587 tail_size = 1; // the imm8 588 break; 589 590 case REP16(0x80): // jcc rdisp32 591 if (which == end_pc_operand) return ip + 4; 592 assert(which == call32_operand, "jcc has no disp32 or imm"); 593 return ip; 594 default: 595 ShouldNotReachHere(); 596 } 597 break; 598 599 case 0x81: // addl a, #32; addl r, #32 600 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 601 // on 32bit in the case of cmpl, the imm might be an oop 602 tail_size = 4; 603 debug_only(has_disp32 = true); // has both kinds of operands! 604 break; 605 606 case 0x83: // addl a, #8; addl r, #8 607 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 608 debug_only(has_disp32 = true); // has both kinds of operands! 609 tail_size = 1; 610 break; 611 612 case 0x9B: 613 switch (0xFF & *ip++) { 614 case 0xD9: // fnstcw a 615 debug_only(has_disp32 = true); 616 break; 617 default: 618 ShouldNotReachHere(); 619 } 620 break; 621 622 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 623 case REP4(0x10): // adc... 624 case REP4(0x20): // and... 625 case REP4(0x30): // xor... 626 case REP4(0x08): // or... 627 case REP4(0x18): // sbb... 628 case REP4(0x28): // sub... 629 case 0xF7: // mull a 630 case 0x8D: // lea r, a 631 case 0x87: // xchg r, a 632 case REP4(0x38): // cmp... 633 case 0x85: // test r, a 634 debug_only(has_disp32 = true); // has both kinds of operands! 635 break; 636 637 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 638 case 0xC6: // movb a, #8 639 case 0x80: // cmpb a, #8 640 case 0x6B: // imul r, a, #8 641 debug_only(has_disp32 = true); // has both kinds of operands! 642 tail_size = 1; // the imm8 643 break; 644 645 case 0xC4: // VEX_3bytes 646 case 0xC5: // VEX_2bytes 647 assert((UseAVX > 0), "shouldn't have VEX prefix"); 648 assert(ip == inst+1, "no prefixes allowed"); 649 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 650 // but they have prefix 0x0F and processed when 0x0F processed above. 651 // 652 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 653 // instructions (these instructions are not supported in 64-bit mode). 654 // To distinguish them bits [7:6] are set in the VEX second byte since 655 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 656 // those VEX bits REX and vvvv bits are inverted. 657 // 658 // Fortunately C2 doesn't generate these instructions so we don't need 659 // to check for them in product version. 660 661 // Check second byte 662 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 663 664 // First byte 665 if ((0xFF & *inst) == VEX_3bytes) { 666 ip++; // third byte 667 is_64bit = ((VEX_W & *ip) == VEX_W); 668 } 669 ip++; // opcode 670 // To find the end of instruction (which == end_pc_operand). 671 switch (0xFF & *ip) { 672 case 0x61: // pcmpestri r, r/a, #8 673 case 0x70: // pshufd r, r/a, #8 674 case 0x73: // psrldq r, #8 675 tail_size = 1; // the imm8 676 break; 677 default: 678 break; 679 } 680 ip++; // skip opcode 681 debug_only(has_disp32 = true); // has both kinds of operands! 682 break; 683 684 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 685 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 686 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 687 case 0xDD: // fld_d a; fst_d a; fstp_d a 688 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 689 case 0xDF: // fild_d a; fistp_d a 690 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 691 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 692 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 693 debug_only(has_disp32 = true); 694 break; 695 696 case 0xE8: // call rdisp32 697 case 0xE9: // jmp rdisp32 698 if (which == end_pc_operand) return ip + 4; 699 assert(which == call32_operand, "call has no disp32 or imm"); 700 return ip; 701 702 case 0xF0: // Lock 703 assert(os::is_MP(), "only on MP"); 704 goto again_after_prefix; 705 706 case 0xF3: // For SSE 707 case 0xF2: // For SSE2 708 switch (0xFF & *ip++) { 709 case REX: 710 case REX_B: 711 case REX_X: 712 case REX_XB: 713 case REX_R: 714 case REX_RB: 715 case REX_RX: 716 case REX_RXB: 717 case REX_W: 718 case REX_WB: 719 case REX_WX: 720 case REX_WXB: 721 case REX_WR: 722 case REX_WRB: 723 case REX_WRX: 724 case REX_WRXB: 725 NOT_LP64(assert(false, "found 64bit prefix")); 726 ip++; 727 default: 728 ip++; 729 } 730 debug_only(has_disp32 = true); // has both kinds of operands! 731 break; 732 733 default: 734 ShouldNotReachHere(); 735 736 #undef REP8 737 #undef REP16 738 } 739 740 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 741 #ifdef _LP64 742 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 743 #else 744 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 745 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 746 #endif // LP64 747 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 748 749 // parse the output of emit_operand 750 int op2 = 0xFF & *ip++; 751 int base = op2 & 0x07; 752 int op3 = -1; 753 const int b100 = 4; 754 const int b101 = 5; 755 if (base == b100 && (op2 >> 6) != 3) { 756 op3 = 0xFF & *ip++; 757 base = op3 & 0x07; // refetch the base 758 } 759 // now ip points at the disp (if any) 760 761 switch (op2 >> 6) { 762 case 0: 763 // [00 reg 100][ss index base] 764 // [00 reg 100][00 100 esp] 765 // [00 reg base] 766 // [00 reg 100][ss index 101][disp32] 767 // [00 reg 101] [disp32] 768 769 if (base == b101) { 770 if (which == disp32_operand) 771 return ip; // caller wants the disp32 772 ip += 4; // skip the disp32 773 } 774 break; 775 776 case 1: 777 // [01 reg 100][ss index base][disp8] 778 // [01 reg 100][00 100 esp][disp8] 779 // [01 reg base] [disp8] 780 ip += 1; // skip the disp8 781 break; 782 783 case 2: 784 // [10 reg 100][ss index base][disp32] 785 // [10 reg 100][00 100 esp][disp32] 786 // [10 reg base] [disp32] 787 if (which == disp32_operand) 788 return ip; // caller wants the disp32 789 ip += 4; // skip the disp32 790 break; 791 792 case 3: 793 // [11 reg base] (not a memory addressing mode) 794 break; 795 } 796 797 if (which == end_pc_operand) { 798 return ip + tail_size; 799 } 800 801 #ifdef _LP64 802 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 803 #else 804 assert(which == imm_operand, "instruction has only an imm field"); 805 #endif // LP64 806 return ip; 807 } 808 809 address Assembler::locate_next_instruction(address inst) { 810 // Secretly share code with locate_operand: 811 return locate_operand(inst, end_pc_operand); 812 } 813 814 815 #ifdef ASSERT 816 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 817 address inst = inst_mark(); 818 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 819 address opnd; 820 821 Relocation* r = rspec.reloc(); 822 if (r->type() == relocInfo::none) { 823 return; 824 } else if (r->is_call() || format == call32_operand) { 825 // assert(format == imm32_operand, "cannot specify a nonzero format"); 826 opnd = locate_operand(inst, call32_operand); 827 } else if (r->is_data()) { 828 assert(format == imm_operand || format == disp32_operand 829 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 830 opnd = locate_operand(inst, (WhichOperand)format); 831 } else { 832 assert(format == imm_operand, "cannot specify a format"); 833 return; 834 } 835 assert(opnd == pc(), "must put operand where relocs can find it"); 836 } 837 #endif // ASSERT 838 839 void Assembler::emit_operand32(Register reg, Address adr) { 840 assert(reg->encoding() < 8, "no extended registers"); 841 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 842 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 843 adr._rspec); 844 } 845 846 void Assembler::emit_operand(Register reg, Address adr, 847 int rip_relative_correction) { 848 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 849 adr._rspec, 850 rip_relative_correction); 851 } 852 853 void Assembler::emit_operand(XMMRegister reg, Address adr) { 854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 855 adr._rspec); 856 } 857 858 // MMX operations 859 void Assembler::emit_operand(MMXRegister reg, Address adr) { 860 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 861 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 862 } 863 864 // work around gcc (3.2.1-7a) bug 865 void Assembler::emit_operand(Address adr, MMXRegister reg) { 866 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 867 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 868 } 869 870 871 void Assembler::emit_farith(int b1, int b2, int i) { 872 assert(isByte(b1) && isByte(b2), "wrong opcode"); 873 assert(0 <= i && i < 8, "illegal stack offset"); 874 emit_byte(b1); 875 emit_byte(b2 + i); 876 } 877 878 879 // Now the Assembler instructions (identical for 32/64 bits) 880 881 void Assembler::adcl(Address dst, int32_t imm32) { 882 InstructionMark im(this); 883 prefix(dst); 884 emit_arith_operand(0x81, rdx, dst, imm32); 885 } 886 887 void Assembler::adcl(Address dst, Register src) { 888 InstructionMark im(this); 889 prefix(dst, src); 890 emit_byte(0x11); 891 emit_operand(src, dst); 892 } 893 894 void Assembler::adcl(Register dst, int32_t imm32) { 895 prefix(dst); 896 emit_arith(0x81, 0xD0, dst, imm32); 897 } 898 899 void Assembler::adcl(Register dst, Address src) { 900 InstructionMark im(this); 901 prefix(src, dst); 902 emit_byte(0x13); 903 emit_operand(dst, src); 904 } 905 906 void Assembler::adcl(Register dst, Register src) { 907 (void) prefix_and_encode(dst->encoding(), src->encoding()); 908 emit_arith(0x13, 0xC0, dst, src); 909 } 910 911 void Assembler::addl(Address dst, int32_t imm32) { 912 InstructionMark im(this); 913 prefix(dst); 914 emit_arith_operand(0x81, rax, dst, imm32); 915 } 916 917 void Assembler::addl(Address dst, Register src) { 918 InstructionMark im(this); 919 prefix(dst, src); 920 emit_byte(0x01); 921 emit_operand(src, dst); 922 } 923 924 void Assembler::addl(Register dst, int32_t imm32) { 925 prefix(dst); 926 emit_arith(0x81, 0xC0, dst, imm32); 927 } 928 929 void Assembler::addl(Register dst, Address src) { 930 InstructionMark im(this); 931 prefix(src, dst); 932 emit_byte(0x03); 933 emit_operand(dst, src); 934 } 935 936 void Assembler::addl(Register dst, Register src) { 937 (void) prefix_and_encode(dst->encoding(), src->encoding()); 938 emit_arith(0x03, 0xC0, dst, src); 939 } 940 941 void Assembler::addr_nop_4() { 942 // 4 bytes: NOP DWORD PTR [EAX+0] 943 emit_byte(0x0F); 944 emit_byte(0x1F); 945 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 946 emit_byte(0); // 8-bits offset (1 byte) 947 } 948 949 void Assembler::addr_nop_5() { 950 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 951 emit_byte(0x0F); 952 emit_byte(0x1F); 953 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 954 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 955 emit_byte(0); // 8-bits offset (1 byte) 956 } 957 958 void Assembler::addr_nop_7() { 959 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 960 emit_byte(0x0F); 961 emit_byte(0x1F); 962 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 963 emit_long(0); // 32-bits offset (4 bytes) 964 } 965 966 void Assembler::addr_nop_8() { 967 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 968 emit_byte(0x0F); 969 emit_byte(0x1F); 970 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 971 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 972 emit_long(0); // 32-bits offset (4 bytes) 973 } 974 975 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 976 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 977 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 978 emit_byte(0x58); 979 emit_byte(0xC0 | encode); 980 } 981 982 void Assembler::addsd(XMMRegister dst, Address src) { 983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 984 InstructionMark im(this); 985 simd_prefix(dst, dst, src, VEX_SIMD_F2); 986 emit_byte(0x58); 987 emit_operand(dst, src); 988 } 989 990 void Assembler::addss(XMMRegister dst, XMMRegister src) { 991 NOT_LP64(assert(VM_Version::supports_sse(), "")); 992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 993 emit_byte(0x58); 994 emit_byte(0xC0 | encode); 995 } 996 997 void Assembler::addss(XMMRegister dst, Address src) { 998 NOT_LP64(assert(VM_Version::supports_sse(), "")); 999 InstructionMark im(this); 1000 simd_prefix(dst, dst, src, VEX_SIMD_F3); 1001 emit_byte(0x58); 1002 emit_operand(dst, src); 1003 } 1004 1005 void Assembler::andl(Address dst, int32_t imm32) { 1006 InstructionMark im(this); 1007 prefix(dst); 1008 emit_byte(0x81); 1009 emit_operand(rsp, dst, 4); 1010 emit_long(imm32); 1011 } 1012 1013 void Assembler::andl(Register dst, int32_t imm32) { 1014 prefix(dst); 1015 emit_arith(0x81, 0xE0, dst, imm32); 1016 } 1017 1018 void Assembler::andl(Register dst, Address src) { 1019 InstructionMark im(this); 1020 prefix(src, dst); 1021 emit_byte(0x23); 1022 emit_operand(dst, src); 1023 } 1024 1025 void Assembler::andl(Register dst, Register src) { 1026 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1027 emit_arith(0x23, 0xC0, dst, src); 1028 } 1029 1030 void Assembler::andpd(XMMRegister dst, Address src) { 1031 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1032 InstructionMark im(this); 1033 simd_prefix(dst, dst, src, VEX_SIMD_66); 1034 emit_byte(0x54); 1035 emit_operand(dst, src); 1036 } 1037 1038 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 1039 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1040 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 1041 emit_byte(0x54); 1042 emit_byte(0xC0 | encode); 1043 } 1044 1045 void Assembler::andps(XMMRegister dst, Address src) { 1046 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1047 InstructionMark im(this); 1048 simd_prefix(dst, dst, src, VEX_SIMD_NONE); 1049 emit_byte(0x54); 1050 emit_operand(dst, src); 1051 } 1052 1053 void Assembler::andps(XMMRegister dst, XMMRegister src) { 1054 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); 1056 emit_byte(0x54); 1057 emit_byte(0xC0 | encode); 1058 } 1059 1060 void Assembler::bsfl(Register dst, Register src) { 1061 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1062 emit_byte(0x0F); 1063 emit_byte(0xBC); 1064 emit_byte(0xC0 | encode); 1065 } 1066 1067 void Assembler::bsrl(Register dst, Register src) { 1068 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); 1069 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1070 emit_byte(0x0F); 1071 emit_byte(0xBD); 1072 emit_byte(0xC0 | encode); 1073 } 1074 1075 void Assembler::bswapl(Register reg) { // bswap 1076 int encode = prefix_and_encode(reg->encoding()); 1077 emit_byte(0x0F); 1078 emit_byte(0xC8 | encode); 1079 } 1080 1081 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1082 // suspect disp32 is always good 1083 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1084 1085 if (L.is_bound()) { 1086 const int long_size = 5; 1087 int offs = (int)( target(L) - pc() ); 1088 assert(offs <= 0, "assembler error"); 1089 InstructionMark im(this); 1090 // 1110 1000 #32-bit disp 1091 emit_byte(0xE8); 1092 emit_data(offs - long_size, rtype, operand); 1093 } else { 1094 InstructionMark im(this); 1095 // 1110 1000 #32-bit disp 1096 L.add_patch_at(code(), locator()); 1097 1098 emit_byte(0xE8); 1099 emit_data(int(0), rtype, operand); 1100 } 1101 } 1102 1103 void Assembler::call(Register dst) { 1104 int encode = prefix_and_encode(dst->encoding()); 1105 emit_byte(0xFF); 1106 emit_byte(0xD0 | encode); 1107 } 1108 1109 1110 void Assembler::call(Address adr) { 1111 InstructionMark im(this); 1112 prefix(adr); 1113 emit_byte(0xFF); 1114 emit_operand(rdx, adr); 1115 } 1116 1117 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1118 assert(entry != NULL, "call most probably wrong"); 1119 InstructionMark im(this); 1120 emit_byte(0xE8); 1121 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); 1122 assert(is_simm32(disp), "must be 32bit offset (call2)"); 1123 // Technically, should use call32_operand, but this format is 1124 // implied by the fact that we're emitting a call instruction. 1125 1126 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1127 emit_data((int) disp, rspec, operand); 1128 } 1129 1130 void Assembler::cdql() { 1131 emit_byte(0x99); 1132 } 1133 1134 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1135 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1136 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1137 emit_byte(0x0F); 1138 emit_byte(0x40 | cc); 1139 emit_byte(0xC0 | encode); 1140 } 1141 1142 1143 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1144 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1145 prefix(src, dst); 1146 emit_byte(0x0F); 1147 emit_byte(0x40 | cc); 1148 emit_operand(dst, src); 1149 } 1150 1151 void Assembler::cmpb(Address dst, int imm8) { 1152 InstructionMark im(this); 1153 prefix(dst); 1154 emit_byte(0x80); 1155 emit_operand(rdi, dst, 1); 1156 emit_byte(imm8); 1157 } 1158 1159 void Assembler::cmpl(Address dst, int32_t imm32) { 1160 InstructionMark im(this); 1161 prefix(dst); 1162 emit_byte(0x81); 1163 emit_operand(rdi, dst, 4); 1164 emit_long(imm32); 1165 } 1166 1167 void Assembler::cmpl(Register dst, int32_t imm32) { 1168 prefix(dst); 1169 emit_arith(0x81, 0xF8, dst, imm32); 1170 } 1171 1172 void Assembler::cmpl(Register dst, Register src) { 1173 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1174 emit_arith(0x3B, 0xC0, dst, src); 1175 } 1176 1177 1178 void Assembler::cmpl(Register dst, Address src) { 1179 InstructionMark im(this); 1180 prefix(src, dst); 1181 emit_byte(0x3B); 1182 emit_operand(dst, src); 1183 } 1184 1185 void Assembler::cmpw(Address dst, int imm16) { 1186 InstructionMark im(this); 1187 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1188 emit_byte(0x66); 1189 emit_byte(0x81); 1190 emit_operand(rdi, dst, 2); 1191 emit_word(imm16); 1192 } 1193 1194 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1195 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1196 // The ZF is set if the compared values were equal, and cleared otherwise. 1197 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1198 if (Atomics & 2) { 1199 // caveat: no instructionmark, so this isn't relocatable. 1200 // Emit a synthetic, non-atomic, CAS equivalent. 1201 // Beware. The synthetic form sets all ICCs, not just ZF. 1202 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) 1203 cmpl(rax, adr); 1204 movl(rax, adr); 1205 if (reg != rax) { 1206 Label L ; 1207 jcc(Assembler::notEqual, L); 1208 movl(adr, reg); 1209 bind(L); 1210 } 1211 } else { 1212 InstructionMark im(this); 1213 prefix(adr, reg); 1214 emit_byte(0x0F); 1215 emit_byte(0xB1); 1216 emit_operand(reg, adr); 1217 } 1218 } 1219 1220 void Assembler::comisd(XMMRegister dst, Address src) { 1221 // NOTE: dbx seems to decode this as comiss even though the 1222 // 0x66 is there. Strangly ucomisd comes out correct 1223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1224 InstructionMark im(this); 1225 simd_prefix(dst, src, VEX_SIMD_66); 1226 emit_byte(0x2F); 1227 emit_operand(dst, src); 1228 } 1229 1230 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1231 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1232 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 1233 emit_byte(0x2F); 1234 emit_byte(0xC0 | encode); 1235 } 1236 1237 void Assembler::comiss(XMMRegister dst, Address src) { 1238 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1239 InstructionMark im(this); 1240 simd_prefix(dst, src, VEX_SIMD_NONE); 1241 emit_byte(0x2F); 1242 emit_operand(dst, src); 1243 } 1244 1245 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1246 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1247 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); 1248 emit_byte(0x2F); 1249 emit_byte(0xC0 | encode); 1250 } 1251 1252 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1253 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1254 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); 1255 emit_byte(0xE6); 1256 emit_byte(0xC0 | encode); 1257 } 1258 1259 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); 1262 emit_byte(0x5B); 1263 emit_byte(0xC0 | encode); 1264 } 1265 1266 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1268 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 1269 emit_byte(0x5A); 1270 emit_byte(0xC0 | encode); 1271 } 1272 1273 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1275 InstructionMark im(this); 1276 simd_prefix(dst, dst, src, VEX_SIMD_F2); 1277 emit_byte(0x5A); 1278 emit_operand(dst, src); 1279 } 1280 1281 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1282 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1283 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 1284 emit_byte(0x2A); 1285 emit_byte(0xC0 | encode); 1286 } 1287 1288 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1289 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1290 InstructionMark im(this); 1291 simd_prefix(dst, dst, src, VEX_SIMD_F2); 1292 emit_byte(0x2A); 1293 emit_operand(dst, src); 1294 } 1295 1296 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1297 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 1299 emit_byte(0x2A); 1300 emit_byte(0xC0 | encode); 1301 } 1302 1303 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1304 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1305 InstructionMark im(this); 1306 simd_prefix(dst, dst, src, VEX_SIMD_F3); 1307 emit_byte(0x2A); 1308 emit_operand(dst, src); 1309 } 1310 1311 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 1314 emit_byte(0x5A); 1315 emit_byte(0xC0 | encode); 1316 } 1317 1318 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1320 InstructionMark im(this); 1321 simd_prefix(dst, dst, src, VEX_SIMD_F3); 1322 emit_byte(0x5A); 1323 emit_operand(dst, src); 1324 } 1325 1326 1327 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1329 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); 1330 emit_byte(0x2C); 1331 emit_byte(0xC0 | encode); 1332 } 1333 1334 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1335 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1336 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); 1337 emit_byte(0x2C); 1338 emit_byte(0xC0 | encode); 1339 } 1340 1341 void Assembler::decl(Address dst) { 1342 // Don't use it directly. Use MacroAssembler::decrement() instead. 1343 InstructionMark im(this); 1344 prefix(dst); 1345 emit_byte(0xFF); 1346 emit_operand(rcx, dst); 1347 } 1348 1349 void Assembler::divsd(XMMRegister dst, Address src) { 1350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1351 InstructionMark im(this); 1352 simd_prefix(dst, dst, src, VEX_SIMD_F2); 1353 emit_byte(0x5E); 1354 emit_operand(dst, src); 1355 } 1356 1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 1360 emit_byte(0x5E); 1361 emit_byte(0xC0 | encode); 1362 } 1363 1364 void Assembler::divss(XMMRegister dst, Address src) { 1365 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1366 InstructionMark im(this); 1367 simd_prefix(dst, dst, src, VEX_SIMD_F3); 1368 emit_byte(0x5E); 1369 emit_operand(dst, src); 1370 } 1371 1372 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1373 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 1375 emit_byte(0x5E); 1376 emit_byte(0xC0 | encode); 1377 } 1378 1379 void Assembler::emms() { 1380 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1381 emit_byte(0x0F); 1382 emit_byte(0x77); 1383 } 1384 1385 void Assembler::hlt() { 1386 emit_byte(0xF4); 1387 } 1388 1389 void Assembler::idivl(Register src) { 1390 int encode = prefix_and_encode(src->encoding()); 1391 emit_byte(0xF7); 1392 emit_byte(0xF8 | encode); 1393 } 1394 1395 void Assembler::divl(Register src) { // Unsigned 1396 int encode = prefix_and_encode(src->encoding()); 1397 emit_byte(0xF7); 1398 emit_byte(0xF0 | encode); 1399 } 1400 1401 void Assembler::imull(Register dst, Register src) { 1402 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1403 emit_byte(0x0F); 1404 emit_byte(0xAF); 1405 emit_byte(0xC0 | encode); 1406 } 1407 1408 1409 void Assembler::imull(Register dst, Register src, int value) { 1410 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1411 if (is8bit(value)) { 1412 emit_byte(0x6B); 1413 emit_byte(0xC0 | encode); 1414 emit_byte(value & 0xFF); 1415 } else { 1416 emit_byte(0x69); 1417 emit_byte(0xC0 | encode); 1418 emit_long(value); 1419 } 1420 } 1421 1422 void Assembler::incl(Address dst) { 1423 // Don't use it directly. Use MacroAssembler::increment() instead. 1424 InstructionMark im(this); 1425 prefix(dst); 1426 emit_byte(0xFF); 1427 emit_operand(rax, dst); 1428 } 1429 1430 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 1431 InstructionMark im(this); 1432 assert((0 <= cc) && (cc < 16), "illegal cc"); 1433 if (L.is_bound()) { 1434 address dst = target(L); 1435 assert(dst != NULL, "jcc most probably wrong"); 1436 1437 const int short_size = 2; 1438 const int long_size = 6; 1439 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; 1440 if (maybe_short && is8bit(offs - short_size)) { 1441 // 0111 tttn #8-bit disp 1442 emit_byte(0x70 | cc); 1443 emit_byte((offs - short_size) & 0xFF); 1444 } else { 1445 // 0000 1111 1000 tttn #32-bit disp 1446 assert(is_simm32(offs - long_size), 1447 "must be 32bit offset (call4)"); 1448 emit_byte(0x0F); 1449 emit_byte(0x80 | cc); 1450 emit_long(offs - long_size); 1451 } 1452 } else { 1453 // Note: could eliminate cond. jumps to this jump if condition 1454 // is the same however, seems to be rather unlikely case. 1455 // Note: use jccb() if label to be bound is very close to get 1456 // an 8-bit displacement 1457 L.add_patch_at(code(), locator()); 1458 emit_byte(0x0F); 1459 emit_byte(0x80 | cc); 1460 emit_long(0); 1461 } 1462 } 1463 1464 void Assembler::jccb(Condition cc, Label& L) { 1465 if (L.is_bound()) { 1466 const int short_size = 2; 1467 address entry = target(L); 1468 #ifdef ASSERT 1469 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); 1470 intptr_t delta = short_branch_delta(); 1471 if (delta != 0) { 1472 dist += (dist < 0 ? (-delta) :delta); 1473 } 1474 assert(is8bit(dist), "Dispacement too large for a short jmp"); 1475 #endif 1476 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; 1477 // 0111 tttn #8-bit disp 1478 emit_byte(0x70 | cc); 1479 emit_byte((offs - short_size) & 0xFF); 1480 } else { 1481 InstructionMark im(this); 1482 L.add_patch_at(code(), locator()); 1483 emit_byte(0x70 | cc); 1484 emit_byte(0); 1485 } 1486 } 1487 1488 void Assembler::jmp(Address adr) { 1489 InstructionMark im(this); 1490 prefix(adr); 1491 emit_byte(0xFF); 1492 emit_operand(rsp, adr); 1493 } 1494 1495 void Assembler::jmp(Label& L, bool maybe_short) { 1496 if (L.is_bound()) { 1497 address entry = target(L); 1498 assert(entry != NULL, "jmp most probably wrong"); 1499 InstructionMark im(this); 1500 const int short_size = 2; 1501 const int long_size = 5; 1502 intptr_t offs = entry - _code_pos; 1503 if (maybe_short && is8bit(offs - short_size)) { 1504 emit_byte(0xEB); 1505 emit_byte((offs - short_size) & 0xFF); 1506 } else { 1507 emit_byte(0xE9); 1508 emit_long(offs - long_size); 1509 } 1510 } else { 1511 // By default, forward jumps are always 32-bit displacements, since 1512 // we can't yet know where the label will be bound. If you're sure that 1513 // the forward jump will not run beyond 256 bytes, use jmpb to 1514 // force an 8-bit displacement. 1515 InstructionMark im(this); 1516 L.add_patch_at(code(), locator()); 1517 emit_byte(0xE9); 1518 emit_long(0); 1519 } 1520 } 1521 1522 void Assembler::jmp(Register entry) { 1523 int encode = prefix_and_encode(entry->encoding()); 1524 emit_byte(0xFF); 1525 emit_byte(0xE0 | encode); 1526 } 1527 1528 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 1529 InstructionMark im(this); 1530 emit_byte(0xE9); 1531 assert(dest != NULL, "must have a target"); 1532 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); 1533 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 1534 emit_data(disp, rspec.reloc(), call32_operand); 1535 } 1536 1537 void Assembler::jmpb(Label& L) { 1538 if (L.is_bound()) { 1539 const int short_size = 2; 1540 address entry = target(L); 1541 assert(entry != NULL, "jmp most probably wrong"); 1542 #ifdef ASSERT 1543 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); 1544 intptr_t delta = short_branch_delta(); 1545 if (delta != 0) { 1546 dist += (dist < 0 ? (-delta) :delta); 1547 } 1548 assert(is8bit(dist), "Dispacement too large for a short jmp"); 1549 #endif 1550 intptr_t offs = entry - _code_pos; 1551 emit_byte(0xEB); 1552 emit_byte((offs - short_size) & 0xFF); 1553 } else { 1554 InstructionMark im(this); 1555 L.add_patch_at(code(), locator()); 1556 emit_byte(0xEB); 1557 emit_byte(0); 1558 } 1559 } 1560 1561 void Assembler::ldmxcsr( Address src) { 1562 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1563 InstructionMark im(this); 1564 prefix(src); 1565 emit_byte(0x0F); 1566 emit_byte(0xAE); 1567 emit_operand(as_Register(2), src); 1568 } 1569 1570 void Assembler::leal(Register dst, Address src) { 1571 InstructionMark im(this); 1572 #ifdef _LP64 1573 emit_byte(0x67); // addr32 1574 prefix(src, dst); 1575 #endif // LP64 1576 emit_byte(0x8D); 1577 emit_operand(dst, src); 1578 } 1579 1580 void Assembler::lock() { 1581 if (Atomics & 1) { 1582 // Emit either nothing, a NOP, or a NOP: prefix 1583 emit_byte(0x90) ; 1584 } else { 1585 emit_byte(0xF0); 1586 } 1587 } 1588 1589 void Assembler::lzcntl(Register dst, Register src) { 1590 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 1591 emit_byte(0xF3); 1592 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1593 emit_byte(0x0F); 1594 emit_byte(0xBD); 1595 emit_byte(0xC0 | encode); 1596 } 1597 1598 // Emit mfence instruction 1599 void Assembler::mfence() { 1600 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 1601 emit_byte( 0x0F ); 1602 emit_byte( 0xAE ); 1603 emit_byte( 0xF0 ); 1604 } 1605 1606 void Assembler::mov(Register dst, Register src) { 1607 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 1608 } 1609 1610 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 1611 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1612 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 1613 emit_byte(0x28); 1614 emit_byte(0xC0 | encode); 1615 } 1616 1617 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 1618 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1619 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); 1620 emit_byte(0x28); 1621 emit_byte(0xC0 | encode); 1622 } 1623 1624 void Assembler::movb(Register dst, Address src) { 1625 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 1626 InstructionMark im(this); 1627 prefix(src, dst, true); 1628 emit_byte(0x8A); 1629 emit_operand(dst, src); 1630 } 1631 1632 1633 void Assembler::movb(Address dst, int imm8) { 1634 InstructionMark im(this); 1635 prefix(dst); 1636 emit_byte(0xC6); 1637 emit_operand(rax, dst, 1); 1638 emit_byte(imm8); 1639 } 1640 1641 1642 void Assembler::movb(Address dst, Register src) { 1643 assert(src->has_byte_register(), "must have byte register"); 1644 InstructionMark im(this); 1645 prefix(dst, src, true); 1646 emit_byte(0x88); 1647 emit_operand(src, dst); 1648 } 1649 1650 void Assembler::movdl(XMMRegister dst, Register src) { 1651 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1652 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 1653 emit_byte(0x6E); 1654 emit_byte(0xC0 | encode); 1655 } 1656 1657 void Assembler::movdl(Register dst, XMMRegister src) { 1658 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1659 // swap src/dst to get correct prefix 1660 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); 1661 emit_byte(0x7E); 1662 emit_byte(0xC0 | encode); 1663 } 1664 1665 void Assembler::movdl(XMMRegister dst, Address src) { 1666 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1667 InstructionMark im(this); 1668 simd_prefix(dst, src, VEX_SIMD_66); 1669 emit_byte(0x6E); 1670 emit_operand(dst, src); 1671 } 1672 1673 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 1674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1675 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 1676 emit_byte(0x6F); 1677 emit_byte(0xC0 | encode); 1678 } 1679 1680 void Assembler::movdqu(XMMRegister dst, Address src) { 1681 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1682 InstructionMark im(this); 1683 simd_prefix(dst, src, VEX_SIMD_F3); 1684 emit_byte(0x6F); 1685 emit_operand(dst, src); 1686 } 1687 1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1690 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); 1691 emit_byte(0x6F); 1692 emit_byte(0xC0 | encode); 1693 } 1694 1695 void Assembler::movdqu(Address dst, XMMRegister src) { 1696 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1697 InstructionMark im(this); 1698 simd_prefix(dst, src, VEX_SIMD_F3); 1699 emit_byte(0x7F); 1700 emit_operand(src, dst); 1701 } 1702 1703 // Uses zero extension on 64bit 1704 1705 void Assembler::movl(Register dst, int32_t imm32) { 1706 int encode = prefix_and_encode(dst->encoding()); 1707 emit_byte(0xB8 | encode); 1708 emit_long(imm32); 1709 } 1710 1711 void Assembler::movl(Register dst, Register src) { 1712 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1713 emit_byte(0x8B); 1714 emit_byte(0xC0 | encode); 1715 } 1716 1717 void Assembler::movl(Register dst, Address src) { 1718 InstructionMark im(this); 1719 prefix(src, dst); 1720 emit_byte(0x8B); 1721 emit_operand(dst, src); 1722 } 1723 1724 void Assembler::movl(Address dst, int32_t imm32) { 1725 InstructionMark im(this); 1726 prefix(dst); 1727 emit_byte(0xC7); 1728 emit_operand(rax, dst, 4); 1729 emit_long(imm32); 1730 } 1731 1732 void Assembler::movl(Address dst, Register src) { 1733 InstructionMark im(this); 1734 prefix(dst, src); 1735 emit_byte(0x89); 1736 emit_operand(src, dst); 1737 } 1738 1739 // New cpus require to use movsd and movss to avoid partial register stall 1740 // when loading from memory. But for old Opteron use movlpd instead of movsd. 1741 // The selection is done in MacroAssembler::movdbl() and movflt(). 1742 void Assembler::movlpd(XMMRegister dst, Address src) { 1743 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1744 InstructionMark im(this); 1745 simd_prefix(dst, dst, src, VEX_SIMD_66); 1746 emit_byte(0x12); 1747 emit_operand(dst, src); 1748 } 1749 1750 void Assembler::movq( MMXRegister dst, Address src ) { 1751 assert( VM_Version::supports_mmx(), "" ); 1752 emit_byte(0x0F); 1753 emit_byte(0x6F); 1754 emit_operand(dst, src); 1755 } 1756 1757 void Assembler::movq( Address dst, MMXRegister src ) { 1758 assert( VM_Version::supports_mmx(), "" ); 1759 emit_byte(0x0F); 1760 emit_byte(0x7F); 1761 // workaround gcc (3.2.1-7a) bug 1762 // In that version of gcc with only an emit_operand(MMX, Address) 1763 // gcc will tail jump and try and reverse the parameters completely 1764 // obliterating dst in the process. By having a version available 1765 // that doesn't need to swap the args at the tail jump the bug is 1766 // avoided. 1767 emit_operand(dst, src); 1768 } 1769 1770 void Assembler::movq(XMMRegister dst, Address src) { 1771 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1772 InstructionMark im(this); 1773 simd_prefix(dst, src, VEX_SIMD_F3); 1774 emit_byte(0x7E); 1775 emit_operand(dst, src); 1776 } 1777 1778 void Assembler::movq(Address dst, XMMRegister src) { 1779 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1780 InstructionMark im(this); 1781 simd_prefix(dst, src, VEX_SIMD_66); 1782 emit_byte(0xD6); 1783 emit_operand(src, dst); 1784 } 1785 1786 void Assembler::movsbl(Register dst, Address src) { // movsxb 1787 InstructionMark im(this); 1788 prefix(src, dst); 1789 emit_byte(0x0F); 1790 emit_byte(0xBE); 1791 emit_operand(dst, src); 1792 } 1793 1794 void Assembler::movsbl(Register dst, Register src) { // movsxb 1795 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 1796 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); 1797 emit_byte(0x0F); 1798 emit_byte(0xBE); 1799 emit_byte(0xC0 | encode); 1800 } 1801 1802 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1804 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 1805 emit_byte(0x10); 1806 emit_byte(0xC0 | encode); 1807 } 1808 1809 void Assembler::movsd(XMMRegister dst, Address src) { 1810 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1811 InstructionMark im(this); 1812 simd_prefix(dst, src, VEX_SIMD_F2); 1813 emit_byte(0x10); 1814 emit_operand(dst, src); 1815 } 1816 1817 void Assembler::movsd(Address dst, XMMRegister src) { 1818 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1819 InstructionMark im(this); 1820 simd_prefix(dst, src, VEX_SIMD_F2); 1821 emit_byte(0x11); 1822 emit_operand(src, dst); 1823 } 1824 1825 void Assembler::movss(XMMRegister dst, XMMRegister src) { 1826 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1827 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 1828 emit_byte(0x10); 1829 emit_byte(0xC0 | encode); 1830 } 1831 1832 void Assembler::movss(XMMRegister dst, Address src) { 1833 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1834 InstructionMark im(this); 1835 simd_prefix(dst, src, VEX_SIMD_F3); 1836 emit_byte(0x10); 1837 emit_operand(dst, src); 1838 } 1839 1840 void Assembler::movss(Address dst, XMMRegister src) { 1841 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1842 InstructionMark im(this); 1843 simd_prefix(dst, src, VEX_SIMD_F3); 1844 emit_byte(0x11); 1845 emit_operand(src, dst); 1846 } 1847 1848 void Assembler::movswl(Register dst, Address src) { // movsxw 1849 InstructionMark im(this); 1850 prefix(src, dst); 1851 emit_byte(0x0F); 1852 emit_byte(0xBF); 1853 emit_operand(dst, src); 1854 } 1855 1856 void Assembler::movswl(Register dst, Register src) { // movsxw 1857 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1858 emit_byte(0x0F); 1859 emit_byte(0xBF); 1860 emit_byte(0xC0 | encode); 1861 } 1862 1863 void Assembler::movw(Address dst, int imm16) { 1864 InstructionMark im(this); 1865 1866 emit_byte(0x66); // switch to 16-bit mode 1867 prefix(dst); 1868 emit_byte(0xC7); 1869 emit_operand(rax, dst, 2); 1870 emit_word(imm16); 1871 } 1872 1873 void Assembler::movw(Register dst, Address src) { 1874 InstructionMark im(this); 1875 emit_byte(0x66); 1876 prefix(src, dst); 1877 emit_byte(0x8B); 1878 emit_operand(dst, src); 1879 } 1880 1881 void Assembler::movw(Address dst, Register src) { 1882 InstructionMark im(this); 1883 emit_byte(0x66); 1884 prefix(dst, src); 1885 emit_byte(0x89); 1886 emit_operand(src, dst); 1887 } 1888 1889 void Assembler::movzbl(Register dst, Address src) { // movzxb 1890 InstructionMark im(this); 1891 prefix(src, dst); 1892 emit_byte(0x0F); 1893 emit_byte(0xB6); 1894 emit_operand(dst, src); 1895 } 1896 1897 void Assembler::movzbl(Register dst, Register src) { // movzxb 1898 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 1899 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); 1900 emit_byte(0x0F); 1901 emit_byte(0xB6); 1902 emit_byte(0xC0 | encode); 1903 } 1904 1905 void Assembler::movzwl(Register dst, Address src) { // movzxw 1906 InstructionMark im(this); 1907 prefix(src, dst); 1908 emit_byte(0x0F); 1909 emit_byte(0xB7); 1910 emit_operand(dst, src); 1911 } 1912 1913 void Assembler::movzwl(Register dst, Register src) { // movzxw 1914 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1915 emit_byte(0x0F); 1916 emit_byte(0xB7); 1917 emit_byte(0xC0 | encode); 1918 } 1919 1920 void Assembler::mull(Address src) { 1921 InstructionMark im(this); 1922 prefix(src); 1923 emit_byte(0xF7); 1924 emit_operand(rsp, src); 1925 } 1926 1927 void Assembler::mull(Register src) { 1928 int encode = prefix_and_encode(src->encoding()); 1929 emit_byte(0xF7); 1930 emit_byte(0xE0 | encode); 1931 } 1932 1933 void Assembler::mulsd(XMMRegister dst, Address src) { 1934 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1935 InstructionMark im(this); 1936 simd_prefix(dst, dst, src, VEX_SIMD_F2); 1937 emit_byte(0x59); 1938 emit_operand(dst, src); 1939 } 1940 1941 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 1942 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1943 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 1944 emit_byte(0x59); 1945 emit_byte(0xC0 | encode); 1946 } 1947 1948 void Assembler::mulss(XMMRegister dst, Address src) { 1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1950 InstructionMark im(this); 1951 simd_prefix(dst, dst, src, VEX_SIMD_F3); 1952 emit_byte(0x59); 1953 emit_operand(dst, src); 1954 } 1955 1956 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 1957 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1958 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 1959 emit_byte(0x59); 1960 emit_byte(0xC0 | encode); 1961 } 1962 1963 void Assembler::negl(Register dst) { 1964 int encode = prefix_and_encode(dst->encoding()); 1965 emit_byte(0xF7); 1966 emit_byte(0xD8 | encode); 1967 } 1968 1969 void Assembler::nop(int i) { 1970 #ifdef ASSERT 1971 assert(i > 0, " "); 1972 // The fancy nops aren't currently recognized by debuggers making it a 1973 // pain to disassemble code while debugging. If asserts are on clearly 1974 // speed is not an issue so simply use the single byte traditional nop 1975 // to do alignment. 1976 1977 for (; i > 0 ; i--) emit_byte(0x90); 1978 return; 1979 1980 #endif // ASSERT 1981 1982 if (UseAddressNop && VM_Version::is_intel()) { 1983 // 1984 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 1985 // 1: 0x90 1986 // 2: 0x66 0x90 1987 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 1988 // 4: 0x0F 0x1F 0x40 0x00 1989 // 5: 0x0F 0x1F 0x44 0x00 0x00 1990 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 1991 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 1992 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 1993 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 1994 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 1995 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 1996 1997 // The rest coding is Intel specific - don't use consecutive address nops 1998 1999 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2000 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2001 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2002 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2003 2004 while(i >= 15) { 2005 // For Intel don't generate consecutive addess nops (mix with regular nops) 2006 i -= 15; 2007 emit_byte(0x66); // size prefix 2008 emit_byte(0x66); // size prefix 2009 emit_byte(0x66); // size prefix 2010 addr_nop_8(); 2011 emit_byte(0x66); // size prefix 2012 emit_byte(0x66); // size prefix 2013 emit_byte(0x66); // size prefix 2014 emit_byte(0x90); // nop 2015 } 2016 switch (i) { 2017 case 14: 2018 emit_byte(0x66); // size prefix 2019 case 13: 2020 emit_byte(0x66); // size prefix 2021 case 12: 2022 addr_nop_8(); 2023 emit_byte(0x66); // size prefix 2024 emit_byte(0x66); // size prefix 2025 emit_byte(0x66); // size prefix 2026 emit_byte(0x90); // nop 2027 break; 2028 case 11: 2029 emit_byte(0x66); // size prefix 2030 case 10: 2031 emit_byte(0x66); // size prefix 2032 case 9: 2033 emit_byte(0x66); // size prefix 2034 case 8: 2035 addr_nop_8(); 2036 break; 2037 case 7: 2038 addr_nop_7(); 2039 break; 2040 case 6: 2041 emit_byte(0x66); // size prefix 2042 case 5: 2043 addr_nop_5(); 2044 break; 2045 case 4: 2046 addr_nop_4(); 2047 break; 2048 case 3: 2049 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 2050 emit_byte(0x66); // size prefix 2051 case 2: 2052 emit_byte(0x66); // size prefix 2053 case 1: 2054 emit_byte(0x90); // nop 2055 break; 2056 default: 2057 assert(i == 0, " "); 2058 } 2059 return; 2060 } 2061 if (UseAddressNop && VM_Version::is_amd()) { 2062 // 2063 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 2064 // 1: 0x90 2065 // 2: 0x66 0x90 2066 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2067 // 4: 0x0F 0x1F 0x40 0x00 2068 // 5: 0x0F 0x1F 0x44 0x00 0x00 2069 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2070 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2071 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2072 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2073 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2074 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2075 2076 // The rest coding is AMD specific - use consecutive address nops 2077 2078 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 2079 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 2080 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2081 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2082 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2083 // Size prefixes (0x66) are added for larger sizes 2084 2085 while(i >= 22) { 2086 i -= 11; 2087 emit_byte(0x66); // size prefix 2088 emit_byte(0x66); // size prefix 2089 emit_byte(0x66); // size prefix 2090 addr_nop_8(); 2091 } 2092 // Generate first nop for size between 21-12 2093 switch (i) { 2094 case 21: 2095 i -= 1; 2096 emit_byte(0x66); // size prefix 2097 case 20: 2098 case 19: 2099 i -= 1; 2100 emit_byte(0x66); // size prefix 2101 case 18: 2102 case 17: 2103 i -= 1; 2104 emit_byte(0x66); // size prefix 2105 case 16: 2106 case 15: 2107 i -= 8; 2108 addr_nop_8(); 2109 break; 2110 case 14: 2111 case 13: 2112 i -= 7; 2113 addr_nop_7(); 2114 break; 2115 case 12: 2116 i -= 6; 2117 emit_byte(0x66); // size prefix 2118 addr_nop_5(); 2119 break; 2120 default: 2121 assert(i < 12, " "); 2122 } 2123 2124 // Generate second nop for size between 11-1 2125 switch (i) { 2126 case 11: 2127 emit_byte(0x66); // size prefix 2128 case 10: 2129 emit_byte(0x66); // size prefix 2130 case 9: 2131 emit_byte(0x66); // size prefix 2132 case 8: 2133 addr_nop_8(); 2134 break; 2135 case 7: 2136 addr_nop_7(); 2137 break; 2138 case 6: 2139 emit_byte(0x66); // size prefix 2140 case 5: 2141 addr_nop_5(); 2142 break; 2143 case 4: 2144 addr_nop_4(); 2145 break; 2146 case 3: 2147 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 2148 emit_byte(0x66); // size prefix 2149 case 2: 2150 emit_byte(0x66); // size prefix 2151 case 1: 2152 emit_byte(0x90); // nop 2153 break; 2154 default: 2155 assert(i == 0, " "); 2156 } 2157 return; 2158 } 2159 2160 // Using nops with size prefixes "0x66 0x90". 2161 // From AMD Optimization Guide: 2162 // 1: 0x90 2163 // 2: 0x66 0x90 2164 // 3: 0x66 0x66 0x90 2165 // 4: 0x66 0x66 0x66 0x90 2166 // 5: 0x66 0x66 0x90 0x66 0x90 2167 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 2168 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 2169 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 2170 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 2171 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 2172 // 2173 while(i > 12) { 2174 i -= 4; 2175 emit_byte(0x66); // size prefix 2176 emit_byte(0x66); 2177 emit_byte(0x66); 2178 emit_byte(0x90); // nop 2179 } 2180 // 1 - 12 nops 2181 if(i > 8) { 2182 if(i > 9) { 2183 i -= 1; 2184 emit_byte(0x66); 2185 } 2186 i -= 3; 2187 emit_byte(0x66); 2188 emit_byte(0x66); 2189 emit_byte(0x90); 2190 } 2191 // 1 - 8 nops 2192 if(i > 4) { 2193 if(i > 6) { 2194 i -= 1; 2195 emit_byte(0x66); 2196 } 2197 i -= 3; 2198 emit_byte(0x66); 2199 emit_byte(0x66); 2200 emit_byte(0x90); 2201 } 2202 switch (i) { 2203 case 4: 2204 emit_byte(0x66); 2205 case 3: 2206 emit_byte(0x66); 2207 case 2: 2208 emit_byte(0x66); 2209 case 1: 2210 emit_byte(0x90); 2211 break; 2212 default: 2213 assert(i == 0, " "); 2214 } 2215 } 2216 2217 void Assembler::notl(Register dst) { 2218 int encode = prefix_and_encode(dst->encoding()); 2219 emit_byte(0xF7); 2220 emit_byte(0xD0 | encode ); 2221 } 2222 2223 void Assembler::orl(Address dst, int32_t imm32) { 2224 InstructionMark im(this); 2225 prefix(dst); 2226 emit_arith_operand(0x81, rcx, dst, imm32); 2227 } 2228 2229 void Assembler::orl(Register dst, int32_t imm32) { 2230 prefix(dst); 2231 emit_arith(0x81, 0xC8, dst, imm32); 2232 } 2233 2234 void Assembler::orl(Register dst, Address src) { 2235 InstructionMark im(this); 2236 prefix(src, dst); 2237 emit_byte(0x0B); 2238 emit_operand(dst, src); 2239 } 2240 2241 void Assembler::orl(Register dst, Register src) { 2242 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2243 emit_arith(0x0B, 0xC0, dst, src); 2244 } 2245 2246 void Assembler::packuswb(XMMRegister dst, Address src) { 2247 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2248 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2249 InstructionMark im(this); 2250 simd_prefix(dst, dst, src, VEX_SIMD_66); 2251 emit_byte(0x67); 2252 emit_operand(dst, src); 2253 } 2254 2255 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 2256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2257 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2258 emit_byte(0x67); 2259 emit_byte(0xC0 | encode); 2260 } 2261 2262 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 2263 assert(VM_Version::supports_sse4_2(), ""); 2264 InstructionMark im(this); 2265 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); 2266 emit_byte(0x61); 2267 emit_operand(dst, src); 2268 emit_byte(imm8); 2269 } 2270 2271 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 2272 assert(VM_Version::supports_sse4_2(), ""); 2273 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); 2274 emit_byte(0x61); 2275 emit_byte(0xC0 | encode); 2276 emit_byte(imm8); 2277 } 2278 2279 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 2280 assert(VM_Version::supports_sse4_1(), ""); 2281 InstructionMark im(this); 2282 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); 2283 emit_byte(0x30); 2284 emit_operand(dst, src); 2285 } 2286 2287 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 2288 assert(VM_Version::supports_sse4_1(), ""); 2289 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); 2290 emit_byte(0x30); 2291 emit_byte(0xC0 | encode); 2292 } 2293 2294 // generic 2295 void Assembler::pop(Register dst) { 2296 int encode = prefix_and_encode(dst->encoding()); 2297 emit_byte(0x58 | encode); 2298 } 2299 2300 void Assembler::popcntl(Register dst, Address src) { 2301 assert(VM_Version::supports_popcnt(), "must support"); 2302 InstructionMark im(this); 2303 emit_byte(0xF3); 2304 prefix(src, dst); 2305 emit_byte(0x0F); 2306 emit_byte(0xB8); 2307 emit_operand(dst, src); 2308 } 2309 2310 void Assembler::popcntl(Register dst, Register src) { 2311 assert(VM_Version::supports_popcnt(), "must support"); 2312 emit_byte(0xF3); 2313 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2314 emit_byte(0x0F); 2315 emit_byte(0xB8); 2316 emit_byte(0xC0 | encode); 2317 } 2318 2319 void Assembler::popf() { 2320 emit_byte(0x9D); 2321 } 2322 2323 #ifndef _LP64 // no 32bit push/pop on amd64 2324 void Assembler::popl(Address dst) { 2325 // NOTE: this will adjust stack by 8byte on 64bits 2326 InstructionMark im(this); 2327 prefix(dst); 2328 emit_byte(0x8F); 2329 emit_operand(rax, dst); 2330 } 2331 #endif 2332 2333 void Assembler::prefetch_prefix(Address src) { 2334 prefix(src); 2335 emit_byte(0x0F); 2336 } 2337 2338 void Assembler::prefetchnta(Address src) { 2339 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2340 InstructionMark im(this); 2341 prefetch_prefix(src); 2342 emit_byte(0x18); 2343 emit_operand(rax, src); // 0, src 2344 } 2345 2346 void Assembler::prefetchr(Address src) { 2347 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 2348 InstructionMark im(this); 2349 prefetch_prefix(src); 2350 emit_byte(0x0D); 2351 emit_operand(rax, src); // 0, src 2352 } 2353 2354 void Assembler::prefetcht0(Address src) { 2355 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2356 InstructionMark im(this); 2357 prefetch_prefix(src); 2358 emit_byte(0x18); 2359 emit_operand(rcx, src); // 1, src 2360 } 2361 2362 void Assembler::prefetcht1(Address src) { 2363 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2364 InstructionMark im(this); 2365 prefetch_prefix(src); 2366 emit_byte(0x18); 2367 emit_operand(rdx, src); // 2, src 2368 } 2369 2370 void Assembler::prefetcht2(Address src) { 2371 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2372 InstructionMark im(this); 2373 prefetch_prefix(src); 2374 emit_byte(0x18); 2375 emit_operand(rbx, src); // 3, src 2376 } 2377 2378 void Assembler::prefetchw(Address src) { 2379 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 2380 InstructionMark im(this); 2381 prefetch_prefix(src); 2382 emit_byte(0x0D); 2383 emit_operand(rcx, src); // 1, src 2384 } 2385 2386 void Assembler::prefix(Prefix p) { 2387 a_byte(p); 2388 } 2389 2390 void Assembler::por(XMMRegister dst, XMMRegister src) { 2391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2392 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2393 emit_byte(0xEB); 2394 emit_byte(0xC0 | encode); 2395 } 2396 2397 void Assembler::por(XMMRegister dst, Address src) { 2398 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2399 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2400 InstructionMark im(this); 2401 simd_prefix(dst, dst, src, VEX_SIMD_66); 2402 emit_byte(0xEB); 2403 emit_operand(dst, src); 2404 } 2405 2406 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 2407 assert(isByte(mode), "invalid value"); 2408 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2409 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 2410 emit_byte(0x70); 2411 emit_byte(0xC0 | encode); 2412 emit_byte(mode & 0xFF); 2413 2414 } 2415 2416 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 2417 assert(isByte(mode), "invalid value"); 2418 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2419 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2420 InstructionMark im(this); 2421 simd_prefix(dst, src, VEX_SIMD_66); 2422 emit_byte(0x70); 2423 emit_operand(dst, src); 2424 emit_byte(mode & 0xFF); 2425 } 2426 2427 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 2428 assert(isByte(mode), "invalid value"); 2429 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2430 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); 2431 emit_byte(0x70); 2432 emit_byte(0xC0 | encode); 2433 emit_byte(mode & 0xFF); 2434 } 2435 2436 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 2437 assert(isByte(mode), "invalid value"); 2438 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2439 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2440 InstructionMark im(this); 2441 simd_prefix(dst, src, VEX_SIMD_F2); 2442 emit_byte(0x70); 2443 emit_operand(dst, src); 2444 emit_byte(mode & 0xFF); 2445 } 2446 2447 void Assembler::psrlq(XMMRegister dst, int shift) { 2448 // Shift 64 bit value logically right by specified number of bits. 2449 // HMM Table D-1 says sse2 or mmx. 2450 // Do not confuse it with psrldq SSE2 instruction which 2451 // shifts 128 bit value in xmm register by number of bytes. 2452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2453 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); 2454 emit_byte(0x73); 2455 emit_byte(0xC0 | encode); 2456 emit_byte(shift); 2457 } 2458 2459 void Assembler::psrldq(XMMRegister dst, int shift) { 2460 // Shift 128 bit value in xmm register by number of bytes. 2461 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2462 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); 2463 emit_byte(0x73); 2464 emit_byte(0xC0 | encode); 2465 emit_byte(shift); 2466 } 2467 2468 void Assembler::ptest(XMMRegister dst, Address src) { 2469 assert(VM_Version::supports_sse4_1(), ""); 2470 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2471 InstructionMark im(this); 2472 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); 2473 emit_byte(0x17); 2474 emit_operand(dst, src); 2475 } 2476 2477 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 2478 assert(VM_Version::supports_sse4_1(), ""); 2479 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); 2480 emit_byte(0x17); 2481 emit_byte(0xC0 | encode); 2482 } 2483 2484 void Assembler::punpcklbw(XMMRegister dst, Address src) { 2485 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2486 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2487 InstructionMark im(this); 2488 simd_prefix(dst, dst, src, VEX_SIMD_66); 2489 emit_byte(0x60); 2490 emit_operand(dst, src); 2491 } 2492 2493 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 2494 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2496 emit_byte(0x60); 2497 emit_byte(0xC0 | encode); 2498 } 2499 2500 void Assembler::punpckldq(XMMRegister dst, Address src) { 2501 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2502 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2503 InstructionMark im(this); 2504 simd_prefix(dst, dst, src, VEX_SIMD_66); 2505 emit_byte(0x62); 2506 emit_operand(dst, src); 2507 } 2508 2509 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2511 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2512 emit_byte(0x62); 2513 emit_byte(0xC0 | encode); 2514 } 2515 2516 void Assembler::push(int32_t imm32) { 2517 // in 64bits we push 64bits onto the stack but only 2518 // take a 32bit immediate 2519 emit_byte(0x68); 2520 emit_long(imm32); 2521 } 2522 2523 void Assembler::push(Register src) { 2524 int encode = prefix_and_encode(src->encoding()); 2525 2526 emit_byte(0x50 | encode); 2527 } 2528 2529 void Assembler::pushf() { 2530 emit_byte(0x9C); 2531 } 2532 2533 #ifndef _LP64 // no 32bit push/pop on amd64 2534 void Assembler::pushl(Address src) { 2535 // Note this will push 64bit on 64bit 2536 InstructionMark im(this); 2537 prefix(src); 2538 emit_byte(0xFF); 2539 emit_operand(rsi, src); 2540 } 2541 #endif 2542 2543 void Assembler::pxor(XMMRegister dst, Address src) { 2544 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2545 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2546 InstructionMark im(this); 2547 simd_prefix(dst, dst, src, VEX_SIMD_66); 2548 emit_byte(0xEF); 2549 emit_operand(dst, src); 2550 } 2551 2552 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 2553 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2554 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2555 emit_byte(0xEF); 2556 emit_byte(0xC0 | encode); 2557 } 2558 2559 void Assembler::rcll(Register dst, int imm8) { 2560 assert(isShiftCount(imm8), "illegal shift count"); 2561 int encode = prefix_and_encode(dst->encoding()); 2562 if (imm8 == 1) { 2563 emit_byte(0xD1); 2564 emit_byte(0xD0 | encode); 2565 } else { 2566 emit_byte(0xC1); 2567 emit_byte(0xD0 | encode); 2568 emit_byte(imm8); 2569 } 2570 } 2571 2572 // copies data from [esi] to [edi] using rcx pointer sized words 2573 // generic 2574 void Assembler::rep_mov() { 2575 emit_byte(0xF3); 2576 // MOVSQ 2577 LP64_ONLY(prefix(REX_W)); 2578 emit_byte(0xA5); 2579 } 2580 2581 // sets rcx pointer sized words with rax, value at [edi] 2582 // generic 2583 void Assembler::rep_set() { // rep_set 2584 emit_byte(0xF3); 2585 // STOSQ 2586 LP64_ONLY(prefix(REX_W)); 2587 emit_byte(0xAB); 2588 } 2589 2590 // scans rcx pointer sized words at [edi] for occurance of rax, 2591 // generic 2592 void Assembler::repne_scan() { // repne_scan 2593 emit_byte(0xF2); 2594 // SCASQ 2595 LP64_ONLY(prefix(REX_W)); 2596 emit_byte(0xAF); 2597 } 2598 2599 #ifdef _LP64 2600 // scans rcx 4 byte words at [edi] for occurance of rax, 2601 // generic 2602 void Assembler::repne_scanl() { // repne_scan 2603 emit_byte(0xF2); 2604 // SCASL 2605 emit_byte(0xAF); 2606 } 2607 #endif 2608 2609 void Assembler::ret(int imm16) { 2610 if (imm16 == 0) { 2611 emit_byte(0xC3); 2612 } else { 2613 emit_byte(0xC2); 2614 emit_word(imm16); 2615 } 2616 } 2617 2618 void Assembler::sahf() { 2619 #ifdef _LP64 2620 // Not supported in 64bit mode 2621 ShouldNotReachHere(); 2622 #endif 2623 emit_byte(0x9E); 2624 } 2625 2626 void Assembler::sarl(Register dst, int imm8) { 2627 int encode = prefix_and_encode(dst->encoding()); 2628 assert(isShiftCount(imm8), "illegal shift count"); 2629 if (imm8 == 1) { 2630 emit_byte(0xD1); 2631 emit_byte(0xF8 | encode); 2632 } else { 2633 emit_byte(0xC1); 2634 emit_byte(0xF8 | encode); 2635 emit_byte(imm8); 2636 } 2637 } 2638 2639 void Assembler::sarl(Register dst) { 2640 int encode = prefix_and_encode(dst->encoding()); 2641 emit_byte(0xD3); 2642 emit_byte(0xF8 | encode); 2643 } 2644 2645 void Assembler::sbbl(Address dst, int32_t imm32) { 2646 InstructionMark im(this); 2647 prefix(dst); 2648 emit_arith_operand(0x81, rbx, dst, imm32); 2649 } 2650 2651 void Assembler::sbbl(Register dst, int32_t imm32) { 2652 prefix(dst); 2653 emit_arith(0x81, 0xD8, dst, imm32); 2654 } 2655 2656 2657 void Assembler::sbbl(Register dst, Address src) { 2658 InstructionMark im(this); 2659 prefix(src, dst); 2660 emit_byte(0x1B); 2661 emit_operand(dst, src); 2662 } 2663 2664 void Assembler::sbbl(Register dst, Register src) { 2665 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2666 emit_arith(0x1B, 0xC0, dst, src); 2667 } 2668 2669 void Assembler::setb(Condition cc, Register dst) { 2670 assert(0 <= cc && cc < 16, "illegal cc"); 2671 int encode = prefix_and_encode(dst->encoding(), true); 2672 emit_byte(0x0F); 2673 emit_byte(0x90 | cc); 2674 emit_byte(0xC0 | encode); 2675 } 2676 2677 void Assembler::shll(Register dst, int imm8) { 2678 assert(isShiftCount(imm8), "illegal shift count"); 2679 int encode = prefix_and_encode(dst->encoding()); 2680 if (imm8 == 1 ) { 2681 emit_byte(0xD1); 2682 emit_byte(0xE0 | encode); 2683 } else { 2684 emit_byte(0xC1); 2685 emit_byte(0xE0 | encode); 2686 emit_byte(imm8); 2687 } 2688 } 2689 2690 void Assembler::shll(Register dst) { 2691 int encode = prefix_and_encode(dst->encoding()); 2692 emit_byte(0xD3); 2693 emit_byte(0xE0 | encode); 2694 } 2695 2696 void Assembler::shrl(Register dst, int imm8) { 2697 assert(isShiftCount(imm8), "illegal shift count"); 2698 int encode = prefix_and_encode(dst->encoding()); 2699 emit_byte(0xC1); 2700 emit_byte(0xE8 | encode); 2701 emit_byte(imm8); 2702 } 2703 2704 void Assembler::shrl(Register dst) { 2705 int encode = prefix_and_encode(dst->encoding()); 2706 emit_byte(0xD3); 2707 emit_byte(0xE8 | encode); 2708 } 2709 2710 // copies a single word from [esi] to [edi] 2711 void Assembler::smovl() { 2712 emit_byte(0xA5); 2713 } 2714 2715 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 2716 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2717 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 2718 emit_byte(0x51); 2719 emit_byte(0xC0 | encode); 2720 } 2721 2722 void Assembler::sqrtsd(XMMRegister dst, Address src) { 2723 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2724 InstructionMark im(this); 2725 simd_prefix(dst, dst, src, VEX_SIMD_F2); 2726 emit_byte(0x51); 2727 emit_operand(dst, src); 2728 } 2729 2730 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 2731 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 2733 emit_byte(0x51); 2734 emit_byte(0xC0 | encode); 2735 } 2736 2737 void Assembler::sqrtss(XMMRegister dst, Address src) { 2738 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2739 InstructionMark im(this); 2740 simd_prefix(dst, dst, src, VEX_SIMD_F3); 2741 emit_byte(0x51); 2742 emit_operand(dst, src); 2743 } 2744 2745 void Assembler::stmxcsr( Address dst) { 2746 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2747 InstructionMark im(this); 2748 prefix(dst); 2749 emit_byte(0x0F); 2750 emit_byte(0xAE); 2751 emit_operand(as_Register(3), dst); 2752 } 2753 2754 void Assembler::subl(Address dst, int32_t imm32) { 2755 InstructionMark im(this); 2756 prefix(dst); 2757 emit_arith_operand(0x81, rbp, dst, imm32); 2758 } 2759 2760 void Assembler::subl(Address dst, Register src) { 2761 InstructionMark im(this); 2762 prefix(dst, src); 2763 emit_byte(0x29); 2764 emit_operand(src, dst); 2765 } 2766 2767 void Assembler::subl(Register dst, int32_t imm32) { 2768 prefix(dst); 2769 emit_arith(0x81, 0xE8, dst, imm32); 2770 } 2771 2772 void Assembler::subl(Register dst, Address src) { 2773 InstructionMark im(this); 2774 prefix(src, dst); 2775 emit_byte(0x2B); 2776 emit_operand(dst, src); 2777 } 2778 2779 void Assembler::subl(Register dst, Register src) { 2780 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2781 emit_arith(0x2B, 0xC0, dst, src); 2782 } 2783 2784 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 2785 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); 2787 emit_byte(0x5C); 2788 emit_byte(0xC0 | encode); 2789 } 2790 2791 void Assembler::subsd(XMMRegister dst, Address src) { 2792 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2793 InstructionMark im(this); 2794 simd_prefix(dst, dst, src, VEX_SIMD_F2); 2795 emit_byte(0x5C); 2796 emit_operand(dst, src); 2797 } 2798 2799 void Assembler::subss(XMMRegister dst, XMMRegister src) { 2800 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2801 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); 2802 emit_byte(0x5C); 2803 emit_byte(0xC0 | encode); 2804 } 2805 2806 void Assembler::subss(XMMRegister dst, Address src) { 2807 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2808 InstructionMark im(this); 2809 simd_prefix(dst, dst, src, VEX_SIMD_F3); 2810 emit_byte(0x5C); 2811 emit_operand(dst, src); 2812 } 2813 2814 void Assembler::testb(Register dst, int imm8) { 2815 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2816 (void) prefix_and_encode(dst->encoding(), true); 2817 emit_arith_b(0xF6, 0xC0, dst, imm8); 2818 } 2819 2820 void Assembler::testl(Register dst, int32_t imm32) { 2821 // not using emit_arith because test 2822 // doesn't support sign-extension of 2823 // 8bit operands 2824 int encode = dst->encoding(); 2825 if (encode == 0) { 2826 emit_byte(0xA9); 2827 } else { 2828 encode = prefix_and_encode(encode); 2829 emit_byte(0xF7); 2830 emit_byte(0xC0 | encode); 2831 } 2832 emit_long(imm32); 2833 } 2834 2835 void Assembler::testl(Register dst, Register src) { 2836 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2837 emit_arith(0x85, 0xC0, dst, src); 2838 } 2839 2840 void Assembler::testl(Register dst, Address src) { 2841 InstructionMark im(this); 2842 prefix(src, dst); 2843 emit_byte(0x85); 2844 emit_operand(dst, src); 2845 } 2846 2847 void Assembler::ucomisd(XMMRegister dst, Address src) { 2848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2849 InstructionMark im(this); 2850 simd_prefix(dst, src, VEX_SIMD_66); 2851 emit_byte(0x2E); 2852 emit_operand(dst, src); 2853 } 2854 2855 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 2856 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2857 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); 2858 emit_byte(0x2E); 2859 emit_byte(0xC0 | encode); 2860 } 2861 2862 void Assembler::ucomiss(XMMRegister dst, Address src) { 2863 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2864 InstructionMark im(this); 2865 simd_prefix(dst, src, VEX_SIMD_NONE); 2866 emit_byte(0x2E); 2867 emit_operand(dst, src); 2868 } 2869 2870 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 2871 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2872 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); 2873 emit_byte(0x2E); 2874 emit_byte(0xC0 | encode); 2875 } 2876 2877 2878 void Assembler::xaddl(Address dst, Register src) { 2879 InstructionMark im(this); 2880 prefix(dst, src); 2881 emit_byte(0x0F); 2882 emit_byte(0xC1); 2883 emit_operand(src, dst); 2884 } 2885 2886 void Assembler::xchgl(Register dst, Address src) { // xchg 2887 InstructionMark im(this); 2888 prefix(src, dst); 2889 emit_byte(0x87); 2890 emit_operand(dst, src); 2891 } 2892 2893 void Assembler::xchgl(Register dst, Register src) { 2894 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2895 emit_byte(0x87); 2896 emit_byte(0xc0 | encode); 2897 } 2898 2899 void Assembler::xorl(Register dst, int32_t imm32) { 2900 prefix(dst); 2901 emit_arith(0x81, 0xF0, dst, imm32); 2902 } 2903 2904 void Assembler::xorl(Register dst, Address src) { 2905 InstructionMark im(this); 2906 prefix(src, dst); 2907 emit_byte(0x33); 2908 emit_operand(dst, src); 2909 } 2910 2911 void Assembler::xorl(Register dst, Register src) { 2912 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2913 emit_arith(0x33, 0xC0, dst, src); 2914 } 2915 2916 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 2917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2918 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); 2919 emit_byte(0x57); 2920 emit_byte(0xC0 | encode); 2921 } 2922 2923 void Assembler::xorpd(XMMRegister dst, Address src) { 2924 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2925 InstructionMark im(this); 2926 simd_prefix(dst, dst, src, VEX_SIMD_66); 2927 emit_byte(0x57); 2928 emit_operand(dst, src); 2929 } 2930 2931 2932 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 2933 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2934 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); 2935 emit_byte(0x57); 2936 emit_byte(0xC0 | encode); 2937 } 2938 2939 void Assembler::xorps(XMMRegister dst, Address src) { 2940 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2941 InstructionMark im(this); 2942 simd_prefix(dst, dst, src, VEX_SIMD_NONE); 2943 emit_byte(0x57); 2944 emit_operand(dst, src); 2945 } 2946 2947 // AVX 3-operands non destructive source instructions (encoded with VEX prefix) 2948 2949 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 2950 assert(VM_Version::supports_avx(), ""); 2951 InstructionMark im(this); 2952 vex_prefix(dst, nds, src, VEX_SIMD_F2); 2953 emit_byte(0x58); 2954 emit_operand(dst, src); 2955 } 2956 2957 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 2958 assert(VM_Version::supports_avx(), ""); 2959 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); 2960 emit_byte(0x58); 2961 emit_byte(0xC0 | encode); 2962 } 2963 2964 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 2965 assert(VM_Version::supports_avx(), ""); 2966 InstructionMark im(this); 2967 vex_prefix(dst, nds, src, VEX_SIMD_F3); 2968 emit_byte(0x58); 2969 emit_operand(dst, src); 2970 } 2971 2972 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 2973 assert(VM_Version::supports_avx(), ""); 2974 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); 2975 emit_byte(0x58); 2976 emit_byte(0xC0 | encode); 2977 } 2978 2979 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) { 2980 assert(VM_Version::supports_avx(), ""); 2981 InstructionMark im(this); 2982 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector 2983 emit_byte(0x54); 2984 emit_operand(dst, src); 2985 } 2986 2987 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) { 2988 assert(VM_Version::supports_avx(), ""); 2989 InstructionMark im(this); 2990 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector 2991 emit_byte(0x54); 2992 emit_operand(dst, src); 2993 } 2994 2995 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 2996 assert(VM_Version::supports_avx(), ""); 2997 InstructionMark im(this); 2998 vex_prefix(dst, nds, src, VEX_SIMD_F2); 2999 emit_byte(0x5E); 3000 emit_operand(dst, src); 3001 } 3002 3003 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3004 assert(VM_Version::supports_avx(), ""); 3005 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); 3006 emit_byte(0x5E); 3007 emit_byte(0xC0 | encode); 3008 } 3009 3010 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 3011 assert(VM_Version::supports_avx(), ""); 3012 InstructionMark im(this); 3013 vex_prefix(dst, nds, src, VEX_SIMD_F3); 3014 emit_byte(0x5E); 3015 emit_operand(dst, src); 3016 } 3017 3018 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3019 assert(VM_Version::supports_avx(), ""); 3020 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); 3021 emit_byte(0x5E); 3022 emit_byte(0xC0 | encode); 3023 } 3024 3025 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 3026 assert(VM_Version::supports_avx(), ""); 3027 InstructionMark im(this); 3028 vex_prefix(dst, nds, src, VEX_SIMD_F2); 3029 emit_byte(0x59); 3030 emit_operand(dst, src); 3031 } 3032 3033 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3034 assert(VM_Version::supports_avx(), ""); 3035 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); 3036 emit_byte(0x59); 3037 emit_byte(0xC0 | encode); 3038 } 3039 3040 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 3041 InstructionMark im(this); 3042 vex_prefix(dst, nds, src, VEX_SIMD_F3); 3043 emit_byte(0x59); 3044 emit_operand(dst, src); 3045 } 3046 3047 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3048 assert(VM_Version::supports_avx(), ""); 3049 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); 3050 emit_byte(0x59); 3051 emit_byte(0xC0 | encode); 3052 } 3053 3054 3055 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 3056 assert(VM_Version::supports_avx(), ""); 3057 InstructionMark im(this); 3058 vex_prefix(dst, nds, src, VEX_SIMD_F2); 3059 emit_byte(0x5C); 3060 emit_operand(dst, src); 3061 } 3062 3063 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3064 assert(VM_Version::supports_avx(), ""); 3065 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); 3066 emit_byte(0x5C); 3067 emit_byte(0xC0 | encode); 3068 } 3069 3070 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 3071 assert(VM_Version::supports_avx(), ""); 3072 InstructionMark im(this); 3073 vex_prefix(dst, nds, src, VEX_SIMD_F3); 3074 emit_byte(0x5C); 3075 emit_operand(dst, src); 3076 } 3077 3078 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3079 assert(VM_Version::supports_avx(), ""); 3080 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); 3081 emit_byte(0x5C); 3082 emit_byte(0xC0 | encode); 3083 } 3084 3085 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) { 3086 assert(VM_Version::supports_avx(), ""); 3087 InstructionMark im(this); 3088 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector 3089 emit_byte(0x57); 3090 emit_operand(dst, src); 3091 } 3092 3093 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { 3094 assert(VM_Version::supports_avx(), ""); 3095 InstructionMark im(this); 3096 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector 3097 emit_byte(0x57); 3098 emit_operand(dst, src); 3099 } 3100 3101 3102 #ifndef _LP64 3103 // 32bit only pieces of the assembler 3104 3105 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 3106 // NO PREFIX AS NEVER 64BIT 3107 InstructionMark im(this); 3108 emit_byte(0x81); 3109 emit_byte(0xF8 | src1->encoding()); 3110 emit_data(imm32, rspec, 0); 3111 } 3112 3113 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 3114 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 3115 InstructionMark im(this); 3116 emit_byte(0x81); 3117 emit_operand(rdi, src1); 3118 emit_data(imm32, rspec, 0); 3119 } 3120 3121 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 3122 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 3123 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 3124 void Assembler::cmpxchg8(Address adr) { 3125 InstructionMark im(this); 3126 emit_byte(0x0F); 3127 emit_byte(0xc7); 3128 emit_operand(rcx, adr); 3129 } 3130 3131 void Assembler::decl(Register dst) { 3132 // Don't use it directly. Use MacroAssembler::decrementl() instead. 3133 emit_byte(0x48 | dst->encoding()); 3134 } 3135 3136 #endif // _LP64 3137 3138 // 64bit typically doesn't use the x87 but needs to for the trig funcs 3139 3140 void Assembler::fabs() { 3141 emit_byte(0xD9); 3142 emit_byte(0xE1); 3143 } 3144 3145 void Assembler::fadd(int i) { 3146 emit_farith(0xD8, 0xC0, i); 3147 } 3148 3149 void Assembler::fadd_d(Address src) { 3150 InstructionMark im(this); 3151 emit_byte(0xDC); 3152 emit_operand32(rax, src); 3153 } 3154 3155 void Assembler::fadd_s(Address src) { 3156 InstructionMark im(this); 3157 emit_byte(0xD8); 3158 emit_operand32(rax, src); 3159 } 3160 3161 void Assembler::fadda(int i) { 3162 emit_farith(0xDC, 0xC0, i); 3163 } 3164 3165 void Assembler::faddp(int i) { 3166 emit_farith(0xDE, 0xC0, i); 3167 } 3168 3169 void Assembler::fchs() { 3170 emit_byte(0xD9); 3171 emit_byte(0xE0); 3172 } 3173 3174 void Assembler::fcom(int i) { 3175 emit_farith(0xD8, 0xD0, i); 3176 } 3177 3178 void Assembler::fcomp(int i) { 3179 emit_farith(0xD8, 0xD8, i); 3180 } 3181 3182 void Assembler::fcomp_d(Address src) { 3183 InstructionMark im(this); 3184 emit_byte(0xDC); 3185 emit_operand32(rbx, src); 3186 } 3187 3188 void Assembler::fcomp_s(Address src) { 3189 InstructionMark im(this); 3190 emit_byte(0xD8); 3191 emit_operand32(rbx, src); 3192 } 3193 3194 void Assembler::fcompp() { 3195 emit_byte(0xDE); 3196 emit_byte(0xD9); 3197 } 3198 3199 void Assembler::fcos() { 3200 emit_byte(0xD9); 3201 emit_byte(0xFF); 3202 } 3203 3204 void Assembler::fdecstp() { 3205 emit_byte(0xD9); 3206 emit_byte(0xF6); 3207 } 3208 3209 void Assembler::fdiv(int i) { 3210 emit_farith(0xD8, 0xF0, i); 3211 } 3212 3213 void Assembler::fdiv_d(Address src) { 3214 InstructionMark im(this); 3215 emit_byte(0xDC); 3216 emit_operand32(rsi, src); 3217 } 3218 3219 void Assembler::fdiv_s(Address src) { 3220 InstructionMark im(this); 3221 emit_byte(0xD8); 3222 emit_operand32(rsi, src); 3223 } 3224 3225 void Assembler::fdiva(int i) { 3226 emit_farith(0xDC, 0xF8, i); 3227 } 3228 3229 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 3230 // is erroneous for some of the floating-point instructions below. 3231 3232 void Assembler::fdivp(int i) { 3233 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 3234 } 3235 3236 void Assembler::fdivr(int i) { 3237 emit_farith(0xD8, 0xF8, i); 3238 } 3239 3240 void Assembler::fdivr_d(Address src) { 3241 InstructionMark im(this); 3242 emit_byte(0xDC); 3243 emit_operand32(rdi, src); 3244 } 3245 3246 void Assembler::fdivr_s(Address src) { 3247 InstructionMark im(this); 3248 emit_byte(0xD8); 3249 emit_operand32(rdi, src); 3250 } 3251 3252 void Assembler::fdivra(int i) { 3253 emit_farith(0xDC, 0xF0, i); 3254 } 3255 3256 void Assembler::fdivrp(int i) { 3257 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 3258 } 3259 3260 void Assembler::ffree(int i) { 3261 emit_farith(0xDD, 0xC0, i); 3262 } 3263 3264 void Assembler::fild_d(Address adr) { 3265 InstructionMark im(this); 3266 emit_byte(0xDF); 3267 emit_operand32(rbp, adr); 3268 } 3269 3270 void Assembler::fild_s(Address adr) { 3271 InstructionMark im(this); 3272 emit_byte(0xDB); 3273 emit_operand32(rax, adr); 3274 } 3275 3276 void Assembler::fincstp() { 3277 emit_byte(0xD9); 3278 emit_byte(0xF7); 3279 } 3280 3281 void Assembler::finit() { 3282 emit_byte(0x9B); 3283 emit_byte(0xDB); 3284 emit_byte(0xE3); 3285 } 3286 3287 void Assembler::fist_s(Address adr) { 3288 InstructionMark im(this); 3289 emit_byte(0xDB); 3290 emit_operand32(rdx, adr); 3291 } 3292 3293 void Assembler::fistp_d(Address adr) { 3294 InstructionMark im(this); 3295 emit_byte(0xDF); 3296 emit_operand32(rdi, adr); 3297 } 3298 3299 void Assembler::fistp_s(Address adr) { 3300 InstructionMark im(this); 3301 emit_byte(0xDB); 3302 emit_operand32(rbx, adr); 3303 } 3304 3305 void Assembler::fld1() { 3306 emit_byte(0xD9); 3307 emit_byte(0xE8); 3308 } 3309 3310 void Assembler::fld_d(Address adr) { 3311 InstructionMark im(this); 3312 emit_byte(0xDD); 3313 emit_operand32(rax, adr); 3314 } 3315 3316 void Assembler::fld_s(Address adr) { 3317 InstructionMark im(this); 3318 emit_byte(0xD9); 3319 emit_operand32(rax, adr); 3320 } 3321 3322 3323 void Assembler::fld_s(int index) { 3324 emit_farith(0xD9, 0xC0, index); 3325 } 3326 3327 void Assembler::fld_x(Address adr) { 3328 InstructionMark im(this); 3329 emit_byte(0xDB); 3330 emit_operand32(rbp, adr); 3331 } 3332 3333 void Assembler::fldcw(Address src) { 3334 InstructionMark im(this); 3335 emit_byte(0xd9); 3336 emit_operand32(rbp, src); 3337 } 3338 3339 void Assembler::fldenv(Address src) { 3340 InstructionMark im(this); 3341 emit_byte(0xD9); 3342 emit_operand32(rsp, src); 3343 } 3344 3345 void Assembler::fldlg2() { 3346 emit_byte(0xD9); 3347 emit_byte(0xEC); 3348 } 3349 3350 void Assembler::fldln2() { 3351 emit_byte(0xD9); 3352 emit_byte(0xED); 3353 } 3354 3355 void Assembler::fldz() { 3356 emit_byte(0xD9); 3357 emit_byte(0xEE); 3358 } 3359 3360 void Assembler::flog() { 3361 fldln2(); 3362 fxch(); 3363 fyl2x(); 3364 } 3365 3366 void Assembler::flog10() { 3367 fldlg2(); 3368 fxch(); 3369 fyl2x(); 3370 } 3371 3372 void Assembler::fmul(int i) { 3373 emit_farith(0xD8, 0xC8, i); 3374 } 3375 3376 void Assembler::fmul_d(Address src) { 3377 InstructionMark im(this); 3378 emit_byte(0xDC); 3379 emit_operand32(rcx, src); 3380 } 3381 3382 void Assembler::fmul_s(Address src) { 3383 InstructionMark im(this); 3384 emit_byte(0xD8); 3385 emit_operand32(rcx, src); 3386 } 3387 3388 void Assembler::fmula(int i) { 3389 emit_farith(0xDC, 0xC8, i); 3390 } 3391 3392 void Assembler::fmulp(int i) { 3393 emit_farith(0xDE, 0xC8, i); 3394 } 3395 3396 void Assembler::fnsave(Address dst) { 3397 InstructionMark im(this); 3398 emit_byte(0xDD); 3399 emit_operand32(rsi, dst); 3400 } 3401 3402 void Assembler::fnstcw(Address src) { 3403 InstructionMark im(this); 3404 emit_byte(0x9B); 3405 emit_byte(0xD9); 3406 emit_operand32(rdi, src); 3407 } 3408 3409 void Assembler::fnstsw_ax() { 3410 emit_byte(0xdF); 3411 emit_byte(0xE0); 3412 } 3413 3414 void Assembler::fprem() { 3415 emit_byte(0xD9); 3416 emit_byte(0xF8); 3417 } 3418 3419 void Assembler::fprem1() { 3420 emit_byte(0xD9); 3421 emit_byte(0xF5); 3422 } 3423 3424 void Assembler::frstor(Address src) { 3425 InstructionMark im(this); 3426 emit_byte(0xDD); 3427 emit_operand32(rsp, src); 3428 } 3429 3430 void Assembler::fsin() { 3431 emit_byte(0xD9); 3432 emit_byte(0xFE); 3433 } 3434 3435 void Assembler::fsqrt() { 3436 emit_byte(0xD9); 3437 emit_byte(0xFA); 3438 } 3439 3440 void Assembler::fst_d(Address adr) { 3441 InstructionMark im(this); 3442 emit_byte(0xDD); 3443 emit_operand32(rdx, adr); 3444 } 3445 3446 void Assembler::fst_s(Address adr) { 3447 InstructionMark im(this); 3448 emit_byte(0xD9); 3449 emit_operand32(rdx, adr); 3450 } 3451 3452 void Assembler::fstp_d(Address adr) { 3453 InstructionMark im(this); 3454 emit_byte(0xDD); 3455 emit_operand32(rbx, adr); 3456 } 3457 3458 void Assembler::fstp_d(int index) { 3459 emit_farith(0xDD, 0xD8, index); 3460 } 3461 3462 void Assembler::fstp_s(Address adr) { 3463 InstructionMark im(this); 3464 emit_byte(0xD9); 3465 emit_operand32(rbx, adr); 3466 } 3467 3468 void Assembler::fstp_x(Address adr) { 3469 InstructionMark im(this); 3470 emit_byte(0xDB); 3471 emit_operand32(rdi, adr); 3472 } 3473 3474 void Assembler::fsub(int i) { 3475 emit_farith(0xD8, 0xE0, i); 3476 } 3477 3478 void Assembler::fsub_d(Address src) { 3479 InstructionMark im(this); 3480 emit_byte(0xDC); 3481 emit_operand32(rsp, src); 3482 } 3483 3484 void Assembler::fsub_s(Address src) { 3485 InstructionMark im(this); 3486 emit_byte(0xD8); 3487 emit_operand32(rsp, src); 3488 } 3489 3490 void Assembler::fsuba(int i) { 3491 emit_farith(0xDC, 0xE8, i); 3492 } 3493 3494 void Assembler::fsubp(int i) { 3495 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 3496 } 3497 3498 void Assembler::fsubr(int i) { 3499 emit_farith(0xD8, 0xE8, i); 3500 } 3501 3502 void Assembler::fsubr_d(Address src) { 3503 InstructionMark im(this); 3504 emit_byte(0xDC); 3505 emit_operand32(rbp, src); 3506 } 3507 3508 void Assembler::fsubr_s(Address src) { 3509 InstructionMark im(this); 3510 emit_byte(0xD8); 3511 emit_operand32(rbp, src); 3512 } 3513 3514 void Assembler::fsubra(int i) { 3515 emit_farith(0xDC, 0xE0, i); 3516 } 3517 3518 void Assembler::fsubrp(int i) { 3519 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 3520 } 3521 3522 void Assembler::ftan() { 3523 emit_byte(0xD9); 3524 emit_byte(0xF2); 3525 emit_byte(0xDD); 3526 emit_byte(0xD8); 3527 } 3528 3529 void Assembler::ftst() { 3530 emit_byte(0xD9); 3531 emit_byte(0xE4); 3532 } 3533 3534 void Assembler::fucomi(int i) { 3535 // make sure the instruction is supported (introduced for P6, together with cmov) 3536 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 3537 emit_farith(0xDB, 0xE8, i); 3538 } 3539 3540 void Assembler::fucomip(int i) { 3541 // make sure the instruction is supported (introduced for P6, together with cmov) 3542 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 3543 emit_farith(0xDF, 0xE8, i); 3544 } 3545 3546 void Assembler::fwait() { 3547 emit_byte(0x9B); 3548 } 3549 3550 void Assembler::fxch(int i) { 3551 emit_farith(0xD9, 0xC8, i); 3552 } 3553 3554 void Assembler::fyl2x() { 3555 emit_byte(0xD9); 3556 emit_byte(0xF1); 3557 } 3558 3559 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 3560 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 3561 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 3562 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 3563 3564 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 3565 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 3566 if (pre > 0) { 3567 emit_byte(simd_pre[pre]); 3568 } 3569 if (rex_w) { 3570 prefixq(adr, xreg); 3571 } else { 3572 prefix(adr, xreg); 3573 } 3574 if (opc > 0) { 3575 emit_byte(0x0F); 3576 int opc2 = simd_opc[opc]; 3577 if (opc2 > 0) { 3578 emit_byte(opc2); 3579 } 3580 } 3581 } 3582 3583 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 3584 if (pre > 0) { 3585 emit_byte(simd_pre[pre]); 3586 } 3587 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : 3588 prefix_and_encode(dst_enc, src_enc); 3589 if (opc > 0) { 3590 emit_byte(0x0F); 3591 int opc2 = simd_opc[opc]; 3592 if (opc2 > 0) { 3593 emit_byte(opc2); 3594 } 3595 } 3596 return encode; 3597 } 3598 3599 3600 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { 3601 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 3602 prefix(VEX_3bytes); 3603 3604 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 3605 byte1 = (~byte1) & 0xE0; 3606 byte1 |= opc; 3607 a_byte(byte1); 3608 3609 int byte2 = ((~nds_enc) & 0xf) << 3; 3610 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; 3611 emit_byte(byte2); 3612 } else { 3613 prefix(VEX_2bytes); 3614 3615 int byte1 = vex_r ? VEX_R : 0; 3616 byte1 = (~byte1) & 0x80; 3617 byte1 |= ((~nds_enc) & 0xf) << 3; 3618 byte1 |= (vector256 ? 4 : 0) | pre; 3619 emit_byte(byte1); 3620 } 3621 } 3622 3623 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ 3624 bool vex_r = (xreg_enc >= 8); 3625 bool vex_b = adr.base_needs_rex(); 3626 bool vex_x = adr.index_needs_rex(); 3627 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); 3628 } 3629 3630 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { 3631 bool vex_r = (dst_enc >= 8); 3632 bool vex_b = (src_enc >= 8); 3633 bool vex_x = false; 3634 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); 3635 return (((dst_enc & 7) << 3) | (src_enc & 7)); 3636 } 3637 3638 3639 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { 3640 if (UseAVX > 0) { 3641 int xreg_enc = xreg->encoding(); 3642 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 3643 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); 3644 } else { 3645 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 3646 rex_prefix(adr, xreg, pre, opc, rex_w); 3647 } 3648 } 3649 3650 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { 3651 int dst_enc = dst->encoding(); 3652 int src_enc = src->encoding(); 3653 if (UseAVX > 0) { 3654 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 3655 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); 3656 } else { 3657 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 3658 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); 3659 } 3660 } 3661 3662 #ifndef _LP64 3663 3664 void Assembler::incl(Register dst) { 3665 // Don't use it directly. Use MacroAssembler::incrementl() instead. 3666 emit_byte(0x40 | dst->encoding()); 3667 } 3668 3669 void Assembler::lea(Register dst, Address src) { 3670 leal(dst, src); 3671 } 3672 3673 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 3674 InstructionMark im(this); 3675 emit_byte(0xC7); 3676 emit_operand(rax, dst); 3677 emit_data((int)imm32, rspec, 0); 3678 } 3679 3680 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 3681 InstructionMark im(this); 3682 int encode = prefix_and_encode(dst->encoding()); 3683 emit_byte(0xB8 | encode); 3684 emit_data((int)imm32, rspec, 0); 3685 } 3686 3687 void Assembler::popa() { // 32bit 3688 emit_byte(0x61); 3689 } 3690 3691 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 3692 InstructionMark im(this); 3693 emit_byte(0x68); 3694 emit_data(imm32, rspec, 0); 3695 } 3696 3697 void Assembler::pusha() { // 32bit 3698 emit_byte(0x60); 3699 } 3700 3701 void Assembler::set_byte_if_not_zero(Register dst) { 3702 emit_byte(0x0F); 3703 emit_byte(0x95); 3704 emit_byte(0xE0 | dst->encoding()); 3705 } 3706 3707 void Assembler::shldl(Register dst, Register src) { 3708 emit_byte(0x0F); 3709 emit_byte(0xA5); 3710 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); 3711 } 3712 3713 void Assembler::shrdl(Register dst, Register src) { 3714 emit_byte(0x0F); 3715 emit_byte(0xAD); 3716 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); 3717 } 3718 3719 #else // LP64 3720 3721 void Assembler::set_byte_if_not_zero(Register dst) { 3722 int enc = prefix_and_encode(dst->encoding(), true); 3723 emit_byte(0x0F); 3724 emit_byte(0x95); 3725 emit_byte(0xE0 | enc); 3726 } 3727 3728 // 64bit only pieces of the assembler 3729 // This should only be used by 64bit instructions that can use rip-relative 3730 // it cannot be used by instructions that want an immediate value. 3731 3732 bool Assembler::reachable(AddressLiteral adr) { 3733 int64_t disp; 3734 // None will force a 64bit literal to the code stream. Likely a placeholder 3735 // for something that will be patched later and we need to certain it will 3736 // always be reachable. 3737 if (adr.reloc() == relocInfo::none) { 3738 return false; 3739 } 3740 if (adr.reloc() == relocInfo::internal_word_type) { 3741 // This should be rip relative and easily reachable. 3742 return true; 3743 } 3744 if (adr.reloc() == relocInfo::virtual_call_type || 3745 adr.reloc() == relocInfo::opt_virtual_call_type || 3746 adr.reloc() == relocInfo::static_call_type || 3747 adr.reloc() == relocInfo::static_stub_type ) { 3748 // This should be rip relative within the code cache and easily 3749 // reachable until we get huge code caches. (At which point 3750 // ic code is going to have issues). 3751 return true; 3752 } 3753 if (adr.reloc() != relocInfo::external_word_type && 3754 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 3755 adr.reloc() != relocInfo::poll_type && // relocs to identify them 3756 adr.reloc() != relocInfo::runtime_call_type ) { 3757 return false; 3758 } 3759 3760 // Stress the correction code 3761 if (ForceUnreachable) { 3762 // Must be runtimecall reloc, see if it is in the codecache 3763 // Flipping stuff in the codecache to be unreachable causes issues 3764 // with things like inline caches where the additional instructions 3765 // are not handled. 3766 if (CodeCache::find_blob(adr._target) == NULL) { 3767 return false; 3768 } 3769 } 3770 // For external_word_type/runtime_call_type if it is reachable from where we 3771 // are now (possibly a temp buffer) and where we might end up 3772 // anywhere in the codeCache then we are always reachable. 3773 // This would have to change if we ever save/restore shared code 3774 // to be more pessimistic. 3775 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 3776 if (!is_simm32(disp)) return false; 3777 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 3778 if (!is_simm32(disp)) return false; 3779 3780 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); 3781 3782 // Because rip relative is a disp + address_of_next_instruction and we 3783 // don't know the value of address_of_next_instruction we apply a fudge factor 3784 // to make sure we will be ok no matter the size of the instruction we get placed into. 3785 // We don't have to fudge the checks above here because they are already worst case. 3786 3787 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 3788 // + 4 because better safe than sorry. 3789 const int fudge = 12 + 4; 3790 if (disp < 0) { 3791 disp -= fudge; 3792 } else { 3793 disp += fudge; 3794 } 3795 return is_simm32(disp); 3796 } 3797 3798 // Check if the polling page is not reachable from the code cache using rip-relative 3799 // addressing. 3800 bool Assembler::is_polling_page_far() { 3801 intptr_t addr = (intptr_t)os::get_polling_page(); 3802 return ForceUnreachable || 3803 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 3804 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 3805 } 3806 3807 void Assembler::emit_data64(jlong data, 3808 relocInfo::relocType rtype, 3809 int format) { 3810 if (rtype == relocInfo::none) { 3811 emit_long64(data); 3812 } else { 3813 emit_data64(data, Relocation::spec_simple(rtype), format); 3814 } 3815 } 3816 3817 void Assembler::emit_data64(jlong data, 3818 RelocationHolder const& rspec, 3819 int format) { 3820 assert(imm_operand == 0, "default format must be immediate in this file"); 3821 assert(imm_operand == format, "must be immediate"); 3822 assert(inst_mark() != NULL, "must be inside InstructionMark"); 3823 // Do not use AbstractAssembler::relocate, which is not intended for 3824 // embedded words. Instead, relocate to the enclosing instruction. 3825 code_section()->relocate(inst_mark(), rspec, format); 3826 #ifdef ASSERT 3827 check_relocation(rspec, format); 3828 #endif 3829 emit_long64(data); 3830 } 3831 3832 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 3833 if (reg_enc >= 8) { 3834 prefix(REX_B); 3835 reg_enc -= 8; 3836 } else if (byteinst && reg_enc >= 4) { 3837 prefix(REX); 3838 } 3839 return reg_enc; 3840 } 3841 3842 int Assembler::prefixq_and_encode(int reg_enc) { 3843 if (reg_enc < 8) { 3844 prefix(REX_W); 3845 } else { 3846 prefix(REX_WB); 3847 reg_enc -= 8; 3848 } 3849 return reg_enc; 3850 } 3851 3852 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { 3853 if (dst_enc < 8) { 3854 if (src_enc >= 8) { 3855 prefix(REX_B); 3856 src_enc -= 8; 3857 } else if (byteinst && src_enc >= 4) { 3858 prefix(REX); 3859 } 3860 } else { 3861 if (src_enc < 8) { 3862 prefix(REX_R); 3863 } else { 3864 prefix(REX_RB); 3865 src_enc -= 8; 3866 } 3867 dst_enc -= 8; 3868 } 3869 return dst_enc << 3 | src_enc; 3870 } 3871 3872 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 3873 if (dst_enc < 8) { 3874 if (src_enc < 8) { 3875 prefix(REX_W); 3876 } else { 3877 prefix(REX_WB); 3878 src_enc -= 8; 3879 } 3880 } else { 3881 if (src_enc < 8) { 3882 prefix(REX_WR); 3883 } else { 3884 prefix(REX_WRB); 3885 src_enc -= 8; 3886 } 3887 dst_enc -= 8; 3888 } 3889 return dst_enc << 3 | src_enc; 3890 } 3891 3892 void Assembler::prefix(Register reg) { 3893 if (reg->encoding() >= 8) { 3894 prefix(REX_B); 3895 } 3896 } 3897 3898 void Assembler::prefix(Address adr) { 3899 if (adr.base_needs_rex()) { 3900 if (adr.index_needs_rex()) { 3901 prefix(REX_XB); 3902 } else { 3903 prefix(REX_B); 3904 } 3905 } else { 3906 if (adr.index_needs_rex()) { 3907 prefix(REX_X); 3908 } 3909 } 3910 } 3911 3912 void Assembler::prefixq(Address adr) { 3913 if (adr.base_needs_rex()) { 3914 if (adr.index_needs_rex()) { 3915 prefix(REX_WXB); 3916 } else { 3917 prefix(REX_WB); 3918 } 3919 } else { 3920 if (adr.index_needs_rex()) { 3921 prefix(REX_WX); 3922 } else { 3923 prefix(REX_W); 3924 } 3925 } 3926 } 3927 3928 3929 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 3930 if (reg->encoding() < 8) { 3931 if (adr.base_needs_rex()) { 3932 if (adr.index_needs_rex()) { 3933 prefix(REX_XB); 3934 } else { 3935 prefix(REX_B); 3936 } 3937 } else { 3938 if (adr.index_needs_rex()) { 3939 prefix(REX_X); 3940 } else if (byteinst && reg->encoding() >= 4 ) { 3941 prefix(REX); 3942 } 3943 } 3944 } else { 3945 if (adr.base_needs_rex()) { 3946 if (adr.index_needs_rex()) { 3947 prefix(REX_RXB); 3948 } else { 3949 prefix(REX_RB); 3950 } 3951 } else { 3952 if (adr.index_needs_rex()) { 3953 prefix(REX_RX); 3954 } else { 3955 prefix(REX_R); 3956 } 3957 } 3958 } 3959 } 3960 3961 void Assembler::prefixq(Address adr, Register src) { 3962 if (src->encoding() < 8) { 3963 if (adr.base_needs_rex()) { 3964 if (adr.index_needs_rex()) { 3965 prefix(REX_WXB); 3966 } else { 3967 prefix(REX_WB); 3968 } 3969 } else { 3970 if (adr.index_needs_rex()) { 3971 prefix(REX_WX); 3972 } else { 3973 prefix(REX_W); 3974 } 3975 } 3976 } else { 3977 if (adr.base_needs_rex()) { 3978 if (adr.index_needs_rex()) { 3979 prefix(REX_WRXB); 3980 } else { 3981 prefix(REX_WRB); 3982 } 3983 } else { 3984 if (adr.index_needs_rex()) { 3985 prefix(REX_WRX); 3986 } else { 3987 prefix(REX_WR); 3988 } 3989 } 3990 } 3991 } 3992 3993 void Assembler::prefix(Address adr, XMMRegister reg) { 3994 if (reg->encoding() < 8) { 3995 if (adr.base_needs_rex()) { 3996 if (adr.index_needs_rex()) { 3997 prefix(REX_XB); 3998 } else { 3999 prefix(REX_B); 4000 } 4001 } else { 4002 if (adr.index_needs_rex()) { 4003 prefix(REX_X); 4004 } 4005 } 4006 } else { 4007 if (adr.base_needs_rex()) { 4008 if (adr.index_needs_rex()) { 4009 prefix(REX_RXB); 4010 } else { 4011 prefix(REX_RB); 4012 } 4013 } else { 4014 if (adr.index_needs_rex()) { 4015 prefix(REX_RX); 4016 } else { 4017 prefix(REX_R); 4018 } 4019 } 4020 } 4021 } 4022 4023 void Assembler::prefixq(Address adr, XMMRegister src) { 4024 if (src->encoding() < 8) { 4025 if (adr.base_needs_rex()) { 4026 if (adr.index_needs_rex()) { 4027 prefix(REX_WXB); 4028 } else { 4029 prefix(REX_WB); 4030 } 4031 } else { 4032 if (adr.index_needs_rex()) { 4033 prefix(REX_WX); 4034 } else { 4035 prefix(REX_W); 4036 } 4037 } 4038 } else { 4039 if (adr.base_needs_rex()) { 4040 if (adr.index_needs_rex()) { 4041 prefix(REX_WRXB); 4042 } else { 4043 prefix(REX_WRB); 4044 } 4045 } else { 4046 if (adr.index_needs_rex()) { 4047 prefix(REX_WRX); 4048 } else { 4049 prefix(REX_WR); 4050 } 4051 } 4052 } 4053 } 4054 4055 void Assembler::adcq(Register dst, int32_t imm32) { 4056 (void) prefixq_and_encode(dst->encoding()); 4057 emit_arith(0x81, 0xD0, dst, imm32); 4058 } 4059 4060 void Assembler::adcq(Register dst, Address src) { 4061 InstructionMark im(this); 4062 prefixq(src, dst); 4063 emit_byte(0x13); 4064 emit_operand(dst, src); 4065 } 4066 4067 void Assembler::adcq(Register dst, Register src) { 4068 (int) prefixq_and_encode(dst->encoding(), src->encoding()); 4069 emit_arith(0x13, 0xC0, dst, src); 4070 } 4071 4072 void Assembler::addq(Address dst, int32_t imm32) { 4073 InstructionMark im(this); 4074 prefixq(dst); 4075 emit_arith_operand(0x81, rax, dst,imm32); 4076 } 4077 4078 void Assembler::addq(Address dst, Register src) { 4079 InstructionMark im(this); 4080 prefixq(dst, src); 4081 emit_byte(0x01); 4082 emit_operand(src, dst); 4083 } 4084 4085 void Assembler::addq(Register dst, int32_t imm32) { 4086 (void) prefixq_and_encode(dst->encoding()); 4087 emit_arith(0x81, 0xC0, dst, imm32); 4088 } 4089 4090 void Assembler::addq(Register dst, Address src) { 4091 InstructionMark im(this); 4092 prefixq(src, dst); 4093 emit_byte(0x03); 4094 emit_operand(dst, src); 4095 } 4096 4097 void Assembler::addq(Register dst, Register src) { 4098 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4099 emit_arith(0x03, 0xC0, dst, src); 4100 } 4101 4102 void Assembler::andq(Address dst, int32_t imm32) { 4103 InstructionMark im(this); 4104 prefixq(dst); 4105 emit_byte(0x81); 4106 emit_operand(rsp, dst, 4); 4107 emit_long(imm32); 4108 } 4109 4110 void Assembler::andq(Register dst, int32_t imm32) { 4111 (void) prefixq_and_encode(dst->encoding()); 4112 emit_arith(0x81, 0xE0, dst, imm32); 4113 } 4114 4115 void Assembler::andq(Register dst, Address src) { 4116 InstructionMark im(this); 4117 prefixq(src, dst); 4118 emit_byte(0x23); 4119 emit_operand(dst, src); 4120 } 4121 4122 void Assembler::andq(Register dst, Register src) { 4123 (int) prefixq_and_encode(dst->encoding(), src->encoding()); 4124 emit_arith(0x23, 0xC0, dst, src); 4125 } 4126 4127 void Assembler::bsfq(Register dst, Register src) { 4128 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4129 emit_byte(0x0F); 4130 emit_byte(0xBC); 4131 emit_byte(0xC0 | encode); 4132 } 4133 4134 void Assembler::bsrq(Register dst, Register src) { 4135 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); 4136 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4137 emit_byte(0x0F); 4138 emit_byte(0xBD); 4139 emit_byte(0xC0 | encode); 4140 } 4141 4142 void Assembler::bswapq(Register reg) { 4143 int encode = prefixq_and_encode(reg->encoding()); 4144 emit_byte(0x0F); 4145 emit_byte(0xC8 | encode); 4146 } 4147 4148 void Assembler::cdqq() { 4149 prefix(REX_W); 4150 emit_byte(0x99); 4151 } 4152 4153 void Assembler::clflush(Address adr) { 4154 prefix(adr); 4155 emit_byte(0x0F); 4156 emit_byte(0xAE); 4157 emit_operand(rdi, adr); 4158 } 4159 4160 void Assembler::cmovq(Condition cc, Register dst, Register src) { 4161 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4162 emit_byte(0x0F); 4163 emit_byte(0x40 | cc); 4164 emit_byte(0xC0 | encode); 4165 } 4166 4167 void Assembler::cmovq(Condition cc, Register dst, Address src) { 4168 InstructionMark im(this); 4169 prefixq(src, dst); 4170 emit_byte(0x0F); 4171 emit_byte(0x40 | cc); 4172 emit_operand(dst, src); 4173 } 4174 4175 void Assembler::cmpq(Address dst, int32_t imm32) { 4176 InstructionMark im(this); 4177 prefixq(dst); 4178 emit_byte(0x81); 4179 emit_operand(rdi, dst, 4); 4180 emit_long(imm32); 4181 } 4182 4183 void Assembler::cmpq(Register dst, int32_t imm32) { 4184 (void) prefixq_and_encode(dst->encoding()); 4185 emit_arith(0x81, 0xF8, dst, imm32); 4186 } 4187 4188 void Assembler::cmpq(Address dst, Register src) { 4189 InstructionMark im(this); 4190 prefixq(dst, src); 4191 emit_byte(0x3B); 4192 emit_operand(src, dst); 4193 } 4194 4195 void Assembler::cmpq(Register dst, Register src) { 4196 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4197 emit_arith(0x3B, 0xC0, dst, src); 4198 } 4199 4200 void Assembler::cmpq(Register dst, Address src) { 4201 InstructionMark im(this); 4202 prefixq(src, dst); 4203 emit_byte(0x3B); 4204 emit_operand(dst, src); 4205 } 4206 4207 void Assembler::cmpxchgq(Register reg, Address adr) { 4208 InstructionMark im(this); 4209 prefixq(adr, reg); 4210 emit_byte(0x0F); 4211 emit_byte(0xB1); 4212 emit_operand(reg, adr); 4213 } 4214 4215 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 4216 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4217 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); 4218 emit_byte(0x2A); 4219 emit_byte(0xC0 | encode); 4220 } 4221 4222 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 4223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4224 InstructionMark im(this); 4225 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); 4226 emit_byte(0x2A); 4227 emit_operand(dst, src); 4228 } 4229 4230 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 4231 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4232 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); 4233 emit_byte(0x2A); 4234 emit_byte(0xC0 | encode); 4235 } 4236 4237 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 4238 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4239 InstructionMark im(this); 4240 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); 4241 emit_byte(0x2A); 4242 emit_operand(dst, src); 4243 } 4244 4245 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 4246 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4247 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); 4248 emit_byte(0x2C); 4249 emit_byte(0xC0 | encode); 4250 } 4251 4252 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 4253 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4254 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); 4255 emit_byte(0x2C); 4256 emit_byte(0xC0 | encode); 4257 } 4258 4259 void Assembler::decl(Register dst) { 4260 // Don't use it directly. Use MacroAssembler::decrementl() instead. 4261 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 4262 int encode = prefix_and_encode(dst->encoding()); 4263 emit_byte(0xFF); 4264 emit_byte(0xC8 | encode); 4265 } 4266 4267 void Assembler::decq(Register dst) { 4268 // Don't use it directly. Use MacroAssembler::decrementq() instead. 4269 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 4270 int encode = prefixq_and_encode(dst->encoding()); 4271 emit_byte(0xFF); 4272 emit_byte(0xC8 | encode); 4273 } 4274 4275 void Assembler::decq(Address dst) { 4276 // Don't use it directly. Use MacroAssembler::decrementq() instead. 4277 InstructionMark im(this); 4278 prefixq(dst); 4279 emit_byte(0xFF); 4280 emit_operand(rcx, dst); 4281 } 4282 4283 void Assembler::fxrstor(Address src) { 4284 prefixq(src); 4285 emit_byte(0x0F); 4286 emit_byte(0xAE); 4287 emit_operand(as_Register(1), src); 4288 } 4289 4290 void Assembler::fxsave(Address dst) { 4291 prefixq(dst); 4292 emit_byte(0x0F); 4293 emit_byte(0xAE); 4294 emit_operand(as_Register(0), dst); 4295 } 4296 4297 void Assembler::idivq(Register src) { 4298 int encode = prefixq_and_encode(src->encoding()); 4299 emit_byte(0xF7); 4300 emit_byte(0xF8 | encode); 4301 } 4302 4303 void Assembler::imulq(Register dst, Register src) { 4304 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4305 emit_byte(0x0F); 4306 emit_byte(0xAF); 4307 emit_byte(0xC0 | encode); 4308 } 4309 4310 void Assembler::imulq(Register dst, Register src, int value) { 4311 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4312 if (is8bit(value)) { 4313 emit_byte(0x6B); 4314 emit_byte(0xC0 | encode); 4315 emit_byte(value & 0xFF); 4316 } else { 4317 emit_byte(0x69); 4318 emit_byte(0xC0 | encode); 4319 emit_long(value); 4320 } 4321 } 4322 4323 void Assembler::incl(Register dst) { 4324 // Don't use it directly. Use MacroAssembler::incrementl() instead. 4325 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 4326 int encode = prefix_and_encode(dst->encoding()); 4327 emit_byte(0xFF); 4328 emit_byte(0xC0 | encode); 4329 } 4330 4331 void Assembler::incq(Register dst) { 4332 // Don't use it directly. Use MacroAssembler::incrementq() instead. 4333 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 4334 int encode = prefixq_and_encode(dst->encoding()); 4335 emit_byte(0xFF); 4336 emit_byte(0xC0 | encode); 4337 } 4338 4339 void Assembler::incq(Address dst) { 4340 // Don't use it directly. Use MacroAssembler::incrementq() instead. 4341 InstructionMark im(this); 4342 prefixq(dst); 4343 emit_byte(0xFF); 4344 emit_operand(rax, dst); 4345 } 4346 4347 void Assembler::lea(Register dst, Address src) { 4348 leaq(dst, src); 4349 } 4350 4351 void Assembler::leaq(Register dst, Address src) { 4352 InstructionMark im(this); 4353 prefixq(src, dst); 4354 emit_byte(0x8D); 4355 emit_operand(dst, src); 4356 } 4357 4358 void Assembler::mov64(Register dst, int64_t imm64) { 4359 InstructionMark im(this); 4360 int encode = prefixq_and_encode(dst->encoding()); 4361 emit_byte(0xB8 | encode); 4362 emit_long64(imm64); 4363 } 4364 4365 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 4366 InstructionMark im(this); 4367 int encode = prefixq_and_encode(dst->encoding()); 4368 emit_byte(0xB8 | encode); 4369 emit_data64(imm64, rspec); 4370 } 4371 4372 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 4373 InstructionMark im(this); 4374 int encode = prefix_and_encode(dst->encoding()); 4375 emit_byte(0xB8 | encode); 4376 emit_data((int)imm32, rspec, narrow_oop_operand); 4377 } 4378 4379 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 4380 InstructionMark im(this); 4381 prefix(dst); 4382 emit_byte(0xC7); 4383 emit_operand(rax, dst, 4); 4384 emit_data((int)imm32, rspec, narrow_oop_operand); 4385 } 4386 4387 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 4388 InstructionMark im(this); 4389 int encode = prefix_and_encode(src1->encoding()); 4390 emit_byte(0x81); 4391 emit_byte(0xF8 | encode); 4392 emit_data((int)imm32, rspec, narrow_oop_operand); 4393 } 4394 4395 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 4396 InstructionMark im(this); 4397 prefix(src1); 4398 emit_byte(0x81); 4399 emit_operand(rax, src1, 4); 4400 emit_data((int)imm32, rspec, narrow_oop_operand); 4401 } 4402 4403 void Assembler::lzcntq(Register dst, Register src) { 4404 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 4405 emit_byte(0xF3); 4406 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4407 emit_byte(0x0F); 4408 emit_byte(0xBD); 4409 emit_byte(0xC0 | encode); 4410 } 4411 4412 void Assembler::movdq(XMMRegister dst, Register src) { 4413 // table D-1 says MMX/SSE2 4414 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4415 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); 4416 emit_byte(0x6E); 4417 emit_byte(0xC0 | encode); 4418 } 4419 4420 void Assembler::movdq(Register dst, XMMRegister src) { 4421 // table D-1 says MMX/SSE2 4422 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4423 // swap src/dst to get correct prefix 4424 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); 4425 emit_byte(0x7E); 4426 emit_byte(0xC0 | encode); 4427 } 4428 4429 void Assembler::movq(Register dst, Register src) { 4430 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4431 emit_byte(0x8B); 4432 emit_byte(0xC0 | encode); 4433 } 4434 4435 void Assembler::movq(Register dst, Address src) { 4436 InstructionMark im(this); 4437 prefixq(src, dst); 4438 emit_byte(0x8B); 4439 emit_operand(dst, src); 4440 } 4441 4442 void Assembler::movq(Address dst, Register src) { 4443 InstructionMark im(this); 4444 prefixq(dst, src); 4445 emit_byte(0x89); 4446 emit_operand(src, dst); 4447 } 4448 4449 void Assembler::movsbq(Register dst, Address src) { 4450 InstructionMark im(this); 4451 prefixq(src, dst); 4452 emit_byte(0x0F); 4453 emit_byte(0xBE); 4454 emit_operand(dst, src); 4455 } 4456 4457 void Assembler::movsbq(Register dst, Register src) { 4458 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4459 emit_byte(0x0F); 4460 emit_byte(0xBE); 4461 emit_byte(0xC0 | encode); 4462 } 4463 4464 void Assembler::movslq(Register dst, int32_t imm32) { 4465 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 4466 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 4467 // as a result we shouldn't use until tested at runtime... 4468 ShouldNotReachHere(); 4469 InstructionMark im(this); 4470 int encode = prefixq_and_encode(dst->encoding()); 4471 emit_byte(0xC7 | encode); 4472 emit_long(imm32); 4473 } 4474 4475 void Assembler::movslq(Address dst, int32_t imm32) { 4476 assert(is_simm32(imm32), "lost bits"); 4477 InstructionMark im(this); 4478 prefixq(dst); 4479 emit_byte(0xC7); 4480 emit_operand(rax, dst, 4); 4481 emit_long(imm32); 4482 } 4483 4484 void Assembler::movslq(Register dst, Address src) { 4485 InstructionMark im(this); 4486 prefixq(src, dst); 4487 emit_byte(0x63); 4488 emit_operand(dst, src); 4489 } 4490 4491 void Assembler::movslq(Register dst, Register src) { 4492 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4493 emit_byte(0x63); 4494 emit_byte(0xC0 | encode); 4495 } 4496 4497 void Assembler::movswq(Register dst, Address src) { 4498 InstructionMark im(this); 4499 prefixq(src, dst); 4500 emit_byte(0x0F); 4501 emit_byte(0xBF); 4502 emit_operand(dst, src); 4503 } 4504 4505 void Assembler::movswq(Register dst, Register src) { 4506 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4507 emit_byte(0x0F); 4508 emit_byte(0xBF); 4509 emit_byte(0xC0 | encode); 4510 } 4511 4512 void Assembler::movzbq(Register dst, Address src) { 4513 InstructionMark im(this); 4514 prefixq(src, dst); 4515 emit_byte(0x0F); 4516 emit_byte(0xB6); 4517 emit_operand(dst, src); 4518 } 4519 4520 void Assembler::movzbq(Register dst, Register src) { 4521 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4522 emit_byte(0x0F); 4523 emit_byte(0xB6); 4524 emit_byte(0xC0 | encode); 4525 } 4526 4527 void Assembler::movzwq(Register dst, Address src) { 4528 InstructionMark im(this); 4529 prefixq(src, dst); 4530 emit_byte(0x0F); 4531 emit_byte(0xB7); 4532 emit_operand(dst, src); 4533 } 4534 4535 void Assembler::movzwq(Register dst, Register src) { 4536 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4537 emit_byte(0x0F); 4538 emit_byte(0xB7); 4539 emit_byte(0xC0 | encode); 4540 } 4541 4542 void Assembler::negq(Register dst) { 4543 int encode = prefixq_and_encode(dst->encoding()); 4544 emit_byte(0xF7); 4545 emit_byte(0xD8 | encode); 4546 } 4547 4548 void Assembler::notq(Register dst) { 4549 int encode = prefixq_and_encode(dst->encoding()); 4550 emit_byte(0xF7); 4551 emit_byte(0xD0 | encode); 4552 } 4553 4554 void Assembler::orq(Address dst, int32_t imm32) { 4555 InstructionMark im(this); 4556 prefixq(dst); 4557 emit_byte(0x81); 4558 emit_operand(rcx, dst, 4); 4559 emit_long(imm32); 4560 } 4561 4562 void Assembler::orq(Register dst, int32_t imm32) { 4563 (void) prefixq_and_encode(dst->encoding()); 4564 emit_arith(0x81, 0xC8, dst, imm32); 4565 } 4566 4567 void Assembler::orq(Register dst, Address src) { 4568 InstructionMark im(this); 4569 prefixq(src, dst); 4570 emit_byte(0x0B); 4571 emit_operand(dst, src); 4572 } 4573 4574 void Assembler::orq(Register dst, Register src) { 4575 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4576 emit_arith(0x0B, 0xC0, dst, src); 4577 } 4578 4579 void Assembler::popa() { // 64bit 4580 movq(r15, Address(rsp, 0)); 4581 movq(r14, Address(rsp, wordSize)); 4582 movq(r13, Address(rsp, 2 * wordSize)); 4583 movq(r12, Address(rsp, 3 * wordSize)); 4584 movq(r11, Address(rsp, 4 * wordSize)); 4585 movq(r10, Address(rsp, 5 * wordSize)); 4586 movq(r9, Address(rsp, 6 * wordSize)); 4587 movq(r8, Address(rsp, 7 * wordSize)); 4588 movq(rdi, Address(rsp, 8 * wordSize)); 4589 movq(rsi, Address(rsp, 9 * wordSize)); 4590 movq(rbp, Address(rsp, 10 * wordSize)); 4591 // skip rsp 4592 movq(rbx, Address(rsp, 12 * wordSize)); 4593 movq(rdx, Address(rsp, 13 * wordSize)); 4594 movq(rcx, Address(rsp, 14 * wordSize)); 4595 movq(rax, Address(rsp, 15 * wordSize)); 4596 4597 addq(rsp, 16 * wordSize); 4598 } 4599 4600 void Assembler::popcntq(Register dst, Address src) { 4601 assert(VM_Version::supports_popcnt(), "must support"); 4602 InstructionMark im(this); 4603 emit_byte(0xF3); 4604 prefixq(src, dst); 4605 emit_byte(0x0F); 4606 emit_byte(0xB8); 4607 emit_operand(dst, src); 4608 } 4609 4610 void Assembler::popcntq(Register dst, Register src) { 4611 assert(VM_Version::supports_popcnt(), "must support"); 4612 emit_byte(0xF3); 4613 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4614 emit_byte(0x0F); 4615 emit_byte(0xB8); 4616 emit_byte(0xC0 | encode); 4617 } 4618 4619 void Assembler::popq(Address dst) { 4620 InstructionMark im(this); 4621 prefixq(dst); 4622 emit_byte(0x8F); 4623 emit_operand(rax, dst); 4624 } 4625 4626 void Assembler::pusha() { // 64bit 4627 // we have to store original rsp. ABI says that 128 bytes 4628 // below rsp are local scratch. 4629 movq(Address(rsp, -5 * wordSize), rsp); 4630 4631 subq(rsp, 16 * wordSize); 4632 4633 movq(Address(rsp, 15 * wordSize), rax); 4634 movq(Address(rsp, 14 * wordSize), rcx); 4635 movq(Address(rsp, 13 * wordSize), rdx); 4636 movq(Address(rsp, 12 * wordSize), rbx); 4637 // skip rsp 4638 movq(Address(rsp, 10 * wordSize), rbp); 4639 movq(Address(rsp, 9 * wordSize), rsi); 4640 movq(Address(rsp, 8 * wordSize), rdi); 4641 movq(Address(rsp, 7 * wordSize), r8); 4642 movq(Address(rsp, 6 * wordSize), r9); 4643 movq(Address(rsp, 5 * wordSize), r10); 4644 movq(Address(rsp, 4 * wordSize), r11); 4645 movq(Address(rsp, 3 * wordSize), r12); 4646 movq(Address(rsp, 2 * wordSize), r13); 4647 movq(Address(rsp, wordSize), r14); 4648 movq(Address(rsp, 0), r15); 4649 } 4650 4651 void Assembler::pushq(Address src) { 4652 InstructionMark im(this); 4653 prefixq(src); 4654 emit_byte(0xFF); 4655 emit_operand(rsi, src); 4656 } 4657 4658 void Assembler::rclq(Register dst, int imm8) { 4659 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 4660 int encode = prefixq_and_encode(dst->encoding()); 4661 if (imm8 == 1) { 4662 emit_byte(0xD1); 4663 emit_byte(0xD0 | encode); 4664 } else { 4665 emit_byte(0xC1); 4666 emit_byte(0xD0 | encode); 4667 emit_byte(imm8); 4668 } 4669 } 4670 void Assembler::sarq(Register dst, int imm8) { 4671 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 4672 int encode = prefixq_and_encode(dst->encoding()); 4673 if (imm8 == 1) { 4674 emit_byte(0xD1); 4675 emit_byte(0xF8 | encode); 4676 } else { 4677 emit_byte(0xC1); 4678 emit_byte(0xF8 | encode); 4679 emit_byte(imm8); 4680 } 4681 } 4682 4683 void Assembler::sarq(Register dst) { 4684 int encode = prefixq_and_encode(dst->encoding()); 4685 emit_byte(0xD3); 4686 emit_byte(0xF8 | encode); 4687 } 4688 4689 void Assembler::sbbq(Address dst, int32_t imm32) { 4690 InstructionMark im(this); 4691 prefixq(dst); 4692 emit_arith_operand(0x81, rbx, dst, imm32); 4693 } 4694 4695 void Assembler::sbbq(Register dst, int32_t imm32) { 4696 (void) prefixq_and_encode(dst->encoding()); 4697 emit_arith(0x81, 0xD8, dst, imm32); 4698 } 4699 4700 void Assembler::sbbq(Register dst, Address src) { 4701 InstructionMark im(this); 4702 prefixq(src, dst); 4703 emit_byte(0x1B); 4704 emit_operand(dst, src); 4705 } 4706 4707 void Assembler::sbbq(Register dst, Register src) { 4708 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4709 emit_arith(0x1B, 0xC0, dst, src); 4710 } 4711 4712 void Assembler::shlq(Register dst, int imm8) { 4713 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 4714 int encode = prefixq_and_encode(dst->encoding()); 4715 if (imm8 == 1) { 4716 emit_byte(0xD1); 4717 emit_byte(0xE0 | encode); 4718 } else { 4719 emit_byte(0xC1); 4720 emit_byte(0xE0 | encode); 4721 emit_byte(imm8); 4722 } 4723 } 4724 4725 void Assembler::shlq(Register dst) { 4726 int encode = prefixq_and_encode(dst->encoding()); 4727 emit_byte(0xD3); 4728 emit_byte(0xE0 | encode); 4729 } 4730 4731 void Assembler::shrq(Register dst, int imm8) { 4732 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 4733 int encode = prefixq_and_encode(dst->encoding()); 4734 emit_byte(0xC1); 4735 emit_byte(0xE8 | encode); 4736 emit_byte(imm8); 4737 } 4738 4739 void Assembler::shrq(Register dst) { 4740 int encode = prefixq_and_encode(dst->encoding()); 4741 emit_byte(0xD3); 4742 emit_byte(0xE8 | encode); 4743 } 4744 4745 void Assembler::subq(Address dst, int32_t imm32) { 4746 InstructionMark im(this); 4747 prefixq(dst); 4748 emit_arith_operand(0x81, rbp, dst, imm32); 4749 } 4750 4751 void Assembler::subq(Address dst, Register src) { 4752 InstructionMark im(this); 4753 prefixq(dst, src); 4754 emit_byte(0x29); 4755 emit_operand(src, dst); 4756 } 4757 4758 void Assembler::subq(Register dst, int32_t imm32) { 4759 (void) prefixq_and_encode(dst->encoding()); 4760 emit_arith(0x81, 0xE8, dst, imm32); 4761 } 4762 4763 void Assembler::subq(Register dst, Address src) { 4764 InstructionMark im(this); 4765 prefixq(src, dst); 4766 emit_byte(0x2B); 4767 emit_operand(dst, src); 4768 } 4769 4770 void Assembler::subq(Register dst, Register src) { 4771 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4772 emit_arith(0x2B, 0xC0, dst, src); 4773 } 4774 4775 void Assembler::testq(Register dst, int32_t imm32) { 4776 // not using emit_arith because test 4777 // doesn't support sign-extension of 4778 // 8bit operands 4779 int encode = dst->encoding(); 4780 if (encode == 0) { 4781 prefix(REX_W); 4782 emit_byte(0xA9); 4783 } else { 4784 encode = prefixq_and_encode(encode); 4785 emit_byte(0xF7); 4786 emit_byte(0xC0 | encode); 4787 } 4788 emit_long(imm32); 4789 } 4790 4791 void Assembler::testq(Register dst, Register src) { 4792 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4793 emit_arith(0x85, 0xC0, dst, src); 4794 } 4795 4796 void Assembler::xaddq(Address dst, Register src) { 4797 InstructionMark im(this); 4798 prefixq(dst, src); 4799 emit_byte(0x0F); 4800 emit_byte(0xC1); 4801 emit_operand(src, dst); 4802 } 4803 4804 void Assembler::xchgq(Register dst, Address src) { 4805 InstructionMark im(this); 4806 prefixq(src, dst); 4807 emit_byte(0x87); 4808 emit_operand(dst, src); 4809 } 4810 4811 void Assembler::xchgq(Register dst, Register src) { 4812 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4813 emit_byte(0x87); 4814 emit_byte(0xc0 | encode); 4815 } 4816 4817 void Assembler::xorq(Register dst, Register src) { 4818 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4819 emit_arith(0x33, 0xC0, dst, src); 4820 } 4821 4822 void Assembler::xorq(Register dst, Address src) { 4823 InstructionMark im(this); 4824 prefixq(src, dst); 4825 emit_byte(0x33); 4826 emit_operand(dst, src); 4827 } 4828 4829 #endif // !LP64 4830 4831 static Assembler::Condition reverse[] = { 4832 Assembler::noOverflow /* overflow = 0x0 */ , 4833 Assembler::overflow /* noOverflow = 0x1 */ , 4834 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 4835 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 4836 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 4837 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 4838 Assembler::above /* belowEqual = 0x6 */ , 4839 Assembler::belowEqual /* above = 0x7 */ , 4840 Assembler::positive /* negative = 0x8 */ , 4841 Assembler::negative /* positive = 0x9 */ , 4842 Assembler::noParity /* parity = 0xa */ , 4843 Assembler::parity /* noParity = 0xb */ , 4844 Assembler::greaterEqual /* less = 0xc */ , 4845 Assembler::less /* greaterEqual = 0xd */ , 4846 Assembler::greater /* lessEqual = 0xe */ , 4847 Assembler::lessEqual /* greater = 0xf, */ 4848 4849 }; 4850 4851 4852 // Implementation of MacroAssembler 4853 4854 // First all the versions that have distinct versions depending on 32/64 bit 4855 // Unless the difference is trivial (1 line or so). 4856 4857 #ifndef _LP64 4858 4859 // 32bit versions 4860 4861 Address MacroAssembler::as_Address(AddressLiteral adr) { 4862 return Address(adr.target(), adr.rspec()); 4863 } 4864 4865 Address MacroAssembler::as_Address(ArrayAddress adr) { 4866 return Address::make_array(adr); 4867 } 4868 4869 int MacroAssembler::biased_locking_enter(Register lock_reg, 4870 Register obj_reg, 4871 Register swap_reg, 4872 Register tmp_reg, 4873 bool swap_reg_contains_mark, 4874 Label& done, 4875 Label* slow_case, 4876 BiasedLockingCounters* counters) { 4877 assert(UseBiasedLocking, "why call this otherwise?"); 4878 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); 4879 assert_different_registers(lock_reg, obj_reg, swap_reg); 4880 4881 if (PrintBiasedLockingStatistics && counters == NULL) 4882 counters = BiasedLocking::counters(); 4883 4884 bool need_tmp_reg = false; 4885 if (tmp_reg == noreg) { 4886 need_tmp_reg = true; 4887 tmp_reg = lock_reg; 4888 } else { 4889 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 4890 } 4891 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 4892 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 4893 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 4894 Address saved_mark_addr(lock_reg, 0); 4895 4896 // Biased locking 4897 // See whether the lock is currently biased toward our thread and 4898 // whether the epoch is still valid 4899 // Note that the runtime guarantees sufficient alignment of JavaThread 4900 // pointers to allow age to be placed into low bits 4901 // First check to see whether biasing is even enabled for this object 4902 Label cas_label; 4903 int null_check_offset = -1; 4904 if (!swap_reg_contains_mark) { 4905 null_check_offset = offset(); 4906 movl(swap_reg, mark_addr); 4907 } 4908 if (need_tmp_reg) { 4909 push(tmp_reg); 4910 } 4911 movl(tmp_reg, swap_reg); 4912 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); 4913 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); 4914 if (need_tmp_reg) { 4915 pop(tmp_reg); 4916 } 4917 jcc(Assembler::notEqual, cas_label); 4918 // The bias pattern is present in the object's header. Need to check 4919 // whether the bias owner and the epoch are both still current. 4920 // Note that because there is no current thread register on x86 we 4921 // need to store off the mark word we read out of the object to 4922 // avoid reloading it and needing to recheck invariants below. This 4923 // store is unfortunate but it makes the overall code shorter and 4924 // simpler. 4925 movl(saved_mark_addr, swap_reg); 4926 if (need_tmp_reg) { 4927 push(tmp_reg); 4928 } 4929 get_thread(tmp_reg); 4930 xorl(swap_reg, tmp_reg); 4931 if (swap_reg_contains_mark) { 4932 null_check_offset = offset(); 4933 } 4934 movl(tmp_reg, klass_addr); 4935 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); 4936 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); 4937 if (need_tmp_reg) { 4938 pop(tmp_reg); 4939 } 4940 if (counters != NULL) { 4941 cond_inc32(Assembler::zero, 4942 ExternalAddress((address)counters->biased_lock_entry_count_addr())); 4943 } 4944 jcc(Assembler::equal, done); 4945 4946 Label try_revoke_bias; 4947 Label try_rebias; 4948 4949 // At this point we know that the header has the bias pattern and 4950 // that we are not the bias owner in the current epoch. We need to 4951 // figure out more details about the state of the header in order to 4952 // know what operations can be legally performed on the object's 4953 // header. 4954 4955 // If the low three bits in the xor result aren't clear, that means 4956 // the prototype header is no longer biased and we have to revoke 4957 // the bias on this object. 4958 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); 4959 jcc(Assembler::notZero, try_revoke_bias); 4960 4961 // Biasing is still enabled for this data type. See whether the 4962 // epoch of the current bias is still valid, meaning that the epoch 4963 // bits of the mark word are equal to the epoch bits of the 4964 // prototype header. (Note that the prototype header's epoch bits 4965 // only change at a safepoint.) If not, attempt to rebias the object 4966 // toward the current thread. Note that we must be absolutely sure 4967 // that the current epoch is invalid in order to do this because 4968 // otherwise the manipulations it performs on the mark word are 4969 // illegal. 4970 testl(swap_reg, markOopDesc::epoch_mask_in_place); 4971 jcc(Assembler::notZero, try_rebias); 4972 4973 // The epoch of the current bias is still valid but we know nothing 4974 // about the owner; it might be set or it might be clear. Try to 4975 // acquire the bias of the object using an atomic operation. If this 4976 // fails we will go in to the runtime to revoke the object's bias. 4977 // Note that we first construct the presumed unbiased header so we 4978 // don't accidentally blow away another thread's valid bias. 4979 movl(swap_reg, saved_mark_addr); 4980 andl(swap_reg, 4981 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 4982 if (need_tmp_reg) { 4983 push(tmp_reg); 4984 } 4985 get_thread(tmp_reg); 4986 orl(tmp_reg, swap_reg); 4987 if (os::is_MP()) { 4988 lock(); 4989 } 4990 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); 4991 if (need_tmp_reg) { 4992 pop(tmp_reg); 4993 } 4994 // If the biasing toward our thread failed, this means that 4995 // another thread succeeded in biasing it toward itself and we 4996 // need to revoke that bias. The revocation will occur in the 4997 // interpreter runtime in the slow case. 4998 if (counters != NULL) { 4999 cond_inc32(Assembler::zero, 5000 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); 5001 } 5002 if (slow_case != NULL) { 5003 jcc(Assembler::notZero, *slow_case); 5004 } 5005 jmp(done); 5006 5007 bind(try_rebias); 5008 // At this point we know the epoch has expired, meaning that the 5009 // current "bias owner", if any, is actually invalid. Under these 5010 // circumstances _only_, we are allowed to use the current header's 5011 // value as the comparison value when doing the cas to acquire the 5012 // bias in the current epoch. In other words, we allow transfer of 5013 // the bias from one thread to another directly in this situation. 5014 // 5015 // FIXME: due to a lack of registers we currently blow away the age 5016 // bits in this situation. Should attempt to preserve them. 5017 if (need_tmp_reg) { 5018 push(tmp_reg); 5019 } 5020 get_thread(tmp_reg); 5021 movl(swap_reg, klass_addr); 5022 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); 5023 movl(swap_reg, saved_mark_addr); 5024 if (os::is_MP()) { 5025 lock(); 5026 } 5027 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); 5028 if (need_tmp_reg) { 5029 pop(tmp_reg); 5030 } 5031 // If the biasing toward our thread failed, then another thread 5032 // succeeded in biasing it toward itself and we need to revoke that 5033 // bias. The revocation will occur in the runtime in the slow case. 5034 if (counters != NULL) { 5035 cond_inc32(Assembler::zero, 5036 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); 5037 } 5038 if (slow_case != NULL) { 5039 jcc(Assembler::notZero, *slow_case); 5040 } 5041 jmp(done); 5042 5043 bind(try_revoke_bias); 5044 // The prototype mark in the klass doesn't have the bias bit set any 5045 // more, indicating that objects of this data type are not supposed 5046 // to be biased any more. We are going to try to reset the mark of 5047 // this object to the prototype value and fall through to the 5048 // CAS-based locking scheme. Note that if our CAS fails, it means 5049 // that another thread raced us for the privilege of revoking the 5050 // bias of this particular object, so it's okay to continue in the 5051 // normal locking code. 5052 // 5053 // FIXME: due to a lack of registers we currently blow away the age 5054 // bits in this situation. Should attempt to preserve them. 5055 movl(swap_reg, saved_mark_addr); 5056 if (need_tmp_reg) { 5057 push(tmp_reg); 5058 } 5059 movl(tmp_reg, klass_addr); 5060 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); 5061 if (os::is_MP()) { 5062 lock(); 5063 } 5064 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); 5065 if (need_tmp_reg) { 5066 pop(tmp_reg); 5067 } 5068 // Fall through to the normal CAS-based lock, because no matter what 5069 // the result of the above CAS, some thread must have succeeded in 5070 // removing the bias bit from the object's header. 5071 if (counters != NULL) { 5072 cond_inc32(Assembler::zero, 5073 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); 5074 } 5075 5076 bind(cas_label); 5077 5078 return null_check_offset; 5079 } 5080 void MacroAssembler::call_VM_leaf_base(address entry_point, 5081 int number_of_arguments) { 5082 call(RuntimeAddress(entry_point)); 5083 increment(rsp, number_of_arguments * wordSize); 5084 } 5085 5086 void MacroAssembler::cmpoop(Address src1, jobject obj) { 5087 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 5088 } 5089 5090 void MacroAssembler::cmpoop(Register src1, jobject obj) { 5091 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 5092 } 5093 5094 void MacroAssembler::extend_sign(Register hi, Register lo) { 5095 // According to Intel Doc. AP-526, "Integer Divide", p.18. 5096 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 5097 cdql(); 5098 } else { 5099 movl(hi, lo); 5100 sarl(hi, 31); 5101 } 5102 } 5103 5104 void MacroAssembler::fat_nop() { 5105 // A 5 byte nop that is safe for patching (see patch_verified_entry) 5106 emit_byte(0x26); // es: 5107 emit_byte(0x2e); // cs: 5108 emit_byte(0x64); // fs: 5109 emit_byte(0x65); // gs: 5110 emit_byte(0x90); 5111 } 5112 5113 void MacroAssembler::jC2(Register tmp, Label& L) { 5114 // set parity bit if FPU flag C2 is set (via rax) 5115 save_rax(tmp); 5116 fwait(); fnstsw_ax(); 5117 sahf(); 5118 restore_rax(tmp); 5119 // branch 5120 jcc(Assembler::parity, L); 5121 } 5122 5123 void MacroAssembler::jnC2(Register tmp, Label& L) { 5124 // set parity bit if FPU flag C2 is set (via rax) 5125 save_rax(tmp); 5126 fwait(); fnstsw_ax(); 5127 sahf(); 5128 restore_rax(tmp); 5129 // branch 5130 jcc(Assembler::noParity, L); 5131 } 5132 5133 // 32bit can do a case table jump in one instruction but we no longer allow the base 5134 // to be installed in the Address class 5135 void MacroAssembler::jump(ArrayAddress entry) { 5136 jmp(as_Address(entry)); 5137 } 5138 5139 // Note: y_lo will be destroyed 5140 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 5141 // Long compare for Java (semantics as described in JVM spec.) 5142 Label high, low, done; 5143 5144 cmpl(x_hi, y_hi); 5145 jcc(Assembler::less, low); 5146 jcc(Assembler::greater, high); 5147 // x_hi is the return register 5148 xorl(x_hi, x_hi); 5149 cmpl(x_lo, y_lo); 5150 jcc(Assembler::below, low); 5151 jcc(Assembler::equal, done); 5152 5153 bind(high); 5154 xorl(x_hi, x_hi); 5155 increment(x_hi); 5156 jmp(done); 5157 5158 bind(low); 5159 xorl(x_hi, x_hi); 5160 decrementl(x_hi); 5161 5162 bind(done); 5163 } 5164 5165 void MacroAssembler::lea(Register dst, AddressLiteral src) { 5166 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 5167 } 5168 5169 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 5170 // leal(dst, as_Address(adr)); 5171 // see note in movl as to why we must use a move 5172 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 5173 } 5174 5175 void MacroAssembler::leave() { 5176 mov(rsp, rbp); 5177 pop(rbp); 5178 } 5179 5180 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 5181 // Multiplication of two Java long values stored on the stack 5182 // as illustrated below. Result is in rdx:rax. 5183 // 5184 // rsp ---> [ ?? ] \ \ 5185 // .... | y_rsp_offset | 5186 // [ y_lo ] / (in bytes) | x_rsp_offset 5187 // [ y_hi ] | (in bytes) 5188 // .... | 5189 // [ x_lo ] / 5190 // [ x_hi ] 5191 // .... 5192 // 5193 // Basic idea: lo(result) = lo(x_lo * y_lo) 5194 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 5195 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 5196 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 5197 Label quick; 5198 // load x_hi, y_hi and check if quick 5199 // multiplication is possible 5200 movl(rbx, x_hi); 5201 movl(rcx, y_hi); 5202 movl(rax, rbx); 5203 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 5204 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 5205 // do full multiplication 5206 // 1st step 5207 mull(y_lo); // x_hi * y_lo 5208 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 5209 // 2nd step 5210 movl(rax, x_lo); 5211 mull(rcx); // x_lo * y_hi 5212 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 5213 // 3rd step 5214 bind(quick); // note: rbx, = 0 if quick multiply! 5215 movl(rax, x_lo); 5216 mull(y_lo); // x_lo * y_lo 5217 addl(rdx, rbx); // correct hi(x_lo * y_lo) 5218 } 5219 5220 void MacroAssembler::lneg(Register hi, Register lo) { 5221 negl(lo); 5222 adcl(hi, 0); 5223 negl(hi); 5224 } 5225 5226 void MacroAssembler::lshl(Register hi, Register lo) { 5227 // Java shift left long support (semantics as described in JVM spec., p.305) 5228 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 5229 // shift value is in rcx ! 5230 assert(hi != rcx, "must not use rcx"); 5231 assert(lo != rcx, "must not use rcx"); 5232 const Register s = rcx; // shift count 5233 const int n = BitsPerWord; 5234 Label L; 5235 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 5236 cmpl(s, n); // if (s < n) 5237 jcc(Assembler::less, L); // else (s >= n) 5238 movl(hi, lo); // x := x << n 5239 xorl(lo, lo); 5240 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 5241 bind(L); // s (mod n) < n 5242 shldl(hi, lo); // x := x << s 5243 shll(lo); 5244 } 5245 5246 5247 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 5248 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 5249 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 5250 assert(hi != rcx, "must not use rcx"); 5251 assert(lo != rcx, "must not use rcx"); 5252 const Register s = rcx; // shift count 5253 const int n = BitsPerWord; 5254 Label L; 5255 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 5256 cmpl(s, n); // if (s < n) 5257 jcc(Assembler::less, L); // else (s >= n) 5258 movl(lo, hi); // x := x >> n 5259 if (sign_extension) sarl(hi, 31); 5260 else xorl(hi, hi); 5261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 5262 bind(L); // s (mod n) < n 5263 shrdl(lo, hi); // x := x >> s 5264 if (sign_extension) sarl(hi); 5265 else shrl(hi); 5266 } 5267 5268 void MacroAssembler::movoop(Register dst, jobject obj) { 5269 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 5270 } 5271 5272 void MacroAssembler::movoop(Address dst, jobject obj) { 5273 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 5274 } 5275 5276 void MacroAssembler::movptr(Register dst, AddressLiteral src) { 5277 if (src.is_lval()) { 5278 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 5279 } else { 5280 movl(dst, as_Address(src)); 5281 } 5282 } 5283 5284 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 5285 movl(as_Address(dst), src); 5286 } 5287 5288 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 5289 movl(dst, as_Address(src)); 5290 } 5291 5292 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 5293 void MacroAssembler::movptr(Address dst, intptr_t src) { 5294 movl(dst, src); 5295 } 5296 5297 5298 void MacroAssembler::pop_callee_saved_registers() { 5299 pop(rcx); 5300 pop(rdx); 5301 pop(rdi); 5302 pop(rsi); 5303 } 5304 5305 void MacroAssembler::pop_fTOS() { 5306 fld_d(Address(rsp, 0)); 5307 addl(rsp, 2 * wordSize); 5308 } 5309 5310 void MacroAssembler::push_callee_saved_registers() { 5311 push(rsi); 5312 push(rdi); 5313 push(rdx); 5314 push(rcx); 5315 } 5316 5317 void MacroAssembler::push_fTOS() { 5318 subl(rsp, 2 * wordSize); 5319 fstp_d(Address(rsp, 0)); 5320 } 5321 5322 5323 void MacroAssembler::pushoop(jobject obj) { 5324 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 5325 } 5326 5327 5328 void MacroAssembler::pushptr(AddressLiteral src) { 5329 if (src.is_lval()) { 5330 push_literal32((int32_t)src.target(), src.rspec()); 5331 } else { 5332 pushl(as_Address(src)); 5333 } 5334 } 5335 5336 void MacroAssembler::set_word_if_not_zero(Register dst) { 5337 xorl(dst, dst); 5338 set_byte_if_not_zero(dst); 5339 } 5340 5341 static void pass_arg0(MacroAssembler* masm, Register arg) { 5342 masm->push(arg); 5343 } 5344 5345 static void pass_arg1(MacroAssembler* masm, Register arg) { 5346 masm->push(arg); 5347 } 5348 5349 static void pass_arg2(MacroAssembler* masm, Register arg) { 5350 masm->push(arg); 5351 } 5352 5353 static void pass_arg3(MacroAssembler* masm, Register arg) { 5354 masm->push(arg); 5355 } 5356 5357 #ifndef PRODUCT 5358 extern "C" void findpc(intptr_t x); 5359 #endif 5360 5361 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 5362 // In order to get locks to work, we need to fake a in_VM state 5363 JavaThread* thread = JavaThread::current(); 5364 JavaThreadState saved_state = thread->thread_state(); 5365 thread->set_thread_state(_thread_in_vm); 5366 if (ShowMessageBoxOnError) { 5367 JavaThread* thread = JavaThread::current(); 5368 JavaThreadState saved_state = thread->thread_state(); 5369 thread->set_thread_state(_thread_in_vm); 5370 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 5371 ttyLocker ttyl; 5372 BytecodeCounter::print(); 5373 } 5374 // To see where a verify_oop failed, get $ebx+40/X for this frame. 5375 // This is the value of eip which points to where verify_oop will return. 5376 if (os::message_box(msg, "Execution stopped, print registers?")) { 5377 ttyLocker ttyl; 5378 tty->print_cr("eip = 0x%08x", eip); 5379 #ifndef PRODUCT 5380 if ((WizardMode || Verbose) && PrintMiscellaneous) { 5381 tty->cr(); 5382 findpc(eip); 5383 tty->cr(); 5384 } 5385 #endif 5386 tty->print_cr("rax = 0x%08x", rax); 5387 tty->print_cr("rbx = 0x%08x", rbx); 5388 tty->print_cr("rcx = 0x%08x", rcx); 5389 tty->print_cr("rdx = 0x%08x", rdx); 5390 tty->print_cr("rdi = 0x%08x", rdi); 5391 tty->print_cr("rsi = 0x%08x", rsi); 5392 tty->print_cr("rbp = 0x%08x", rbp); 5393 tty->print_cr("rsp = 0x%08x", rsp); 5394 BREAKPOINT; 5395 assert(false, "start up GDB"); 5396 } 5397 } else { 5398 ttyLocker ttyl; 5399 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 5400 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 5401 } 5402 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 5403 } 5404 5405 void MacroAssembler::stop(const char* msg) { 5406 ExternalAddress message((address)msg); 5407 // push address of message 5408 pushptr(message.addr()); 5409 { Label L; call(L, relocInfo::none); bind(L); } // push eip 5410 pusha(); // push registers 5411 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 5412 hlt(); 5413 } 5414 5415 void MacroAssembler::warn(const char* msg) { 5416 push_CPU_state(); 5417 5418 ExternalAddress message((address) msg); 5419 // push address of message 5420 pushptr(message.addr()); 5421 5422 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 5423 addl(rsp, wordSize); // discard argument 5424 pop_CPU_state(); 5425 } 5426 5427 #else // _LP64 5428 5429 // 64 bit versions 5430 5431 Address MacroAssembler::as_Address(AddressLiteral adr) { 5432 // amd64 always does this as a pc-rel 5433 // we can be absolute or disp based on the instruction type 5434 // jmp/call are displacements others are absolute 5435 assert(!adr.is_lval(), "must be rval"); 5436 assert(reachable(adr), "must be"); 5437 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 5438 5439 } 5440 5441 Address MacroAssembler::as_Address(ArrayAddress adr) { 5442 AddressLiteral base = adr.base(); 5443 lea(rscratch1, base); 5444 Address index = adr.index(); 5445 assert(index._disp == 0, "must not have disp"); // maybe it can? 5446 Address array(rscratch1, index._index, index._scale, index._disp); 5447 return array; 5448 } 5449 5450 int MacroAssembler::biased_locking_enter(Register lock_reg, 5451 Register obj_reg, 5452 Register swap_reg, 5453 Register tmp_reg, 5454 bool swap_reg_contains_mark, 5455 Label& done, 5456 Label* slow_case, 5457 BiasedLockingCounters* counters) { 5458 assert(UseBiasedLocking, "why call this otherwise?"); 5459 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 5460 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 5461 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 5462 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 5463 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 5464 Address saved_mark_addr(lock_reg, 0); 5465 5466 if (PrintBiasedLockingStatistics && counters == NULL) 5467 counters = BiasedLocking::counters(); 5468 5469 // Biased locking 5470 // See whether the lock is currently biased toward our thread and 5471 // whether the epoch is still valid 5472 // Note that the runtime guarantees sufficient alignment of JavaThread 5473 // pointers to allow age to be placed into low bits 5474 // First check to see whether biasing is even enabled for this object 5475 Label cas_label; 5476 int null_check_offset = -1; 5477 if (!swap_reg_contains_mark) { 5478 null_check_offset = offset(); 5479 movq(swap_reg, mark_addr); 5480 } 5481 movq(tmp_reg, swap_reg); 5482 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); 5483 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); 5484 jcc(Assembler::notEqual, cas_label); 5485 // The bias pattern is present in the object's header. Need to check 5486 // whether the bias owner and the epoch are both still current. 5487 load_prototype_header(tmp_reg, obj_reg); 5488 orq(tmp_reg, r15_thread); 5489 xorq(tmp_reg, swap_reg); 5490 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 5491 if (counters != NULL) { 5492 cond_inc32(Assembler::zero, 5493 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 5494 } 5495 jcc(Assembler::equal, done); 5496 5497 Label try_revoke_bias; 5498 Label try_rebias; 5499 5500 // At this point we know that the header has the bias pattern and 5501 // that we are not the bias owner in the current epoch. We need to 5502 // figure out more details about the state of the header in order to 5503 // know what operations can be legally performed on the object's 5504 // header. 5505 5506 // If the low three bits in the xor result aren't clear, that means 5507 // the prototype header is no longer biased and we have to revoke 5508 // the bias on this object. 5509 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); 5510 jcc(Assembler::notZero, try_revoke_bias); 5511 5512 // Biasing is still enabled for this data type. See whether the 5513 // epoch of the current bias is still valid, meaning that the epoch 5514 // bits of the mark word are equal to the epoch bits of the 5515 // prototype header. (Note that the prototype header's epoch bits 5516 // only change at a safepoint.) If not, attempt to rebias the object 5517 // toward the current thread. Note that we must be absolutely sure 5518 // that the current epoch is invalid in order to do this because 5519 // otherwise the manipulations it performs on the mark word are 5520 // illegal. 5521 testq(tmp_reg, markOopDesc::epoch_mask_in_place); 5522 jcc(Assembler::notZero, try_rebias); 5523 5524 // The epoch of the current bias is still valid but we know nothing 5525 // about the owner; it might be set or it might be clear. Try to 5526 // acquire the bias of the object using an atomic operation. If this 5527 // fails we will go in to the runtime to revoke the object's bias. 5528 // Note that we first construct the presumed unbiased header so we 5529 // don't accidentally blow away another thread's valid bias. 5530 andq(swap_reg, 5531 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 5532 movq(tmp_reg, swap_reg); 5533 orq(tmp_reg, r15_thread); 5534 if (os::is_MP()) { 5535 lock(); 5536 } 5537 cmpxchgq(tmp_reg, Address(obj_reg, 0)); 5538 // If the biasing toward our thread failed, this means that 5539 // another thread succeeded in biasing it toward itself and we 5540 // need to revoke that bias. The revocation will occur in the 5541 // interpreter runtime in the slow case. 5542 if (counters != NULL) { 5543 cond_inc32(Assembler::zero, 5544 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 5545 } 5546 if (slow_case != NULL) { 5547 jcc(Assembler::notZero, *slow_case); 5548 } 5549 jmp(done); 5550 5551 bind(try_rebias); 5552 // At this point we know the epoch has expired, meaning that the 5553 // current "bias owner", if any, is actually invalid. Under these 5554 // circumstances _only_, we are allowed to use the current header's 5555 // value as the comparison value when doing the cas to acquire the 5556 // bias in the current epoch. In other words, we allow transfer of 5557 // the bias from one thread to another directly in this situation. 5558 // 5559 // FIXME: due to a lack of registers we currently blow away the age 5560 // bits in this situation. Should attempt to preserve them. 5561 load_prototype_header(tmp_reg, obj_reg); 5562 orq(tmp_reg, r15_thread); 5563 if (os::is_MP()) { 5564 lock(); 5565 } 5566 cmpxchgq(tmp_reg, Address(obj_reg, 0)); 5567 // If the biasing toward our thread failed, then another thread 5568 // succeeded in biasing it toward itself and we need to revoke that 5569 // bias. The revocation will occur in the runtime in the slow case. 5570 if (counters != NULL) { 5571 cond_inc32(Assembler::zero, 5572 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 5573 } 5574 if (slow_case != NULL) { 5575 jcc(Assembler::notZero, *slow_case); 5576 } 5577 jmp(done); 5578 5579 bind(try_revoke_bias); 5580 // The prototype mark in the klass doesn't have the bias bit set any 5581 // more, indicating that objects of this data type are not supposed 5582 // to be biased any more. We are going to try to reset the mark of 5583 // this object to the prototype value and fall through to the 5584 // CAS-based locking scheme. Note that if our CAS fails, it means 5585 // that another thread raced us for the privilege of revoking the 5586 // bias of this particular object, so it's okay to continue in the 5587 // normal locking code. 5588 // 5589 // FIXME: due to a lack of registers we currently blow away the age 5590 // bits in this situation. Should attempt to preserve them. 5591 load_prototype_header(tmp_reg, obj_reg); 5592 if (os::is_MP()) { 5593 lock(); 5594 } 5595 cmpxchgq(tmp_reg, Address(obj_reg, 0)); 5596 // Fall through to the normal CAS-based lock, because no matter what 5597 // the result of the above CAS, some thread must have succeeded in 5598 // removing the bias bit from the object's header. 5599 if (counters != NULL) { 5600 cond_inc32(Assembler::zero, 5601 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 5602 } 5603 5604 bind(cas_label); 5605 5606 return null_check_offset; 5607 } 5608 5609 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 5610 Label L, E; 5611 5612 #ifdef _WIN64 5613 // Windows always allocates space for it's register args 5614 assert(num_args <= 4, "only register arguments supported"); 5615 subq(rsp, frame::arg_reg_save_area_bytes); 5616 #endif 5617 5618 // Align stack if necessary 5619 testl(rsp, 15); 5620 jcc(Assembler::zero, L); 5621 5622 subq(rsp, 8); 5623 { 5624 call(RuntimeAddress(entry_point)); 5625 } 5626 addq(rsp, 8); 5627 jmp(E); 5628 5629 bind(L); 5630 { 5631 call(RuntimeAddress(entry_point)); 5632 } 5633 5634 bind(E); 5635 5636 #ifdef _WIN64 5637 // restore stack pointer 5638 addq(rsp, frame::arg_reg_save_area_bytes); 5639 #endif 5640 5641 } 5642 5643 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 5644 assert(!src2.is_lval(), "should use cmpptr"); 5645 5646 if (reachable(src2)) { 5647 cmpq(src1, as_Address(src2)); 5648 } else { 5649 lea(rscratch1, src2); 5650 Assembler::cmpq(src1, Address(rscratch1, 0)); 5651 } 5652 } 5653 5654 int MacroAssembler::corrected_idivq(Register reg) { 5655 // Full implementation of Java ldiv and lrem; checks for special 5656 // case as described in JVM spec., p.243 & p.271. The function 5657 // returns the (pc) offset of the idivl instruction - may be needed 5658 // for implicit exceptions. 5659 // 5660 // normal case special case 5661 // 5662 // input : rax: dividend min_long 5663 // reg: divisor (may not be eax/edx) -1 5664 // 5665 // output: rax: quotient (= rax idiv reg) min_long 5666 // rdx: remainder (= rax irem reg) 0 5667 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 5668 static const int64_t min_long = 0x8000000000000000; 5669 Label normal_case, special_case; 5670 5671 // check for special case 5672 cmp64(rax, ExternalAddress((address) &min_long)); 5673 jcc(Assembler::notEqual, normal_case); 5674 xorl(rdx, rdx); // prepare rdx for possible special case (where 5675 // remainder = 0) 5676 cmpq(reg, -1); 5677 jcc(Assembler::equal, special_case); 5678 5679 // handle normal case 5680 bind(normal_case); 5681 cdqq(); 5682 int idivq_offset = offset(); 5683 idivq(reg); 5684 5685 // normal and special case exit 5686 bind(special_case); 5687 5688 return idivq_offset; 5689 } 5690 5691 void MacroAssembler::decrementq(Register reg, int value) { 5692 if (value == min_jint) { subq(reg, value); return; } 5693 if (value < 0) { incrementq(reg, -value); return; } 5694 if (value == 0) { ; return; } 5695 if (value == 1 && UseIncDec) { decq(reg) ; return; } 5696 /* else */ { subq(reg, value) ; return; } 5697 } 5698 5699 void MacroAssembler::decrementq(Address dst, int value) { 5700 if (value == min_jint) { subq(dst, value); return; } 5701 if (value < 0) { incrementq(dst, -value); return; } 5702 if (value == 0) { ; return; } 5703 if (value == 1 && UseIncDec) { decq(dst) ; return; } 5704 /* else */ { subq(dst, value) ; return; } 5705 } 5706 5707 void MacroAssembler::fat_nop() { 5708 // A 5 byte nop that is safe for patching (see patch_verified_entry) 5709 // Recommened sequence from 'Software Optimization Guide for the AMD 5710 // Hammer Processor' 5711 emit_byte(0x66); 5712 emit_byte(0x66); 5713 emit_byte(0x90); 5714 emit_byte(0x66); 5715 emit_byte(0x90); 5716 } 5717 5718 void MacroAssembler::incrementq(Register reg, int value) { 5719 if (value == min_jint) { addq(reg, value); return; } 5720 if (value < 0) { decrementq(reg, -value); return; } 5721 if (value == 0) { ; return; } 5722 if (value == 1 && UseIncDec) { incq(reg) ; return; } 5723 /* else */ { addq(reg, value) ; return; } 5724 } 5725 5726 void MacroAssembler::incrementq(Address dst, int value) { 5727 if (value == min_jint) { addq(dst, value); return; } 5728 if (value < 0) { decrementq(dst, -value); return; } 5729 if (value == 0) { ; return; } 5730 if (value == 1 && UseIncDec) { incq(dst) ; return; } 5731 /* else */ { addq(dst, value) ; return; } 5732 } 5733 5734 // 32bit can do a case table jump in one instruction but we no longer allow the base 5735 // to be installed in the Address class 5736 void MacroAssembler::jump(ArrayAddress entry) { 5737 lea(rscratch1, entry.base()); 5738 Address dispatch = entry.index(); 5739 assert(dispatch._base == noreg, "must be"); 5740 dispatch._base = rscratch1; 5741 jmp(dispatch); 5742 } 5743 5744 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 5745 ShouldNotReachHere(); // 64bit doesn't use two regs 5746 cmpq(x_lo, y_lo); 5747 } 5748 5749 void MacroAssembler::lea(Register dst, AddressLiteral src) { 5750 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 5751 } 5752 5753 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 5754 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 5755 movptr(dst, rscratch1); 5756 } 5757 5758 void MacroAssembler::leave() { 5759 // %%% is this really better? Why not on 32bit too? 5760 emit_byte(0xC9); // LEAVE 5761 } 5762 5763 void MacroAssembler::lneg(Register hi, Register lo) { 5764 ShouldNotReachHere(); // 64bit doesn't use two regs 5765 negq(lo); 5766 } 5767 5768 void MacroAssembler::movoop(Register dst, jobject obj) { 5769 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 5770 } 5771 5772 void MacroAssembler::movoop(Address dst, jobject obj) { 5773 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 5774 movq(dst, rscratch1); 5775 } 5776 5777 void MacroAssembler::movptr(Register dst, AddressLiteral src) { 5778 if (src.is_lval()) { 5779 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 5780 } else { 5781 if (reachable(src)) { 5782 movq(dst, as_Address(src)); 5783 } else { 5784 lea(rscratch1, src); 5785 movq(dst, Address(rscratch1,0)); 5786 } 5787 } 5788 } 5789 5790 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 5791 movq(as_Address(dst), src); 5792 } 5793 5794 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 5795 movq(dst, as_Address(src)); 5796 } 5797 5798 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 5799 void MacroAssembler::movptr(Address dst, intptr_t src) { 5800 mov64(rscratch1, src); 5801 movq(dst, rscratch1); 5802 } 5803 5804 // These are mostly for initializing NULL 5805 void MacroAssembler::movptr(Address dst, int32_t src) { 5806 movslq(dst, src); 5807 } 5808 5809 void MacroAssembler::movptr(Register dst, int32_t src) { 5810 mov64(dst, (intptr_t)src); 5811 } 5812 5813 void MacroAssembler::pushoop(jobject obj) { 5814 movoop(rscratch1, obj); 5815 push(rscratch1); 5816 } 5817 5818 void MacroAssembler::pushptr(AddressLiteral src) { 5819 lea(rscratch1, src); 5820 if (src.is_lval()) { 5821 push(rscratch1); 5822 } else { 5823 pushq(Address(rscratch1, 0)); 5824 } 5825 } 5826 5827 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 5828 bool clear_pc) { 5829 // we must set sp to zero to clear frame 5830 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 5831 // must clear fp, so that compiled frames are not confused; it is 5832 // possible that we need it only for debugging 5833 if (clear_fp) { 5834 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 5835 } 5836 5837 if (clear_pc) { 5838 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 5839 } 5840 } 5841 5842 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 5843 Register last_java_fp, 5844 address last_java_pc) { 5845 // determine last_java_sp register 5846 if (!last_java_sp->is_valid()) { 5847 last_java_sp = rsp; 5848 } 5849 5850 // last_java_fp is optional 5851 if (last_java_fp->is_valid()) { 5852 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 5853 last_java_fp); 5854 } 5855 5856 // last_java_pc is optional 5857 if (last_java_pc != NULL) { 5858 Address java_pc(r15_thread, 5859 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 5860 lea(rscratch1, InternalAddress(last_java_pc)); 5861 movptr(java_pc, rscratch1); 5862 } 5863 5864 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 5865 } 5866 5867 static void pass_arg0(MacroAssembler* masm, Register arg) { 5868 if (c_rarg0 != arg ) { 5869 masm->mov(c_rarg0, arg); 5870 } 5871 } 5872 5873 static void pass_arg1(MacroAssembler* masm, Register arg) { 5874 if (c_rarg1 != arg ) { 5875 masm->mov(c_rarg1, arg); 5876 } 5877 } 5878 5879 static void pass_arg2(MacroAssembler* masm, Register arg) { 5880 if (c_rarg2 != arg ) { 5881 masm->mov(c_rarg2, arg); 5882 } 5883 } 5884 5885 static void pass_arg3(MacroAssembler* masm, Register arg) { 5886 if (c_rarg3 != arg ) { 5887 masm->mov(c_rarg3, arg); 5888 } 5889 } 5890 5891 void MacroAssembler::stop(const char* msg) { 5892 address rip = pc(); 5893 pusha(); // get regs on stack 5894 lea(c_rarg0, ExternalAddress((address) msg)); 5895 lea(c_rarg1, InternalAddress(rip)); 5896 movq(c_rarg2, rsp); // pass pointer to regs array 5897 andq(rsp, -16); // align stack as required by ABI 5898 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 5899 hlt(); 5900 } 5901 5902 void MacroAssembler::warn(const char* msg) { 5903 push(rsp); 5904 andq(rsp, -16); // align stack as required by push_CPU_state and call 5905 5906 push_CPU_state(); // keeps alignment at 16 bytes 5907 lea(c_rarg0, ExternalAddress((address) msg)); 5908 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 5909 pop_CPU_state(); 5910 pop(rsp); 5911 } 5912 5913 #ifndef PRODUCT 5914 extern "C" void findpc(intptr_t x); 5915 #endif 5916 5917 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 5918 // In order to get locks to work, we need to fake a in_VM state 5919 if (ShowMessageBoxOnError ) { 5920 JavaThread* thread = JavaThread::current(); 5921 JavaThreadState saved_state = thread->thread_state(); 5922 thread->set_thread_state(_thread_in_vm); 5923 #ifndef PRODUCT 5924 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 5925 ttyLocker ttyl; 5926 BytecodeCounter::print(); 5927 } 5928 #endif 5929 // To see where a verify_oop failed, get $ebx+40/X for this frame. 5930 // XXX correct this offset for amd64 5931 // This is the value of eip which points to where verify_oop will return. 5932 if (os::message_box(msg, "Execution stopped, print registers?")) { 5933 ttyLocker ttyl; 5934 tty->print_cr("rip = 0x%016lx", pc); 5935 #ifndef PRODUCT 5936 tty->cr(); 5937 findpc(pc); 5938 tty->cr(); 5939 #endif 5940 tty->print_cr("rax = 0x%016lx", regs[15]); 5941 tty->print_cr("rbx = 0x%016lx", regs[12]); 5942 tty->print_cr("rcx = 0x%016lx", regs[14]); 5943 tty->print_cr("rdx = 0x%016lx", regs[13]); 5944 tty->print_cr("rdi = 0x%016lx", regs[8]); 5945 tty->print_cr("rsi = 0x%016lx", regs[9]); 5946 tty->print_cr("rbp = 0x%016lx", regs[10]); 5947 tty->print_cr("rsp = 0x%016lx", regs[11]); 5948 tty->print_cr("r8 = 0x%016lx", regs[7]); 5949 tty->print_cr("r9 = 0x%016lx", regs[6]); 5950 tty->print_cr("r10 = 0x%016lx", regs[5]); 5951 tty->print_cr("r11 = 0x%016lx", regs[4]); 5952 tty->print_cr("r12 = 0x%016lx", regs[3]); 5953 tty->print_cr("r13 = 0x%016lx", regs[2]); 5954 tty->print_cr("r14 = 0x%016lx", regs[1]); 5955 tty->print_cr("r15 = 0x%016lx", regs[0]); 5956 BREAKPOINT; 5957 } 5958 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 5959 } else { 5960 ttyLocker ttyl; 5961 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 5962 msg); 5963 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 5964 } 5965 } 5966 5967 #endif // _LP64 5968 5969 // Now versions that are common to 32/64 bit 5970 5971 void MacroAssembler::addptr(Register dst, int32_t imm32) { 5972 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 5973 } 5974 5975 void MacroAssembler::addptr(Register dst, Register src) { 5976 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 5977 } 5978 5979 void MacroAssembler::addptr(Address dst, Register src) { 5980 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 5981 } 5982 5983 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 5984 if (reachable(src)) { 5985 Assembler::addsd(dst, as_Address(src)); 5986 } else { 5987 lea(rscratch1, src); 5988 Assembler::addsd(dst, Address(rscratch1, 0)); 5989 } 5990 } 5991 5992 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 5993 if (reachable(src)) { 5994 addss(dst, as_Address(src)); 5995 } else { 5996 lea(rscratch1, src); 5997 addss(dst, Address(rscratch1, 0)); 5998 } 5999 } 6000 6001 void MacroAssembler::align(int modulus) { 6002 if (offset() % modulus != 0) { 6003 nop(modulus - (offset() % modulus)); 6004 } 6005 } 6006 6007 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 6008 // Used in sign-masking with aligned address. 6009 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 6010 if (reachable(src)) { 6011 Assembler::andpd(dst, as_Address(src)); 6012 } else { 6013 lea(rscratch1, src); 6014 Assembler::andpd(dst, Address(rscratch1, 0)); 6015 } 6016 } 6017 6018 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 6019 // Used in sign-masking with aligned address. 6020 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 6021 if (reachable(src)) { 6022 Assembler::andps(dst, as_Address(src)); 6023 } else { 6024 lea(rscratch1, src); 6025 Assembler::andps(dst, Address(rscratch1, 0)); 6026 } 6027 } 6028 6029 void MacroAssembler::andptr(Register dst, int32_t imm32) { 6030 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 6031 } 6032 6033 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { 6034 pushf(); 6035 if (os::is_MP()) 6036 lock(); 6037 incrementl(counter_addr); 6038 popf(); 6039 } 6040 6041 // Writes to stack successive pages until offset reached to check for 6042 // stack overflow + shadow pages. This clobbers tmp. 6043 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 6044 movptr(tmp, rsp); 6045 // Bang stack for total size given plus shadow page size. 6046 // Bang one page at a time because large size can bang beyond yellow and 6047 // red zones. 6048 Label loop; 6049 bind(loop); 6050 movl(Address(tmp, (-os::vm_page_size())), size ); 6051 subptr(tmp, os::vm_page_size()); 6052 subl(size, os::vm_page_size()); 6053 jcc(Assembler::greater, loop); 6054 6055 // Bang down shadow pages too. 6056 // The -1 because we already subtracted 1 page. 6057 for (int i = 0; i< StackShadowPages-1; i++) { 6058 // this could be any sized move but this is can be a debugging crumb 6059 // so the bigger the better. 6060 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 6061 } 6062 } 6063 6064 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 6065 assert(UseBiasedLocking, "why call this otherwise?"); 6066 6067 // Check for biased locking unlock case, which is a no-op 6068 // Note: we do not have to check the thread ID for two reasons. 6069 // First, the interpreter checks for IllegalMonitorStateException at 6070 // a higher level. Second, if the bias was revoked while we held the 6071 // lock, the object could not be rebiased toward another thread, so 6072 // the bias bit would be clear. 6073 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 6074 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 6075 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 6076 jcc(Assembler::equal, done); 6077 } 6078 6079 void MacroAssembler::c2bool(Register x) { 6080 // implements x == 0 ? 0 : 1 6081 // note: must only look at least-significant byte of x 6082 // since C-style booleans are stored in one byte 6083 // only! (was bug) 6084 andl(x, 0xFF); 6085 setb(Assembler::notZero, x); 6086 } 6087 6088 // Wouldn't need if AddressLiteral version had new name 6089 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 6090 Assembler::call(L, rtype); 6091 } 6092 6093 void MacroAssembler::call(Register entry) { 6094 Assembler::call(entry); 6095 } 6096 6097 void MacroAssembler::call(AddressLiteral entry) { 6098 if (reachable(entry)) { 6099 Assembler::call_literal(entry.target(), entry.rspec()); 6100 } else { 6101 lea(rscratch1, entry); 6102 Assembler::call(rscratch1); 6103 } 6104 } 6105 6106 // Implementation of call_VM versions 6107 6108 void MacroAssembler::call_VM(Register oop_result, 6109 address entry_point, 6110 bool check_exceptions) { 6111 Label C, E; 6112 call(C, relocInfo::none); 6113 jmp(E); 6114 6115 bind(C); 6116 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 6117 ret(0); 6118 6119 bind(E); 6120 } 6121 6122 void MacroAssembler::call_VM(Register oop_result, 6123 address entry_point, 6124 Register arg_1, 6125 bool check_exceptions) { 6126 Label C, E; 6127 call(C, relocInfo::none); 6128 jmp(E); 6129 6130 bind(C); 6131 pass_arg1(this, arg_1); 6132 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 6133 ret(0); 6134 6135 bind(E); 6136 } 6137 6138 void MacroAssembler::call_VM(Register oop_result, 6139 address entry_point, 6140 Register arg_1, 6141 Register arg_2, 6142 bool check_exceptions) { 6143 Label C, E; 6144 call(C, relocInfo::none); 6145 jmp(E); 6146 6147 bind(C); 6148 6149 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6150 6151 pass_arg2(this, arg_2); 6152 pass_arg1(this, arg_1); 6153 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 6154 ret(0); 6155 6156 bind(E); 6157 } 6158 6159 void MacroAssembler::call_VM(Register oop_result, 6160 address entry_point, 6161 Register arg_1, 6162 Register arg_2, 6163 Register arg_3, 6164 bool check_exceptions) { 6165 Label C, E; 6166 call(C, relocInfo::none); 6167 jmp(E); 6168 6169 bind(C); 6170 6171 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 6172 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 6173 pass_arg3(this, arg_3); 6174 6175 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6176 pass_arg2(this, arg_2); 6177 6178 pass_arg1(this, arg_1); 6179 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 6180 ret(0); 6181 6182 bind(E); 6183 } 6184 6185 void MacroAssembler::call_VM(Register oop_result, 6186 Register last_java_sp, 6187 address entry_point, 6188 int number_of_arguments, 6189 bool check_exceptions) { 6190 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 6191 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 6192 } 6193 6194 void MacroAssembler::call_VM(Register oop_result, 6195 Register last_java_sp, 6196 address entry_point, 6197 Register arg_1, 6198 bool check_exceptions) { 6199 pass_arg1(this, arg_1); 6200 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 6201 } 6202 6203 void MacroAssembler::call_VM(Register oop_result, 6204 Register last_java_sp, 6205 address entry_point, 6206 Register arg_1, 6207 Register arg_2, 6208 bool check_exceptions) { 6209 6210 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6211 pass_arg2(this, arg_2); 6212 pass_arg1(this, arg_1); 6213 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 6214 } 6215 6216 void MacroAssembler::call_VM(Register oop_result, 6217 Register last_java_sp, 6218 address entry_point, 6219 Register arg_1, 6220 Register arg_2, 6221 Register arg_3, 6222 bool check_exceptions) { 6223 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 6224 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 6225 pass_arg3(this, arg_3); 6226 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6227 pass_arg2(this, arg_2); 6228 pass_arg1(this, arg_1); 6229 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 6230 } 6231 6232 void MacroAssembler::super_call_VM(Register oop_result, 6233 Register last_java_sp, 6234 address entry_point, 6235 int number_of_arguments, 6236 bool check_exceptions) { 6237 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 6238 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 6239 } 6240 6241 void MacroAssembler::super_call_VM(Register oop_result, 6242 Register last_java_sp, 6243 address entry_point, 6244 Register arg_1, 6245 bool check_exceptions) { 6246 pass_arg1(this, arg_1); 6247 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 6248 } 6249 6250 void MacroAssembler::super_call_VM(Register oop_result, 6251 Register last_java_sp, 6252 address entry_point, 6253 Register arg_1, 6254 Register arg_2, 6255 bool check_exceptions) { 6256 6257 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6258 pass_arg2(this, arg_2); 6259 pass_arg1(this, arg_1); 6260 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 6261 } 6262 6263 void MacroAssembler::super_call_VM(Register oop_result, 6264 Register last_java_sp, 6265 address entry_point, 6266 Register arg_1, 6267 Register arg_2, 6268 Register arg_3, 6269 bool check_exceptions) { 6270 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 6271 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 6272 pass_arg3(this, arg_3); 6273 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6274 pass_arg2(this, arg_2); 6275 pass_arg1(this, arg_1); 6276 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 6277 } 6278 6279 void MacroAssembler::call_VM_base(Register oop_result, 6280 Register java_thread, 6281 Register last_java_sp, 6282 address entry_point, 6283 int number_of_arguments, 6284 bool check_exceptions) { 6285 // determine java_thread register 6286 if (!java_thread->is_valid()) { 6287 #ifdef _LP64 6288 java_thread = r15_thread; 6289 #else 6290 java_thread = rdi; 6291 get_thread(java_thread); 6292 #endif // LP64 6293 } 6294 // determine last_java_sp register 6295 if (!last_java_sp->is_valid()) { 6296 last_java_sp = rsp; 6297 } 6298 // debugging support 6299 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 6300 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 6301 #ifdef ASSERT 6302 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 6303 // r12 is the heapbase. 6304 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base");) 6305 #endif // ASSERT 6306 6307 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 6308 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 6309 6310 // push java thread (becomes first argument of C function) 6311 6312 NOT_LP64(push(java_thread); number_of_arguments++); 6313 LP64_ONLY(mov(c_rarg0, r15_thread)); 6314 6315 // set last Java frame before call 6316 assert(last_java_sp != rbp, "can't use ebp/rbp"); 6317 6318 // Only interpreter should have to set fp 6319 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 6320 6321 // do the call, remove parameters 6322 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 6323 6324 // restore the thread (cannot use the pushed argument since arguments 6325 // may be overwritten by C code generated by an optimizing compiler); 6326 // however can use the register value directly if it is callee saved. 6327 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 6328 // rdi & rsi (also r15) are callee saved -> nothing to do 6329 #ifdef ASSERT 6330 guarantee(java_thread != rax, "change this code"); 6331 push(rax); 6332 { Label L; 6333 get_thread(rax); 6334 cmpptr(java_thread, rax); 6335 jcc(Assembler::equal, L); 6336 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); 6337 bind(L); 6338 } 6339 pop(rax); 6340 #endif 6341 } else { 6342 get_thread(java_thread); 6343 } 6344 // reset last Java frame 6345 // Only interpreter should have to clear fp 6346 reset_last_Java_frame(java_thread, true, false); 6347 6348 #ifndef CC_INTERP 6349 // C++ interp handles this in the interpreter 6350 check_and_handle_popframe(java_thread); 6351 check_and_handle_earlyret(java_thread); 6352 #endif /* CC_INTERP */ 6353 6354 if (check_exceptions) { 6355 // check for pending exceptions (java_thread is set upon return) 6356 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 6357 #ifndef _LP64 6358 jump_cc(Assembler::notEqual, 6359 RuntimeAddress(StubRoutines::forward_exception_entry())); 6360 #else 6361 // This used to conditionally jump to forward_exception however it is 6362 // possible if we relocate that the branch will not reach. So we must jump 6363 // around so we can always reach 6364 6365 Label ok; 6366 jcc(Assembler::equal, ok); 6367 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 6368 bind(ok); 6369 #endif // LP64 6370 } 6371 6372 // get oop result if there is one and reset the value in the thread 6373 if (oop_result->is_valid()) { 6374 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 6375 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 6376 verify_oop(oop_result, "broken oop in call_VM_base"); 6377 } 6378 } 6379 6380 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 6381 6382 // Calculate the value for last_Java_sp 6383 // somewhat subtle. call_VM does an intermediate call 6384 // which places a return address on the stack just under the 6385 // stack pointer as the user finsihed with it. This allows 6386 // use to retrieve last_Java_pc from last_Java_sp[-1]. 6387 // On 32bit we then have to push additional args on the stack to accomplish 6388 // the actual requested call. On 64bit call_VM only can use register args 6389 // so the only extra space is the return address that call_VM created. 6390 // This hopefully explains the calculations here. 6391 6392 #ifdef _LP64 6393 // We've pushed one address, correct last_Java_sp 6394 lea(rax, Address(rsp, wordSize)); 6395 #else 6396 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 6397 #endif // LP64 6398 6399 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 6400 6401 } 6402 6403 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 6404 call_VM_leaf_base(entry_point, number_of_arguments); 6405 } 6406 6407 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 6408 pass_arg0(this, arg_0); 6409 call_VM_leaf(entry_point, 1); 6410 } 6411 6412 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 6413 6414 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 6415 pass_arg1(this, arg_1); 6416 pass_arg0(this, arg_0); 6417 call_VM_leaf(entry_point, 2); 6418 } 6419 6420 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 6421 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 6422 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6423 pass_arg2(this, arg_2); 6424 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 6425 pass_arg1(this, arg_1); 6426 pass_arg0(this, arg_0); 6427 call_VM_leaf(entry_point, 3); 6428 } 6429 6430 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 6431 pass_arg0(this, arg_0); 6432 MacroAssembler::call_VM_leaf_base(entry_point, 1); 6433 } 6434 6435 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 6436 6437 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 6438 pass_arg1(this, arg_1); 6439 pass_arg0(this, arg_0); 6440 MacroAssembler::call_VM_leaf_base(entry_point, 2); 6441 } 6442 6443 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 6444 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 6445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6446 pass_arg2(this, arg_2); 6447 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 6448 pass_arg1(this, arg_1); 6449 pass_arg0(this, arg_0); 6450 MacroAssembler::call_VM_leaf_base(entry_point, 3); 6451 } 6452 6453 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 6454 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 6455 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 6456 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 6457 pass_arg3(this, arg_3); 6458 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 6459 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 6460 pass_arg2(this, arg_2); 6461 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 6462 pass_arg1(this, arg_1); 6463 pass_arg0(this, arg_0); 6464 MacroAssembler::call_VM_leaf_base(entry_point, 4); 6465 } 6466 6467 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 6468 } 6469 6470 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 6471 } 6472 6473 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 6474 if (reachable(src1)) { 6475 cmpl(as_Address(src1), imm); 6476 } else { 6477 lea(rscratch1, src1); 6478 cmpl(Address(rscratch1, 0), imm); 6479 } 6480 } 6481 6482 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 6483 assert(!src2.is_lval(), "use cmpptr"); 6484 if (reachable(src2)) { 6485 cmpl(src1, as_Address(src2)); 6486 } else { 6487 lea(rscratch1, src2); 6488 cmpl(src1, Address(rscratch1, 0)); 6489 } 6490 } 6491 6492 void MacroAssembler::cmp32(Register src1, int32_t imm) { 6493 Assembler::cmpl(src1, imm); 6494 } 6495 6496 void MacroAssembler::cmp32(Register src1, Address src2) { 6497 Assembler::cmpl(src1, src2); 6498 } 6499 6500 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 6501 ucomisd(opr1, opr2); 6502 6503 Label L; 6504 if (unordered_is_less) { 6505 movl(dst, -1); 6506 jcc(Assembler::parity, L); 6507 jcc(Assembler::below , L); 6508 movl(dst, 0); 6509 jcc(Assembler::equal , L); 6510 increment(dst); 6511 } else { // unordered is greater 6512 movl(dst, 1); 6513 jcc(Assembler::parity, L); 6514 jcc(Assembler::above , L); 6515 movl(dst, 0); 6516 jcc(Assembler::equal , L); 6517 decrementl(dst); 6518 } 6519 bind(L); 6520 } 6521 6522 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 6523 ucomiss(opr1, opr2); 6524 6525 Label L; 6526 if (unordered_is_less) { 6527 movl(dst, -1); 6528 jcc(Assembler::parity, L); 6529 jcc(Assembler::below , L); 6530 movl(dst, 0); 6531 jcc(Assembler::equal , L); 6532 increment(dst); 6533 } else { // unordered is greater 6534 movl(dst, 1); 6535 jcc(Assembler::parity, L); 6536 jcc(Assembler::above , L); 6537 movl(dst, 0); 6538 jcc(Assembler::equal , L); 6539 decrementl(dst); 6540 } 6541 bind(L); 6542 } 6543 6544 6545 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 6546 if (reachable(src1)) { 6547 cmpb(as_Address(src1), imm); 6548 } else { 6549 lea(rscratch1, src1); 6550 cmpb(Address(rscratch1, 0), imm); 6551 } 6552 } 6553 6554 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 6555 #ifdef _LP64 6556 if (src2.is_lval()) { 6557 movptr(rscratch1, src2); 6558 Assembler::cmpq(src1, rscratch1); 6559 } else if (reachable(src2)) { 6560 cmpq(src1, as_Address(src2)); 6561 } else { 6562 lea(rscratch1, src2); 6563 Assembler::cmpq(src1, Address(rscratch1, 0)); 6564 } 6565 #else 6566 if (src2.is_lval()) { 6567 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 6568 } else { 6569 cmpl(src1, as_Address(src2)); 6570 } 6571 #endif // _LP64 6572 } 6573 6574 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 6575 assert(src2.is_lval(), "not a mem-mem compare"); 6576 #ifdef _LP64 6577 // moves src2's literal address 6578 movptr(rscratch1, src2); 6579 Assembler::cmpq(src1, rscratch1); 6580 #else 6581 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 6582 #endif // _LP64 6583 } 6584 6585 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 6586 if (reachable(adr)) { 6587 if (os::is_MP()) 6588 lock(); 6589 cmpxchgptr(reg, as_Address(adr)); 6590 } else { 6591 lea(rscratch1, adr); 6592 if (os::is_MP()) 6593 lock(); 6594 cmpxchgptr(reg, Address(rscratch1, 0)); 6595 } 6596 } 6597 6598 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 6599 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 6600 } 6601 6602 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 6603 if (reachable(src)) { 6604 Assembler::comisd(dst, as_Address(src)); 6605 } else { 6606 lea(rscratch1, src); 6607 Assembler::comisd(dst, Address(rscratch1, 0)); 6608 } 6609 } 6610 6611 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 6612 if (reachable(src)) { 6613 Assembler::comiss(dst, as_Address(src)); 6614 } else { 6615 lea(rscratch1, src); 6616 Assembler::comiss(dst, Address(rscratch1, 0)); 6617 } 6618 } 6619 6620 6621 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 6622 Condition negated_cond = negate_condition(cond); 6623 Label L; 6624 jcc(negated_cond, L); 6625 atomic_incl(counter_addr); 6626 bind(L); 6627 } 6628 6629 int MacroAssembler::corrected_idivl(Register reg) { 6630 // Full implementation of Java idiv and irem; checks for 6631 // special case as described in JVM spec., p.243 & p.271. 6632 // The function returns the (pc) offset of the idivl 6633 // instruction - may be needed for implicit exceptions. 6634 // 6635 // normal case special case 6636 // 6637 // input : rax,: dividend min_int 6638 // reg: divisor (may not be rax,/rdx) -1 6639 // 6640 // output: rax,: quotient (= rax, idiv reg) min_int 6641 // rdx: remainder (= rax, irem reg) 0 6642 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 6643 const int min_int = 0x80000000; 6644 Label normal_case, special_case; 6645 6646 // check for special case 6647 cmpl(rax, min_int); 6648 jcc(Assembler::notEqual, normal_case); 6649 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 6650 cmpl(reg, -1); 6651 jcc(Assembler::equal, special_case); 6652 6653 // handle normal case 6654 bind(normal_case); 6655 cdql(); 6656 int idivl_offset = offset(); 6657 idivl(reg); 6658 6659 // normal and special case exit 6660 bind(special_case); 6661 6662 return idivl_offset; 6663 } 6664 6665 6666 6667 void MacroAssembler::decrementl(Register reg, int value) { 6668 if (value == min_jint) {subl(reg, value) ; return; } 6669 if (value < 0) { incrementl(reg, -value); return; } 6670 if (value == 0) { ; return; } 6671 if (value == 1 && UseIncDec) { decl(reg) ; return; } 6672 /* else */ { subl(reg, value) ; return; } 6673 } 6674 6675 void MacroAssembler::decrementl(Address dst, int value) { 6676 if (value == min_jint) {subl(dst, value) ; return; } 6677 if (value < 0) { incrementl(dst, -value); return; } 6678 if (value == 0) { ; return; } 6679 if (value == 1 && UseIncDec) { decl(dst) ; return; } 6680 /* else */ { subl(dst, value) ; return; } 6681 } 6682 6683 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 6684 assert (shift_value > 0, "illegal shift value"); 6685 Label _is_positive; 6686 testl (reg, reg); 6687 jcc (Assembler::positive, _is_positive); 6688 int offset = (1 << shift_value) - 1 ; 6689 6690 if (offset == 1) { 6691 incrementl(reg); 6692 } else { 6693 addl(reg, offset); 6694 } 6695 6696 bind (_is_positive); 6697 sarl(reg, shift_value); 6698 } 6699 6700 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 6701 if (reachable(src)) { 6702 Assembler::divsd(dst, as_Address(src)); 6703 } else { 6704 lea(rscratch1, src); 6705 Assembler::divsd(dst, Address(rscratch1, 0)); 6706 } 6707 } 6708 6709 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 6710 if (reachable(src)) { 6711 Assembler::divss(dst, as_Address(src)); 6712 } else { 6713 lea(rscratch1, src); 6714 Assembler::divss(dst, Address(rscratch1, 0)); 6715 } 6716 } 6717 6718 // !defined(COMPILER2) is because of stupid core builds 6719 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) 6720 void MacroAssembler::empty_FPU_stack() { 6721 if (VM_Version::supports_mmx()) { 6722 emms(); 6723 } else { 6724 for (int i = 8; i-- > 0; ) ffree(i); 6725 } 6726 } 6727 #endif // !LP64 || C1 || !C2 6728 6729 6730 // Defines obj, preserves var_size_in_bytes 6731 void MacroAssembler::eden_allocate(Register obj, 6732 Register var_size_in_bytes, 6733 int con_size_in_bytes, 6734 Register t1, 6735 Label& slow_case) { 6736 assert(obj == rax, "obj must be in rax, for cmpxchg"); 6737 assert_different_registers(obj, var_size_in_bytes, t1); 6738 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { 6739 jmp(slow_case); 6740 } else { 6741 Register end = t1; 6742 Label retry; 6743 bind(retry); 6744 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 6745 movptr(obj, heap_top); 6746 if (var_size_in_bytes == noreg) { 6747 lea(end, Address(obj, con_size_in_bytes)); 6748 } else { 6749 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 6750 } 6751 // if end < obj then we wrapped around => object too long => slow case 6752 cmpptr(end, obj); 6753 jcc(Assembler::below, slow_case); 6754 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 6755 jcc(Assembler::above, slow_case); 6756 // Compare obj with the top addr, and if still equal, store the new top addr in 6757 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 6758 // it otherwise. Use lock prefix for atomicity on MPs. 6759 locked_cmpxchgptr(end, heap_top); 6760 jcc(Assembler::notEqual, retry); 6761 } 6762 } 6763 6764 void MacroAssembler::enter() { 6765 push(rbp); 6766 mov(rbp, rsp); 6767 } 6768 6769 void MacroAssembler::fcmp(Register tmp) { 6770 fcmp(tmp, 1, true, true); 6771 } 6772 6773 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 6774 assert(!pop_right || pop_left, "usage error"); 6775 if (VM_Version::supports_cmov()) { 6776 assert(tmp == noreg, "unneeded temp"); 6777 if (pop_left) { 6778 fucomip(index); 6779 } else { 6780 fucomi(index); 6781 } 6782 if (pop_right) { 6783 fpop(); 6784 } 6785 } else { 6786 assert(tmp != noreg, "need temp"); 6787 if (pop_left) { 6788 if (pop_right) { 6789 fcompp(); 6790 } else { 6791 fcomp(index); 6792 } 6793 } else { 6794 fcom(index); 6795 } 6796 // convert FPU condition into eflags condition via rax, 6797 save_rax(tmp); 6798 fwait(); fnstsw_ax(); 6799 sahf(); 6800 restore_rax(tmp); 6801 } 6802 // condition codes set as follows: 6803 // 6804 // CF (corresponds to C0) if x < y 6805 // PF (corresponds to C2) if unordered 6806 // ZF (corresponds to C3) if x = y 6807 } 6808 6809 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 6810 fcmp2int(dst, unordered_is_less, 1, true, true); 6811 } 6812 6813 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 6814 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 6815 Label L; 6816 if (unordered_is_less) { 6817 movl(dst, -1); 6818 jcc(Assembler::parity, L); 6819 jcc(Assembler::below , L); 6820 movl(dst, 0); 6821 jcc(Assembler::equal , L); 6822 increment(dst); 6823 } else { // unordered is greater 6824 movl(dst, 1); 6825 jcc(Assembler::parity, L); 6826 jcc(Assembler::above , L); 6827 movl(dst, 0); 6828 jcc(Assembler::equal , L); 6829 decrementl(dst); 6830 } 6831 bind(L); 6832 } 6833 6834 void MacroAssembler::fld_d(AddressLiteral src) { 6835 fld_d(as_Address(src)); 6836 } 6837 6838 void MacroAssembler::fld_s(AddressLiteral src) { 6839 fld_s(as_Address(src)); 6840 } 6841 6842 void MacroAssembler::fld_x(AddressLiteral src) { 6843 Assembler::fld_x(as_Address(src)); 6844 } 6845 6846 void MacroAssembler::fldcw(AddressLiteral src) { 6847 Assembler::fldcw(as_Address(src)); 6848 } 6849 6850 void MacroAssembler::fpop() { 6851 ffree(); 6852 fincstp(); 6853 } 6854 6855 void MacroAssembler::fremr(Register tmp) { 6856 save_rax(tmp); 6857 { Label L; 6858 bind(L); 6859 fprem(); 6860 fwait(); fnstsw_ax(); 6861 #ifdef _LP64 6862 testl(rax, 0x400); 6863 jcc(Assembler::notEqual, L); 6864 #else 6865 sahf(); 6866 jcc(Assembler::parity, L); 6867 #endif // _LP64 6868 } 6869 restore_rax(tmp); 6870 // Result is in ST0. 6871 // Note: fxch & fpop to get rid of ST1 6872 // (otherwise FPU stack could overflow eventually) 6873 fxch(1); 6874 fpop(); 6875 } 6876 6877 6878 void MacroAssembler::incrementl(AddressLiteral dst) { 6879 if (reachable(dst)) { 6880 incrementl(as_Address(dst)); 6881 } else { 6882 lea(rscratch1, dst); 6883 incrementl(Address(rscratch1, 0)); 6884 } 6885 } 6886 6887 void MacroAssembler::incrementl(ArrayAddress dst) { 6888 incrementl(as_Address(dst)); 6889 } 6890 6891 void MacroAssembler::incrementl(Register reg, int value) { 6892 if (value == min_jint) {addl(reg, value) ; return; } 6893 if (value < 0) { decrementl(reg, -value); return; } 6894 if (value == 0) { ; return; } 6895 if (value == 1 && UseIncDec) { incl(reg) ; return; } 6896 /* else */ { addl(reg, value) ; return; } 6897 } 6898 6899 void MacroAssembler::incrementl(Address dst, int value) { 6900 if (value == min_jint) {addl(dst, value) ; return; } 6901 if (value < 0) { decrementl(dst, -value); return; } 6902 if (value == 0) { ; return; } 6903 if (value == 1 && UseIncDec) { incl(dst) ; return; } 6904 /* else */ { addl(dst, value) ; return; } 6905 } 6906 6907 void MacroAssembler::jump(AddressLiteral dst) { 6908 if (reachable(dst)) { 6909 jmp_literal(dst.target(), dst.rspec()); 6910 } else { 6911 lea(rscratch1, dst); 6912 jmp(rscratch1); 6913 } 6914 } 6915 6916 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 6917 if (reachable(dst)) { 6918 InstructionMark im(this); 6919 relocate(dst.reloc()); 6920 const int short_size = 2; 6921 const int long_size = 6; 6922 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); 6923 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 6924 // 0111 tttn #8-bit disp 6925 emit_byte(0x70 | cc); 6926 emit_byte((offs - short_size) & 0xFF); 6927 } else { 6928 // 0000 1111 1000 tttn #32-bit disp 6929 emit_byte(0x0F); 6930 emit_byte(0x80 | cc); 6931 emit_long(offs - long_size); 6932 } 6933 } else { 6934 #ifdef ASSERT 6935 warning("reversing conditional branch"); 6936 #endif /* ASSERT */ 6937 Label skip; 6938 jccb(reverse[cc], skip); 6939 lea(rscratch1, dst); 6940 Assembler::jmp(rscratch1); 6941 bind(skip); 6942 } 6943 } 6944 6945 void MacroAssembler::ldmxcsr(AddressLiteral src) { 6946 if (reachable(src)) { 6947 Assembler::ldmxcsr(as_Address(src)); 6948 } else { 6949 lea(rscratch1, src); 6950 Assembler::ldmxcsr(Address(rscratch1, 0)); 6951 } 6952 } 6953 6954 int MacroAssembler::load_signed_byte(Register dst, Address src) { 6955 int off; 6956 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 6957 off = offset(); 6958 movsbl(dst, src); // movsxb 6959 } else { 6960 off = load_unsigned_byte(dst, src); 6961 shll(dst, 24); 6962 sarl(dst, 24); 6963 } 6964 return off; 6965 } 6966 6967 // Note: load_signed_short used to be called load_signed_word. 6968 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 6969 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 6970 // The term "word" in HotSpot means a 32- or 64-bit machine word. 6971 int MacroAssembler::load_signed_short(Register dst, Address src) { 6972 int off; 6973 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 6974 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 6975 // version but this is what 64bit has always done. This seems to imply 6976 // that users are only using 32bits worth. 6977 off = offset(); 6978 movswl(dst, src); // movsxw 6979 } else { 6980 off = load_unsigned_short(dst, src); 6981 shll(dst, 16); 6982 sarl(dst, 16); 6983 } 6984 return off; 6985 } 6986 6987 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 6988 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 6989 // and "3.9 Partial Register Penalties", p. 22). 6990 int off; 6991 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 6992 off = offset(); 6993 movzbl(dst, src); // movzxb 6994 } else { 6995 xorl(dst, dst); 6996 off = offset(); 6997 movb(dst, src); 6998 } 6999 return off; 7000 } 7001 7002 // Note: load_unsigned_short used to be called load_unsigned_word. 7003 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 7004 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 7005 // and "3.9 Partial Register Penalties", p. 22). 7006 int off; 7007 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 7008 off = offset(); 7009 movzwl(dst, src); // movzxw 7010 } else { 7011 xorl(dst, dst); 7012 off = offset(); 7013 movw(dst, src); 7014 } 7015 return off; 7016 } 7017 7018 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 7019 switch (size_in_bytes) { 7020 #ifndef _LP64 7021 case 8: 7022 assert(dst2 != noreg, "second dest register required"); 7023 movl(dst, src); 7024 movl(dst2, src.plus_disp(BytesPerInt)); 7025 break; 7026 #else 7027 case 8: movq(dst, src); break; 7028 #endif 7029 case 4: movl(dst, src); break; 7030 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 7031 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 7032 default: ShouldNotReachHere(); 7033 } 7034 } 7035 7036 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 7037 switch (size_in_bytes) { 7038 #ifndef _LP64 7039 case 8: 7040 assert(src2 != noreg, "second source register required"); 7041 movl(dst, src); 7042 movl(dst.plus_disp(BytesPerInt), src2); 7043 break; 7044 #else 7045 case 8: movq(dst, src); break; 7046 #endif 7047 case 4: movl(dst, src); break; 7048 case 2: movw(dst, src); break; 7049 case 1: movb(dst, src); break; 7050 default: ShouldNotReachHere(); 7051 } 7052 } 7053 7054 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 7055 if (reachable(dst)) { 7056 movl(as_Address(dst), src); 7057 } else { 7058 lea(rscratch1, dst); 7059 movl(Address(rscratch1, 0), src); 7060 } 7061 } 7062 7063 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 7064 if (reachable(src)) { 7065 movl(dst, as_Address(src)); 7066 } else { 7067 lea(rscratch1, src); 7068 movl(dst, Address(rscratch1, 0)); 7069 } 7070 } 7071 7072 // C++ bool manipulation 7073 7074 void MacroAssembler::movbool(Register dst, Address src) { 7075 if(sizeof(bool) == 1) 7076 movb(dst, src); 7077 else if(sizeof(bool) == 2) 7078 movw(dst, src); 7079 else if(sizeof(bool) == 4) 7080 movl(dst, src); 7081 else 7082 // unsupported 7083 ShouldNotReachHere(); 7084 } 7085 7086 void MacroAssembler::movbool(Address dst, bool boolconst) { 7087 if(sizeof(bool) == 1) 7088 movb(dst, (int) boolconst); 7089 else if(sizeof(bool) == 2) 7090 movw(dst, (int) boolconst); 7091 else if(sizeof(bool) == 4) 7092 movl(dst, (int) boolconst); 7093 else 7094 // unsupported 7095 ShouldNotReachHere(); 7096 } 7097 7098 void MacroAssembler::movbool(Address dst, Register src) { 7099 if(sizeof(bool) == 1) 7100 movb(dst, src); 7101 else if(sizeof(bool) == 2) 7102 movw(dst, src); 7103 else if(sizeof(bool) == 4) 7104 movl(dst, src); 7105 else 7106 // unsupported 7107 ShouldNotReachHere(); 7108 } 7109 7110 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 7111 movb(as_Address(dst), src); 7112 } 7113 7114 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 7115 if (reachable(src)) { 7116 if (UseXmmLoadAndClearUpper) { 7117 movsd (dst, as_Address(src)); 7118 } else { 7119 movlpd(dst, as_Address(src)); 7120 } 7121 } else { 7122 lea(rscratch1, src); 7123 if (UseXmmLoadAndClearUpper) { 7124 movsd (dst, Address(rscratch1, 0)); 7125 } else { 7126 movlpd(dst, Address(rscratch1, 0)); 7127 } 7128 } 7129 } 7130 7131 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 7132 if (reachable(src)) { 7133 movss(dst, as_Address(src)); 7134 } else { 7135 lea(rscratch1, src); 7136 movss(dst, Address(rscratch1, 0)); 7137 } 7138 } 7139 7140 void MacroAssembler::movptr(Register dst, Register src) { 7141 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 7142 } 7143 7144 void MacroAssembler::movptr(Register dst, Address src) { 7145 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 7146 } 7147 7148 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 7149 void MacroAssembler::movptr(Register dst, intptr_t src) { 7150 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 7151 } 7152 7153 void MacroAssembler::movptr(Address dst, Register src) { 7154 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 7155 } 7156 7157 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 7158 if (reachable(src)) { 7159 Assembler::movsd(dst, as_Address(src)); 7160 } else { 7161 lea(rscratch1, src); 7162 Assembler::movsd(dst, Address(rscratch1, 0)); 7163 } 7164 } 7165 7166 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 7167 if (reachable(src)) { 7168 Assembler::movss(dst, as_Address(src)); 7169 } else { 7170 lea(rscratch1, src); 7171 Assembler::movss(dst, Address(rscratch1, 0)); 7172 } 7173 } 7174 7175 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 7176 if (reachable(src)) { 7177 Assembler::mulsd(dst, as_Address(src)); 7178 } else { 7179 lea(rscratch1, src); 7180 Assembler::mulsd(dst, Address(rscratch1, 0)); 7181 } 7182 } 7183 7184 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 7185 if (reachable(src)) { 7186 Assembler::mulss(dst, as_Address(src)); 7187 } else { 7188 lea(rscratch1, src); 7189 Assembler::mulss(dst, Address(rscratch1, 0)); 7190 } 7191 } 7192 7193 void MacroAssembler::null_check(Register reg, int offset) { 7194 if (needs_explicit_null_check(offset)) { 7195 // provoke OS NULL exception if reg = NULL by 7196 // accessing M[reg] w/o changing any (non-CC) registers 7197 // NOTE: cmpl is plenty here to provoke a segv 7198 cmpptr(rax, Address(reg, 0)); 7199 // Note: should probably use testl(rax, Address(reg, 0)); 7200 // may be shorter code (however, this version of 7201 // testl needs to be implemented first) 7202 } else { 7203 // nothing to do, (later) access of M[reg + offset] 7204 // will provoke OS NULL exception if reg = NULL 7205 } 7206 } 7207 7208 void MacroAssembler::os_breakpoint() { 7209 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 7210 // (e.g., MSVC can't call ps() otherwise) 7211 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 7212 } 7213 7214 void MacroAssembler::pop_CPU_state() { 7215 pop_FPU_state(); 7216 pop_IU_state(); 7217 } 7218 7219 void MacroAssembler::pop_FPU_state() { 7220 NOT_LP64(frstor(Address(rsp, 0));) 7221 LP64_ONLY(fxrstor(Address(rsp, 0));) 7222 addptr(rsp, FPUStateSizeInWords * wordSize); 7223 } 7224 7225 void MacroAssembler::pop_IU_state() { 7226 popa(); 7227 LP64_ONLY(addq(rsp, 8)); 7228 popf(); 7229 } 7230 7231 // Save Integer and Float state 7232 // Warning: Stack must be 16 byte aligned (64bit) 7233 void MacroAssembler::push_CPU_state() { 7234 push_IU_state(); 7235 push_FPU_state(); 7236 } 7237 7238 void MacroAssembler::push_FPU_state() { 7239 subptr(rsp, FPUStateSizeInWords * wordSize); 7240 #ifndef _LP64 7241 fnsave(Address(rsp, 0)); 7242 fwait(); 7243 #else 7244 fxsave(Address(rsp, 0)); 7245 #endif // LP64 7246 } 7247 7248 void MacroAssembler::push_IU_state() { 7249 // Push flags first because pusha kills them 7250 pushf(); 7251 // Make sure rsp stays 16-byte aligned 7252 LP64_ONLY(subq(rsp, 8)); 7253 pusha(); 7254 } 7255 7256 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 7257 // determine java_thread register 7258 if (!java_thread->is_valid()) { 7259 java_thread = rdi; 7260 get_thread(java_thread); 7261 } 7262 // we must set sp to zero to clear frame 7263 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 7264 if (clear_fp) { 7265 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 7266 } 7267 7268 if (clear_pc) 7269 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 7270 7271 } 7272 7273 void MacroAssembler::restore_rax(Register tmp) { 7274 if (tmp == noreg) pop(rax); 7275 else if (tmp != rax) mov(rax, tmp); 7276 } 7277 7278 void MacroAssembler::round_to(Register reg, int modulus) { 7279 addptr(reg, modulus - 1); 7280 andptr(reg, -modulus); 7281 } 7282 7283 void MacroAssembler::save_rax(Register tmp) { 7284 if (tmp == noreg) push(rax); 7285 else if (tmp != rax) mov(tmp, rax); 7286 } 7287 7288 // Write serialization page so VM thread can do a pseudo remote membar. 7289 // We use the current thread pointer to calculate a thread specific 7290 // offset to write to within the page. This minimizes bus traffic 7291 // due to cache line collision. 7292 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 7293 movl(tmp, thread); 7294 shrl(tmp, os::get_serialize_page_shift_count()); 7295 andl(tmp, (os::vm_page_size() - sizeof(int))); 7296 7297 Address index(noreg, tmp, Address::times_1); 7298 ExternalAddress page(os::get_memory_serialize_page()); 7299 7300 // Size of store must match masking code above 7301 movl(as_Address(ArrayAddress(page, index)), tmp); 7302 } 7303 7304 // Calls to C land 7305 // 7306 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 7307 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 7308 // has to be reset to 0. This is required to allow proper stack traversal. 7309 void MacroAssembler::set_last_Java_frame(Register java_thread, 7310 Register last_java_sp, 7311 Register last_java_fp, 7312 address last_java_pc) { 7313 // determine java_thread register 7314 if (!java_thread->is_valid()) { 7315 java_thread = rdi; 7316 get_thread(java_thread); 7317 } 7318 // determine last_java_sp register 7319 if (!last_java_sp->is_valid()) { 7320 last_java_sp = rsp; 7321 } 7322 7323 // last_java_fp is optional 7324 7325 if (last_java_fp->is_valid()) { 7326 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 7327 } 7328 7329 // last_java_pc is optional 7330 7331 if (last_java_pc != NULL) { 7332 lea(Address(java_thread, 7333 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 7334 InternalAddress(last_java_pc)); 7335 7336 } 7337 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 7338 } 7339 7340 void MacroAssembler::shlptr(Register dst, int imm8) { 7341 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 7342 } 7343 7344 void MacroAssembler::shrptr(Register dst, int imm8) { 7345 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 7346 } 7347 7348 void MacroAssembler::sign_extend_byte(Register reg) { 7349 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 7350 movsbl(reg, reg); // movsxb 7351 } else { 7352 shll(reg, 24); 7353 sarl(reg, 24); 7354 } 7355 } 7356 7357 void MacroAssembler::sign_extend_short(Register reg) { 7358 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 7359 movswl(reg, reg); // movsxw 7360 } else { 7361 shll(reg, 16); 7362 sarl(reg, 16); 7363 } 7364 } 7365 7366 void MacroAssembler::testl(Register dst, AddressLiteral src) { 7367 assert(reachable(src), "Address should be reachable"); 7368 testl(dst, as_Address(src)); 7369 } 7370 7371 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 7372 if (reachable(src)) { 7373 Assembler::sqrtsd(dst, as_Address(src)); 7374 } else { 7375 lea(rscratch1, src); 7376 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 7377 } 7378 } 7379 7380 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 7381 if (reachable(src)) { 7382 Assembler::sqrtss(dst, as_Address(src)); 7383 } else { 7384 lea(rscratch1, src); 7385 Assembler::sqrtss(dst, Address(rscratch1, 0)); 7386 } 7387 } 7388 7389 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 7390 if (reachable(src)) { 7391 Assembler::subsd(dst, as_Address(src)); 7392 } else { 7393 lea(rscratch1, src); 7394 Assembler::subsd(dst, Address(rscratch1, 0)); 7395 } 7396 } 7397 7398 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 7399 if (reachable(src)) { 7400 Assembler::subss(dst, as_Address(src)); 7401 } else { 7402 lea(rscratch1, src); 7403 Assembler::subss(dst, Address(rscratch1, 0)); 7404 } 7405 } 7406 7407 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 7408 if (reachable(src)) { 7409 Assembler::ucomisd(dst, as_Address(src)); 7410 } else { 7411 lea(rscratch1, src); 7412 Assembler::ucomisd(dst, Address(rscratch1, 0)); 7413 } 7414 } 7415 7416 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 7417 if (reachable(src)) { 7418 Assembler::ucomiss(dst, as_Address(src)); 7419 } else { 7420 lea(rscratch1, src); 7421 Assembler::ucomiss(dst, Address(rscratch1, 0)); 7422 } 7423 } 7424 7425 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 7426 // Used in sign-bit flipping with aligned address. 7427 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 7428 if (reachable(src)) { 7429 Assembler::xorpd(dst, as_Address(src)); 7430 } else { 7431 lea(rscratch1, src); 7432 Assembler::xorpd(dst, Address(rscratch1, 0)); 7433 } 7434 } 7435 7436 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 7437 // Used in sign-bit flipping with aligned address. 7438 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 7439 if (reachable(src)) { 7440 Assembler::xorps(dst, as_Address(src)); 7441 } else { 7442 lea(rscratch1, src); 7443 Assembler::xorps(dst, Address(rscratch1, 0)); 7444 } 7445 } 7446 7447 // AVX 3-operands instructions 7448 7449 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7450 if (reachable(src)) { 7451 vaddsd(dst, nds, as_Address(src)); 7452 } else { 7453 lea(rscratch1, src); 7454 vaddsd(dst, nds, Address(rscratch1, 0)); 7455 } 7456 } 7457 7458 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7459 if (reachable(src)) { 7460 vaddss(dst, nds, as_Address(src)); 7461 } else { 7462 lea(rscratch1, src); 7463 vaddss(dst, nds, Address(rscratch1, 0)); 7464 } 7465 } 7466 7467 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7468 if (reachable(src)) { 7469 vandpd(dst, nds, as_Address(src)); 7470 } else { 7471 lea(rscratch1, src); 7472 vandpd(dst, nds, Address(rscratch1, 0)); 7473 } 7474 } 7475 7476 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7477 if (reachable(src)) { 7478 vandps(dst, nds, as_Address(src)); 7479 } else { 7480 lea(rscratch1, src); 7481 vandps(dst, nds, Address(rscratch1, 0)); 7482 } 7483 } 7484 7485 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7486 if (reachable(src)) { 7487 vdivsd(dst, nds, as_Address(src)); 7488 } else { 7489 lea(rscratch1, src); 7490 vdivsd(dst, nds, Address(rscratch1, 0)); 7491 } 7492 } 7493 7494 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7495 if (reachable(src)) { 7496 vdivss(dst, nds, as_Address(src)); 7497 } else { 7498 lea(rscratch1, src); 7499 vdivss(dst, nds, Address(rscratch1, 0)); 7500 } 7501 } 7502 7503 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7504 if (reachable(src)) { 7505 vmulsd(dst, nds, as_Address(src)); 7506 } else { 7507 lea(rscratch1, src); 7508 vmulsd(dst, nds, Address(rscratch1, 0)); 7509 } 7510 } 7511 7512 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7513 if (reachable(src)) { 7514 vmulss(dst, nds, as_Address(src)); 7515 } else { 7516 lea(rscratch1, src); 7517 vmulss(dst, nds, Address(rscratch1, 0)); 7518 } 7519 } 7520 7521 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7522 if (reachable(src)) { 7523 vsubsd(dst, nds, as_Address(src)); 7524 } else { 7525 lea(rscratch1, src); 7526 vsubsd(dst, nds, Address(rscratch1, 0)); 7527 } 7528 } 7529 7530 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7531 if (reachable(src)) { 7532 vsubss(dst, nds, as_Address(src)); 7533 } else { 7534 lea(rscratch1, src); 7535 vsubss(dst, nds, Address(rscratch1, 0)); 7536 } 7537 } 7538 7539 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7540 if (reachable(src)) { 7541 vxorpd(dst, nds, as_Address(src)); 7542 } else { 7543 lea(rscratch1, src); 7544 vxorpd(dst, nds, Address(rscratch1, 0)); 7545 } 7546 } 7547 7548 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 7549 if (reachable(src)) { 7550 vxorps(dst, nds, as_Address(src)); 7551 } else { 7552 lea(rscratch1, src); 7553 vxorps(dst, nds, Address(rscratch1, 0)); 7554 } 7555 } 7556 7557 7558 ////////////////////////////////////////////////////////////////////////////////// 7559 #ifndef SERIALGC 7560 7561 void MacroAssembler::g1_write_barrier_pre(Register obj, 7562 Register pre_val, 7563 Register thread, 7564 Register tmp, 7565 bool tosca_live, 7566 bool expand_call) { 7567 7568 // If expand_call is true then we expand the call_VM_leaf macro 7569 // directly to skip generating the check by 7570 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 7571 7572 #ifdef _LP64 7573 assert(thread == r15_thread, "must be"); 7574 #endif // _LP64 7575 7576 Label done; 7577 Label runtime; 7578 7579 assert(pre_val != noreg, "check this code"); 7580 7581 if (obj != noreg) { 7582 assert_different_registers(obj, pre_val, tmp); 7583 assert(pre_val != rax, "check this code"); 7584 } 7585 7586 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 7587 PtrQueue::byte_offset_of_active())); 7588 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 7589 PtrQueue::byte_offset_of_index())); 7590 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 7591 PtrQueue::byte_offset_of_buf())); 7592 7593 7594 // Is marking active? 7595 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { 7596 cmpl(in_progress, 0); 7597 } else { 7598 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); 7599 cmpb(in_progress, 0); 7600 } 7601 jcc(Assembler::equal, done); 7602 7603 // Do we need to load the previous value? 7604 if (obj != noreg) { 7605 load_heap_oop(pre_val, Address(obj, 0)); 7606 } 7607 7608 // Is the previous value null? 7609 cmpptr(pre_val, (int32_t) NULL_WORD); 7610 jcc(Assembler::equal, done); 7611 7612 // Can we store original value in the thread's buffer? 7613 // Is index == 0? 7614 // (The index field is typed as size_t.) 7615 7616 movptr(tmp, index); // tmp := *index_adr 7617 cmpptr(tmp, 0); // tmp == 0? 7618 jcc(Assembler::equal, runtime); // If yes, goto runtime 7619 7620 subptr(tmp, wordSize); // tmp := tmp - wordSize 7621 movptr(index, tmp); // *index_adr := tmp 7622 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 7623 7624 // Record the previous value 7625 movptr(Address(tmp, 0), pre_val); 7626 jmp(done); 7627 7628 bind(runtime); 7629 // save the live input values 7630 if(tosca_live) push(rax); 7631 7632 if (obj != noreg && obj != rax) 7633 push(obj); 7634 7635 if (pre_val != rax) 7636 push(pre_val); 7637 7638 // Calling the runtime using the regular call_VM_leaf mechanism generates 7639 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 7640 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 7641 // 7642 // If we care generating the pre-barrier without a frame (e.g. in the 7643 // intrinsified Reference.get() routine) then ebp might be pointing to 7644 // the caller frame and so this check will most likely fail at runtime. 7645 // 7646 // Expanding the call directly bypasses the generation of the check. 7647 // So when we do not have have a full interpreter frame on the stack 7648 // expand_call should be passed true. 7649 7650 NOT_LP64( push(thread); ) 7651 7652 if (expand_call) { 7653 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 7654 pass_arg1(this, thread); 7655 pass_arg0(this, pre_val); 7656 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 7657 } else { 7658 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 7659 } 7660 7661 NOT_LP64( pop(thread); ) 7662 7663 // save the live input values 7664 if (pre_val != rax) 7665 pop(pre_val); 7666 7667 if (obj != noreg && obj != rax) 7668 pop(obj); 7669 7670 if(tosca_live) pop(rax); 7671 7672 bind(done); 7673 } 7674 7675 void MacroAssembler::g1_write_barrier_post(Register store_addr, 7676 Register new_val, 7677 Register thread, 7678 Register tmp, 7679 Register tmp2) { 7680 #ifdef _LP64 7681 assert(thread == r15_thread, "must be"); 7682 #endif // _LP64 7683 7684 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 7685 PtrQueue::byte_offset_of_index())); 7686 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 7687 PtrQueue::byte_offset_of_buf())); 7688 7689 BarrierSet* bs = Universe::heap()->barrier_set(); 7690 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 7691 Label done; 7692 Label runtime; 7693 7694 // Does store cross heap regions? 7695 7696 movptr(tmp, store_addr); 7697 xorptr(tmp, new_val); 7698 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 7699 jcc(Assembler::equal, done); 7700 7701 // crosses regions, storing NULL? 7702 7703 cmpptr(new_val, (int32_t) NULL_WORD); 7704 jcc(Assembler::equal, done); 7705 7706 // storing region crossing non-NULL, is card already dirty? 7707 7708 ExternalAddress cardtable((address) ct->byte_map_base); 7709 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 7710 #ifdef _LP64 7711 const Register card_addr = tmp; 7712 7713 movq(card_addr, store_addr); 7714 shrq(card_addr, CardTableModRefBS::card_shift); 7715 7716 lea(tmp2, cardtable); 7717 7718 // get the address of the card 7719 addq(card_addr, tmp2); 7720 #else 7721 const Register card_index = tmp; 7722 7723 movl(card_index, store_addr); 7724 shrl(card_index, CardTableModRefBS::card_shift); 7725 7726 Address index(noreg, card_index, Address::times_1); 7727 const Register card_addr = tmp; 7728 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); 7729 #endif 7730 cmpb(Address(card_addr, 0), 0); 7731 jcc(Assembler::equal, done); 7732 7733 // storing a region crossing, non-NULL oop, card is clean. 7734 // dirty card and log. 7735 7736 movb(Address(card_addr, 0), 0); 7737 7738 cmpl(queue_index, 0); 7739 jcc(Assembler::equal, runtime); 7740 subl(queue_index, wordSize); 7741 movptr(tmp2, buffer); 7742 #ifdef _LP64 7743 movslq(rscratch1, queue_index); 7744 addq(tmp2, rscratch1); 7745 movq(Address(tmp2, 0), card_addr); 7746 #else 7747 addl(tmp2, queue_index); 7748 movl(Address(tmp2, 0), card_index); 7749 #endif 7750 jmp(done); 7751 7752 bind(runtime); 7753 // save the live input values 7754 push(store_addr); 7755 push(new_val); 7756 #ifdef _LP64 7757 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 7758 #else 7759 push(thread); 7760 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 7761 pop(thread); 7762 #endif 7763 pop(new_val); 7764 pop(store_addr); 7765 7766 bind(done); 7767 } 7768 7769 #endif // SERIALGC 7770 ////////////////////////////////////////////////////////////////////////////////// 7771 7772 7773 void MacroAssembler::store_check(Register obj) { 7774 // Does a store check for the oop in register obj. The content of 7775 // register obj is destroyed afterwards. 7776 store_check_part_1(obj); 7777 store_check_part_2(obj); 7778 } 7779 7780 void MacroAssembler::store_check(Register obj, Address dst) { 7781 store_check(obj); 7782 } 7783 7784 7785 // split the store check operation so that other instructions can be scheduled inbetween 7786 void MacroAssembler::store_check_part_1(Register obj) { 7787 BarrierSet* bs = Universe::heap()->barrier_set(); 7788 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); 7789 shrptr(obj, CardTableModRefBS::card_shift); 7790 } 7791 7792 void MacroAssembler::store_check_part_2(Register obj) { 7793 BarrierSet* bs = Universe::heap()->barrier_set(); 7794 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); 7795 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 7796 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 7797 7798 // The calculation for byte_map_base is as follows: 7799 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 7800 // So this essentially converts an address to a displacement and 7801 // it will never need to be relocated. On 64bit however the value may be too 7802 // large for a 32bit displacement 7803 7804 intptr_t disp = (intptr_t) ct->byte_map_base; 7805 if (is_simm32(disp)) { 7806 Address cardtable(noreg, obj, Address::times_1, disp); 7807 movb(cardtable, 0); 7808 } else { 7809 // By doing it as an ExternalAddress disp could be converted to a rip-relative 7810 // displacement and done in a single instruction given favorable mapping and 7811 // a smarter version of as_Address. Worst case it is two instructions which 7812 // is no worse off then loading disp into a register and doing as a simple 7813 // Address() as above. 7814 // We can't do as ExternalAddress as the only style since if disp == 0 we'll 7815 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case 7816 // in some cases we'll get a single instruction version. 7817 7818 ExternalAddress cardtable((address)disp); 7819 Address index(noreg, obj, Address::times_1); 7820 movb(as_Address(ArrayAddress(cardtable, index)), 0); 7821 } 7822 } 7823 7824 void MacroAssembler::subptr(Register dst, int32_t imm32) { 7825 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 7826 } 7827 7828 void MacroAssembler::subptr(Register dst, Register src) { 7829 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 7830 } 7831 7832 // C++ bool manipulation 7833 void MacroAssembler::testbool(Register dst) { 7834 if(sizeof(bool) == 1) 7835 testb(dst, 0xff); 7836 else if(sizeof(bool) == 2) { 7837 // testw implementation needed for two byte bools 7838 ShouldNotReachHere(); 7839 } else if(sizeof(bool) == 4) 7840 testl(dst, dst); 7841 else 7842 // unsupported 7843 ShouldNotReachHere(); 7844 } 7845 7846 void MacroAssembler::testptr(Register dst, Register src) { 7847 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 7848 } 7849 7850 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 7851 void MacroAssembler::tlab_allocate(Register obj, 7852 Register var_size_in_bytes, 7853 int con_size_in_bytes, 7854 Register t1, 7855 Register t2, 7856 Label& slow_case) { 7857 assert_different_registers(obj, t1, t2); 7858 assert_different_registers(obj, var_size_in_bytes, t1); 7859 Register end = t2; 7860 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 7861 7862 verify_tlab(); 7863 7864 NOT_LP64(get_thread(thread)); 7865 7866 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 7867 if (var_size_in_bytes == noreg) { 7868 lea(end, Address(obj, con_size_in_bytes)); 7869 } else { 7870 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 7871 } 7872 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 7873 jcc(Assembler::above, slow_case); 7874 7875 // update the tlab top pointer 7876 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 7877 7878 // recover var_size_in_bytes if necessary 7879 if (var_size_in_bytes == end) { 7880 subptr(var_size_in_bytes, obj); 7881 } 7882 verify_tlab(); 7883 } 7884 7885 // Preserves rbx, and rdx. 7886 Register MacroAssembler::tlab_refill(Label& retry, 7887 Label& try_eden, 7888 Label& slow_case) { 7889 Register top = rax; 7890 Register t1 = rcx; 7891 Register t2 = rsi; 7892 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 7893 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 7894 Label do_refill, discard_tlab; 7895 7896 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { 7897 // No allocation in the shared eden. 7898 jmp(slow_case); 7899 } 7900 7901 NOT_LP64(get_thread(thread_reg)); 7902 7903 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 7904 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 7905 7906 // calculate amount of free space 7907 subptr(t1, top); 7908 shrptr(t1, LogHeapWordSize); 7909 7910 // Retain tlab and allocate object in shared space if 7911 // the amount free in the tlab is too large to discard. 7912 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 7913 jcc(Assembler::lessEqual, discard_tlab); 7914 7915 // Retain 7916 // %%% yuck as movptr... 7917 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 7918 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 7919 if (TLABStats) { 7920 // increment number of slow_allocations 7921 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 7922 } 7923 jmp(try_eden); 7924 7925 bind(discard_tlab); 7926 if (TLABStats) { 7927 // increment number of refills 7928 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 7929 // accumulate wastage -- t1 is amount free in tlab 7930 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 7931 } 7932 7933 // if tlab is currently allocated (top or end != null) then 7934 // fill [top, end + alignment_reserve) with array object 7935 testptr(top, top); 7936 jcc(Assembler::zero, do_refill); 7937 7938 // set up the mark word 7939 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 7940 // set the length to the remaining space 7941 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 7942 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 7943 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 7944 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 7945 // set klass to intArrayKlass 7946 // dubious reloc why not an oop reloc? 7947 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 7948 // store klass last. concurrent gcs assumes klass length is valid if 7949 // klass field is not null. 7950 store_klass(top, t1); 7951 7952 movptr(t1, top); 7953 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 7954 incr_allocated_bytes(thread_reg, t1, 0); 7955 7956 // refill the tlab with an eden allocation 7957 bind(do_refill); 7958 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 7959 shlptr(t1, LogHeapWordSize); 7960 // allocate new tlab, address returned in top 7961 eden_allocate(top, t1, 0, t2, slow_case); 7962 7963 // Check that t1 was preserved in eden_allocate. 7964 #ifdef ASSERT 7965 if (UseTLAB) { 7966 Label ok; 7967 Register tsize = rsi; 7968 assert_different_registers(tsize, thread_reg, t1); 7969 push(tsize); 7970 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 7971 shlptr(tsize, LogHeapWordSize); 7972 cmpptr(t1, tsize); 7973 jcc(Assembler::equal, ok); 7974 stop("assert(t1 != tlab size)"); 7975 should_not_reach_here(); 7976 7977 bind(ok); 7978 pop(tsize); 7979 } 7980 #endif 7981 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 7982 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 7983 addptr(top, t1); 7984 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 7985 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 7986 verify_tlab(); 7987 jmp(retry); 7988 7989 return thread_reg; // for use by caller 7990 } 7991 7992 void MacroAssembler::incr_allocated_bytes(Register thread, 7993 Register var_size_in_bytes, 7994 int con_size_in_bytes, 7995 Register t1) { 7996 if (!thread->is_valid()) { 7997 #ifdef _LP64 7998 thread = r15_thread; 7999 #else 8000 assert(t1->is_valid(), "need temp reg"); 8001 thread = t1; 8002 get_thread(thread); 8003 #endif 8004 } 8005 8006 #ifdef _LP64 8007 if (var_size_in_bytes->is_valid()) { 8008 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 8009 } else { 8010 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 8011 } 8012 #else 8013 if (var_size_in_bytes->is_valid()) { 8014 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 8015 } else { 8016 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 8017 } 8018 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 8019 #endif 8020 } 8021 8022 static const double pi_4 = 0.7853981633974483; 8023 8024 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 8025 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 8026 // was attempted in this code; unfortunately it appears that the 8027 // switch to 80-bit precision and back causes this to be 8028 // unprofitable compared with simply performing a runtime call if 8029 // the argument is out of the (-pi/4, pi/4) range. 8030 8031 Register tmp = noreg; 8032 if (!VM_Version::supports_cmov()) { 8033 // fcmp needs a temporary so preserve rbx, 8034 tmp = rbx; 8035 push(tmp); 8036 } 8037 8038 Label slow_case, done; 8039 8040 ExternalAddress pi4_adr = (address)&pi_4; 8041 if (reachable(pi4_adr)) { 8042 // x ?<= pi/4 8043 fld_d(pi4_adr); 8044 fld_s(1); // Stack: X PI/4 X 8045 fabs(); // Stack: |X| PI/4 X 8046 fcmp(tmp); 8047 jcc(Assembler::above, slow_case); 8048 8049 // fastest case: -pi/4 <= x <= pi/4 8050 switch(trig) { 8051 case 's': 8052 fsin(); 8053 break; 8054 case 'c': 8055 fcos(); 8056 break; 8057 case 't': 8058 ftan(); 8059 break; 8060 default: 8061 assert(false, "bad intrinsic"); 8062 break; 8063 } 8064 jmp(done); 8065 } 8066 8067 // slow case: runtime call 8068 bind(slow_case); 8069 // Preserve registers across runtime call 8070 pusha(); 8071 int incoming_argument_and_return_value_offset = -1; 8072 if (num_fpu_regs_in_use > 1) { 8073 // Must preserve all other FPU regs (could alternatively convert 8074 // SharedRuntime::dsin and dcos into assembly routines known not to trash 8075 // FPU state, but can not trust C compiler) 8076 NEEDS_CLEANUP; 8077 // NOTE that in this case we also push the incoming argument to 8078 // the stack and restore it later; we also use this stack slot to 8079 // hold the return value from dsin or dcos. 8080 for (int i = 0; i < num_fpu_regs_in_use; i++) { 8081 subptr(rsp, sizeof(jdouble)); 8082 fstp_d(Address(rsp, 0)); 8083 } 8084 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 8085 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); 8086 } 8087 subptr(rsp, sizeof(jdouble)); 8088 fstp_d(Address(rsp, 0)); 8089 #ifdef _LP64 8090 movdbl(xmm0, Address(rsp, 0)); 8091 #endif // _LP64 8092 8093 // NOTE: we must not use call_VM_leaf here because that requires a 8094 // complete interpreter frame in debug mode -- same bug as 4387334 8095 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 8096 // do proper 64bit abi 8097 8098 NEEDS_CLEANUP; 8099 // Need to add stack banging before this runtime call if it needs to 8100 // be taken; however, there is no generic stack banging routine at 8101 // the MacroAssembler level 8102 switch(trig) { 8103 case 's': 8104 { 8105 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); 8106 } 8107 break; 8108 case 'c': 8109 { 8110 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); 8111 } 8112 break; 8113 case 't': 8114 { 8115 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); 8116 } 8117 break; 8118 default: 8119 assert(false, "bad intrinsic"); 8120 break; 8121 } 8122 #ifdef _LP64 8123 movsd(Address(rsp, 0), xmm0); 8124 fld_d(Address(rsp, 0)); 8125 #endif // _LP64 8126 addptr(rsp, sizeof(jdouble)); 8127 if (num_fpu_regs_in_use > 1) { 8128 // Must save return value to stack and then restore entire FPU stack 8129 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 8130 for (int i = 0; i < num_fpu_regs_in_use; i++) { 8131 fld_d(Address(rsp, 0)); 8132 addptr(rsp, sizeof(jdouble)); 8133 } 8134 } 8135 popa(); 8136 8137 // Come here with result in F-TOS 8138 bind(done); 8139 8140 if (tmp != noreg) { 8141 pop(tmp); 8142 } 8143 } 8144 8145 8146 // Look up the method for a megamorphic invokeinterface call. 8147 // The target method is determined by <intf_klass, itable_index>. 8148 // The receiver klass is in recv_klass. 8149 // On success, the result will be in method_result, and execution falls through. 8150 // On failure, execution transfers to the given label. 8151 void MacroAssembler::lookup_interface_method(Register recv_klass, 8152 Register intf_klass, 8153 RegisterOrConstant itable_index, 8154 Register method_result, 8155 Register scan_temp, 8156 Label& L_no_such_interface) { 8157 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 8158 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 8159 "caller must use same register for non-constant itable index as for method"); 8160 8161 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 8162 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; 8163 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 8164 int scan_step = itableOffsetEntry::size() * wordSize; 8165 int vte_size = vtableEntry::size() * wordSize; 8166 Address::ScaleFactor times_vte_scale = Address::times_ptr; 8167 assert(vte_size == wordSize, "else adjust times_vte_scale"); 8168 8169 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); 8170 8171 // %%% Could store the aligned, prescaled offset in the klassoop. 8172 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 8173 if (HeapWordsPerLong > 1) { 8174 // Round up to align_object_offset boundary 8175 // see code for instanceKlass::start_of_itable! 8176 round_to(scan_temp, BytesPerLong); 8177 } 8178 8179 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 8180 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 8181 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 8182 8183 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 8184 // if (scan->interface() == intf) { 8185 // result = (klass + scan->offset() + itable_index); 8186 // } 8187 // } 8188 Label search, found_method; 8189 8190 for (int peel = 1; peel >= 0; peel--) { 8191 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 8192 cmpptr(intf_klass, method_result); 8193 8194 if (peel) { 8195 jccb(Assembler::equal, found_method); 8196 } else { 8197 jccb(Assembler::notEqual, search); 8198 // (invert the test to fall through to found_method...) 8199 } 8200 8201 if (!peel) break; 8202 8203 bind(search); 8204 8205 // Check that the previous entry is non-null. A null entry means that 8206 // the receiver class doesn't implement the interface, and wasn't the 8207 // same as when the caller was compiled. 8208 testptr(method_result, method_result); 8209 jcc(Assembler::zero, L_no_such_interface); 8210 addptr(scan_temp, scan_step); 8211 } 8212 8213 bind(found_method); 8214 8215 // Got a hit. 8216 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 8217 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 8218 } 8219 8220 8221 void MacroAssembler::check_klass_subtype(Register sub_klass, 8222 Register super_klass, 8223 Register temp_reg, 8224 Label& L_success) { 8225 Label L_failure; 8226 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 8227 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 8228 bind(L_failure); 8229 } 8230 8231 8232 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 8233 Register super_klass, 8234 Register temp_reg, 8235 Label* L_success, 8236 Label* L_failure, 8237 Label* L_slow_path, 8238 RegisterOrConstant super_check_offset) { 8239 assert_different_registers(sub_klass, super_klass, temp_reg); 8240 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 8241 if (super_check_offset.is_register()) { 8242 assert_different_registers(sub_klass, super_klass, 8243 super_check_offset.as_register()); 8244 } else if (must_load_sco) { 8245 assert(temp_reg != noreg, "supply either a temp or a register offset"); 8246 } 8247 8248 Label L_fallthrough; 8249 int label_nulls = 0; 8250 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 8251 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 8252 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 8253 assert(label_nulls <= 1, "at most one NULL in the batch"); 8254 8255 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 8256 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 8257 Address super_check_offset_addr(super_klass, sco_offset); 8258 8259 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 8260 // range of a jccb. If this routine grows larger, reconsider at 8261 // least some of these. 8262 #define local_jcc(assembler_cond, label) \ 8263 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 8264 else jcc( assembler_cond, label) /*omit semi*/ 8265 8266 // Hacked jmp, which may only be used just before L_fallthrough. 8267 #define final_jmp(label) \ 8268 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 8269 else jmp(label) /*omit semi*/ 8270 8271 // If the pointers are equal, we are done (e.g., String[] elements). 8272 // This self-check enables sharing of secondary supertype arrays among 8273 // non-primary types such as array-of-interface. Otherwise, each such 8274 // type would need its own customized SSA. 8275 // We move this check to the front of the fast path because many 8276 // type checks are in fact trivially successful in this manner, 8277 // so we get a nicely predicted branch right at the start of the check. 8278 cmpptr(sub_klass, super_klass); 8279 local_jcc(Assembler::equal, *L_success); 8280 8281 // Check the supertype display: 8282 if (must_load_sco) { 8283 // Positive movl does right thing on LP64. 8284 movl(temp_reg, super_check_offset_addr); 8285 super_check_offset = RegisterOrConstant(temp_reg); 8286 } 8287 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 8288 cmpptr(super_klass, super_check_addr); // load displayed supertype 8289 8290 // This check has worked decisively for primary supers. 8291 // Secondary supers are sought in the super_cache ('super_cache_addr'). 8292 // (Secondary supers are interfaces and very deeply nested subtypes.) 8293 // This works in the same check above because of a tricky aliasing 8294 // between the super_cache and the primary super display elements. 8295 // (The 'super_check_addr' can address either, as the case requires.) 8296 // Note that the cache is updated below if it does not help us find 8297 // what we need immediately. 8298 // So if it was a primary super, we can just fail immediately. 8299 // Otherwise, it's the slow path for us (no success at this point). 8300 8301 if (super_check_offset.is_register()) { 8302 local_jcc(Assembler::equal, *L_success); 8303 cmpl(super_check_offset.as_register(), sc_offset); 8304 if (L_failure == &L_fallthrough) { 8305 local_jcc(Assembler::equal, *L_slow_path); 8306 } else { 8307 local_jcc(Assembler::notEqual, *L_failure); 8308 final_jmp(*L_slow_path); 8309 } 8310 } else if (super_check_offset.as_constant() == sc_offset) { 8311 // Need a slow path; fast failure is impossible. 8312 if (L_slow_path == &L_fallthrough) { 8313 local_jcc(Assembler::equal, *L_success); 8314 } else { 8315 local_jcc(Assembler::notEqual, *L_slow_path); 8316 final_jmp(*L_success); 8317 } 8318 } else { 8319 // No slow path; it's a fast decision. 8320 if (L_failure == &L_fallthrough) { 8321 local_jcc(Assembler::equal, *L_success); 8322 } else { 8323 local_jcc(Assembler::notEqual, *L_failure); 8324 final_jmp(*L_success); 8325 } 8326 } 8327 8328 bind(L_fallthrough); 8329 8330 #undef local_jcc 8331 #undef final_jmp 8332 } 8333 8334 8335 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 8336 Register super_klass, 8337 Register temp_reg, 8338 Register temp2_reg, 8339 Label* L_success, 8340 Label* L_failure, 8341 bool set_cond_codes) { 8342 assert_different_registers(sub_klass, super_klass, temp_reg); 8343 if (temp2_reg != noreg) 8344 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 8345 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 8346 8347 Label L_fallthrough; 8348 int label_nulls = 0; 8349 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 8350 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 8351 assert(label_nulls <= 1, "at most one NULL in the batch"); 8352 8353 // a couple of useful fields in sub_klass: 8354 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 8355 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 8356 Address secondary_supers_addr(sub_klass, ss_offset); 8357 Address super_cache_addr( sub_klass, sc_offset); 8358 8359 // Do a linear scan of the secondary super-klass chain. 8360 // This code is rarely used, so simplicity is a virtue here. 8361 // The repne_scan instruction uses fixed registers, which we must spill. 8362 // Don't worry too much about pre-existing connections with the input regs. 8363 8364 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 8365 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 8366 8367 // Get super_klass value into rax (even if it was in rdi or rcx). 8368 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 8369 if (super_klass != rax || UseCompressedOops) { 8370 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 8371 mov(rax, super_klass); 8372 } 8373 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 8374 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 8375 8376 #ifndef PRODUCT 8377 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 8378 ExternalAddress pst_counter_addr((address) pst_counter); 8379 NOT_LP64( incrementl(pst_counter_addr) ); 8380 LP64_ONLY( lea(rcx, pst_counter_addr) ); 8381 LP64_ONLY( incrementl(Address(rcx, 0)) ); 8382 #endif //PRODUCT 8383 8384 // We will consult the secondary-super array. 8385 movptr(rdi, secondary_supers_addr); 8386 // Load the array length. (Positive movl does right thing on LP64.) 8387 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); 8388 // Skip to start of data. 8389 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); 8390 8391 // Scan RCX words at [RDI] for an occurrence of RAX. 8392 // Set NZ/Z based on last compare. 8393 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 8394 // not change flags (only scas instruction which is repeated sets flags). 8395 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 8396 #ifdef _LP64 8397 // This part is tricky, as values in supers array could be 32 or 64 bit wide 8398 // and we store values in objArrays always encoded, thus we need to encode 8399 // the value of rax before repne. Note that rax is dead after the repne. 8400 if (UseCompressedOops) { 8401 encode_heap_oop_not_null(rax); // Changes flags. 8402 // The superclass is never null; it would be a basic system error if a null 8403 // pointer were to sneak in here. Note that we have already loaded the 8404 // Klass::super_check_offset from the super_klass in the fast path, 8405 // so if there is a null in that register, we are already in the afterlife. 8406 testl(rax,rax); // Set Z = 0 8407 repne_scanl(); 8408 } else 8409 #endif // _LP64 8410 { 8411 testptr(rax,rax); // Set Z = 0 8412 repne_scan(); 8413 } 8414 // Unspill the temp. registers: 8415 if (pushed_rdi) pop(rdi); 8416 if (pushed_rcx) pop(rcx); 8417 if (pushed_rax) pop(rax); 8418 8419 if (set_cond_codes) { 8420 // Special hack for the AD files: rdi is guaranteed non-zero. 8421 assert(!pushed_rdi, "rdi must be left non-NULL"); 8422 // Also, the condition codes are properly set Z/NZ on succeed/failure. 8423 } 8424 8425 if (L_failure == &L_fallthrough) 8426 jccb(Assembler::notEqual, *L_failure); 8427 else jcc(Assembler::notEqual, *L_failure); 8428 8429 // Success. Cache the super we found and proceed in triumph. 8430 movptr(super_cache_addr, super_klass); 8431 8432 if (L_success != &L_fallthrough) { 8433 jmp(*L_success); 8434 } 8435 8436 #undef IS_A_TEMP 8437 8438 bind(L_fallthrough); 8439 } 8440 8441 8442 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 8443 if (VM_Version::supports_cmov()) { 8444 cmovl(cc, dst, src); 8445 } else { 8446 Label L; 8447 jccb(negate_condition(cc), L); 8448 movl(dst, src); 8449 bind(L); 8450 } 8451 } 8452 8453 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 8454 if (VM_Version::supports_cmov()) { 8455 cmovl(cc, dst, src); 8456 } else { 8457 Label L; 8458 jccb(negate_condition(cc), L); 8459 movl(dst, src); 8460 bind(L); 8461 } 8462 } 8463 8464 void MacroAssembler::verify_oop(Register reg, const char* s) { 8465 if (!VerifyOops) return; 8466 8467 // Pass register number to verify_oop_subroutine 8468 char* b = new char[strlen(s) + 50]; 8469 sprintf(b, "verify_oop: %s: %s", reg->name(), s); 8470 #ifdef _LP64 8471 push(rscratch1); // save r10, trashed by movptr() 8472 #endif 8473 push(rax); // save rax, 8474 push(reg); // pass register argument 8475 ExternalAddress buffer((address) b); 8476 // avoid using pushptr, as it modifies scratch registers 8477 // and our contract is not to modify anything 8478 movptr(rax, buffer.addr()); 8479 push(rax); 8480 // call indirectly to solve generation ordering problem 8481 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 8482 call(rax); 8483 // Caller pops the arguments (oop, message) and restores rax, r10 8484 } 8485 8486 8487 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 8488 Register tmp, 8489 int offset) { 8490 intptr_t value = *delayed_value_addr; 8491 if (value != 0) 8492 return RegisterOrConstant(value + offset); 8493 8494 // load indirectly to solve generation ordering problem 8495 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 8496 8497 #ifdef ASSERT 8498 { Label L; 8499 testptr(tmp, tmp); 8500 if (WizardMode) { 8501 jcc(Assembler::notZero, L); 8502 char* buf = new char[40]; 8503 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); 8504 stop(buf); 8505 } else { 8506 jccb(Assembler::notZero, L); 8507 hlt(); 8508 } 8509 bind(L); 8510 } 8511 #endif 8512 8513 if (offset != 0) 8514 addptr(tmp, offset); 8515 8516 return RegisterOrConstant(tmp); 8517 } 8518 8519 8520 // registers on entry: 8521 // - rax ('check' register): required MethodType 8522 // - rcx: method handle 8523 // - rdx, rsi, or ?: killable temp 8524 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, 8525 Register temp_reg, 8526 Label& wrong_method_type) { 8527 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)); 8528 // compare method type against that of the receiver 8529 if (UseCompressedOops) { 8530 load_heap_oop(temp_reg, type_addr); 8531 cmpptr(mtype_reg, temp_reg); 8532 } else { 8533 cmpptr(mtype_reg, type_addr); 8534 } 8535 jcc(Assembler::notEqual, wrong_method_type); 8536 } 8537 8538 8539 // A method handle has a "vmslots" field which gives the size of its 8540 // argument list in JVM stack slots. This field is either located directly 8541 // in every method handle, or else is indirectly accessed through the 8542 // method handle's MethodType. This macro hides the distinction. 8543 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, 8544 Register temp_reg) { 8545 assert_different_registers(vmslots_reg, mh_reg, temp_reg); 8546 // load mh.type.form.vmslots 8547 Register temp2_reg = vmslots_reg; 8548 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg))); 8549 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg))); 8550 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); 8551 } 8552 8553 8554 // registers on entry: 8555 // - rcx: method handle 8556 // - rdx: killable temp (interpreted only) 8557 // - rax: killable temp (compiled only) 8558 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { 8559 assert(mh_reg == rcx, "caller must put MH object in rcx"); 8560 assert_different_registers(mh_reg, temp_reg); 8561 8562 // pick out the interpreted side of the handler 8563 // NOTE: vmentry is not an oop! 8564 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg))); 8565 8566 // off we go... 8567 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); 8568 8569 // for the various stubs which take control at this point, 8570 // see MethodHandles::generate_method_handle_stub 8571 } 8572 8573 8574 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 8575 int extra_slot_offset) { 8576 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 8577 int stackElementSize = Interpreter::stackElementSize; 8578 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 8579 #ifdef ASSERT 8580 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 8581 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 8582 #endif 8583 Register scale_reg = noreg; 8584 Address::ScaleFactor scale_factor = Address::no_scale; 8585 if (arg_slot.is_constant()) { 8586 offset += arg_slot.as_constant() * stackElementSize; 8587 } else { 8588 scale_reg = arg_slot.as_register(); 8589 scale_factor = Address::times(stackElementSize); 8590 } 8591 offset += wordSize; // return PC is on stack 8592 return Address(rsp, scale_reg, scale_factor, offset); 8593 } 8594 8595 8596 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 8597 if (!VerifyOops) return; 8598 8599 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 8600 // Pass register number to verify_oop_subroutine 8601 char* b = new char[strlen(s) + 50]; 8602 sprintf(b, "verify_oop_addr: %s", s); 8603 8604 #ifdef _LP64 8605 push(rscratch1); // save r10, trashed by movptr() 8606 #endif 8607 push(rax); // save rax, 8608 // addr may contain rsp so we will have to adjust it based on the push 8609 // we just did (and on 64 bit we do two pushes) 8610 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 8611 // stores rax into addr which is backwards of what was intended. 8612 if (addr.uses(rsp)) { 8613 lea(rax, addr); 8614 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 8615 } else { 8616 pushptr(addr); 8617 } 8618 8619 ExternalAddress buffer((address) b); 8620 // pass msg argument 8621 // avoid using pushptr, as it modifies scratch registers 8622 // and our contract is not to modify anything 8623 movptr(rax, buffer.addr()); 8624 push(rax); 8625 8626 // call indirectly to solve generation ordering problem 8627 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 8628 call(rax); 8629 // Caller pops the arguments (addr, message) and restores rax, r10. 8630 } 8631 8632 void MacroAssembler::verify_tlab() { 8633 #ifdef ASSERT 8634 if (UseTLAB && VerifyOops) { 8635 Label next, ok; 8636 Register t1 = rsi; 8637 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 8638 8639 push(t1); 8640 NOT_LP64(push(thread_reg)); 8641 NOT_LP64(get_thread(thread_reg)); 8642 8643 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 8644 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 8645 jcc(Assembler::aboveEqual, next); 8646 stop("assert(top >= start)"); 8647 should_not_reach_here(); 8648 8649 bind(next); 8650 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 8651 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 8652 jcc(Assembler::aboveEqual, ok); 8653 stop("assert(top <= end)"); 8654 should_not_reach_here(); 8655 8656 bind(ok); 8657 NOT_LP64(pop(thread_reg)); 8658 pop(t1); 8659 } 8660 #endif 8661 } 8662 8663 class ControlWord { 8664 public: 8665 int32_t _value; 8666 8667 int rounding_control() const { return (_value >> 10) & 3 ; } 8668 int precision_control() const { return (_value >> 8) & 3 ; } 8669 bool precision() const { return ((_value >> 5) & 1) != 0; } 8670 bool underflow() const { return ((_value >> 4) & 1) != 0; } 8671 bool overflow() const { return ((_value >> 3) & 1) != 0; } 8672 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 8673 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 8674 bool invalid() const { return ((_value >> 0) & 1) != 0; } 8675 8676 void print() const { 8677 // rounding control 8678 const char* rc; 8679 switch (rounding_control()) { 8680 case 0: rc = "round near"; break; 8681 case 1: rc = "round down"; break; 8682 case 2: rc = "round up "; break; 8683 case 3: rc = "chop "; break; 8684 }; 8685 // precision control 8686 const char* pc; 8687 switch (precision_control()) { 8688 case 0: pc = "24 bits "; break; 8689 case 1: pc = "reserved"; break; 8690 case 2: pc = "53 bits "; break; 8691 case 3: pc = "64 bits "; break; 8692 }; 8693 // flags 8694 char f[9]; 8695 f[0] = ' '; 8696 f[1] = ' '; 8697 f[2] = (precision ()) ? 'P' : 'p'; 8698 f[3] = (underflow ()) ? 'U' : 'u'; 8699 f[4] = (overflow ()) ? 'O' : 'o'; 8700 f[5] = (zero_divide ()) ? 'Z' : 'z'; 8701 f[6] = (denormalized()) ? 'D' : 'd'; 8702 f[7] = (invalid ()) ? 'I' : 'i'; 8703 f[8] = '\x0'; 8704 // output 8705 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 8706 } 8707 8708 }; 8709 8710 class StatusWord { 8711 public: 8712 int32_t _value; 8713 8714 bool busy() const { return ((_value >> 15) & 1) != 0; } 8715 bool C3() const { return ((_value >> 14) & 1) != 0; } 8716 bool C2() const { return ((_value >> 10) & 1) != 0; } 8717 bool C1() const { return ((_value >> 9) & 1) != 0; } 8718 bool C0() const { return ((_value >> 8) & 1) != 0; } 8719 int top() const { return (_value >> 11) & 7 ; } 8720 bool error_status() const { return ((_value >> 7) & 1) != 0; } 8721 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 8722 bool precision() const { return ((_value >> 5) & 1) != 0; } 8723 bool underflow() const { return ((_value >> 4) & 1) != 0; } 8724 bool overflow() const { return ((_value >> 3) & 1) != 0; } 8725 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 8726 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 8727 bool invalid() const { return ((_value >> 0) & 1) != 0; } 8728 8729 void print() const { 8730 // condition codes 8731 char c[5]; 8732 c[0] = (C3()) ? '3' : '-'; 8733 c[1] = (C2()) ? '2' : '-'; 8734 c[2] = (C1()) ? '1' : '-'; 8735 c[3] = (C0()) ? '0' : '-'; 8736 c[4] = '\x0'; 8737 // flags 8738 char f[9]; 8739 f[0] = (error_status()) ? 'E' : '-'; 8740 f[1] = (stack_fault ()) ? 'S' : '-'; 8741 f[2] = (precision ()) ? 'P' : '-'; 8742 f[3] = (underflow ()) ? 'U' : '-'; 8743 f[4] = (overflow ()) ? 'O' : '-'; 8744 f[5] = (zero_divide ()) ? 'Z' : '-'; 8745 f[6] = (denormalized()) ? 'D' : '-'; 8746 f[7] = (invalid ()) ? 'I' : '-'; 8747 f[8] = '\x0'; 8748 // output 8749 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 8750 } 8751 8752 }; 8753 8754 class TagWord { 8755 public: 8756 int32_t _value; 8757 8758 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 8759 8760 void print() const { 8761 printf("%04x", _value & 0xFFFF); 8762 } 8763 8764 }; 8765 8766 class FPU_Register { 8767 public: 8768 int32_t _m0; 8769 int32_t _m1; 8770 int16_t _ex; 8771 8772 bool is_indefinite() const { 8773 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 8774 } 8775 8776 void print() const { 8777 char sign = (_ex < 0) ? '-' : '+'; 8778 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 8779 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 8780 }; 8781 8782 }; 8783 8784 class FPU_State { 8785 public: 8786 enum { 8787 register_size = 10, 8788 number_of_registers = 8, 8789 register_mask = 7 8790 }; 8791 8792 ControlWord _control_word; 8793 StatusWord _status_word; 8794 TagWord _tag_word; 8795 int32_t _error_offset; 8796 int32_t _error_selector; 8797 int32_t _data_offset; 8798 int32_t _data_selector; 8799 int8_t _register[register_size * number_of_registers]; 8800 8801 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 8802 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 8803 8804 const char* tag_as_string(int tag) const { 8805 switch (tag) { 8806 case 0: return "valid"; 8807 case 1: return "zero"; 8808 case 2: return "special"; 8809 case 3: return "empty"; 8810 } 8811 ShouldNotReachHere(); 8812 return NULL; 8813 } 8814 8815 void print() const { 8816 // print computation registers 8817 { int t = _status_word.top(); 8818 for (int i = 0; i < number_of_registers; i++) { 8819 int j = (i - t) & register_mask; 8820 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 8821 st(j)->print(); 8822 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 8823 } 8824 } 8825 printf("\n"); 8826 // print control registers 8827 printf("ctrl = "); _control_word.print(); printf("\n"); 8828 printf("stat = "); _status_word .print(); printf("\n"); 8829 printf("tags = "); _tag_word .print(); printf("\n"); 8830 } 8831 8832 }; 8833 8834 class Flag_Register { 8835 public: 8836 int32_t _value; 8837 8838 bool overflow() const { return ((_value >> 11) & 1) != 0; } 8839 bool direction() const { return ((_value >> 10) & 1) != 0; } 8840 bool sign() const { return ((_value >> 7) & 1) != 0; } 8841 bool zero() const { return ((_value >> 6) & 1) != 0; } 8842 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 8843 bool parity() const { return ((_value >> 2) & 1) != 0; } 8844 bool carry() const { return ((_value >> 0) & 1) != 0; } 8845 8846 void print() const { 8847 // flags 8848 char f[8]; 8849 f[0] = (overflow ()) ? 'O' : '-'; 8850 f[1] = (direction ()) ? 'D' : '-'; 8851 f[2] = (sign ()) ? 'S' : '-'; 8852 f[3] = (zero ()) ? 'Z' : '-'; 8853 f[4] = (auxiliary_carry()) ? 'A' : '-'; 8854 f[5] = (parity ()) ? 'P' : '-'; 8855 f[6] = (carry ()) ? 'C' : '-'; 8856 f[7] = '\x0'; 8857 // output 8858 printf("%08x flags = %s", _value, f); 8859 } 8860 8861 }; 8862 8863 class IU_Register { 8864 public: 8865 int32_t _value; 8866 8867 void print() const { 8868 printf("%08x %11d", _value, _value); 8869 } 8870 8871 }; 8872 8873 class IU_State { 8874 public: 8875 Flag_Register _eflags; 8876 IU_Register _rdi; 8877 IU_Register _rsi; 8878 IU_Register _rbp; 8879 IU_Register _rsp; 8880 IU_Register _rbx; 8881 IU_Register _rdx; 8882 IU_Register _rcx; 8883 IU_Register _rax; 8884 8885 void print() const { 8886 // computation registers 8887 printf("rax, = "); _rax.print(); printf("\n"); 8888 printf("rbx, = "); _rbx.print(); printf("\n"); 8889 printf("rcx = "); _rcx.print(); printf("\n"); 8890 printf("rdx = "); _rdx.print(); printf("\n"); 8891 printf("rdi = "); _rdi.print(); printf("\n"); 8892 printf("rsi = "); _rsi.print(); printf("\n"); 8893 printf("rbp, = "); _rbp.print(); printf("\n"); 8894 printf("rsp = "); _rsp.print(); printf("\n"); 8895 printf("\n"); 8896 // control registers 8897 printf("flgs = "); _eflags.print(); printf("\n"); 8898 } 8899 }; 8900 8901 8902 class CPU_State { 8903 public: 8904 FPU_State _fpu_state; 8905 IU_State _iu_state; 8906 8907 void print() const { 8908 printf("--------------------------------------------------\n"); 8909 _iu_state .print(); 8910 printf("\n"); 8911 _fpu_state.print(); 8912 printf("--------------------------------------------------\n"); 8913 } 8914 8915 }; 8916 8917 8918 static void _print_CPU_state(CPU_State* state) { 8919 state->print(); 8920 }; 8921 8922 8923 void MacroAssembler::print_CPU_state() { 8924 push_CPU_state(); 8925 push(rsp); // pass CPU state 8926 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 8927 addptr(rsp, wordSize); // discard argument 8928 pop_CPU_state(); 8929 } 8930 8931 8932 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 8933 static int counter = 0; 8934 FPU_State* fs = &state->_fpu_state; 8935 counter++; 8936 // For leaf calls, only verify that the top few elements remain empty. 8937 // We only need 1 empty at the top for C2 code. 8938 if( stack_depth < 0 ) { 8939 if( fs->tag_for_st(7) != 3 ) { 8940 printf("FPR7 not empty\n"); 8941 state->print(); 8942 assert(false, "error"); 8943 return false; 8944 } 8945 return true; // All other stack states do not matter 8946 } 8947 8948 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 8949 "bad FPU control word"); 8950 8951 // compute stack depth 8952 int i = 0; 8953 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 8954 int d = i; 8955 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 8956 // verify findings 8957 if (i != FPU_State::number_of_registers) { 8958 // stack not contiguous 8959 printf("%s: stack not contiguous at ST%d\n", s, i); 8960 state->print(); 8961 assert(false, "error"); 8962 return false; 8963 } 8964 // check if computed stack depth corresponds to expected stack depth 8965 if (stack_depth < 0) { 8966 // expected stack depth is -stack_depth or less 8967 if (d > -stack_depth) { 8968 // too many elements on the stack 8969 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 8970 state->print(); 8971 assert(false, "error"); 8972 return false; 8973 } 8974 } else { 8975 // expected stack depth is stack_depth 8976 if (d != stack_depth) { 8977 // wrong stack depth 8978 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 8979 state->print(); 8980 assert(false, "error"); 8981 return false; 8982 } 8983 } 8984 // everything is cool 8985 return true; 8986 } 8987 8988 8989 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 8990 if (!VerifyFPU) return; 8991 push_CPU_state(); 8992 push(rsp); // pass CPU state 8993 ExternalAddress msg((address) s); 8994 // pass message string s 8995 pushptr(msg.addr()); 8996 push(stack_depth); // pass stack depth 8997 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 8998 addptr(rsp, 3 * wordSize); // discard arguments 8999 // check for error 9000 { Label L; 9001 testl(rax, rax); 9002 jcc(Assembler::notZero, L); 9003 int3(); // break if error condition 9004 bind(L); 9005 } 9006 pop_CPU_state(); 9007 } 9008 9009 void MacroAssembler::load_klass(Register dst, Register src) { 9010 #ifdef _LP64 9011 if (UseCompressedOops) { 9012 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 9013 decode_heap_oop_not_null(dst); 9014 } else 9015 #endif 9016 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 9017 } 9018 9019 void MacroAssembler::load_prototype_header(Register dst, Register src) { 9020 #ifdef _LP64 9021 if (UseCompressedOops) { 9022 assert (Universe::heap() != NULL, "java heap should be initialized"); 9023 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 9024 if (Universe::narrow_oop_shift() != 0) { 9025 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9026 if (LogMinObjAlignmentInBytes == Address::times_8) { 9027 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); 9028 } else { 9029 // OK to use shift since we don't need to preserve flags. 9030 shlq(dst, LogMinObjAlignmentInBytes); 9031 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset())); 9032 } 9033 } else { 9034 movq(dst, Address(dst, Klass::prototype_header_offset())); 9035 } 9036 } else 9037 #endif 9038 { 9039 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 9040 movptr(dst, Address(dst, Klass::prototype_header_offset())); 9041 } 9042 } 9043 9044 void MacroAssembler::store_klass(Register dst, Register src) { 9045 #ifdef _LP64 9046 if (UseCompressedOops) { 9047 encode_heap_oop_not_null(src); 9048 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 9049 } else 9050 #endif 9051 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 9052 } 9053 9054 void MacroAssembler::load_heap_oop(Register dst, Address src) { 9055 #ifdef _LP64 9056 if (UseCompressedOops) { 9057 movl(dst, src); 9058 decode_heap_oop(dst); 9059 } else 9060 #endif 9061 movptr(dst, src); 9062 } 9063 9064 // Doesn't do verfication, generates fixed size code 9065 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 9066 #ifdef _LP64 9067 if (UseCompressedOops) { 9068 movl(dst, src); 9069 decode_heap_oop_not_null(dst); 9070 } else 9071 #endif 9072 movptr(dst, src); 9073 } 9074 9075 void MacroAssembler::store_heap_oop(Address dst, Register src) { 9076 #ifdef _LP64 9077 if (UseCompressedOops) { 9078 assert(!dst.uses(src), "not enough registers"); 9079 encode_heap_oop(src); 9080 movl(dst, src); 9081 } else 9082 #endif 9083 movptr(dst, src); 9084 } 9085 9086 // Used for storing NULLs. 9087 void MacroAssembler::store_heap_oop_null(Address dst) { 9088 #ifdef _LP64 9089 if (UseCompressedOops) { 9090 movl(dst, (int32_t)NULL_WORD); 9091 } else { 9092 movslq(dst, (int32_t)NULL_WORD); 9093 } 9094 #else 9095 movl(dst, (int32_t)NULL_WORD); 9096 #endif 9097 } 9098 9099 #ifdef _LP64 9100 void MacroAssembler::store_klass_gap(Register dst, Register src) { 9101 if (UseCompressedOops) { 9102 // Store to klass gap in destination 9103 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 9104 } 9105 } 9106 9107 #ifdef ASSERT 9108 void MacroAssembler::verify_heapbase(const char* msg) { 9109 assert (UseCompressedOops, "should be compressed"); 9110 assert (Universe::heap() != NULL, "java heap should be initialized"); 9111 if (CheckCompressedOops) { 9112 Label ok; 9113 push(rscratch1); // cmpptr trashes rscratch1 9114 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); 9115 jcc(Assembler::equal, ok); 9116 stop(msg); 9117 bind(ok); 9118 pop(rscratch1); 9119 } 9120 } 9121 #endif 9122 9123 // Algorithm must match oop.inline.hpp encode_heap_oop. 9124 void MacroAssembler::encode_heap_oop(Register r) { 9125 #ifdef ASSERT 9126 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 9127 #endif 9128 verify_oop(r, "broken oop in encode_heap_oop"); 9129 if (Universe::narrow_oop_base() == NULL) { 9130 if (Universe::narrow_oop_shift() != 0) { 9131 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9132 shrq(r, LogMinObjAlignmentInBytes); 9133 } 9134 return; 9135 } 9136 testq(r, r); 9137 cmovq(Assembler::equal, r, r12_heapbase); 9138 subq(r, r12_heapbase); 9139 shrq(r, LogMinObjAlignmentInBytes); 9140 } 9141 9142 void MacroAssembler::encode_heap_oop_not_null(Register r) { 9143 #ifdef ASSERT 9144 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 9145 if (CheckCompressedOops) { 9146 Label ok; 9147 testq(r, r); 9148 jcc(Assembler::notEqual, ok); 9149 stop("null oop passed to encode_heap_oop_not_null"); 9150 bind(ok); 9151 } 9152 #endif 9153 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 9154 if (Universe::narrow_oop_base() != NULL) { 9155 subq(r, r12_heapbase); 9156 } 9157 if (Universe::narrow_oop_shift() != 0) { 9158 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9159 shrq(r, LogMinObjAlignmentInBytes); 9160 } 9161 } 9162 9163 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 9164 #ifdef ASSERT 9165 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 9166 if (CheckCompressedOops) { 9167 Label ok; 9168 testq(src, src); 9169 jcc(Assembler::notEqual, ok); 9170 stop("null oop passed to encode_heap_oop_not_null2"); 9171 bind(ok); 9172 } 9173 #endif 9174 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 9175 if (dst != src) { 9176 movq(dst, src); 9177 } 9178 if (Universe::narrow_oop_base() != NULL) { 9179 subq(dst, r12_heapbase); 9180 } 9181 if (Universe::narrow_oop_shift() != 0) { 9182 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9183 shrq(dst, LogMinObjAlignmentInBytes); 9184 } 9185 } 9186 9187 void MacroAssembler::decode_heap_oop(Register r) { 9188 #ifdef ASSERT 9189 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 9190 #endif 9191 if (Universe::narrow_oop_base() == NULL) { 9192 if (Universe::narrow_oop_shift() != 0) { 9193 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9194 shlq(r, LogMinObjAlignmentInBytes); 9195 } 9196 } else { 9197 Label done; 9198 shlq(r, LogMinObjAlignmentInBytes); 9199 jccb(Assembler::equal, done); 9200 addq(r, r12_heapbase); 9201 bind(done); 9202 } 9203 verify_oop(r, "broken oop in decode_heap_oop"); 9204 } 9205 9206 void MacroAssembler::decode_heap_oop_not_null(Register r) { 9207 // Note: it will change flags 9208 assert (UseCompressedOops, "should only be used for compressed headers"); 9209 assert (Universe::heap() != NULL, "java heap should be initialized"); 9210 // Cannot assert, unverified entry point counts instructions (see .ad file) 9211 // vtableStubs also counts instructions in pd_code_size_limit. 9212 // Also do not verify_oop as this is called by verify_oop. 9213 if (Universe::narrow_oop_shift() != 0) { 9214 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9215 shlq(r, LogMinObjAlignmentInBytes); 9216 if (Universe::narrow_oop_base() != NULL) { 9217 addq(r, r12_heapbase); 9218 } 9219 } else { 9220 assert (Universe::narrow_oop_base() == NULL, "sanity"); 9221 } 9222 } 9223 9224 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 9225 // Note: it will change flags 9226 assert (UseCompressedOops, "should only be used for compressed headers"); 9227 assert (Universe::heap() != NULL, "java heap should be initialized"); 9228 // Cannot assert, unverified entry point counts instructions (see .ad file) 9229 // vtableStubs also counts instructions in pd_code_size_limit. 9230 // Also do not verify_oop as this is called by verify_oop. 9231 if (Universe::narrow_oop_shift() != 0) { 9232 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 9233 if (LogMinObjAlignmentInBytes == Address::times_8) { 9234 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 9235 } else { 9236 if (dst != src) { 9237 movq(dst, src); 9238 } 9239 shlq(dst, LogMinObjAlignmentInBytes); 9240 if (Universe::narrow_oop_base() != NULL) { 9241 addq(dst, r12_heapbase); 9242 } 9243 } 9244 } else { 9245 assert (Universe::narrow_oop_base() == NULL, "sanity"); 9246 if (dst != src) { 9247 movq(dst, src); 9248 } 9249 } 9250 } 9251 9252 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 9253 assert (UseCompressedOops, "should only be used for compressed headers"); 9254 assert (Universe::heap() != NULL, "java heap should be initialized"); 9255 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 9256 int oop_index = oop_recorder()->find_index(obj); 9257 RelocationHolder rspec = oop_Relocation::spec(oop_index); 9258 mov_narrow_oop(dst, oop_index, rspec); 9259 } 9260 9261 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 9262 assert (UseCompressedOops, "should only be used for compressed headers"); 9263 assert (Universe::heap() != NULL, "java heap should be initialized"); 9264 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 9265 int oop_index = oop_recorder()->find_index(obj); 9266 RelocationHolder rspec = oop_Relocation::spec(oop_index); 9267 mov_narrow_oop(dst, oop_index, rspec); 9268 } 9269 9270 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 9271 assert (UseCompressedOops, "should only be used for compressed headers"); 9272 assert (Universe::heap() != NULL, "java heap should be initialized"); 9273 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 9274 int oop_index = oop_recorder()->find_index(obj); 9275 RelocationHolder rspec = oop_Relocation::spec(oop_index); 9276 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 9277 } 9278 9279 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 9280 assert (UseCompressedOops, "should only be used for compressed headers"); 9281 assert (Universe::heap() != NULL, "java heap should be initialized"); 9282 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 9283 int oop_index = oop_recorder()->find_index(obj); 9284 RelocationHolder rspec = oop_Relocation::spec(oop_index); 9285 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 9286 } 9287 9288 void MacroAssembler::reinit_heapbase() { 9289 if (UseCompressedOops) { 9290 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); 9291 } 9292 } 9293 #endif // _LP64 9294 9295 // IndexOf for constant substrings with size >= 8 chars 9296 // which don't need to be loaded through stack. 9297 void MacroAssembler::string_indexofC8(Register str1, Register str2, 9298 Register cnt1, Register cnt2, 9299 int int_cnt2, Register result, 9300 XMMRegister vec, Register tmp) { 9301 ShortBranchVerifier sbv(this); 9302 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 9303 9304 // This method uses pcmpestri inxtruction with bound registers 9305 // inputs: 9306 // xmm - substring 9307 // rax - substring length (elements count) 9308 // mem - scanned string 9309 // rdx - string length (elements count) 9310 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 9311 // outputs: 9312 // rcx - matched index in string 9313 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 9314 9315 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 9316 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 9317 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 9318 9319 // Note, inline_string_indexOf() generates checks: 9320 // if (substr.count > string.count) return -1; 9321 // if (substr.count == 0) return 0; 9322 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); 9323 9324 // Load substring. 9325 movdqu(vec, Address(str2, 0)); 9326 movl(cnt2, int_cnt2); 9327 movptr(result, str1); // string addr 9328 9329 if (int_cnt2 > 8) { 9330 jmpb(SCAN_TO_SUBSTR); 9331 9332 // Reload substr for rescan, this code 9333 // is executed only for large substrings (> 8 chars) 9334 bind(RELOAD_SUBSTR); 9335 movdqu(vec, Address(str2, 0)); 9336 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 9337 9338 bind(RELOAD_STR); 9339 // We came here after the beginning of the substring was 9340 // matched but the rest of it was not so we need to search 9341 // again. Start from the next element after the previous match. 9342 9343 // cnt2 is number of substring reminding elements and 9344 // cnt1 is number of string reminding elements when cmp failed. 9345 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 9346 subl(cnt1, cnt2); 9347 addl(cnt1, int_cnt2); 9348 movl(cnt2, int_cnt2); // Now restore cnt2 9349 9350 decrementl(cnt1); // Shift to next element 9351 cmpl(cnt1, cnt2); 9352 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 9353 9354 addptr(result, 2); 9355 9356 } // (int_cnt2 > 8) 9357 9358 // Scan string for start of substr in 16-byte vectors 9359 bind(SCAN_TO_SUBSTR); 9360 pcmpestri(vec, Address(result, 0), 0x0d); 9361 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 9362 subl(cnt1, 8); 9363 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 9364 cmpl(cnt1, cnt2); 9365 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 9366 addptr(result, 16); 9367 jmpb(SCAN_TO_SUBSTR); 9368 9369 // Found a potential substr 9370 bind(FOUND_CANDIDATE); 9371 // Matched whole vector if first element matched (tmp(rcx) == 0). 9372 if (int_cnt2 == 8) { 9373 jccb(Assembler::overflow, RET_FOUND); // OF == 1 9374 } else { // int_cnt2 > 8 9375 jccb(Assembler::overflow, FOUND_SUBSTR); 9376 } 9377 // After pcmpestri tmp(rcx) contains matched element index 9378 // Compute start addr of substr 9379 lea(result, Address(result, tmp, Address::times_2)); 9380 9381 // Make sure string is still long enough 9382 subl(cnt1, tmp); 9383 cmpl(cnt1, cnt2); 9384 if (int_cnt2 == 8) { 9385 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 9386 } else { // int_cnt2 > 8 9387 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 9388 } 9389 // Left less then substring. 9390 9391 bind(RET_NOT_FOUND); 9392 movl(result, -1); 9393 jmpb(EXIT); 9394 9395 if (int_cnt2 > 8) { 9396 // This code is optimized for the case when whole substring 9397 // is matched if its head is matched. 9398 bind(MATCH_SUBSTR_HEAD); 9399 pcmpestri(vec, Address(result, 0), 0x0d); 9400 // Reload only string if does not match 9401 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 9402 9403 Label CONT_SCAN_SUBSTR; 9404 // Compare the rest of substring (> 8 chars). 9405 bind(FOUND_SUBSTR); 9406 // First 8 chars are already matched. 9407 negptr(cnt2); 9408 addptr(cnt2, 8); 9409 9410 bind(SCAN_SUBSTR); 9411 subl(cnt1, 8); 9412 cmpl(cnt2, -8); // Do not read beyond substring 9413 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 9414 // Back-up strings to avoid reading beyond substring: 9415 // cnt1 = cnt1 - cnt2 + 8 9416 addl(cnt1, cnt2); // cnt2 is negative 9417 addl(cnt1, 8); 9418 movl(cnt2, 8); negptr(cnt2); 9419 bind(CONT_SCAN_SUBSTR); 9420 if (int_cnt2 < (int)G) { 9421 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); 9422 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); 9423 } else { 9424 // calculate index in register to avoid integer overflow (int_cnt2*2) 9425 movl(tmp, int_cnt2); 9426 addptr(tmp, cnt2); 9427 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); 9428 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); 9429 } 9430 // Need to reload strings pointers if not matched whole vector 9431 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 9432 addptr(cnt2, 8); 9433 jcc(Assembler::negative, SCAN_SUBSTR); 9434 // Fall through if found full substring 9435 9436 } // (int_cnt2 > 8) 9437 9438 bind(RET_FOUND); 9439 // Found result if we matched full small substring. 9440 // Compute substr offset 9441 subptr(result, str1); 9442 shrl(result, 1); // index 9443 bind(EXIT); 9444 9445 } // string_indexofC8 9446 9447 // Small strings are loaded through stack if they cross page boundary. 9448 void MacroAssembler::string_indexof(Register str1, Register str2, 9449 Register cnt1, Register cnt2, 9450 int int_cnt2, Register result, 9451 XMMRegister vec, Register tmp) { 9452 ShortBranchVerifier sbv(this); 9453 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 9454 // 9455 // int_cnt2 is length of small (< 8 chars) constant substring 9456 // or (-1) for non constant substring in which case its length 9457 // is in cnt2 register. 9458 // 9459 // Note, inline_string_indexOf() generates checks: 9460 // if (substr.count > string.count) return -1; 9461 // if (substr.count == 0) return 0; 9462 // 9463 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); 9464 9465 // This method uses pcmpestri inxtruction with bound registers 9466 // inputs: 9467 // xmm - substring 9468 // rax - substring length (elements count) 9469 // mem - scanned string 9470 // rdx - string length (elements count) 9471 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 9472 // outputs: 9473 // rcx - matched index in string 9474 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 9475 9476 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 9477 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 9478 FOUND_CANDIDATE; 9479 9480 { //======================================================== 9481 // We don't know where these strings are located 9482 // and we can't read beyond them. Load them through stack. 9483 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 9484 9485 movptr(tmp, rsp); // save old SP 9486 9487 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 9488 if (int_cnt2 == 1) { // One char 9489 load_unsigned_short(result, Address(str2, 0)); 9490 movdl(vec, result); // move 32 bits 9491 } else if (int_cnt2 == 2) { // Two chars 9492 movdl(vec, Address(str2, 0)); // move 32 bits 9493 } else if (int_cnt2 == 4) { // Four chars 9494 movq(vec, Address(str2, 0)); // move 64 bits 9495 } else { // cnt2 = { 3, 5, 6, 7 } 9496 // Array header size is 12 bytes in 32-bit VM 9497 // + 6 bytes for 3 chars == 18 bytes, 9498 // enough space to load vec and shift. 9499 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity"); 9500 movdqu(vec, Address(str2, (int_cnt2*2)-16)); 9501 psrldq(vec, 16-(int_cnt2*2)); 9502 } 9503 } else { // not constant substring 9504 cmpl(cnt2, 8); 9505 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 9506 9507 // We can read beyond string if srt+16 does not cross page boundary 9508 // since heaps are aligned and mapped by pages. 9509 assert(os::vm_page_size() < (int)G, "default page should be small"); 9510 movl(result, str2); // We need only low 32 bits 9511 andl(result, (os::vm_page_size()-1)); 9512 cmpl(result, (os::vm_page_size()-16)); 9513 jccb(Assembler::belowEqual, CHECK_STR); 9514 9515 // Move small strings to stack to allow load 16 bytes into vec. 9516 subptr(rsp, 16); 9517 int stk_offset = wordSize-2; 9518 push(cnt2); 9519 9520 bind(COPY_SUBSTR); 9521 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); 9522 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 9523 decrement(cnt2); 9524 jccb(Assembler::notZero, COPY_SUBSTR); 9525 9526 pop(cnt2); 9527 movptr(str2, rsp); // New substring address 9528 } // non constant 9529 9530 bind(CHECK_STR); 9531 cmpl(cnt1, 8); 9532 jccb(Assembler::aboveEqual, BIG_STRINGS); 9533 9534 // Check cross page boundary. 9535 movl(result, str1); // We need only low 32 bits 9536 andl(result, (os::vm_page_size()-1)); 9537 cmpl(result, (os::vm_page_size()-16)); 9538 jccb(Assembler::belowEqual, BIG_STRINGS); 9539 9540 subptr(rsp, 16); 9541 int stk_offset = -2; 9542 if (int_cnt2 < 0) { // not constant 9543 push(cnt2); 9544 stk_offset += wordSize; 9545 } 9546 movl(cnt2, cnt1); 9547 9548 bind(COPY_STR); 9549 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); 9550 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 9551 decrement(cnt2); 9552 jccb(Assembler::notZero, COPY_STR); 9553 9554 if (int_cnt2 < 0) { // not constant 9555 pop(cnt2); 9556 } 9557 movptr(str1, rsp); // New string address 9558 9559 bind(BIG_STRINGS); 9560 // Load substring. 9561 if (int_cnt2 < 0) { // -1 9562 movdqu(vec, Address(str2, 0)); 9563 push(cnt2); // substr count 9564 push(str2); // substr addr 9565 push(str1); // string addr 9566 } else { 9567 // Small (< 8 chars) constant substrings are loaded already. 9568 movl(cnt2, int_cnt2); 9569 } 9570 push(tmp); // original SP 9571 9572 } // Finished loading 9573 9574 //======================================================== 9575 // Start search 9576 // 9577 9578 movptr(result, str1); // string addr 9579 9580 if (int_cnt2 < 0) { // Only for non constant substring 9581 jmpb(SCAN_TO_SUBSTR); 9582 9583 // SP saved at sp+0 9584 // String saved at sp+1*wordSize 9585 // Substr saved at sp+2*wordSize 9586 // Substr count saved at sp+3*wordSize 9587 9588 // Reload substr for rescan, this code 9589 // is executed only for large substrings (> 8 chars) 9590 bind(RELOAD_SUBSTR); 9591 movptr(str2, Address(rsp, 2*wordSize)); 9592 movl(cnt2, Address(rsp, 3*wordSize)); 9593 movdqu(vec, Address(str2, 0)); 9594 // We came here after the beginning of the substring was 9595 // matched but the rest of it was not so we need to search 9596 // again. Start from the next element after the previous match. 9597 subptr(str1, result); // Restore counter 9598 shrl(str1, 1); 9599 addl(cnt1, str1); 9600 decrementl(cnt1); // Shift to next element 9601 cmpl(cnt1, cnt2); 9602 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 9603 9604 addptr(result, 2); 9605 } // non constant 9606 9607 // Scan string for start of substr in 16-byte vectors 9608 bind(SCAN_TO_SUBSTR); 9609 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 9610 pcmpestri(vec, Address(result, 0), 0x0d); 9611 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 9612 subl(cnt1, 8); 9613 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 9614 cmpl(cnt1, cnt2); 9615 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 9616 addptr(result, 16); 9617 9618 bind(ADJUST_STR); 9619 cmpl(cnt1, 8); // Do not read beyond string 9620 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 9621 // Back-up string to avoid reading beyond string. 9622 lea(result, Address(result, cnt1, Address::times_2, -16)); 9623 movl(cnt1, 8); 9624 jmpb(SCAN_TO_SUBSTR); 9625 9626 // Found a potential substr 9627 bind(FOUND_CANDIDATE); 9628 // After pcmpestri tmp(rcx) contains matched element index 9629 9630 // Make sure string is still long enough 9631 subl(cnt1, tmp); 9632 cmpl(cnt1, cnt2); 9633 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 9634 // Left less then substring. 9635 9636 bind(RET_NOT_FOUND); 9637 movl(result, -1); 9638 jmpb(CLEANUP); 9639 9640 bind(FOUND_SUBSTR); 9641 // Compute start addr of substr 9642 lea(result, Address(result, tmp, Address::times_2)); 9643 9644 if (int_cnt2 > 0) { // Constant substring 9645 // Repeat search for small substring (< 8 chars) 9646 // from new point without reloading substring. 9647 // Have to check that we don't read beyond string. 9648 cmpl(tmp, 8-int_cnt2); 9649 jccb(Assembler::greater, ADJUST_STR); 9650 // Fall through if matched whole substring. 9651 } else { // non constant 9652 assert(int_cnt2 == -1, "should be != 0"); 9653 9654 addl(tmp, cnt2); 9655 // Found result if we matched whole substring. 9656 cmpl(tmp, 8); 9657 jccb(Assembler::lessEqual, RET_FOUND); 9658 9659 // Repeat search for small substring (<= 8 chars) 9660 // from new point 'str1' without reloading substring. 9661 cmpl(cnt2, 8); 9662 // Have to check that we don't read beyond string. 9663 jccb(Assembler::lessEqual, ADJUST_STR); 9664 9665 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 9666 // Compare the rest of substring (> 8 chars). 9667 movptr(str1, result); 9668 9669 cmpl(tmp, cnt2); 9670 // First 8 chars are already matched. 9671 jccb(Assembler::equal, CHECK_NEXT); 9672 9673 bind(SCAN_SUBSTR); 9674 pcmpestri(vec, Address(str1, 0), 0x0d); 9675 // Need to reload strings pointers if not matched whole vector 9676 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 9677 9678 bind(CHECK_NEXT); 9679 subl(cnt2, 8); 9680 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 9681 addptr(str1, 16); 9682 addptr(str2, 16); 9683 subl(cnt1, 8); 9684 cmpl(cnt2, 8); // Do not read beyond substring 9685 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 9686 // Back-up strings to avoid reading beyond substring. 9687 lea(str2, Address(str2, cnt2, Address::times_2, -16)); 9688 lea(str1, Address(str1, cnt2, Address::times_2, -16)); 9689 subl(cnt1, cnt2); 9690 movl(cnt2, 8); 9691 addl(cnt1, 8); 9692 bind(CONT_SCAN_SUBSTR); 9693 movdqu(vec, Address(str2, 0)); 9694 jmpb(SCAN_SUBSTR); 9695 9696 bind(RET_FOUND_LONG); 9697 movptr(str1, Address(rsp, wordSize)); 9698 } // non constant 9699 9700 bind(RET_FOUND); 9701 // Compute substr offset 9702 subptr(result, str1); 9703 shrl(result, 1); // index 9704 9705 bind(CLEANUP); 9706 pop(rsp); // restore SP 9707 9708 } // string_indexof 9709 9710 // Compare strings. 9711 void MacroAssembler::string_compare(Register str1, Register str2, 9712 Register cnt1, Register cnt2, Register result, 9713 XMMRegister vec1) { 9714 ShortBranchVerifier sbv(this); 9715 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 9716 9717 // Compute the minimum of the string lengths and the 9718 // difference of the string lengths (stack). 9719 // Do the conditional move stuff 9720 movl(result, cnt1); 9721 subl(cnt1, cnt2); 9722 push(cnt1); 9723 cmov32(Assembler::lessEqual, cnt2, result); 9724 9725 // Is the minimum length zero? 9726 testl(cnt2, cnt2); 9727 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 9728 9729 // Load first characters 9730 load_unsigned_short(result, Address(str1, 0)); 9731 load_unsigned_short(cnt1, Address(str2, 0)); 9732 9733 // Compare first characters 9734 subl(result, cnt1); 9735 jcc(Assembler::notZero, POP_LABEL); 9736 decrementl(cnt2); 9737 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 9738 9739 { 9740 // Check after comparing first character to see if strings are equivalent 9741 Label LSkip2; 9742 // Check if the strings start at same location 9743 cmpptr(str1, str2); 9744 jccb(Assembler::notEqual, LSkip2); 9745 9746 // Check if the length difference is zero (from stack) 9747 cmpl(Address(rsp, 0), 0x0); 9748 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 9749 9750 // Strings might not be equivalent 9751 bind(LSkip2); 9752 } 9753 9754 Address::ScaleFactor scale = Address::times_2; 9755 int stride = 8; 9756 9757 // Advance to next element 9758 addptr(str1, 16/stride); 9759 addptr(str2, 16/stride); 9760 9761 if (UseSSE42Intrinsics) { 9762 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 9763 int pcmpmask = 0x19; 9764 // Setup to compare 16-byte vectors 9765 movl(result, cnt2); 9766 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 9767 jccb(Assembler::zero, COMPARE_TAIL); 9768 9769 lea(str1, Address(str1, result, scale)); 9770 lea(str2, Address(str2, result, scale)); 9771 negptr(result); 9772 9773 // pcmpestri 9774 // inputs: 9775 // vec1- substring 9776 // rax - negative string length (elements count) 9777 // mem - scaned string 9778 // rdx - string length (elements count) 9779 // pcmpmask - cmp mode: 11000 (string compare with negated result) 9780 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 9781 // outputs: 9782 // rcx - first mismatched element index 9783 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 9784 9785 bind(COMPARE_WIDE_VECTORS); 9786 movdqu(vec1, Address(str1, result, scale)); 9787 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 9788 // After pcmpestri cnt1(rcx) contains mismatched element index 9789 9790 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 9791 addptr(result, stride); 9792 subptr(cnt2, stride); 9793 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 9794 9795 // compare wide vectors tail 9796 testl(result, result); 9797 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 9798 9799 movl(cnt2, stride); 9800 movl(result, stride); 9801 negptr(result); 9802 movdqu(vec1, Address(str1, result, scale)); 9803 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 9804 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 9805 9806 // Mismatched characters in the vectors 9807 bind(VECTOR_NOT_EQUAL); 9808 addptr(result, cnt1); 9809 movptr(cnt2, result); 9810 load_unsigned_short(result, Address(str1, cnt2, scale)); 9811 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); 9812 subl(result, cnt1); 9813 jmpb(POP_LABEL); 9814 9815 bind(COMPARE_TAIL); // limit is zero 9816 movl(cnt2, result); 9817 // Fallthru to tail compare 9818 } 9819 9820 // Shift str2 and str1 to the end of the arrays, negate min 9821 lea(str1, Address(str1, cnt2, scale, 0)); 9822 lea(str2, Address(str2, cnt2, scale, 0)); 9823 negptr(cnt2); 9824 9825 // Compare the rest of the elements 9826 bind(WHILE_HEAD_LABEL); 9827 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); 9828 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); 9829 subl(result, cnt1); 9830 jccb(Assembler::notZero, POP_LABEL); 9831 increment(cnt2); 9832 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 9833 9834 // Strings are equal up to min length. Return the length difference. 9835 bind(LENGTH_DIFF_LABEL); 9836 pop(result); 9837 jmpb(DONE_LABEL); 9838 9839 // Discard the stored length difference 9840 bind(POP_LABEL); 9841 pop(cnt1); 9842 9843 // That's it 9844 bind(DONE_LABEL); 9845 } 9846 9847 // Compare char[] arrays aligned to 4 bytes or substrings. 9848 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 9849 Register limit, Register result, Register chr, 9850 XMMRegister vec1, XMMRegister vec2) { 9851 ShortBranchVerifier sbv(this); 9852 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; 9853 9854 int length_offset = arrayOopDesc::length_offset_in_bytes(); 9855 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 9856 9857 // Check the input args 9858 cmpptr(ary1, ary2); 9859 jcc(Assembler::equal, TRUE_LABEL); 9860 9861 if (is_array_equ) { 9862 // Need additional checks for arrays_equals. 9863 testptr(ary1, ary1); 9864 jcc(Assembler::zero, FALSE_LABEL); 9865 testptr(ary2, ary2); 9866 jcc(Assembler::zero, FALSE_LABEL); 9867 9868 // Check the lengths 9869 movl(limit, Address(ary1, length_offset)); 9870 cmpl(limit, Address(ary2, length_offset)); 9871 jcc(Assembler::notEqual, FALSE_LABEL); 9872 } 9873 9874 // count == 0 9875 testl(limit, limit); 9876 jcc(Assembler::zero, TRUE_LABEL); 9877 9878 if (is_array_equ) { 9879 // Load array address 9880 lea(ary1, Address(ary1, base_offset)); 9881 lea(ary2, Address(ary2, base_offset)); 9882 } 9883 9884 shll(limit, 1); // byte count != 0 9885 movl(result, limit); // copy 9886 9887 if (UseSSE42Intrinsics) { 9888 // With SSE4.2, use double quad vector compare 9889 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 9890 9891 // Compare 16-byte vectors 9892 andl(result, 0x0000000e); // tail count (in bytes) 9893 andl(limit, 0xfffffff0); // vector count (in bytes) 9894 jccb(Assembler::zero, COMPARE_TAIL); 9895 9896 lea(ary1, Address(ary1, limit, Address::times_1)); 9897 lea(ary2, Address(ary2, limit, Address::times_1)); 9898 negptr(limit); 9899 9900 bind(COMPARE_WIDE_VECTORS); 9901 movdqu(vec1, Address(ary1, limit, Address::times_1)); 9902 movdqu(vec2, Address(ary2, limit, Address::times_1)); 9903 pxor(vec1, vec2); 9904 9905 ptest(vec1, vec1); 9906 jccb(Assembler::notZero, FALSE_LABEL); 9907 addptr(limit, 16); 9908 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 9909 9910 testl(result, result); 9911 jccb(Assembler::zero, TRUE_LABEL); 9912 9913 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 9914 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 9915 pxor(vec1, vec2); 9916 9917 ptest(vec1, vec1); 9918 jccb(Assembler::notZero, FALSE_LABEL); 9919 jmpb(TRUE_LABEL); 9920 9921 bind(COMPARE_TAIL); // limit is zero 9922 movl(limit, result); 9923 // Fallthru to tail compare 9924 } 9925 9926 // Compare 4-byte vectors 9927 andl(limit, 0xfffffffc); // vector count (in bytes) 9928 jccb(Assembler::zero, COMPARE_CHAR); 9929 9930 lea(ary1, Address(ary1, limit, Address::times_1)); 9931 lea(ary2, Address(ary2, limit, Address::times_1)); 9932 negptr(limit); 9933 9934 bind(COMPARE_VECTORS); 9935 movl(chr, Address(ary1, limit, Address::times_1)); 9936 cmpl(chr, Address(ary2, limit, Address::times_1)); 9937 jccb(Assembler::notEqual, FALSE_LABEL); 9938 addptr(limit, 4); 9939 jcc(Assembler::notZero, COMPARE_VECTORS); 9940 9941 // Compare trailing char (final 2 bytes), if any 9942 bind(COMPARE_CHAR); 9943 testl(result, 0x2); // tail char 9944 jccb(Assembler::zero, TRUE_LABEL); 9945 load_unsigned_short(chr, Address(ary1, 0)); 9946 load_unsigned_short(limit, Address(ary2, 0)); 9947 cmpl(chr, limit); 9948 jccb(Assembler::notEqual, FALSE_LABEL); 9949 9950 bind(TRUE_LABEL); 9951 movl(result, 1); // return true 9952 jmpb(DONE); 9953 9954 bind(FALSE_LABEL); 9955 xorl(result, result); // return false 9956 9957 // That's it 9958 bind(DONE); 9959 } 9960 9961 #ifdef PRODUCT 9962 #define BLOCK_COMMENT(str) /* nothing */ 9963 #else 9964 #define BLOCK_COMMENT(str) block_comment(str) 9965 #endif 9966 9967 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 9968 void MacroAssembler::generate_fill(BasicType t, bool aligned, 9969 Register to, Register value, Register count, 9970 Register rtmp, XMMRegister xtmp) { 9971 ShortBranchVerifier sbv(this); 9972 assert_different_registers(to, value, count, rtmp); 9973 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 9974 Label L_fill_2_bytes, L_fill_4_bytes; 9975 9976 int shift = -1; 9977 switch (t) { 9978 case T_BYTE: 9979 shift = 2; 9980 break; 9981 case T_SHORT: 9982 shift = 1; 9983 break; 9984 case T_INT: 9985 shift = 0; 9986 break; 9987 default: ShouldNotReachHere(); 9988 } 9989 9990 if (t == T_BYTE) { 9991 andl(value, 0xff); 9992 movl(rtmp, value); 9993 shll(rtmp, 8); 9994 orl(value, rtmp); 9995 } 9996 if (t == T_SHORT) { 9997 andl(value, 0xffff); 9998 } 9999 if (t == T_BYTE || t == T_SHORT) { 10000 movl(rtmp, value); 10001 shll(rtmp, 16); 10002 orl(value, rtmp); 10003 } 10004 10005 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 10006 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 10007 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 10008 // align source address at 4 bytes address boundary 10009 if (t == T_BYTE) { 10010 // One byte misalignment happens only for byte arrays 10011 testptr(to, 1); 10012 jccb(Assembler::zero, L_skip_align1); 10013 movb(Address(to, 0), value); 10014 increment(to); 10015 decrement(count); 10016 BIND(L_skip_align1); 10017 } 10018 // Two bytes misalignment happens only for byte and short (char) arrays 10019 testptr(to, 2); 10020 jccb(Assembler::zero, L_skip_align2); 10021 movw(Address(to, 0), value); 10022 addptr(to, 2); 10023 subl(count, 1<<(shift-1)); 10024 BIND(L_skip_align2); 10025 } 10026 if (UseSSE < 2) { 10027 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 10028 // Fill 32-byte chunks 10029 subl(count, 8 << shift); 10030 jcc(Assembler::less, L_check_fill_8_bytes); 10031 align(16); 10032 10033 BIND(L_fill_32_bytes_loop); 10034 10035 for (int i = 0; i < 32; i += 4) { 10036 movl(Address(to, i), value); 10037 } 10038 10039 addptr(to, 32); 10040 subl(count, 8 << shift); 10041 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 10042 BIND(L_check_fill_8_bytes); 10043 addl(count, 8 << shift); 10044 jccb(Assembler::zero, L_exit); 10045 jmpb(L_fill_8_bytes); 10046 10047 // 10048 // length is too short, just fill qwords 10049 // 10050 BIND(L_fill_8_bytes_loop); 10051 movl(Address(to, 0), value); 10052 movl(Address(to, 4), value); 10053 addptr(to, 8); 10054 BIND(L_fill_8_bytes); 10055 subl(count, 1 << (shift + 1)); 10056 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 10057 // fall through to fill 4 bytes 10058 } else { 10059 Label L_fill_32_bytes; 10060 if (!UseUnalignedLoadStores) { 10061 // align to 8 bytes, we know we are 4 byte aligned to start 10062 testptr(to, 4); 10063 jccb(Assembler::zero, L_fill_32_bytes); 10064 movl(Address(to, 0), value); 10065 addptr(to, 4); 10066 subl(count, 1<<shift); 10067 } 10068 BIND(L_fill_32_bytes); 10069 { 10070 assert( UseSSE >= 2, "supported cpu only" ); 10071 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 10072 // Fill 32-byte chunks 10073 movdl(xtmp, value); 10074 pshufd(xtmp, xtmp, 0); 10075 10076 subl(count, 8 << shift); 10077 jcc(Assembler::less, L_check_fill_8_bytes); 10078 align(16); 10079 10080 BIND(L_fill_32_bytes_loop); 10081 10082 if (UseUnalignedLoadStores) { 10083 movdqu(Address(to, 0), xtmp); 10084 movdqu(Address(to, 16), xtmp); 10085 } else { 10086 movq(Address(to, 0), xtmp); 10087 movq(Address(to, 8), xtmp); 10088 movq(Address(to, 16), xtmp); 10089 movq(Address(to, 24), xtmp); 10090 } 10091 10092 addptr(to, 32); 10093 subl(count, 8 << shift); 10094 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 10095 BIND(L_check_fill_8_bytes); 10096 addl(count, 8 << shift); 10097 jccb(Assembler::zero, L_exit); 10098 jmpb(L_fill_8_bytes); 10099 10100 // 10101 // length is too short, just fill qwords 10102 // 10103 BIND(L_fill_8_bytes_loop); 10104 movq(Address(to, 0), xtmp); 10105 addptr(to, 8); 10106 BIND(L_fill_8_bytes); 10107 subl(count, 1 << (shift + 1)); 10108 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 10109 } 10110 } 10111 // fill trailing 4 bytes 10112 BIND(L_fill_4_bytes); 10113 testl(count, 1<<shift); 10114 jccb(Assembler::zero, L_fill_2_bytes); 10115 movl(Address(to, 0), value); 10116 if (t == T_BYTE || t == T_SHORT) { 10117 addptr(to, 4); 10118 BIND(L_fill_2_bytes); 10119 // fill trailing 2 bytes 10120 testl(count, 1<<(shift-1)); 10121 jccb(Assembler::zero, L_fill_byte); 10122 movw(Address(to, 0), value); 10123 if (t == T_BYTE) { 10124 addptr(to, 2); 10125 BIND(L_fill_byte); 10126 // fill trailing byte 10127 testl(count, 1); 10128 jccb(Assembler::zero, L_exit); 10129 movb(Address(to, 0), value); 10130 } else { 10131 BIND(L_fill_byte); 10132 } 10133 } else { 10134 BIND(L_fill_2_bytes); 10135 } 10136 BIND(L_exit); 10137 } 10138 #undef BIND 10139 #undef BLOCK_COMMENT 10140 10141 10142 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 10143 switch (cond) { 10144 // Note some conditions are synonyms for others 10145 case Assembler::zero: return Assembler::notZero; 10146 case Assembler::notZero: return Assembler::zero; 10147 case Assembler::less: return Assembler::greaterEqual; 10148 case Assembler::lessEqual: return Assembler::greater; 10149 case Assembler::greater: return Assembler::lessEqual; 10150 case Assembler::greaterEqual: return Assembler::less; 10151 case Assembler::below: return Assembler::aboveEqual; 10152 case Assembler::belowEqual: return Assembler::above; 10153 case Assembler::above: return Assembler::belowEqual; 10154 case Assembler::aboveEqual: return Assembler::below; 10155 case Assembler::overflow: return Assembler::noOverflow; 10156 case Assembler::noOverflow: return Assembler::overflow; 10157 case Assembler::negative: return Assembler::positive; 10158 case Assembler::positive: return Assembler::negative; 10159 case Assembler::parity: return Assembler::noParity; 10160 case Assembler::noParity: return Assembler::parity; 10161 } 10162 ShouldNotReachHere(); return Assembler::overflow; 10163 } 10164 10165 SkipIfEqual::SkipIfEqual( 10166 MacroAssembler* masm, const bool* flag_addr, bool value) { 10167 _masm = masm; 10168 _masm->cmp8(ExternalAddress((address)flag_addr), value); 10169 _masm->jcc(Assembler::equal, _label); 10170 } 10171 10172 SkipIfEqual::~SkipIfEqual() { 10173 _masm->bind(_label); 10174 }