1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 class BiasedLockingCounters;
29
30 // Contains all the definitions needed for x86 assembly code generation.
31
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
51
52
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
56
57 #ifdef _WIN64
58
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
63
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
68
69 #else
70
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
77
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
86
87 #endif // _WIN64
88
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
104
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
117
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
126
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
129
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
132
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
139
140 #endif // _LP64
141
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
144
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
150
151 class ArrayAddress;
152
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
178
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
185
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
191
192 public:
193
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
202
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
205
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
212
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
221
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
231
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
238 Address a = (*this);
239 a._disp += disp.constant_or_zero() * scale_size(scale);
240 if (disp.is_register()) {
241 assert(!a.index()->is_valid(), "competing indexes");
242 a._index = disp.as_register();
243 a._scale = scale;
244 }
245 return a;
246 }
247 bool is_same_address(Address a) const {
248 // disregard _rspec
249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
250 }
251
252 // The following two overloads are used in connection with the
253 // ByteSize type (see sizes.hpp). They simplify the use of
254 // ByteSize'd arguments in assembly code. Note that their equivalent
255 // for the optimized build are the member functions with int disp
256 // argument since ByteSize is mapped to an int type in that case.
257 //
258 // Note: DO NOT introduce similar overloaded functions for WordSize
259 // arguments as in the optimized mode, both ByteSize and WordSize
260 // are mapped to the same type and thus the compiler cannot make a
261 // distinction anymore (=> compiler errors).
262
263 #ifdef ASSERT
264 Address(Register base, ByteSize disp)
265 : _base(base),
266 _index(noreg),
267 _scale(no_scale),
268 _disp(in_bytes(disp)) {
269 }
270
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
272 : _base(base),
273 _index(index),
274 _scale(scale),
275 _disp(in_bytes(disp)) {
276 assert(!index->is_valid() == (scale == Address::no_scale),
277 "inconsistent address");
278 }
279
280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
281 : _base (base),
282 _index(index.register_or_noreg()),
283 _scale(scale),
284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
285 if (!index.is_register()) scale = Address::no_scale;
286 assert(!_index->is_valid() == (scale == Address::no_scale),
287 "inconsistent address");
288 }
289
290 #endif // ASSERT
291
292 // accessors
293 bool uses(Register reg) const { return _base == reg || _index == reg; }
294 Register base() const { return _base; }
295 Register index() const { return _index; }
296 ScaleFactor scale() const { return _scale; }
297 int disp() const { return _disp; }
298
299 // Convert the raw encoding form into the form expected by the constructor for
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert
301 // that to noreg for the Address constructor.
302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
303
304 static Address make_array(ArrayAddress);
305
306 private:
307 bool base_needs_rex() const {
308 return _base != noreg && _base->encoding() >= 8;
309 }
310
311 bool index_needs_rex() const {
312 return _index != noreg &&_index->encoding() >= 8;
313 }
314
315 relocInfo::relocType reloc() const { return _rspec.type(); }
316
317 friend class Assembler;
318 friend class MacroAssembler;
319 friend class LIR_Assembler; // base/index/scale/disp
320 };
321
322 //
323 // AddressLiteral has been split out from Address because operands of this type
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
325 // the few instructions that need to deal with address literals are unique and the
326 // MacroAssembler does not have to implement every instruction in the Assembler
327 // in order to search for address literals that may need special handling depending
328 // on the instruction and the platform. As small step on the way to merging i486/amd64
329 // directories.
330 //
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
332 friend class ArrayAddress;
333 RelocationHolder _rspec;
334 // Typically we use AddressLiterals we want to use their rval
335 // However in some situations we want the lval (effect address) of the item.
336 // We provide a special factory for making those lvals.
337 bool _is_lval;
338
339 // If the target is far we'll need to load the ea of this to
340 // a register to reach it. Otherwise if near we can do rip
341 // relative addressing.
342
343 address _target;
344
345 protected:
346 // creation
347 AddressLiteral()
348 : _is_lval(false),
349 _target(NULL)
350 {}
351
352 public:
353
354
355 AddressLiteral(address target, relocInfo::relocType rtype);
356
357 AddressLiteral(address target, RelocationHolder const& rspec)
358 : _rspec(rspec),
359 _is_lval(false),
360 _target(target)
361 {}
362
363 AddressLiteral addr() {
364 AddressLiteral ret = *this;
365 ret._is_lval = true;
366 return ret;
367 }
368
369
370 private:
371
372 address target() { return _target; }
373 bool is_lval() { return _is_lval; }
374
375 relocInfo::relocType reloc() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
377
378 friend class Assembler;
379 friend class MacroAssembler;
380 friend class Address;
381 friend class LIR_Assembler;
382 };
383
384 // Convience classes
385 class RuntimeAddress: public AddressLiteral {
386
387 public:
388
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
390
391 };
392
393 class OopAddress: public AddressLiteral {
394
395 public:
396
397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
398
399 };
400
401 class ExternalAddress: public AddressLiteral {
402 private:
403 static relocInfo::relocType reloc_for_target(address target) {
404 // Sometimes ExternalAddress is used for values which aren't
405 // exactly addresses, like the card table base.
406 // external_word_type can't be used for values in the first page
407 // so just skip the reloc in that case.
408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
409 }
410
411 public:
412
413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
414
415 };
416
417 class InternalAddress: public AddressLiteral {
418
419 public:
420
421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
422
423 };
424
425 // x86 can do array addressing as a single operation since disp can be an absolute
426 // address amd64 can't. We create a class that expresses the concept but does extra
427 // magic on amd64 to get the final result
428
429 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
430 private:
431
432 AddressLiteral _base;
433 Address _index;
434
435 public:
436
437 ArrayAddress() {};
438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
439 AddressLiteral base() { return _base; }
440 Address index() { return _index; }
441
442 };
443
444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
445
446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
448 // is what you get. The Assembler is generating code into a CodeBuffer.
449
450 class Assembler : public AbstractAssembler {
451 friend class AbstractAssembler; // for the non-virtual hack
452 friend class LIR_Assembler; // as_Address()
453 friend class StubGenerator;
454
455 public:
456 enum Condition { // The x86 condition codes used for conditional jumps/moves.
457 zero = 0x4,
458 notZero = 0x5,
459 equal = 0x4,
460 notEqual = 0x5,
461 less = 0xc,
462 lessEqual = 0xe,
463 greater = 0xf,
464 greaterEqual = 0xd,
465 below = 0x2,
466 belowEqual = 0x6,
467 above = 0x7,
468 aboveEqual = 0x3,
469 overflow = 0x0,
470 noOverflow = 0x1,
471 carrySet = 0x2,
472 carryClear = 0x3,
473 negative = 0x8,
474 positive = 0x9,
475 parity = 0xa,
476 noParity = 0xb
477 };
478
479 enum Prefix {
480 // segment overrides
481 CS_segment = 0x2e,
482 SS_segment = 0x36,
483 DS_segment = 0x3e,
484 ES_segment = 0x26,
485 FS_segment = 0x64,
486 GS_segment = 0x65,
487
488 REX = 0x40,
489
490 REX_B = 0x41,
491 REX_X = 0x42,
492 REX_XB = 0x43,
493 REX_R = 0x44,
494 REX_RB = 0x45,
495 REX_RX = 0x46,
496 REX_RXB = 0x47,
497
498 REX_W = 0x48,
499
500 REX_WB = 0x49,
501 REX_WX = 0x4A,
502 REX_WXB = 0x4B,
503 REX_WR = 0x4C,
504 REX_WRB = 0x4D,
505 REX_WRX = 0x4E,
506 REX_WRXB = 0x4F,
507
508 VEX_3bytes = 0xC4,
509 VEX_2bytes = 0xC5
510 };
511
512 enum VexPrefix {
513 VEX_B = 0x20,
514 VEX_X = 0x40,
515 VEX_R = 0x80,
516 VEX_W = 0x80
517 };
518
519 enum VexSimdPrefix {
520 VEX_SIMD_NONE = 0x0,
521 VEX_SIMD_66 = 0x1,
522 VEX_SIMD_F3 = 0x2,
523 VEX_SIMD_F2 = 0x3
524 };
525
526 enum VexOpcode {
527 VEX_OPCODE_NONE = 0x0,
528 VEX_OPCODE_0F = 0x1,
529 VEX_OPCODE_0F_38 = 0x2,
530 VEX_OPCODE_0F_3A = 0x3
531 };
532
533 enum WhichOperand {
534 // input to locate_operand, and format code for relocations
535 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
536 disp32_operand = 1, // embedded 32-bit displacement or address
537 call32_operand = 2, // embedded 32-bit self-relative displacement
538 #ifndef _LP64
539 _WhichOperand_limit = 3
540 #else
541 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
542 _WhichOperand_limit = 4
543 #endif
544 };
545
546
547
548 // NOTE: The general philopsophy of the declarations here is that 64bit versions
549 // of instructions are freely declared without the need for wrapping them an ifdef.
550 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
551 // In the .cpp file the implementations are wrapped so that they are dropped out
552 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
553 // to the size it was prior to merging up the 32bit and 64bit assemblers.
554 //
555 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
556 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
557
558 private:
559
560
561 // 64bit prefixes
562 int prefix_and_encode(int reg_enc, bool byteinst = false);
563 int prefixq_and_encode(int reg_enc);
564
565 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
566 int prefixq_and_encode(int dst_enc, int src_enc);
567
568 void prefix(Register reg);
569 void prefix(Address adr);
570 void prefixq(Address adr);
571
572 void prefix(Address adr, Register reg, bool byteinst = false);
573 void prefix(Address adr, XMMRegister reg);
574 void prefixq(Address adr, Register reg);
575 void prefixq(Address adr, XMMRegister reg);
576
577 void prefetch_prefix(Address src);
578
579 void rex_prefix(Address adr, XMMRegister xreg,
580 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
581 int rex_prefix_and_encode(int dst_enc, int src_enc,
582 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
583
584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
585 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
586 bool vector256);
587
588 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
589 VexSimdPrefix pre, VexOpcode opc,
590 bool vex_w, bool vector256);
591
592 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
593 VexSimdPrefix pre, bool vector256 = false) {
594 vex_prefix(src, nds->encoding(), dst->encoding(),
595 pre, VEX_OPCODE_0F, false, vector256);
596 }
597
598 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
599 VexSimdPrefix pre, VexOpcode opc,
600 bool vex_w, bool vector256);
601
602 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
603 VexSimdPrefix pre, bool vector256 = false) {
604 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
605 pre, VEX_OPCODE_0F, false, vector256);
606 }
607
608 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
609 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
610 bool rex_w = false, bool vector256 = false);
611
612 void simd_prefix(XMMRegister dst, Address src,
613 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
614 simd_prefix(dst, xnoreg, src, pre, opc);
615 }
616 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
617 simd_prefix(src, dst, pre);
618 }
619 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
620 VexSimdPrefix pre) {
621 bool rex_w = true;
622 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
623 }
624
625
626 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
627 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
628 bool rex_w = false, bool vector256 = false);
629
630 int simd_prefix_and_encode(XMMRegister dst, XMMRegister src,
631 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
632 return simd_prefix_and_encode(dst, xnoreg, src, pre, opc);
633 }
634
635 // Move/convert 32-bit integer value.
636 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
637 VexSimdPrefix pre) {
638 // It is OK to cast from Register to XMMRegister to pass argument here
639 // since only encoding is used in simd_prefix_and_encode() and number of
640 // Gen and Xmm registers are the same.
641 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
642 }
643 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
644 return simd_prefix_and_encode(dst, xnoreg, src, pre);
645 }
646 int simd_prefix_and_encode(Register dst, XMMRegister src,
647 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
648 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
649 }
650
651 // Move/convert 64-bit integer value.
652 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
653 VexSimdPrefix pre) {
654 bool rex_w = true;
655 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
656 }
657 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
658 return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
659 }
660 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
661 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
662 bool rex_w = true;
663 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
664 }
665
666 // Helper functions for groups of instructions
667 void emit_arith_b(int op1, int op2, Register dst, int imm8);
668
669 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
670 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
671 // only 32bit??
672 void emit_arith(int op1, int op2, Register dst, jobject obj);
673 void emit_arith(int op1, int op2, Register dst, Register src);
674
675 void emit_operand(Register reg,
676 Register base, Register index, Address::ScaleFactor scale,
677 int disp,
678 RelocationHolder const& rspec,
679 int rip_relative_correction = 0);
680
681 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
682
683 // operands that only take the original 32bit registers
684 void emit_operand32(Register reg, Address adr);
685
686 void emit_operand(XMMRegister reg,
687 Register base, Register index, Address::ScaleFactor scale,
688 int disp,
689 RelocationHolder const& rspec);
690
691 void emit_operand(XMMRegister reg, Address adr);
692
693 void emit_operand(MMXRegister reg, Address adr);
694
695 // workaround gcc (3.2.1-7) bug
696 void emit_operand(Address adr, MMXRegister reg);
697
698
699 // Immediate-to-memory forms
700 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
701
702 void emit_farith(int b1, int b2, int i);
703
704
705 protected:
706 #ifdef ASSERT
707 void check_relocation(RelocationHolder const& rspec, int format);
708 #endif
709
710 inline void emit_long64(jlong x);
711
712 void emit_data(jint data, relocInfo::relocType rtype, int format);
713 void emit_data(jint data, RelocationHolder const& rspec, int format);
714 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
715 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
716
717 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
718
719 // These are all easily abused and hence protected
720
721 // 32BIT ONLY SECTION
722 #ifndef _LP64
723 // Make these disappear in 64bit mode since they would never be correct
724 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
725 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
726
727 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
728 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
729
730 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
731 #else
732 // 64BIT ONLY SECTION
733 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
734
735 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
736 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
737
738 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
739 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
740 #endif // _LP64
741
742 // These are unique in that we are ensured by the caller that the 32bit
743 // relative in these instructions will always be able to reach the potentially
744 // 64bit address described by entry. Since they can take a 64bit address they
745 // don't have the 32 suffix like the other instructions in this class.
746
747 void call_literal(address entry, RelocationHolder const& rspec);
748 void jmp_literal(address entry, RelocationHolder const& rspec);
749
750 // Avoid using directly section
751 // Instructions in this section are actually usable by anyone without danger
752 // of failure but have performance issues that are addressed my enhanced
753 // instructions which will do the proper thing base on the particular cpu.
754 // We protect them because we don't trust you...
755
756 // Don't use next inc() and dec() methods directly. INC & DEC instructions
757 // could cause a partial flag stall since they don't set CF flag.
758 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
759 // which call inc() & dec() or add() & sub() in accordance with
760 // the product flag UseIncDec value.
761
762 void decl(Register dst);
763 void decl(Address dst);
764 void decq(Register dst);
765 void decq(Address dst);
766
767 void incl(Register dst);
768 void incl(Address dst);
769 void incq(Register dst);
770 void incq(Address dst);
771
772 // New cpus require use of movsd and movss to avoid partial register stall
773 // when loading from memory. But for old Opteron use movlpd instead of movsd.
774 // The selection is done in MacroAssembler::movdbl() and movflt().
775
776 // Move Scalar Single-Precision Floating-Point Values
777 void movss(XMMRegister dst, Address src);
778 void movss(XMMRegister dst, XMMRegister src);
779 void movss(Address dst, XMMRegister src);
780
781 // Move Scalar Double-Precision Floating-Point Values
782 void movsd(XMMRegister dst, Address src);
783 void movsd(XMMRegister dst, XMMRegister src);
784 void movsd(Address dst, XMMRegister src);
785 void movlpd(XMMRegister dst, Address src);
786
787 // New cpus require use of movaps and movapd to avoid partial register stall
788 // when moving between registers.
789 void movaps(XMMRegister dst, XMMRegister src);
790 void movapd(XMMRegister dst, XMMRegister src);
791
792 // End avoid using directly
793
794
795 // Instruction prefixes
796 void prefix(Prefix p);
797
798 public:
799
800 // Creation
801 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
802
803 // Decoding
804 static address locate_operand(address inst, WhichOperand which);
805 static address locate_next_instruction(address inst);
806
807 // Utilities
808 static bool is_polling_page_far() NOT_LP64({ return false;});
809
810 // Generic instructions
811 // Does 32bit or 64bit as needed for the platform. In some sense these
812 // belong in macro assembler but there is no need for both varieties to exist
813
814 void lea(Register dst, Address src);
815
816 void mov(Register dst, Register src);
817
818 void pusha();
819 void popa();
820
821 void pushf();
822 void popf();
823
824 void push(int32_t imm32);
825
826 void push(Register src);
827
828 void pop(Register dst);
829
830 // These are dummies to prevent surprise implicit conversions to Register
831 void push(void* v);
832 void pop(void* v);
833
834 // These do register sized moves/scans
835 void rep_mov();
836 void rep_set();
837 void repne_scan();
838 #ifdef _LP64
839 void repne_scanl();
840 #endif
841
842 // Vanilla instructions in lexical order
843
844 void adcl(Address dst, int32_t imm32);
845 void adcl(Address dst, Register src);
846 void adcl(Register dst, int32_t imm32);
847 void adcl(Register dst, Address src);
848 void adcl(Register dst, Register src);
849
850 void adcq(Register dst, int32_t imm32);
851 void adcq(Register dst, Address src);
852 void adcq(Register dst, Register src);
853
854 void addl(Address dst, int32_t imm32);
855 void addl(Address dst, Register src);
856 void addl(Register dst, int32_t imm32);
857 void addl(Register dst, Address src);
858 void addl(Register dst, Register src);
859
860 void addq(Address dst, int32_t imm32);
861 void addq(Address dst, Register src);
862 void addq(Register dst, int32_t imm32);
863 void addq(Register dst, Address src);
864 void addq(Register dst, Register src);
865
866 void addr_nop_4();
867 void addr_nop_5();
868 void addr_nop_7();
869 void addr_nop_8();
870
871 // Add Scalar Double-Precision Floating-Point Values
872 void addsd(XMMRegister dst, Address src);
873 void addsd(XMMRegister dst, XMMRegister src);
874
875 // Add Scalar Single-Precision Floating-Point Values
876 void addss(XMMRegister dst, Address src);
877 void addss(XMMRegister dst, XMMRegister src);
878
879 void andl(Address dst, int32_t imm32);
880 void andl(Register dst, int32_t imm32);
881 void andl(Register dst, Address src);
882 void andl(Register dst, Register src);
883
884 void andq(Address dst, int32_t imm32);
885 void andq(Register dst, int32_t imm32);
886 void andq(Register dst, Address src);
887 void andq(Register dst, Register src);
888
889 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
890 void andpd(XMMRegister dst, XMMRegister src);
891
892 // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
893 void andps(XMMRegister dst, XMMRegister src);
894
895 void bsfl(Register dst, Register src);
896 void bsrl(Register dst, Register src);
897
898 #ifdef _LP64
899 void bsfq(Register dst, Register src);
900 void bsrq(Register dst, Register src);
901 #endif
902
903 void bswapl(Register reg);
904
905 void bswapq(Register reg);
906
907 void call(Label& L, relocInfo::relocType rtype);
908 void call(Register reg); // push pc; pc <- reg
909 void call(Address adr); // push pc; pc <- adr
910
911 void cdql();
912
913 void cdqq();
914
915 void cld() { emit_byte(0xfc); }
916
917 void clflush(Address adr);
918
919 void cmovl(Condition cc, Register dst, Register src);
920 void cmovl(Condition cc, Register dst, Address src);
921
922 void cmovq(Condition cc, Register dst, Register src);
923 void cmovq(Condition cc, Register dst, Address src);
924
925
926 void cmpb(Address dst, int imm8);
927
928 void cmpl(Address dst, int32_t imm32);
929
930 void cmpl(Register dst, int32_t imm32);
931 void cmpl(Register dst, Register src);
932 void cmpl(Register dst, Address src);
933
934 void cmpq(Address dst, int32_t imm32);
935 void cmpq(Address dst, Register src);
936
937 void cmpq(Register dst, int32_t imm32);
938 void cmpq(Register dst, Register src);
939 void cmpq(Register dst, Address src);
940
941 // these are dummies used to catch attempting to convert NULL to Register
942 void cmpl(Register dst, void* junk); // dummy
943 void cmpq(Register dst, void* junk); // dummy
944
945 void cmpw(Address dst, int imm16);
946
947 void cmpxchg8 (Address adr);
948
949 void cmpxchgl(Register reg, Address adr);
950
951 void cmpxchgq(Register reg, Address adr);
952
953 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
954 void comisd(XMMRegister dst, Address src);
955 void comisd(XMMRegister dst, XMMRegister src);
956
957 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
958 void comiss(XMMRegister dst, Address src);
959 void comiss(XMMRegister dst, XMMRegister src);
960
961 // Identify processor type and features
962 void cpuid() {
963 emit_byte(0x0F);
964 emit_byte(0xA2);
965 }
966
967 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
968 void cvtsd2ss(XMMRegister dst, XMMRegister src);
969 void cvtsd2ss(XMMRegister dst, Address src);
970
971 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
972 void cvtsi2sdl(XMMRegister dst, Register src);
973 void cvtsi2sdl(XMMRegister dst, Address src);
974 void cvtsi2sdq(XMMRegister dst, Register src);
975 void cvtsi2sdq(XMMRegister dst, Address src);
976
977 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
978 void cvtsi2ssl(XMMRegister dst, Register src);
979 void cvtsi2ssl(XMMRegister dst, Address src);
980 void cvtsi2ssq(XMMRegister dst, Register src);
981 void cvtsi2ssq(XMMRegister dst, Address src);
982
983 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
984 void cvtdq2pd(XMMRegister dst, XMMRegister src);
985
986 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
987 void cvtdq2ps(XMMRegister dst, XMMRegister src);
988
989 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
990 void cvtss2sd(XMMRegister dst, XMMRegister src);
991 void cvtss2sd(XMMRegister dst, Address src);
992
993 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
994 void cvttsd2sil(Register dst, Address src);
995 void cvttsd2sil(Register dst, XMMRegister src);
996 void cvttsd2siq(Register dst, XMMRegister src);
997
998 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
999 void cvttss2sil(Register dst, XMMRegister src);
1000 void cvttss2siq(Register dst, XMMRegister src);
1001
1002 // Divide Scalar Double-Precision Floating-Point Values
1003 void divsd(XMMRegister dst, Address src);
1004 void divsd(XMMRegister dst, XMMRegister src);
1005
1006 // Divide Scalar Single-Precision Floating-Point Values
1007 void divss(XMMRegister dst, Address src);
1008 void divss(XMMRegister dst, XMMRegister src);
1009
1010 void emms();
1011
1012 void fabs();
1013
1014 void fadd(int i);
1015
1016 void fadd_d(Address src);
1017 void fadd_s(Address src);
1018
1019 // "Alternate" versions of x87 instructions place result down in FPU
1020 // stack instead of on TOS
1021
1022 void fadda(int i); // "alternate" fadd
1023 void faddp(int i = 1);
1024
1025 void fchs();
1026
1027 void fcom(int i);
1028
1029 void fcomp(int i = 1);
1030 void fcomp_d(Address src);
1031 void fcomp_s(Address src);
1032
1033 void fcompp();
1034
1035 void fcos();
1036
1037 void fdecstp();
1038
1039 void fdiv(int i);
1040 void fdiv_d(Address src);
1041 void fdivr_s(Address src);
1042 void fdiva(int i); // "alternate" fdiv
1043 void fdivp(int i = 1);
1044
1045 void fdivr(int i);
1046 void fdivr_d(Address src);
1047 void fdiv_s(Address src);
1048
1049 void fdivra(int i); // "alternate" reversed fdiv
1050
1051 void fdivrp(int i = 1);
1052
1053 void ffree(int i = 0);
1054
1055 void fild_d(Address adr);
1056 void fild_s(Address adr);
1057
1058 void fincstp();
1059
1060 void finit();
1061
1062 void fist_s (Address adr);
1063 void fistp_d(Address adr);
1064 void fistp_s(Address adr);
1065
1066 void fld1();
1067
1068 void fld_d(Address adr);
1069 void fld_s(Address adr);
1070 void fld_s(int index);
1071 void fld_x(Address adr); // extended-precision (80-bit) format
1072
1073 void fldcw(Address src);
1074
1075 void fldenv(Address src);
1076
1077 void fldlg2();
1078
1079 void fldln2();
1080
1081 void fldz();
1082
1083 void flog();
1084 void flog10();
1085
1086 void fmul(int i);
1087
1088 void fmul_d(Address src);
1089 void fmul_s(Address src);
1090
1091 void fmula(int i); // "alternate" fmul
1092
1093 void fmulp(int i = 1);
1094
1095 void fnsave(Address dst);
1096
1097 void fnstcw(Address src);
1098
1099 void fnstsw_ax();
1100
1101 void fprem();
1102 void fprem1();
1103
1104 void frstor(Address src);
1105
1106 void fsin();
1107
1108 void fsqrt();
1109
1110 void fst_d(Address adr);
1111 void fst_s(Address adr);
1112
1113 void fstp_d(Address adr);
1114 void fstp_d(int index);
1115 void fstp_s(Address adr);
1116 void fstp_x(Address adr); // extended-precision (80-bit) format
1117
1118 void fsub(int i);
1119 void fsub_d(Address src);
1120 void fsub_s(Address src);
1121
1122 void fsuba(int i); // "alternate" fsub
1123
1124 void fsubp(int i = 1);
1125
1126 void fsubr(int i);
1127 void fsubr_d(Address src);
1128 void fsubr_s(Address src);
1129
1130 void fsubra(int i); // "alternate" reversed fsub
1131
1132 void fsubrp(int i = 1);
1133
1134 void ftan();
1135
1136 void ftst();
1137
1138 void fucomi(int i = 1);
1139 void fucomip(int i = 1);
1140
1141 void fwait();
1142
1143 void fxch(int i = 1);
1144
1145 void fxrstor(Address src);
1146
1147 void fxsave(Address dst);
1148
1149 void fyl2x();
1150
1151 void hlt();
1152
1153 void idivl(Register src);
1154 void divl(Register src); // Unsigned division
1155
1156 void idivq(Register src);
1157
1158 void imull(Register dst, Register src);
1159 void imull(Register dst, Register src, int value);
1160
1161 void imulq(Register dst, Register src);
1162 void imulq(Register dst, Register src, int value);
1163
1164
1165 // jcc is the generic conditional branch generator to run-
1166 // time routines, jcc is used for branches to labels. jcc
1167 // takes a branch opcode (cc) and a label (L) and generates
1168 // either a backward branch or a forward branch and links it
1169 // to the label fixup chain. Usage:
1170 //
1171 // Label L; // unbound label
1172 // jcc(cc, L); // forward branch to unbound label
1173 // bind(L); // bind label to the current pc
1174 // jcc(cc, L); // backward branch to bound label
1175 // bind(L); // illegal: a label may be bound only once
1176 //
1177 // Note: The same Label can be used for forward and backward branches
1178 // but it may be bound only once.
1179
1180 void jcc(Condition cc, Label& L, bool maybe_short = true);
1181
1182 // Conditional jump to a 8-bit offset to L.
1183 // WARNING: be very careful using this for forward jumps. If the label is
1184 // not bound within an 8-bit offset of this instruction, a run-time error
1185 // will occur.
1186 void jccb(Condition cc, Label& L);
1187
1188 void jmp(Address entry); // pc <- entry
1189
1190 // Label operations & relative jumps (PPUM Appendix D)
1191 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1192
1193 void jmp(Register entry); // pc <- entry
1194
1195 // Unconditional 8-bit offset jump to L.
1196 // WARNING: be very careful using this for forward jumps. If the label is
1197 // not bound within an 8-bit offset of this instruction, a run-time error
1198 // will occur.
1199 void jmpb(Label& L);
1200
1201 void ldmxcsr( Address src );
1202
1203 void leal(Register dst, Address src);
1204
1205 void leaq(Register dst, Address src);
1206
1207 void lfence() {
1208 emit_byte(0x0F);
1209 emit_byte(0xAE);
1210 emit_byte(0xE8);
1211 }
1212
1213 void lock();
1214
1215 void lzcntl(Register dst, Register src);
1216
1217 #ifdef _LP64
1218 void lzcntq(Register dst, Register src);
1219 #endif
1220
1221 enum Membar_mask_bits {
1222 StoreStore = 1 << 3,
1223 LoadStore = 1 << 2,
1224 StoreLoad = 1 << 1,
1225 LoadLoad = 1 << 0
1226 };
1227
1228 // Serializes memory and blows flags
1229 void membar(Membar_mask_bits order_constraint) {
1230 if (os::is_MP()) {
1231 // We only have to handle StoreLoad
1232 if (order_constraint & StoreLoad) {
1233 // All usable chips support "locked" instructions which suffice
1234 // as barriers, and are much faster than the alternative of
1235 // using cpuid instruction. We use here a locked add [esp],0.
1236 // This is conveniently otherwise a no-op except for blowing
1237 // flags.
1238 // Any change to this code may need to revisit other places in
1239 // the code where this idiom is used, in particular the
1240 // orderAccess code.
1241 lock();
1242 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1243 }
1244 }
1245 }
1246
1247 void mfence();
1248
1249 // Moves
1250
1251 void mov64(Register dst, int64_t imm64);
1252
1253 void movb(Address dst, Register src);
1254 void movb(Address dst, int imm8);
1255 void movb(Register dst, Address src);
1256
1257 void movdl(XMMRegister dst, Register src);
1258 void movdl(Register dst, XMMRegister src);
1259 void movdl(XMMRegister dst, Address src);
1260
1261 // Move Double Quadword
1262 void movdq(XMMRegister dst, Register src);
1263 void movdq(Register dst, XMMRegister src);
1264
1265 // Move Aligned Double Quadword
1266 void movdqa(XMMRegister dst, XMMRegister src);
1267
1268 // Move Unaligned Double Quadword
1269 void movdqu(Address dst, XMMRegister src);
1270 void movdqu(XMMRegister dst, Address src);
1271 void movdqu(XMMRegister dst, XMMRegister src);
1272
1273 void movl(Register dst, int32_t imm32);
1274 void movl(Address dst, int32_t imm32);
1275 void movl(Register dst, Register src);
1276 void movl(Register dst, Address src);
1277 void movl(Address dst, Register src);
1278
1279 // These dummies prevent using movl from converting a zero (like NULL) into Register
1280 // by giving the compiler two choices it can't resolve
1281
1282 void movl(Address dst, void* junk);
1283 void movl(Register dst, void* junk);
1284
1285 #ifdef _LP64
1286 void movq(Register dst, Register src);
1287 void movq(Register dst, Address src);
1288 void movq(Address dst, Register src);
1289 #endif
1290
1291 void movq(Address dst, MMXRegister src );
1292 void movq(MMXRegister dst, Address src );
1293
1294 #ifdef _LP64
1295 // These dummies prevent using movq from converting a zero (like NULL) into Register
1296 // by giving the compiler two choices it can't resolve
1297
1298 void movq(Address dst, void* dummy);
1299 void movq(Register dst, void* dummy);
1300 #endif
1301
1302 // Move Quadword
1303 void movq(Address dst, XMMRegister src);
1304 void movq(XMMRegister dst, Address src);
1305
1306 void movsbl(Register dst, Address src);
1307 void movsbl(Register dst, Register src);
1308
1309 #ifdef _LP64
1310 void movsbq(Register dst, Address src);
1311 void movsbq(Register dst, Register src);
1312
1313 // Move signed 32bit immediate to 64bit extending sign
1314 void movslq(Address dst, int32_t imm64);
1315 void movslq(Register dst, int32_t imm64);
1316
1317 void movslq(Register dst, Address src);
1318 void movslq(Register dst, Register src);
1319 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1320 #endif
1321
1322 void movswl(Register dst, Address src);
1323 void movswl(Register dst, Register src);
1324
1325 #ifdef _LP64
1326 void movswq(Register dst, Address src);
1327 void movswq(Register dst, Register src);
1328 #endif
1329
1330 void movw(Address dst, int imm16);
1331 void movw(Register dst, Address src);
1332 void movw(Address dst, Register src);
1333
1334 void movzbl(Register dst, Address src);
1335 void movzbl(Register dst, Register src);
1336
1337 #ifdef _LP64
1338 void movzbq(Register dst, Address src);
1339 void movzbq(Register dst, Register src);
1340 #endif
1341
1342 void movzwl(Register dst, Address src);
1343 void movzwl(Register dst, Register src);
1344
1345 #ifdef _LP64
1346 void movzwq(Register dst, Address src);
1347 void movzwq(Register dst, Register src);
1348 #endif
1349
1350 void mull(Address src);
1351 void mull(Register src);
1352
1353 // Multiply Scalar Double-Precision Floating-Point Values
1354 void mulsd(XMMRegister dst, Address src);
1355 void mulsd(XMMRegister dst, XMMRegister src);
1356
1357 // Multiply Scalar Single-Precision Floating-Point Values
1358 void mulss(XMMRegister dst, Address src);
1359 void mulss(XMMRegister dst, XMMRegister src);
1360
1361 void negl(Register dst);
1362
1363 #ifdef _LP64
1364 void negq(Register dst);
1365 #endif
1366
1367 void nop(int i = 1);
1368
1369 void notl(Register dst);
1370
1371 #ifdef _LP64
1372 void notq(Register dst);
1373 #endif
1374
1375 void orl(Address dst, int32_t imm32);
1376 void orl(Register dst, int32_t imm32);
1377 void orl(Register dst, Address src);
1378 void orl(Register dst, Register src);
1379
1380 void orq(Address dst, int32_t imm32);
1381 void orq(Register dst, int32_t imm32);
1382 void orq(Register dst, Address src);
1383 void orq(Register dst, Register src);
1384
1385 // Pack with unsigned saturation
1386 void packuswb(XMMRegister dst, XMMRegister src);
1387 void packuswb(XMMRegister dst, Address src);
1388
1389 // SSE4.2 string instructions
1390 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1391 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1392
1393 // SSE4.1 packed move
1394 void pmovzxbw(XMMRegister dst, XMMRegister src);
1395 void pmovzxbw(XMMRegister dst, Address src);
1396
1397 #ifndef _LP64 // no 32bit push/pop on amd64
1398 void popl(Address dst);
1399 #endif
1400
1401 #ifdef _LP64
1402 void popq(Address dst);
1403 #endif
1404
1405 void popcntl(Register dst, Address src);
1406 void popcntl(Register dst, Register src);
1407
1408 #ifdef _LP64
1409 void popcntq(Register dst, Address src);
1410 void popcntq(Register dst, Register src);
1411 #endif
1412
1413 // Prefetches (SSE, SSE2, 3DNOW only)
1414
1415 void prefetchnta(Address src);
1416 void prefetchr(Address src);
1417 void prefetcht0(Address src);
1418 void prefetcht1(Address src);
1419 void prefetcht2(Address src);
1420 void prefetchw(Address src);
1421
1422 // POR - Bitwise logical OR
1423 void por(XMMRegister dst, XMMRegister src);
1424 void por(XMMRegister dst, Address src);
1425
1426 // Shuffle Packed Doublewords
1427 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1428 void pshufd(XMMRegister dst, Address src, int mode);
1429
1430 // Shuffle Packed Low Words
1431 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1432 void pshuflw(XMMRegister dst, Address src, int mode);
1433
1434 // Shift Right by bits Logical Quadword Immediate
1435 void psrlq(XMMRegister dst, int shift);
1436
1437 // Shift Right by bytes Logical DoubleQuadword Immediate
1438 void psrldq(XMMRegister dst, int shift);
1439
1440 // Logical Compare Double Quadword
1441 void ptest(XMMRegister dst, XMMRegister src);
1442 void ptest(XMMRegister dst, Address src);
1443
1444 // Interleave Low Bytes
1445 void punpcklbw(XMMRegister dst, XMMRegister src);
1446 void punpcklbw(XMMRegister dst, Address src);
1447
1448 // Interleave Low Doublewords
1449 void punpckldq(XMMRegister dst, XMMRegister src);
1450 void punpckldq(XMMRegister dst, Address src);
1451
1452 #ifndef _LP64 // no 32bit push/pop on amd64
1453 void pushl(Address src);
1454 #endif
1455
1456 void pushq(Address src);
1457
1458 // Xor Packed Byte Integer Values
1459 void pxor(XMMRegister dst, Address src);
1460 void pxor(XMMRegister dst, XMMRegister src);
1461
1462 void rcll(Register dst, int imm8);
1463
1464 void rclq(Register dst, int imm8);
1465
1466 void ret(int imm16);
1467
1468 void sahf();
1469
1470 void sarl(Register dst, int imm8);
1471 void sarl(Register dst);
1472
1473 void sarq(Register dst, int imm8);
1474 void sarq(Register dst);
1475
1476 void sbbl(Address dst, int32_t imm32);
1477 void sbbl(Register dst, int32_t imm32);
1478 void sbbl(Register dst, Address src);
1479 void sbbl(Register dst, Register src);
1480
1481 void sbbq(Address dst, int32_t imm32);
1482 void sbbq(Register dst, int32_t imm32);
1483 void sbbq(Register dst, Address src);
1484 void sbbq(Register dst, Register src);
1485
1486 void setb(Condition cc, Register dst);
1487
1488 void shldl(Register dst, Register src);
1489
1490 void shll(Register dst, int imm8);
1491 void shll(Register dst);
1492
1493 void shlq(Register dst, int imm8);
1494 void shlq(Register dst);
1495
1496 void shrdl(Register dst, Register src);
1497
1498 void shrl(Register dst, int imm8);
1499 void shrl(Register dst);
1500
1501 void shrq(Register dst, int imm8);
1502 void shrq(Register dst);
1503
1504 void smovl(); // QQQ generic?
1505
1506 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1507 void sqrtsd(XMMRegister dst, Address src);
1508 void sqrtsd(XMMRegister dst, XMMRegister src);
1509
1510 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1511 void sqrtss(XMMRegister dst, Address src);
1512 void sqrtss(XMMRegister dst, XMMRegister src);
1513
1514 void std() { emit_byte(0xfd); }
1515
1516 void stmxcsr( Address dst );
1517
1518 void subl(Address dst, int32_t imm32);
1519 void subl(Address dst, Register src);
1520 void subl(Register dst, int32_t imm32);
1521 void subl(Register dst, Address src);
1522 void subl(Register dst, Register src);
1523
1524 void subq(Address dst, int32_t imm32);
1525 void subq(Address dst, Register src);
1526 void subq(Register dst, int32_t imm32);
1527 void subq(Register dst, Address src);
1528 void subq(Register dst, Register src);
1529
1530 void subl_imm32(Register dst, int32_t imm32);
1531 void subq_imm32(Register dst, int32_t imm32);
1532
1533 // Subtract Scalar Double-Precision Floating-Point Values
1534 void subsd(XMMRegister dst, Address src);
1535 void subsd(XMMRegister dst, XMMRegister src);
1536
1537 // Subtract Scalar Single-Precision Floating-Point Values
1538 void subss(XMMRegister dst, Address src);
1539 void subss(XMMRegister dst, XMMRegister src);
1540
1541 void testb(Register dst, int imm8);
1542
1543 void testl(Register dst, int32_t imm32);
1544 void testl(Register dst, Register src);
1545 void testl(Register dst, Address src);
1546
1547 void testq(Register dst, int32_t imm32);
1548 void testq(Register dst, Register src);
1549
1550
1551 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1552 void ucomisd(XMMRegister dst, Address src);
1553 void ucomisd(XMMRegister dst, XMMRegister src);
1554
1555 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1556 void ucomiss(XMMRegister dst, Address src);
1557 void ucomiss(XMMRegister dst, XMMRegister src);
1558
1559 void xaddl(Address dst, Register src);
1560
1561 void xaddq(Address dst, Register src);
1562
1563 void xchgl(Register reg, Address adr);
1564 void xchgl(Register dst, Register src);
1565
1566 void xchgq(Register reg, Address adr);
1567 void xchgq(Register dst, Register src);
1568
1569 // Get Value of Extended Control Register
1570 void xgetbv() {
1571 emit_byte(0x0F);
1572 emit_byte(0x01);
1573 emit_byte(0xD0);
1574 }
1575
1576 void xorl(Register dst, int32_t imm32);
1577 void xorl(Register dst, Address src);
1578 void xorl(Register dst, Register src);
1579
1580 void xorq(Register dst, Address src);
1581 void xorq(Register dst, Register src);
1582
1583 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1584 void xorpd(XMMRegister dst, XMMRegister src);
1585
1586 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1587 void xorps(XMMRegister dst, XMMRegister src);
1588
1589 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1590
1591 // AVX 3-operands instructions (encoded with VEX prefix)
1592 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1593 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1594 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1595 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1596 void vandpd(XMMRegister dst, XMMRegister nds, Address src);
1597 void vandps(XMMRegister dst, XMMRegister nds, Address src);
1598 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1599 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1600 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1601 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1602 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1603 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1604 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1605 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1606 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1607 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1608 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1609 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1610 void vxorpd(XMMRegister dst, XMMRegister nds, Address src);
1611 void vxorps(XMMRegister dst, XMMRegister nds, Address src);
1612
1613
1614 protected:
1615 // Next instructions require address alignment 16 bytes SSE mode.
1616 // They should be called only from corresponding MacroAssembler instructions.
1617 void andpd(XMMRegister dst, Address src);
1618 void andps(XMMRegister dst, Address src);
1619 void xorpd(XMMRegister dst, Address src);
1620 void xorps(XMMRegister dst, Address src);
1621
1622 };
1623
1624
1625 // MacroAssembler extends Assembler by frequently used macros.
1626 //
1627 // Instructions for which a 'better' code sequence exists depending
1628 // on arguments should also go in here.
1629
1630 class MacroAssembler: public Assembler {
1631 friend class LIR_Assembler;
1632 friend class Runtime1; // as_Address()
1633
1634 protected:
1635
1636 Address as_Address(AddressLiteral adr);
1637 Address as_Address(ArrayAddress adr);
1638
1639 // Support for VM calls
1640 //
1641 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1642 // may customize this version by overriding it for its purposes (e.g., to save/restore
1643 // additional registers when doing a VM call).
1644 #ifdef CC_INTERP
1645 // c++ interpreter never wants to use interp_masm version of call_VM
1646 #define VIRTUAL
1647 #else
1648 #define VIRTUAL virtual
1649 #endif
1650
1651 VIRTUAL void call_VM_leaf_base(
1652 address entry_point, // the entry point
1653 int number_of_arguments // the number of arguments to pop after the call
1654 );
1655
1656 // This is the base routine called by the different versions of call_VM. The interpreter
1657 // may customize this version by overriding it for its purposes (e.g., to save/restore
1658 // additional registers when doing a VM call).
1659 //
1660 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1661 // returns the register which contains the thread upon return. If a thread register has been
1662 // specified, the return value will correspond to that register. If no last_java_sp is specified
1663 // (noreg) than rsp will be used instead.
1664 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1665 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1666 Register java_thread, // the thread if computed before ; use noreg otherwise
1667 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1668 address entry_point, // the entry point
1669 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1670 bool check_exceptions // whether to check for pending exceptions after return
1671 );
1672
1673 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1674 // The implementation is only non-empty for the InterpreterMacroAssembler,
1675 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1676 virtual void check_and_handle_popframe(Register java_thread);
1677 virtual void check_and_handle_earlyret(Register java_thread);
1678
1679 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1680
1681 // helpers for FPU flag access
1682 // tmp is a temporary register, if none is available use noreg
1683 void save_rax (Register tmp);
1684 void restore_rax(Register tmp);
1685
1686 public:
1687 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1688
1689 // Support for NULL-checks
1690 //
1691 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1692 // If the accessed location is M[reg + offset] and the offset is known, provide the
1693 // offset. No explicit code generation is needed if the offset is within a certain
1694 // range (0 <= offset <= page_size).
1695
1696 void null_check(Register reg, int offset = -1);
1697 static bool needs_explicit_null_check(intptr_t offset);
1698
1699 // Required platform-specific helpers for Label::patch_instructions.
1700 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1701 void pd_patch_instruction(address branch, address target);
1702 #ifndef PRODUCT
1703 static void pd_print_patched_instruction(address branch);
1704 #endif
1705
1706 // The following 4 methods return the offset of the appropriate move instruction
1707
1708 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1709 int load_unsigned_byte(Register dst, Address src);
1710 int load_unsigned_short(Register dst, Address src);
1711
1712 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1713 int load_signed_byte(Register dst, Address src);
1714 int load_signed_short(Register dst, Address src);
1715
1716 // Support for sign-extension (hi:lo = extend_sign(lo))
1717 void extend_sign(Register hi, Register lo);
1718
1719 // Load and store values by size and signed-ness
1720 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1721 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1722
1723 // Support for inc/dec with optimal instruction selection depending on value
1724
1725 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1726 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1727
1728 void decrementl(Address dst, int value = 1);
1729 void decrementl(Register reg, int value = 1);
1730
1731 void decrementq(Register reg, int value = 1);
1732 void decrementq(Address dst, int value = 1);
1733
1734 void incrementl(Address dst, int value = 1);
1735 void incrementl(Register reg, int value = 1);
1736
1737 void incrementq(Register reg, int value = 1);
1738 void incrementq(Address dst, int value = 1);
1739
1740
1741 // Support optimal SSE move instructions.
1742 void movflt(XMMRegister dst, XMMRegister src) {
1743 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1744 else { movss (dst, src); return; }
1745 }
1746 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1747 void movflt(XMMRegister dst, AddressLiteral src);
1748 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1749
1750 void movdbl(XMMRegister dst, XMMRegister src) {
1751 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1752 else { movsd (dst, src); return; }
1753 }
1754
1755 void movdbl(XMMRegister dst, AddressLiteral src);
1756
1757 void movdbl(XMMRegister dst, Address src) {
1758 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1759 else { movlpd(dst, src); return; }
1760 }
1761 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1762
1763 void incrementl(AddressLiteral dst);
1764 void incrementl(ArrayAddress dst);
1765
1766 // Alignment
1767 void align(int modulus);
1768
1769 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1770 void fat_nop();
1771
1772 // Stack frame creation/removal
1773 void enter();
1774 void leave();
1775
1776 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1777 // The pointer will be loaded into the thread register.
1778 void get_thread(Register thread);
1779
1780
1781 // Support for VM calls
1782 //
1783 // It is imperative that all calls into the VM are handled via the call_VM macros.
1784 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1785 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1786
1787
1788 void call_VM(Register oop_result,
1789 address entry_point,
1790 bool check_exceptions = true);
1791 void call_VM(Register oop_result,
1792 address entry_point,
1793 Register arg_1,
1794 bool check_exceptions = true);
1795 void call_VM(Register oop_result,
1796 address entry_point,
1797 Register arg_1, Register arg_2,
1798 bool check_exceptions = true);
1799 void call_VM(Register oop_result,
1800 address entry_point,
1801 Register arg_1, Register arg_2, Register arg_3,
1802 bool check_exceptions = true);
1803
1804 // Overloadings with last_Java_sp
1805 void call_VM(Register oop_result,
1806 Register last_java_sp,
1807 address entry_point,
1808 int number_of_arguments = 0,
1809 bool check_exceptions = true);
1810 void call_VM(Register oop_result,
1811 Register last_java_sp,
1812 address entry_point,
1813 Register arg_1, bool
1814 check_exceptions = true);
1815 void call_VM(Register oop_result,
1816 Register last_java_sp,
1817 address entry_point,
1818 Register arg_1, Register arg_2,
1819 bool check_exceptions = true);
1820 void call_VM(Register oop_result,
1821 Register last_java_sp,
1822 address entry_point,
1823 Register arg_1, Register arg_2, Register arg_3,
1824 bool check_exceptions = true);
1825
1826 // These always tightly bind to MacroAssembler::call_VM_base
1827 // bypassing the virtual implementation
1828 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1829 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1830 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1831 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1832 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1833
1834 void call_VM_leaf(address entry_point,
1835 int number_of_arguments = 0);
1836 void call_VM_leaf(address entry_point,
1837 Register arg_1);
1838 void call_VM_leaf(address entry_point,
1839 Register arg_1, Register arg_2);
1840 void call_VM_leaf(address entry_point,
1841 Register arg_1, Register arg_2, Register arg_3);
1842
1843 // These always tightly bind to MacroAssembler::call_VM_leaf_base
1844 // bypassing the virtual implementation
1845 void super_call_VM_leaf(address entry_point);
1846 void super_call_VM_leaf(address entry_point, Register arg_1);
1847 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1848 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1849 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
1850
1851 // last Java Frame (fills frame anchor)
1852 void set_last_Java_frame(Register thread,
1853 Register last_java_sp,
1854 Register last_java_fp,
1855 address last_java_pc);
1856
1857 // thread in the default location (r15_thread on 64bit)
1858 void set_last_Java_frame(Register last_java_sp,
1859 Register last_java_fp,
1860 address last_java_pc);
1861
1862 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1863
1864 // thread in the default location (r15_thread on 64bit)
1865 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1866
1867 // Stores
1868 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1869 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1870
1871 #ifndef SERIALGC
1872
1873 void g1_write_barrier_pre(Register obj,
1874 Register pre_val,
1875 Register thread,
1876 Register tmp,
1877 bool tosca_live,
1878 bool expand_call);
1879
1880 void g1_write_barrier_post(Register store_addr,
1881 Register new_val,
1882 Register thread,
1883 Register tmp,
1884 Register tmp2);
1885
1886 #endif // SERIALGC
1887
1888 // split store_check(Register obj) to enhance instruction interleaving
1889 void store_check_part_1(Register obj);
1890 void store_check_part_2(Register obj);
1891
1892 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1893 void c2bool(Register x);
1894
1895 // C++ bool manipulation
1896
1897 void movbool(Register dst, Address src);
1898 void movbool(Address dst, bool boolconst);
1899 void movbool(Address dst, Register src);
1900 void testbool(Register dst);
1901
1902 // oop manipulations
1903 void load_klass(Register dst, Register src);
1904 void store_klass(Register dst, Register src);
1905
1906 void load_heap_oop(Register dst, Address src);
1907 void load_heap_oop_not_null(Register dst, Address src);
1908 void store_heap_oop(Address dst, Register src);
1909
1910 // Used for storing NULL. All other oop constants should be
1911 // stored using routines that take a jobject.
1912 void store_heap_oop_null(Address dst);
1913
1914 void load_prototype_header(Register dst, Register src);
1915
1916 #ifdef _LP64
1917 void store_klass_gap(Register dst, Register src);
1918
1919 // This dummy is to prevent a call to store_heap_oop from
1920 // converting a zero (like NULL) into a Register by giving
1921 // the compiler two choices it can't resolve
1922
1923 void store_heap_oop(Address dst, void* dummy);
1924
1925 void encode_heap_oop(Register r);
1926 void decode_heap_oop(Register r);
1927 void encode_heap_oop_not_null(Register r);
1928 void decode_heap_oop_not_null(Register r);
1929 void encode_heap_oop_not_null(Register dst, Register src);
1930 void decode_heap_oop_not_null(Register dst, Register src);
1931
1932 void set_narrow_oop(Register dst, jobject obj);
1933 void set_narrow_oop(Address dst, jobject obj);
1934 void cmp_narrow_oop(Register dst, jobject obj);
1935 void cmp_narrow_oop(Address dst, jobject obj);
1936
1937 // if heap base register is used - reinit it with the correct value
1938 void reinit_heapbase();
1939
1940 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1941
1942 #endif // _LP64
1943
1944 // Int division/remainder for Java
1945 // (as idivl, but checks for special case as described in JVM spec.)
1946 // returns idivl instruction offset for implicit exception handling
1947 int corrected_idivl(Register reg);
1948
1949 // Long division/remainder for Java
1950 // (as idivq, but checks for special case as described in JVM spec.)
1951 // returns idivq instruction offset for implicit exception handling
1952 int corrected_idivq(Register reg);
1953
1954 void int3();
1955
1956 // Long operation macros for a 32bit cpu
1957 // Long negation for Java
1958 void lneg(Register hi, Register lo);
1959
1960 // Long multiplication for Java
1961 // (destroys contents of eax, ebx, ecx and edx)
1962 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1963
1964 // Long shifts for Java
1965 // (semantics as described in JVM spec.)
1966 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1967 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1968
1969 // Long compare for Java
1970 // (semantics as described in JVM spec.)
1971 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1972
1973
1974 // misc
1975
1976 // Sign extension
1977 void sign_extend_short(Register reg);
1978 void sign_extend_byte(Register reg);
1979
1980 // Division by power of 2, rounding towards 0
1981 void division_with_shift(Register reg, int shift_value);
1982
1983 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1984 //
1985 // CF (corresponds to C0) if x < y
1986 // PF (corresponds to C2) if unordered
1987 // ZF (corresponds to C3) if x = y
1988 //
1989 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1990 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1991 void fcmp(Register tmp);
1992 // Variant of the above which allows y to be further down the stack
1993 // and which only pops x and y if specified. If pop_right is
1994 // specified then pop_left must also be specified.
1995 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1996
1997 // Floating-point comparison for Java
1998 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1999 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2000 // (semantics as described in JVM spec.)
2001 void fcmp2int(Register dst, bool unordered_is_less);
2002 // Variant of the above which allows y to be further down the stack
2003 // and which only pops x and y if specified. If pop_right is
2004 // specified then pop_left must also be specified.
2005 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
2006
2007 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
2008 // tmp is a temporary register, if none is available use noreg
2009 void fremr(Register tmp);
2010
2011
2012 // same as fcmp2int, but using SSE2
2013 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2014 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2015
2016 // Inlined sin/cos generator for Java; must not use CPU instruction
2017 // directly on Intel as it does not have high enough precision
2018 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2019 // number of FPU stack slots in use; all but the topmost will
2020 // require saving if a slow case is necessary. Assumes argument is
2021 // on FP TOS; result is on FP TOS. No cpu registers are changed by
2022 // this code.
2023 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2024
2025 // branch to L if FPU flag C2 is set/not set
2026 // tmp is a temporary register, if none is available use noreg
2027 void jC2 (Register tmp, Label& L);
2028 void jnC2(Register tmp, Label& L);
2029
2030 // Pop ST (ffree & fincstp combined)
2031 void fpop();
2032
2033 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2034 void push_fTOS();
2035
2036 // pops double TOS element from CPU stack and pushes on FPU stack
2037 void pop_fTOS();
2038
2039 void empty_FPU_stack();
2040
2041 void push_IU_state();
2042 void pop_IU_state();
2043
2044 void push_FPU_state();
2045 void pop_FPU_state();
2046
2047 void push_CPU_state();
2048 void pop_CPU_state();
2049
2050 // Round up to a power of two
2051 void round_to(Register reg, int modulus);
2052
2053 // Callee saved registers handling
2054 void push_callee_saved_registers();
2055 void pop_callee_saved_registers();
2056
2057 // allocation
2058 void eden_allocate(
2059 Register obj, // result: pointer to object after successful allocation
2060 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2061 int con_size_in_bytes, // object size in bytes if known at compile time
2062 Register t1, // temp register
2063 Label& slow_case // continuation point if fast allocation fails
2064 );
2065 void tlab_allocate(
2066 Register obj, // result: pointer to object after successful allocation
2067 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2068 int con_size_in_bytes, // object size in bytes if known at compile time
2069 Register t1, // temp register
2070 Register t2, // temp register
2071 Label& slow_case // continuation point if fast allocation fails
2072 );
2073 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2074 void incr_allocated_bytes(Register thread,
2075 Register var_size_in_bytes, int con_size_in_bytes,
2076 Register t1 = noreg);
2077
2078 // interface method calling
2079 void lookup_interface_method(Register recv_klass,
2080 Register intf_klass,
2081 RegisterOrConstant itable_index,
2082 Register method_result,
2083 Register scan_temp,
2084 Label& no_such_interface);
2085
2086 // Test sub_klass against super_klass, with fast and slow paths.
2087
2088 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2089 // One of the three labels can be NULL, meaning take the fall-through.
2090 // If super_check_offset is -1, the value is loaded up from super_klass.
2091 // No registers are killed, except temp_reg.
2092 void check_klass_subtype_fast_path(Register sub_klass,
2093 Register super_klass,
2094 Register temp_reg,
2095 Label* L_success,
2096 Label* L_failure,
2097 Label* L_slow_path,
2098 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2099
2100 // The rest of the type check; must be wired to a corresponding fast path.
2101 // It does not repeat the fast path logic, so don't use it standalone.
2102 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2103 // Updates the sub's secondary super cache as necessary.
2104 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2105 void check_klass_subtype_slow_path(Register sub_klass,
2106 Register super_klass,
2107 Register temp_reg,
2108 Register temp2_reg,
2109 Label* L_success,
2110 Label* L_failure,
2111 bool set_cond_codes = false);
2112
2113 // Simplified, combined version, good for typical uses.
2114 // Falls through on failure.
2115 void check_klass_subtype(Register sub_klass,
2116 Register super_klass,
2117 Register temp_reg,
2118 Label& L_success);
2119
2120 // method handles (JSR 292)
2121 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2122 Register temp_reg,
2123 Label& wrong_method_type);
2124 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2125 Register temp_reg);
2126 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2127 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2128
2129
2130 //----
2131 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2132
2133 // Debugging
2134
2135 // only if +VerifyOops
2136 void verify_oop(Register reg, const char* s = "broken oop");
2137 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2138
2139 // only if +VerifyFPU
2140 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2141
2142 // prints msg, dumps registers and stops execution
2143 void stop(const char* msg);
2144
2145 // prints msg and continues
2146 void warn(const char* msg);
2147
2148 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2149 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2150
2151 void os_breakpoint();
2152
2153 void untested() { stop("untested"); }
2154
2155 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
2156
2157 void should_not_reach_here() { stop("should not reach here"); }
2158
2159 void print_CPU_state();
2160
2161 // Stack overflow checking
2162 void bang_stack_with_offset(int offset) {
2163 // stack grows down, caller passes positive offset
2164 assert(offset > 0, "must bang with negative offset");
2165 movl(Address(rsp, (-offset)), rax);
2166 }
2167
2168 // Writes to stack successive pages until offset reached to check for
2169 // stack overflow + shadow pages. Also, clobbers tmp
2170 void bang_stack_size(Register size, Register tmp);
2171
2172 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2173 Register tmp,
2174 int offset);
2175
2176 // Support for serializing memory accesses between threads
2177 void serialize_memory(Register thread, Register tmp);
2178
2179 void verify_tlab();
2180
2181 // Biased locking support
2182 // lock_reg and obj_reg must be loaded up with the appropriate values.
2183 // swap_reg must be rax, and is killed.
2184 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2185 // be killed; if not supplied, push/pop will be used internally to
2186 // allocate a temporary (inefficient, avoid if possible).
2187 // Optional slow case is for implementations (interpreter and C1) which branch to
2188 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2189 // Returns offset of first potentially-faulting instruction for null
2190 // check info (currently consumed only by C1). If
2191 // swap_reg_contains_mark is true then returns -1 as it is assumed
2192 // the calling code has already passed any potential faults.
2193 int biased_locking_enter(Register lock_reg, Register obj_reg,
2194 Register swap_reg, Register tmp_reg,
2195 bool swap_reg_contains_mark,
2196 Label& done, Label* slow_case = NULL,
2197 BiasedLockingCounters* counters = NULL);
2198 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2199
2200
2201 Condition negate_condition(Condition cond);
2202
2203 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2204 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2205 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2206 // here in MacroAssembler. The major exception to this rule is call
2207
2208 // Arithmetics
2209
2210
2211 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2212 void addptr(Address dst, Register src);
2213
2214 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2215 void addptr(Register dst, int32_t src);
2216 void addptr(Register dst, Register src);
2217 void addptr(Register dst, RegisterOrConstant src) {
2218 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2219 else addptr(dst, src.as_register());
2220 }
2221
2222 void andptr(Register dst, int32_t src);
2223 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2224
2225 void cmp8(AddressLiteral src1, int imm);
2226
2227 // renamed to drag out the casting of address to int32_t/intptr_t
2228 void cmp32(Register src1, int32_t imm);
2229
2230 void cmp32(AddressLiteral src1, int32_t imm);
2231 // compare reg - mem, or reg - &mem
2232 void cmp32(Register src1, AddressLiteral src2);
2233
2234 void cmp32(Register src1, Address src2);
2235
2236 #ifndef _LP64
2237 void cmpoop(Address dst, jobject obj);
2238 void cmpoop(Register dst, jobject obj);
2239 #endif // _LP64
2240
2241 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2242 void cmpptr(Address src1, AddressLiteral src2);
2243
2244 void cmpptr(Register src1, AddressLiteral src2);
2245
2246 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2247 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2248 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2249
2250 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2251 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2252
2253 // cmp64 to avoild hiding cmpq
2254 void cmp64(Register src1, AddressLiteral src);
2255
2256 void cmpxchgptr(Register reg, Address adr);
2257
2258 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2259
2260
2261 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2262
2263
2264 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2265
2266 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2267
2268 void shlptr(Register dst, int32_t shift);
2269 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2270
2271 void shrptr(Register dst, int32_t shift);
2272 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2273
2274 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2275 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2276
2277 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2278
2279 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2280 void subptr(Register dst, int32_t src);
2281 void subptr_imm32(Register dst, int32_t src);
2282 void subptr(Register dst, Register src);
2283 void subptr(Register dst, RegisterOrConstant src) {
2284 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2285 else subptr(dst, src.as_register());
2286 }
2287
2288 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2289 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2290
2291 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2292 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2293
2294 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2295
2296
2297
2298 // Helper functions for statistics gathering.
2299 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2300 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2301 // Unconditional atomic increment.
2302 void atomic_incl(AddressLiteral counter_addr);
2303
2304 void lea(Register dst, AddressLiteral adr);
2305 void lea(Address dst, AddressLiteral adr);
2306 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2307
2308 void leal32(Register dst, Address src) { leal(dst, src); }
2309
2310 // Import other testl() methods from the parent class or else
2311 // they will be hidden by the following overriding declaration.
2312 using Assembler::testl;
2313 void testl(Register dst, AddressLiteral src);
2314
2315 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2316 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2317 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2318
2319 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2320 void testptr(Register src1, Register src2);
2321
2322 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2323 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2324
2325 // Calls
2326
2327 void call(Label& L, relocInfo::relocType rtype);
2328 void call(Register entry);
2329
2330 // NOTE: this call tranfers to the effective address of entry NOT
2331 // the address contained by entry. This is because this is more natural
2332 // for jumps/calls.
2333 void call(AddressLiteral entry);
2334
2335 // Jumps
2336
2337 // NOTE: these jumps tranfer to the effective address of dst NOT
2338 // the address contained by dst. This is because this is more natural
2339 // for jumps/calls.
2340 void jump(AddressLiteral dst);
2341 void jump_cc(Condition cc, AddressLiteral dst);
2342
2343 // 32bit can do a case table jump in one instruction but we no longer allow the base
2344 // to be installed in the Address class. This jump will tranfers to the address
2345 // contained in the location described by entry (not the address of entry)
2346 void jump(ArrayAddress entry);
2347
2348 // Floating
2349
2350 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2351 void andpd(XMMRegister dst, AddressLiteral src);
2352
2353 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2354 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2355 void andps(XMMRegister dst, AddressLiteral src);
2356
2357 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2358 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2359 void comiss(XMMRegister dst, AddressLiteral src);
2360
2361 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2362 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2363 void comisd(XMMRegister dst, AddressLiteral src);
2364
2365 void fadd_s(Address src) { Assembler::fadd_s(src); }
2366 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2367
2368 void fldcw(Address src) { Assembler::fldcw(src); }
2369 void fldcw(AddressLiteral src);
2370
2371 void fld_s(int index) { Assembler::fld_s(index); }
2372 void fld_s(Address src) { Assembler::fld_s(src); }
2373 void fld_s(AddressLiteral src);
2374
2375 void fld_d(Address src) { Assembler::fld_d(src); }
2376 void fld_d(AddressLiteral src);
2377
2378 void fld_x(Address src) { Assembler::fld_x(src); }
2379 void fld_x(AddressLiteral src);
2380
2381 void fmul_s(Address src) { Assembler::fmul_s(src); }
2382 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2383
2384 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2385 void ldmxcsr(AddressLiteral src);
2386
2387 private:
2388 // these are private because users should be doing movflt/movdbl
2389
2390 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2391 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2392 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2393 void movss(XMMRegister dst, AddressLiteral src);
2394
2395 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2396 void movlpd(XMMRegister dst, AddressLiteral src);
2397
2398 public:
2399
2400 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2401 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2402 void addsd(XMMRegister dst, AddressLiteral src);
2403
2404 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2405 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2406 void addss(XMMRegister dst, AddressLiteral src);
2407
2408 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2409 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2410 void divsd(XMMRegister dst, AddressLiteral src);
2411
2412 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2413 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2414 void divss(XMMRegister dst, AddressLiteral src);
2415
2416 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2417 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2418 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2419 void movsd(XMMRegister dst, AddressLiteral src);
2420
2421 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2422 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2423 void mulsd(XMMRegister dst, AddressLiteral src);
2424
2425 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2426 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2427 void mulss(XMMRegister dst, AddressLiteral src);
2428
2429 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2430 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2431 void sqrtsd(XMMRegister dst, AddressLiteral src);
2432
2433 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2434 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2435 void sqrtss(XMMRegister dst, AddressLiteral src);
2436
2437 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2438 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2439 void subsd(XMMRegister dst, AddressLiteral src);
2440
2441 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2442 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2443 void subss(XMMRegister dst, AddressLiteral src);
2444
2445 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2446 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2447 void ucomiss(XMMRegister dst, AddressLiteral src);
2448
2449 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2450 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2451 void ucomisd(XMMRegister dst, AddressLiteral src);
2452
2453 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2454 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2455 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2456 void xorpd(XMMRegister dst, AddressLiteral src);
2457
2458 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2459 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2460 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2461 void xorps(XMMRegister dst, AddressLiteral src);
2462
2463 // AVX 3-operands instructions
2464
2465 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2466 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
2467 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2468
2469 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2470 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2471 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2472
2473 void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); }
2474 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2475
2476 void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); }
2477 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2478
2479 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2480 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2481 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2482
2483 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2484 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
2485 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2486
2487 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2488 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
2489 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2490
2491 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2492 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
2493 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2494
2495 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2496 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
2497 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2498
2499 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2500 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
2501 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2502
2503 void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); }
2504 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2505
2506 void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); }
2507 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2508
2509
2510 // Data
2511
2512 void cmov32( Condition cc, Register dst, Address src);
2513 void cmov32( Condition cc, Register dst, Register src);
2514
2515 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2516
2517 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2518 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2519
2520 void movoop(Register dst, jobject obj);
2521 void movoop(Address dst, jobject obj);
2522
2523 void movptr(ArrayAddress dst, Register src);
2524 // can this do an lea?
2525 void movptr(Register dst, ArrayAddress src);
2526
2527 void movptr(Register dst, Address src);
2528
2529 void movptr(Register dst, AddressLiteral src);
2530
2531 void movptr(Register dst, intptr_t src);
2532 void movptr(Register dst, Register src);
2533 void movptr(Address dst, intptr_t src);
2534
2535 void movptr(Address dst, Register src);
2536
2537 void movptr(Register dst, RegisterOrConstant src) {
2538 if (src.is_constant()) movptr(dst, src.as_constant());
2539 else movptr(dst, src.as_register());
2540 }
2541
2542 #ifdef _LP64
2543 // Generally the next two are only used for moving NULL
2544 // Although there are situations in initializing the mark word where
2545 // they could be used. They are dangerous.
2546
2547 // They only exist on LP64 so that int32_t and intptr_t are not the same
2548 // and we have ambiguous declarations.
2549
2550 void movptr(Address dst, int32_t imm32);
2551 void movptr(Register dst, int32_t imm32);
2552 #endif // _LP64
2553
2554 // to avoid hiding movl
2555 void mov32(AddressLiteral dst, Register src);
2556 void mov32(Register dst, AddressLiteral src);
2557
2558 // to avoid hiding movb
2559 void movbyte(ArrayAddress dst, int src);
2560
2561 // Can push value or effective address
2562 void pushptr(AddressLiteral src);
2563
2564 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2565 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2566
2567 void pushoop(jobject obj);
2568
2569 // sign extend as need a l to ptr sized element
2570 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2571 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2572
2573 // C2 compiled method's prolog code.
2574 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
2575
2576 // IndexOf strings.
2577 // Small strings are loaded through stack if they cross page boundary.
2578 void string_indexof(Register str1, Register str2,
2579 Register cnt1, Register cnt2,
2580 int int_cnt2, Register result,
2581 XMMRegister vec, Register tmp);
2582
2583 // IndexOf for constant substrings with size >= 8 elements
2584 // which don't need to be loaded through stack.
2585 void string_indexofC8(Register str1, Register str2,
2586 Register cnt1, Register cnt2,
2587 int int_cnt2, Register result,
2588 XMMRegister vec, Register tmp);
2589
2590 // Smallest code: we don't need to load through stack,
2591 // check string tail.
2592
2593 // Compare strings.
2594 void string_compare(Register str1, Register str2,
2595 Register cnt1, Register cnt2, Register result,
2596 XMMRegister vec1);
2597
2598 // Compare char[] arrays.
2599 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2600 Register limit, Register result, Register chr,
2601 XMMRegister vec1, XMMRegister vec2);
2602
2603 // Fill primitive arrays
2604 void generate_fill(BasicType t, bool aligned,
2605 Register to, Register value, Register count,
2606 Register rtmp, XMMRegister xtmp);
2607
2608 #undef VIRTUAL
2609
2610 };
2611
2612 /**
2613 * class SkipIfEqual:
2614 *
2615 * Instantiating this class will result in assembly code being output that will
2616 * jump around any code emitted between the creation of the instance and it's
2617 * automatic destruction at the end of a scope block, depending on the value of
2618 * the flag passed to the constructor, which will be checked at run-time.
2619 */
2620 class SkipIfEqual {
2621 private:
2622 MacroAssembler* _masm;
2623 Label _label;
2624
2625 public:
2626 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2627 ~SkipIfEqual();
2628 };
2629
2630 #ifdef ASSERT
2631 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2632 #endif
2633
2634 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP