1 //
2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
242
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
246
247 #define __ _masm.
248
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
251
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
255
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
266
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
269
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
275
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
282
283 static int preserve_SP_size() {
284 return 2; // op, rm(reg/reg)
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
296
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
300
301 static int sizeof_FFree_Float_Stack_All = -1;
302
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
307
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
313
314 //
315 // Compute padding required for nodes which need alignment
316 //
317
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
325
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
334
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
343
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
349
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 cbuf.insts()->emit_int8(c);
354 }
355
356 // EMIT_CC()
357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
358 unsigned char c = (unsigned char)( f1 | f2 );
359 cbuf.insts()->emit_int8(c);
360 }
361
362 // EMIT_OPCODE()
363 void emit_opcode(CodeBuffer &cbuf, int code) {
364 cbuf.insts()->emit_int8((unsigned char) code);
365 }
366
367 // EMIT_OPCODE() w/ relocation information
368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
369 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
370 emit_opcode(cbuf, code);
371 }
372
373 // EMIT_D8()
374 void emit_d8(CodeBuffer &cbuf, int d8) {
375 cbuf.insts()->emit_int8((unsigned char) d8);
376 }
377
378 // EMIT_D16()
379 void emit_d16(CodeBuffer &cbuf, int d16) {
380 cbuf.insts()->emit_int16(d16);
381 }
382
383 // EMIT_D32()
384 void emit_d32(CodeBuffer &cbuf, int d32) {
385 cbuf.insts()->emit_int32(d32);
386 }
387
388 // emit 32 bit value and construct relocation entry from relocInfo::relocType
389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
390 int format) {
391 cbuf.relocate(cbuf.insts_mark(), reloc, format);
392 cbuf.insts()->emit_int32(d32);
393 }
394
395 // emit 32 bit value and construct relocation entry from RelocationHolder
396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
397 int format) {
398 #ifdef ASSERT
399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
401 }
402 #endif
403 cbuf.relocate(cbuf.insts_mark(), rspec, format);
404 cbuf.insts()->emit_int32(d32);
405 }
406
407 // Access stack slot for load or store
408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
410 if( -128 <= disp && disp <= 127 ) {
411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
413 emit_d8 (cbuf, disp); // Displacement // R/M byte
414 } else {
415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
417 emit_d32(cbuf, disp); // Displacement // R/M byte
418 }
419 }
420
421 // eRegI ereg, memory mem) %{ // emit_reg_mem
422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
423 // There is no index & no scale, use form without SIB byte
424 if ((index == 0x4) &&
425 (scale == 0) && (base != ESP_enc)) {
426 // If no displacement, mode is 0x0; unless base is [EBP]
427 if ( (displace == 0) && (base != EBP_enc) ) {
428 emit_rm(cbuf, 0x0, reg_encoding, base);
429 }
430 else { // If 8-bit displacement, mode 0x1
431 if ((displace >= -128) && (displace <= 127)
432 && !(displace_is_oop) ) {
433 emit_rm(cbuf, 0x1, reg_encoding, base);
434 emit_d8(cbuf, displace);
435 }
436 else { // If 32-bit displacement
437 if (base == -1) { // Special flag for absolute address
438 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
439 // (manual lies; no SIB needed here)
440 if ( displace_is_oop ) {
441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
442 } else {
443 emit_d32 (cbuf, displace);
444 }
445 }
446 else { // Normal base + offset
447 emit_rm(cbuf, 0x2, reg_encoding, base);
448 if ( displace_is_oop ) {
449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
450 } else {
451 emit_d32 (cbuf, displace);
452 }
453 }
454 }
455 }
456 }
457 else { // Else, encode with the SIB byte
458 // If no displacement, mode is 0x0; unless base is [EBP]
459 if (displace == 0 && (base != EBP_enc)) { // If no displacement
460 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 }
463 else { // If 8-bit displacement, mode 0x1
464 if ((displace >= -128) && (displace <= 127)
465 && !(displace_is_oop) ) {
466 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, base);
468 emit_d8(cbuf, displace);
469 }
470 else { // If 32-bit displacement
471 if (base == 0x04 ) {
472 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
473 emit_rm(cbuf, scale, index, 0x04);
474 } else {
475 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
476 emit_rm(cbuf, scale, index, base);
477 }
478 if ( displace_is_oop ) {
479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
480 } else {
481 emit_d32 (cbuf, displace);
482 }
483 }
484 }
485 }
486 }
487
488
489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
490 if( dst_encoding == src_encoding ) {
491 // reg-reg copy, use an empty encoding
492 } else {
493 emit_opcode( cbuf, 0x8B );
494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
495 }
496 }
497
498 void emit_cmpfp_fixup(MacroAssembler& _masm) {
499 Label exit;
500 __ jccb(Assembler::noParity, exit);
501 __ pushf();
502 //
503 // comiss/ucomiss instructions set ZF,PF,CF flags and
504 // zero OF,AF,SF for NaN values.
505 // Fixup flags by zeroing ZF,PF so that compare of NaN
506 // values returns 'less than' result (CF is set).
507 // Leave the rest of flags unchanged.
508 //
509 // 7 6 5 4 3 2 1 0
510 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
511 // 0 0 1 0 1 0 1 1 (0x2B)
512 //
513 __ andl(Address(rsp, 0), 0xffffff2b);
514 __ popf();
515 __ bind(exit);
516 }
517
518 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
519 Label done;
520 __ movl(dst, -1);
521 __ jcc(Assembler::parity, done);
522 __ jcc(Assembler::below, done);
523 __ setb(Assembler::notEqual, dst);
524 __ movzbl(dst, dst);
525 __ bind(done);
526 }
527
528
529 //=============================================================================
530 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
531
532 int Compile::ConstantTable::calculate_table_base_offset() const {
533 return 0; // absolute addressing, no offset
534 }
535
536 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
537 // Empty encoding
538 }
539
540 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
541 return 0;
542 }
543
544 #ifndef PRODUCT
545 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
546 st->print("# MachConstantBaseNode (empty encoding)");
547 }
548 #endif
549
550
551 //=============================================================================
552 #ifndef PRODUCT
553 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
554 Compile* C = ra_->C;
555
556 int framesize = C->frame_slots() << LogBytesPerInt;
557 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
558 // Remove wordSize for return addr which is already pushed.
559 framesize -= wordSize;
560
561 if (C->need_stack_bang(framesize)) {
562 framesize -= wordSize;
563 st->print("# stack bang");
564 st->print("\n\t");
565 st->print("PUSH EBP\t# Save EBP");
566 if (framesize) {
567 st->print("\n\t");
568 st->print("SUB ESP, #%d\t# Create frame",framesize);
569 }
570 } else {
571 st->print("SUB ESP, #%d\t# Create frame",framesize);
572 st->print("\n\t");
573 framesize -= wordSize;
574 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
575 }
576
577 if (VerifyStackAtCalls) {
578 st->print("\n\t");
579 framesize -= wordSize;
580 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
581 }
582
583 if( C->in_24_bit_fp_mode() ) {
584 st->print("\n\t");
585 st->print("FLDCW \t# load 24 bit fpu control word");
586 }
587 if (UseSSE >= 2 && VerifyFPU) {
588 st->print("\n\t");
589 st->print("# verify FPU stack (must be clean on entry)");
590 }
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 st->print("\n\t");
595 st->print("# stack alignment check");
596 }
597 #endif
598 st->cr();
599 }
600 #endif
601
602
603 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
604 Compile* C = ra_->C;
605 MacroAssembler _masm(&cbuf);
606
607 int framesize = C->frame_slots() << LogBytesPerInt;
608
609 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
610
611 C->set_frame_complete(cbuf.insts_size());
612
613 if (C->has_mach_constant_base_node()) {
614 // NOTE: We set the table base offset here because users might be
615 // emitted before MachConstantBaseNode.
616 Compile::ConstantTable& constant_table = C->constant_table();
617 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
618 }
619 }
620
621 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
622 return MachNode::size(ra_); // too many variables; just compute it the hard way
623 }
624
625 int MachPrologNode::reloc() const {
626 return 0; // a large enough number
627 }
628
629 //=============================================================================
630 #ifndef PRODUCT
631 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
632 Compile *C = ra_->C;
633 int framesize = C->frame_slots() << LogBytesPerInt;
634 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
635 // Remove two words for return addr and rbp,
636 framesize -= 2*wordSize;
637
638 if( C->in_24_bit_fp_mode() ) {
639 st->print("FLDCW standard control word");
640 st->cr(); st->print("\t");
641 }
642 if( framesize ) {
643 st->print("ADD ESP,%d\t# Destroy frame",framesize);
644 st->cr(); st->print("\t");
645 }
646 st->print_cr("POPL EBP"); st->print("\t");
647 if( do_polling() && C->is_method_compilation() ) {
648 st->print("TEST PollPage,EAX\t! Poll Safepoint");
649 st->cr(); st->print("\t");
650 }
651 }
652 #endif
653
654 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656
657 // If method set FPU control word, restore to standard control word
658 if( C->in_24_bit_fp_mode() ) {
659 MacroAssembler masm(&cbuf);
660 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
661 }
662
663 int framesize = C->frame_slots() << LogBytesPerInt;
664 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
665 // Remove two words for return addr and rbp,
666 framesize -= 2*wordSize;
667
668 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
669
670 if( framesize >= 128 ) {
671 emit_opcode(cbuf, 0x81); // add SP, #framesize
672 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
673 emit_d32(cbuf, framesize);
674 }
675 else if( framesize ) {
676 emit_opcode(cbuf, 0x83); // add SP, #framesize
677 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
678 emit_d8(cbuf, framesize);
679 }
680
681 emit_opcode(cbuf, 0x58 | EBP_enc);
682
683 if( do_polling() && C->is_method_compilation() ) {
684 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
685 emit_opcode(cbuf,0x85);
686 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
687 emit_d32(cbuf, (intptr_t)os::get_polling_page());
688 }
689 }
690
691 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
692 Compile *C = ra_->C;
693 // If method set FPU control word, restore to standard control word
694 int size = C->in_24_bit_fp_mode() ? 6 : 0;
695 if( do_polling() && C->is_method_compilation() ) size += 6;
696
697 int framesize = C->frame_slots() << LogBytesPerInt;
698 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
699 // Remove two words for return addr and rbp,
700 framesize -= 2*wordSize;
701
702 size++; // popl rbp,
703
704 if( framesize >= 128 ) {
705 size += 6;
706 } else {
707 size += framesize ? 3 : 0;
708 }
709 return size;
710 }
711
712 int MachEpilogNode::reloc() const {
713 return 0; // a large enough number
714 }
715
716 const Pipeline * MachEpilogNode::pipeline() const {
717 return MachNode::pipeline_class();
718 }
719
720 int MachEpilogNode::safepoint_offset() const { return 0; }
721
722 //=============================================================================
723
724 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
725 static enum RC rc_class( OptoReg::Name reg ) {
726
727 if( !OptoReg::is_valid(reg) ) return rc_bad;
728 if (OptoReg::is_stack(reg)) return rc_stack;
729
730 VMReg r = OptoReg::as_VMReg(reg);
731 if (r->is_Register()) return rc_int;
732 if (r->is_FloatRegister()) {
733 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
734 return rc_float;
735 }
736 assert(r->is_XMMRegister(), "must be");
737 return rc_xmm;
738 }
739
740 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
741 int opcode, const char *op_str, int size, outputStream* st ) {
742 if( cbuf ) {
743 emit_opcode (*cbuf, opcode );
744 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
745 #ifndef PRODUCT
746 } else if( !do_size ) {
747 if( size != 0 ) st->print("\n\t");
748 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
749 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
750 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
751 } else { // FLD, FST, PUSH, POP
752 st->print("%s [ESP + #%d]",op_str,offset);
753 }
754 #endif
755 }
756 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
757 return size+3+offset_size;
758 }
759
760 // Helper for XMM registers. Extra opcode bits, limited syntax.
761 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
762 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
763 if (cbuf) {
764 MacroAssembler _masm(cbuf);
765 if (reg_lo+1 == reg_hi) { // double move?
766 if (is_load) {
767 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
768 } else {
769 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
770 }
771 } else {
772 if (is_load) {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
774 } else {
775 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
776 }
777 }
778 #ifndef PRODUCT
779 } else if (!do_size) {
780 if (size != 0) st->print("\n\t");
781 if (reg_lo+1 == reg_hi) { // double move?
782 if (is_load) st->print("%s %s,[ESP + #%d]",
783 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
784 Matcher::regName[reg_lo], offset);
785 else st->print("MOVSD [ESP + #%d],%s",
786 offset, Matcher::regName[reg_lo]);
787 } else {
788 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
789 Matcher::regName[reg_lo], offset);
790 else st->print("MOVSS [ESP + #%d],%s",
791 offset, Matcher::regName[reg_lo]);
792 }
793 #endif
794 }
795 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
796 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
797 return size+5+offset_size;
798 }
799
800
801 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
802 int src_hi, int dst_hi, int size, outputStream* st ) {
803 if (cbuf) {
804 MacroAssembler _masm(cbuf);
805 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
806 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
807 as_XMMRegister(Matcher::_regEncode[src_lo]));
808 } else {
809 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
810 as_XMMRegister(Matcher::_regEncode[src_lo]));
811 }
812 #ifndef PRODUCT
813 } else if (!do_size) {
814 if (size != 0) st->print("\n\t");
815 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
816 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
817 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
818 } else {
819 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 }
821 } else {
822 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
823 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
824 } else {
825 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
826 }
827 }
828 #endif
829 }
830 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
831 // Only MOVAPS SSE prefix uses 1 byte.
832 int sz = 4;
833 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
834 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
835 return size + sz;
836 }
837
838 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
839 int src_hi, int dst_hi, int size, outputStream* st ) {
840 // 32-bit
841 if (cbuf) {
842 MacroAssembler _masm(cbuf);
843 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
844 as_Register(Matcher::_regEncode[src_lo]));
845 #ifndef PRODUCT
846 } else if (!do_size) {
847 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
848 #endif
849 }
850 return 4;
851 }
852
853
854 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
855 int src_hi, int dst_hi, int size, outputStream* st ) {
856 // 32-bit
857 if (cbuf) {
858 MacroAssembler _masm(cbuf);
859 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
860 as_XMMRegister(Matcher::_regEncode[src_lo]));
861 #ifndef PRODUCT
862 } else if (!do_size) {
863 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
864 #endif
865 }
866 return 4;
867 }
868
869 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
870 if( cbuf ) {
871 emit_opcode(*cbuf, 0x8B );
872 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
873 #ifndef PRODUCT
874 } else if( !do_size ) {
875 if( size != 0 ) st->print("\n\t");
876 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
877 #endif
878 }
879 return size+2;
880 }
881
882 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
883 int offset, int size, outputStream* st ) {
884 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
885 if( cbuf ) {
886 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
887 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
888 #ifndef PRODUCT
889 } else if( !do_size ) {
890 if( size != 0 ) st->print("\n\t");
891 st->print("FLD %s",Matcher::regName[src_lo]);
892 #endif
893 }
894 size += 2;
895 }
896
897 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
898 const char *op_str;
899 int op;
900 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
901 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
902 op = 0xDD;
903 } else { // 32-bit store
904 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
905 op = 0xD9;
906 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
907 }
908
909 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
910 }
911
912 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
913 // Get registers to move
914 OptoReg::Name src_second = ra_->get_reg_second(in(1));
915 OptoReg::Name src_first = ra_->get_reg_first(in(1));
916 OptoReg::Name dst_second = ra_->get_reg_second(this );
917 OptoReg::Name dst_first = ra_->get_reg_first(this );
918
919 enum RC src_second_rc = rc_class(src_second);
920 enum RC src_first_rc = rc_class(src_first);
921 enum RC dst_second_rc = rc_class(dst_second);
922 enum RC dst_first_rc = rc_class(dst_first);
923
924 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
925
926 // Generate spill code!
927 int size = 0;
928
929 if( src_first == dst_first && src_second == dst_second )
930 return size; // Self copy, no move
931
932 // --------------------------------------
933 // Check for mem-mem move. push/pop to move.
934 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
935 if( src_second == dst_first ) { // overlapping stack copy ranges
936 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
937 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
938 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
939 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
940 }
941 // move low bits
942 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
943 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
944 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
945 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
946 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
947 }
948 return size;
949 }
950
951 // --------------------------------------
952 // Check for integer reg-reg copy
953 if( src_first_rc == rc_int && dst_first_rc == rc_int )
954 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
955
956 // Check for integer store
957 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
958 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
959
960 // Check for integer load
961 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
962 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
963
964 // Check for integer reg-xmm reg copy
965 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
966 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
967 "no 64 bit integer-float reg moves" );
968 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
969 }
970 // --------------------------------------
971 // Check for float reg-reg copy
972 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
973 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
974 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
975 if( cbuf ) {
976
977 // Note the mucking with the register encode to compensate for the 0/1
978 // indexing issue mentioned in a comment in the reg_def sections
979 // for FPR registers many lines above here.
980
981 if( src_first != FPR1L_num ) {
982 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
983 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
984 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
985 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
986 } else {
987 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
988 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
989 }
990 #ifndef PRODUCT
991 } else if( !do_size ) {
992 if( size != 0 ) st->print("\n\t");
993 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
994 else st->print( "FST %s", Matcher::regName[dst_first]);
995 #endif
996 }
997 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
998 }
999
1000 // Check for float store
1001 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1002 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1003 }
1004
1005 // Check for float load
1006 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1007 int offset = ra_->reg2offset(src_first);
1008 const char *op_str;
1009 int op;
1010 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1011 op_str = "FLD_D";
1012 op = 0xDD;
1013 } else { // 32-bit load
1014 op_str = "FLD_S";
1015 op = 0xD9;
1016 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1017 }
1018 if( cbuf ) {
1019 emit_opcode (*cbuf, op );
1020 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1021 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1022 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1023 #ifndef PRODUCT
1024 } else if( !do_size ) {
1025 if( size != 0 ) st->print("\n\t");
1026 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1027 #endif
1028 }
1029 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1030 return size + 3+offset_size+2;
1031 }
1032
1033 // Check for xmm reg-reg copy
1034 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1035 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1036 (src_first+1 == src_second && dst_first+1 == dst_second),
1037 "no non-adjacent float-moves" );
1038 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1039 }
1040
1041 // Check for xmm reg-integer reg copy
1042 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1043 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1044 "no 64 bit float-integer reg moves" );
1045 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1046 }
1047
1048 // Check for xmm store
1049 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1050 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1051 }
1052
1053 // Check for float xmm load
1054 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1055 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1056 }
1057
1058 // Copy from float reg to xmm reg
1059 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1060 // copy to the top of stack from floating point reg
1061 // and use LEA to preserve flags
1062 if( cbuf ) {
1063 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1064 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1065 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1066 emit_d8(*cbuf,0xF8);
1067 #ifndef PRODUCT
1068 } else if( !do_size ) {
1069 if( size != 0 ) st->print("\n\t");
1070 st->print("LEA ESP,[ESP-8]");
1071 #endif
1072 }
1073 size += 4;
1074
1075 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1076
1077 // Copy from the temp memory to the xmm reg.
1078 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1079
1080 if( cbuf ) {
1081 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1082 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1083 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1084 emit_d8(*cbuf,0x08);
1085 #ifndef PRODUCT
1086 } else if( !do_size ) {
1087 if( size != 0 ) st->print("\n\t");
1088 st->print("LEA ESP,[ESP+8]");
1089 #endif
1090 }
1091 size += 4;
1092 return size;
1093 }
1094
1095 assert( size > 0, "missed a case" );
1096
1097 // --------------------------------------------------------------------
1098 // Check for second bits still needing moving.
1099 if( src_second == dst_second )
1100 return size; // Self copy; no move
1101 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1102
1103 // Check for second word int-int move
1104 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1105 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1106
1107 // Check for second word integer store
1108 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1109 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1110
1111 // Check for second word integer load
1112 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1113 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1114
1115
1116 Unimplemented();
1117 }
1118
1119 #ifndef PRODUCT
1120 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1121 implementation( NULL, ra_, false, st );
1122 }
1123 #endif
1124
1125 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1126 implementation( &cbuf, ra_, false, NULL );
1127 }
1128
1129 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1130 return implementation( NULL, ra_, true, NULL );
1131 }
1132
1133 //=============================================================================
1134 #ifndef PRODUCT
1135 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1136 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1137 }
1138 #endif
1139
1140 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1141 MacroAssembler _masm(&cbuf);
1142 __ nop(_count);
1143 }
1144
1145 uint MachNopNode::size(PhaseRegAlloc *) const {
1146 return _count;
1147 }
1148
1149
1150 //=============================================================================
1151 #ifndef PRODUCT
1152 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1153 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1154 int reg = ra_->get_reg_first(this);
1155 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1156 }
1157 #endif
1158
1159 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1160 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1161 int reg = ra_->get_encode(this);
1162 if( offset >= 128 ) {
1163 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1164 emit_rm(cbuf, 0x2, reg, 0x04);
1165 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1166 emit_d32(cbuf, offset);
1167 }
1168 else {
1169 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1170 emit_rm(cbuf, 0x1, reg, 0x04);
1171 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1172 emit_d8(cbuf, offset);
1173 }
1174 }
1175
1176 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1177 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1178 if( offset >= 128 ) {
1179 return 7;
1180 }
1181 else {
1182 return 4;
1183 }
1184 }
1185
1186 //=============================================================================
1187
1188 // emit call stub, compiled java to interpreter
1189 void emit_java_to_interp(CodeBuffer &cbuf ) {
1190 // Stub is fixed up when the corresponding call is converted from calling
1191 // compiled code to calling interpreted code.
1192 // mov rbx,0
1193 // jmp -1
1194
1195 address mark = cbuf.insts_mark(); // get mark within main instrs section
1196
1197 // Note that the code buffer's insts_mark is always relative to insts.
1198 // That's why we must use the macroassembler to generate a stub.
1199 MacroAssembler _masm(&cbuf);
1200
1201 address base =
1202 __ start_a_stub(Compile::MAX_stubs_size);
1203 if (base == NULL) return; // CodeBuffer::expand failed
1204 // static stub relocation stores the instruction address of the call
1205 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1206 // static stub relocation also tags the methodOop in the code-stream.
1207 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1208 // This is recognized as unresolved by relocs/nativeInst/ic code
1209 __ jump(RuntimeAddress(__ pc()));
1210
1211 __ end_a_stub();
1212 // Update current stubs pointer and restore insts_end.
1213 }
1214 // size of call stub, compiled java to interpretor
1215 uint size_java_to_interp() {
1216 return 10; // movl; jmp
1217 }
1218 // relocation entries for call stub, compiled java to interpretor
1219 uint reloc_java_to_interp() {
1220 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1221 }
1222
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1227 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1228 st->print_cr("\tNOP");
1229 st->print_cr("\tNOP");
1230 if( !OptoBreakpoint )
1231 st->print_cr("\tNOP");
1232 }
1233 #endif
1234
1235 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1236 MacroAssembler masm(&cbuf);
1237 #ifdef ASSERT
1238 uint insts_size = cbuf.insts_size();
1239 #endif
1240 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1241 masm.jump_cc(Assembler::notEqual,
1242 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1243 /* WARNING these NOPs are critical so that verified entry point is properly
1244 aligned for patching by NativeJump::patch_verified_entry() */
1245 int nops_cnt = 2;
1246 if( !OptoBreakpoint ) // Leave space for int3
1247 nops_cnt += 1;
1248 masm.nop(nops_cnt);
1249
1250 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1251 }
1252
1253 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1254 return OptoBreakpoint ? 11 : 12;
1255 }
1256
1257
1258 //=============================================================================
1259 uint size_exception_handler() {
1260 // NativeCall instruction size is the same as NativeJump.
1261 // exception handler starts out as jump and can be patched to
1262 // a call be deoptimization. (4932387)
1263 // Note that this value is also credited (in output.cpp) to
1264 // the size of the code section.
1265 return NativeJump::instruction_size;
1266 }
1267
1268 // Emit exception handler code. Stuff framesize into a register
1269 // and call a VM stub routine.
1270 int emit_exception_handler(CodeBuffer& cbuf) {
1271
1272 // Note that the code buffer's insts_mark is always relative to insts.
1273 // That's why we must use the macroassembler to generate a handler.
1274 MacroAssembler _masm(&cbuf);
1275 address base =
1276 __ start_a_stub(size_exception_handler());
1277 if (base == NULL) return 0; // CodeBuffer::expand failed
1278 int offset = __ offset();
1279 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1280 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1281 __ end_a_stub();
1282 return offset;
1283 }
1284
1285 uint size_deopt_handler() {
1286 // NativeCall instruction size is the same as NativeJump.
1287 // exception handler starts out as jump and can be patched to
1288 // a call be deoptimization. (4932387)
1289 // Note that this value is also credited (in output.cpp) to
1290 // the size of the code section.
1291 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1292 }
1293
1294 // Emit deopt handler code.
1295 int emit_deopt_handler(CodeBuffer& cbuf) {
1296
1297 // Note that the code buffer's insts_mark is always relative to insts.
1298 // That's why we must use the macroassembler to generate a handler.
1299 MacroAssembler _masm(&cbuf);
1300 address base =
1301 __ start_a_stub(size_exception_handler());
1302 if (base == NULL) return 0; // CodeBuffer::expand failed
1303 int offset = __ offset();
1304 InternalAddress here(__ pc());
1305 __ pushptr(here.addr());
1306
1307 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1308 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1309 __ end_a_stub();
1310 return offset;
1311 }
1312
1313
1314 const bool Matcher::match_rule_supported(int opcode) {
1315 if (!has_match_rule(opcode))
1316 return false;
1317
1318 return true; // Per default match rules are supported.
1319 }
1320
1321 int Matcher::regnum_to_fpu_offset(int regnum) {
1322 return regnum - 32; // The FP registers are in the second chunk
1323 }
1324
1325 // This is UltraSparc specific, true just means we have fast l2f conversion
1326 const bool Matcher::convL2FSupported(void) {
1327 return true;
1328 }
1329
1330 // Vector width in bytes
1331 const uint Matcher::vector_width_in_bytes(void) {
1332 return UseSSE >= 2 ? 8 : 0;
1333 }
1334
1335 // Vector ideal reg
1336 const uint Matcher::vector_ideal_reg(void) {
1337 return Op_RegD;
1338 }
1339
1340 // Is this branch offset short enough that a short branch can be used?
1341 //
1342 // NOTE: If the platform does not provide any short branch variants, then
1343 // this method should return false for offset 0.
1344 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1345 // The passed offset is relative to address of the branch.
1346 // On 86 a branch displacement is calculated relative to address
1347 // of a next instruction.
1348 offset -= br_size;
1349
1350 // the short version of jmpConUCF2 contains multiple branches,
1351 // making the reach slightly less
1352 if (rule == jmpConUCF2_rule)
1353 return (-126 <= offset && offset <= 125);
1354 return (-128 <= offset && offset <= 127);
1355 }
1356
1357 const bool Matcher::isSimpleConstant64(jlong value) {
1358 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1359 return false;
1360 }
1361
1362 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1363 const bool Matcher::init_array_count_is_in_bytes = false;
1364
1365 // Threshold size for cleararray.
1366 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1367
1368 // Needs 2 CMOV's for longs.
1369 const int Matcher::long_cmove_cost() { return 1; }
1370
1371 // No CMOVF/CMOVD with SSE/SSE2
1372 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1373
1374 // Should the Matcher clone shifts on addressing modes, expecting them to
1375 // be subsumed into complex addressing expressions or compute them into
1376 // registers? True for Intel but false for most RISCs
1377 const bool Matcher::clone_shift_expressions = true;
1378
1379 // Do we need to mask the count passed to shift instructions or does
1380 // the cpu only look at the lower 5/6 bits anyway?
1381 const bool Matcher::need_masked_shift_count = false;
1382
1383 bool Matcher::narrow_oop_use_complex_address() {
1384 ShouldNotCallThis();
1385 return true;
1386 }
1387
1388
1389 // Is it better to copy float constants, or load them directly from memory?
1390 // Intel can load a float constant from a direct address, requiring no
1391 // extra registers. Most RISCs will have to materialize an address into a
1392 // register first, so they would do better to copy the constant from stack.
1393 const bool Matcher::rematerialize_float_constants = true;
1394
1395 // If CPU can load and store mis-aligned doubles directly then no fixup is
1396 // needed. Else we split the double into 2 integer pieces and move it
1397 // piece-by-piece. Only happens when passing doubles into C code as the
1398 // Java calling convention forces doubles to be aligned.
1399 const bool Matcher::misaligned_doubles_ok = true;
1400
1401
1402 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1403 // Get the memory operand from the node
1404 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1405 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1406 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1407 uint opcnt = 1; // First operand
1408 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1409 while( idx >= skipped+num_edges ) {
1410 skipped += num_edges;
1411 opcnt++; // Bump operand count
1412 assert( opcnt < numopnds, "Accessing non-existent operand" );
1413 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1414 }
1415
1416 MachOper *memory = node->_opnds[opcnt];
1417 MachOper *new_memory = NULL;
1418 switch (memory->opcode()) {
1419 case DIRECT:
1420 case INDOFFSET32X:
1421 // No transformation necessary.
1422 return;
1423 case INDIRECT:
1424 new_memory = new (C) indirect_win95_safeOper( );
1425 break;
1426 case INDOFFSET8:
1427 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1428 break;
1429 case INDOFFSET32:
1430 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1431 break;
1432 case INDINDEXOFFSET:
1433 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1434 break;
1435 case INDINDEXSCALE:
1436 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1437 break;
1438 case INDINDEXSCALEOFFSET:
1439 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1440 break;
1441 case LOAD_LONG_INDIRECT:
1442 case LOAD_LONG_INDOFFSET32:
1443 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1444 return;
1445 default:
1446 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1447 return;
1448 }
1449 node->_opnds[opcnt] = new_memory;
1450 }
1451
1452 // Advertise here if the CPU requires explicit rounding operations
1453 // to implement the UseStrictFP mode.
1454 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1455
1456 // Are floats conerted to double when stored to stack during deoptimization?
1457 // On x32 it is stored with convertion only when FPU is used for floats.
1458 bool Matcher::float_in_double() { return (UseSSE == 0); }
1459
1460 // Do ints take an entire long register or just half?
1461 const bool Matcher::int_in_long = false;
1462
1463 // Return whether or not this register is ever used as an argument. This
1464 // function is used on startup to build the trampoline stubs in generateOptoStub.
1465 // Registers not mentioned will be killed by the VM call in the trampoline, and
1466 // arguments in those registers not be available to the callee.
1467 bool Matcher::can_be_java_arg( int reg ) {
1468 if( reg == ECX_num || reg == EDX_num ) return true;
1469 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1470 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1471 return false;
1472 }
1473
1474 bool Matcher::is_spillable_arg( int reg ) {
1475 return can_be_java_arg(reg);
1476 }
1477
1478 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1479 // Use hardware integer DIV instruction when
1480 // it is faster than a code which use multiply.
1481 // Only when constant divisor fits into 32 bit
1482 // (min_jint is excluded to get only correct
1483 // positive 32 bit values from negative).
1484 return VM_Version::has_fast_idiv() &&
1485 (divisor == (int)divisor && divisor != min_jint);
1486 }
1487
1488 // Register for DIVI projection of divmodI
1489 RegMask Matcher::divI_proj_mask() {
1490 return EAX_REG_mask();
1491 }
1492
1493 // Register for MODI projection of divmodI
1494 RegMask Matcher::modI_proj_mask() {
1495 return EDX_REG_mask();
1496 }
1497
1498 // Register for DIVL projection of divmodL
1499 RegMask Matcher::divL_proj_mask() {
1500 ShouldNotReachHere();
1501 return RegMask();
1502 }
1503
1504 // Register for MODL projection of divmodL
1505 RegMask Matcher::modL_proj_mask() {
1506 ShouldNotReachHere();
1507 return RegMask();
1508 }
1509
1510 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1511 return EBP_REG_mask();
1512 }
1513
1514 // Returns true if the high 32 bits of the value is known to be zero.
1515 bool is_operand_hi32_zero(Node* n) {
1516 int opc = n->Opcode();
1517 if (opc == Op_LoadUI2L) {
1518 return true;
1519 }
1520 if (opc == Op_AndL) {
1521 Node* o2 = n->in(2);
1522 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1523 return true;
1524 }
1525 }
1526 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1527 return true;
1528 }
1529 return false;
1530 }
1531
1532 %}
1533
1534 //----------ENCODING BLOCK-----------------------------------------------------
1535 // This block specifies the encoding classes used by the compiler to output
1536 // byte streams. Encoding classes generate functions which are called by
1537 // Machine Instruction Nodes in order to generate the bit encoding of the
1538 // instruction. Operands specify their base encoding interface with the
1539 // interface keyword. There are currently supported four interfaces,
1540 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1541 // operand to generate a function which returns its register number when
1542 // queried. CONST_INTER causes an operand to generate a function which
1543 // returns the value of the constant when queried. MEMORY_INTER causes an
1544 // operand to generate four functions which return the Base Register, the
1545 // Index Register, the Scale Value, and the Offset Value of the operand when
1546 // queried. COND_INTER causes an operand to generate six functions which
1547 // return the encoding code (ie - encoding bits for the instruction)
1548 // associated with each basic boolean condition for a conditional instruction.
1549 // Instructions specify two basic values for encoding. They use the
1550 // ins_encode keyword to specify their encoding class (which must be one of
1551 // the class names specified in the encoding block), and they use the
1552 // opcode keyword to specify, in order, their primary, secondary, and
1553 // tertiary opcode. Only the opcode sections which a particular instruction
1554 // needs for encoding need to be specified.
1555 encode %{
1556 // Build emit functions for each basic byte or larger field in the intel
1557 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1558 // code in the enc_class source block. Emit functions will live in the
1559 // main source block for now. In future, we can generalize this by
1560 // adding a syntax that specifies the sizes of fields in an order,
1561 // so that the adlc can build the emit functions automagically
1562
1563 // Emit primary opcode
1564 enc_class OpcP %{
1565 emit_opcode(cbuf, $primary);
1566 %}
1567
1568 // Emit secondary opcode
1569 enc_class OpcS %{
1570 emit_opcode(cbuf, $secondary);
1571 %}
1572
1573 // Emit opcode directly
1574 enc_class Opcode(immI d8) %{
1575 emit_opcode(cbuf, $d8$$constant);
1576 %}
1577
1578 enc_class SizePrefix %{
1579 emit_opcode(cbuf,0x66);
1580 %}
1581
1582 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1583 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1584 %}
1585
1586 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1587 emit_opcode(cbuf,$opcode$$constant);
1588 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1589 %}
1590
1591 enc_class mov_r32_imm0( eRegI dst ) %{
1592 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1593 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1594 %}
1595
1596 enc_class cdq_enc %{
1597 // Full implementation of Java idiv and irem; checks for
1598 // special case as described in JVM spec., p.243 & p.271.
1599 //
1600 // normal case special case
1601 //
1602 // input : rax,: dividend min_int
1603 // reg: divisor -1
1604 //
1605 // output: rax,: quotient (= rax, idiv reg) min_int
1606 // rdx: remainder (= rax, irem reg) 0
1607 //
1608 // Code sequnce:
1609 //
1610 // 81 F8 00 00 00 80 cmp rax,80000000h
1611 // 0F 85 0B 00 00 00 jne normal_case
1612 // 33 D2 xor rdx,edx
1613 // 83 F9 FF cmp rcx,0FFh
1614 // 0F 84 03 00 00 00 je done
1615 // normal_case:
1616 // 99 cdq
1617 // F7 F9 idiv rax,ecx
1618 // done:
1619 //
1620 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1621 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1622 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1623 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1624 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1625 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1626 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1627 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1628 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1629 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1630 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1631 // normal_case:
1632 emit_opcode(cbuf,0x99); // cdq
1633 // idiv (note: must be emitted by the user of this rule)
1634 // normal:
1635 %}
1636
1637 // Dense encoding for older common ops
1638 enc_class Opc_plus(immI opcode, eRegI reg) %{
1639 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1640 %}
1641
1642
1643 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1644 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1645 // Check for 8-bit immediate, and set sign extend bit in opcode
1646 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1647 emit_opcode(cbuf, $primary | 0x02);
1648 }
1649 else { // If 32-bit immediate
1650 emit_opcode(cbuf, $primary);
1651 }
1652 %}
1653
1654 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1655 // Emit primary opcode and set sign-extend bit
1656 // Check for 8-bit immediate, and set sign extend bit in opcode
1657 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1658 emit_opcode(cbuf, $primary | 0x02); }
1659 else { // If 32-bit immediate
1660 emit_opcode(cbuf, $primary);
1661 }
1662 // Emit r/m byte with secondary opcode, after primary opcode.
1663 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1664 %}
1665
1666 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1667 // Check for 8-bit immediate, and set sign extend bit in opcode
1668 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1669 $$$emit8$imm$$constant;
1670 }
1671 else { // If 32-bit immediate
1672 // Output immediate
1673 $$$emit32$imm$$constant;
1674 }
1675 %}
1676
1677 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1678 // Emit primary opcode and set sign-extend bit
1679 // Check for 8-bit immediate, and set sign extend bit in opcode
1680 int con = (int)$imm$$constant; // Throw away top bits
1681 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1682 // Emit r/m byte with secondary opcode, after primary opcode.
1683 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1684 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1685 else emit_d32(cbuf,con);
1686 %}
1687
1688 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1689 // Emit primary opcode and set sign-extend bit
1690 // Check for 8-bit immediate, and set sign extend bit in opcode
1691 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1692 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1693 // Emit r/m byte with tertiary opcode, after primary opcode.
1694 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1695 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1696 else emit_d32(cbuf,con);
1697 %}
1698
1699 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1700 emit_cc(cbuf, $secondary, $dst$$reg );
1701 %}
1702
1703 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1704 int destlo = $dst$$reg;
1705 int desthi = HIGH_FROM_LOW(destlo);
1706 // bswap lo
1707 emit_opcode(cbuf, 0x0F);
1708 emit_cc(cbuf, 0xC8, destlo);
1709 // bswap hi
1710 emit_opcode(cbuf, 0x0F);
1711 emit_cc(cbuf, 0xC8, desthi);
1712 // xchg lo and hi
1713 emit_opcode(cbuf, 0x87);
1714 emit_rm(cbuf, 0x3, destlo, desthi);
1715 %}
1716
1717 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1718 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1719 %}
1720
1721 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1722 $$$emit8$primary;
1723 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1724 %}
1725
1726 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1727 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1728 emit_d8(cbuf, op >> 8 );
1729 emit_d8(cbuf, op & 255);
1730 %}
1731
1732 // emulate a CMOV with a conditional branch around a MOV
1733 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1734 // Invert sense of branch from sense of CMOV
1735 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1736 emit_d8( cbuf, $brOffs$$constant );
1737 %}
1738
1739 enc_class enc_PartialSubtypeCheck( ) %{
1740 Register Redi = as_Register(EDI_enc); // result register
1741 Register Reax = as_Register(EAX_enc); // super class
1742 Register Recx = as_Register(ECX_enc); // killed
1743 Register Resi = as_Register(ESI_enc); // sub class
1744 Label miss;
1745
1746 MacroAssembler _masm(&cbuf);
1747 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1748 NULL, &miss,
1749 /*set_cond_codes:*/ true);
1750 if ($primary) {
1751 __ xorptr(Redi, Redi);
1752 }
1753 __ bind(miss);
1754 %}
1755
1756 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1757 MacroAssembler masm(&cbuf);
1758 int start = masm.offset();
1759 if (UseSSE >= 2) {
1760 if (VerifyFPU) {
1761 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1762 }
1763 } else {
1764 // External c_calling_convention expects the FPU stack to be 'clean'.
1765 // Compiled code leaves it dirty. Do cleanup now.
1766 masm.empty_FPU_stack();
1767 }
1768 if (sizeof_FFree_Float_Stack_All == -1) {
1769 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1770 } else {
1771 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1772 }
1773 %}
1774
1775 enc_class Verify_FPU_For_Leaf %{
1776 if( VerifyFPU ) {
1777 MacroAssembler masm(&cbuf);
1778 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1779 }
1780 %}
1781
1782 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1783 // This is the instruction starting address for relocation info.
1784 cbuf.set_insts_mark();
1785 $$$emit8$primary;
1786 // CALL directly to the runtime
1787 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1788 runtime_call_Relocation::spec(), RELOC_IMM32 );
1789
1790 if (UseSSE >= 2) {
1791 MacroAssembler _masm(&cbuf);
1792 BasicType rt = tf()->return_type();
1793
1794 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1795 // A C runtime call where the return value is unused. In SSE2+
1796 // mode the result needs to be removed from the FPU stack. It's
1797 // likely that this function call could be removed by the
1798 // optimizer if the C function is a pure function.
1799 __ ffree(0);
1800 } else if (rt == T_FLOAT) {
1801 __ lea(rsp, Address(rsp, -4));
1802 __ fstp_s(Address(rsp, 0));
1803 __ movflt(xmm0, Address(rsp, 0));
1804 __ lea(rsp, Address(rsp, 4));
1805 } else if (rt == T_DOUBLE) {
1806 __ lea(rsp, Address(rsp, -8));
1807 __ fstp_d(Address(rsp, 0));
1808 __ movdbl(xmm0, Address(rsp, 0));
1809 __ lea(rsp, Address(rsp, 8));
1810 }
1811 }
1812 %}
1813
1814
1815 enc_class pre_call_FPU %{
1816 // If method sets FPU control word restore it here
1817 debug_only(int off0 = cbuf.insts_size());
1818 if( Compile::current()->in_24_bit_fp_mode() ) {
1819 MacroAssembler masm(&cbuf);
1820 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1821 }
1822 debug_only(int off1 = cbuf.insts_size());
1823 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1824 %}
1825
1826 enc_class post_call_FPU %{
1827 // If method sets FPU control word do it here also
1828 if( Compile::current()->in_24_bit_fp_mode() ) {
1829 MacroAssembler masm(&cbuf);
1830 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1831 }
1832 %}
1833
1834 enc_class preserve_SP %{
1835 debug_only(int off0 = cbuf.insts_size());
1836 MacroAssembler _masm(&cbuf);
1837 // RBP is preserved across all calls, even compiled calls.
1838 // Use it to preserve RSP in places where the callee might change the SP.
1839 __ movptr(rbp_mh_SP_save, rsp);
1840 debug_only(int off1 = cbuf.insts_size());
1841 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1842 %}
1843
1844 enc_class restore_SP %{
1845 MacroAssembler _masm(&cbuf);
1846 __ movptr(rsp, rbp_mh_SP_save);
1847 %}
1848
1849 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1850 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1851 // who we intended to call.
1852 cbuf.set_insts_mark();
1853 $$$emit8$primary;
1854 if ( !_method ) {
1855 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1856 runtime_call_Relocation::spec(), RELOC_IMM32 );
1857 } else if(_optimized_virtual) {
1858 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1859 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1860 } else {
1861 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1862 static_call_Relocation::spec(), RELOC_IMM32 );
1863 }
1864 if( _method ) { // Emit stub for static call
1865 emit_java_to_interp(cbuf);
1866 }
1867 %}
1868
1869 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1870 // !!!!!
1871 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1872 // emit_call_dynamic_prologue( cbuf );
1873 cbuf.set_insts_mark();
1874 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1875 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1876 address virtual_call_oop_addr = cbuf.insts_mark();
1877 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1878 // who we intended to call.
1879 cbuf.set_insts_mark();
1880 $$$emit8$primary;
1881 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1882 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1883 %}
1884
1885 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1886 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1887 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1888
1889 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1890 cbuf.set_insts_mark();
1891 $$$emit8$primary;
1892 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1893 emit_d8(cbuf, disp); // Displacement
1894
1895 %}
1896
1897 // Following encoding is no longer used, but may be restored if calling
1898 // convention changes significantly.
1899 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1900 //
1901 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1902 // // int ic_reg = Matcher::inline_cache_reg();
1903 // // int ic_encode = Matcher::_regEncode[ic_reg];
1904 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1905 // // int imo_encode = Matcher::_regEncode[imo_reg];
1906 //
1907 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1908 // // // so we load it immediately before the call
1909 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1910 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1911 //
1912 // // xor rbp,ebp
1913 // emit_opcode(cbuf, 0x33);
1914 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1915 //
1916 // // CALL to interpreter.
1917 // cbuf.set_insts_mark();
1918 // $$$emit8$primary;
1919 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1920 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1921 // %}
1922
1923 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1924 $$$emit8$primary;
1925 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1926 $$$emit8$shift$$constant;
1927 %}
1928
1929 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1933 $$$emit32$src$$constant;
1934 %}
1935
1936 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1937 // Load immediate does not have a zero or sign extended version
1938 // for 8-bit immediates
1939 emit_opcode(cbuf, $primary + $dst$$reg);
1940 $$$emit32$src$$constant;
1941 %}
1942
1943 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1944 // Load immediate does not have a zero or sign extended version
1945 // for 8-bit immediates
1946 int dst_enc = $dst$$reg;
1947 int src_con = $src$$constant & 0x0FFFFFFFFL;
1948 if (src_con == 0) {
1949 // xor dst, dst
1950 emit_opcode(cbuf, 0x33);
1951 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1952 } else {
1953 emit_opcode(cbuf, $primary + dst_enc);
1954 emit_d32(cbuf, src_con);
1955 }
1956 %}
1957
1958 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1959 // Load immediate does not have a zero or sign extended version
1960 // for 8-bit immediates
1961 int dst_enc = $dst$$reg + 2;
1962 int src_con = ((julong)($src$$constant)) >> 32;
1963 if (src_con == 0) {
1964 // xor dst, dst
1965 emit_opcode(cbuf, 0x33);
1966 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1967 } else {
1968 emit_opcode(cbuf, $primary + dst_enc);
1969 emit_d32(cbuf, src_con);
1970 }
1971 %}
1972
1973
1974 // Encode a reg-reg copy. If it is useless, then empty encoding.
1975 enc_class enc_Copy( eRegI dst, eRegI src ) %{
1976 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1977 %}
1978
1979 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
1980 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1981 %}
1982
1983 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1988 $$$emit8$primary;
1989 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1990 %}
1991
1992 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1993 $$$emit8$secondary;
1994 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1995 %}
1996
1997 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1998 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1999 %}
2000
2001 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2006 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2007 %}
2008
2009 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2010 // Output immediate
2011 $$$emit32$src$$constant;
2012 %}
2013
2014 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2015 // Output Float immediate bits
2016 jfloat jf = $src$$constant;
2017 int jf_as_bits = jint_cast( jf );
2018 emit_d32(cbuf, jf_as_bits);
2019 %}
2020
2021 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2022 // Output Float immediate bits
2023 jfloat jf = $src$$constant;
2024 int jf_as_bits = jint_cast( jf );
2025 emit_d32(cbuf, jf_as_bits);
2026 %}
2027
2028 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2029 // Output immediate
2030 $$$emit16$src$$constant;
2031 %}
2032
2033 enc_class Con_d32(immI src) %{
2034 emit_d32(cbuf,$src$$constant);
2035 %}
2036
2037 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2038 // Output immediate memory reference
2039 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2040 emit_d32(cbuf, 0x00);
2041 %}
2042
2043 enc_class lock_prefix( ) %{
2044 if( os::is_MP() )
2045 emit_opcode(cbuf,0xF0); // [Lock]
2046 %}
2047
2048 // Cmp-xchg long value.
2049 // Note: we need to swap rbx, and rcx before and after the
2050 // cmpxchg8 instruction because the instruction uses
2051 // rcx as the high order word of the new value to store but
2052 // our register encoding uses rbx,.
2053 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2054
2055 // XCHG rbx,ecx
2056 emit_opcode(cbuf,0x87);
2057 emit_opcode(cbuf,0xD9);
2058 // [Lock]
2059 if( os::is_MP() )
2060 emit_opcode(cbuf,0xF0);
2061 // CMPXCHG8 [Eptr]
2062 emit_opcode(cbuf,0x0F);
2063 emit_opcode(cbuf,0xC7);
2064 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2065 // XCHG rbx,ecx
2066 emit_opcode(cbuf,0x87);
2067 emit_opcode(cbuf,0xD9);
2068 %}
2069
2070 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074
2075 // CMPXCHG [Eptr]
2076 emit_opcode(cbuf,0x0F);
2077 emit_opcode(cbuf,0xB1);
2078 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2079 %}
2080
2081 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2082 int res_encoding = $res$$reg;
2083
2084 // MOV res,0
2085 emit_opcode( cbuf, 0xB8 + res_encoding);
2086 emit_d32( cbuf, 0 );
2087 // JNE,s fail
2088 emit_opcode(cbuf,0x75);
2089 emit_d8(cbuf, 5 );
2090 // MOV res,1
2091 emit_opcode( cbuf, 0xB8 + res_encoding);
2092 emit_d32( cbuf, 1 );
2093 // fail:
2094 %}
2095
2096 enc_class set_instruction_start( ) %{
2097 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2098 %}
2099
2100 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2101 int reg_encoding = $ereg$$reg;
2102 int base = $mem$$base;
2103 int index = $mem$$index;
2104 int scale = $mem$$scale;
2105 int displace = $mem$$disp;
2106 bool disp_is_oop = $mem->disp_is_oop();
2107 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2108 %}
2109
2110 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2111 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2112 int base = $mem$$base;
2113 int index = $mem$$index;
2114 int scale = $mem$$scale;
2115 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2116 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2117 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2118 %}
2119
2120 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2121 int r1, r2;
2122 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2123 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,$tertiary);
2126 emit_rm(cbuf, 0x3, r1, r2);
2127 emit_d8(cbuf,$cnt$$constant);
2128 emit_d8(cbuf,$primary);
2129 emit_rm(cbuf, 0x3, $secondary, r1);
2130 emit_d8(cbuf,$cnt$$constant);
2131 %}
2132
2133 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2134 emit_opcode( cbuf, 0x8B ); // Move
2135 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2136 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2137 emit_d8(cbuf,$primary);
2138 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2139 emit_d8(cbuf,$cnt$$constant-32);
2140 }
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2143 emit_d8(cbuf,31);
2144 %}
2145
2146 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2147 int r1, r2;
2148 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2149 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2150
2151 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2152 emit_rm(cbuf, 0x3, r1, r2);
2153 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2154 emit_opcode(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, r1);
2156 emit_d8(cbuf,$cnt$$constant-32);
2157 }
2158 emit_opcode(cbuf,0x33); // XOR r2,r2
2159 emit_rm(cbuf, 0x3, r2, r2);
2160 %}
2161
2162 // Clone of RegMem but accepts an extra parameter to access each
2163 // half of a double in memory; it never needs relocation info.
2164 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2165 emit_opcode(cbuf,$opcode$$constant);
2166 int reg_encoding = $rm_reg$$reg;
2167 int base = $mem$$base;
2168 int index = $mem$$index;
2169 int scale = $mem$$scale;
2170 int displace = $mem$$disp + $disp_for_half$$constant;
2171 bool disp_is_oop = false;
2172 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2173 %}
2174
2175 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2176 //
2177 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2178 // and it never needs relocation information.
2179 // Frequently used to move data between FPU's Stack Top and memory.
2180 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2181 int rm_byte_opcode = $rm_opcode$$constant;
2182 int base = $mem$$base;
2183 int index = $mem$$index;
2184 int scale = $mem$$scale;
2185 int displace = $mem$$disp;
2186 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2187 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2188 %}
2189
2190 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2191 int rm_byte_opcode = $rm_opcode$$constant;
2192 int base = $mem$$base;
2193 int index = $mem$$index;
2194 int scale = $mem$$scale;
2195 int displace = $mem$$disp;
2196 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2197 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2198 %}
2199
2200 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2201 int reg_encoding = $dst$$reg;
2202 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2203 int index = 0x04; // 0x04 indicates no index
2204 int scale = 0x00; // 0x00 indicates no scale
2205 int displace = $src1$$constant; // 0x00 indicates no displacement
2206 bool disp_is_oop = false;
2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2208 %}
2209
2210 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2211 // Compare dst,src
2212 emit_opcode(cbuf,0x3B);
2213 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2214 // jmp dst < src around move
2215 emit_opcode(cbuf,0x7C);
2216 emit_d8(cbuf,2);
2217 // move dst,src
2218 emit_opcode(cbuf,0x8B);
2219 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2220 %}
2221
2222 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2223 // Compare dst,src
2224 emit_opcode(cbuf,0x3B);
2225 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2226 // jmp dst > src around move
2227 emit_opcode(cbuf,0x7F);
2228 emit_d8(cbuf,2);
2229 // move dst,src
2230 emit_opcode(cbuf,0x8B);
2231 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232 %}
2233
2234 enc_class enc_FPR_store(memory mem, regDPR src) %{
2235 // If src is FPR1, we can just FST to store it.
2236 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2237 int reg_encoding = 0x2; // Just store
2238 int base = $mem$$base;
2239 int index = $mem$$index;
2240 int scale = $mem$$scale;
2241 int displace = $mem$$disp;
2242 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2243 if( $src$$reg != FPR1L_enc ) {
2244 reg_encoding = 0x3; // Store & pop
2245 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2246 emit_d8( cbuf, 0xC0-1+$src$$reg );
2247 }
2248 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2249 emit_opcode(cbuf,$primary);
2250 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2251 %}
2252
2253 enc_class neg_reg(eRegI dst) %{
2254 // NEG $dst
2255 emit_opcode(cbuf,0xF7);
2256 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2257 %}
2258
2259 enc_class setLT_reg(eCXRegI dst) %{
2260 // SETLT $dst
2261 emit_opcode(cbuf,0x0F);
2262 emit_opcode(cbuf,0x9C);
2263 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2264 %}
2265
2266 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2267 int tmpReg = $tmp$$reg;
2268
2269 // SUB $p,$q
2270 emit_opcode(cbuf,0x2B);
2271 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2272 // SBB $tmp,$tmp
2273 emit_opcode(cbuf,0x1B);
2274 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2275 // AND $tmp,$y
2276 emit_opcode(cbuf,0x23);
2277 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2278 // ADD $p,$tmp
2279 emit_opcode(cbuf,0x03);
2280 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2281 %}
2282
2283 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2284 int tmpReg = $tmp$$reg;
2285
2286 // SUB $p,$q
2287 emit_opcode(cbuf,0x2B);
2288 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2289 // SBB $tmp,$tmp
2290 emit_opcode(cbuf,0x1B);
2291 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2292 // AND $tmp,$y
2293 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2294 emit_opcode(cbuf,0x23);
2295 int reg_encoding = tmpReg;
2296 int base = $mem$$base;
2297 int index = $mem$$index;
2298 int scale = $mem$$scale;
2299 int displace = $mem$$disp;
2300 bool disp_is_oop = $mem->disp_is_oop();
2301 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2302 // ADD $p,$tmp
2303 emit_opcode(cbuf,0x03);
2304 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2305 %}
2306
2307 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2308 // TEST shift,32
2309 emit_opcode(cbuf,0xF7);
2310 emit_rm(cbuf, 0x3, 0, ECX_enc);
2311 emit_d32(cbuf,0x20);
2312 // JEQ,s small
2313 emit_opcode(cbuf, 0x74);
2314 emit_d8(cbuf, 0x04);
2315 // MOV $dst.hi,$dst.lo
2316 emit_opcode( cbuf, 0x8B );
2317 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2318 // CLR $dst.lo
2319 emit_opcode(cbuf, 0x33);
2320 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2321 // small:
2322 // SHLD $dst.hi,$dst.lo,$shift
2323 emit_opcode(cbuf,0x0F);
2324 emit_opcode(cbuf,0xA5);
2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2326 // SHL $dst.lo,$shift"
2327 emit_opcode(cbuf,0xD3);
2328 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2329 %}
2330
2331 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2332 // TEST shift,32
2333 emit_opcode(cbuf,0xF7);
2334 emit_rm(cbuf, 0x3, 0, ECX_enc);
2335 emit_d32(cbuf,0x20);
2336 // JEQ,s small
2337 emit_opcode(cbuf, 0x74);
2338 emit_d8(cbuf, 0x04);
2339 // MOV $dst.lo,$dst.hi
2340 emit_opcode( cbuf, 0x8B );
2341 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2342 // CLR $dst.hi
2343 emit_opcode(cbuf, 0x33);
2344 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2345 // small:
2346 // SHRD $dst.lo,$dst.hi,$shift
2347 emit_opcode(cbuf,0x0F);
2348 emit_opcode(cbuf,0xAD);
2349 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2350 // SHR $dst.hi,$shift"
2351 emit_opcode(cbuf,0xD3);
2352 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2353 %}
2354
2355 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2356 // TEST shift,32
2357 emit_opcode(cbuf,0xF7);
2358 emit_rm(cbuf, 0x3, 0, ECX_enc);
2359 emit_d32(cbuf,0x20);
2360 // JEQ,s small
2361 emit_opcode(cbuf, 0x74);
2362 emit_d8(cbuf, 0x05);
2363 // MOV $dst.lo,$dst.hi
2364 emit_opcode( cbuf, 0x8B );
2365 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2366 // SAR $dst.hi,31
2367 emit_opcode(cbuf, 0xC1);
2368 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2369 emit_d8(cbuf, 0x1F );
2370 // small:
2371 // SHRD $dst.lo,$dst.hi,$shift
2372 emit_opcode(cbuf,0x0F);
2373 emit_opcode(cbuf,0xAD);
2374 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2375 // SAR $dst.hi,$shift"
2376 emit_opcode(cbuf,0xD3);
2377 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2378 %}
2379
2380
2381 // ----------------- Encodings for floating point unit -----------------
2382 // May leave result in FPU-TOS or FPU reg depending on opcodes
2383 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2384 $$$emit8$primary;
2385 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2386 %}
2387
2388 // Pop argument in FPR0 with FSTP ST(0)
2389 enc_class PopFPU() %{
2390 emit_opcode( cbuf, 0xDD );
2391 emit_d8( cbuf, 0xD8 );
2392 %}
2393
2394 // !!!!! equivalent to Pop_Reg_F
2395 enc_class Pop_Reg_DPR( regDPR dst ) %{
2396 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2397 emit_d8( cbuf, 0xD8+$dst$$reg );
2398 %}
2399
2400 enc_class Push_Reg_DPR( regDPR dst ) %{
2401 emit_opcode( cbuf, 0xD9 );
2402 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2403 %}
2404
2405 enc_class strictfp_bias1( regDPR dst ) %{
2406 emit_opcode( cbuf, 0xDB ); // FLD m80real
2407 emit_opcode( cbuf, 0x2D );
2408 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2409 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2410 emit_opcode( cbuf, 0xC8+$dst$$reg );
2411 %}
2412
2413 enc_class strictfp_bias2( regDPR dst ) %{
2414 emit_opcode( cbuf, 0xDB ); // FLD m80real
2415 emit_opcode( cbuf, 0x2D );
2416 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2417 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2418 emit_opcode( cbuf, 0xC8+$dst$$reg );
2419 %}
2420
2421 // Special case for moving an integer register to a stack slot.
2422 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2423 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2424 %}
2425
2426 // Special case for moving a register to a stack slot.
2427 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2428 // Opcode already emitted
2429 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2430 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2431 emit_d32(cbuf, $dst$$disp); // Displacement
2432 %}
2433
2434 // Push the integer in stackSlot 'src' onto FP-stack
2435 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2436 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2437 %}
2438
2439 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2440 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2441 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2442 %}
2443
2444 // Same as Pop_Mem_F except for opcode
2445 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2446 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2447 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2448 %}
2449
2450 enc_class Pop_Reg_FPR( regFPR dst ) %{
2451 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2452 emit_d8( cbuf, 0xD8+$dst$$reg );
2453 %}
2454
2455 enc_class Push_Reg_FPR( regFPR dst ) %{
2456 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2457 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2458 %}
2459
2460 // Push FPU's float to a stack-slot, and pop FPU-stack
2461 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2462 int pop = 0x02;
2463 if ($src$$reg != FPR1L_enc) {
2464 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2465 emit_d8( cbuf, 0xC0-1+$src$$reg );
2466 pop = 0x03;
2467 }
2468 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2469 %}
2470
2471 // Push FPU's double to a stack-slot, and pop FPU-stack
2472 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2473 int pop = 0x02;
2474 if ($src$$reg != FPR1L_enc) {
2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2476 emit_d8( cbuf, 0xC0-1+$src$$reg );
2477 pop = 0x03;
2478 }
2479 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2480 %}
2481
2482 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2483 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2484 int pop = 0xD0 - 1; // -1 since we skip FLD
2485 if ($src$$reg != FPR1L_enc) {
2486 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2487 emit_d8( cbuf, 0xC0-1+$src$$reg );
2488 pop = 0xD8;
2489 }
2490 emit_opcode( cbuf, 0xDD );
2491 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2492 %}
2493
2494
2495 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2496 // load dst in FPR0
2497 emit_opcode( cbuf, 0xD9 );
2498 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2499 if ($src$$reg != FPR1L_enc) {
2500 // fincstp
2501 emit_opcode (cbuf, 0xD9);
2502 emit_opcode (cbuf, 0xF7);
2503 // swap src with FPR1:
2504 // FXCH FPR1 with src
2505 emit_opcode(cbuf, 0xD9);
2506 emit_d8(cbuf, 0xC8-1+$src$$reg );
2507 // fdecstp
2508 emit_opcode (cbuf, 0xD9);
2509 emit_opcode (cbuf, 0xF6);
2510 }
2511 %}
2512
2513 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2514 MacroAssembler _masm(&cbuf);
2515 __ subptr(rsp, 8);
2516 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2517 __ fld_d(Address(rsp, 0));
2518 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2519 __ fld_d(Address(rsp, 0));
2520 %}
2521
2522 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ subptr(rsp, 4);
2525 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2526 __ fld_s(Address(rsp, 0));
2527 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2528 __ fld_s(Address(rsp, 0));
2529 %}
2530
2531 enc_class Push_ResultD(regD dst) %{
2532 MacroAssembler _masm(&cbuf);
2533 __ fstp_d(Address(rsp, 0));
2534 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2535 __ addptr(rsp, 8);
2536 %}
2537
2538 enc_class Push_ResultF(regF dst, immI d8) %{
2539 MacroAssembler _masm(&cbuf);
2540 __ fstp_s(Address(rsp, 0));
2541 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2542 __ addptr(rsp, $d8$$constant);
2543 %}
2544
2545 enc_class Push_SrcD(regD src) %{
2546 MacroAssembler _masm(&cbuf);
2547 __ subptr(rsp, 8);
2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2549 __ fld_d(Address(rsp, 0));
2550 %}
2551
2552 enc_class push_stack_temp_qword() %{
2553 MacroAssembler _masm(&cbuf);
2554 __ subptr(rsp, 8);
2555 %}
2556
2557 enc_class pop_stack_temp_qword() %{
2558 MacroAssembler _masm(&cbuf);
2559 __ addptr(rsp, 8);
2560 %}
2561
2562 enc_class push_xmm_to_fpr1(regD src) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2565 __ fld_d(Address(rsp, 0));
2566 %}
2567
2568 // Compute X^Y using Intel's fast hardware instructions, if possible.
2569 // Otherwise return a NaN.
2570 enc_class pow_exp_core_encoding %{
2571 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2572 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2573 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2574 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2575 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2576 emit_opcode(cbuf,0x1C);
2577 emit_d8(cbuf,0x24);
2578 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2579 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2580 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2581 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2582 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2583 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2584 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2585 emit_d32(cbuf,0xFFFFF800);
2586 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2587 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2588 emit_d32(cbuf,1023);
2589 emit_opcode(cbuf,0x8B); // mov rbx,eax
2590 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2591 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2592 emit_rm(cbuf,0x3,0x4,EAX_enc);
2593 emit_d8(cbuf,20);
2594 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2595 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2596 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2597 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2598 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2599 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2600 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2601 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2602 emit_d32(cbuf,0);
2603 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2604 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2605 %}
2606
2607 enc_class Push_Result_Mod_DPR( regDPR src) %{
2608 if ($src$$reg != FPR1L_enc) {
2609 // fincstp
2610 emit_opcode (cbuf, 0xD9);
2611 emit_opcode (cbuf, 0xF7);
2612 // FXCH FPR1 with src
2613 emit_opcode(cbuf, 0xD9);
2614 emit_d8(cbuf, 0xC8-1+$src$$reg );
2615 // fdecstp
2616 emit_opcode (cbuf, 0xD9);
2617 emit_opcode (cbuf, 0xF6);
2618 }
2619 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2620 // // FSTP FPR$dst$$reg
2621 // emit_opcode( cbuf, 0xDD );
2622 // emit_d8( cbuf, 0xD8+$dst$$reg );
2623 %}
2624
2625 enc_class fnstsw_sahf_skip_parity() %{
2626 // fnstsw ax
2627 emit_opcode( cbuf, 0xDF );
2628 emit_opcode( cbuf, 0xE0 );
2629 // sahf
2630 emit_opcode( cbuf, 0x9E );
2631 // jnp ::skip
2632 emit_opcode( cbuf, 0x7B );
2633 emit_opcode( cbuf, 0x05 );
2634 %}
2635
2636 enc_class emitModDPR() %{
2637 // fprem must be iterative
2638 // :: loop
2639 // fprem
2640 emit_opcode( cbuf, 0xD9 );
2641 emit_opcode( cbuf, 0xF8 );
2642 // wait
2643 emit_opcode( cbuf, 0x9b );
2644 // fnstsw ax
2645 emit_opcode( cbuf, 0xDF );
2646 emit_opcode( cbuf, 0xE0 );
2647 // sahf
2648 emit_opcode( cbuf, 0x9E );
2649 // jp ::loop
2650 emit_opcode( cbuf, 0x0F );
2651 emit_opcode( cbuf, 0x8A );
2652 emit_opcode( cbuf, 0xF4 );
2653 emit_opcode( cbuf, 0xFF );
2654 emit_opcode( cbuf, 0xFF );
2655 emit_opcode( cbuf, 0xFF );
2656 %}
2657
2658 enc_class fpu_flags() %{
2659 // fnstsw_ax
2660 emit_opcode( cbuf, 0xDF);
2661 emit_opcode( cbuf, 0xE0);
2662 // test ax,0x0400
2663 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2664 emit_opcode( cbuf, 0xA9 );
2665 emit_d16 ( cbuf, 0x0400 );
2666 // // // This sequence works, but stalls for 12-16 cycles on PPro
2667 // // test rax,0x0400
2668 // emit_opcode( cbuf, 0xA9 );
2669 // emit_d32 ( cbuf, 0x00000400 );
2670 //
2671 // jz exit (no unordered comparison)
2672 emit_opcode( cbuf, 0x74 );
2673 emit_d8 ( cbuf, 0x02 );
2674 // mov ah,1 - treat as LT case (set carry flag)
2675 emit_opcode( cbuf, 0xB4 );
2676 emit_d8 ( cbuf, 0x01 );
2677 // sahf
2678 emit_opcode( cbuf, 0x9E);
2679 %}
2680
2681 enc_class cmpF_P6_fixup() %{
2682 // Fixup the integer flags in case comparison involved a NaN
2683 //
2684 // JNP exit (no unordered comparison, P-flag is set by NaN)
2685 emit_opcode( cbuf, 0x7B );
2686 emit_d8 ( cbuf, 0x03 );
2687 // MOV AH,1 - treat as LT case (set carry flag)
2688 emit_opcode( cbuf, 0xB4 );
2689 emit_d8 ( cbuf, 0x01 );
2690 // SAHF
2691 emit_opcode( cbuf, 0x9E);
2692 // NOP // target for branch to avoid branch to branch
2693 emit_opcode( cbuf, 0x90);
2694 %}
2695
2696 // fnstsw_ax();
2697 // sahf();
2698 // movl(dst, nan_result);
2699 // jcc(Assembler::parity, exit);
2700 // movl(dst, less_result);
2701 // jcc(Assembler::below, exit);
2702 // movl(dst, equal_result);
2703 // jcc(Assembler::equal, exit);
2704 // movl(dst, greater_result);
2705
2706 // less_result = 1;
2707 // greater_result = -1;
2708 // equal_result = 0;
2709 // nan_result = -1;
2710
2711 enc_class CmpF_Result(eRegI dst) %{
2712 // fnstsw_ax();
2713 emit_opcode( cbuf, 0xDF);
2714 emit_opcode( cbuf, 0xE0);
2715 // sahf
2716 emit_opcode( cbuf, 0x9E);
2717 // movl(dst, nan_result);
2718 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2719 emit_d32( cbuf, -1 );
2720 // jcc(Assembler::parity, exit);
2721 emit_opcode( cbuf, 0x7A );
2722 emit_d8 ( cbuf, 0x13 );
2723 // movl(dst, less_result);
2724 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2725 emit_d32( cbuf, -1 );
2726 // jcc(Assembler::below, exit);
2727 emit_opcode( cbuf, 0x72 );
2728 emit_d8 ( cbuf, 0x0C );
2729 // movl(dst, equal_result);
2730 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2731 emit_d32( cbuf, 0 );
2732 // jcc(Assembler::equal, exit);
2733 emit_opcode( cbuf, 0x74 );
2734 emit_d8 ( cbuf, 0x05 );
2735 // movl(dst, greater_result);
2736 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2737 emit_d32( cbuf, 1 );
2738 %}
2739
2740
2741 // Compare the longs and set flags
2742 // BROKEN! Do Not use as-is
2743 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2744 // CMP $src1.hi,$src2.hi
2745 emit_opcode( cbuf, 0x3B );
2746 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2747 // JNE,s done
2748 emit_opcode(cbuf,0x75);
2749 emit_d8(cbuf, 2 );
2750 // CMP $src1.lo,$src2.lo
2751 emit_opcode( cbuf, 0x3B );
2752 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2753 // done:
2754 %}
2755
2756 enc_class convert_int_long( regL dst, eRegI src ) %{
2757 // mov $dst.lo,$src
2758 int dst_encoding = $dst$$reg;
2759 int src_encoding = $src$$reg;
2760 encode_Copy( cbuf, dst_encoding , src_encoding );
2761 // mov $dst.hi,$src
2762 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2763 // sar $dst.hi,31
2764 emit_opcode( cbuf, 0xC1 );
2765 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2766 emit_d8(cbuf, 0x1F );
2767 %}
2768
2769 enc_class convert_long_double( eRegL src ) %{
2770 // push $src.hi
2771 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2772 // push $src.lo
2773 emit_opcode(cbuf, 0x50+$src$$reg );
2774 // fild 64-bits at [SP]
2775 emit_opcode(cbuf,0xdf);
2776 emit_d8(cbuf, 0x6C);
2777 emit_d8(cbuf, 0x24);
2778 emit_d8(cbuf, 0x00);
2779 // pop stack
2780 emit_opcode(cbuf, 0x83); // add SP, #8
2781 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2782 emit_d8(cbuf, 0x8);
2783 %}
2784
2785 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2786 // IMUL EDX:EAX,$src1
2787 emit_opcode( cbuf, 0xF7 );
2788 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2789 // SAR EDX,$cnt-32
2790 int shift_count = ((int)$cnt$$constant) - 32;
2791 if (shift_count > 0) {
2792 emit_opcode(cbuf, 0xC1);
2793 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2794 emit_d8(cbuf, shift_count);
2795 }
2796 %}
2797
2798 // this version doesn't have add sp, 8
2799 enc_class convert_long_double2( eRegL src ) %{
2800 // push $src.hi
2801 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2802 // push $src.lo
2803 emit_opcode(cbuf, 0x50+$src$$reg );
2804 // fild 64-bits at [SP]
2805 emit_opcode(cbuf,0xdf);
2806 emit_d8(cbuf, 0x6C);
2807 emit_d8(cbuf, 0x24);
2808 emit_d8(cbuf, 0x00);
2809 %}
2810
2811 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2812 // Basic idea: long = (long)int * (long)int
2813 // IMUL EDX:EAX, src
2814 emit_opcode( cbuf, 0xF7 );
2815 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2816 %}
2817
2818 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2819 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2820 // MUL EDX:EAX, src
2821 emit_opcode( cbuf, 0xF7 );
2822 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2823 %}
2824
2825 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2826 // Basic idea: lo(result) = lo(x_lo * y_lo)
2827 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2828 // MOV $tmp,$src.lo
2829 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2830 // IMUL $tmp,EDX
2831 emit_opcode( cbuf, 0x0F );
2832 emit_opcode( cbuf, 0xAF );
2833 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2834 // MOV EDX,$src.hi
2835 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2836 // IMUL EDX,EAX
2837 emit_opcode( cbuf, 0x0F );
2838 emit_opcode( cbuf, 0xAF );
2839 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2840 // ADD $tmp,EDX
2841 emit_opcode( cbuf, 0x03 );
2842 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2843 // MUL EDX:EAX,$src.lo
2844 emit_opcode( cbuf, 0xF7 );
2845 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2846 // ADD EDX,ESI
2847 emit_opcode( cbuf, 0x03 );
2848 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2849 %}
2850
2851 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
2852 // Basic idea: lo(result) = lo(src * y_lo)
2853 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2854 // IMUL $tmp,EDX,$src
2855 emit_opcode( cbuf, 0x6B );
2856 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2857 emit_d8( cbuf, (int)$src$$constant );
2858 // MOV EDX,$src
2859 emit_opcode(cbuf, 0xB8 + EDX_enc);
2860 emit_d32( cbuf, (int)$src$$constant );
2861 // MUL EDX:EAX,EDX
2862 emit_opcode( cbuf, 0xF7 );
2863 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2864 // ADD EDX,ESI
2865 emit_opcode( cbuf, 0x03 );
2866 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2867 %}
2868
2869 enc_class long_div( eRegL src1, eRegL src2 ) %{
2870 // PUSH src1.hi
2871 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2872 // PUSH src1.lo
2873 emit_opcode(cbuf, 0x50+$src1$$reg );
2874 // PUSH src2.hi
2875 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2876 // PUSH src2.lo
2877 emit_opcode(cbuf, 0x50+$src2$$reg );
2878 // CALL directly to the runtime
2879 cbuf.set_insts_mark();
2880 emit_opcode(cbuf,0xE8); // Call into runtime
2881 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2882 // Restore stack
2883 emit_opcode(cbuf, 0x83); // add SP, #framesize
2884 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2885 emit_d8(cbuf, 4*4);
2886 %}
2887
2888 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2889 // PUSH src1.hi
2890 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2891 // PUSH src1.lo
2892 emit_opcode(cbuf, 0x50+$src1$$reg );
2893 // PUSH src2.hi
2894 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2895 // PUSH src2.lo
2896 emit_opcode(cbuf, 0x50+$src2$$reg );
2897 // CALL directly to the runtime
2898 cbuf.set_insts_mark();
2899 emit_opcode(cbuf,0xE8); // Call into runtime
2900 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2901 // Restore stack
2902 emit_opcode(cbuf, 0x83); // add SP, #framesize
2903 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2904 emit_d8(cbuf, 4*4);
2905 %}
2906
2907 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
2908 // MOV $tmp,$src.lo
2909 emit_opcode(cbuf, 0x8B);
2910 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2911 // OR $tmp,$src.hi
2912 emit_opcode(cbuf, 0x0B);
2913 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2914 %}
2915
2916 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2917 // CMP $src1.lo,$src2.lo
2918 emit_opcode( cbuf, 0x3B );
2919 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2920 // JNE,s skip
2921 emit_cc(cbuf, 0x70, 0x5);
2922 emit_d8(cbuf,2);
2923 // CMP $src1.hi,$src2.hi
2924 emit_opcode( cbuf, 0x3B );
2925 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2926 %}
2927
2928 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
2929 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2930 emit_opcode( cbuf, 0x3B );
2931 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2932 // MOV $tmp,$src1.hi
2933 emit_opcode( cbuf, 0x8B );
2934 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2935 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2936 emit_opcode( cbuf, 0x1B );
2937 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2938 %}
2939
2940 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
2941 // XOR $tmp,$tmp
2942 emit_opcode(cbuf,0x33); // XOR
2943 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2944 // CMP $tmp,$src.lo
2945 emit_opcode( cbuf, 0x3B );
2946 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2947 // SBB $tmp,$src.hi
2948 emit_opcode( cbuf, 0x1B );
2949 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2950 %}
2951
2952 // Sniff, sniff... smells like Gnu Superoptimizer
2953 enc_class neg_long( eRegL dst ) %{
2954 emit_opcode(cbuf,0xF7); // NEG hi
2955 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2956 emit_opcode(cbuf,0xF7); // NEG lo
2957 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2958 emit_opcode(cbuf,0x83); // SBB hi,0
2959 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2960 emit_d8 (cbuf,0 );
2961 %}
2962
2963
2964 // Because the transitions from emitted code to the runtime
2965 // monitorenter/exit helper stubs are so slow it's critical that
2966 // we inline both the stack-locking fast-path and the inflated fast path.
2967 //
2968 // See also: cmpFastLock and cmpFastUnlock.
2969 //
2970 // What follows is a specialized inline transliteration of the code
2971 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2972 // another option would be to emit TrySlowEnter and TrySlowExit methods
2973 // at startup-time. These methods would accept arguments as
2974 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2975 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2976 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2977 // In practice, however, the # of lock sites is bounded and is usually small.
2978 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2979 // if the processor uses simple bimodal branch predictors keyed by EIP
2980 // Since the helper routines would be called from multiple synchronization
2981 // sites.
2982 //
2983 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2984 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2985 // to those specialized methods. That'd give us a mostly platform-independent
2986 // implementation that the JITs could optimize and inline at their pleasure.
2987 // Done correctly, the only time we'd need to cross to native could would be
2988 // to park() or unpark() threads. We'd also need a few more unsafe operators
2989 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2990 // (b) explicit barriers or fence operations.
2991 //
2992 // TODO:
2993 //
2994 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2995 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2996 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2997 // the lock operators would typically be faster than reifying Self.
2998 //
2999 // * Ideally I'd define the primitives as:
3000 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3001 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3002 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3003 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3004 // Furthermore the register assignments are overconstrained, possibly resulting in
3005 // sub-optimal code near the synchronization site.
3006 //
3007 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3008 // Alternately, use a better sp-proximity test.
3009 //
3010 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3011 // Either one is sufficient to uniquely identify a thread.
3012 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3013 //
3014 // * Intrinsify notify() and notifyAll() for the common cases where the
3015 // object is locked by the calling thread but the waitlist is empty.
3016 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3017 //
3018 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3019 // But beware of excessive branch density on AMD Opterons.
3020 //
3021 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3022 // or failure of the fast-path. If the fast-path fails then we pass
3023 // control to the slow-path, typically in C. In Fast_Lock and
3024 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3025 // will emit a conditional branch immediately after the node.
3026 // So we have branches to branches and lots of ICC.ZF games.
3027 // Instead, it might be better to have C2 pass a "FailureLabel"
3028 // into Fast_Lock and Fast_Unlock. In the case of success, control
3029 // will drop through the node. ICC.ZF is undefined at exit.
3030 // In the case of failure, the node will branch directly to the
3031 // FailureLabel
3032
3033
3034 // obj: object to lock
3035 // box: on-stack box address (displaced header location) - KILLED
3036 // rax,: tmp -- KILLED
3037 // scr: tmp -- KILLED
3038 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3039
3040 Register objReg = as_Register($obj$$reg);
3041 Register boxReg = as_Register($box$$reg);
3042 Register tmpReg = as_Register($tmp$$reg);
3043 Register scrReg = as_Register($scr$$reg);
3044
3045 // Ensure the register assignents are disjoint
3046 guarantee (objReg != boxReg, "") ;
3047 guarantee (objReg != tmpReg, "") ;
3048 guarantee (objReg != scrReg, "") ;
3049 guarantee (boxReg != tmpReg, "") ;
3050 guarantee (boxReg != scrReg, "") ;
3051 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3052
3053 MacroAssembler masm(&cbuf);
3054
3055 if (_counters != NULL) {
3056 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3057 }
3058 if (EmitSync & 1) {
3059 // set box->dhw = unused_mark (3)
3060 // Force all sync thru slow-path: slow_enter() and slow_exit()
3061 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3062 masm.cmpptr (rsp, (int32_t)0) ;
3063 } else
3064 if (EmitSync & 2) {
3065 Label DONE_LABEL ;
3066 if (UseBiasedLocking) {
3067 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3068 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3069 }
3070
3071 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3072 masm.orptr (tmpReg, 0x1);
3073 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3074 if (os::is_MP()) { masm.lock(); }
3075 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3076 masm.jcc(Assembler::equal, DONE_LABEL);
3077 // Recursive locking
3078 masm.subptr(tmpReg, rsp);
3079 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3080 masm.movptr(Address(boxReg, 0), tmpReg);
3081 masm.bind(DONE_LABEL) ;
3082 } else {
3083 // Possible cases that we'll encounter in fast_lock
3084 // ------------------------------------------------
3085 // * Inflated
3086 // -- unlocked
3087 // -- Locked
3088 // = by self
3089 // = by other
3090 // * biased
3091 // -- by Self
3092 // -- by other
3093 // * neutral
3094 // * stack-locked
3095 // -- by self
3096 // = sp-proximity test hits
3097 // = sp-proximity test generates false-negative
3098 // -- by other
3099 //
3100
3101 Label IsInflated, DONE_LABEL, PopDone ;
3102
3103 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3104 // order to reduce the number of conditional branches in the most common cases.
3105 // Beware -- there's a subtle invariant that fetch of the markword
3106 // at [FETCH], below, will never observe a biased encoding (*101b).
3107 // If this invariant is not held we risk exclusion (safety) failure.
3108 if (UseBiasedLocking && !UseOptoBiasInlining) {
3109 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3110 }
3111
3112 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3113 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3114 masm.jccb (Assembler::notZero, IsInflated) ;
3115
3116 // Attempt stack-locking ...
3117 masm.orptr (tmpReg, 0x1);
3118 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3119 if (os::is_MP()) { masm.lock(); }
3120 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3121 if (_counters != NULL) {
3122 masm.cond_inc32(Assembler::equal,
3123 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3124 }
3125 masm.jccb (Assembler::equal, DONE_LABEL);
3126
3127 // Recursive locking
3128 masm.subptr(tmpReg, rsp);
3129 masm.andptr(tmpReg, 0xFFFFF003 );
3130 masm.movptr(Address(boxReg, 0), tmpReg);
3131 if (_counters != NULL) {
3132 masm.cond_inc32(Assembler::equal,
3133 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3134 }
3135 masm.jmp (DONE_LABEL) ;
3136
3137 masm.bind (IsInflated) ;
3138
3139 // The object is inflated.
3140 //
3141 // TODO-FIXME: eliminate the ugly use of manifest constants:
3142 // Use markOopDesc::monitor_value instead of "2".
3143 // use markOop::unused_mark() instead of "3".
3144 // The tmpReg value is an objectMonitor reference ORed with
3145 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3146 // objectmonitor pointer by masking off the "2" bit or we can just
3147 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3148 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3149 //
3150 // I use the latter as it avoids AGI stalls.
3151 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3152 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3153 //
3154 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3155
3156 // boxReg refers to the on-stack BasicLock in the current frame.
3157 // We'd like to write:
3158 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3159 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3160 // additional latency as we have another ST in the store buffer that must drain.
3161
3162 if (EmitSync & 8192) {
3163 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3164 masm.get_thread (scrReg) ;
3165 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3166 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3167 if (os::is_MP()) { masm.lock(); }
3168 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3169 } else
3170 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3171 masm.movptr(scrReg, boxReg) ;
3172 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3173
3174 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3175 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3176 // prefetchw [eax + Offset(_owner)-2]
3177 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3178 }
3179
3180 if ((EmitSync & 64) == 0) {
3181 // Optimistic form: consider XORL tmpReg,tmpReg
3182 masm.movptr(tmpReg, NULL_WORD) ;
3183 } else {
3184 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3185 // Test-And-CAS instead of CAS
3186 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3187 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3188 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3189 }
3190
3191 // Appears unlocked - try to swing _owner from null to non-null.
3192 // Ideally, I'd manifest "Self" with get_thread and then attempt
3193 // to CAS the register containing Self into m->Owner.
3194 // But we don't have enough registers, so instead we can either try to CAS
3195 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3196 // we later store "Self" into m->Owner. Transiently storing a stack address
3197 // (rsp or the address of the box) into m->owner is harmless.
3198 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3199 if (os::is_MP()) { masm.lock(); }
3200 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3201 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3202 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3203 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3204 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3205 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3206
3207 // If the CAS fails we can either retry or pass control to the slow-path.
3208 // We use the latter tactic.
3209 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3210 // If the CAS was successful ...
3211 // Self has acquired the lock
3212 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3213 // Intentional fall-through into DONE_LABEL ...
3214 } else {
3215 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3216 masm.movptr(boxReg, tmpReg) ;
3217
3218 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3219 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3220 // prefetchw [eax + Offset(_owner)-2]
3221 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3222 }
3223
3224 if ((EmitSync & 64) == 0) {
3225 // Optimistic form
3226 masm.xorptr (tmpReg, tmpReg) ;
3227 } else {
3228 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3229 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3230 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3231 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3232 }
3233
3234 // Appears unlocked - try to swing _owner from null to non-null.
3235 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3236 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3237 masm.get_thread (scrReg) ;
3238 if (os::is_MP()) { masm.lock(); }
3239 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3240
3241 // If the CAS fails we can either retry or pass control to the slow-path.
3242 // We use the latter tactic.
3243 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3244 // If the CAS was successful ...
3245 // Self has acquired the lock
3246 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3247 // Intentional fall-through into DONE_LABEL ...
3248 }
3249
3250 // DONE_LABEL is a hot target - we'd really like to place it at the
3251 // start of cache line by padding with NOPs.
3252 // See the AMD and Intel software optimization manuals for the
3253 // most efficient "long" NOP encodings.
3254 // Unfortunately none of our alignment mechanisms suffice.
3255 masm.bind(DONE_LABEL);
3256
3257 // Avoid branch-to-branch on AMD processors
3258 // This appears to be superstition.
3259 if (EmitSync & 32) masm.nop() ;
3260
3261
3262 // At DONE_LABEL the icc ZFlag is set as follows ...
3263 // Fast_Unlock uses the same protocol.
3264 // ZFlag == 1 -> Success
3265 // ZFlag == 0 -> Failure - force control through the slow-path
3266 }
3267 %}
3268
3269 // obj: object to unlock
3270 // box: box address (displaced header location), killed. Must be EAX.
3271 // rbx,: killed tmp; cannot be obj nor box.
3272 //
3273 // Some commentary on balanced locking:
3274 //
3275 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3276 // Methods that don't have provably balanced locking are forced to run in the
3277 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3278 // The interpreter provides two properties:
3279 // I1: At return-time the interpreter automatically and quietly unlocks any
3280 // objects acquired the current activation (frame). Recall that the
3281 // interpreter maintains an on-stack list of locks currently held by
3282 // a frame.
3283 // I2: If a method attempts to unlock an object that is not held by the
3284 // the frame the interpreter throws IMSX.
3285 //
3286 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3287 // B() doesn't have provably balanced locking so it runs in the interpreter.
3288 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3289 // is still locked by A().
3290 //
3291 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3292 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3293 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3294 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3295
3296 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3297
3298 Register objReg = as_Register($obj$$reg);
3299 Register boxReg = as_Register($box$$reg);
3300 Register tmpReg = as_Register($tmp$$reg);
3301
3302 guarantee (objReg != boxReg, "") ;
3303 guarantee (objReg != tmpReg, "") ;
3304 guarantee (boxReg != tmpReg, "") ;
3305 guarantee (boxReg == as_Register(EAX_enc), "") ;
3306 MacroAssembler masm(&cbuf);
3307
3308 if (EmitSync & 4) {
3309 // Disable - inhibit all inlining. Force control through the slow-path
3310 masm.cmpptr (rsp, 0) ;
3311 } else
3312 if (EmitSync & 8) {
3313 Label DONE_LABEL ;
3314 if (UseBiasedLocking) {
3315 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3316 }
3317 // classic stack-locking code ...
3318 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3319 masm.testptr(tmpReg, tmpReg) ;
3320 masm.jcc (Assembler::zero, DONE_LABEL) ;
3321 if (os::is_MP()) { masm.lock(); }
3322 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3323 masm.bind(DONE_LABEL);
3324 } else {
3325 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3326
3327 // Critically, the biased locking test must have precedence over
3328 // and appear before the (box->dhw == 0) recursive stack-lock test.
3329 if (UseBiasedLocking && !UseOptoBiasInlining) {
3330 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3331 }
3332
3333 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3334 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3335 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3336
3337 masm.testptr(tmpReg, 0x02) ; // Inflated?
3338 masm.jccb (Assembler::zero, Stacked) ;
3339
3340 masm.bind (Inflated) ;
3341 // It's inflated.
3342 // Despite our balanced locking property we still check that m->_owner == Self
3343 // as java routines or native JNI code called by this thread might
3344 // have released the lock.
3345 // Refer to the comments in synchronizer.cpp for how we might encode extra
3346 // state in _succ so we can avoid fetching EntryList|cxq.
3347 //
3348 // I'd like to add more cases in fast_lock() and fast_unlock() --
3349 // such as recursive enter and exit -- but we have to be wary of
3350 // I$ bloat, T$ effects and BP$ effects.
3351 //
3352 // If there's no contention try a 1-0 exit. That is, exit without
3353 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3354 // we detect and recover from the race that the 1-0 exit admits.
3355 //
3356 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3357 // before it STs null into _owner, releasing the lock. Updates
3358 // to data protected by the critical section must be visible before
3359 // we drop the lock (and thus before any other thread could acquire
3360 // the lock and observe the fields protected by the lock).
3361 // IA32's memory-model is SPO, so STs are ordered with respect to
3362 // each other and there's no need for an explicit barrier (fence).
3363 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3364
3365 masm.get_thread (boxReg) ;
3366 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3367 // prefetchw [ebx + Offset(_owner)-2]
3368 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3369 }
3370
3371 // Note that we could employ various encoding schemes to reduce
3372 // the number of loads below (currently 4) to just 2 or 3.
3373 // Refer to the comments in synchronizer.cpp.
3374 // In practice the chain of fetches doesn't seem to impact performance, however.
3375 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3376 // Attempt to reduce branch density - AMD's branch predictor.
3377 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3378 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3379 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3380 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3381 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3382 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3383 masm.jmpb (DONE_LABEL) ;
3384 } else {
3385 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3386 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3387 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3388 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3389 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3390 masm.jccb (Assembler::notZero, CheckSucc) ;
3391 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3392 masm.jmpb (DONE_LABEL) ;
3393 }
3394
3395 // The Following code fragment (EmitSync & 65536) improves the performance of
3396 // contended applications and contended synchronization microbenchmarks.
3397 // Unfortunately the emission of the code - even though not executed - causes regressions
3398 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3399 // with an equal number of never-executed NOPs results in the same regression.
3400 // We leave it off by default.
3401
3402 if ((EmitSync & 65536) != 0) {
3403 Label LSuccess, LGoSlowPath ;
3404
3405 masm.bind (CheckSucc) ;
3406
3407 // Optional pre-test ... it's safe to elide this
3408 if ((EmitSync & 16) == 0) {
3409 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3410 masm.jccb (Assembler::zero, LGoSlowPath) ;
3411 }
3412
3413 // We have a classic Dekker-style idiom:
3414 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3415 // There are a number of ways to implement the barrier:
3416 // (1) lock:andl &m->_owner, 0
3417 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3418 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3419 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3420 // (2) If supported, an explicit MFENCE is appealing.
3421 // In older IA32 processors MFENCE is slower than lock:add or xchg
3422 // particularly if the write-buffer is full as might be the case if
3423 // if stores closely precede the fence or fence-equivalent instruction.
3424 // In more modern implementations MFENCE appears faster, however.
3425 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3426 // The $lines underlying the top-of-stack should be in M-state.
3427 // The locked add instruction is serializing, of course.
3428 // (4) Use xchg, which is serializing
3429 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3430 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3431 // The integer condition codes will tell us if succ was 0.
3432 // Since _succ and _owner should reside in the same $line and
3433 // we just stored into _owner, it's likely that the $line
3434 // remains in M-state for the lock:orl.
3435 //
3436 // We currently use (3), although it's likely that switching to (2)
3437 // is correct for the future.
3438
3439 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3440 if (os::is_MP()) {
3441 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3442 masm.mfence();
3443 } else {
3444 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3445 }
3446 }
3447 // Ratify _succ remains non-null
3448 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3449 masm.jccb (Assembler::notZero, LSuccess) ;
3450
3451 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3452 if (os::is_MP()) { masm.lock(); }
3453 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3454 masm.jccb (Assembler::notEqual, LSuccess) ;
3455 // Since we're low on registers we installed rsp as a placeholding in _owner.
3456 // Now install Self over rsp. This is safe as we're transitioning from
3457 // non-null to non=null
3458 masm.get_thread (boxReg) ;
3459 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3460 // Intentional fall-through into LGoSlowPath ...
3461
3462 masm.bind (LGoSlowPath) ;
3463 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3464 masm.jmpb (DONE_LABEL) ;
3465
3466 masm.bind (LSuccess) ;
3467 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3468 masm.jmpb (DONE_LABEL) ;
3469 }
3470
3471 masm.bind (Stacked) ;
3472 // It's not inflated and it's not recursively stack-locked and it's not biased.
3473 // It must be stack-locked.
3474 // Try to reset the header to displaced header.
3475 // The "box" value on the stack is stable, so we can reload
3476 // and be assured we observe the same value as above.
3477 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3478 if (os::is_MP()) { masm.lock(); }
3479 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3480 // Intention fall-thru into DONE_LABEL
3481
3482
3483 // DONE_LABEL is a hot target - we'd really like to place it at the
3484 // start of cache line by padding with NOPs.
3485 // See the AMD and Intel software optimization manuals for the
3486 // most efficient "long" NOP encodings.
3487 // Unfortunately none of our alignment mechanisms suffice.
3488 if ((EmitSync & 65536) == 0) {
3489 masm.bind (CheckSucc) ;
3490 }
3491 masm.bind(DONE_LABEL);
3492
3493 // Avoid branch to branch on AMD processors
3494 if (EmitSync & 32768) { masm.nop() ; }
3495 }
3496 %}
3497
3498
3499 enc_class enc_pop_rdx() %{
3500 emit_opcode(cbuf,0x5A);
3501 %}
3502
3503 enc_class enc_rethrow() %{
3504 cbuf.set_insts_mark();
3505 emit_opcode(cbuf, 0xE9); // jmp entry
3506 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3507 runtime_call_Relocation::spec(), RELOC_IMM32 );
3508 %}
3509
3510
3511 // Convert a double to an int. Java semantics require we do complex
3512 // manglelations in the corner cases. So we set the rounding mode to
3513 // 'zero', store the darned double down as an int, and reset the
3514 // rounding mode to 'nearest'. The hardware throws an exception which
3515 // patches up the correct value directly to the stack.
3516 enc_class DPR2I_encoding( regDPR src ) %{
3517 // Flip to round-to-zero mode. We attempted to allow invalid-op
3518 // exceptions here, so that a NAN or other corner-case value will
3519 // thrown an exception (but normal values get converted at full speed).
3520 // However, I2C adapters and other float-stack manglers leave pending
3521 // invalid-op exceptions hanging. We would have to clear them before
3522 // enabling them and that is more expensive than just testing for the
3523 // invalid value Intel stores down in the corner cases.
3524 emit_opcode(cbuf,0xD9); // FLDCW trunc
3525 emit_opcode(cbuf,0x2D);
3526 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3527 // Allocate a word
3528 emit_opcode(cbuf,0x83); // SUB ESP,4
3529 emit_opcode(cbuf,0xEC);
3530 emit_d8(cbuf,0x04);
3531 // Encoding assumes a double has been pushed into FPR0.
3532 // Store down the double as an int, popping the FPU stack
3533 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3534 emit_opcode(cbuf,0x1C);
3535 emit_d8(cbuf,0x24);
3536 // Restore the rounding mode; mask the exception
3537 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3538 emit_opcode(cbuf,0x2D);
3539 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3540 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3541 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3542
3543 // Load the converted int; adjust CPU stack
3544 emit_opcode(cbuf,0x58); // POP EAX
3545 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3546 emit_d32 (cbuf,0x80000000); // 0x80000000
3547 emit_opcode(cbuf,0x75); // JNE around_slow_call
3548 emit_d8 (cbuf,0x07); // Size of slow_call
3549 // Push src onto stack slow-path
3550 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3551 emit_d8 (cbuf,0xC0-1+$src$$reg );
3552 // CALL directly to the runtime
3553 cbuf.set_insts_mark();
3554 emit_opcode(cbuf,0xE8); // Call into runtime
3555 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3556 // Carry on here...
3557 %}
3558
3559 enc_class DPR2L_encoding( regDPR src ) %{
3560 emit_opcode(cbuf,0xD9); // FLDCW trunc
3561 emit_opcode(cbuf,0x2D);
3562 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3563 // Allocate a word
3564 emit_opcode(cbuf,0x83); // SUB ESP,8
3565 emit_opcode(cbuf,0xEC);
3566 emit_d8(cbuf,0x08);
3567 // Encoding assumes a double has been pushed into FPR0.
3568 // Store down the double as a long, popping the FPU stack
3569 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3570 emit_opcode(cbuf,0x3C);
3571 emit_d8(cbuf,0x24);
3572 // Restore the rounding mode; mask the exception
3573 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3574 emit_opcode(cbuf,0x2D);
3575 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3576 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3577 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3578
3579 // Load the converted int; adjust CPU stack
3580 emit_opcode(cbuf,0x58); // POP EAX
3581 emit_opcode(cbuf,0x5A); // POP EDX
3582 emit_opcode(cbuf,0x81); // CMP EDX,imm
3583 emit_d8 (cbuf,0xFA); // rdx
3584 emit_d32 (cbuf,0x80000000); // 0x80000000
3585 emit_opcode(cbuf,0x75); // JNE around_slow_call
3586 emit_d8 (cbuf,0x07+4); // Size of slow_call
3587 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3588 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3589 emit_opcode(cbuf,0x75); // JNE around_slow_call
3590 emit_d8 (cbuf,0x07); // Size of slow_call
3591 // Push src onto stack slow-path
3592 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3593 emit_d8 (cbuf,0xC0-1+$src$$reg );
3594 // CALL directly to the runtime
3595 cbuf.set_insts_mark();
3596 emit_opcode(cbuf,0xE8); // Call into runtime
3597 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3598 // Carry on here...
3599 %}
3600
3601 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3602 // Operand was loaded from memory into fp ST (stack top)
3603 // FMUL ST,$src /* D8 C8+i */
3604 emit_opcode(cbuf, 0xD8);
3605 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3606 %}
3607
3608 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3609 // FADDP ST,src2 /* D8 C0+i */
3610 emit_opcode(cbuf, 0xD8);
3611 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3612 //could use FADDP src2,fpST /* DE C0+i */
3613 %}
3614
3615 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3616 // FADDP src2,ST /* DE C0+i */
3617 emit_opcode(cbuf, 0xDE);
3618 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3619 %}
3620
3621 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3622 // Operand has been loaded into fp ST (stack top)
3623 // FSUB ST,$src1
3624 emit_opcode(cbuf, 0xD8);
3625 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3626
3627 // FDIV
3628 emit_opcode(cbuf, 0xD8);
3629 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3630 %}
3631
3632 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3633 // Operand was loaded from memory into fp ST (stack top)
3634 // FADD ST,$src /* D8 C0+i */
3635 emit_opcode(cbuf, 0xD8);
3636 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3637
3638 // FMUL ST,src2 /* D8 C*+i */
3639 emit_opcode(cbuf, 0xD8);
3640 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3641 %}
3642
3643
3644 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3645 // Operand was loaded from memory into fp ST (stack top)
3646 // FADD ST,$src /* D8 C0+i */
3647 emit_opcode(cbuf, 0xD8);
3648 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3649
3650 // FMULP src2,ST /* DE C8+i */
3651 emit_opcode(cbuf, 0xDE);
3652 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3653 %}
3654
3655 // Atomically load the volatile long
3656 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3657 emit_opcode(cbuf,0xDF);
3658 int rm_byte_opcode = 0x05;
3659 int base = $mem$$base;
3660 int index = $mem$$index;
3661 int scale = $mem$$scale;
3662 int displace = $mem$$disp;
3663 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3664 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3665 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3666 %}
3667
3668 // Volatile Store Long. Must be atomic, so move it into
3669 // the FP TOS and then do a 64-bit FIST. Has to probe the
3670 // target address before the store (for null-ptr checks)
3671 // so the memory operand is used twice in the encoding.
3672 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3673 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3674 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3675 emit_opcode(cbuf,0xDF);
3676 int rm_byte_opcode = 0x07;
3677 int base = $mem$$base;
3678 int index = $mem$$index;
3679 int scale = $mem$$scale;
3680 int displace = $mem$$disp;
3681 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3682 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3683 %}
3684
3685 // Safepoint Poll. This polls the safepoint page, and causes an
3686 // exception if it is not readable. Unfortunately, it kills the condition code
3687 // in the process
3688 // We current use TESTL [spp],EDI
3689 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3690
3691 enc_class Safepoint_Poll() %{
3692 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3693 emit_opcode(cbuf,0x85);
3694 emit_rm (cbuf, 0x0, 0x7, 0x5);
3695 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3696 %}
3697 %}
3698
3699
3700 //----------FRAME--------------------------------------------------------------
3701 // Definition of frame structure and management information.
3702 //
3703 // S T A C K L A Y O U T Allocators stack-slot number
3704 // | (to get allocators register number
3705 // G Owned by | | v add OptoReg::stack0())
3706 // r CALLER | |
3707 // o | +--------+ pad to even-align allocators stack-slot
3708 // w V | pad0 | numbers; owned by CALLER
3709 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3710 // h ^ | in | 5
3711 // | | args | 4 Holes in incoming args owned by SELF
3712 // | | | | 3
3713 // | | +--------+
3714 // V | | old out| Empty on Intel, window on Sparc
3715 // | old |preserve| Must be even aligned.
3716 // | SP-+--------+----> Matcher::_old_SP, even aligned
3717 // | | in | 3 area for Intel ret address
3718 // Owned by |preserve| Empty on Sparc.
3719 // SELF +--------+
3720 // | | pad2 | 2 pad to align old SP
3721 // | +--------+ 1
3722 // | | locks | 0
3723 // | +--------+----> OptoReg::stack0(), even aligned
3724 // | | pad1 | 11 pad to align new SP
3725 // | +--------+
3726 // | | | 10
3727 // | | spills | 9 spills
3728 // V | | 8 (pad0 slot for callee)
3729 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3730 // ^ | out | 7
3731 // | | args | 6 Holes in outgoing args owned by CALLEE
3732 // Owned by +--------+
3733 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3734 // | new |preserve| Must be even-aligned.
3735 // | SP-+--------+----> Matcher::_new_SP, even aligned
3736 // | | |
3737 //
3738 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3739 // known from SELF's arguments and the Java calling convention.
3740 // Region 6-7 is determined per call site.
3741 // Note 2: If the calling convention leaves holes in the incoming argument
3742 // area, those holes are owned by SELF. Holes in the outgoing area
3743 // are owned by the CALLEE. Holes should not be nessecary in the
3744 // incoming area, as the Java calling convention is completely under
3745 // the control of the AD file. Doubles can be sorted and packed to
3746 // avoid holes. Holes in the outgoing arguments may be nessecary for
3747 // varargs C calling conventions.
3748 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3749 // even aligned with pad0 as needed.
3750 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3751 // region 6-11 is even aligned; it may be padded out more so that
3752 // the region from SP to FP meets the minimum stack alignment.
3753
3754 frame %{
3755 // What direction does stack grow in (assumed to be same for C & Java)
3756 stack_direction(TOWARDS_LOW);
3757
3758 // These three registers define part of the calling convention
3759 // between compiled code and the interpreter.
3760 inline_cache_reg(EAX); // Inline Cache Register
3761 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3762
3763 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3764 cisc_spilling_operand_name(indOffset32);
3765
3766 // Number of stack slots consumed by locking an object
3767 sync_stack_slots(1);
3768
3769 // Compiled code's Frame Pointer
3770 frame_pointer(ESP);
3771 // Interpreter stores its frame pointer in a register which is
3772 // stored to the stack by I2CAdaptors.
3773 // I2CAdaptors convert from interpreted java to compiled java.
3774 interpreter_frame_pointer(EBP);
3775
3776 // Stack alignment requirement
3777 // Alignment size in bytes (128-bit -> 16 bytes)
3778 stack_alignment(StackAlignmentInBytes);
3779
3780 // Number of stack slots between incoming argument block and the start of
3781 // a new frame. The PROLOG must add this many slots to the stack. The
3782 // EPILOG must remove this many slots. Intel needs one slot for
3783 // return address and one for rbp, (must save rbp)
3784 in_preserve_stack_slots(2+VerifyStackAtCalls);
3785
3786 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3787 // for calls to C. Supports the var-args backing area for register parms.
3788 varargs_C_out_slots_killed(0);
3789
3790 // The after-PROLOG location of the return address. Location of
3791 // return address specifies a type (REG or STACK) and a number
3792 // representing the register number (i.e. - use a register name) or
3793 // stack slot.
3794 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3795 // Otherwise, it is above the locks and verification slot and alignment word
3796 return_addr(STACK - 1 +
3797 round_to(1+VerifyStackAtCalls+
3798 Compile::current()->fixed_slots(),
3799 (StackAlignmentInBytes/wordSize)));
3800
3801 // Body of function which returns an integer array locating
3802 // arguments either in registers or in stack slots. Passed an array
3803 // of ideal registers called "sig" and a "length" count. Stack-slot
3804 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3805 // arguments for a CALLEE. Incoming stack arguments are
3806 // automatically biased by the preserve_stack_slots field above.
3807 calling_convention %{
3808 // No difference between ingoing/outgoing just pass false
3809 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3810 %}
3811
3812
3813 // Body of function which returns an integer array locating
3814 // arguments either in registers or in stack slots. Passed an array
3815 // of ideal registers called "sig" and a "length" count. Stack-slot
3816 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3817 // arguments for a CALLEE. Incoming stack arguments are
3818 // automatically biased by the preserve_stack_slots field above.
3819 c_calling_convention %{
3820 // This is obviously always outgoing
3821 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3822 %}
3823
3824 // Location of C & interpreter return values
3825 c_return_value %{
3826 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3827 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3828 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3829
3830 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3831 // that C functions return float and double results in XMM0.
3832 if( ideal_reg == Op_RegD && UseSSE>=2 )
3833 return OptoRegPair(XMM0b_num,XMM0a_num);
3834 if( ideal_reg == Op_RegF && UseSSE>=2 )
3835 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3836
3837 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3838 %}
3839
3840 // Location of return values
3841 return_value %{
3842 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3843 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3844 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3845 if( ideal_reg == Op_RegD && UseSSE>=2 )
3846 return OptoRegPair(XMM0b_num,XMM0a_num);
3847 if( ideal_reg == Op_RegF && UseSSE>=1 )
3848 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3849 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3850 %}
3851
3852 %}
3853
3854 //----------ATTRIBUTES---------------------------------------------------------
3855 //----------Operand Attributes-------------------------------------------------
3856 op_attrib op_cost(0); // Required cost attribute
3857
3858 //----------Instruction Attributes---------------------------------------------
3859 ins_attrib ins_cost(100); // Required cost attribute
3860 ins_attrib ins_size(8); // Required size attribute (in bits)
3861 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3862 // non-matching short branch variant of some
3863 // long branch?
3864 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3865 // specifies the alignment that some part of the instruction (not
3866 // necessarily the start) requires. If > 1, a compute_padding()
3867 // function must be provided for the instruction
3868
3869 //----------OPERANDS-----------------------------------------------------------
3870 // Operand definitions must precede instruction definitions for correct parsing
3871 // in the ADLC because operands constitute user defined types which are used in
3872 // instruction definitions.
3873
3874 //----------Simple Operands----------------------------------------------------
3875 // Immediate Operands
3876 // Integer Immediate
3877 operand immI() %{
3878 match(ConI);
3879
3880 op_cost(10);
3881 format %{ %}
3882 interface(CONST_INTER);
3883 %}
3884
3885 // Constant for test vs zero
3886 operand immI0() %{
3887 predicate(n->get_int() == 0);
3888 match(ConI);
3889
3890 op_cost(0);
3891 format %{ %}
3892 interface(CONST_INTER);
3893 %}
3894
3895 // Constant for increment
3896 operand immI1() %{
3897 predicate(n->get_int() == 1);
3898 match(ConI);
3899
3900 op_cost(0);
3901 format %{ %}
3902 interface(CONST_INTER);
3903 %}
3904
3905 // Constant for decrement
3906 operand immI_M1() %{
3907 predicate(n->get_int() == -1);
3908 match(ConI);
3909
3910 op_cost(0);
3911 format %{ %}
3912 interface(CONST_INTER);
3913 %}
3914
3915 // Valid scale values for addressing modes
3916 operand immI2() %{
3917 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3918 match(ConI);
3919
3920 format %{ %}
3921 interface(CONST_INTER);
3922 %}
3923
3924 operand immI8() %{
3925 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3926 match(ConI);
3927
3928 op_cost(5);
3929 format %{ %}
3930 interface(CONST_INTER);
3931 %}
3932
3933 operand immI16() %{
3934 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3935 match(ConI);
3936
3937 op_cost(10);
3938 format %{ %}
3939 interface(CONST_INTER);
3940 %}
3941
3942 // Constant for long shifts
3943 operand immI_32() %{
3944 predicate( n->get_int() == 32 );
3945 match(ConI);
3946
3947 op_cost(0);
3948 format %{ %}
3949 interface(CONST_INTER);
3950 %}
3951
3952 operand immI_1_31() %{
3953 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3954 match(ConI);
3955
3956 op_cost(0);
3957 format %{ %}
3958 interface(CONST_INTER);
3959 %}
3960
3961 operand immI_32_63() %{
3962 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3963 match(ConI);
3964 op_cost(0);
3965
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3969
3970 operand immI_1() %{
3971 predicate( n->get_int() == 1 );
3972 match(ConI);
3973
3974 op_cost(0);
3975 format %{ %}
3976 interface(CONST_INTER);
3977 %}
3978
3979 operand immI_2() %{
3980 predicate( n->get_int() == 2 );
3981 match(ConI);
3982
3983 op_cost(0);
3984 format %{ %}
3985 interface(CONST_INTER);
3986 %}
3987
3988 operand immI_3() %{
3989 predicate( n->get_int() == 3 );
3990 match(ConI);
3991
3992 op_cost(0);
3993 format %{ %}
3994 interface(CONST_INTER);
3995 %}
3996
3997 // Pointer Immediate
3998 operand immP() %{
3999 match(ConP);
4000
4001 op_cost(10);
4002 format %{ %}
4003 interface(CONST_INTER);
4004 %}
4005
4006 // NULL Pointer Immediate
4007 operand immP0() %{
4008 predicate( n->get_ptr() == 0 );
4009 match(ConP);
4010 op_cost(0);
4011
4012 format %{ %}
4013 interface(CONST_INTER);
4014 %}
4015
4016 // Long Immediate
4017 operand immL() %{
4018 match(ConL);
4019
4020 op_cost(20);
4021 format %{ %}
4022 interface(CONST_INTER);
4023 %}
4024
4025 // Long Immediate zero
4026 operand immL0() %{
4027 predicate( n->get_long() == 0L );
4028 match(ConL);
4029 op_cost(0);
4030
4031 format %{ %}
4032 interface(CONST_INTER);
4033 %}
4034
4035 // Long Immediate zero
4036 operand immL_M1() %{
4037 predicate( n->get_long() == -1L );
4038 match(ConL);
4039 op_cost(0);
4040
4041 format %{ %}
4042 interface(CONST_INTER);
4043 %}
4044
4045 // Long immediate from 0 to 127.
4046 // Used for a shorter form of long mul by 10.
4047 operand immL_127() %{
4048 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4049 match(ConL);
4050 op_cost(0);
4051
4052 format %{ %}
4053 interface(CONST_INTER);
4054 %}
4055
4056 // Long Immediate: low 32-bit mask
4057 operand immL_32bits() %{
4058 predicate(n->get_long() == 0xFFFFFFFFL);
4059 match(ConL);
4060 op_cost(0);
4061
4062 format %{ %}
4063 interface(CONST_INTER);
4064 %}
4065
4066 // Long Immediate: low 32-bit mask
4067 operand immL32() %{
4068 predicate(n->get_long() == (int)(n->get_long()));
4069 match(ConL);
4070 op_cost(20);
4071
4072 format %{ %}
4073 interface(CONST_INTER);
4074 %}
4075
4076 //Double Immediate zero
4077 operand immDPR0() %{
4078 // Do additional (and counter-intuitive) test against NaN to work around VC++
4079 // bug that generates code such that NaNs compare equal to 0.0
4080 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4081 match(ConD);
4082
4083 op_cost(5);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4087
4088 // Double Immediate one
4089 operand immDPR1() %{
4090 predicate( UseSSE<=1 && n->getd() == 1.0 );
4091 match(ConD);
4092
4093 op_cost(5);
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4097
4098 // Double Immediate
4099 operand immDPR() %{
4100 predicate(UseSSE<=1);
4101 match(ConD);
4102
4103 op_cost(5);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4107
4108 operand immD() %{
4109 predicate(UseSSE>=2);
4110 match(ConD);
4111
4112 op_cost(5);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4116
4117 // Double Immediate zero
4118 operand immD0() %{
4119 // Do additional (and counter-intuitive) test against NaN to work around VC++
4120 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4121 // compare equal to -0.0.
4122 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4123 match(ConD);
4124
4125 format %{ %}
4126 interface(CONST_INTER);
4127 %}
4128
4129 // Float Immediate zero
4130 operand immFPR0() %{
4131 predicate(UseSSE == 0 && n->getf() == 0.0F);
4132 match(ConF);
4133
4134 op_cost(5);
4135 format %{ %}
4136 interface(CONST_INTER);
4137 %}
4138
4139 // Float Immediate one
4140 operand immFPR1() %{
4141 predicate(UseSSE == 0 && n->getf() == 1.0F);
4142 match(ConF);
4143
4144 op_cost(5);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // Float Immediate
4150 operand immFPR() %{
4151 predicate( UseSSE == 0 );
4152 match(ConF);
4153
4154 op_cost(5);
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 // Float Immediate
4160 operand immF() %{
4161 predicate(UseSSE >= 1);
4162 match(ConF);
4163
4164 op_cost(5);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4168
4169 // Float Immediate zero. Zero and not -0.0
4170 operand immF0() %{
4171 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4172 match(ConF);
4173
4174 op_cost(5);
4175 format %{ %}
4176 interface(CONST_INTER);
4177 %}
4178
4179 // Immediates for special shifts (sign extend)
4180
4181 // Constants for increment
4182 operand immI_16() %{
4183 predicate( n->get_int() == 16 );
4184 match(ConI);
4185
4186 format %{ %}
4187 interface(CONST_INTER);
4188 %}
4189
4190 operand immI_24() %{
4191 predicate( n->get_int() == 24 );
4192 match(ConI);
4193
4194 format %{ %}
4195 interface(CONST_INTER);
4196 %}
4197
4198 // Constant for byte-wide masking
4199 operand immI_255() %{
4200 predicate( n->get_int() == 255 );
4201 match(ConI);
4202
4203 format %{ %}
4204 interface(CONST_INTER);
4205 %}
4206
4207 // Constant for short-wide masking
4208 operand immI_65535() %{
4209 predicate(n->get_int() == 65535);
4210 match(ConI);
4211
4212 format %{ %}
4213 interface(CONST_INTER);
4214 %}
4215
4216 // Register Operands
4217 // Integer Register
4218 operand eRegI() %{
4219 constraint(ALLOC_IN_RC(e_reg));
4220 match(RegI);
4221 match(xRegI);
4222 match(eAXRegI);
4223 match(eBXRegI);
4224 match(eCXRegI);
4225 match(eDXRegI);
4226 match(eDIRegI);
4227 match(eSIRegI);
4228
4229 format %{ %}
4230 interface(REG_INTER);
4231 %}
4232
4233 // Subset of Integer Register
4234 operand xRegI(eRegI reg) %{
4235 constraint(ALLOC_IN_RC(x_reg));
4236 match(reg);
4237 match(eAXRegI);
4238 match(eBXRegI);
4239 match(eCXRegI);
4240 match(eDXRegI);
4241
4242 format %{ %}
4243 interface(REG_INTER);
4244 %}
4245
4246 // Special Registers
4247 operand eAXRegI(xRegI reg) %{
4248 constraint(ALLOC_IN_RC(eax_reg));
4249 match(reg);
4250 match(eRegI);
4251
4252 format %{ "EAX" %}
4253 interface(REG_INTER);
4254 %}
4255
4256 // Special Registers
4257 operand eBXRegI(xRegI reg) %{
4258 constraint(ALLOC_IN_RC(ebx_reg));
4259 match(reg);
4260 match(eRegI);
4261
4262 format %{ "EBX" %}
4263 interface(REG_INTER);
4264 %}
4265
4266 operand eCXRegI(xRegI reg) %{
4267 constraint(ALLOC_IN_RC(ecx_reg));
4268 match(reg);
4269 match(eRegI);
4270
4271 format %{ "ECX" %}
4272 interface(REG_INTER);
4273 %}
4274
4275 operand eDXRegI(xRegI reg) %{
4276 constraint(ALLOC_IN_RC(edx_reg));
4277 match(reg);
4278 match(eRegI);
4279
4280 format %{ "EDX" %}
4281 interface(REG_INTER);
4282 %}
4283
4284 operand eDIRegI(xRegI reg) %{
4285 constraint(ALLOC_IN_RC(edi_reg));
4286 match(reg);
4287 match(eRegI);
4288
4289 format %{ "EDI" %}
4290 interface(REG_INTER);
4291 %}
4292
4293 operand naxRegI() %{
4294 constraint(ALLOC_IN_RC(nax_reg));
4295 match(RegI);
4296 match(eCXRegI);
4297 match(eDXRegI);
4298 match(eSIRegI);
4299 match(eDIRegI);
4300
4301 format %{ %}
4302 interface(REG_INTER);
4303 %}
4304
4305 operand nadxRegI() %{
4306 constraint(ALLOC_IN_RC(nadx_reg));
4307 match(RegI);
4308 match(eBXRegI);
4309 match(eCXRegI);
4310 match(eSIRegI);
4311 match(eDIRegI);
4312
4313 format %{ %}
4314 interface(REG_INTER);
4315 %}
4316
4317 operand ncxRegI() %{
4318 constraint(ALLOC_IN_RC(ncx_reg));
4319 match(RegI);
4320 match(eAXRegI);
4321 match(eDXRegI);
4322 match(eSIRegI);
4323 match(eDIRegI);
4324
4325 format %{ %}
4326 interface(REG_INTER);
4327 %}
4328
4329 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4330 // //
4331 operand eSIRegI(xRegI reg) %{
4332 constraint(ALLOC_IN_RC(esi_reg));
4333 match(reg);
4334 match(eRegI);
4335
4336 format %{ "ESI" %}
4337 interface(REG_INTER);
4338 %}
4339
4340 // Pointer Register
4341 operand anyRegP() %{
4342 constraint(ALLOC_IN_RC(any_reg));
4343 match(RegP);
4344 match(eAXRegP);
4345 match(eBXRegP);
4346 match(eCXRegP);
4347 match(eDIRegP);
4348 match(eRegP);
4349
4350 format %{ %}
4351 interface(REG_INTER);
4352 %}
4353
4354 operand eRegP() %{
4355 constraint(ALLOC_IN_RC(e_reg));
4356 match(RegP);
4357 match(eAXRegP);
4358 match(eBXRegP);
4359 match(eCXRegP);
4360 match(eDIRegP);
4361
4362 format %{ %}
4363 interface(REG_INTER);
4364 %}
4365
4366 // On windows95, EBP is not safe to use for implicit null tests.
4367 operand eRegP_no_EBP() %{
4368 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4369 match(RegP);
4370 match(eAXRegP);
4371 match(eBXRegP);
4372 match(eCXRegP);
4373 match(eDIRegP);
4374
4375 op_cost(100);
4376 format %{ %}
4377 interface(REG_INTER);
4378 %}
4379
4380 operand naxRegP() %{
4381 constraint(ALLOC_IN_RC(nax_reg));
4382 match(RegP);
4383 match(eBXRegP);
4384 match(eDXRegP);
4385 match(eCXRegP);
4386 match(eSIRegP);
4387 match(eDIRegP);
4388
4389 format %{ %}
4390 interface(REG_INTER);
4391 %}
4392
4393 operand nabxRegP() %{
4394 constraint(ALLOC_IN_RC(nabx_reg));
4395 match(RegP);
4396 match(eCXRegP);
4397 match(eDXRegP);
4398 match(eSIRegP);
4399 match(eDIRegP);
4400
4401 format %{ %}
4402 interface(REG_INTER);
4403 %}
4404
4405 operand pRegP() %{
4406 constraint(ALLOC_IN_RC(p_reg));
4407 match(RegP);
4408 match(eBXRegP);
4409 match(eDXRegP);
4410 match(eSIRegP);
4411 match(eDIRegP);
4412
4413 format %{ %}
4414 interface(REG_INTER);
4415 %}
4416
4417 // Special Registers
4418 // Return a pointer value
4419 operand eAXRegP(eRegP reg) %{
4420 constraint(ALLOC_IN_RC(eax_reg));
4421 match(reg);
4422 format %{ "EAX" %}
4423 interface(REG_INTER);
4424 %}
4425
4426 // Used in AtomicAdd
4427 operand eBXRegP(eRegP reg) %{
4428 constraint(ALLOC_IN_RC(ebx_reg));
4429 match(reg);
4430 format %{ "EBX" %}
4431 interface(REG_INTER);
4432 %}
4433
4434 // Tail-call (interprocedural jump) to interpreter
4435 operand eCXRegP(eRegP reg) %{
4436 constraint(ALLOC_IN_RC(ecx_reg));
4437 match(reg);
4438 format %{ "ECX" %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand eSIRegP(eRegP reg) %{
4443 constraint(ALLOC_IN_RC(esi_reg));
4444 match(reg);
4445 format %{ "ESI" %}
4446 interface(REG_INTER);
4447 %}
4448
4449 // Used in rep stosw
4450 operand eDIRegP(eRegP reg) %{
4451 constraint(ALLOC_IN_RC(edi_reg));
4452 match(reg);
4453 format %{ "EDI" %}
4454 interface(REG_INTER);
4455 %}
4456
4457 operand eBPRegP() %{
4458 constraint(ALLOC_IN_RC(ebp_reg));
4459 match(RegP);
4460 format %{ "EBP" %}
4461 interface(REG_INTER);
4462 %}
4463
4464 operand eRegL() %{
4465 constraint(ALLOC_IN_RC(long_reg));
4466 match(RegL);
4467 match(eADXRegL);
4468
4469 format %{ %}
4470 interface(REG_INTER);
4471 %}
4472
4473 operand eADXRegL( eRegL reg ) %{
4474 constraint(ALLOC_IN_RC(eadx_reg));
4475 match(reg);
4476
4477 format %{ "EDX:EAX" %}
4478 interface(REG_INTER);
4479 %}
4480
4481 operand eBCXRegL( eRegL reg ) %{
4482 constraint(ALLOC_IN_RC(ebcx_reg));
4483 match(reg);
4484
4485 format %{ "EBX:ECX" %}
4486 interface(REG_INTER);
4487 %}
4488
4489 // Special case for integer high multiply
4490 operand eADXRegL_low_only() %{
4491 constraint(ALLOC_IN_RC(eadx_reg));
4492 match(RegL);
4493
4494 format %{ "EAX" %}
4495 interface(REG_INTER);
4496 %}
4497
4498 // Flags register, used as output of compare instructions
4499 operand eFlagsReg() %{
4500 constraint(ALLOC_IN_RC(int_flags));
4501 match(RegFlags);
4502
4503 format %{ "EFLAGS" %}
4504 interface(REG_INTER);
4505 %}
4506
4507 // Flags register, used as output of FLOATING POINT compare instructions
4508 operand eFlagsRegU() %{
4509 constraint(ALLOC_IN_RC(int_flags));
4510 match(RegFlags);
4511
4512 format %{ "EFLAGS_U" %}
4513 interface(REG_INTER);
4514 %}
4515
4516 operand eFlagsRegUCF() %{
4517 constraint(ALLOC_IN_RC(int_flags));
4518 match(RegFlags);
4519 predicate(false);
4520
4521 format %{ "EFLAGS_U_CF" %}
4522 interface(REG_INTER);
4523 %}
4524
4525 // Condition Code Register used by long compare
4526 operand flagsReg_long_LTGE() %{
4527 constraint(ALLOC_IN_RC(int_flags));
4528 match(RegFlags);
4529 format %{ "FLAGS_LTGE" %}
4530 interface(REG_INTER);
4531 %}
4532 operand flagsReg_long_EQNE() %{
4533 constraint(ALLOC_IN_RC(int_flags));
4534 match(RegFlags);
4535 format %{ "FLAGS_EQNE" %}
4536 interface(REG_INTER);
4537 %}
4538 operand flagsReg_long_LEGT() %{
4539 constraint(ALLOC_IN_RC(int_flags));
4540 match(RegFlags);
4541 format %{ "FLAGS_LEGT" %}
4542 interface(REG_INTER);
4543 %}
4544
4545 // Float register operands
4546 operand regDPR() %{
4547 predicate( UseSSE < 2 );
4548 constraint(ALLOC_IN_RC(dbl_reg));
4549 match(RegD);
4550 match(regDPR1);
4551 match(regDPR2);
4552 format %{ %}
4553 interface(REG_INTER);
4554 %}
4555
4556 operand regDPR1(regDPR reg) %{
4557 predicate( UseSSE < 2 );
4558 constraint(ALLOC_IN_RC(dbl_reg0));
4559 match(reg);
4560 format %{ "FPR1" %}
4561 interface(REG_INTER);
4562 %}
4563
4564 operand regDPR2(regDPR reg) %{
4565 predicate( UseSSE < 2 );
4566 constraint(ALLOC_IN_RC(dbl_reg1));
4567 match(reg);
4568 format %{ "FPR2" %}
4569 interface(REG_INTER);
4570 %}
4571
4572 operand regnotDPR1(regDPR reg) %{
4573 predicate( UseSSE < 2 );
4574 constraint(ALLOC_IN_RC(dbl_notreg0));
4575 match(reg);
4576 format %{ %}
4577 interface(REG_INTER);
4578 %}
4579
4580 // XMM Double register operands
4581 operand regD() %{
4582 predicate( UseSSE>=2 );
4583 constraint(ALLOC_IN_RC(xdb_reg));
4584 match(RegD);
4585 match(regD6);
4586 match(regD7);
4587 format %{ %}
4588 interface(REG_INTER);
4589 %}
4590
4591 // XMM6 double register operands
4592 operand regD6(regD reg) %{
4593 predicate( UseSSE>=2 );
4594 constraint(ALLOC_IN_RC(xdb_reg6));
4595 match(reg);
4596 format %{ "XMM6" %}
4597 interface(REG_INTER);
4598 %}
4599
4600 // XMM7 double register operands
4601 operand regD7(regD reg) %{
4602 predicate( UseSSE>=2 );
4603 constraint(ALLOC_IN_RC(xdb_reg7));
4604 match(reg);
4605 format %{ "XMM7" %}
4606 interface(REG_INTER);
4607 %}
4608
4609 // Float register operands
4610 operand regFPR() %{
4611 predicate( UseSSE < 2 );
4612 constraint(ALLOC_IN_RC(flt_reg));
4613 match(RegF);
4614 match(regFPR1);
4615 format %{ %}
4616 interface(REG_INTER);
4617 %}
4618
4619 // Float register operands
4620 operand regFPR1(regFPR reg) %{
4621 predicate( UseSSE < 2 );
4622 constraint(ALLOC_IN_RC(flt_reg0));
4623 match(reg);
4624 format %{ "FPR1" %}
4625 interface(REG_INTER);
4626 %}
4627
4628 // XMM register operands
4629 operand regF() %{
4630 predicate( UseSSE>=1 );
4631 constraint(ALLOC_IN_RC(xmm_reg));
4632 match(RegF);
4633 format %{ %}
4634 interface(REG_INTER);
4635 %}
4636
4637
4638 //----------Memory Operands----------------------------------------------------
4639 // Direct Memory Operand
4640 operand direct(immP addr) %{
4641 match(addr);
4642
4643 format %{ "[$addr]" %}
4644 interface(MEMORY_INTER) %{
4645 base(0xFFFFFFFF);
4646 index(0x4);
4647 scale(0x0);
4648 disp($addr);
4649 %}
4650 %}
4651
4652 // Indirect Memory Operand
4653 operand indirect(eRegP reg) %{
4654 constraint(ALLOC_IN_RC(e_reg));
4655 match(reg);
4656
4657 format %{ "[$reg]" %}
4658 interface(MEMORY_INTER) %{
4659 base($reg);
4660 index(0x4);
4661 scale(0x0);
4662 disp(0x0);
4663 %}
4664 %}
4665
4666 // Indirect Memory Plus Short Offset Operand
4667 operand indOffset8(eRegP reg, immI8 off) %{
4668 match(AddP reg off);
4669
4670 format %{ "[$reg + $off]" %}
4671 interface(MEMORY_INTER) %{
4672 base($reg);
4673 index(0x4);
4674 scale(0x0);
4675 disp($off);
4676 %}
4677 %}
4678
4679 // Indirect Memory Plus Long Offset Operand
4680 operand indOffset32(eRegP reg, immI off) %{
4681 match(AddP reg off);
4682
4683 format %{ "[$reg + $off]" %}
4684 interface(MEMORY_INTER) %{
4685 base($reg);
4686 index(0x4);
4687 scale(0x0);
4688 disp($off);
4689 %}
4690 %}
4691
4692 // Indirect Memory Plus Long Offset Operand
4693 operand indOffset32X(eRegI reg, immP off) %{
4694 match(AddP off reg);
4695
4696 format %{ "[$reg + $off]" %}
4697 interface(MEMORY_INTER) %{
4698 base($reg);
4699 index(0x4);
4700 scale(0x0);
4701 disp($off);
4702 %}
4703 %}
4704
4705 // Indirect Memory Plus Index Register Plus Offset Operand
4706 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
4707 match(AddP (AddP reg ireg) off);
4708
4709 op_cost(10);
4710 format %{"[$reg + $off + $ireg]" %}
4711 interface(MEMORY_INTER) %{
4712 base($reg);
4713 index($ireg);
4714 scale(0x0);
4715 disp($off);
4716 %}
4717 %}
4718
4719 // Indirect Memory Plus Index Register Plus Offset Operand
4720 operand indIndex(eRegP reg, eRegI ireg) %{
4721 match(AddP reg ireg);
4722
4723 op_cost(10);
4724 format %{"[$reg + $ireg]" %}
4725 interface(MEMORY_INTER) %{
4726 base($reg);
4727 index($ireg);
4728 scale(0x0);
4729 disp(0x0);
4730 %}
4731 %}
4732
4733 // // -------------------------------------------------------------------------
4734 // // 486 architecture doesn't support "scale * index + offset" with out a base
4735 // // -------------------------------------------------------------------------
4736 // // Scaled Memory Operands
4737 // // Indirect Memory Times Scale Plus Offset Operand
4738 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
4739 // match(AddP off (LShiftI ireg scale));
4740 //
4741 // op_cost(10);
4742 // format %{"[$off + $ireg << $scale]" %}
4743 // interface(MEMORY_INTER) %{
4744 // base(0x4);
4745 // index($ireg);
4746 // scale($scale);
4747 // disp($off);
4748 // %}
4749 // %}
4750
4751 // Indirect Memory Times Scale Plus Index Register
4752 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
4753 match(AddP reg (LShiftI ireg scale));
4754
4755 op_cost(10);
4756 format %{"[$reg + $ireg << $scale]" %}
4757 interface(MEMORY_INTER) %{
4758 base($reg);
4759 index($ireg);
4760 scale($scale);
4761 disp(0x0);
4762 %}
4763 %}
4764
4765 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4766 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
4767 match(AddP (AddP reg (LShiftI ireg scale)) off);
4768
4769 op_cost(10);
4770 format %{"[$reg + $off + $ireg << $scale]" %}
4771 interface(MEMORY_INTER) %{
4772 base($reg);
4773 index($ireg);
4774 scale($scale);
4775 disp($off);
4776 %}
4777 %}
4778
4779 //----------Load Long Memory Operands------------------------------------------
4780 // The load-long idiom will use it's address expression again after loading
4781 // the first word of the long. If the load-long destination overlaps with
4782 // registers used in the addressing expression, the 2nd half will be loaded
4783 // from a clobbered address. Fix this by requiring that load-long use
4784 // address registers that do not overlap with the load-long target.
4785
4786 // load-long support
4787 operand load_long_RegP() %{
4788 constraint(ALLOC_IN_RC(esi_reg));
4789 match(RegP);
4790 match(eSIRegP);
4791 op_cost(100);
4792 format %{ %}
4793 interface(REG_INTER);
4794 %}
4795
4796 // Indirect Memory Operand Long
4797 operand load_long_indirect(load_long_RegP reg) %{
4798 constraint(ALLOC_IN_RC(esi_reg));
4799 match(reg);
4800
4801 format %{ "[$reg]" %}
4802 interface(MEMORY_INTER) %{
4803 base($reg);
4804 index(0x4);
4805 scale(0x0);
4806 disp(0x0);
4807 %}
4808 %}
4809
4810 // Indirect Memory Plus Long Offset Operand
4811 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4812 match(AddP reg off);
4813
4814 format %{ "[$reg + $off]" %}
4815 interface(MEMORY_INTER) %{
4816 base($reg);
4817 index(0x4);
4818 scale(0x0);
4819 disp($off);
4820 %}
4821 %}
4822
4823 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4824
4825
4826 //----------Special Memory Operands--------------------------------------------
4827 // Stack Slot Operand - This operand is used for loading and storing temporary
4828 // values on the stack where a match requires a value to
4829 // flow through memory.
4830 operand stackSlotP(sRegP reg) %{
4831 constraint(ALLOC_IN_RC(stack_slots));
4832 // No match rule because this operand is only generated in matching
4833 format %{ "[$reg]" %}
4834 interface(MEMORY_INTER) %{
4835 base(0x4); // ESP
4836 index(0x4); // No Index
4837 scale(0x0); // No Scale
4838 disp($reg); // Stack Offset
4839 %}
4840 %}
4841
4842 operand stackSlotI(sRegI reg) %{
4843 constraint(ALLOC_IN_RC(stack_slots));
4844 // No match rule because this operand is only generated in matching
4845 format %{ "[$reg]" %}
4846 interface(MEMORY_INTER) %{
4847 base(0x4); // ESP
4848 index(0x4); // No Index
4849 scale(0x0); // No Scale
4850 disp($reg); // Stack Offset
4851 %}
4852 %}
4853
4854 operand stackSlotF(sRegF reg) %{
4855 constraint(ALLOC_IN_RC(stack_slots));
4856 // No match rule because this operand is only generated in matching
4857 format %{ "[$reg]" %}
4858 interface(MEMORY_INTER) %{
4859 base(0x4); // ESP
4860 index(0x4); // No Index
4861 scale(0x0); // No Scale
4862 disp($reg); // Stack Offset
4863 %}
4864 %}
4865
4866 operand stackSlotD(sRegD reg) %{
4867 constraint(ALLOC_IN_RC(stack_slots));
4868 // No match rule because this operand is only generated in matching
4869 format %{ "[$reg]" %}
4870 interface(MEMORY_INTER) %{
4871 base(0x4); // ESP
4872 index(0x4); // No Index
4873 scale(0x0); // No Scale
4874 disp($reg); // Stack Offset
4875 %}
4876 %}
4877
4878 operand stackSlotL(sRegL reg) %{
4879 constraint(ALLOC_IN_RC(stack_slots));
4880 // No match rule because this operand is only generated in matching
4881 format %{ "[$reg]" %}
4882 interface(MEMORY_INTER) %{
4883 base(0x4); // ESP
4884 index(0x4); // No Index
4885 scale(0x0); // No Scale
4886 disp($reg); // Stack Offset
4887 %}
4888 %}
4889
4890 //----------Memory Operands - Win95 Implicit Null Variants----------------
4891 // Indirect Memory Operand
4892 operand indirect_win95_safe(eRegP_no_EBP reg)
4893 %{
4894 constraint(ALLOC_IN_RC(e_reg));
4895 match(reg);
4896
4897 op_cost(100);
4898 format %{ "[$reg]" %}
4899 interface(MEMORY_INTER) %{
4900 base($reg);
4901 index(0x4);
4902 scale(0x0);
4903 disp(0x0);
4904 %}
4905 %}
4906
4907 // Indirect Memory Plus Short Offset Operand
4908 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4909 %{
4910 match(AddP reg off);
4911
4912 op_cost(100);
4913 format %{ "[$reg + $off]" %}
4914 interface(MEMORY_INTER) %{
4915 base($reg);
4916 index(0x4);
4917 scale(0x0);
4918 disp($off);
4919 %}
4920 %}
4921
4922 // Indirect Memory Plus Long Offset Operand
4923 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4924 %{
4925 match(AddP reg off);
4926
4927 op_cost(100);
4928 format %{ "[$reg + $off]" %}
4929 interface(MEMORY_INTER) %{
4930 base($reg);
4931 index(0x4);
4932 scale(0x0);
4933 disp($off);
4934 %}
4935 %}
4936
4937 // Indirect Memory Plus Index Register Plus Offset Operand
4938 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
4939 %{
4940 match(AddP (AddP reg ireg) off);
4941
4942 op_cost(100);
4943 format %{"[$reg + $off + $ireg]" %}
4944 interface(MEMORY_INTER) %{
4945 base($reg);
4946 index($ireg);
4947 scale(0x0);
4948 disp($off);
4949 %}
4950 %}
4951
4952 // Indirect Memory Times Scale Plus Index Register
4953 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
4954 %{
4955 match(AddP reg (LShiftI ireg scale));
4956
4957 op_cost(100);
4958 format %{"[$reg + $ireg << $scale]" %}
4959 interface(MEMORY_INTER) %{
4960 base($reg);
4961 index($ireg);
4962 scale($scale);
4963 disp(0x0);
4964 %}
4965 %}
4966
4967 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4968 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
4969 %{
4970 match(AddP (AddP reg (LShiftI ireg scale)) off);
4971
4972 op_cost(100);
4973 format %{"[$reg + $off + $ireg << $scale]" %}
4974 interface(MEMORY_INTER) %{
4975 base($reg);
4976 index($ireg);
4977 scale($scale);
4978 disp($off);
4979 %}
4980 %}
4981
4982 //----------Conditional Branch Operands----------------------------------------
4983 // Comparison Op - This is the operation of the comparison, and is limited to
4984 // the following set of codes:
4985 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4986 //
4987 // Other attributes of the comparison, such as unsignedness, are specified
4988 // by the comparison instruction that sets a condition code flags register.
4989 // That result is represented by a flags operand whose subtype is appropriate
4990 // to the unsignedness (etc.) of the comparison.
4991 //
4992 // Later, the instruction which matches both the Comparison Op (a Bool) and
4993 // the flags (produced by the Cmp) specifies the coding of the comparison op
4994 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4995
4996 // Comparision Code
4997 operand cmpOp() %{
4998 match(Bool);
4999
5000 format %{ "" %}
5001 interface(COND_INTER) %{
5002 equal(0x4, "e");
5003 not_equal(0x5, "ne");
5004 less(0xC, "l");
5005 greater_equal(0xD, "ge");
5006 less_equal(0xE, "le");
5007 greater(0xF, "g");
5008 %}
5009 %}
5010
5011 // Comparison Code, unsigned compare. Used by FP also, with
5012 // C2 (unordered) turned into GT or LT already. The other bits
5013 // C0 and C3 are turned into Carry & Zero flags.
5014 operand cmpOpU() %{
5015 match(Bool);
5016
5017 format %{ "" %}
5018 interface(COND_INTER) %{
5019 equal(0x4, "e");
5020 not_equal(0x5, "ne");
5021 less(0x2, "b");
5022 greater_equal(0x3, "nb");
5023 less_equal(0x6, "be");
5024 greater(0x7, "nbe");
5025 %}
5026 %}
5027
5028 // Floating comparisons that don't require any fixup for the unordered case
5029 operand cmpOpUCF() %{
5030 match(Bool);
5031 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5032 n->as_Bool()->_test._test == BoolTest::ge ||
5033 n->as_Bool()->_test._test == BoolTest::le ||
5034 n->as_Bool()->_test._test == BoolTest::gt);
5035 format %{ "" %}
5036 interface(COND_INTER) %{
5037 equal(0x4, "e");
5038 not_equal(0x5, "ne");
5039 less(0x2, "b");
5040 greater_equal(0x3, "nb");
5041 less_equal(0x6, "be");
5042 greater(0x7, "nbe");
5043 %}
5044 %}
5045
5046
5047 // Floating comparisons that can be fixed up with extra conditional jumps
5048 operand cmpOpUCF2() %{
5049 match(Bool);
5050 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5051 n->as_Bool()->_test._test == BoolTest::eq);
5052 format %{ "" %}
5053 interface(COND_INTER) %{
5054 equal(0x4, "e");
5055 not_equal(0x5, "ne");
5056 less(0x2, "b");
5057 greater_equal(0x3, "nb");
5058 less_equal(0x6, "be");
5059 greater(0x7, "nbe");
5060 %}
5061 %}
5062
5063 // Comparison Code for FP conditional move
5064 operand cmpOp_fcmov() %{
5065 match(Bool);
5066
5067 format %{ "" %}
5068 interface(COND_INTER) %{
5069 equal (0x0C8);
5070 not_equal (0x1C8);
5071 less (0x0C0);
5072 greater_equal(0x1C0);
5073 less_equal (0x0D0);
5074 greater (0x1D0);
5075 %}
5076 %}
5077
5078 // Comparision Code used in long compares
5079 operand cmpOp_commute() %{
5080 match(Bool);
5081
5082 format %{ "" %}
5083 interface(COND_INTER) %{
5084 equal(0x4, "e");
5085 not_equal(0x5, "ne");
5086 less(0xF, "g");
5087 greater_equal(0xE, "le");
5088 less_equal(0xD, "ge");
5089 greater(0xC, "l");
5090 %}
5091 %}
5092
5093 //----------OPERAND CLASSES----------------------------------------------------
5094 // Operand Classes are groups of operands that are used as to simplify
5095 // instruction definitions by not requiring the AD writer to specify separate
5096 // instructions for every form of operand when the instruction accepts
5097 // multiple operand types with the same basic encoding and format. The classic
5098 // case of this is memory operands.
5099
5100 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5101 indIndex, indIndexScale, indIndexScaleOffset);
5102
5103 // Long memory operations are encoded in 2 instructions and a +4 offset.
5104 // This means some kind of offset is always required and you cannot use
5105 // an oop as the offset (done when working on static globals).
5106 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5107 indIndex, indIndexScale, indIndexScaleOffset);
5108
5109
5110 //----------PIPELINE-----------------------------------------------------------
5111 // Rules which define the behavior of the target architectures pipeline.
5112 pipeline %{
5113
5114 //----------ATTRIBUTES---------------------------------------------------------
5115 attributes %{
5116 variable_size_instructions; // Fixed size instructions
5117 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5118 instruction_unit_size = 1; // An instruction is 1 bytes long
5119 instruction_fetch_unit_size = 16; // The processor fetches one line
5120 instruction_fetch_units = 1; // of 16 bytes
5121
5122 // List of nop instructions
5123 nops( MachNop );
5124 %}
5125
5126 //----------RESOURCES----------------------------------------------------------
5127 // Resources are the functional units available to the machine
5128
5129 // Generic P2/P3 pipeline
5130 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5131 // 3 instructions decoded per cycle.
5132 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5133 // 2 ALU op, only ALU0 handles mul/div instructions.
5134 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5135 MS0, MS1, MEM = MS0 | MS1,
5136 BR, FPU,
5137 ALU0, ALU1, ALU = ALU0 | ALU1 );
5138
5139 //----------PIPELINE DESCRIPTION-----------------------------------------------
5140 // Pipeline Description specifies the stages in the machine's pipeline
5141
5142 // Generic P2/P3 pipeline
5143 pipe_desc(S0, S1, S2, S3, S4, S5);
5144
5145 //----------PIPELINE CLASSES---------------------------------------------------
5146 // Pipeline Classes describe the stages in which input and output are
5147 // referenced by the hardware pipeline.
5148
5149 // Naming convention: ialu or fpu
5150 // Then: _reg
5151 // Then: _reg if there is a 2nd register
5152 // Then: _long if it's a pair of instructions implementing a long
5153 // Then: _fat if it requires the big decoder
5154 // Or: _mem if it requires the big decoder and a memory unit.
5155
5156 // Integer ALU reg operation
5157 pipe_class ialu_reg(eRegI dst) %{
5158 single_instruction;
5159 dst : S4(write);
5160 dst : S3(read);
5161 DECODE : S0; // any decoder
5162 ALU : S3; // any alu
5163 %}
5164
5165 // Long ALU reg operation
5166 pipe_class ialu_reg_long(eRegL dst) %{
5167 instruction_count(2);
5168 dst : S4(write);
5169 dst : S3(read);
5170 DECODE : S0(2); // any 2 decoders
5171 ALU : S3(2); // both alus
5172 %}
5173
5174 // Integer ALU reg operation using big decoder
5175 pipe_class ialu_reg_fat(eRegI dst) %{
5176 single_instruction;
5177 dst : S4(write);
5178 dst : S3(read);
5179 D0 : S0; // big decoder only
5180 ALU : S3; // any alu
5181 %}
5182
5183 // Long ALU reg operation using big decoder
5184 pipe_class ialu_reg_long_fat(eRegL dst) %{
5185 instruction_count(2);
5186 dst : S4(write);
5187 dst : S3(read);
5188 D0 : S0(2); // big decoder only; twice
5189 ALU : S3(2); // any 2 alus
5190 %}
5191
5192 // Integer ALU reg-reg operation
5193 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5194 single_instruction;
5195 dst : S4(write);
5196 src : S3(read);
5197 DECODE : S0; // any decoder
5198 ALU : S3; // any alu
5199 %}
5200
5201 // Long ALU reg-reg operation
5202 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5203 instruction_count(2);
5204 dst : S4(write);
5205 src : S3(read);
5206 DECODE : S0(2); // any 2 decoders
5207 ALU : S3(2); // both alus
5208 %}
5209
5210 // Integer ALU reg-reg operation
5211 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5212 single_instruction;
5213 dst : S4(write);
5214 src : S3(read);
5215 D0 : S0; // big decoder only
5216 ALU : S3; // any alu
5217 %}
5218
5219 // Long ALU reg-reg operation
5220 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5221 instruction_count(2);
5222 dst : S4(write);
5223 src : S3(read);
5224 D0 : S0(2); // big decoder only; twice
5225 ALU : S3(2); // both alus
5226 %}
5227
5228 // Integer ALU reg-mem operation
5229 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5230 single_instruction;
5231 dst : S5(write);
5232 mem : S3(read);
5233 D0 : S0; // big decoder only
5234 ALU : S4; // any alu
5235 MEM : S3; // any mem
5236 %}
5237
5238 // Long ALU reg-mem operation
5239 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5240 instruction_count(2);
5241 dst : S5(write);
5242 mem : S3(read);
5243 D0 : S0(2); // big decoder only; twice
5244 ALU : S4(2); // any 2 alus
5245 MEM : S3(2); // both mems
5246 %}
5247
5248 // Integer mem operation (prefetch)
5249 pipe_class ialu_mem(memory mem)
5250 %{
5251 single_instruction;
5252 mem : S3(read);
5253 D0 : S0; // big decoder only
5254 MEM : S3; // any mem
5255 %}
5256
5257 // Integer Store to Memory
5258 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5259 single_instruction;
5260 mem : S3(read);
5261 src : S5(read);
5262 D0 : S0; // big decoder only
5263 ALU : S4; // any alu
5264 MEM : S3;
5265 %}
5266
5267 // Long Store to Memory
5268 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5269 instruction_count(2);
5270 mem : S3(read);
5271 src : S5(read);
5272 D0 : S0(2); // big decoder only; twice
5273 ALU : S4(2); // any 2 alus
5274 MEM : S3(2); // Both mems
5275 %}
5276
5277 // Integer Store to Memory
5278 pipe_class ialu_mem_imm(memory mem) %{
5279 single_instruction;
5280 mem : S3(read);
5281 D0 : S0; // big decoder only
5282 ALU : S4; // any alu
5283 MEM : S3;
5284 %}
5285
5286 // Integer ALU0 reg-reg operation
5287 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5288 single_instruction;
5289 dst : S4(write);
5290 src : S3(read);
5291 D0 : S0; // Big decoder only
5292 ALU0 : S3; // only alu0
5293 %}
5294
5295 // Integer ALU0 reg-mem operation
5296 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5297 single_instruction;
5298 dst : S5(write);
5299 mem : S3(read);
5300 D0 : S0; // big decoder only
5301 ALU0 : S4; // ALU0 only
5302 MEM : S3; // any mem
5303 %}
5304
5305 // Integer ALU reg-reg operation
5306 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5307 single_instruction;
5308 cr : S4(write);
5309 src1 : S3(read);
5310 src2 : S3(read);
5311 DECODE : S0; // any decoder
5312 ALU : S3; // any alu
5313 %}
5314
5315 // Integer ALU reg-imm operation
5316 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5317 single_instruction;
5318 cr : S4(write);
5319 src1 : S3(read);
5320 DECODE : S0; // any decoder
5321 ALU : S3; // any alu
5322 %}
5323
5324 // Integer ALU reg-mem operation
5325 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5326 single_instruction;
5327 cr : S4(write);
5328 src1 : S3(read);
5329 src2 : S3(read);
5330 D0 : S0; // big decoder only
5331 ALU : S4; // any alu
5332 MEM : S3;
5333 %}
5334
5335 // Conditional move reg-reg
5336 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5337 instruction_count(4);
5338 y : S4(read);
5339 q : S3(read);
5340 p : S3(read);
5341 DECODE : S0(4); // any decoder
5342 %}
5343
5344 // Conditional move reg-reg
5345 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5346 single_instruction;
5347 dst : S4(write);
5348 src : S3(read);
5349 cr : S3(read);
5350 DECODE : S0; // any decoder
5351 %}
5352
5353 // Conditional move reg-mem
5354 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5355 single_instruction;
5356 dst : S4(write);
5357 src : S3(read);
5358 cr : S3(read);
5359 DECODE : S0; // any decoder
5360 MEM : S3;
5361 %}
5362
5363 // Conditional move reg-reg long
5364 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5365 single_instruction;
5366 dst : S4(write);
5367 src : S3(read);
5368 cr : S3(read);
5369 DECODE : S0(2); // any 2 decoders
5370 %}
5371
5372 // Conditional move double reg-reg
5373 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5374 single_instruction;
5375 dst : S4(write);
5376 src : S3(read);
5377 cr : S3(read);
5378 DECODE : S0; // any decoder
5379 %}
5380
5381 // Float reg-reg operation
5382 pipe_class fpu_reg(regDPR dst) %{
5383 instruction_count(2);
5384 dst : S3(read);
5385 DECODE : S0(2); // any 2 decoders
5386 FPU : S3;
5387 %}
5388
5389 // Float reg-reg operation
5390 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5391 instruction_count(2);
5392 dst : S4(write);
5393 src : S3(read);
5394 DECODE : S0(2); // any 2 decoders
5395 FPU : S3;
5396 %}
5397
5398 // Float reg-reg operation
5399 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5400 instruction_count(3);
5401 dst : S4(write);
5402 src1 : S3(read);
5403 src2 : S3(read);
5404 DECODE : S0(3); // any 3 decoders
5405 FPU : S3(2);
5406 %}
5407
5408 // Float reg-reg operation
5409 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5410 instruction_count(4);
5411 dst : S4(write);
5412 src1 : S3(read);
5413 src2 : S3(read);
5414 src3 : S3(read);
5415 DECODE : S0(4); // any 3 decoders
5416 FPU : S3(2);
5417 %}
5418
5419 // Float reg-reg operation
5420 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5421 instruction_count(4);
5422 dst : S4(write);
5423 src1 : S3(read);
5424 src2 : S3(read);
5425 src3 : S3(read);
5426 DECODE : S1(3); // any 3 decoders
5427 D0 : S0; // Big decoder only
5428 FPU : S3(2);
5429 MEM : S3;
5430 %}
5431
5432 // Float reg-mem operation
5433 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5434 instruction_count(2);
5435 dst : S5(write);
5436 mem : S3(read);
5437 D0 : S0; // big decoder only
5438 DECODE : S1; // any decoder for FPU POP
5439 FPU : S4;
5440 MEM : S3; // any mem
5441 %}
5442
5443 // Float reg-mem operation
5444 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5445 instruction_count(3);
5446 dst : S5(write);
5447 src1 : S3(read);
5448 mem : S3(read);
5449 D0 : S0; // big decoder only
5450 DECODE : S1(2); // any decoder for FPU POP
5451 FPU : S4;
5452 MEM : S3; // any mem
5453 %}
5454
5455 // Float mem-reg operation
5456 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5457 instruction_count(2);
5458 src : S5(read);
5459 mem : S3(read);
5460 DECODE : S0; // any decoder for FPU PUSH
5461 D0 : S1; // big decoder only
5462 FPU : S4;
5463 MEM : S3; // any mem
5464 %}
5465
5466 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5467 instruction_count(3);
5468 src1 : S3(read);
5469 src2 : S3(read);
5470 mem : S3(read);
5471 DECODE : S0(2); // any decoder for FPU PUSH
5472 D0 : S1; // big decoder only
5473 FPU : S4;
5474 MEM : S3; // any mem
5475 %}
5476
5477 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5478 instruction_count(3);
5479 src1 : S3(read);
5480 src2 : S3(read);
5481 mem : S4(read);
5482 DECODE : S0; // any decoder for FPU PUSH
5483 D0 : S0(2); // big decoder only
5484 FPU : S4;
5485 MEM : S3(2); // any mem
5486 %}
5487
5488 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5489 instruction_count(2);
5490 src1 : S3(read);
5491 dst : S4(read);
5492 D0 : S0(2); // big decoder only
5493 MEM : S3(2); // any mem
5494 %}
5495
5496 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5497 instruction_count(3);
5498 src1 : S3(read);
5499 src2 : S3(read);
5500 dst : S4(read);
5501 D0 : S0(3); // big decoder only
5502 FPU : S4;
5503 MEM : S3(3); // any mem
5504 %}
5505
5506 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5507 instruction_count(3);
5508 src1 : S4(read);
5509 mem : S4(read);
5510 DECODE : S0; // any decoder for FPU PUSH
5511 D0 : S0(2); // big decoder only
5512 FPU : S4;
5513 MEM : S3(2); // any mem
5514 %}
5515
5516 // Float load constant
5517 pipe_class fpu_reg_con(regDPR dst) %{
5518 instruction_count(2);
5519 dst : S5(write);
5520 D0 : S0; // big decoder only for the load
5521 DECODE : S1; // any decoder for FPU POP
5522 FPU : S4;
5523 MEM : S3; // any mem
5524 %}
5525
5526 // Float load constant
5527 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5528 instruction_count(3);
5529 dst : S5(write);
5530 src : S3(read);
5531 D0 : S0; // big decoder only for the load
5532 DECODE : S1(2); // any decoder for FPU POP
5533 FPU : S4;
5534 MEM : S3; // any mem
5535 %}
5536
5537 // UnConditional branch
5538 pipe_class pipe_jmp( label labl ) %{
5539 single_instruction;
5540 BR : S3;
5541 %}
5542
5543 // Conditional branch
5544 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5545 single_instruction;
5546 cr : S1(read);
5547 BR : S3;
5548 %}
5549
5550 // Allocation idiom
5551 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5552 instruction_count(1); force_serialization;
5553 fixed_latency(6);
5554 heap_ptr : S3(read);
5555 DECODE : S0(3);
5556 D0 : S2;
5557 MEM : S3;
5558 ALU : S3(2);
5559 dst : S5(write);
5560 BR : S5;
5561 %}
5562
5563 // Generic big/slow expanded idiom
5564 pipe_class pipe_slow( ) %{
5565 instruction_count(10); multiple_bundles; force_serialization;
5566 fixed_latency(100);
5567 D0 : S0(2);
5568 MEM : S3(2);
5569 %}
5570
5571 // The real do-nothing guy
5572 pipe_class empty( ) %{
5573 instruction_count(0);
5574 %}
5575
5576 // Define the class for the Nop node
5577 define %{
5578 MachNop = empty;
5579 %}
5580
5581 %}
5582
5583 //----------INSTRUCTIONS-------------------------------------------------------
5584 //
5585 // match -- States which machine-independent subtree may be replaced
5586 // by this instruction.
5587 // ins_cost -- The estimated cost of this instruction is used by instruction
5588 // selection to identify a minimum cost tree of machine
5589 // instructions that matches a tree of machine-independent
5590 // instructions.
5591 // format -- A string providing the disassembly for this instruction.
5592 // The value of an instruction's operand may be inserted
5593 // by referring to it with a '$' prefix.
5594 // opcode -- Three instruction opcodes may be provided. These are referred
5595 // to within an encode class as $primary, $secondary, and $tertiary
5596 // respectively. The primary opcode is commonly used to
5597 // indicate the type of machine instruction, while secondary
5598 // and tertiary are often used for prefix options or addressing
5599 // modes.
5600 // ins_encode -- A list of encode classes with parameters. The encode class
5601 // name must have been defined in an 'enc_class' specification
5602 // in the encode section of the architecture description.
5603
5604 //----------BSWAP-Instruction--------------------------------------------------
5605 instruct bytes_reverse_int(eRegI dst) %{
5606 match(Set dst (ReverseBytesI dst));
5607
5608 format %{ "BSWAP $dst" %}
5609 opcode(0x0F, 0xC8);
5610 ins_encode( OpcP, OpcSReg(dst) );
5611 ins_pipe( ialu_reg );
5612 %}
5613
5614 instruct bytes_reverse_long(eRegL dst) %{
5615 match(Set dst (ReverseBytesL dst));
5616
5617 format %{ "BSWAP $dst.lo\n\t"
5618 "BSWAP $dst.hi\n\t"
5619 "XCHG $dst.lo $dst.hi" %}
5620
5621 ins_cost(125);
5622 ins_encode( bswap_long_bytes(dst) );
5623 ins_pipe( ialu_reg_reg);
5624 %}
5625
5626 instruct bytes_reverse_unsigned_short(eRegI dst) %{
5627 match(Set dst (ReverseBytesUS dst));
5628
5629 format %{ "BSWAP $dst\n\t"
5630 "SHR $dst,16\n\t" %}
5631 ins_encode %{
5632 __ bswapl($dst$$Register);
5633 __ shrl($dst$$Register, 16);
5634 %}
5635 ins_pipe( ialu_reg );
5636 %}
5637
5638 instruct bytes_reverse_short(eRegI dst) %{
5639 match(Set dst (ReverseBytesS dst));
5640
5641 format %{ "BSWAP $dst\n\t"
5642 "SAR $dst,16\n\t" %}
5643 ins_encode %{
5644 __ bswapl($dst$$Register);
5645 __ sarl($dst$$Register, 16);
5646 %}
5647 ins_pipe( ialu_reg );
5648 %}
5649
5650
5651 //---------- Zeros Count Instructions ------------------------------------------
5652
5653 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5654 predicate(UseCountLeadingZerosInstruction);
5655 match(Set dst (CountLeadingZerosI src));
5656 effect(KILL cr);
5657
5658 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5659 ins_encode %{
5660 __ lzcntl($dst$$Register, $src$$Register);
5661 %}
5662 ins_pipe(ialu_reg);
5663 %}
5664
5665 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
5666 predicate(!UseCountLeadingZerosInstruction);
5667 match(Set dst (CountLeadingZerosI src));
5668 effect(KILL cr);
5669
5670 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5671 "JNZ skip\n\t"
5672 "MOV $dst, -1\n"
5673 "skip:\n\t"
5674 "NEG $dst\n\t"
5675 "ADD $dst, 31" %}
5676 ins_encode %{
5677 Register Rdst = $dst$$Register;
5678 Register Rsrc = $src$$Register;
5679 Label skip;
5680 __ bsrl(Rdst, Rsrc);
5681 __ jccb(Assembler::notZero, skip);
5682 __ movl(Rdst, -1);
5683 __ bind(skip);
5684 __ negl(Rdst);
5685 __ addl(Rdst, BitsPerInt - 1);
5686 %}
5687 ins_pipe(ialu_reg);
5688 %}
5689
5690 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5691 predicate(UseCountLeadingZerosInstruction);
5692 match(Set dst (CountLeadingZerosL src));
5693 effect(TEMP dst, KILL cr);
5694
5695 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5696 "JNC done\n\t"
5697 "LZCNT $dst, $src.lo\n\t"
5698 "ADD $dst, 32\n"
5699 "done:" %}
5700 ins_encode %{
5701 Register Rdst = $dst$$Register;
5702 Register Rsrc = $src$$Register;
5703 Label done;
5704 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5705 __ jccb(Assembler::carryClear, done);
5706 __ lzcntl(Rdst, Rsrc);
5707 __ addl(Rdst, BitsPerInt);
5708 __ bind(done);
5709 %}
5710 ins_pipe(ialu_reg);
5711 %}
5712
5713 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
5714 predicate(!UseCountLeadingZerosInstruction);
5715 match(Set dst (CountLeadingZerosL src));
5716 effect(TEMP dst, KILL cr);
5717
5718 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5719 "JZ msw_is_zero\n\t"
5720 "ADD $dst, 32\n\t"
5721 "JMP not_zero\n"
5722 "msw_is_zero:\n\t"
5723 "BSR $dst, $src.lo\n\t"
5724 "JNZ not_zero\n\t"
5725 "MOV $dst, -1\n"
5726 "not_zero:\n\t"
5727 "NEG $dst\n\t"
5728 "ADD $dst, 63\n" %}
5729 ins_encode %{
5730 Register Rdst = $dst$$Register;
5731 Register Rsrc = $src$$Register;
5732 Label msw_is_zero;
5733 Label not_zero;
5734 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5735 __ jccb(Assembler::zero, msw_is_zero);
5736 __ addl(Rdst, BitsPerInt);
5737 __ jmpb(not_zero);
5738 __ bind(msw_is_zero);
5739 __ bsrl(Rdst, Rsrc);
5740 __ jccb(Assembler::notZero, not_zero);
5741 __ movl(Rdst, -1);
5742 __ bind(not_zero);
5743 __ negl(Rdst);
5744 __ addl(Rdst, BitsPerLong - 1);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5750 match(Set dst (CountTrailingZerosI src));
5751 effect(KILL cr);
5752
5753 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5754 "JNZ done\n\t"
5755 "MOV $dst, 32\n"
5756 "done:" %}
5757 ins_encode %{
5758 Register Rdst = $dst$$Register;
5759 Label done;
5760 __ bsfl(Rdst, $src$$Register);
5761 __ jccb(Assembler::notZero, done);
5762 __ movl(Rdst, BitsPerInt);
5763 __ bind(done);
5764 %}
5765 ins_pipe(ialu_reg);
5766 %}
5767
5768 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5769 match(Set dst (CountTrailingZerosL src));
5770 effect(TEMP dst, KILL cr);
5771
5772 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5773 "JNZ done\n\t"
5774 "BSF $dst, $src.hi\n\t"
5775 "JNZ msw_not_zero\n\t"
5776 "MOV $dst, 32\n"
5777 "msw_not_zero:\n\t"
5778 "ADD $dst, 32\n"
5779 "done:" %}
5780 ins_encode %{
5781 Register Rdst = $dst$$Register;
5782 Register Rsrc = $src$$Register;
5783 Label msw_not_zero;
5784 Label done;
5785 __ bsfl(Rdst, Rsrc);
5786 __ jccb(Assembler::notZero, done);
5787 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5788 __ jccb(Assembler::notZero, msw_not_zero);
5789 __ movl(Rdst, BitsPerInt);
5790 __ bind(msw_not_zero);
5791 __ addl(Rdst, BitsPerInt);
5792 __ bind(done);
5793 %}
5794 ins_pipe(ialu_reg);
5795 %}
5796
5797
5798 //---------- Population Count Instructions -------------------------------------
5799
5800 instruct popCountI(eRegI dst, eRegI src) %{
5801 predicate(UsePopCountInstruction);
5802 match(Set dst (PopCountI src));
5803
5804 format %{ "POPCNT $dst, $src" %}
5805 ins_encode %{
5806 __ popcntl($dst$$Register, $src$$Register);
5807 %}
5808 ins_pipe(ialu_reg);
5809 %}
5810
5811 instruct popCountI_mem(eRegI dst, memory mem) %{
5812 predicate(UsePopCountInstruction);
5813 match(Set dst (PopCountI (LoadI mem)));
5814
5815 format %{ "POPCNT $dst, $mem" %}
5816 ins_encode %{
5817 __ popcntl($dst$$Register, $mem$$Address);
5818 %}
5819 ins_pipe(ialu_reg);
5820 %}
5821
5822 // Note: Long.bitCount(long) returns an int.
5823 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
5824 predicate(UsePopCountInstruction);
5825 match(Set dst (PopCountL src));
5826 effect(KILL cr, TEMP tmp, TEMP dst);
5827
5828 format %{ "POPCNT $dst, $src.lo\n\t"
5829 "POPCNT $tmp, $src.hi\n\t"
5830 "ADD $dst, $tmp" %}
5831 ins_encode %{
5832 __ popcntl($dst$$Register, $src$$Register);
5833 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5834 __ addl($dst$$Register, $tmp$$Register);
5835 %}
5836 ins_pipe(ialu_reg);
5837 %}
5838
5839 // Note: Long.bitCount(long) returns an int.
5840 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
5841 predicate(UsePopCountInstruction);
5842 match(Set dst (PopCountL (LoadL mem)));
5843 effect(KILL cr, TEMP tmp, TEMP dst);
5844
5845 format %{ "POPCNT $dst, $mem\n\t"
5846 "POPCNT $tmp, $mem+4\n\t"
5847 "ADD $dst, $tmp" %}
5848 ins_encode %{
5849 //__ popcntl($dst$$Register, $mem$$Address$$first);
5850 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5851 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5852 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5853 __ addl($dst$$Register, $tmp$$Register);
5854 %}
5855 ins_pipe(ialu_reg);
5856 %}
5857
5858
5859 //----------Load/Store/Move Instructions---------------------------------------
5860 //----------Load Instructions--------------------------------------------------
5861 // Load Byte (8bit signed)
5862 instruct loadB(xRegI dst, memory mem) %{
5863 match(Set dst (LoadB mem));
5864
5865 ins_cost(125);
5866 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5867
5868 ins_encode %{
5869 __ movsbl($dst$$Register, $mem$$Address);
5870 %}
5871
5872 ins_pipe(ialu_reg_mem);
5873 %}
5874
5875 // Load Byte (8bit signed) into Long Register
5876 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5877 match(Set dst (ConvI2L (LoadB mem)));
5878 effect(KILL cr);
5879
5880 ins_cost(375);
5881 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5882 "MOV $dst.hi,$dst.lo\n\t"
5883 "SAR $dst.hi,7" %}
5884
5885 ins_encode %{
5886 __ movsbl($dst$$Register, $mem$$Address);
5887 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5888 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5889 %}
5890
5891 ins_pipe(ialu_reg_mem);
5892 %}
5893
5894 // Load Unsigned Byte (8bit UNsigned)
5895 instruct loadUB(xRegI dst, memory mem) %{
5896 match(Set dst (LoadUB mem));
5897
5898 ins_cost(125);
5899 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5900
5901 ins_encode %{
5902 __ movzbl($dst$$Register, $mem$$Address);
5903 %}
5904
5905 ins_pipe(ialu_reg_mem);
5906 %}
5907
5908 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5909 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5910 match(Set dst (ConvI2L (LoadUB mem)));
5911 effect(KILL cr);
5912
5913 ins_cost(250);
5914 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5915 "XOR $dst.hi,$dst.hi" %}
5916
5917 ins_encode %{
5918 Register Rdst = $dst$$Register;
5919 __ movzbl(Rdst, $mem$$Address);
5920 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5921 %}
5922
5923 ins_pipe(ialu_reg_mem);
5924 %}
5925
5926 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5927 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5928 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5929 effect(KILL cr);
5930
5931 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5932 "XOR $dst.hi,$dst.hi\n\t"
5933 "AND $dst.lo,$mask" %}
5934 ins_encode %{
5935 Register Rdst = $dst$$Register;
5936 __ movzbl(Rdst, $mem$$Address);
5937 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5938 __ andl(Rdst, $mask$$constant);
5939 %}
5940 ins_pipe(ialu_reg_mem);
5941 %}
5942
5943 // Load Short (16bit signed)
5944 instruct loadS(eRegI dst, memory mem) %{
5945 match(Set dst (LoadS mem));
5946
5947 ins_cost(125);
5948 format %{ "MOVSX $dst,$mem\t# short" %}
5949
5950 ins_encode %{
5951 __ movswl($dst$$Register, $mem$$Address);
5952 %}
5953
5954 ins_pipe(ialu_reg_mem);
5955 %}
5956
5957 // Load Short (16 bit signed) to Byte (8 bit signed)
5958 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5959 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5960
5961 ins_cost(125);
5962 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5963 ins_encode %{
5964 __ movsbl($dst$$Register, $mem$$Address);
5965 %}
5966 ins_pipe(ialu_reg_mem);
5967 %}
5968
5969 // Load Short (16bit signed) into Long Register
5970 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5971 match(Set dst (ConvI2L (LoadS mem)));
5972 effect(KILL cr);
5973
5974 ins_cost(375);
5975 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5976 "MOV $dst.hi,$dst.lo\n\t"
5977 "SAR $dst.hi,15" %}
5978
5979 ins_encode %{
5980 __ movswl($dst$$Register, $mem$$Address);
5981 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5982 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5983 %}
5984
5985 ins_pipe(ialu_reg_mem);
5986 %}
5987
5988 // Load Unsigned Short/Char (16bit unsigned)
5989 instruct loadUS(eRegI dst, memory mem) %{
5990 match(Set dst (LoadUS mem));
5991
5992 ins_cost(125);
5993 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5994
5995 ins_encode %{
5996 __ movzwl($dst$$Register, $mem$$Address);
5997 %}
5998
5999 ins_pipe(ialu_reg_mem);
6000 %}
6001
6002 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6003 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6004 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6005
6006 ins_cost(125);
6007 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6008 ins_encode %{
6009 __ movsbl($dst$$Register, $mem$$Address);
6010 %}
6011 ins_pipe(ialu_reg_mem);
6012 %}
6013
6014 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6015 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6016 match(Set dst (ConvI2L (LoadUS mem)));
6017 effect(KILL cr);
6018
6019 ins_cost(250);
6020 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6021 "XOR $dst.hi,$dst.hi" %}
6022
6023 ins_encode %{
6024 __ movzwl($dst$$Register, $mem$$Address);
6025 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6026 %}
6027
6028 ins_pipe(ialu_reg_mem);
6029 %}
6030
6031 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6032 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6033 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6034 effect(KILL cr);
6035
6036 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6037 "XOR $dst.hi,$dst.hi" %}
6038 ins_encode %{
6039 Register Rdst = $dst$$Register;
6040 __ movzbl(Rdst, $mem$$Address);
6041 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6042 %}
6043 ins_pipe(ialu_reg_mem);
6044 %}
6045
6046 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6047 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6048 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6049 effect(KILL cr);
6050
6051 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6052 "XOR $dst.hi,$dst.hi\n\t"
6053 "AND $dst.lo,$mask" %}
6054 ins_encode %{
6055 Register Rdst = $dst$$Register;
6056 __ movzwl(Rdst, $mem$$Address);
6057 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6058 __ andl(Rdst, $mask$$constant);
6059 %}
6060 ins_pipe(ialu_reg_mem);
6061 %}
6062
6063 // Load Integer
6064 instruct loadI(eRegI dst, memory mem) %{
6065 match(Set dst (LoadI mem));
6066
6067 ins_cost(125);
6068 format %{ "MOV $dst,$mem\t# int" %}
6069
6070 ins_encode %{
6071 __ movl($dst$$Register, $mem$$Address);
6072 %}
6073
6074 ins_pipe(ialu_reg_mem);
6075 %}
6076
6077 // Load Integer (32 bit signed) to Byte (8 bit signed)
6078 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6079 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6080
6081 ins_cost(125);
6082 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6083 ins_encode %{
6084 __ movsbl($dst$$Register, $mem$$Address);
6085 %}
6086 ins_pipe(ialu_reg_mem);
6087 %}
6088
6089 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6090 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6091 match(Set dst (AndI (LoadI mem) mask));
6092
6093 ins_cost(125);
6094 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6095 ins_encode %{
6096 __ movzbl($dst$$Register, $mem$$Address);
6097 %}
6098 ins_pipe(ialu_reg_mem);
6099 %}
6100
6101 // Load Integer (32 bit signed) to Short (16 bit signed)
6102 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6103 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6104
6105 ins_cost(125);
6106 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6107 ins_encode %{
6108 __ movswl($dst$$Register, $mem$$Address);
6109 %}
6110 ins_pipe(ialu_reg_mem);
6111 %}
6112
6113 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6114 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6115 match(Set dst (AndI (LoadI mem) mask));
6116
6117 ins_cost(125);
6118 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6119 ins_encode %{
6120 __ movzwl($dst$$Register, $mem$$Address);
6121 %}
6122 ins_pipe(ialu_reg_mem);
6123 %}
6124
6125 // Load Integer into Long Register
6126 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6127 match(Set dst (ConvI2L (LoadI mem)));
6128 effect(KILL cr);
6129
6130 ins_cost(375);
6131 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6132 "MOV $dst.hi,$dst.lo\n\t"
6133 "SAR $dst.hi,31" %}
6134
6135 ins_encode %{
6136 __ movl($dst$$Register, $mem$$Address);
6137 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6138 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6139 %}
6140
6141 ins_pipe(ialu_reg_mem);
6142 %}
6143
6144 // Load Integer with mask 0xFF into Long Register
6145 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6146 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6147 effect(KILL cr);
6148
6149 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6150 "XOR $dst.hi,$dst.hi" %}
6151 ins_encode %{
6152 Register Rdst = $dst$$Register;
6153 __ movzbl(Rdst, $mem$$Address);
6154 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6155 %}
6156 ins_pipe(ialu_reg_mem);
6157 %}
6158
6159 // Load Integer with mask 0xFFFF into Long Register
6160 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6161 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6162 effect(KILL cr);
6163
6164 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6165 "XOR $dst.hi,$dst.hi" %}
6166 ins_encode %{
6167 Register Rdst = $dst$$Register;
6168 __ movzwl(Rdst, $mem$$Address);
6169 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6170 %}
6171 ins_pipe(ialu_reg_mem);
6172 %}
6173
6174 // Load Integer with 32-bit mask into Long Register
6175 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6176 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6177 effect(KILL cr);
6178
6179 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6180 "XOR $dst.hi,$dst.hi\n\t"
6181 "AND $dst.lo,$mask" %}
6182 ins_encode %{
6183 Register Rdst = $dst$$Register;
6184 __ movl(Rdst, $mem$$Address);
6185 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6186 __ andl(Rdst, $mask$$constant);
6187 %}
6188 ins_pipe(ialu_reg_mem);
6189 %}
6190
6191 // Load Unsigned Integer into Long Register
6192 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6193 match(Set dst (LoadUI2L mem));
6194 effect(KILL cr);
6195
6196 ins_cost(250);
6197 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6198 "XOR $dst.hi,$dst.hi" %}
6199
6200 ins_encode %{
6201 __ movl($dst$$Register, $mem$$Address);
6202 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6203 %}
6204
6205 ins_pipe(ialu_reg_mem);
6206 %}
6207
6208 // Load Long. Cannot clobber address while loading, so restrict address
6209 // register to ESI
6210 instruct loadL(eRegL dst, load_long_memory mem) %{
6211 predicate(!((LoadLNode*)n)->require_atomic_access());
6212 match(Set dst (LoadL mem));
6213
6214 ins_cost(250);
6215 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6216 "MOV $dst.hi,$mem+4" %}
6217
6218 ins_encode %{
6219 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6220 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6221 __ movl($dst$$Register, Amemlo);
6222 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6223 %}
6224
6225 ins_pipe(ialu_reg_long_mem);
6226 %}
6227
6228 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6229 // then store it down to the stack and reload on the int
6230 // side.
6231 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6232 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6233 match(Set dst (LoadL mem));
6234
6235 ins_cost(200);
6236 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6237 "FISTp $dst" %}
6238 ins_encode(enc_loadL_volatile(mem,dst));
6239 ins_pipe( fpu_reg_mem );
6240 %}
6241
6242 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6243 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6244 match(Set dst (LoadL mem));
6245 effect(TEMP tmp);
6246 ins_cost(180);
6247 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6248 "MOVSD $dst,$tmp" %}
6249 ins_encode %{
6250 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6251 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6252 %}
6253 ins_pipe( pipe_slow );
6254 %}
6255
6256 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6257 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6258 match(Set dst (LoadL mem));
6259 effect(TEMP tmp);
6260 ins_cost(160);
6261 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6262 "MOVD $dst.lo,$tmp\n\t"
6263 "PSRLQ $tmp,32\n\t"
6264 "MOVD $dst.hi,$tmp" %}
6265 ins_encode %{
6266 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6267 __ movdl($dst$$Register, $tmp$$XMMRegister);
6268 __ psrlq($tmp$$XMMRegister, 32);
6269 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6270 %}
6271 ins_pipe( pipe_slow );
6272 %}
6273
6274 // Load Range
6275 instruct loadRange(eRegI dst, memory mem) %{
6276 match(Set dst (LoadRange mem));
6277
6278 ins_cost(125);
6279 format %{ "MOV $dst,$mem" %}
6280 opcode(0x8B);
6281 ins_encode( OpcP, RegMem(dst,mem));
6282 ins_pipe( ialu_reg_mem );
6283 %}
6284
6285
6286 // Load Pointer
6287 instruct loadP(eRegP dst, memory mem) %{
6288 match(Set dst (LoadP mem));
6289
6290 ins_cost(125);
6291 format %{ "MOV $dst,$mem" %}
6292 opcode(0x8B);
6293 ins_encode( OpcP, RegMem(dst,mem));
6294 ins_pipe( ialu_reg_mem );
6295 %}
6296
6297 // Load Klass Pointer
6298 instruct loadKlass(eRegP dst, memory mem) %{
6299 match(Set dst (LoadKlass mem));
6300
6301 ins_cost(125);
6302 format %{ "MOV $dst,$mem" %}
6303 opcode(0x8B);
6304 ins_encode( OpcP, RegMem(dst,mem));
6305 ins_pipe( ialu_reg_mem );
6306 %}
6307
6308 // Load Double
6309 instruct loadDPR(regDPR dst, memory mem) %{
6310 predicate(UseSSE<=1);
6311 match(Set dst (LoadD mem));
6312
6313 ins_cost(150);
6314 format %{ "FLD_D ST,$mem\n\t"
6315 "FSTP $dst" %}
6316 opcode(0xDD); /* DD /0 */
6317 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6318 Pop_Reg_DPR(dst) );
6319 ins_pipe( fpu_reg_mem );
6320 %}
6321
6322 // Load Double to XMM
6323 instruct loadD(regD dst, memory mem) %{
6324 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6325 match(Set dst (LoadD mem));
6326 ins_cost(145);
6327 format %{ "MOVSD $dst,$mem" %}
6328 ins_encode %{
6329 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6330 %}
6331 ins_pipe( pipe_slow );
6332 %}
6333
6334 instruct loadD_partial(regD dst, memory mem) %{
6335 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6336 match(Set dst (LoadD mem));
6337 ins_cost(145);
6338 format %{ "MOVLPD $dst,$mem" %}
6339 ins_encode %{
6340 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6341 %}
6342 ins_pipe( pipe_slow );
6343 %}
6344
6345 // Load to XMM register (single-precision floating point)
6346 // MOVSS instruction
6347 instruct loadF(regF dst, memory mem) %{
6348 predicate(UseSSE>=1);
6349 match(Set dst (LoadF mem));
6350 ins_cost(145);
6351 format %{ "MOVSS $dst,$mem" %}
6352 ins_encode %{
6353 __ movflt ($dst$$XMMRegister, $mem$$Address);
6354 %}
6355 ins_pipe( pipe_slow );
6356 %}
6357
6358 // Load Float
6359 instruct loadFPR(regFPR dst, memory mem) %{
6360 predicate(UseSSE==0);
6361 match(Set dst (LoadF mem));
6362
6363 ins_cost(150);
6364 format %{ "FLD_S ST,$mem\n\t"
6365 "FSTP $dst" %}
6366 opcode(0xD9); /* D9 /0 */
6367 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6368 Pop_Reg_FPR(dst) );
6369 ins_pipe( fpu_reg_mem );
6370 %}
6371
6372 // Load Aligned Packed Byte to XMM register
6373 instruct loadA8B(regD dst, memory mem) %{
6374 predicate(UseSSE>=1);
6375 match(Set dst (Load8B mem));
6376 ins_cost(125);
6377 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6378 ins_encode %{
6379 __ movq($dst$$XMMRegister, $mem$$Address);
6380 %}
6381 ins_pipe( pipe_slow );
6382 %}
6383
6384 // Load Aligned Packed Short to XMM register
6385 instruct loadA4S(regD dst, memory mem) %{
6386 predicate(UseSSE>=1);
6387 match(Set dst (Load4S mem));
6388 ins_cost(125);
6389 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6390 ins_encode %{
6391 __ movq($dst$$XMMRegister, $mem$$Address);
6392 %}
6393 ins_pipe( pipe_slow );
6394 %}
6395
6396 // Load Aligned Packed Char to XMM register
6397 instruct loadA4C(regD dst, memory mem) %{
6398 predicate(UseSSE>=1);
6399 match(Set dst (Load4C mem));
6400 ins_cost(125);
6401 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6402 ins_encode %{
6403 __ movq($dst$$XMMRegister, $mem$$Address);
6404 %}
6405 ins_pipe( pipe_slow );
6406 %}
6407
6408 // Load Aligned Packed Integer to XMM register
6409 instruct load2IU(regD dst, memory mem) %{
6410 predicate(UseSSE>=1);
6411 match(Set dst (Load2I mem));
6412 ins_cost(125);
6413 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6414 ins_encode %{
6415 __ movq($dst$$XMMRegister, $mem$$Address);
6416 %}
6417 ins_pipe( pipe_slow );
6418 %}
6419
6420 // Load Aligned Packed Single to XMM
6421 instruct loadA2F(regD dst, memory mem) %{
6422 predicate(UseSSE>=1);
6423 match(Set dst (Load2F mem));
6424 ins_cost(145);
6425 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6426 ins_encode %{
6427 __ movq($dst$$XMMRegister, $mem$$Address);
6428 %}
6429 ins_pipe( pipe_slow );
6430 %}
6431
6432 // Load Effective Address
6433 instruct leaP8(eRegP dst, indOffset8 mem) %{
6434 match(Set dst mem);
6435
6436 ins_cost(110);
6437 format %{ "LEA $dst,$mem" %}
6438 opcode(0x8D);
6439 ins_encode( OpcP, RegMem(dst,mem));
6440 ins_pipe( ialu_reg_reg_fat );
6441 %}
6442
6443 instruct leaP32(eRegP dst, indOffset32 mem) %{
6444 match(Set dst mem);
6445
6446 ins_cost(110);
6447 format %{ "LEA $dst,$mem" %}
6448 opcode(0x8D);
6449 ins_encode( OpcP, RegMem(dst,mem));
6450 ins_pipe( ialu_reg_reg_fat );
6451 %}
6452
6453 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6454 match(Set dst mem);
6455
6456 ins_cost(110);
6457 format %{ "LEA $dst,$mem" %}
6458 opcode(0x8D);
6459 ins_encode( OpcP, RegMem(dst,mem));
6460 ins_pipe( ialu_reg_reg_fat );
6461 %}
6462
6463 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6464 match(Set dst mem);
6465
6466 ins_cost(110);
6467 format %{ "LEA $dst,$mem" %}
6468 opcode(0x8D);
6469 ins_encode( OpcP, RegMem(dst,mem));
6470 ins_pipe( ialu_reg_reg_fat );
6471 %}
6472
6473 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6474 match(Set dst mem);
6475
6476 ins_cost(110);
6477 format %{ "LEA $dst,$mem" %}
6478 opcode(0x8D);
6479 ins_encode( OpcP, RegMem(dst,mem));
6480 ins_pipe( ialu_reg_reg_fat );
6481 %}
6482
6483 // Load Constant
6484 instruct loadConI(eRegI dst, immI src) %{
6485 match(Set dst src);
6486
6487 format %{ "MOV $dst,$src" %}
6488 ins_encode( LdImmI(dst, src) );
6489 ins_pipe( ialu_reg_fat );
6490 %}
6491
6492 // Load Constant zero
6493 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6494 match(Set dst src);
6495 effect(KILL cr);
6496
6497 ins_cost(50);
6498 format %{ "XOR $dst,$dst" %}
6499 opcode(0x33); /* + rd */
6500 ins_encode( OpcP, RegReg( dst, dst ) );
6501 ins_pipe( ialu_reg );
6502 %}
6503
6504 instruct loadConP(eRegP dst, immP src) %{
6505 match(Set dst src);
6506
6507 format %{ "MOV $dst,$src" %}
6508 opcode(0xB8); /* + rd */
6509 ins_encode( LdImmP(dst, src) );
6510 ins_pipe( ialu_reg_fat );
6511 %}
6512
6513 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6514 match(Set dst src);
6515 effect(KILL cr);
6516 ins_cost(200);
6517 format %{ "MOV $dst.lo,$src.lo\n\t"
6518 "MOV $dst.hi,$src.hi" %}
6519 opcode(0xB8);
6520 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6521 ins_pipe( ialu_reg_long_fat );
6522 %}
6523
6524 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6525 match(Set dst src);
6526 effect(KILL cr);
6527 ins_cost(150);
6528 format %{ "XOR $dst.lo,$dst.lo\n\t"
6529 "XOR $dst.hi,$dst.hi" %}
6530 opcode(0x33,0x33);
6531 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6532 ins_pipe( ialu_reg_long );
6533 %}
6534
6535 // The instruction usage is guarded by predicate in operand immFPR().
6536 instruct loadConFPR(regFPR dst, immFPR con) %{
6537 match(Set dst con);
6538 ins_cost(125);
6539 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6540 "FSTP $dst" %}
6541 ins_encode %{
6542 __ fld_s($constantaddress($con));
6543 __ fstp_d($dst$$reg);
6544 %}
6545 ins_pipe(fpu_reg_con);
6546 %}
6547
6548 // The instruction usage is guarded by predicate in operand immFPR0().
6549 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6550 match(Set dst con);
6551 ins_cost(125);
6552 format %{ "FLDZ ST\n\t"
6553 "FSTP $dst" %}
6554 ins_encode %{
6555 __ fldz();
6556 __ fstp_d($dst$$reg);
6557 %}
6558 ins_pipe(fpu_reg_con);
6559 %}
6560
6561 // The instruction usage is guarded by predicate in operand immFPR1().
6562 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6563 match(Set dst con);
6564 ins_cost(125);
6565 format %{ "FLD1 ST\n\t"
6566 "FSTP $dst" %}
6567 ins_encode %{
6568 __ fld1();
6569 __ fstp_d($dst$$reg);
6570 %}
6571 ins_pipe(fpu_reg_con);
6572 %}
6573
6574 // The instruction usage is guarded by predicate in operand immF().
6575 instruct loadConF(regF dst, immF con) %{
6576 match(Set dst con);
6577 ins_cost(125);
6578 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6579 ins_encode %{
6580 __ movflt($dst$$XMMRegister, $constantaddress($con));
6581 %}
6582 ins_pipe(pipe_slow);
6583 %}
6584
6585 // The instruction usage is guarded by predicate in operand immF0().
6586 instruct loadConF0(regF dst, immF0 src) %{
6587 match(Set dst src);
6588 ins_cost(100);
6589 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6590 ins_encode %{
6591 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6592 %}
6593 ins_pipe(pipe_slow);
6594 %}
6595
6596 // The instruction usage is guarded by predicate in operand immDPR().
6597 instruct loadConDPR(regDPR dst, immDPR con) %{
6598 match(Set dst con);
6599 ins_cost(125);
6600
6601 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6602 "FSTP $dst" %}
6603 ins_encode %{
6604 __ fld_d($constantaddress($con));
6605 __ fstp_d($dst$$reg);
6606 %}
6607 ins_pipe(fpu_reg_con);
6608 %}
6609
6610 // The instruction usage is guarded by predicate in operand immDPR0().
6611 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6612 match(Set dst con);
6613 ins_cost(125);
6614
6615 format %{ "FLDZ ST\n\t"
6616 "FSTP $dst" %}
6617 ins_encode %{
6618 __ fldz();
6619 __ fstp_d($dst$$reg);
6620 %}
6621 ins_pipe(fpu_reg_con);
6622 %}
6623
6624 // The instruction usage is guarded by predicate in operand immDPR1().
6625 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6626 match(Set dst con);
6627 ins_cost(125);
6628
6629 format %{ "FLD1 ST\n\t"
6630 "FSTP $dst" %}
6631 ins_encode %{
6632 __ fld1();
6633 __ fstp_d($dst$$reg);
6634 %}
6635 ins_pipe(fpu_reg_con);
6636 %}
6637
6638 // The instruction usage is guarded by predicate in operand immD().
6639 instruct loadConD(regD dst, immD con) %{
6640 match(Set dst con);
6641 ins_cost(125);
6642 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6643 ins_encode %{
6644 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6645 %}
6646 ins_pipe(pipe_slow);
6647 %}
6648
6649 // The instruction usage is guarded by predicate in operand immD0().
6650 instruct loadConD0(regD dst, immD0 src) %{
6651 match(Set dst src);
6652 ins_cost(100);
6653 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6654 ins_encode %{
6655 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6656 %}
6657 ins_pipe( pipe_slow );
6658 %}
6659
6660 // Load Stack Slot
6661 instruct loadSSI(eRegI dst, stackSlotI src) %{
6662 match(Set dst src);
6663 ins_cost(125);
6664
6665 format %{ "MOV $dst,$src" %}
6666 opcode(0x8B);
6667 ins_encode( OpcP, RegMem(dst,src));
6668 ins_pipe( ialu_reg_mem );
6669 %}
6670
6671 instruct loadSSL(eRegL dst, stackSlotL src) %{
6672 match(Set dst src);
6673
6674 ins_cost(200);
6675 format %{ "MOV $dst,$src.lo\n\t"
6676 "MOV $dst+4,$src.hi" %}
6677 opcode(0x8B, 0x8B);
6678 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6679 ins_pipe( ialu_mem_long_reg );
6680 %}
6681
6682 // Load Stack Slot
6683 instruct loadSSP(eRegP dst, stackSlotP src) %{
6684 match(Set dst src);
6685 ins_cost(125);
6686
6687 format %{ "MOV $dst,$src" %}
6688 opcode(0x8B);
6689 ins_encode( OpcP, RegMem(dst,src));
6690 ins_pipe( ialu_reg_mem );
6691 %}
6692
6693 // Load Stack Slot
6694 instruct loadSSF(regFPR dst, stackSlotF src) %{
6695 match(Set dst src);
6696 ins_cost(125);
6697
6698 format %{ "FLD_S $src\n\t"
6699 "FSTP $dst" %}
6700 opcode(0xD9); /* D9 /0, FLD m32real */
6701 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6702 Pop_Reg_FPR(dst) );
6703 ins_pipe( fpu_reg_mem );
6704 %}
6705
6706 // Load Stack Slot
6707 instruct loadSSD(regDPR dst, stackSlotD src) %{
6708 match(Set dst src);
6709 ins_cost(125);
6710
6711 format %{ "FLD_D $src\n\t"
6712 "FSTP $dst" %}
6713 opcode(0xDD); /* DD /0, FLD m64real */
6714 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6715 Pop_Reg_DPR(dst) );
6716 ins_pipe( fpu_reg_mem );
6717 %}
6718
6719 // Prefetch instructions.
6720 // Must be safe to execute with invalid address (cannot fault).
6721
6722 instruct prefetchr0( memory mem ) %{
6723 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6724 match(PrefetchRead mem);
6725 ins_cost(0);
6726 size(0);
6727 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6728 ins_encode();
6729 ins_pipe(empty);
6730 %}
6731
6732 instruct prefetchr( memory mem ) %{
6733 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6734 match(PrefetchRead mem);
6735 ins_cost(100);
6736
6737 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6738 ins_encode %{
6739 __ prefetchr($mem$$Address);
6740 %}
6741 ins_pipe(ialu_mem);
6742 %}
6743
6744 instruct prefetchrNTA( memory mem ) %{
6745 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6746 match(PrefetchRead mem);
6747 ins_cost(100);
6748
6749 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6750 ins_encode %{
6751 __ prefetchnta($mem$$Address);
6752 %}
6753 ins_pipe(ialu_mem);
6754 %}
6755
6756 instruct prefetchrT0( memory mem ) %{
6757 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6758 match(PrefetchRead mem);
6759 ins_cost(100);
6760
6761 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6762 ins_encode %{
6763 __ prefetcht0($mem$$Address);
6764 %}
6765 ins_pipe(ialu_mem);
6766 %}
6767
6768 instruct prefetchrT2( memory mem ) %{
6769 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6770 match(PrefetchRead mem);
6771 ins_cost(100);
6772
6773 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6774 ins_encode %{
6775 __ prefetcht2($mem$$Address);
6776 %}
6777 ins_pipe(ialu_mem);
6778 %}
6779
6780 instruct prefetchw0( memory mem ) %{
6781 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6782 match(PrefetchWrite mem);
6783 ins_cost(0);
6784 size(0);
6785 format %{ "Prefetch (non-SSE is empty encoding)" %}
6786 ins_encode();
6787 ins_pipe(empty);
6788 %}
6789
6790 instruct prefetchw( memory mem ) %{
6791 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6792 match( PrefetchWrite mem );
6793 ins_cost(100);
6794
6795 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6796 ins_encode %{
6797 __ prefetchw($mem$$Address);
6798 %}
6799 ins_pipe(ialu_mem);
6800 %}
6801
6802 instruct prefetchwNTA( memory mem ) %{
6803 predicate(UseSSE>=1);
6804 match(PrefetchWrite mem);
6805 ins_cost(100);
6806
6807 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6808 ins_encode %{
6809 __ prefetchnta($mem$$Address);
6810 %}
6811 ins_pipe(ialu_mem);
6812 %}
6813
6814 // Prefetch instructions for allocation.
6815
6816 instruct prefetchAlloc0( memory mem ) %{
6817 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6818 match(PrefetchAllocation mem);
6819 ins_cost(0);
6820 size(0);
6821 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6822 ins_encode();
6823 ins_pipe(empty);
6824 %}
6825
6826 instruct prefetchAlloc( memory mem ) %{
6827 predicate(AllocatePrefetchInstr==3);
6828 match( PrefetchAllocation mem );
6829 ins_cost(100);
6830
6831 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6832 ins_encode %{
6833 __ prefetchw($mem$$Address);
6834 %}
6835 ins_pipe(ialu_mem);
6836 %}
6837
6838 instruct prefetchAllocNTA( memory mem ) %{
6839 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6840 match(PrefetchAllocation mem);
6841 ins_cost(100);
6842
6843 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6844 ins_encode %{
6845 __ prefetchnta($mem$$Address);
6846 %}
6847 ins_pipe(ialu_mem);
6848 %}
6849
6850 instruct prefetchAllocT0( memory mem ) %{
6851 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6852 match(PrefetchAllocation mem);
6853 ins_cost(100);
6854
6855 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6856 ins_encode %{
6857 __ prefetcht0($mem$$Address);
6858 %}
6859 ins_pipe(ialu_mem);
6860 %}
6861
6862 instruct prefetchAllocT2( memory mem ) %{
6863 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6864 match(PrefetchAllocation mem);
6865 ins_cost(100);
6866
6867 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6868 ins_encode %{
6869 __ prefetcht2($mem$$Address);
6870 %}
6871 ins_pipe(ialu_mem);
6872 %}
6873
6874 //----------Store Instructions-------------------------------------------------
6875
6876 // Store Byte
6877 instruct storeB(memory mem, xRegI src) %{
6878 match(Set mem (StoreB mem src));
6879
6880 ins_cost(125);
6881 format %{ "MOV8 $mem,$src" %}
6882 opcode(0x88);
6883 ins_encode( OpcP, RegMem( src, mem ) );
6884 ins_pipe( ialu_mem_reg );
6885 %}
6886
6887 // Store Char/Short
6888 instruct storeC(memory mem, eRegI src) %{
6889 match(Set mem (StoreC mem src));
6890
6891 ins_cost(125);
6892 format %{ "MOV16 $mem,$src" %}
6893 opcode(0x89, 0x66);
6894 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6895 ins_pipe( ialu_mem_reg );
6896 %}
6897
6898 // Store Integer
6899 instruct storeI(memory mem, eRegI src) %{
6900 match(Set mem (StoreI mem src));
6901
6902 ins_cost(125);
6903 format %{ "MOV $mem,$src" %}
6904 opcode(0x89);
6905 ins_encode( OpcP, RegMem( src, mem ) );
6906 ins_pipe( ialu_mem_reg );
6907 %}
6908
6909 // Store Long
6910 instruct storeL(long_memory mem, eRegL src) %{
6911 predicate(!((StoreLNode*)n)->require_atomic_access());
6912 match(Set mem (StoreL mem src));
6913
6914 ins_cost(200);
6915 format %{ "MOV $mem,$src.lo\n\t"
6916 "MOV $mem+4,$src.hi" %}
6917 opcode(0x89, 0x89);
6918 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6919 ins_pipe( ialu_mem_long_reg );
6920 %}
6921
6922 // Store Long to Integer
6923 instruct storeL2I(memory mem, eRegL src) %{
6924 match(Set mem (StoreI mem (ConvL2I src)));
6925
6926 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6927 ins_encode %{
6928 __ movl($mem$$Address, $src$$Register);
6929 %}
6930 ins_pipe(ialu_mem_reg);
6931 %}
6932
6933 // Volatile Store Long. Must be atomic, so move it into
6934 // the FP TOS and then do a 64-bit FIST. Has to probe the
6935 // target address before the store (for null-ptr checks)
6936 // so the memory operand is used twice in the encoding.
6937 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6938 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6939 match(Set mem (StoreL mem src));
6940 effect( KILL cr );
6941 ins_cost(400);
6942 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6943 "FILD $src\n\t"
6944 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6945 opcode(0x3B);
6946 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6947 ins_pipe( fpu_reg_mem );
6948 %}
6949
6950 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6951 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6952 match(Set mem (StoreL mem src));
6953 effect( TEMP tmp, KILL cr );
6954 ins_cost(380);
6955 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6956 "MOVSD $tmp,$src\n\t"
6957 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6958 ins_encode %{
6959 __ cmpl(rax, $mem$$Address);
6960 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6961 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6962 %}
6963 ins_pipe( pipe_slow );
6964 %}
6965
6966 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6967 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6968 match(Set mem (StoreL mem src));
6969 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6970 ins_cost(360);
6971 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6972 "MOVD $tmp,$src.lo\n\t"
6973 "MOVD $tmp2,$src.hi\n\t"
6974 "PUNPCKLDQ $tmp,$tmp2\n\t"
6975 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6976 ins_encode %{
6977 __ cmpl(rax, $mem$$Address);
6978 __ movdl($tmp$$XMMRegister, $src$$Register);
6979 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6980 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6981 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6982 %}
6983 ins_pipe( pipe_slow );
6984 %}
6985
6986 // Store Pointer; for storing unknown oops and raw pointers
6987 instruct storeP(memory mem, anyRegP src) %{
6988 match(Set mem (StoreP mem src));
6989
6990 ins_cost(125);
6991 format %{ "MOV $mem,$src" %}
6992 opcode(0x89);
6993 ins_encode( OpcP, RegMem( src, mem ) );
6994 ins_pipe( ialu_mem_reg );
6995 %}
6996
6997 // Store Integer Immediate
6998 instruct storeImmI(memory mem, immI src) %{
6999 match(Set mem (StoreI mem src));
7000
7001 ins_cost(150);
7002 format %{ "MOV $mem,$src" %}
7003 opcode(0xC7); /* C7 /0 */
7004 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7005 ins_pipe( ialu_mem_imm );
7006 %}
7007
7008 // Store Short/Char Immediate
7009 instruct storeImmI16(memory mem, immI16 src) %{
7010 predicate(UseStoreImmI16);
7011 match(Set mem (StoreC mem src));
7012
7013 ins_cost(150);
7014 format %{ "MOV16 $mem,$src" %}
7015 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7016 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7017 ins_pipe( ialu_mem_imm );
7018 %}
7019
7020 // Store Pointer Immediate; null pointers or constant oops that do not
7021 // need card-mark barriers.
7022 instruct storeImmP(memory mem, immP src) %{
7023 match(Set mem (StoreP mem src));
7024
7025 ins_cost(150);
7026 format %{ "MOV $mem,$src" %}
7027 opcode(0xC7); /* C7 /0 */
7028 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7029 ins_pipe( ialu_mem_imm );
7030 %}
7031
7032 // Store Byte Immediate
7033 instruct storeImmB(memory mem, immI8 src) %{
7034 match(Set mem (StoreB mem src));
7035
7036 ins_cost(150);
7037 format %{ "MOV8 $mem,$src" %}
7038 opcode(0xC6); /* C6 /0 */
7039 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7040 ins_pipe( ialu_mem_imm );
7041 %}
7042
7043 // Store Aligned Packed Byte XMM register to memory
7044 instruct storeA8B(memory mem, regD src) %{
7045 predicate(UseSSE>=1);
7046 match(Set mem (Store8B mem src));
7047 ins_cost(145);
7048 format %{ "MOVQ $mem,$src\t! packed8B" %}
7049 ins_encode %{
7050 __ movq($mem$$Address, $src$$XMMRegister);
7051 %}
7052 ins_pipe( pipe_slow );
7053 %}
7054
7055 // Store Aligned Packed Char/Short XMM register to memory
7056 instruct storeA4C(memory mem, regD src) %{
7057 predicate(UseSSE>=1);
7058 match(Set mem (Store4C mem src));
7059 ins_cost(145);
7060 format %{ "MOVQ $mem,$src\t! packed4C" %}
7061 ins_encode %{
7062 __ movq($mem$$Address, $src$$XMMRegister);
7063 %}
7064 ins_pipe( pipe_slow );
7065 %}
7066
7067 // Store Aligned Packed Integer XMM register to memory
7068 instruct storeA2I(memory mem, regD src) %{
7069 predicate(UseSSE>=1);
7070 match(Set mem (Store2I mem src));
7071 ins_cost(145);
7072 format %{ "MOVQ $mem,$src\t! packed2I" %}
7073 ins_encode %{
7074 __ movq($mem$$Address, $src$$XMMRegister);
7075 %}
7076 ins_pipe( pipe_slow );
7077 %}
7078
7079 // Store CMS card-mark Immediate
7080 instruct storeImmCM(memory mem, immI8 src) %{
7081 match(Set mem (StoreCM mem src));
7082
7083 ins_cost(150);
7084 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7085 opcode(0xC6); /* C6 /0 */
7086 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7087 ins_pipe( ialu_mem_imm );
7088 %}
7089
7090 // Store Double
7091 instruct storeDPR( memory mem, regDPR1 src) %{
7092 predicate(UseSSE<=1);
7093 match(Set mem (StoreD mem src));
7094
7095 ins_cost(100);
7096 format %{ "FST_D $mem,$src" %}
7097 opcode(0xDD); /* DD /2 */
7098 ins_encode( enc_FPR_store(mem,src) );
7099 ins_pipe( fpu_mem_reg );
7100 %}
7101
7102 // Store double does rounding on x86
7103 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7104 predicate(UseSSE<=1);
7105 match(Set mem (StoreD mem (RoundDouble src)));
7106
7107 ins_cost(100);
7108 format %{ "FST_D $mem,$src\t# round" %}
7109 opcode(0xDD); /* DD /2 */
7110 ins_encode( enc_FPR_store(mem,src) );
7111 ins_pipe( fpu_mem_reg );
7112 %}
7113
7114 // Store XMM register to memory (double-precision floating points)
7115 // MOVSD instruction
7116 instruct storeD(memory mem, regD src) %{
7117 predicate(UseSSE>=2);
7118 match(Set mem (StoreD mem src));
7119 ins_cost(95);
7120 format %{ "MOVSD $mem,$src" %}
7121 ins_encode %{
7122 __ movdbl($mem$$Address, $src$$XMMRegister);
7123 %}
7124 ins_pipe( pipe_slow );
7125 %}
7126
7127 // Store XMM register to memory (single-precision floating point)
7128 // MOVSS instruction
7129 instruct storeF(memory mem, regF src) %{
7130 predicate(UseSSE>=1);
7131 match(Set mem (StoreF mem src));
7132 ins_cost(95);
7133 format %{ "MOVSS $mem,$src" %}
7134 ins_encode %{
7135 __ movflt($mem$$Address, $src$$XMMRegister);
7136 %}
7137 ins_pipe( pipe_slow );
7138 %}
7139
7140 // Store Aligned Packed Single Float XMM register to memory
7141 instruct storeA2F(memory mem, regD src) %{
7142 predicate(UseSSE>=1);
7143 match(Set mem (Store2F mem src));
7144 ins_cost(145);
7145 format %{ "MOVQ $mem,$src\t! packed2F" %}
7146 ins_encode %{
7147 __ movq($mem$$Address, $src$$XMMRegister);
7148 %}
7149 ins_pipe( pipe_slow );
7150 %}
7151
7152 // Store Float
7153 instruct storeFPR( memory mem, regFPR1 src) %{
7154 predicate(UseSSE==0);
7155 match(Set mem (StoreF mem src));
7156
7157 ins_cost(100);
7158 format %{ "FST_S $mem,$src" %}
7159 opcode(0xD9); /* D9 /2 */
7160 ins_encode( enc_FPR_store(mem,src) );
7161 ins_pipe( fpu_mem_reg );
7162 %}
7163
7164 // Store Float does rounding on x86
7165 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7166 predicate(UseSSE==0);
7167 match(Set mem (StoreF mem (RoundFloat src)));
7168
7169 ins_cost(100);
7170 format %{ "FST_S $mem,$src\t# round" %}
7171 opcode(0xD9); /* D9 /2 */
7172 ins_encode( enc_FPR_store(mem,src) );
7173 ins_pipe( fpu_mem_reg );
7174 %}
7175
7176 // Store Float does rounding on x86
7177 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7178 predicate(UseSSE<=1);
7179 match(Set mem (StoreF mem (ConvD2F src)));
7180
7181 ins_cost(100);
7182 format %{ "FST_S $mem,$src\t# D-round" %}
7183 opcode(0xD9); /* D9 /2 */
7184 ins_encode( enc_FPR_store(mem,src) );
7185 ins_pipe( fpu_mem_reg );
7186 %}
7187
7188 // Store immediate Float value (it is faster than store from FPU register)
7189 // The instruction usage is guarded by predicate in operand immFPR().
7190 instruct storeFPR_imm( memory mem, immFPR src) %{
7191 match(Set mem (StoreF mem src));
7192
7193 ins_cost(50);
7194 format %{ "MOV $mem,$src\t# store float" %}
7195 opcode(0xC7); /* C7 /0 */
7196 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7197 ins_pipe( ialu_mem_imm );
7198 %}
7199
7200 // Store immediate Float value (it is faster than store from XMM register)
7201 // The instruction usage is guarded by predicate in operand immF().
7202 instruct storeF_imm( memory mem, immF src) %{
7203 match(Set mem (StoreF mem src));
7204
7205 ins_cost(50);
7206 format %{ "MOV $mem,$src\t# store float" %}
7207 opcode(0xC7); /* C7 /0 */
7208 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7209 ins_pipe( ialu_mem_imm );
7210 %}
7211
7212 // Store Integer to stack slot
7213 instruct storeSSI(stackSlotI dst, eRegI src) %{
7214 match(Set dst src);
7215
7216 ins_cost(100);
7217 format %{ "MOV $dst,$src" %}
7218 opcode(0x89);
7219 ins_encode( OpcPRegSS( dst, src ) );
7220 ins_pipe( ialu_mem_reg );
7221 %}
7222
7223 // Store Integer to stack slot
7224 instruct storeSSP(stackSlotP dst, eRegP src) %{
7225 match(Set dst src);
7226
7227 ins_cost(100);
7228 format %{ "MOV $dst,$src" %}
7229 opcode(0x89);
7230 ins_encode( OpcPRegSS( dst, src ) );
7231 ins_pipe( ialu_mem_reg );
7232 %}
7233
7234 // Store Long to stack slot
7235 instruct storeSSL(stackSlotL dst, eRegL src) %{
7236 match(Set dst src);
7237
7238 ins_cost(200);
7239 format %{ "MOV $dst,$src.lo\n\t"
7240 "MOV $dst+4,$src.hi" %}
7241 opcode(0x89, 0x89);
7242 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7243 ins_pipe( ialu_mem_long_reg );
7244 %}
7245
7246 //----------MemBar Instructions-----------------------------------------------
7247 // Memory barrier flavors
7248
7249 instruct membar_acquire() %{
7250 match(MemBarAcquire);
7251 ins_cost(400);
7252
7253 size(0);
7254 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7255 ins_encode();
7256 ins_pipe(empty);
7257 %}
7258
7259 instruct membar_acquire_lock() %{
7260 match(MemBarAcquireLock);
7261 ins_cost(0);
7262
7263 size(0);
7264 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7265 ins_encode( );
7266 ins_pipe(empty);
7267 %}
7268
7269 instruct membar_release() %{
7270 match(MemBarRelease);
7271 ins_cost(400);
7272
7273 size(0);
7274 format %{ "MEMBAR-release ! (empty encoding)" %}
7275 ins_encode( );
7276 ins_pipe(empty);
7277 %}
7278
7279 instruct membar_release_lock() %{
7280 match(MemBarReleaseLock);
7281 ins_cost(0);
7282
7283 size(0);
7284 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7285 ins_encode( );
7286 ins_pipe(empty);
7287 %}
7288
7289 instruct membar_volatile(eFlagsReg cr) %{
7290 match(MemBarVolatile);
7291 effect(KILL cr);
7292 ins_cost(400);
7293
7294 format %{
7295 $$template
7296 if (os::is_MP()) {
7297 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7298 } else {
7299 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7300 }
7301 %}
7302 ins_encode %{
7303 __ membar(Assembler::StoreLoad);
7304 %}
7305 ins_pipe(pipe_slow);
7306 %}
7307
7308 instruct unnecessary_membar_volatile() %{
7309 match(MemBarVolatile);
7310 predicate(Matcher::post_store_load_barrier(n));
7311 ins_cost(0);
7312
7313 size(0);
7314 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7315 ins_encode( );
7316 ins_pipe(empty);
7317 %}
7318
7319 instruct membar_storestore() %{
7320 match(MemBarStoreStore);
7321 ins_cost(0);
7322
7323 size(0);
7324 format %{ "MEMBAR-storestore (empty encoding)" %}
7325 ins_encode( );
7326 ins_pipe(empty);
7327 %}
7328
7329 //----------Move Instructions--------------------------------------------------
7330 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7331 match(Set dst (CastX2P src));
7332 format %{ "# X2P $dst, $src" %}
7333 ins_encode( /*empty encoding*/ );
7334 ins_cost(0);
7335 ins_pipe(empty);
7336 %}
7337
7338 instruct castP2X(eRegI dst, eRegP src ) %{
7339 match(Set dst (CastP2X src));
7340 ins_cost(50);
7341 format %{ "MOV $dst, $src\t# CastP2X" %}
7342 ins_encode( enc_Copy( dst, src) );
7343 ins_pipe( ialu_reg_reg );
7344 %}
7345
7346 //----------Conditional Move---------------------------------------------------
7347 // Conditional move
7348 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7349 predicate(!VM_Version::supports_cmov() );
7350 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7351 ins_cost(200);
7352 format %{ "J$cop,us skip\t# signed cmove\n\t"
7353 "MOV $dst,$src\n"
7354 "skip:" %}
7355 ins_encode %{
7356 Label Lskip;
7357 // Invert sense of branch from sense of CMOV
7358 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7359 __ movl($dst$$Register, $src$$Register);
7360 __ bind(Lskip);
7361 %}
7362 ins_pipe( pipe_cmov_reg );
7363 %}
7364
7365 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7366 predicate(!VM_Version::supports_cmov() );
7367 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7368 ins_cost(200);
7369 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7370 "MOV $dst,$src\n"
7371 "skip:" %}
7372 ins_encode %{
7373 Label Lskip;
7374 // Invert sense of branch from sense of CMOV
7375 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7376 __ movl($dst$$Register, $src$$Register);
7377 __ bind(Lskip);
7378 %}
7379 ins_pipe( pipe_cmov_reg );
7380 %}
7381
7382 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7383 predicate(VM_Version::supports_cmov() );
7384 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7385 ins_cost(200);
7386 format %{ "CMOV$cop $dst,$src" %}
7387 opcode(0x0F,0x40);
7388 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7389 ins_pipe( pipe_cmov_reg );
7390 %}
7391
7392 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7393 predicate(VM_Version::supports_cmov() );
7394 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7395 ins_cost(200);
7396 format %{ "CMOV$cop $dst,$src" %}
7397 opcode(0x0F,0x40);
7398 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7399 ins_pipe( pipe_cmov_reg );
7400 %}
7401
7402 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7403 predicate(VM_Version::supports_cmov() );
7404 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7405 ins_cost(200);
7406 expand %{
7407 cmovI_regU(cop, cr, dst, src);
7408 %}
7409 %}
7410
7411 // Conditional move
7412 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7413 predicate(VM_Version::supports_cmov() );
7414 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7415 ins_cost(250);
7416 format %{ "CMOV$cop $dst,$src" %}
7417 opcode(0x0F,0x40);
7418 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7419 ins_pipe( pipe_cmov_mem );
7420 %}
7421
7422 // Conditional move
7423 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7424 predicate(VM_Version::supports_cmov() );
7425 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7426 ins_cost(250);
7427 format %{ "CMOV$cop $dst,$src" %}
7428 opcode(0x0F,0x40);
7429 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7430 ins_pipe( pipe_cmov_mem );
7431 %}
7432
7433 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7434 predicate(VM_Version::supports_cmov() );
7435 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7436 ins_cost(250);
7437 expand %{
7438 cmovI_memU(cop, cr, dst, src);
7439 %}
7440 %}
7441
7442 // Conditional move
7443 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7444 predicate(VM_Version::supports_cmov() );
7445 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7446 ins_cost(200);
7447 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7448 opcode(0x0F,0x40);
7449 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7450 ins_pipe( pipe_cmov_reg );
7451 %}
7452
7453 // Conditional move (non-P6 version)
7454 // Note: a CMoveP is generated for stubs and native wrappers
7455 // regardless of whether we are on a P6, so we
7456 // emulate a cmov here
7457 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7458 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7459 ins_cost(300);
7460 format %{ "Jn$cop skip\n\t"
7461 "MOV $dst,$src\t# pointer\n"
7462 "skip:" %}
7463 opcode(0x8b);
7464 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7465 ins_pipe( pipe_cmov_reg );
7466 %}
7467
7468 // Conditional move
7469 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7470 predicate(VM_Version::supports_cmov() );
7471 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7472 ins_cost(200);
7473 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7474 opcode(0x0F,0x40);
7475 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7476 ins_pipe( pipe_cmov_reg );
7477 %}
7478
7479 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7480 predicate(VM_Version::supports_cmov() );
7481 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7482 ins_cost(200);
7483 expand %{
7484 cmovP_regU(cop, cr, dst, src);
7485 %}
7486 %}
7487
7488 // DISABLED: Requires the ADLC to emit a bottom_type call that
7489 // correctly meets the two pointer arguments; one is an incoming
7490 // register but the other is a memory operand. ALSO appears to
7491 // be buggy with implicit null checks.
7492 //
7493 //// Conditional move
7494 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7495 // predicate(VM_Version::supports_cmov() );
7496 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7497 // ins_cost(250);
7498 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7499 // opcode(0x0F,0x40);
7500 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7501 // ins_pipe( pipe_cmov_mem );
7502 //%}
7503 //
7504 //// Conditional move
7505 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7506 // predicate(VM_Version::supports_cmov() );
7507 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7508 // ins_cost(250);
7509 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7510 // opcode(0x0F,0x40);
7511 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7512 // ins_pipe( pipe_cmov_mem );
7513 //%}
7514
7515 // Conditional move
7516 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7517 predicate(UseSSE<=1);
7518 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7519 ins_cost(200);
7520 format %{ "FCMOV$cop $dst,$src\t# double" %}
7521 opcode(0xDA);
7522 ins_encode( enc_cmov_dpr(cop,src) );
7523 ins_pipe( pipe_cmovDPR_reg );
7524 %}
7525
7526 // Conditional move
7527 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7528 predicate(UseSSE==0);
7529 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7530 ins_cost(200);
7531 format %{ "FCMOV$cop $dst,$src\t# float" %}
7532 opcode(0xDA);
7533 ins_encode( enc_cmov_dpr(cop,src) );
7534 ins_pipe( pipe_cmovDPR_reg );
7535 %}
7536
7537 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7538 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7539 predicate(UseSSE<=1);
7540 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7541 ins_cost(200);
7542 format %{ "Jn$cop skip\n\t"
7543 "MOV $dst,$src\t# double\n"
7544 "skip:" %}
7545 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7546 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7547 ins_pipe( pipe_cmovDPR_reg );
7548 %}
7549
7550 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7551 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7552 predicate(UseSSE==0);
7553 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7554 ins_cost(200);
7555 format %{ "Jn$cop skip\n\t"
7556 "MOV $dst,$src\t# float\n"
7557 "skip:" %}
7558 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7559 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7560 ins_pipe( pipe_cmovDPR_reg );
7561 %}
7562
7563 // No CMOVE with SSE/SSE2
7564 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7565 predicate (UseSSE>=1);
7566 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7567 ins_cost(200);
7568 format %{ "Jn$cop skip\n\t"
7569 "MOVSS $dst,$src\t# float\n"
7570 "skip:" %}
7571 ins_encode %{
7572 Label skip;
7573 // Invert sense of branch from sense of CMOV
7574 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7575 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7576 __ bind(skip);
7577 %}
7578 ins_pipe( pipe_slow );
7579 %}
7580
7581 // No CMOVE with SSE/SSE2
7582 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7583 predicate (UseSSE>=2);
7584 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7585 ins_cost(200);
7586 format %{ "Jn$cop skip\n\t"
7587 "MOVSD $dst,$src\t# float\n"
7588 "skip:" %}
7589 ins_encode %{
7590 Label skip;
7591 // Invert sense of branch from sense of CMOV
7592 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7593 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7594 __ bind(skip);
7595 %}
7596 ins_pipe( pipe_slow );
7597 %}
7598
7599 // unsigned version
7600 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7601 predicate (UseSSE>=1);
7602 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7603 ins_cost(200);
7604 format %{ "Jn$cop skip\n\t"
7605 "MOVSS $dst,$src\t# float\n"
7606 "skip:" %}
7607 ins_encode %{
7608 Label skip;
7609 // Invert sense of branch from sense of CMOV
7610 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7611 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7612 __ bind(skip);
7613 %}
7614 ins_pipe( pipe_slow );
7615 %}
7616
7617 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7618 predicate (UseSSE>=1);
7619 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7620 ins_cost(200);
7621 expand %{
7622 fcmovF_regU(cop, cr, dst, src);
7623 %}
7624 %}
7625
7626 // unsigned version
7627 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7628 predicate (UseSSE>=2);
7629 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7630 ins_cost(200);
7631 format %{ "Jn$cop skip\n\t"
7632 "MOVSD $dst,$src\t# float\n"
7633 "skip:" %}
7634 ins_encode %{
7635 Label skip;
7636 // Invert sense of branch from sense of CMOV
7637 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7638 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7639 __ bind(skip);
7640 %}
7641 ins_pipe( pipe_slow );
7642 %}
7643
7644 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7645 predicate (UseSSE>=2);
7646 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7647 ins_cost(200);
7648 expand %{
7649 fcmovD_regU(cop, cr, dst, src);
7650 %}
7651 %}
7652
7653 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7654 predicate(VM_Version::supports_cmov() );
7655 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7656 ins_cost(200);
7657 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7658 "CMOV$cop $dst.hi,$src.hi" %}
7659 opcode(0x0F,0x40);
7660 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7661 ins_pipe( pipe_cmov_reg_long );
7662 %}
7663
7664 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7665 predicate(VM_Version::supports_cmov() );
7666 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7667 ins_cost(200);
7668 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7669 "CMOV$cop $dst.hi,$src.hi" %}
7670 opcode(0x0F,0x40);
7671 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7672 ins_pipe( pipe_cmov_reg_long );
7673 %}
7674
7675 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7676 predicate(VM_Version::supports_cmov() );
7677 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7678 ins_cost(200);
7679 expand %{
7680 cmovL_regU(cop, cr, dst, src);
7681 %}
7682 %}
7683
7684 //----------Arithmetic Instructions--------------------------------------------
7685 //----------Addition Instructions----------------------------------------------
7686 // Integer Addition Instructions
7687 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7688 match(Set dst (AddI dst src));
7689 effect(KILL cr);
7690
7691 size(2);
7692 format %{ "ADD $dst,$src" %}
7693 opcode(0x03);
7694 ins_encode( OpcP, RegReg( dst, src) );
7695 ins_pipe( ialu_reg_reg );
7696 %}
7697
7698 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7699 match(Set dst (AddI dst src));
7700 effect(KILL cr);
7701
7702 format %{ "ADD $dst,$src" %}
7703 opcode(0x81, 0x00); /* /0 id */
7704 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7705 ins_pipe( ialu_reg );
7706 %}
7707
7708 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7709 predicate(UseIncDec);
7710 match(Set dst (AddI dst src));
7711 effect(KILL cr);
7712
7713 size(1);
7714 format %{ "INC $dst" %}
7715 opcode(0x40); /* */
7716 ins_encode( Opc_plus( primary, dst ) );
7717 ins_pipe( ialu_reg );
7718 %}
7719
7720 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7721 match(Set dst (AddI src0 src1));
7722 ins_cost(110);
7723
7724 format %{ "LEA $dst,[$src0 + $src1]" %}
7725 opcode(0x8D); /* 0x8D /r */
7726 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7727 ins_pipe( ialu_reg_reg );
7728 %}
7729
7730 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7731 match(Set dst (AddP src0 src1));
7732 ins_cost(110);
7733
7734 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7735 opcode(0x8D); /* 0x8D /r */
7736 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7737 ins_pipe( ialu_reg_reg );
7738 %}
7739
7740 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7741 predicate(UseIncDec);
7742 match(Set dst (AddI dst src));
7743 effect(KILL cr);
7744
7745 size(1);
7746 format %{ "DEC $dst" %}
7747 opcode(0x48); /* */
7748 ins_encode( Opc_plus( primary, dst ) );
7749 ins_pipe( ialu_reg );
7750 %}
7751
7752 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7753 match(Set dst (AddP dst src));
7754 effect(KILL cr);
7755
7756 size(2);
7757 format %{ "ADD $dst,$src" %}
7758 opcode(0x03);
7759 ins_encode( OpcP, RegReg( dst, src) );
7760 ins_pipe( ialu_reg_reg );
7761 %}
7762
7763 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7764 match(Set dst (AddP dst src));
7765 effect(KILL cr);
7766
7767 format %{ "ADD $dst,$src" %}
7768 opcode(0x81,0x00); /* Opcode 81 /0 id */
7769 // ins_encode( RegImm( dst, src) );
7770 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7771 ins_pipe( ialu_reg );
7772 %}
7773
7774 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7775 match(Set dst (AddI dst (LoadI src)));
7776 effect(KILL cr);
7777
7778 ins_cost(125);
7779 format %{ "ADD $dst,$src" %}
7780 opcode(0x03);
7781 ins_encode( OpcP, RegMem( dst, src) );
7782 ins_pipe( ialu_reg_mem );
7783 %}
7784
7785 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7786 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7787 effect(KILL cr);
7788
7789 ins_cost(150);
7790 format %{ "ADD $dst,$src" %}
7791 opcode(0x01); /* Opcode 01 /r */
7792 ins_encode( OpcP, RegMem( src, dst ) );
7793 ins_pipe( ialu_mem_reg );
7794 %}
7795
7796 // Add Memory with Immediate
7797 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7798 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7799 effect(KILL cr);
7800
7801 ins_cost(125);
7802 format %{ "ADD $dst,$src" %}
7803 opcode(0x81); /* Opcode 81 /0 id */
7804 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7805 ins_pipe( ialu_mem_imm );
7806 %}
7807
7808 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7809 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7810 effect(KILL cr);
7811
7812 ins_cost(125);
7813 format %{ "INC $dst" %}
7814 opcode(0xFF); /* Opcode FF /0 */
7815 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7816 ins_pipe( ialu_mem_imm );
7817 %}
7818
7819 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7820 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7821 effect(KILL cr);
7822
7823 ins_cost(125);
7824 format %{ "DEC $dst" %}
7825 opcode(0xFF); /* Opcode FF /1 */
7826 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7827 ins_pipe( ialu_mem_imm );
7828 %}
7829
7830
7831 instruct checkCastPP( eRegP dst ) %{
7832 match(Set dst (CheckCastPP dst));
7833
7834 size(0);
7835 format %{ "#checkcastPP of $dst" %}
7836 ins_encode( /*empty encoding*/ );
7837 ins_pipe( empty );
7838 %}
7839
7840 instruct castPP( eRegP dst ) %{
7841 match(Set dst (CastPP dst));
7842 format %{ "#castPP of $dst" %}
7843 ins_encode( /*empty encoding*/ );
7844 ins_pipe( empty );
7845 %}
7846
7847 instruct castII( eRegI dst ) %{
7848 match(Set dst (CastII dst));
7849 format %{ "#castII of $dst" %}
7850 ins_encode( /*empty encoding*/ );
7851 ins_cost(0);
7852 ins_pipe( empty );
7853 %}
7854
7855
7856 // Load-locked - same as a regular pointer load when used with compare-swap
7857 instruct loadPLocked(eRegP dst, memory mem) %{
7858 match(Set dst (LoadPLocked mem));
7859
7860 ins_cost(125);
7861 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7862 opcode(0x8B);
7863 ins_encode( OpcP, RegMem(dst,mem));
7864 ins_pipe( ialu_reg_mem );
7865 %}
7866
7867 // LoadLong-locked - same as a volatile long load when used with compare-swap
7868 instruct loadLLocked(stackSlotL dst, memory mem) %{
7869 predicate(UseSSE<=1);
7870 match(Set dst (LoadLLocked mem));
7871
7872 ins_cost(200);
7873 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7874 "FISTp $dst" %}
7875 ins_encode(enc_loadL_volatile(mem,dst));
7876 ins_pipe( fpu_reg_mem );
7877 %}
7878
7879 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{
7880 predicate(UseSSE>=2);
7881 match(Set dst (LoadLLocked mem));
7882 effect(TEMP tmp);
7883 ins_cost(180);
7884 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7885 "MOVSD $dst,$tmp" %}
7886 ins_encode %{
7887 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7888 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7889 %}
7890 ins_pipe( pipe_slow );
7891 %}
7892
7893 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{
7894 predicate(UseSSE>=2);
7895 match(Set dst (LoadLLocked mem));
7896 effect(TEMP tmp);
7897 ins_cost(160);
7898 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7899 "MOVD $dst.lo,$tmp\n\t"
7900 "PSRLQ $tmp,32\n\t"
7901 "MOVD $dst.hi,$tmp" %}
7902 ins_encode %{
7903 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7904 __ movdl($dst$$Register, $tmp$$XMMRegister);
7905 __ psrlq($tmp$$XMMRegister, 32);
7906 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7907 %}
7908 ins_pipe( pipe_slow );
7909 %}
7910
7911 // Conditional-store of the updated heap-top.
7912 // Used during allocation of the shared heap.
7913 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7914 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7915 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7916 // EAX is killed if there is contention, but then it's also unused.
7917 // In the common case of no contention, EAX holds the new oop address.
7918 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7919 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7920 ins_pipe( pipe_cmpxchg );
7921 %}
7922
7923 // Conditional-store of an int value.
7924 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7925 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
7926 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7927 effect(KILL oldval);
7928 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7929 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7930 ins_pipe( pipe_cmpxchg );
7931 %}
7932
7933 // Conditional-store of a long value.
7934 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7935 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7936 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7937 effect(KILL oldval);
7938 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7939 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7940 "XCHG EBX,ECX"
7941 %}
7942 ins_encode %{
7943 // Note: we need to swap rbx, and rcx before and after the
7944 // cmpxchg8 instruction because the instruction uses
7945 // rcx as the high order word of the new value to store but
7946 // our register encoding uses rbx.
7947 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7948 if( os::is_MP() )
7949 __ lock();
7950 __ cmpxchg8($mem$$Address);
7951 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7952 %}
7953 ins_pipe( pipe_cmpxchg );
7954 %}
7955
7956 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7957
7958 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7959 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7960 effect(KILL cr, KILL oldval);
7961 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7962 "MOV $res,0\n\t"
7963 "JNE,s fail\n\t"
7964 "MOV $res,1\n"
7965 "fail:" %}
7966 ins_encode( enc_cmpxchg8(mem_ptr),
7967 enc_flags_ne_to_boolean(res) );
7968 ins_pipe( pipe_cmpxchg );
7969 %}
7970
7971 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7972 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7973 effect(KILL cr, KILL oldval);
7974 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7975 "MOV $res,0\n\t"
7976 "JNE,s fail\n\t"
7977 "MOV $res,1\n"
7978 "fail:" %}
7979 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7980 ins_pipe( pipe_cmpxchg );
7981 %}
7982
7983 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7984 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7985 effect(KILL cr, KILL oldval);
7986 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7987 "MOV $res,0\n\t"
7988 "JNE,s fail\n\t"
7989 "MOV $res,1\n"
7990 "fail:" %}
7991 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7992 ins_pipe( pipe_cmpxchg );
7993 %}
7994
7995 //----------Subtraction Instructions-------------------------------------------
7996 // Integer Subtraction Instructions
7997 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7998 match(Set dst (SubI dst src));
7999 effect(KILL cr);
8000
8001 size(2);
8002 format %{ "SUB $dst,$src" %}
8003 opcode(0x2B);
8004 ins_encode( OpcP, RegReg( dst, src) );
8005 ins_pipe( ialu_reg_reg );
8006 %}
8007
8008 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8009 match(Set dst (SubI dst src));
8010 effect(KILL cr);
8011
8012 format %{ "SUB $dst,$src" %}
8013 opcode(0x81,0x05); /* Opcode 81 /5 */
8014 // ins_encode( RegImm( dst, src) );
8015 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8016 ins_pipe( ialu_reg );
8017 %}
8018
8019 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8020 match(Set dst (SubI dst (LoadI src)));
8021 effect(KILL cr);
8022
8023 ins_cost(125);
8024 format %{ "SUB $dst,$src" %}
8025 opcode(0x2B);
8026 ins_encode( OpcP, RegMem( dst, src) );
8027 ins_pipe( ialu_reg_mem );
8028 %}
8029
8030 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8031 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8032 effect(KILL cr);
8033
8034 ins_cost(150);
8035 format %{ "SUB $dst,$src" %}
8036 opcode(0x29); /* Opcode 29 /r */
8037 ins_encode( OpcP, RegMem( src, dst ) );
8038 ins_pipe( ialu_mem_reg );
8039 %}
8040
8041 // Subtract from a pointer
8042 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8043 match(Set dst (AddP dst (SubI zero src)));
8044 effect(KILL cr);
8045
8046 size(2);
8047 format %{ "SUB $dst,$src" %}
8048 opcode(0x2B);
8049 ins_encode( OpcP, RegReg( dst, src) );
8050 ins_pipe( ialu_reg_reg );
8051 %}
8052
8053 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8054 match(Set dst (SubI zero dst));
8055 effect(KILL cr);
8056
8057 size(2);
8058 format %{ "NEG $dst" %}
8059 opcode(0xF7,0x03); // Opcode F7 /3
8060 ins_encode( OpcP, RegOpc( dst ) );
8061 ins_pipe( ialu_reg );
8062 %}
8063
8064
8065 //----------Multiplication/Division Instructions-------------------------------
8066 // Integer Multiplication Instructions
8067 // Multiply Register
8068 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8069 match(Set dst (MulI dst src));
8070 effect(KILL cr);
8071
8072 size(3);
8073 ins_cost(300);
8074 format %{ "IMUL $dst,$src" %}
8075 opcode(0xAF, 0x0F);
8076 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8077 ins_pipe( ialu_reg_reg_alu0 );
8078 %}
8079
8080 // Multiply 32-bit Immediate
8081 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8082 match(Set dst (MulI src imm));
8083 effect(KILL cr);
8084
8085 ins_cost(300);
8086 format %{ "IMUL $dst,$src,$imm" %}
8087 opcode(0x69); /* 69 /r id */
8088 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8089 ins_pipe( ialu_reg_reg_alu0 );
8090 %}
8091
8092 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8093 match(Set dst src);
8094 effect(KILL cr);
8095
8096 // Note that this is artificially increased to make it more expensive than loadConL
8097 ins_cost(250);
8098 format %{ "MOV EAX,$src\t// low word only" %}
8099 opcode(0xB8);
8100 ins_encode( LdImmL_Lo(dst, src) );
8101 ins_pipe( ialu_reg_fat );
8102 %}
8103
8104 // Multiply by 32-bit Immediate, taking the shifted high order results
8105 // (special case for shift by 32)
8106 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8107 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8108 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8109 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8110 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8111 effect(USE src1, KILL cr);
8112
8113 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8114 ins_cost(0*100 + 1*400 - 150);
8115 format %{ "IMUL EDX:EAX,$src1" %}
8116 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8117 ins_pipe( pipe_slow );
8118 %}
8119
8120 // Multiply by 32-bit Immediate, taking the shifted high order results
8121 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8122 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8123 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8124 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8125 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8126 effect(USE src1, KILL cr);
8127
8128 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8129 ins_cost(1*100 + 1*400 - 150);
8130 format %{ "IMUL EDX:EAX,$src1\n\t"
8131 "SAR EDX,$cnt-32" %}
8132 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8133 ins_pipe( pipe_slow );
8134 %}
8135
8136 // Multiply Memory 32-bit Immediate
8137 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8138 match(Set dst (MulI (LoadI src) imm));
8139 effect(KILL cr);
8140
8141 ins_cost(300);
8142 format %{ "IMUL $dst,$src,$imm" %}
8143 opcode(0x69); /* 69 /r id */
8144 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8145 ins_pipe( ialu_reg_mem_alu0 );
8146 %}
8147
8148 // Multiply Memory
8149 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8150 match(Set dst (MulI dst (LoadI src)));
8151 effect(KILL cr);
8152
8153 ins_cost(350);
8154 format %{ "IMUL $dst,$src" %}
8155 opcode(0xAF, 0x0F);
8156 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8157 ins_pipe( ialu_reg_mem_alu0 );
8158 %}
8159
8160 // Multiply Register Int to Long
8161 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8162 // Basic Idea: long = (long)int * (long)int
8163 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8164 effect(DEF dst, USE src, USE src1, KILL flags);
8165
8166 ins_cost(300);
8167 format %{ "IMUL $dst,$src1" %}
8168
8169 ins_encode( long_int_multiply( dst, src1 ) );
8170 ins_pipe( ialu_reg_reg_alu0 );
8171 %}
8172
8173 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8174 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8175 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8176 effect(KILL flags);
8177
8178 ins_cost(300);
8179 format %{ "MUL $dst,$src1" %}
8180
8181 ins_encode( long_uint_multiply(dst, src1) );
8182 ins_pipe( ialu_reg_reg_alu0 );
8183 %}
8184
8185 // Multiply Register Long
8186 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8187 match(Set dst (MulL dst src));
8188 effect(KILL cr, TEMP tmp);
8189 ins_cost(4*100+3*400);
8190 // Basic idea: lo(result) = lo(x_lo * y_lo)
8191 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8192 format %{ "MOV $tmp,$src.lo\n\t"
8193 "IMUL $tmp,EDX\n\t"
8194 "MOV EDX,$src.hi\n\t"
8195 "IMUL EDX,EAX\n\t"
8196 "ADD $tmp,EDX\n\t"
8197 "MUL EDX:EAX,$src.lo\n\t"
8198 "ADD EDX,$tmp" %}
8199 ins_encode( long_multiply( dst, src, tmp ) );
8200 ins_pipe( pipe_slow );
8201 %}
8202
8203 // Multiply Register Long where the left operand's high 32 bits are zero
8204 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8205 predicate(is_operand_hi32_zero(n->in(1)));
8206 match(Set dst (MulL dst src));
8207 effect(KILL cr, TEMP tmp);
8208 ins_cost(2*100+2*400);
8209 // Basic idea: lo(result) = lo(x_lo * y_lo)
8210 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8211 format %{ "MOV $tmp,$src.hi\n\t"
8212 "IMUL $tmp,EAX\n\t"
8213 "MUL EDX:EAX,$src.lo\n\t"
8214 "ADD EDX,$tmp" %}
8215 ins_encode %{
8216 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8217 __ imull($tmp$$Register, rax);
8218 __ mull($src$$Register);
8219 __ addl(rdx, $tmp$$Register);
8220 %}
8221 ins_pipe( pipe_slow );
8222 %}
8223
8224 // Multiply Register Long where the right operand's high 32 bits are zero
8225 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8226 predicate(is_operand_hi32_zero(n->in(2)));
8227 match(Set dst (MulL dst src));
8228 effect(KILL cr, TEMP tmp);
8229 ins_cost(2*100+2*400);
8230 // Basic idea: lo(result) = lo(x_lo * y_lo)
8231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8232 format %{ "MOV $tmp,$src.lo\n\t"
8233 "IMUL $tmp,EDX\n\t"
8234 "MUL EDX:EAX,$src.lo\n\t"
8235 "ADD EDX,$tmp" %}
8236 ins_encode %{
8237 __ movl($tmp$$Register, $src$$Register);
8238 __ imull($tmp$$Register, rdx);
8239 __ mull($src$$Register);
8240 __ addl(rdx, $tmp$$Register);
8241 %}
8242 ins_pipe( pipe_slow );
8243 %}
8244
8245 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8246 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8247 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8248 match(Set dst (MulL dst src));
8249 effect(KILL cr);
8250 ins_cost(1*400);
8251 // Basic idea: lo(result) = lo(x_lo * y_lo)
8252 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8253 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8254 ins_encode %{
8255 __ mull($src$$Register);
8256 %}
8257 ins_pipe( pipe_slow );
8258 %}
8259
8260 // Multiply Register Long by small constant
8261 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8262 match(Set dst (MulL dst src));
8263 effect(KILL cr, TEMP tmp);
8264 ins_cost(2*100+2*400);
8265 size(12);
8266 // Basic idea: lo(result) = lo(src * EAX)
8267 // hi(result) = hi(src * EAX) + lo(src * EDX)
8268 format %{ "IMUL $tmp,EDX,$src\n\t"
8269 "MOV EDX,$src\n\t"
8270 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8271 "ADD EDX,$tmp" %}
8272 ins_encode( long_multiply_con( dst, src, tmp ) );
8273 ins_pipe( pipe_slow );
8274 %}
8275
8276 // Integer DIV with Register
8277 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8278 match(Set rax (DivI rax div));
8279 effect(KILL rdx, KILL cr);
8280 size(26);
8281 ins_cost(30*100+10*100);
8282 format %{ "CMP EAX,0x80000000\n\t"
8283 "JNE,s normal\n\t"
8284 "XOR EDX,EDX\n\t"
8285 "CMP ECX,-1\n\t"
8286 "JE,s done\n"
8287 "normal: CDQ\n\t"
8288 "IDIV $div\n\t"
8289 "done:" %}
8290 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8291 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8292 ins_pipe( ialu_reg_reg_alu0 );
8293 %}
8294
8295 // Divide Register Long
8296 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8297 match(Set dst (DivL src1 src2));
8298 effect( KILL cr, KILL cx, KILL bx );
8299 ins_cost(10000);
8300 format %{ "PUSH $src1.hi\n\t"
8301 "PUSH $src1.lo\n\t"
8302 "PUSH $src2.hi\n\t"
8303 "PUSH $src2.lo\n\t"
8304 "CALL SharedRuntime::ldiv\n\t"
8305 "ADD ESP,16" %}
8306 ins_encode( long_div(src1,src2) );
8307 ins_pipe( pipe_slow );
8308 %}
8309
8310 // Integer DIVMOD with Register, both quotient and mod results
8311 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8312 match(DivModI rax div);
8313 effect(KILL cr);
8314 size(26);
8315 ins_cost(30*100+10*100);
8316 format %{ "CMP EAX,0x80000000\n\t"
8317 "JNE,s normal\n\t"
8318 "XOR EDX,EDX\n\t"
8319 "CMP ECX,-1\n\t"
8320 "JE,s done\n"
8321 "normal: CDQ\n\t"
8322 "IDIV $div\n\t"
8323 "done:" %}
8324 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8325 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8326 ins_pipe( pipe_slow );
8327 %}
8328
8329 // Integer MOD with Register
8330 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8331 match(Set rdx (ModI rax div));
8332 effect(KILL rax, KILL cr);
8333
8334 size(26);
8335 ins_cost(300);
8336 format %{ "CDQ\n\t"
8337 "IDIV $div" %}
8338 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8339 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8340 ins_pipe( ialu_reg_reg_alu0 );
8341 %}
8342
8343 // Remainder Register Long
8344 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8345 match(Set dst (ModL src1 src2));
8346 effect( KILL cr, KILL cx, KILL bx );
8347 ins_cost(10000);
8348 format %{ "PUSH $src1.hi\n\t"
8349 "PUSH $src1.lo\n\t"
8350 "PUSH $src2.hi\n\t"
8351 "PUSH $src2.lo\n\t"
8352 "CALL SharedRuntime::lrem\n\t"
8353 "ADD ESP,16" %}
8354 ins_encode( long_mod(src1,src2) );
8355 ins_pipe( pipe_slow );
8356 %}
8357
8358 // Divide Register Long (no special case since divisor != -1)
8359 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8360 match(Set dst (DivL dst imm));
8361 effect( TEMP tmp, TEMP tmp2, KILL cr );
8362 ins_cost(1000);
8363 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8364 "XOR $tmp2,$tmp2\n\t"
8365 "CMP $tmp,EDX\n\t"
8366 "JA,s fast\n\t"
8367 "MOV $tmp2,EAX\n\t"
8368 "MOV EAX,EDX\n\t"
8369 "MOV EDX,0\n\t"
8370 "JLE,s pos\n\t"
8371 "LNEG EAX : $tmp2\n\t"
8372 "DIV $tmp # unsigned division\n\t"
8373 "XCHG EAX,$tmp2\n\t"
8374 "DIV $tmp\n\t"
8375 "LNEG $tmp2 : EAX\n\t"
8376 "JMP,s done\n"
8377 "pos:\n\t"
8378 "DIV $tmp\n\t"
8379 "XCHG EAX,$tmp2\n"
8380 "fast:\n\t"
8381 "DIV $tmp\n"
8382 "done:\n\t"
8383 "MOV EDX,$tmp2\n\t"
8384 "NEG EDX:EAX # if $imm < 0" %}
8385 ins_encode %{
8386 int con = (int)$imm$$constant;
8387 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8388 int pcon = (con > 0) ? con : -con;
8389 Label Lfast, Lpos, Ldone;
8390
8391 __ movl($tmp$$Register, pcon);
8392 __ xorl($tmp2$$Register,$tmp2$$Register);
8393 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8394 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8395
8396 __ movl($tmp2$$Register, $dst$$Register); // save
8397 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8398 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8399 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8400
8401 // Negative dividend.
8402 // convert value to positive to use unsigned division
8403 __ lneg($dst$$Register, $tmp2$$Register);
8404 __ divl($tmp$$Register);
8405 __ xchgl($dst$$Register, $tmp2$$Register);
8406 __ divl($tmp$$Register);
8407 // revert result back to negative
8408 __ lneg($tmp2$$Register, $dst$$Register);
8409 __ jmpb(Ldone);
8410
8411 __ bind(Lpos);
8412 __ divl($tmp$$Register); // Use unsigned division
8413 __ xchgl($dst$$Register, $tmp2$$Register);
8414 // Fallthrow for final divide, tmp2 has 32 bit hi result
8415
8416 __ bind(Lfast);
8417 // fast path: src is positive
8418 __ divl($tmp$$Register); // Use unsigned division
8419
8420 __ bind(Ldone);
8421 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8422 if (con < 0) {
8423 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8424 }
8425 %}
8426 ins_pipe( pipe_slow );
8427 %}
8428
8429 // Remainder Register Long (remainder fit into 32 bits)
8430 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8431 match(Set dst (ModL dst imm));
8432 effect( TEMP tmp, TEMP tmp2, KILL cr );
8433 ins_cost(1000);
8434 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8435 "CMP $tmp,EDX\n\t"
8436 "JA,s fast\n\t"
8437 "MOV $tmp2,EAX\n\t"
8438 "MOV EAX,EDX\n\t"
8439 "MOV EDX,0\n\t"
8440 "JLE,s pos\n\t"
8441 "LNEG EAX : $tmp2\n\t"
8442 "DIV $tmp # unsigned division\n\t"
8443 "MOV EAX,$tmp2\n\t"
8444 "DIV $tmp\n\t"
8445 "NEG EDX\n\t"
8446 "JMP,s done\n"
8447 "pos:\n\t"
8448 "DIV $tmp\n\t"
8449 "MOV EAX,$tmp2\n"
8450 "fast:\n\t"
8451 "DIV $tmp\n"
8452 "done:\n\t"
8453 "MOV EAX,EDX\n\t"
8454 "SAR EDX,31\n\t" %}
8455 ins_encode %{
8456 int con = (int)$imm$$constant;
8457 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8458 int pcon = (con > 0) ? con : -con;
8459 Label Lfast, Lpos, Ldone;
8460
8461 __ movl($tmp$$Register, pcon);
8462 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8463 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8464
8465 __ movl($tmp2$$Register, $dst$$Register); // save
8466 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8467 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8468 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8469
8470 // Negative dividend.
8471 // convert value to positive to use unsigned division
8472 __ lneg($dst$$Register, $tmp2$$Register);
8473 __ divl($tmp$$Register);
8474 __ movl($dst$$Register, $tmp2$$Register);
8475 __ divl($tmp$$Register);
8476 // revert remainder back to negative
8477 __ negl(HIGH_FROM_LOW($dst$$Register));
8478 __ jmpb(Ldone);
8479
8480 __ bind(Lpos);
8481 __ divl($tmp$$Register);
8482 __ movl($dst$$Register, $tmp2$$Register);
8483
8484 __ bind(Lfast);
8485 // fast path: src is positive
8486 __ divl($tmp$$Register);
8487
8488 __ bind(Ldone);
8489 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8490 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8491
8492 %}
8493 ins_pipe( pipe_slow );
8494 %}
8495
8496 // Integer Shift Instructions
8497 // Shift Left by one
8498 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8499 match(Set dst (LShiftI dst shift));
8500 effect(KILL cr);
8501
8502 size(2);
8503 format %{ "SHL $dst,$shift" %}
8504 opcode(0xD1, 0x4); /* D1 /4 */
8505 ins_encode( OpcP, RegOpc( dst ) );
8506 ins_pipe( ialu_reg );
8507 %}
8508
8509 // Shift Left by 8-bit immediate
8510 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8511 match(Set dst (LShiftI dst shift));
8512 effect(KILL cr);
8513
8514 size(3);
8515 format %{ "SHL $dst,$shift" %}
8516 opcode(0xC1, 0x4); /* C1 /4 ib */
8517 ins_encode( RegOpcImm( dst, shift) );
8518 ins_pipe( ialu_reg );
8519 %}
8520
8521 // Shift Left by variable
8522 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8523 match(Set dst (LShiftI dst shift));
8524 effect(KILL cr);
8525
8526 size(2);
8527 format %{ "SHL $dst,$shift" %}
8528 opcode(0xD3, 0x4); /* D3 /4 */
8529 ins_encode( OpcP, RegOpc( dst ) );
8530 ins_pipe( ialu_reg_reg );
8531 %}
8532
8533 // Arithmetic shift right by one
8534 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8535 match(Set dst (RShiftI dst shift));
8536 effect(KILL cr);
8537
8538 size(2);
8539 format %{ "SAR $dst,$shift" %}
8540 opcode(0xD1, 0x7); /* D1 /7 */
8541 ins_encode( OpcP, RegOpc( dst ) );
8542 ins_pipe( ialu_reg );
8543 %}
8544
8545 // Arithmetic shift right by one
8546 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8547 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8548 effect(KILL cr);
8549 format %{ "SAR $dst,$shift" %}
8550 opcode(0xD1, 0x7); /* D1 /7 */
8551 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8552 ins_pipe( ialu_mem_imm );
8553 %}
8554
8555 // Arithmetic Shift Right by 8-bit immediate
8556 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8557 match(Set dst (RShiftI dst shift));
8558 effect(KILL cr);
8559
8560 size(3);
8561 format %{ "SAR $dst,$shift" %}
8562 opcode(0xC1, 0x7); /* C1 /7 ib */
8563 ins_encode( RegOpcImm( dst, shift ) );
8564 ins_pipe( ialu_mem_imm );
8565 %}
8566
8567 // Arithmetic Shift Right by 8-bit immediate
8568 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8569 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8570 effect(KILL cr);
8571
8572 format %{ "SAR $dst,$shift" %}
8573 opcode(0xC1, 0x7); /* C1 /7 ib */
8574 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8575 ins_pipe( ialu_mem_imm );
8576 %}
8577
8578 // Arithmetic Shift Right by variable
8579 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8580 match(Set dst (RShiftI dst shift));
8581 effect(KILL cr);
8582
8583 size(2);
8584 format %{ "SAR $dst,$shift" %}
8585 opcode(0xD3, 0x7); /* D3 /7 */
8586 ins_encode( OpcP, RegOpc( dst ) );
8587 ins_pipe( ialu_reg_reg );
8588 %}
8589
8590 // Logical shift right by one
8591 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8592 match(Set dst (URShiftI dst shift));
8593 effect(KILL cr);
8594
8595 size(2);
8596 format %{ "SHR $dst,$shift" %}
8597 opcode(0xD1, 0x5); /* D1 /5 */
8598 ins_encode( OpcP, RegOpc( dst ) );
8599 ins_pipe( ialu_reg );
8600 %}
8601
8602 // Logical Shift Right by 8-bit immediate
8603 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8604 match(Set dst (URShiftI dst shift));
8605 effect(KILL cr);
8606
8607 size(3);
8608 format %{ "SHR $dst,$shift" %}
8609 opcode(0xC1, 0x5); /* C1 /5 ib */
8610 ins_encode( RegOpcImm( dst, shift) );
8611 ins_pipe( ialu_reg );
8612 %}
8613
8614
8615 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8616 // This idiom is used by the compiler for the i2b bytecode.
8617 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8618 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8619
8620 size(3);
8621 format %{ "MOVSX $dst,$src :8" %}
8622 ins_encode %{
8623 __ movsbl($dst$$Register, $src$$Register);
8624 %}
8625 ins_pipe(ialu_reg_reg);
8626 %}
8627
8628 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8629 // This idiom is used by the compiler the i2s bytecode.
8630 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8631 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8632
8633 size(3);
8634 format %{ "MOVSX $dst,$src :16" %}
8635 ins_encode %{
8636 __ movswl($dst$$Register, $src$$Register);
8637 %}
8638 ins_pipe(ialu_reg_reg);
8639 %}
8640
8641
8642 // Logical Shift Right by variable
8643 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8644 match(Set dst (URShiftI dst shift));
8645 effect(KILL cr);
8646
8647 size(2);
8648 format %{ "SHR $dst,$shift" %}
8649 opcode(0xD3, 0x5); /* D3 /5 */
8650 ins_encode( OpcP, RegOpc( dst ) );
8651 ins_pipe( ialu_reg_reg );
8652 %}
8653
8654
8655 //----------Logical Instructions-----------------------------------------------
8656 //----------Integer Logical Instructions---------------------------------------
8657 // And Instructions
8658 // And Register with Register
8659 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8660 match(Set dst (AndI dst src));
8661 effect(KILL cr);
8662
8663 size(2);
8664 format %{ "AND $dst,$src" %}
8665 opcode(0x23);
8666 ins_encode( OpcP, RegReg( dst, src) );
8667 ins_pipe( ialu_reg_reg );
8668 %}
8669
8670 // And Register with Immediate
8671 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8672 match(Set dst (AndI dst src));
8673 effect(KILL cr);
8674
8675 format %{ "AND $dst,$src" %}
8676 opcode(0x81,0x04); /* Opcode 81 /4 */
8677 // ins_encode( RegImm( dst, src) );
8678 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8679 ins_pipe( ialu_reg );
8680 %}
8681
8682 // And Register with Memory
8683 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8684 match(Set dst (AndI dst (LoadI src)));
8685 effect(KILL cr);
8686
8687 ins_cost(125);
8688 format %{ "AND $dst,$src" %}
8689 opcode(0x23);
8690 ins_encode( OpcP, RegMem( dst, src) );
8691 ins_pipe( ialu_reg_mem );
8692 %}
8693
8694 // And Memory with Register
8695 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8696 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8697 effect(KILL cr);
8698
8699 ins_cost(150);
8700 format %{ "AND $dst,$src" %}
8701 opcode(0x21); /* Opcode 21 /r */
8702 ins_encode( OpcP, RegMem( src, dst ) );
8703 ins_pipe( ialu_mem_reg );
8704 %}
8705
8706 // And Memory with Immediate
8707 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8708 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8709 effect(KILL cr);
8710
8711 ins_cost(125);
8712 format %{ "AND $dst,$src" %}
8713 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8714 // ins_encode( MemImm( dst, src) );
8715 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8716 ins_pipe( ialu_mem_imm );
8717 %}
8718
8719 // Or Instructions
8720 // Or Register with Register
8721 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8722 match(Set dst (OrI dst src));
8723 effect(KILL cr);
8724
8725 size(2);
8726 format %{ "OR $dst,$src" %}
8727 opcode(0x0B);
8728 ins_encode( OpcP, RegReg( dst, src) );
8729 ins_pipe( ialu_reg_reg );
8730 %}
8731
8732 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8733 match(Set dst (OrI dst (CastP2X src)));
8734 effect(KILL cr);
8735
8736 size(2);
8737 format %{ "OR $dst,$src" %}
8738 opcode(0x0B);
8739 ins_encode( OpcP, RegReg( dst, src) );
8740 ins_pipe( ialu_reg_reg );
8741 %}
8742
8743
8744 // Or Register with Immediate
8745 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8746 match(Set dst (OrI dst src));
8747 effect(KILL cr);
8748
8749 format %{ "OR $dst,$src" %}
8750 opcode(0x81,0x01); /* Opcode 81 /1 id */
8751 // ins_encode( RegImm( dst, src) );
8752 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8753 ins_pipe( ialu_reg );
8754 %}
8755
8756 // Or Register with Memory
8757 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8758 match(Set dst (OrI dst (LoadI src)));
8759 effect(KILL cr);
8760
8761 ins_cost(125);
8762 format %{ "OR $dst,$src" %}
8763 opcode(0x0B);
8764 ins_encode( OpcP, RegMem( dst, src) );
8765 ins_pipe( ialu_reg_mem );
8766 %}
8767
8768 // Or Memory with Register
8769 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8770 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8771 effect(KILL cr);
8772
8773 ins_cost(150);
8774 format %{ "OR $dst,$src" %}
8775 opcode(0x09); /* Opcode 09 /r */
8776 ins_encode( OpcP, RegMem( src, dst ) );
8777 ins_pipe( ialu_mem_reg );
8778 %}
8779
8780 // Or Memory with Immediate
8781 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8782 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8783 effect(KILL cr);
8784
8785 ins_cost(125);
8786 format %{ "OR $dst,$src" %}
8787 opcode(0x81,0x1); /* Opcode 81 /1 id */
8788 // ins_encode( MemImm( dst, src) );
8789 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8790 ins_pipe( ialu_mem_imm );
8791 %}
8792
8793 // ROL/ROR
8794 // ROL expand
8795 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8796 effect(USE_DEF dst, USE shift, KILL cr);
8797
8798 format %{ "ROL $dst, $shift" %}
8799 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8800 ins_encode( OpcP, RegOpc( dst ));
8801 ins_pipe( ialu_reg );
8802 %}
8803
8804 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8805 effect(USE_DEF dst, USE shift, KILL cr);
8806
8807 format %{ "ROL $dst, $shift" %}
8808 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8809 ins_encode( RegOpcImm(dst, shift) );
8810 ins_pipe(ialu_reg);
8811 %}
8812
8813 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8814 effect(USE_DEF dst, USE shift, KILL cr);
8815
8816 format %{ "ROL $dst, $shift" %}
8817 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8818 ins_encode(OpcP, RegOpc(dst));
8819 ins_pipe( ialu_reg_reg );
8820 %}
8821 // end of ROL expand
8822
8823 // ROL 32bit by one once
8824 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8825 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8826
8827 expand %{
8828 rolI_eReg_imm1(dst, lshift, cr);
8829 %}
8830 %}
8831
8832 // ROL 32bit var by imm8 once
8833 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8834 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8835 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8836
8837 expand %{
8838 rolI_eReg_imm8(dst, lshift, cr);
8839 %}
8840 %}
8841
8842 // ROL 32bit var by var once
8843 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8844 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8845
8846 expand %{
8847 rolI_eReg_CL(dst, shift, cr);
8848 %}
8849 %}
8850
8851 // ROL 32bit var by var once
8852 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8853 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8854
8855 expand %{
8856 rolI_eReg_CL(dst, shift, cr);
8857 %}
8858 %}
8859
8860 // ROR expand
8861 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8862 effect(USE_DEF dst, USE shift, KILL cr);
8863
8864 format %{ "ROR $dst, $shift" %}
8865 opcode(0xD1,0x1); /* Opcode D1 /1 */
8866 ins_encode( OpcP, RegOpc( dst ) );
8867 ins_pipe( ialu_reg );
8868 %}
8869
8870 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8871 effect (USE_DEF dst, USE shift, KILL cr);
8872
8873 format %{ "ROR $dst, $shift" %}
8874 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8875 ins_encode( RegOpcImm(dst, shift) );
8876 ins_pipe( ialu_reg );
8877 %}
8878
8879 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8880 effect(USE_DEF dst, USE shift, KILL cr);
8881
8882 format %{ "ROR $dst, $shift" %}
8883 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8884 ins_encode(OpcP, RegOpc(dst));
8885 ins_pipe( ialu_reg_reg );
8886 %}
8887 // end of ROR expand
8888
8889 // ROR right once
8890 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8891 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8892
8893 expand %{
8894 rorI_eReg_imm1(dst, rshift, cr);
8895 %}
8896 %}
8897
8898 // ROR 32bit by immI8 once
8899 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8900 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8901 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8902
8903 expand %{
8904 rorI_eReg_imm8(dst, rshift, cr);
8905 %}
8906 %}
8907
8908 // ROR 32bit var by var once
8909 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8910 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8911
8912 expand %{
8913 rorI_eReg_CL(dst, shift, cr);
8914 %}
8915 %}
8916
8917 // ROR 32bit var by var once
8918 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8919 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8920
8921 expand %{
8922 rorI_eReg_CL(dst, shift, cr);
8923 %}
8924 %}
8925
8926 // Xor Instructions
8927 // Xor Register with Register
8928 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8929 match(Set dst (XorI dst src));
8930 effect(KILL cr);
8931
8932 size(2);
8933 format %{ "XOR $dst,$src" %}
8934 opcode(0x33);
8935 ins_encode( OpcP, RegReg( dst, src) );
8936 ins_pipe( ialu_reg_reg );
8937 %}
8938
8939 // Xor Register with Immediate -1
8940 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8941 match(Set dst (XorI dst imm));
8942
8943 size(2);
8944 format %{ "NOT $dst" %}
8945 ins_encode %{
8946 __ notl($dst$$Register);
8947 %}
8948 ins_pipe( ialu_reg );
8949 %}
8950
8951 // Xor Register with Immediate
8952 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8953 match(Set dst (XorI dst src));
8954 effect(KILL cr);
8955
8956 format %{ "XOR $dst,$src" %}
8957 opcode(0x81,0x06); /* Opcode 81 /6 id */
8958 // ins_encode( RegImm( dst, src) );
8959 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8960 ins_pipe( ialu_reg );
8961 %}
8962
8963 // Xor Register with Memory
8964 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8965 match(Set dst (XorI dst (LoadI src)));
8966 effect(KILL cr);
8967
8968 ins_cost(125);
8969 format %{ "XOR $dst,$src" %}
8970 opcode(0x33);
8971 ins_encode( OpcP, RegMem(dst, src) );
8972 ins_pipe( ialu_reg_mem );
8973 %}
8974
8975 // Xor Memory with Register
8976 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8977 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8978 effect(KILL cr);
8979
8980 ins_cost(150);
8981 format %{ "XOR $dst,$src" %}
8982 opcode(0x31); /* Opcode 31 /r */
8983 ins_encode( OpcP, RegMem( src, dst ) );
8984 ins_pipe( ialu_mem_reg );
8985 %}
8986
8987 // Xor Memory with Immediate
8988 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8989 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8990 effect(KILL cr);
8991
8992 ins_cost(125);
8993 format %{ "XOR $dst,$src" %}
8994 opcode(0x81,0x6); /* Opcode 81 /6 id */
8995 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8996 ins_pipe( ialu_mem_imm );
8997 %}
8998
8999 //----------Convert Int to Boolean---------------------------------------------
9000
9001 instruct movI_nocopy(eRegI dst, eRegI src) %{
9002 effect( DEF dst, USE src );
9003 format %{ "MOV $dst,$src" %}
9004 ins_encode( enc_Copy( dst, src) );
9005 ins_pipe( ialu_reg_reg );
9006 %}
9007
9008 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9009 effect( USE_DEF dst, USE src, KILL cr );
9010
9011 size(4);
9012 format %{ "NEG $dst\n\t"
9013 "ADC $dst,$src" %}
9014 ins_encode( neg_reg(dst),
9015 OpcRegReg(0x13,dst,src) );
9016 ins_pipe( ialu_reg_reg_long );
9017 %}
9018
9019 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9020 match(Set dst (Conv2B src));
9021
9022 expand %{
9023 movI_nocopy(dst,src);
9024 ci2b(dst,src,cr);
9025 %}
9026 %}
9027
9028 instruct movP_nocopy(eRegI dst, eRegP src) %{
9029 effect( DEF dst, USE src );
9030 format %{ "MOV $dst,$src" %}
9031 ins_encode( enc_Copy( dst, src) );
9032 ins_pipe( ialu_reg_reg );
9033 %}
9034
9035 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9036 effect( USE_DEF dst, USE src, KILL cr );
9037 format %{ "NEG $dst\n\t"
9038 "ADC $dst,$src" %}
9039 ins_encode( neg_reg(dst),
9040 OpcRegReg(0x13,dst,src) );
9041 ins_pipe( ialu_reg_reg_long );
9042 %}
9043
9044 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9045 match(Set dst (Conv2B src));
9046
9047 expand %{
9048 movP_nocopy(dst,src);
9049 cp2b(dst,src,cr);
9050 %}
9051 %}
9052
9053 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9054 match(Set dst (CmpLTMask p q));
9055 effect( KILL cr );
9056 ins_cost(400);
9057
9058 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9059 format %{ "XOR $dst,$dst\n\t"
9060 "CMP $p,$q\n\t"
9061 "SETlt $dst\n\t"
9062 "NEG $dst" %}
9063 ins_encode( OpcRegReg(0x33,dst,dst),
9064 OpcRegReg(0x3B,p,q),
9065 setLT_reg(dst), neg_reg(dst) );
9066 ins_pipe( pipe_slow );
9067 %}
9068
9069 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9070 match(Set dst (CmpLTMask dst zero));
9071 effect( DEF dst, KILL cr );
9072 ins_cost(100);
9073
9074 format %{ "SAR $dst,31" %}
9075 opcode(0xC1, 0x7); /* C1 /7 ib */
9076 ins_encode( RegOpcImm( dst, 0x1F ) );
9077 ins_pipe( ialu_reg );
9078 %}
9079
9080
9081 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9082 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9083 effect( KILL tmp, KILL cr );
9084 ins_cost(400);
9085 // annoyingly, $tmp has no edges so you cant ask for it in
9086 // any format or encoding
9087 format %{ "SUB $p,$q\n\t"
9088 "SBB ECX,ECX\n\t"
9089 "AND ECX,$y\n\t"
9090 "ADD $p,ECX" %}
9091 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9092 ins_pipe( pipe_cmplt );
9093 %}
9094
9095 /* If I enable this, I encourage spilling in the inner loop of compress.
9096 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9097 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9098 effect( USE_KILL tmp, KILL cr );
9099 ins_cost(400);
9100
9101 format %{ "SUB $p,$q\n\t"
9102 "SBB ECX,ECX\n\t"
9103 "AND ECX,$y\n\t"
9104 "ADD $p,ECX" %}
9105 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9106 %}
9107 */
9108
9109 //----------Long Instructions------------------------------------------------
9110 // Add Long Register with Register
9111 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9112 match(Set dst (AddL dst src));
9113 effect(KILL cr);
9114 ins_cost(200);
9115 format %{ "ADD $dst.lo,$src.lo\n\t"
9116 "ADC $dst.hi,$src.hi" %}
9117 opcode(0x03, 0x13);
9118 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9119 ins_pipe( ialu_reg_reg_long );
9120 %}
9121
9122 // Add Long Register with Immediate
9123 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9124 match(Set dst (AddL dst src));
9125 effect(KILL cr);
9126 format %{ "ADD $dst.lo,$src.lo\n\t"
9127 "ADC $dst.hi,$src.hi" %}
9128 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9129 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9130 ins_pipe( ialu_reg_long );
9131 %}
9132
9133 // Add Long Register with Memory
9134 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9135 match(Set dst (AddL dst (LoadL mem)));
9136 effect(KILL cr);
9137 ins_cost(125);
9138 format %{ "ADD $dst.lo,$mem\n\t"
9139 "ADC $dst.hi,$mem+4" %}
9140 opcode(0x03, 0x13);
9141 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9142 ins_pipe( ialu_reg_long_mem );
9143 %}
9144
9145 // Subtract Long Register with Register.
9146 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9147 match(Set dst (SubL dst src));
9148 effect(KILL cr);
9149 ins_cost(200);
9150 format %{ "SUB $dst.lo,$src.lo\n\t"
9151 "SBB $dst.hi,$src.hi" %}
9152 opcode(0x2B, 0x1B);
9153 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9154 ins_pipe( ialu_reg_reg_long );
9155 %}
9156
9157 // Subtract Long Register with Immediate
9158 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9159 match(Set dst (SubL dst src));
9160 effect(KILL cr);
9161 format %{ "SUB $dst.lo,$src.lo\n\t"
9162 "SBB $dst.hi,$src.hi" %}
9163 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9164 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9165 ins_pipe( ialu_reg_long );
9166 %}
9167
9168 // Subtract Long Register with Memory
9169 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9170 match(Set dst (SubL dst (LoadL mem)));
9171 effect(KILL cr);
9172 ins_cost(125);
9173 format %{ "SUB $dst.lo,$mem\n\t"
9174 "SBB $dst.hi,$mem+4" %}
9175 opcode(0x2B, 0x1B);
9176 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9177 ins_pipe( ialu_reg_long_mem );
9178 %}
9179
9180 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9181 match(Set dst (SubL zero dst));
9182 effect(KILL cr);
9183 ins_cost(300);
9184 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9185 ins_encode( neg_long(dst) );
9186 ins_pipe( ialu_reg_reg_long );
9187 %}
9188
9189 // And Long Register with Register
9190 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9191 match(Set dst (AndL dst src));
9192 effect(KILL cr);
9193 format %{ "AND $dst.lo,$src.lo\n\t"
9194 "AND $dst.hi,$src.hi" %}
9195 opcode(0x23,0x23);
9196 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9197 ins_pipe( ialu_reg_reg_long );
9198 %}
9199
9200 // And Long Register with Immediate
9201 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9202 match(Set dst (AndL dst src));
9203 effect(KILL cr);
9204 format %{ "AND $dst.lo,$src.lo\n\t"
9205 "AND $dst.hi,$src.hi" %}
9206 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9207 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9208 ins_pipe( ialu_reg_long );
9209 %}
9210
9211 // And Long Register with Memory
9212 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9213 match(Set dst (AndL dst (LoadL mem)));
9214 effect(KILL cr);
9215 ins_cost(125);
9216 format %{ "AND $dst.lo,$mem\n\t"
9217 "AND $dst.hi,$mem+4" %}
9218 opcode(0x23, 0x23);
9219 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9220 ins_pipe( ialu_reg_long_mem );
9221 %}
9222
9223 // Or Long Register with Register
9224 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9225 match(Set dst (OrL dst src));
9226 effect(KILL cr);
9227 format %{ "OR $dst.lo,$src.lo\n\t"
9228 "OR $dst.hi,$src.hi" %}
9229 opcode(0x0B,0x0B);
9230 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9231 ins_pipe( ialu_reg_reg_long );
9232 %}
9233
9234 // Or Long Register with Immediate
9235 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9236 match(Set dst (OrL dst src));
9237 effect(KILL cr);
9238 format %{ "OR $dst.lo,$src.lo\n\t"
9239 "OR $dst.hi,$src.hi" %}
9240 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9241 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9242 ins_pipe( ialu_reg_long );
9243 %}
9244
9245 // Or Long Register with Memory
9246 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9247 match(Set dst (OrL dst (LoadL mem)));
9248 effect(KILL cr);
9249 ins_cost(125);
9250 format %{ "OR $dst.lo,$mem\n\t"
9251 "OR $dst.hi,$mem+4" %}
9252 opcode(0x0B,0x0B);
9253 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9254 ins_pipe( ialu_reg_long_mem );
9255 %}
9256
9257 // Xor Long Register with Register
9258 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9259 match(Set dst (XorL dst src));
9260 effect(KILL cr);
9261 format %{ "XOR $dst.lo,$src.lo\n\t"
9262 "XOR $dst.hi,$src.hi" %}
9263 opcode(0x33,0x33);
9264 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9265 ins_pipe( ialu_reg_reg_long );
9266 %}
9267
9268 // Xor Long Register with Immediate -1
9269 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9270 match(Set dst (XorL dst imm));
9271 format %{ "NOT $dst.lo\n\t"
9272 "NOT $dst.hi" %}
9273 ins_encode %{
9274 __ notl($dst$$Register);
9275 __ notl(HIGH_FROM_LOW($dst$$Register));
9276 %}
9277 ins_pipe( ialu_reg_long );
9278 %}
9279
9280 // Xor Long Register with Immediate
9281 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9282 match(Set dst (XorL dst src));
9283 effect(KILL cr);
9284 format %{ "XOR $dst.lo,$src.lo\n\t"
9285 "XOR $dst.hi,$src.hi" %}
9286 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9287 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9288 ins_pipe( ialu_reg_long );
9289 %}
9290
9291 // Xor Long Register with Memory
9292 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9293 match(Set dst (XorL dst (LoadL mem)));
9294 effect(KILL cr);
9295 ins_cost(125);
9296 format %{ "XOR $dst.lo,$mem\n\t"
9297 "XOR $dst.hi,$mem+4" %}
9298 opcode(0x33,0x33);
9299 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9300 ins_pipe( ialu_reg_long_mem );
9301 %}
9302
9303 // Shift Left Long by 1
9304 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9305 predicate(UseNewLongLShift);
9306 match(Set dst (LShiftL dst cnt));
9307 effect(KILL cr);
9308 ins_cost(100);
9309 format %{ "ADD $dst.lo,$dst.lo\n\t"
9310 "ADC $dst.hi,$dst.hi" %}
9311 ins_encode %{
9312 __ addl($dst$$Register,$dst$$Register);
9313 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9314 %}
9315 ins_pipe( ialu_reg_long );
9316 %}
9317
9318 // Shift Left Long by 2
9319 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9320 predicate(UseNewLongLShift);
9321 match(Set dst (LShiftL dst cnt));
9322 effect(KILL cr);
9323 ins_cost(100);
9324 format %{ "ADD $dst.lo,$dst.lo\n\t"
9325 "ADC $dst.hi,$dst.hi\n\t"
9326 "ADD $dst.lo,$dst.lo\n\t"
9327 "ADC $dst.hi,$dst.hi" %}
9328 ins_encode %{
9329 __ addl($dst$$Register,$dst$$Register);
9330 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9331 __ addl($dst$$Register,$dst$$Register);
9332 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9333 %}
9334 ins_pipe( ialu_reg_long );
9335 %}
9336
9337 // Shift Left Long by 3
9338 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9339 predicate(UseNewLongLShift);
9340 match(Set dst (LShiftL dst cnt));
9341 effect(KILL cr);
9342 ins_cost(100);
9343 format %{ "ADD $dst.lo,$dst.lo\n\t"
9344 "ADC $dst.hi,$dst.hi\n\t"
9345 "ADD $dst.lo,$dst.lo\n\t"
9346 "ADC $dst.hi,$dst.hi\n\t"
9347 "ADD $dst.lo,$dst.lo\n\t"
9348 "ADC $dst.hi,$dst.hi" %}
9349 ins_encode %{
9350 __ addl($dst$$Register,$dst$$Register);
9351 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9352 __ addl($dst$$Register,$dst$$Register);
9353 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9354 __ addl($dst$$Register,$dst$$Register);
9355 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9356 %}
9357 ins_pipe( ialu_reg_long );
9358 %}
9359
9360 // Shift Left Long by 1-31
9361 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9362 match(Set dst (LShiftL dst cnt));
9363 effect(KILL cr);
9364 ins_cost(200);
9365 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9366 "SHL $dst.lo,$cnt" %}
9367 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9368 ins_encode( move_long_small_shift(dst,cnt) );
9369 ins_pipe( ialu_reg_long );
9370 %}
9371
9372 // Shift Left Long by 32-63
9373 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9374 match(Set dst (LShiftL dst cnt));
9375 effect(KILL cr);
9376 ins_cost(300);
9377 format %{ "MOV $dst.hi,$dst.lo\n"
9378 "\tSHL $dst.hi,$cnt-32\n"
9379 "\tXOR $dst.lo,$dst.lo" %}
9380 opcode(0xC1, 0x4); /* C1 /4 ib */
9381 ins_encode( move_long_big_shift_clr(dst,cnt) );
9382 ins_pipe( ialu_reg_long );
9383 %}
9384
9385 // Shift Left Long by variable
9386 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9387 match(Set dst (LShiftL dst shift));
9388 effect(KILL cr);
9389 ins_cost(500+200);
9390 size(17);
9391 format %{ "TEST $shift,32\n\t"
9392 "JEQ,s small\n\t"
9393 "MOV $dst.hi,$dst.lo\n\t"
9394 "XOR $dst.lo,$dst.lo\n"
9395 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9396 "SHL $dst.lo,$shift" %}
9397 ins_encode( shift_left_long( dst, shift ) );
9398 ins_pipe( pipe_slow );
9399 %}
9400
9401 // Shift Right Long by 1-31
9402 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9403 match(Set dst (URShiftL dst cnt));
9404 effect(KILL cr);
9405 ins_cost(200);
9406 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9407 "SHR $dst.hi,$cnt" %}
9408 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9409 ins_encode( move_long_small_shift(dst,cnt) );
9410 ins_pipe( ialu_reg_long );
9411 %}
9412
9413 // Shift Right Long by 32-63
9414 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9415 match(Set dst (URShiftL dst cnt));
9416 effect(KILL cr);
9417 ins_cost(300);
9418 format %{ "MOV $dst.lo,$dst.hi\n"
9419 "\tSHR $dst.lo,$cnt-32\n"
9420 "\tXOR $dst.hi,$dst.hi" %}
9421 opcode(0xC1, 0x5); /* C1 /5 ib */
9422 ins_encode( move_long_big_shift_clr(dst,cnt) );
9423 ins_pipe( ialu_reg_long );
9424 %}
9425
9426 // Shift Right Long by variable
9427 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9428 match(Set dst (URShiftL dst shift));
9429 effect(KILL cr);
9430 ins_cost(600);
9431 size(17);
9432 format %{ "TEST $shift,32\n\t"
9433 "JEQ,s small\n\t"
9434 "MOV $dst.lo,$dst.hi\n\t"
9435 "XOR $dst.hi,$dst.hi\n"
9436 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9437 "SHR $dst.hi,$shift" %}
9438 ins_encode( shift_right_long( dst, shift ) );
9439 ins_pipe( pipe_slow );
9440 %}
9441
9442 // Shift Right Long by 1-31
9443 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9444 match(Set dst (RShiftL dst cnt));
9445 effect(KILL cr);
9446 ins_cost(200);
9447 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9448 "SAR $dst.hi,$cnt" %}
9449 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9450 ins_encode( move_long_small_shift(dst,cnt) );
9451 ins_pipe( ialu_reg_long );
9452 %}
9453
9454 // Shift Right Long by 32-63
9455 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9456 match(Set dst (RShiftL dst cnt));
9457 effect(KILL cr);
9458 ins_cost(300);
9459 format %{ "MOV $dst.lo,$dst.hi\n"
9460 "\tSAR $dst.lo,$cnt-32\n"
9461 "\tSAR $dst.hi,31" %}
9462 opcode(0xC1, 0x7); /* C1 /7 ib */
9463 ins_encode( move_long_big_shift_sign(dst,cnt) );
9464 ins_pipe( ialu_reg_long );
9465 %}
9466
9467 // Shift Right arithmetic Long by variable
9468 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9469 match(Set dst (RShiftL dst shift));
9470 effect(KILL cr);
9471 ins_cost(600);
9472 size(18);
9473 format %{ "TEST $shift,32\n\t"
9474 "JEQ,s small\n\t"
9475 "MOV $dst.lo,$dst.hi\n\t"
9476 "SAR $dst.hi,31\n"
9477 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9478 "SAR $dst.hi,$shift" %}
9479 ins_encode( shift_right_arith_long( dst, shift ) );
9480 ins_pipe( pipe_slow );
9481 %}
9482
9483
9484 //----------Double Instructions------------------------------------------------
9485 // Double Math
9486
9487 // Compare & branch
9488
9489 // P6 version of float compare, sets condition codes in EFLAGS
9490 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9491 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9492 match(Set cr (CmpD src1 src2));
9493 effect(KILL rax);
9494 ins_cost(150);
9495 format %{ "FLD $src1\n\t"
9496 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9497 "JNP exit\n\t"
9498 "MOV ah,1 // saw a NaN, set CF\n\t"
9499 "SAHF\n"
9500 "exit:\tNOP // avoid branch to branch" %}
9501 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9502 ins_encode( Push_Reg_DPR(src1),
9503 OpcP, RegOpc(src2),
9504 cmpF_P6_fixup );
9505 ins_pipe( pipe_slow );
9506 %}
9507
9508 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9509 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9510 match(Set cr (CmpD src1 src2));
9511 ins_cost(150);
9512 format %{ "FLD $src1\n\t"
9513 "FUCOMIP ST,$src2 // P6 instruction" %}
9514 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9515 ins_encode( Push_Reg_DPR(src1),
9516 OpcP, RegOpc(src2));
9517 ins_pipe( pipe_slow );
9518 %}
9519
9520 // Compare & branch
9521 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9522 predicate(UseSSE<=1);
9523 match(Set cr (CmpD src1 src2));
9524 effect(KILL rax);
9525 ins_cost(200);
9526 format %{ "FLD $src1\n\t"
9527 "FCOMp $src2\n\t"
9528 "FNSTSW AX\n\t"
9529 "TEST AX,0x400\n\t"
9530 "JZ,s flags\n\t"
9531 "MOV AH,1\t# unordered treat as LT\n"
9532 "flags:\tSAHF" %}
9533 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9534 ins_encode( Push_Reg_DPR(src1),
9535 OpcP, RegOpc(src2),
9536 fpu_flags);
9537 ins_pipe( pipe_slow );
9538 %}
9539
9540 // Compare vs zero into -1,0,1
9541 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9542 predicate(UseSSE<=1);
9543 match(Set dst (CmpD3 src1 zero));
9544 effect(KILL cr, KILL rax);
9545 ins_cost(280);
9546 format %{ "FTSTD $dst,$src1" %}
9547 opcode(0xE4, 0xD9);
9548 ins_encode( Push_Reg_DPR(src1),
9549 OpcS, OpcP, PopFPU,
9550 CmpF_Result(dst));
9551 ins_pipe( pipe_slow );
9552 %}
9553
9554 // Compare into -1,0,1
9555 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9556 predicate(UseSSE<=1);
9557 match(Set dst (CmpD3 src1 src2));
9558 effect(KILL cr, KILL rax);
9559 ins_cost(300);
9560 format %{ "FCMPD $dst,$src1,$src2" %}
9561 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9562 ins_encode( Push_Reg_DPR(src1),
9563 OpcP, RegOpc(src2),
9564 CmpF_Result(dst));
9565 ins_pipe( pipe_slow );
9566 %}
9567
9568 // float compare and set condition codes in EFLAGS by XMM regs
9569 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9570 predicate(UseSSE>=2);
9571 match(Set cr (CmpD src1 src2));
9572 ins_cost(145);
9573 format %{ "UCOMISD $src1,$src2\n\t"
9574 "JNP,s exit\n\t"
9575 "PUSHF\t# saw NaN, set CF\n\t"
9576 "AND [rsp], #0xffffff2b\n\t"
9577 "POPF\n"
9578 "exit:" %}
9579 ins_encode %{
9580 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9581 emit_cmpfp_fixup(_masm);
9582 %}
9583 ins_pipe( pipe_slow );
9584 %}
9585
9586 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9587 predicate(UseSSE>=2);
9588 match(Set cr (CmpD src1 src2));
9589 ins_cost(100);
9590 format %{ "UCOMISD $src1,$src2" %}
9591 ins_encode %{
9592 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9593 %}
9594 ins_pipe( pipe_slow );
9595 %}
9596
9597 // float compare and set condition codes in EFLAGS by XMM regs
9598 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9599 predicate(UseSSE>=2);
9600 match(Set cr (CmpD src1 (LoadD src2)));
9601 ins_cost(145);
9602 format %{ "UCOMISD $src1,$src2\n\t"
9603 "JNP,s exit\n\t"
9604 "PUSHF\t# saw NaN, set CF\n\t"
9605 "AND [rsp], #0xffffff2b\n\t"
9606 "POPF\n"
9607 "exit:" %}
9608 ins_encode %{
9609 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9610 emit_cmpfp_fixup(_masm);
9611 %}
9612 ins_pipe( pipe_slow );
9613 %}
9614
9615 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9616 predicate(UseSSE>=2);
9617 match(Set cr (CmpD src1 (LoadD src2)));
9618 ins_cost(100);
9619 format %{ "UCOMISD $src1,$src2" %}
9620 ins_encode %{
9621 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9622 %}
9623 ins_pipe( pipe_slow );
9624 %}
9625
9626 // Compare into -1,0,1 in XMM
9627 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9628 predicate(UseSSE>=2);
9629 match(Set dst (CmpD3 src1 src2));
9630 effect(KILL cr);
9631 ins_cost(255);
9632 format %{ "UCOMISD $src1, $src2\n\t"
9633 "MOV $dst, #-1\n\t"
9634 "JP,s done\n\t"
9635 "JB,s done\n\t"
9636 "SETNE $dst\n\t"
9637 "MOVZB $dst, $dst\n"
9638 "done:" %}
9639 ins_encode %{
9640 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9641 emit_cmpfp3(_masm, $dst$$Register);
9642 %}
9643 ins_pipe( pipe_slow );
9644 %}
9645
9646 // Compare into -1,0,1 in XMM and memory
9647 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9648 predicate(UseSSE>=2);
9649 match(Set dst (CmpD3 src1 (LoadD src2)));
9650 effect(KILL cr);
9651 ins_cost(275);
9652 format %{ "UCOMISD $src1, $src2\n\t"
9653 "MOV $dst, #-1\n\t"
9654 "JP,s done\n\t"
9655 "JB,s done\n\t"
9656 "SETNE $dst\n\t"
9657 "MOVZB $dst, $dst\n"
9658 "done:" %}
9659 ins_encode %{
9660 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9661 emit_cmpfp3(_masm, $dst$$Register);
9662 %}
9663 ins_pipe( pipe_slow );
9664 %}
9665
9666
9667 instruct subDPR_reg(regDPR dst, regDPR src) %{
9668 predicate (UseSSE <=1);
9669 match(Set dst (SubD dst src));
9670
9671 format %{ "FLD $src\n\t"
9672 "DSUBp $dst,ST" %}
9673 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9674 ins_cost(150);
9675 ins_encode( Push_Reg_DPR(src),
9676 OpcP, RegOpc(dst) );
9677 ins_pipe( fpu_reg_reg );
9678 %}
9679
9680 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9681 predicate (UseSSE <=1);
9682 match(Set dst (RoundDouble (SubD src1 src2)));
9683 ins_cost(250);
9684
9685 format %{ "FLD $src2\n\t"
9686 "DSUB ST,$src1\n\t"
9687 "FSTP_D $dst\t# D-round" %}
9688 opcode(0xD8, 0x5);
9689 ins_encode( Push_Reg_DPR(src2),
9690 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9691 ins_pipe( fpu_mem_reg_reg );
9692 %}
9693
9694
9695 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9696 predicate (UseSSE <=1);
9697 match(Set dst (SubD dst (LoadD src)));
9698 ins_cost(150);
9699
9700 format %{ "FLD $src\n\t"
9701 "DSUBp $dst,ST" %}
9702 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9703 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9704 OpcP, RegOpc(dst) );
9705 ins_pipe( fpu_reg_mem );
9706 %}
9707
9708 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9709 predicate (UseSSE<=1);
9710 match(Set dst (AbsD src));
9711 ins_cost(100);
9712 format %{ "FABS" %}
9713 opcode(0xE1, 0xD9);
9714 ins_encode( OpcS, OpcP );
9715 ins_pipe( fpu_reg_reg );
9716 %}
9717
9718 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9719 predicate(UseSSE<=1);
9720 match(Set dst (NegD src));
9721 ins_cost(100);
9722 format %{ "FCHS" %}
9723 opcode(0xE0, 0xD9);
9724 ins_encode( OpcS, OpcP );
9725 ins_pipe( fpu_reg_reg );
9726 %}
9727
9728 instruct addDPR_reg(regDPR dst, regDPR src) %{
9729 predicate(UseSSE<=1);
9730 match(Set dst (AddD dst src));
9731 format %{ "FLD $src\n\t"
9732 "DADD $dst,ST" %}
9733 size(4);
9734 ins_cost(150);
9735 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9736 ins_encode( Push_Reg_DPR(src),
9737 OpcP, RegOpc(dst) );
9738 ins_pipe( fpu_reg_reg );
9739 %}
9740
9741
9742 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9743 predicate(UseSSE<=1);
9744 match(Set dst (RoundDouble (AddD src1 src2)));
9745 ins_cost(250);
9746
9747 format %{ "FLD $src2\n\t"
9748 "DADD ST,$src1\n\t"
9749 "FSTP_D $dst\t# D-round" %}
9750 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9751 ins_encode( Push_Reg_DPR(src2),
9752 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9753 ins_pipe( fpu_mem_reg_reg );
9754 %}
9755
9756
9757 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9758 predicate(UseSSE<=1);
9759 match(Set dst (AddD dst (LoadD src)));
9760 ins_cost(150);
9761
9762 format %{ "FLD $src\n\t"
9763 "DADDp $dst,ST" %}
9764 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9765 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9766 OpcP, RegOpc(dst) );
9767 ins_pipe( fpu_reg_mem );
9768 %}
9769
9770 // add-to-memory
9771 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9772 predicate(UseSSE<=1);
9773 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9774 ins_cost(150);
9775
9776 format %{ "FLD_D $dst\n\t"
9777 "DADD ST,$src\n\t"
9778 "FST_D $dst" %}
9779 opcode(0xDD, 0x0);
9780 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9781 Opcode(0xD8), RegOpc(src),
9782 set_instruction_start,
9783 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9784 ins_pipe( fpu_reg_mem );
9785 %}
9786
9787 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9788 predicate(UseSSE<=1);
9789 match(Set dst (AddD dst con));
9790 ins_cost(125);
9791 format %{ "FLD1\n\t"
9792 "DADDp $dst,ST" %}
9793 ins_encode %{
9794 __ fld1();
9795 __ faddp($dst$$reg);
9796 %}
9797 ins_pipe(fpu_reg);
9798 %}
9799
9800 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9801 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9802 match(Set dst (AddD dst con));
9803 ins_cost(200);
9804 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9805 "DADDp $dst,ST" %}
9806 ins_encode %{
9807 __ fld_d($constantaddress($con));
9808 __ faddp($dst$$reg);
9809 %}
9810 ins_pipe(fpu_reg_mem);
9811 %}
9812
9813 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9814 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9815 match(Set dst (RoundDouble (AddD src con)));
9816 ins_cost(200);
9817 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9818 "DADD ST,$src\n\t"
9819 "FSTP_D $dst\t# D-round" %}
9820 ins_encode %{
9821 __ fld_d($constantaddress($con));
9822 __ fadd($src$$reg);
9823 __ fstp_d(Address(rsp, $dst$$disp));
9824 %}
9825 ins_pipe(fpu_mem_reg_con);
9826 %}
9827
9828 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9829 predicate(UseSSE<=1);
9830 match(Set dst (MulD dst src));
9831 format %{ "FLD $src\n\t"
9832 "DMULp $dst,ST" %}
9833 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9834 ins_cost(150);
9835 ins_encode( Push_Reg_DPR(src),
9836 OpcP, RegOpc(dst) );
9837 ins_pipe( fpu_reg_reg );
9838 %}
9839
9840 // Strict FP instruction biases argument before multiply then
9841 // biases result to avoid double rounding of subnormals.
9842 //
9843 // scale arg1 by multiplying arg1 by 2^(-15360)
9844 // load arg2
9845 // multiply scaled arg1 by arg2
9846 // rescale product by 2^(15360)
9847 //
9848 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9849 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9850 match(Set dst (MulD dst src));
9851 ins_cost(1); // Select this instruction for all strict FP double multiplies
9852
9853 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9854 "DMULp $dst,ST\n\t"
9855 "FLD $src\n\t"
9856 "DMULp $dst,ST\n\t"
9857 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9858 "DMULp $dst,ST\n\t" %}
9859 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9860 ins_encode( strictfp_bias1(dst),
9861 Push_Reg_DPR(src),
9862 OpcP, RegOpc(dst),
9863 strictfp_bias2(dst) );
9864 ins_pipe( fpu_reg_reg );
9865 %}
9866
9867 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9868 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9869 match(Set dst (MulD dst con));
9870 ins_cost(200);
9871 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9872 "DMULp $dst,ST" %}
9873 ins_encode %{
9874 __ fld_d($constantaddress($con));
9875 __ fmulp($dst$$reg);
9876 %}
9877 ins_pipe(fpu_reg_mem);
9878 %}
9879
9880
9881 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9882 predicate( UseSSE<=1 );
9883 match(Set dst (MulD dst (LoadD src)));
9884 ins_cost(200);
9885 format %{ "FLD_D $src\n\t"
9886 "DMULp $dst,ST" %}
9887 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9888 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9889 OpcP, RegOpc(dst) );
9890 ins_pipe( fpu_reg_mem );
9891 %}
9892
9893 //
9894 // Cisc-alternate to reg-reg multiply
9895 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9896 predicate( UseSSE<=1 );
9897 match(Set dst (MulD src (LoadD mem)));
9898 ins_cost(250);
9899 format %{ "FLD_D $mem\n\t"
9900 "DMUL ST,$src\n\t"
9901 "FSTP_D $dst" %}
9902 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9903 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9904 OpcReg_FPR(src),
9905 Pop_Reg_DPR(dst) );
9906 ins_pipe( fpu_reg_reg_mem );
9907 %}
9908
9909
9910 // MACRO3 -- addDPR a mulDPR
9911 // This instruction is a '2-address' instruction in that the result goes
9912 // back to src2. This eliminates a move from the macro; possibly the
9913 // register allocator will have to add it back (and maybe not).
9914 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9915 predicate( UseSSE<=1 );
9916 match(Set src2 (AddD (MulD src0 src1) src2));
9917 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9918 "DMUL ST,$src1\n\t"
9919 "DADDp $src2,ST" %}
9920 ins_cost(250);
9921 opcode(0xDD); /* LoadD DD /0 */
9922 ins_encode( Push_Reg_FPR(src0),
9923 FMul_ST_reg(src1),
9924 FAddP_reg_ST(src2) );
9925 ins_pipe( fpu_reg_reg_reg );
9926 %}
9927
9928
9929 // MACRO3 -- subDPR a mulDPR
9930 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9931 predicate( UseSSE<=1 );
9932 match(Set src2 (SubD (MulD src0 src1) src2));
9933 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9934 "DMUL ST,$src1\n\t"
9935 "DSUBRp $src2,ST" %}
9936 ins_cost(250);
9937 ins_encode( Push_Reg_FPR(src0),
9938 FMul_ST_reg(src1),
9939 Opcode(0xDE), Opc_plus(0xE0,src2));
9940 ins_pipe( fpu_reg_reg_reg );
9941 %}
9942
9943
9944 instruct divDPR_reg(regDPR dst, regDPR src) %{
9945 predicate( UseSSE<=1 );
9946 match(Set dst (DivD dst src));
9947
9948 format %{ "FLD $src\n\t"
9949 "FDIVp $dst,ST" %}
9950 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9951 ins_cost(150);
9952 ins_encode( Push_Reg_DPR(src),
9953 OpcP, RegOpc(dst) );
9954 ins_pipe( fpu_reg_reg );
9955 %}
9956
9957 // Strict FP instruction biases argument before division then
9958 // biases result, to avoid double rounding of subnormals.
9959 //
9960 // scale dividend by multiplying dividend by 2^(-15360)
9961 // load divisor
9962 // divide scaled dividend by divisor
9963 // rescale quotient by 2^(15360)
9964 //
9965 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9966 predicate (UseSSE<=1);
9967 match(Set dst (DivD dst src));
9968 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9969 ins_cost(01);
9970
9971 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9972 "DMULp $dst,ST\n\t"
9973 "FLD $src\n\t"
9974 "FDIVp $dst,ST\n\t"
9975 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9976 "DMULp $dst,ST\n\t" %}
9977 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9978 ins_encode( strictfp_bias1(dst),
9979 Push_Reg_DPR(src),
9980 OpcP, RegOpc(dst),
9981 strictfp_bias2(dst) );
9982 ins_pipe( fpu_reg_reg );
9983 %}
9984
9985 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9986 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9987 match(Set dst (RoundDouble (DivD src1 src2)));
9988
9989 format %{ "FLD $src1\n\t"
9990 "FDIV ST,$src2\n\t"
9991 "FSTP_D $dst\t# D-round" %}
9992 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9993 ins_encode( Push_Reg_DPR(src1),
9994 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9995 ins_pipe( fpu_mem_reg_reg );
9996 %}
9997
9998
9999 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
10000 predicate(UseSSE<=1);
10001 match(Set dst (ModD dst src));
10002 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10003
10004 format %{ "DMOD $dst,$src" %}
10005 ins_cost(250);
10006 ins_encode(Push_Reg_Mod_DPR(dst, src),
10007 emitModDPR(),
10008 Push_Result_Mod_DPR(src),
10009 Pop_Reg_DPR(dst));
10010 ins_pipe( pipe_slow );
10011 %}
10012
10013 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10014 predicate(UseSSE>=2);
10015 match(Set dst (ModD src0 src1));
10016 effect(KILL rax, KILL cr);
10017
10018 format %{ "SUB ESP,8\t # DMOD\n"
10019 "\tMOVSD [ESP+0],$src1\n"
10020 "\tFLD_D [ESP+0]\n"
10021 "\tMOVSD [ESP+0],$src0\n"
10022 "\tFLD_D [ESP+0]\n"
10023 "loop:\tFPREM\n"
10024 "\tFWAIT\n"
10025 "\tFNSTSW AX\n"
10026 "\tSAHF\n"
10027 "\tJP loop\n"
10028 "\tFSTP_D [ESP+0]\n"
10029 "\tMOVSD $dst,[ESP+0]\n"
10030 "\tADD ESP,8\n"
10031 "\tFSTP ST0\t # Restore FPU Stack"
10032 %}
10033 ins_cost(250);
10034 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10035 ins_pipe( pipe_slow );
10036 %}
10037
10038 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10039 predicate (UseSSE<=1);
10040 match(Set dst (SinD src));
10041 ins_cost(1800);
10042 format %{ "DSIN $dst" %}
10043 opcode(0xD9, 0xFE);
10044 ins_encode( OpcP, OpcS );
10045 ins_pipe( pipe_slow );
10046 %}
10047
10048 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10049 predicate (UseSSE>=2);
10050 match(Set dst (SinD dst));
10051 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10052 ins_cost(1800);
10053 format %{ "DSIN $dst" %}
10054 opcode(0xD9, 0xFE);
10055 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10056 ins_pipe( pipe_slow );
10057 %}
10058
10059 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10060 predicate (UseSSE<=1);
10061 match(Set dst (CosD src));
10062 ins_cost(1800);
10063 format %{ "DCOS $dst" %}
10064 opcode(0xD9, 0xFF);
10065 ins_encode( OpcP, OpcS );
10066 ins_pipe( pipe_slow );
10067 %}
10068
10069 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10070 predicate (UseSSE>=2);
10071 match(Set dst (CosD dst));
10072 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10073 ins_cost(1800);
10074 format %{ "DCOS $dst" %}
10075 opcode(0xD9, 0xFF);
10076 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10077 ins_pipe( pipe_slow );
10078 %}
10079
10080 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10081 predicate (UseSSE<=1);
10082 match(Set dst(TanD src));
10083 format %{ "DTAN $dst" %}
10084 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10085 Opcode(0xDD), Opcode(0xD8)); // fstp st
10086 ins_pipe( pipe_slow );
10087 %}
10088
10089 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10090 predicate (UseSSE>=2);
10091 match(Set dst(TanD dst));
10092 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10093 format %{ "DTAN $dst" %}
10094 ins_encode( Push_SrcD(dst),
10095 Opcode(0xD9), Opcode(0xF2), // fptan
10096 Opcode(0xDD), Opcode(0xD8), // fstp st
10097 Push_ResultD(dst) );
10098 ins_pipe( pipe_slow );
10099 %}
10100
10101 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10102 predicate (UseSSE<=1);
10103 match(Set dst(AtanD dst src));
10104 format %{ "DATA $dst,$src" %}
10105 opcode(0xD9, 0xF3);
10106 ins_encode( Push_Reg_DPR(src),
10107 OpcP, OpcS, RegOpc(dst) );
10108 ins_pipe( pipe_slow );
10109 %}
10110
10111 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10112 predicate (UseSSE>=2);
10113 match(Set dst(AtanD dst src));
10114 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10115 format %{ "DATA $dst,$src" %}
10116 opcode(0xD9, 0xF3);
10117 ins_encode( Push_SrcD(src),
10118 OpcP, OpcS, Push_ResultD(dst) );
10119 ins_pipe( pipe_slow );
10120 %}
10121
10122 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10123 predicate (UseSSE<=1);
10124 match(Set dst (SqrtD src));
10125 format %{ "DSQRT $dst,$src" %}
10126 opcode(0xFA, 0xD9);
10127 ins_encode( Push_Reg_DPR(src),
10128 OpcS, OpcP, Pop_Reg_DPR(dst) );
10129 ins_pipe( pipe_slow );
10130 %}
10131
10132 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10133 predicate (UseSSE<=1);
10134 match(Set Y (PowD X Y)); // Raise X to the Yth power
10135 effect(KILL rax, KILL rbx, KILL rcx);
10136 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10137 "FLD_D $X\n\t"
10138 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10139
10140 "FDUP \t\t\t# Q Q\n\t"
10141 "FRNDINT\t\t\t# int(Q) Q\n\t"
10142 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10143 "FISTP dword [ESP]\n\t"
10144 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10145 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10146 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10147 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10148 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10149 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10150 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10151 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10152 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10153 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10154 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10155 "MOV [ESP+0],0\n\t"
10156 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10157
10158 "ADD ESP,8"
10159 %}
10160 ins_encode( push_stack_temp_qword,
10161 Push_Reg_DPR(X),
10162 Opcode(0xD9), Opcode(0xF1), // fyl2x
10163 pow_exp_core_encoding,
10164 pop_stack_temp_qword);
10165 ins_pipe( pipe_slow );
10166 %}
10167
10168 instruct powD_reg(regD dst, regD src0, regD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10169 predicate (UseSSE>=2);
10170 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10171 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10172 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10173 "MOVSD [ESP],$src1\n\t"
10174 "FLD FPR1,$src1\n\t"
10175 "MOVSD [ESP],$src0\n\t"
10176 "FLD FPR1,$src0\n\t"
10177 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10178
10179 "FDUP \t\t\t# Q Q\n\t"
10180 "FRNDINT\t\t\t# int(Q) Q\n\t"
10181 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10182 "FISTP dword [ESP]\n\t"
10183 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10184 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10185 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10186 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10187 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10188 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10189 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10190 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10191 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10192 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10193 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10194 "MOV [ESP+0],0\n\t"
10195 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10196
10197 "FST_D [ESP]\n\t"
10198 "MOVSD $dst,[ESP]\n\t"
10199 "ADD ESP,8"
10200 %}
10201 ins_encode( push_stack_temp_qword,
10202 push_xmm_to_fpr1(src1),
10203 push_xmm_to_fpr1(src0),
10204 Opcode(0xD9), Opcode(0xF1), // fyl2x
10205 pow_exp_core_encoding,
10206 Push_ResultD(dst) );
10207 ins_pipe( pipe_slow );
10208 %}
10209
10210
10211 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10212 predicate (UseSSE<=1);
10213 match(Set dpr1 (ExpD dpr1));
10214 effect(KILL rax, KILL rbx, KILL rcx);
10215 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10216 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10217 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10218
10219 "FDUP \t\t\t# Q Q\n\t"
10220 "FRNDINT\t\t\t# int(Q) Q\n\t"
10221 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10222 "FISTP dword [ESP]\n\t"
10223 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10224 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10225 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10226 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10227 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10228 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10229 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10230 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10231 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10232 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10233 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10234 "MOV [ESP+0],0\n\t"
10235 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10236
10237 "ADD ESP,8"
10238 %}
10239 ins_encode( push_stack_temp_qword,
10240 Opcode(0xD9), Opcode(0xEA), // fldl2e
10241 Opcode(0xDE), Opcode(0xC9), // fmulp
10242 pow_exp_core_encoding,
10243 pop_stack_temp_qword);
10244 ins_pipe( pipe_slow );
10245 %}
10246
10247 instruct expD_reg(regD dst, regD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10248 predicate (UseSSE>=2);
10249 match(Set dst (ExpD src));
10250 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10251 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10252 "MOVSD [ESP],$src\n\t"
10253 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10254 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10255
10256 "FDUP \t\t\t# Q Q\n\t"
10257 "FRNDINT\t\t\t# int(Q) Q\n\t"
10258 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10259 "FISTP dword [ESP]\n\t"
10260 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10261 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10262 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10263 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10264 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10265 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10266 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10267 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10268 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10269 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10270 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10271 "MOV [ESP+0],0\n\t"
10272 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10273
10274 "FST_D [ESP]\n\t"
10275 "MOVSD $dst,[ESP]\n\t"
10276 "ADD ESP,8"
10277 %}
10278 ins_encode( Push_SrcD(src),
10279 Opcode(0xD9), Opcode(0xEA), // fldl2e
10280 Opcode(0xDE), Opcode(0xC9), // fmulp
10281 pow_exp_core_encoding,
10282 Push_ResultD(dst) );
10283 ins_pipe( pipe_slow );
10284 %}
10285
10286
10287
10288 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10289 predicate (UseSSE<=1);
10290 // The source Double operand on FPU stack
10291 match(Set dst (Log10D src));
10292 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10293 // fxch ; swap ST(0) with ST(1)
10294 // fyl2x ; compute log_10(2) * log_2(x)
10295 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10296 "FXCH \n\t"
10297 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10298 %}
10299 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10300 Opcode(0xD9), Opcode(0xC9), // fxch
10301 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10302
10303 ins_pipe( pipe_slow );
10304 %}
10305
10306 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10307 predicate (UseSSE>=2);
10308 effect(KILL cr);
10309 match(Set dst (Log10D src));
10310 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10311 // fyl2x ; compute log_10(2) * log_2(x)
10312 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10313 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10314 %}
10315 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10316 Push_SrcD(src),
10317 Opcode(0xD9), Opcode(0xF1), // fyl2x
10318 Push_ResultD(dst));
10319
10320 ins_pipe( pipe_slow );
10321 %}
10322
10323 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10324 predicate (UseSSE<=1);
10325 // The source Double operand on FPU stack
10326 match(Set dst (LogD src));
10327 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10328 // fxch ; swap ST(0) with ST(1)
10329 // fyl2x ; compute log_e(2) * log_2(x)
10330 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10331 "FXCH \n\t"
10332 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10333 %}
10334 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10335 Opcode(0xD9), Opcode(0xC9), // fxch
10336 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10337
10338 ins_pipe( pipe_slow );
10339 %}
10340
10341 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10342 predicate (UseSSE>=2);
10343 effect(KILL cr);
10344 // The source and result Double operands in XMM registers
10345 match(Set dst (LogD src));
10346 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10347 // fyl2x ; compute log_e(2) * log_2(x)
10348 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10349 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10350 %}
10351 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10352 Push_SrcD(src),
10353 Opcode(0xD9), Opcode(0xF1), // fyl2x
10354 Push_ResultD(dst));
10355 ins_pipe( pipe_slow );
10356 %}
10357
10358 //-------------Float Instructions-------------------------------
10359 // Float Math
10360
10361 // Code for float compare:
10362 // fcompp();
10363 // fwait(); fnstsw_ax();
10364 // sahf();
10365 // movl(dst, unordered_result);
10366 // jcc(Assembler::parity, exit);
10367 // movl(dst, less_result);
10368 // jcc(Assembler::below, exit);
10369 // movl(dst, equal_result);
10370 // jcc(Assembler::equal, exit);
10371 // movl(dst, greater_result);
10372 // exit:
10373
10374 // P6 version of float compare, sets condition codes in EFLAGS
10375 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10376 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10377 match(Set cr (CmpF src1 src2));
10378 effect(KILL rax);
10379 ins_cost(150);
10380 format %{ "FLD $src1\n\t"
10381 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10382 "JNP exit\n\t"
10383 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10384 "SAHF\n"
10385 "exit:\tNOP // avoid branch to branch" %}
10386 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10387 ins_encode( Push_Reg_DPR(src1),
10388 OpcP, RegOpc(src2),
10389 cmpF_P6_fixup );
10390 ins_pipe( pipe_slow );
10391 %}
10392
10393 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10394 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10395 match(Set cr (CmpF src1 src2));
10396 ins_cost(100);
10397 format %{ "FLD $src1\n\t"
10398 "FUCOMIP ST,$src2 // P6 instruction" %}
10399 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10400 ins_encode( Push_Reg_DPR(src1),
10401 OpcP, RegOpc(src2));
10402 ins_pipe( pipe_slow );
10403 %}
10404
10405
10406 // Compare & branch
10407 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10408 predicate(UseSSE == 0);
10409 match(Set cr (CmpF src1 src2));
10410 effect(KILL rax);
10411 ins_cost(200);
10412 format %{ "FLD $src1\n\t"
10413 "FCOMp $src2\n\t"
10414 "FNSTSW AX\n\t"
10415 "TEST AX,0x400\n\t"
10416 "JZ,s flags\n\t"
10417 "MOV AH,1\t# unordered treat as LT\n"
10418 "flags:\tSAHF" %}
10419 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10420 ins_encode( Push_Reg_DPR(src1),
10421 OpcP, RegOpc(src2),
10422 fpu_flags);
10423 ins_pipe( pipe_slow );
10424 %}
10425
10426 // Compare vs zero into -1,0,1
10427 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10428 predicate(UseSSE == 0);
10429 match(Set dst (CmpF3 src1 zero));
10430 effect(KILL cr, KILL rax);
10431 ins_cost(280);
10432 format %{ "FTSTF $dst,$src1" %}
10433 opcode(0xE4, 0xD9);
10434 ins_encode( Push_Reg_DPR(src1),
10435 OpcS, OpcP, PopFPU,
10436 CmpF_Result(dst));
10437 ins_pipe( pipe_slow );
10438 %}
10439
10440 // Compare into -1,0,1
10441 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10442 predicate(UseSSE == 0);
10443 match(Set dst (CmpF3 src1 src2));
10444 effect(KILL cr, KILL rax);
10445 ins_cost(300);
10446 format %{ "FCMPF $dst,$src1,$src2" %}
10447 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10448 ins_encode( Push_Reg_DPR(src1),
10449 OpcP, RegOpc(src2),
10450 CmpF_Result(dst));
10451 ins_pipe( pipe_slow );
10452 %}
10453
10454 // float compare and set condition codes in EFLAGS by XMM regs
10455 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10456 predicate(UseSSE>=1);
10457 match(Set cr (CmpF src1 src2));
10458 ins_cost(145);
10459 format %{ "UCOMISS $src1,$src2\n\t"
10460 "JNP,s exit\n\t"
10461 "PUSHF\t# saw NaN, set CF\n\t"
10462 "AND [rsp], #0xffffff2b\n\t"
10463 "POPF\n"
10464 "exit:" %}
10465 ins_encode %{
10466 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10467 emit_cmpfp_fixup(_masm);
10468 %}
10469 ins_pipe( pipe_slow );
10470 %}
10471
10472 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10473 predicate(UseSSE>=1);
10474 match(Set cr (CmpF src1 src2));
10475 ins_cost(100);
10476 format %{ "UCOMISS $src1,$src2" %}
10477 ins_encode %{
10478 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10479 %}
10480 ins_pipe( pipe_slow );
10481 %}
10482
10483 // float compare and set condition codes in EFLAGS by XMM regs
10484 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10485 predicate(UseSSE>=1);
10486 match(Set cr (CmpF src1 (LoadF src2)));
10487 ins_cost(165);
10488 format %{ "UCOMISS $src1,$src2\n\t"
10489 "JNP,s exit\n\t"
10490 "PUSHF\t# saw NaN, set CF\n\t"
10491 "AND [rsp], #0xffffff2b\n\t"
10492 "POPF\n"
10493 "exit:" %}
10494 ins_encode %{
10495 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10496 emit_cmpfp_fixup(_masm);
10497 %}
10498 ins_pipe( pipe_slow );
10499 %}
10500
10501 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10502 predicate(UseSSE>=1);
10503 match(Set cr (CmpF src1 (LoadF src2)));
10504 ins_cost(100);
10505 format %{ "UCOMISS $src1,$src2" %}
10506 ins_encode %{
10507 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10508 %}
10509 ins_pipe( pipe_slow );
10510 %}
10511
10512 // Compare into -1,0,1 in XMM
10513 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10514 predicate(UseSSE>=1);
10515 match(Set dst (CmpF3 src1 src2));
10516 effect(KILL cr);
10517 ins_cost(255);
10518 format %{ "UCOMISS $src1, $src2\n\t"
10519 "MOV $dst, #-1\n\t"
10520 "JP,s done\n\t"
10521 "JB,s done\n\t"
10522 "SETNE $dst\n\t"
10523 "MOVZB $dst, $dst\n"
10524 "done:" %}
10525 ins_encode %{
10526 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10527 emit_cmpfp3(_masm, $dst$$Register);
10528 %}
10529 ins_pipe( pipe_slow );
10530 %}
10531
10532 // Compare into -1,0,1 in XMM and memory
10533 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10534 predicate(UseSSE>=1);
10535 match(Set dst (CmpF3 src1 (LoadF src2)));
10536 effect(KILL cr);
10537 ins_cost(275);
10538 format %{ "UCOMISS $src1, $src2\n\t"
10539 "MOV $dst, #-1\n\t"
10540 "JP,s done\n\t"
10541 "JB,s done\n\t"
10542 "SETNE $dst\n\t"
10543 "MOVZB $dst, $dst\n"
10544 "done:" %}
10545 ins_encode %{
10546 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10547 emit_cmpfp3(_masm, $dst$$Register);
10548 %}
10549 ins_pipe( pipe_slow );
10550 %}
10551
10552 // Spill to obtain 24-bit precision
10553 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10554 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10555 match(Set dst (SubF src1 src2));
10556
10557 format %{ "FSUB $dst,$src1 - $src2" %}
10558 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10559 ins_encode( Push_Reg_FPR(src1),
10560 OpcReg_FPR(src2),
10561 Pop_Mem_FPR(dst) );
10562 ins_pipe( fpu_mem_reg_reg );
10563 %}
10564 //
10565 // This instruction does not round to 24-bits
10566 instruct subFPR_reg(regFPR dst, regFPR src) %{
10567 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10568 match(Set dst (SubF dst src));
10569
10570 format %{ "FSUB $dst,$src" %}
10571 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10572 ins_encode( Push_Reg_FPR(src),
10573 OpcP, RegOpc(dst) );
10574 ins_pipe( fpu_reg_reg );
10575 %}
10576
10577 // Spill to obtain 24-bit precision
10578 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10579 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10580 match(Set dst (AddF src1 src2));
10581
10582 format %{ "FADD $dst,$src1,$src2" %}
10583 opcode(0xD8, 0x0); /* D8 C0+i */
10584 ins_encode( Push_Reg_FPR(src2),
10585 OpcReg_FPR(src1),
10586 Pop_Mem_FPR(dst) );
10587 ins_pipe( fpu_mem_reg_reg );
10588 %}
10589 //
10590 // This instruction does not round to 24-bits
10591 instruct addFPR_reg(regFPR dst, regFPR src) %{
10592 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10593 match(Set dst (AddF dst src));
10594
10595 format %{ "FLD $src\n\t"
10596 "FADDp $dst,ST" %}
10597 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10598 ins_encode( Push_Reg_FPR(src),
10599 OpcP, RegOpc(dst) );
10600 ins_pipe( fpu_reg_reg );
10601 %}
10602
10603 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10604 predicate(UseSSE==0);
10605 match(Set dst (AbsF src));
10606 ins_cost(100);
10607 format %{ "FABS" %}
10608 opcode(0xE1, 0xD9);
10609 ins_encode( OpcS, OpcP );
10610 ins_pipe( fpu_reg_reg );
10611 %}
10612
10613 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10614 predicate(UseSSE==0);
10615 match(Set dst (NegF src));
10616 ins_cost(100);
10617 format %{ "FCHS" %}
10618 opcode(0xE0, 0xD9);
10619 ins_encode( OpcS, OpcP );
10620 ins_pipe( fpu_reg_reg );
10621 %}
10622
10623 // Cisc-alternate to addFPR_reg
10624 // Spill to obtain 24-bit precision
10625 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10626 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10627 match(Set dst (AddF src1 (LoadF src2)));
10628
10629 format %{ "FLD $src2\n\t"
10630 "FADD ST,$src1\n\t"
10631 "FSTP_S $dst" %}
10632 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10633 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10634 OpcReg_FPR(src1),
10635 Pop_Mem_FPR(dst) );
10636 ins_pipe( fpu_mem_reg_mem );
10637 %}
10638 //
10639 // Cisc-alternate to addFPR_reg
10640 // This instruction does not round to 24-bits
10641 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10642 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10643 match(Set dst (AddF dst (LoadF src)));
10644
10645 format %{ "FADD $dst,$src" %}
10646 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10647 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10648 OpcP, RegOpc(dst) );
10649 ins_pipe( fpu_reg_mem );
10650 %}
10651
10652 // // Following two instructions for _222_mpegaudio
10653 // Spill to obtain 24-bit precision
10654 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10655 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10656 match(Set dst (AddF src1 src2));
10657
10658 format %{ "FADD $dst,$src1,$src2" %}
10659 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10660 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10661 OpcReg_FPR(src2),
10662 Pop_Mem_FPR(dst) );
10663 ins_pipe( fpu_mem_reg_mem );
10664 %}
10665
10666 // Cisc-spill variant
10667 // Spill to obtain 24-bit precision
10668 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10669 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10670 match(Set dst (AddF src1 (LoadF src2)));
10671
10672 format %{ "FADD $dst,$src1,$src2 cisc" %}
10673 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10674 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10675 set_instruction_start,
10676 OpcP, RMopc_Mem(secondary,src1),
10677 Pop_Mem_FPR(dst) );
10678 ins_pipe( fpu_mem_mem_mem );
10679 %}
10680
10681 // Spill to obtain 24-bit precision
10682 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10683 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10684 match(Set dst (AddF src1 src2));
10685
10686 format %{ "FADD $dst,$src1,$src2" %}
10687 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10688 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10689 set_instruction_start,
10690 OpcP, RMopc_Mem(secondary,src1),
10691 Pop_Mem_FPR(dst) );
10692 ins_pipe( fpu_mem_mem_mem );
10693 %}
10694
10695
10696 // Spill to obtain 24-bit precision
10697 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10698 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10699 match(Set dst (AddF src con));
10700 format %{ "FLD $src\n\t"
10701 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10702 "FSTP_S $dst" %}
10703 ins_encode %{
10704 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10705 __ fadd_s($constantaddress($con));
10706 __ fstp_s(Address(rsp, $dst$$disp));
10707 %}
10708 ins_pipe(fpu_mem_reg_con);
10709 %}
10710 //
10711 // This instruction does not round to 24-bits
10712 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10713 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10714 match(Set dst (AddF src con));
10715 format %{ "FLD $src\n\t"
10716 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10717 "FSTP $dst" %}
10718 ins_encode %{
10719 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10720 __ fadd_s($constantaddress($con));
10721 __ fstp_d($dst$$reg);
10722 %}
10723 ins_pipe(fpu_reg_reg_con);
10724 %}
10725
10726 // Spill to obtain 24-bit precision
10727 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10728 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10729 match(Set dst (MulF src1 src2));
10730
10731 format %{ "FLD $src1\n\t"
10732 "FMUL $src2\n\t"
10733 "FSTP_S $dst" %}
10734 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10735 ins_encode( Push_Reg_FPR(src1),
10736 OpcReg_FPR(src2),
10737 Pop_Mem_FPR(dst) );
10738 ins_pipe( fpu_mem_reg_reg );
10739 %}
10740 //
10741 // This instruction does not round to 24-bits
10742 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10743 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10744 match(Set dst (MulF src1 src2));
10745
10746 format %{ "FLD $src1\n\t"
10747 "FMUL $src2\n\t"
10748 "FSTP_S $dst" %}
10749 opcode(0xD8, 0x1); /* D8 C8+i */
10750 ins_encode( Push_Reg_FPR(src2),
10751 OpcReg_FPR(src1),
10752 Pop_Reg_FPR(dst) );
10753 ins_pipe( fpu_reg_reg_reg );
10754 %}
10755
10756
10757 // Spill to obtain 24-bit precision
10758 // Cisc-alternate to reg-reg multiply
10759 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10760 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10761 match(Set dst (MulF src1 (LoadF src2)));
10762
10763 format %{ "FLD_S $src2\n\t"
10764 "FMUL $src1\n\t"
10765 "FSTP_S $dst" %}
10766 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10767 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10768 OpcReg_FPR(src1),
10769 Pop_Mem_FPR(dst) );
10770 ins_pipe( fpu_mem_reg_mem );
10771 %}
10772 //
10773 // This instruction does not round to 24-bits
10774 // Cisc-alternate to reg-reg multiply
10775 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10776 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10777 match(Set dst (MulF src1 (LoadF src2)));
10778
10779 format %{ "FMUL $dst,$src1,$src2" %}
10780 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10781 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10782 OpcReg_FPR(src1),
10783 Pop_Reg_FPR(dst) );
10784 ins_pipe( fpu_reg_reg_mem );
10785 %}
10786
10787 // Spill to obtain 24-bit precision
10788 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10789 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10790 match(Set dst (MulF src1 src2));
10791
10792 format %{ "FMUL $dst,$src1,$src2" %}
10793 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10794 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10795 set_instruction_start,
10796 OpcP, RMopc_Mem(secondary,src1),
10797 Pop_Mem_FPR(dst) );
10798 ins_pipe( fpu_mem_mem_mem );
10799 %}
10800
10801 // Spill to obtain 24-bit precision
10802 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10803 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10804 match(Set dst (MulF src con));
10805
10806 format %{ "FLD $src\n\t"
10807 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10808 "FSTP_S $dst" %}
10809 ins_encode %{
10810 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10811 __ fmul_s($constantaddress($con));
10812 __ fstp_s(Address(rsp, $dst$$disp));
10813 %}
10814 ins_pipe(fpu_mem_reg_con);
10815 %}
10816 //
10817 // This instruction does not round to 24-bits
10818 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10819 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10820 match(Set dst (MulF src con));
10821
10822 format %{ "FLD $src\n\t"
10823 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10824 "FSTP $dst" %}
10825 ins_encode %{
10826 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10827 __ fmul_s($constantaddress($con));
10828 __ fstp_d($dst$$reg);
10829 %}
10830 ins_pipe(fpu_reg_reg_con);
10831 %}
10832
10833
10834 //
10835 // MACRO1 -- subsume unshared load into mulFPR
10836 // This instruction does not round to 24-bits
10837 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10838 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10839 match(Set dst (MulF (LoadF mem1) src));
10840
10841 format %{ "FLD $mem1 ===MACRO1===\n\t"
10842 "FMUL ST,$src\n\t"
10843 "FSTP $dst" %}
10844 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10845 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10846 OpcReg_FPR(src),
10847 Pop_Reg_FPR(dst) );
10848 ins_pipe( fpu_reg_reg_mem );
10849 %}
10850 //
10851 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10852 // This instruction does not round to 24-bits
10853 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10854 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10855 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10856 ins_cost(95);
10857
10858 format %{ "FLD $mem1 ===MACRO2===\n\t"
10859 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10860 "FADD ST,$src2\n\t"
10861 "FSTP $dst" %}
10862 opcode(0xD9); /* LoadF D9 /0 */
10863 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10864 FMul_ST_reg(src1),
10865 FAdd_ST_reg(src2),
10866 Pop_Reg_FPR(dst) );
10867 ins_pipe( fpu_reg_mem_reg_reg );
10868 %}
10869
10870 // MACRO3 -- addFPR a mulFPR
10871 // This instruction does not round to 24-bits. It is a '2-address'
10872 // instruction in that the result goes back to src2. This eliminates
10873 // a move from the macro; possibly the register allocator will have
10874 // to add it back (and maybe not).
10875 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10876 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10877 match(Set src2 (AddF (MulF src0 src1) src2));
10878
10879 format %{ "FLD $src0 ===MACRO3===\n\t"
10880 "FMUL ST,$src1\n\t"
10881 "FADDP $src2,ST" %}
10882 opcode(0xD9); /* LoadF D9 /0 */
10883 ins_encode( Push_Reg_FPR(src0),
10884 FMul_ST_reg(src1),
10885 FAddP_reg_ST(src2) );
10886 ins_pipe( fpu_reg_reg_reg );
10887 %}
10888
10889 // MACRO4 -- divFPR subFPR
10890 // This instruction does not round to 24-bits
10891 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10892 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10893 match(Set dst (DivF (SubF src2 src1) src3));
10894
10895 format %{ "FLD $src2 ===MACRO4===\n\t"
10896 "FSUB ST,$src1\n\t"
10897 "FDIV ST,$src3\n\t"
10898 "FSTP $dst" %}
10899 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10900 ins_encode( Push_Reg_FPR(src2),
10901 subFPR_divFPR_encode(src1,src3),
10902 Pop_Reg_FPR(dst) );
10903 ins_pipe( fpu_reg_reg_reg_reg );
10904 %}
10905
10906 // Spill to obtain 24-bit precision
10907 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10908 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10909 match(Set dst (DivF src1 src2));
10910
10911 format %{ "FDIV $dst,$src1,$src2" %}
10912 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10913 ins_encode( Push_Reg_FPR(src1),
10914 OpcReg_FPR(src2),
10915 Pop_Mem_FPR(dst) );
10916 ins_pipe( fpu_mem_reg_reg );
10917 %}
10918 //
10919 // This instruction does not round to 24-bits
10920 instruct divFPR_reg(regFPR dst, regFPR src) %{
10921 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10922 match(Set dst (DivF dst src));
10923
10924 format %{ "FDIV $dst,$src" %}
10925 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10926 ins_encode( Push_Reg_FPR(src),
10927 OpcP, RegOpc(dst) );
10928 ins_pipe( fpu_reg_reg );
10929 %}
10930
10931
10932 // Spill to obtain 24-bit precision
10933 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10934 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10935 match(Set dst (ModF src1 src2));
10936 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10937
10938 format %{ "FMOD $dst,$src1,$src2" %}
10939 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10940 emitModDPR(),
10941 Push_Result_Mod_DPR(src2),
10942 Pop_Mem_FPR(dst));
10943 ins_pipe( pipe_slow );
10944 %}
10945 //
10946 // This instruction does not round to 24-bits
10947 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10948 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10949 match(Set dst (ModF dst src));
10950 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10951
10952 format %{ "FMOD $dst,$src" %}
10953 ins_encode(Push_Reg_Mod_DPR(dst, src),
10954 emitModDPR(),
10955 Push_Result_Mod_DPR(src),
10956 Pop_Reg_FPR(dst));
10957 ins_pipe( pipe_slow );
10958 %}
10959
10960 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10961 predicate(UseSSE>=1);
10962 match(Set dst (ModF src0 src1));
10963 effect(KILL rax, KILL cr);
10964 format %{ "SUB ESP,4\t # FMOD\n"
10965 "\tMOVSS [ESP+0],$src1\n"
10966 "\tFLD_S [ESP+0]\n"
10967 "\tMOVSS [ESP+0],$src0\n"
10968 "\tFLD_S [ESP+0]\n"
10969 "loop:\tFPREM\n"
10970 "\tFWAIT\n"
10971 "\tFNSTSW AX\n"
10972 "\tSAHF\n"
10973 "\tJP loop\n"
10974 "\tFSTP_S [ESP+0]\n"
10975 "\tMOVSS $dst,[ESP+0]\n"
10976 "\tADD ESP,4\n"
10977 "\tFSTP ST0\t # Restore FPU Stack"
10978 %}
10979 ins_cost(250);
10980 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10981 ins_pipe( pipe_slow );
10982 %}
10983
10984
10985 //----------Arithmetic Conversion Instructions---------------------------------
10986 // The conversions operations are all Alpha sorted. Please keep it that way!
10987
10988 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10989 predicate(UseSSE==0);
10990 match(Set dst (RoundFloat src));
10991 ins_cost(125);
10992 format %{ "FST_S $dst,$src\t# F-round" %}
10993 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10994 ins_pipe( fpu_mem_reg );
10995 %}
10996
10997 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10998 predicate(UseSSE<=1);
10999 match(Set dst (RoundDouble src));
11000 ins_cost(125);
11001 format %{ "FST_D $dst,$src\t# D-round" %}
11002 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11003 ins_pipe( fpu_mem_reg );
11004 %}
11005
11006 // Force rounding to 24-bit precision and 6-bit exponent
11007 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
11008 predicate(UseSSE==0);
11009 match(Set dst (ConvD2F src));
11010 format %{ "FST_S $dst,$src\t# F-round" %}
11011 expand %{
11012 roundFloat_mem_reg(dst,src);
11013 %}
11014 %}
11015
11016 // Force rounding to 24-bit precision and 6-bit exponent
11017 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
11018 predicate(UseSSE==1);
11019 match(Set dst (ConvD2F src));
11020 effect( KILL cr );
11021 format %{ "SUB ESP,4\n\t"
11022 "FST_S [ESP],$src\t# F-round\n\t"
11023 "MOVSS $dst,[ESP]\n\t"
11024 "ADD ESP,4" %}
11025 ins_encode %{
11026 __ subptr(rsp, 4);
11027 if ($src$$reg != FPR1L_enc) {
11028 __ fld_s($src$$reg-1);
11029 __ fstp_s(Address(rsp, 0));
11030 } else {
11031 __ fst_s(Address(rsp, 0));
11032 }
11033 __ movflt($dst$$XMMRegister, Address(rsp, 0));
11034 __ addptr(rsp, 4);
11035 %}
11036 ins_pipe( pipe_slow );
11037 %}
11038
11039 // Force rounding double precision to single precision
11040 instruct convD2F_reg(regF dst, regD src) %{
11041 predicate(UseSSE>=2);
11042 match(Set dst (ConvD2F src));
11043 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11044 ins_encode %{
11045 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11046 %}
11047 ins_pipe( pipe_slow );
11048 %}
11049
11050 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
11051 predicate(UseSSE==0);
11052 match(Set dst (ConvF2D src));
11053 format %{ "FST_S $dst,$src\t# D-round" %}
11054 ins_encode( Pop_Reg_Reg_DPR(dst, src));
11055 ins_pipe( fpu_reg_reg );
11056 %}
11057
11058 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
11059 predicate(UseSSE==1);
11060 match(Set dst (ConvF2D src));
11061 format %{ "FST_D $dst,$src\t# D-round" %}
11062 expand %{
11063 roundDouble_mem_reg(dst,src);
11064 %}
11065 %}
11066
11067 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
11068 predicate(UseSSE==1);
11069 match(Set dst (ConvF2D src));
11070 effect( KILL cr );
11071 format %{ "SUB ESP,4\n\t"
11072 "MOVSS [ESP] $src\n\t"
11073 "FLD_S [ESP]\n\t"
11074 "ADD ESP,4\n\t"
11075 "FSTP $dst\t# D-round" %}
11076 ins_encode %{
11077 __ subptr(rsp, 4);
11078 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11079 __ fld_s(Address(rsp, 0));
11080 __ addptr(rsp, 4);
11081 __ fstp_d($dst$$reg);
11082 %}
11083 ins_pipe( pipe_slow );
11084 %}
11085
11086 instruct convF2D_reg(regD dst, regF src) %{
11087 predicate(UseSSE>=2);
11088 match(Set dst (ConvF2D src));
11089 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11090 ins_encode %{
11091 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11092 %}
11093 ins_pipe( pipe_slow );
11094 %}
11095
11096 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11097 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11098 predicate(UseSSE<=1);
11099 match(Set dst (ConvD2I src));
11100 effect( KILL tmp, KILL cr );
11101 format %{ "FLD $src\t# Convert double to int \n\t"
11102 "FLDCW trunc mode\n\t"
11103 "SUB ESP,4\n\t"
11104 "FISTp [ESP + #0]\n\t"
11105 "FLDCW std/24-bit mode\n\t"
11106 "POP EAX\n\t"
11107 "CMP EAX,0x80000000\n\t"
11108 "JNE,s fast\n\t"
11109 "FLD_D $src\n\t"
11110 "CALL d2i_wrapper\n"
11111 "fast:" %}
11112 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11113 ins_pipe( pipe_slow );
11114 %}
11115
11116 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11117 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11118 predicate(UseSSE>=2);
11119 match(Set dst (ConvD2I src));
11120 effect( KILL tmp, KILL cr );
11121 format %{ "CVTTSD2SI $dst, $src\n\t"
11122 "CMP $dst,0x80000000\n\t"
11123 "JNE,s fast\n\t"
11124 "SUB ESP, 8\n\t"
11125 "MOVSD [ESP], $src\n\t"
11126 "FLD_D [ESP]\n\t"
11127 "ADD ESP, 8\n\t"
11128 "CALL d2i_wrapper\n"
11129 "fast:" %}
11130 ins_encode %{
11131 Label fast;
11132 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11133 __ cmpl($dst$$Register, 0x80000000);
11134 __ jccb(Assembler::notEqual, fast);
11135 __ subptr(rsp, 8);
11136 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11137 __ fld_d(Address(rsp, 0));
11138 __ addptr(rsp, 8);
11139 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11140 __ bind(fast);
11141 %}
11142 ins_pipe( pipe_slow );
11143 %}
11144
11145 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11146 predicate(UseSSE<=1);
11147 match(Set dst (ConvD2L src));
11148 effect( KILL cr );
11149 format %{ "FLD $src\t# Convert double to long\n\t"
11150 "FLDCW trunc mode\n\t"
11151 "SUB ESP,8\n\t"
11152 "FISTp [ESP + #0]\n\t"
11153 "FLDCW std/24-bit mode\n\t"
11154 "POP EAX\n\t"
11155 "POP EDX\n\t"
11156 "CMP EDX,0x80000000\n\t"
11157 "JNE,s fast\n\t"
11158 "TEST EAX,EAX\n\t"
11159 "JNE,s fast\n\t"
11160 "FLD $src\n\t"
11161 "CALL d2l_wrapper\n"
11162 "fast:" %}
11163 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11164 ins_pipe( pipe_slow );
11165 %}
11166
11167 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11168 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11169 predicate (UseSSE>=2);
11170 match(Set dst (ConvD2L src));
11171 effect( KILL cr );
11172 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11173 "MOVSD [ESP],$src\n\t"
11174 "FLD_D [ESP]\n\t"
11175 "FLDCW trunc mode\n\t"
11176 "FISTp [ESP + #0]\n\t"
11177 "FLDCW std/24-bit mode\n\t"
11178 "POP EAX\n\t"
11179 "POP EDX\n\t"
11180 "CMP EDX,0x80000000\n\t"
11181 "JNE,s fast\n\t"
11182 "TEST EAX,EAX\n\t"
11183 "JNE,s fast\n\t"
11184 "SUB ESP,8\n\t"
11185 "MOVSD [ESP],$src\n\t"
11186 "FLD_D [ESP]\n\t"
11187 "ADD ESP,8\n\t"
11188 "CALL d2l_wrapper\n"
11189 "fast:" %}
11190 ins_encode %{
11191 Label fast;
11192 __ subptr(rsp, 8);
11193 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11194 __ fld_d(Address(rsp, 0));
11195 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11196 __ fistp_d(Address(rsp, 0));
11197 // Restore the rounding mode, mask the exception
11198 if (Compile::current()->in_24_bit_fp_mode()) {
11199 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11200 } else {
11201 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11202 }
11203 // Load the converted long, adjust CPU stack
11204 __ pop(rax);
11205 __ pop(rdx);
11206 __ cmpl(rdx, 0x80000000);
11207 __ jccb(Assembler::notEqual, fast);
11208 __ testl(rax, rax);
11209 __ jccb(Assembler::notEqual, fast);
11210 __ subptr(rsp, 8);
11211 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11212 __ fld_d(Address(rsp, 0));
11213 __ addptr(rsp, 8);
11214 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11215 __ bind(fast);
11216 %}
11217 ins_pipe( pipe_slow );
11218 %}
11219
11220 // Convert a double to an int. Java semantics require we do complex
11221 // manglations in the corner cases. So we set the rounding mode to
11222 // 'zero', store the darned double down as an int, and reset the
11223 // rounding mode to 'nearest'. The hardware stores a flag value down
11224 // if we would overflow or converted a NAN; we check for this and
11225 // and go the slow path if needed.
11226 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11227 predicate(UseSSE==0);
11228 match(Set dst (ConvF2I src));
11229 effect( KILL tmp, KILL cr );
11230 format %{ "FLD $src\t# Convert float to int \n\t"
11231 "FLDCW trunc mode\n\t"
11232 "SUB ESP,4\n\t"
11233 "FISTp [ESP + #0]\n\t"
11234 "FLDCW std/24-bit mode\n\t"
11235 "POP EAX\n\t"
11236 "CMP EAX,0x80000000\n\t"
11237 "JNE,s fast\n\t"
11238 "FLD $src\n\t"
11239 "CALL d2i_wrapper\n"
11240 "fast:" %}
11241 // DPR2I_encoding works for FPR2I
11242 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11243 ins_pipe( pipe_slow );
11244 %}
11245
11246 // Convert a float in xmm to an int reg.
11247 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11248 predicate(UseSSE>=1);
11249 match(Set dst (ConvF2I src));
11250 effect( KILL tmp, KILL cr );
11251 format %{ "CVTTSS2SI $dst, $src\n\t"
11252 "CMP $dst,0x80000000\n\t"
11253 "JNE,s fast\n\t"
11254 "SUB ESP, 4\n\t"
11255 "MOVSS [ESP], $src\n\t"
11256 "FLD [ESP]\n\t"
11257 "ADD ESP, 4\n\t"
11258 "CALL d2i_wrapper\n"
11259 "fast:" %}
11260 ins_encode %{
11261 Label fast;
11262 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11263 __ cmpl($dst$$Register, 0x80000000);
11264 __ jccb(Assembler::notEqual, fast);
11265 __ subptr(rsp, 4);
11266 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11267 __ fld_s(Address(rsp, 0));
11268 __ addptr(rsp, 4);
11269 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11270 __ bind(fast);
11271 %}
11272 ins_pipe( pipe_slow );
11273 %}
11274
11275 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11276 predicate(UseSSE==0);
11277 match(Set dst (ConvF2L src));
11278 effect( KILL cr );
11279 format %{ "FLD $src\t# Convert float to long\n\t"
11280 "FLDCW trunc mode\n\t"
11281 "SUB ESP,8\n\t"
11282 "FISTp [ESP + #0]\n\t"
11283 "FLDCW std/24-bit mode\n\t"
11284 "POP EAX\n\t"
11285 "POP EDX\n\t"
11286 "CMP EDX,0x80000000\n\t"
11287 "JNE,s fast\n\t"
11288 "TEST EAX,EAX\n\t"
11289 "JNE,s fast\n\t"
11290 "FLD $src\n\t"
11291 "CALL d2l_wrapper\n"
11292 "fast:" %}
11293 // DPR2L_encoding works for FPR2L
11294 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11295 ins_pipe( pipe_slow );
11296 %}
11297
11298 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11299 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11300 predicate (UseSSE>=1);
11301 match(Set dst (ConvF2L src));
11302 effect( KILL cr );
11303 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11304 "MOVSS [ESP],$src\n\t"
11305 "FLD_S [ESP]\n\t"
11306 "FLDCW trunc mode\n\t"
11307 "FISTp [ESP + #0]\n\t"
11308 "FLDCW std/24-bit mode\n\t"
11309 "POP EAX\n\t"
11310 "POP EDX\n\t"
11311 "CMP EDX,0x80000000\n\t"
11312 "JNE,s fast\n\t"
11313 "TEST EAX,EAX\n\t"
11314 "JNE,s fast\n\t"
11315 "SUB ESP,4\t# Convert float to long\n\t"
11316 "MOVSS [ESP],$src\n\t"
11317 "FLD_S [ESP]\n\t"
11318 "ADD ESP,4\n\t"
11319 "CALL d2l_wrapper\n"
11320 "fast:" %}
11321 ins_encode %{
11322 Label fast;
11323 __ subptr(rsp, 8);
11324 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11325 __ fld_s(Address(rsp, 0));
11326 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11327 __ fistp_d(Address(rsp, 0));
11328 // Restore the rounding mode, mask the exception
11329 if (Compile::current()->in_24_bit_fp_mode()) {
11330 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11331 } else {
11332 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11333 }
11334 // Load the converted long, adjust CPU stack
11335 __ pop(rax);
11336 __ pop(rdx);
11337 __ cmpl(rdx, 0x80000000);
11338 __ jccb(Assembler::notEqual, fast);
11339 __ testl(rax, rax);
11340 __ jccb(Assembler::notEqual, fast);
11341 __ subptr(rsp, 4);
11342 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11343 __ fld_s(Address(rsp, 0));
11344 __ addptr(rsp, 4);
11345 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11346 __ bind(fast);
11347 %}
11348 ins_pipe( pipe_slow );
11349 %}
11350
11351 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11352 predicate( UseSSE<=1 );
11353 match(Set dst (ConvI2D src));
11354 format %{ "FILD $src\n\t"
11355 "FSTP $dst" %}
11356 opcode(0xDB, 0x0); /* DB /0 */
11357 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11358 ins_pipe( fpu_reg_mem );
11359 %}
11360
11361 instruct convI2D_reg(regD dst, eRegI src) %{
11362 predicate( UseSSE>=2 && !UseXmmI2D );
11363 match(Set dst (ConvI2D src));
11364 format %{ "CVTSI2SD $dst,$src" %}
11365 ins_encode %{
11366 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11367 %}
11368 ins_pipe( pipe_slow );
11369 %}
11370
11371 instruct convI2D_mem(regD dst, memory mem) %{
11372 predicate( UseSSE>=2 );
11373 match(Set dst (ConvI2D (LoadI mem)));
11374 format %{ "CVTSI2SD $dst,$mem" %}
11375 ins_encode %{
11376 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11377 %}
11378 ins_pipe( pipe_slow );
11379 %}
11380
11381 instruct convXI2D_reg(regD dst, eRegI src)
11382 %{
11383 predicate( UseSSE>=2 && UseXmmI2D );
11384 match(Set dst (ConvI2D src));
11385
11386 format %{ "MOVD $dst,$src\n\t"
11387 "CVTDQ2PD $dst,$dst\t# i2d" %}
11388 ins_encode %{
11389 __ movdl($dst$$XMMRegister, $src$$Register);
11390 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11391 %}
11392 ins_pipe(pipe_slow); // XXX
11393 %}
11394
11395 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11396 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11397 match(Set dst (ConvI2D (LoadI mem)));
11398 format %{ "FILD $mem\n\t"
11399 "FSTP $dst" %}
11400 opcode(0xDB); /* DB /0 */
11401 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11402 Pop_Reg_DPR(dst));
11403 ins_pipe( fpu_reg_mem );
11404 %}
11405
11406 // Convert a byte to a float; no rounding step needed.
11407 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11408 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11409 match(Set dst (ConvI2F src));
11410 format %{ "FILD $src\n\t"
11411 "FSTP $dst" %}
11412
11413 opcode(0xDB, 0x0); /* DB /0 */
11414 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11415 ins_pipe( fpu_reg_mem );
11416 %}
11417
11418 // In 24-bit mode, force exponent rounding by storing back out
11419 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11420 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11421 match(Set dst (ConvI2F src));
11422 ins_cost(200);
11423 format %{ "FILD $src\n\t"
11424 "FSTP_S $dst" %}
11425 opcode(0xDB, 0x0); /* DB /0 */
11426 ins_encode( Push_Mem_I(src),
11427 Pop_Mem_FPR(dst));
11428 ins_pipe( fpu_mem_mem );
11429 %}
11430
11431 // In 24-bit mode, force exponent rounding by storing back out
11432 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11433 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11434 match(Set dst (ConvI2F (LoadI mem)));
11435 ins_cost(200);
11436 format %{ "FILD $mem\n\t"
11437 "FSTP_S $dst" %}
11438 opcode(0xDB); /* DB /0 */
11439 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11440 Pop_Mem_FPR(dst));
11441 ins_pipe( fpu_mem_mem );
11442 %}
11443
11444 // This instruction does not round to 24-bits
11445 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11446 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11447 match(Set dst (ConvI2F src));
11448 format %{ "FILD $src\n\t"
11449 "FSTP $dst" %}
11450 opcode(0xDB, 0x0); /* DB /0 */
11451 ins_encode( Push_Mem_I(src),
11452 Pop_Reg_FPR(dst));
11453 ins_pipe( fpu_reg_mem );
11454 %}
11455
11456 // This instruction does not round to 24-bits
11457 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11458 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11459 match(Set dst (ConvI2F (LoadI mem)));
11460 format %{ "FILD $mem\n\t"
11461 "FSTP $dst" %}
11462 opcode(0xDB); /* DB /0 */
11463 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11464 Pop_Reg_FPR(dst));
11465 ins_pipe( fpu_reg_mem );
11466 %}
11467
11468 // Convert an int to a float in xmm; no rounding step needed.
11469 instruct convI2F_reg(regF dst, eRegI src) %{
11470 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11471 match(Set dst (ConvI2F src));
11472 format %{ "CVTSI2SS $dst, $src" %}
11473 ins_encode %{
11474 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11475 %}
11476 ins_pipe( pipe_slow );
11477 %}
11478
11479 instruct convXI2F_reg(regF dst, eRegI src)
11480 %{
11481 predicate( UseSSE>=2 && UseXmmI2F );
11482 match(Set dst (ConvI2F src));
11483
11484 format %{ "MOVD $dst,$src\n\t"
11485 "CVTDQ2PS $dst,$dst\t# i2f" %}
11486 ins_encode %{
11487 __ movdl($dst$$XMMRegister, $src$$Register);
11488 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11489 %}
11490 ins_pipe(pipe_slow); // XXX
11491 %}
11492
11493 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11494 match(Set dst (ConvI2L src));
11495 effect(KILL cr);
11496 ins_cost(375);
11497 format %{ "MOV $dst.lo,$src\n\t"
11498 "MOV $dst.hi,$src\n\t"
11499 "SAR $dst.hi,31" %}
11500 ins_encode(convert_int_long(dst,src));
11501 ins_pipe( ialu_reg_reg_long );
11502 %}
11503
11504 // Zero-extend convert int to long
11505 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11506 match(Set dst (AndL (ConvI2L src) mask) );
11507 effect( KILL flags );
11508 ins_cost(250);
11509 format %{ "MOV $dst.lo,$src\n\t"
11510 "XOR $dst.hi,$dst.hi" %}
11511 opcode(0x33); // XOR
11512 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11513 ins_pipe( ialu_reg_reg_long );
11514 %}
11515
11516 // Zero-extend long
11517 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11518 match(Set dst (AndL src mask) );
11519 effect( KILL flags );
11520 ins_cost(250);
11521 format %{ "MOV $dst.lo,$src.lo\n\t"
11522 "XOR $dst.hi,$dst.hi\n\t" %}
11523 opcode(0x33); // XOR
11524 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11525 ins_pipe( ialu_reg_reg_long );
11526 %}
11527
11528 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11529 predicate (UseSSE<=1);
11530 match(Set dst (ConvL2D src));
11531 effect( KILL cr );
11532 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11533 "PUSH $src.lo\n\t"
11534 "FILD ST,[ESP + #0]\n\t"
11535 "ADD ESP,8\n\t"
11536 "FSTP_D $dst\t# D-round" %}
11537 opcode(0xDF, 0x5); /* DF /5 */
11538 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11539 ins_pipe( pipe_slow );
11540 %}
11541
11542 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11543 predicate (UseSSE>=2);
11544 match(Set dst (ConvL2D src));
11545 effect( KILL cr );
11546 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11547 "PUSH $src.lo\n\t"
11548 "FILD_D [ESP]\n\t"
11549 "FSTP_D [ESP]\n\t"
11550 "MOVSD $dst,[ESP]\n\t"
11551 "ADD ESP,8" %}
11552 opcode(0xDF, 0x5); /* DF /5 */
11553 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11554 ins_pipe( pipe_slow );
11555 %}
11556
11557 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11558 predicate (UseSSE>=1);
11559 match(Set dst (ConvL2F src));
11560 effect( KILL cr );
11561 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11562 "PUSH $src.lo\n\t"
11563 "FILD_D [ESP]\n\t"
11564 "FSTP_S [ESP]\n\t"
11565 "MOVSS $dst,[ESP]\n\t"
11566 "ADD ESP,8" %}
11567 opcode(0xDF, 0x5); /* DF /5 */
11568 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11569 ins_pipe( pipe_slow );
11570 %}
11571
11572 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11573 match(Set dst (ConvL2F src));
11574 effect( KILL cr );
11575 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11576 "PUSH $src.lo\n\t"
11577 "FILD ST,[ESP + #0]\n\t"
11578 "ADD ESP,8\n\t"
11579 "FSTP_S $dst\t# F-round" %}
11580 opcode(0xDF, 0x5); /* DF /5 */
11581 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11582 ins_pipe( pipe_slow );
11583 %}
11584
11585 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11586 match(Set dst (ConvL2I src));
11587 effect( DEF dst, USE src );
11588 format %{ "MOV $dst,$src.lo" %}
11589 ins_encode(enc_CopyL_Lo(dst,src));
11590 ins_pipe( ialu_reg_reg );
11591 %}
11592
11593
11594 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11595 match(Set dst (MoveF2I src));
11596 effect( DEF dst, USE src );
11597 ins_cost(100);
11598 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11599 ins_encode %{
11600 __ movl($dst$$Register, Address(rsp, $src$$disp));
11601 %}
11602 ins_pipe( ialu_reg_mem );
11603 %}
11604
11605 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11606 predicate(UseSSE==0);
11607 match(Set dst (MoveF2I src));
11608 effect( DEF dst, USE src );
11609
11610 ins_cost(125);
11611 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11612 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11613 ins_pipe( fpu_mem_reg );
11614 %}
11615
11616 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11617 predicate(UseSSE>=1);
11618 match(Set dst (MoveF2I src));
11619 effect( DEF dst, USE src );
11620
11621 ins_cost(95);
11622 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11623 ins_encode %{
11624 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11625 %}
11626 ins_pipe( pipe_slow );
11627 %}
11628
11629 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
11630 predicate(UseSSE>=2);
11631 match(Set dst (MoveF2I src));
11632 effect( DEF dst, USE src );
11633 ins_cost(85);
11634 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11635 ins_encode %{
11636 __ movdl($dst$$Register, $src$$XMMRegister);
11637 %}
11638 ins_pipe( pipe_slow );
11639 %}
11640
11641 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11642 match(Set dst (MoveI2F src));
11643 effect( DEF dst, USE src );
11644
11645 ins_cost(100);
11646 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11647 ins_encode %{
11648 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11649 %}
11650 ins_pipe( ialu_mem_reg );
11651 %}
11652
11653
11654 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11655 predicate(UseSSE==0);
11656 match(Set dst (MoveI2F src));
11657 effect(DEF dst, USE src);
11658
11659 ins_cost(125);
11660 format %{ "FLD_S $src\n\t"
11661 "FSTP $dst\t# MoveI2F_stack_reg" %}
11662 opcode(0xD9); /* D9 /0, FLD m32real */
11663 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11664 Pop_Reg_FPR(dst) );
11665 ins_pipe( fpu_reg_mem );
11666 %}
11667
11668 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11669 predicate(UseSSE>=1);
11670 match(Set dst (MoveI2F src));
11671 effect( DEF dst, USE src );
11672
11673 ins_cost(95);
11674 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11675 ins_encode %{
11676 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11677 %}
11678 ins_pipe( pipe_slow );
11679 %}
11680
11681 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
11682 predicate(UseSSE>=2);
11683 match(Set dst (MoveI2F src));
11684 effect( DEF dst, USE src );
11685
11686 ins_cost(85);
11687 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11688 ins_encode %{
11689 __ movdl($dst$$XMMRegister, $src$$Register);
11690 %}
11691 ins_pipe( pipe_slow );
11692 %}
11693
11694 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11695 match(Set dst (MoveD2L src));
11696 effect(DEF dst, USE src);
11697
11698 ins_cost(250);
11699 format %{ "MOV $dst.lo,$src\n\t"
11700 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11701 opcode(0x8B, 0x8B);
11702 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11703 ins_pipe( ialu_mem_long_reg );
11704 %}
11705
11706 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11707 predicate(UseSSE<=1);
11708 match(Set dst (MoveD2L src));
11709 effect(DEF dst, USE src);
11710
11711 ins_cost(125);
11712 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11713 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11714 ins_pipe( fpu_mem_reg );
11715 %}
11716
11717 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11718 predicate(UseSSE>=2);
11719 match(Set dst (MoveD2L src));
11720 effect(DEF dst, USE src);
11721 ins_cost(95);
11722 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11723 ins_encode %{
11724 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11725 %}
11726 ins_pipe( pipe_slow );
11727 %}
11728
11729 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11730 predicate(UseSSE>=2);
11731 match(Set dst (MoveD2L src));
11732 effect(DEF dst, USE src, TEMP tmp);
11733 ins_cost(85);
11734 format %{ "MOVD $dst.lo,$src\n\t"
11735 "PSHUFLW $tmp,$src,0x4E\n\t"
11736 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11737 ins_encode %{
11738 __ movdl($dst$$Register, $src$$XMMRegister);
11739 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11740 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11741 %}
11742 ins_pipe( pipe_slow );
11743 %}
11744
11745 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11746 match(Set dst (MoveL2D src));
11747 effect(DEF dst, USE src);
11748
11749 ins_cost(200);
11750 format %{ "MOV $dst,$src.lo\n\t"
11751 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11752 opcode(0x89, 0x89);
11753 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11754 ins_pipe( ialu_mem_long_reg );
11755 %}
11756
11757
11758 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11759 predicate(UseSSE<=1);
11760 match(Set dst (MoveL2D src));
11761 effect(DEF dst, USE src);
11762 ins_cost(125);
11763
11764 format %{ "FLD_D $src\n\t"
11765 "FSTP $dst\t# MoveL2D_stack_reg" %}
11766 opcode(0xDD); /* DD /0, FLD m64real */
11767 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11768 Pop_Reg_DPR(dst) );
11769 ins_pipe( fpu_reg_mem );
11770 %}
11771
11772
11773 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11774 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11775 match(Set dst (MoveL2D src));
11776 effect(DEF dst, USE src);
11777
11778 ins_cost(95);
11779 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11780 ins_encode %{
11781 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11782 %}
11783 ins_pipe( pipe_slow );
11784 %}
11785
11786 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11787 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11788 match(Set dst (MoveL2D src));
11789 effect(DEF dst, USE src);
11790
11791 ins_cost(95);
11792 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11793 ins_encode %{
11794 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11795 %}
11796 ins_pipe( pipe_slow );
11797 %}
11798
11799 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11800 predicate(UseSSE>=2);
11801 match(Set dst (MoveL2D src));
11802 effect(TEMP dst, USE src, TEMP tmp);
11803 ins_cost(85);
11804 format %{ "MOVD $dst,$src.lo\n\t"
11805 "MOVD $tmp,$src.hi\n\t"
11806 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11807 ins_encode %{
11808 __ movdl($dst$$XMMRegister, $src$$Register);
11809 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11810 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11811 %}
11812 ins_pipe( pipe_slow );
11813 %}
11814
11815 // Replicate scalar to packed byte (1 byte) values in xmm
11816 instruct Repl8B_reg(regD dst, regD src) %{
11817 predicate(UseSSE>=2);
11818 match(Set dst (Replicate8B src));
11819 format %{ "MOVDQA $dst,$src\n\t"
11820 "PUNPCKLBW $dst,$dst\n\t"
11821 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11822 ins_encode %{
11823 if ($dst$$reg != $src$$reg) {
11824 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
11825 }
11826 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11827 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11828 %}
11829 ins_pipe( pipe_slow );
11830 %}
11831
11832 // Replicate scalar to packed byte (1 byte) values in xmm
11833 instruct Repl8B_eRegI(regD dst, eRegI src) %{
11834 predicate(UseSSE>=2);
11835 match(Set dst (Replicate8B src));
11836 format %{ "MOVD $dst,$src\n\t"
11837 "PUNPCKLBW $dst,$dst\n\t"
11838 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11839 ins_encode %{
11840 __ movdl($dst$$XMMRegister, $src$$Register);
11841 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11842 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11843 %}
11844 ins_pipe( pipe_slow );
11845 %}
11846
11847 // Replicate scalar zero to packed byte (1 byte) values in xmm
11848 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11849 predicate(UseSSE>=2);
11850 match(Set dst (Replicate8B zero));
11851 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11852 ins_encode %{
11853 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11854 %}
11855 ins_pipe( fpu_reg_reg );
11856 %}
11857
11858 // Replicate scalar to packed shore (2 byte) values in xmm
11859 instruct Repl4S_reg(regD dst, regD src) %{
11860 predicate(UseSSE>=2);
11861 match(Set dst (Replicate4S src));
11862 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11863 ins_encode %{
11864 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11865 %}
11866 ins_pipe( fpu_reg_reg );
11867 %}
11868
11869 // Replicate scalar to packed shore (2 byte) values in xmm
11870 instruct Repl4S_eRegI(regD dst, eRegI src) %{
11871 predicate(UseSSE>=2);
11872 match(Set dst (Replicate4S src));
11873 format %{ "MOVD $dst,$src\n\t"
11874 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11875 ins_encode %{
11876 __ movdl($dst$$XMMRegister, $src$$Register);
11877 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11878 %}
11879 ins_pipe( fpu_reg_reg );
11880 %}
11881
11882 // Replicate scalar zero to packed short (2 byte) values in xmm
11883 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11884 predicate(UseSSE>=2);
11885 match(Set dst (Replicate4S zero));
11886 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11887 ins_encode %{
11888 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11889 %}
11890 ins_pipe( fpu_reg_reg );
11891 %}
11892
11893 // Replicate scalar to packed char (2 byte) values in xmm
11894 instruct Repl4C_reg(regD dst, regD src) %{
11895 predicate(UseSSE>=2);
11896 match(Set dst (Replicate4C src));
11897 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11898 ins_encode %{
11899 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11900 %}
11901 ins_pipe( fpu_reg_reg );
11902 %}
11903
11904 // Replicate scalar to packed char (2 byte) values in xmm
11905 instruct Repl4C_eRegI(regD dst, eRegI src) %{
11906 predicate(UseSSE>=2);
11907 match(Set dst (Replicate4C src));
11908 format %{ "MOVD $dst,$src\n\t"
11909 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11910 ins_encode %{
11911 __ movdl($dst$$XMMRegister, $src$$Register);
11912 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11913 %}
11914 ins_pipe( fpu_reg_reg );
11915 %}
11916
11917 // Replicate scalar zero to packed char (2 byte) values in xmm
11918 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11919 predicate(UseSSE>=2);
11920 match(Set dst (Replicate4C zero));
11921 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11922 ins_encode %{
11923 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11924 %}
11925 ins_pipe( fpu_reg_reg );
11926 %}
11927
11928 // Replicate scalar to packed integer (4 byte) values in xmm
11929 instruct Repl2I_reg(regD dst, regD src) %{
11930 predicate(UseSSE>=2);
11931 match(Set dst (Replicate2I src));
11932 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11933 ins_encode %{
11934 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11935 %}
11936 ins_pipe( fpu_reg_reg );
11937 %}
11938
11939 // Replicate scalar to packed integer (4 byte) values in xmm
11940 instruct Repl2I_eRegI(regD dst, eRegI src) %{
11941 predicate(UseSSE>=2);
11942 match(Set dst (Replicate2I src));
11943 format %{ "MOVD $dst,$src\n\t"
11944 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11945 ins_encode %{
11946 __ movdl($dst$$XMMRegister, $src$$Register);
11947 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11948 %}
11949 ins_pipe( fpu_reg_reg );
11950 %}
11951
11952 // Replicate scalar zero to packed integer (2 byte) values in xmm
11953 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11954 predicate(UseSSE>=2);
11955 match(Set dst (Replicate2I zero));
11956 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11957 ins_encode %{
11958 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11959 %}
11960 ins_pipe( fpu_reg_reg );
11961 %}
11962
11963 // Replicate scalar to packed single precision floating point values in xmm
11964 instruct Repl2F_reg(regD dst, regD src) %{
11965 predicate(UseSSE>=2);
11966 match(Set dst (Replicate2F src));
11967 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11968 ins_encode %{
11969 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11970 %}
11971 ins_pipe( fpu_reg_reg );
11972 %}
11973
11974 // Replicate scalar to packed single precision floating point values in xmm
11975 instruct Repl2F_regF(regD dst, regF src) %{
11976 predicate(UseSSE>=2);
11977 match(Set dst (Replicate2F src));
11978 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11979 ins_encode %{
11980 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11981 %}
11982 ins_pipe( fpu_reg_reg );
11983 %}
11984
11985 // Replicate scalar to packed single precision floating point values in xmm
11986 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11987 predicate(UseSSE>=2);
11988 match(Set dst (Replicate2F zero));
11989 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11990 ins_encode %{
11991 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11992 %}
11993 ins_pipe( fpu_reg_reg );
11994 %}
11995
11996 // =======================================================================
11997 // fast clearing of an array
11998 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11999 match(Set dummy (ClearArray cnt base));
12000 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12001 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12002 "XOR EAX,EAX\n\t"
12003 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12004 opcode(0,0x4);
12005 ins_encode( Opcode(0xD1), RegOpc(ECX),
12006 OpcRegReg(0x33,EAX,EAX),
12007 Opcode(0xF3), Opcode(0xAB) );
12008 ins_pipe( pipe_slow );
12009 %}
12010
12011 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
12012 eAXRegI result, regD tmp1, eFlagsReg cr) %{
12013 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12014 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12015
12016 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12017 ins_encode %{
12018 __ string_compare($str1$$Register, $str2$$Register,
12019 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12020 $tmp1$$XMMRegister);
12021 %}
12022 ins_pipe( pipe_slow );
12023 %}
12024
12025 // fast string equals
12026 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12027 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12028 match(Set result (StrEquals (Binary str1 str2) cnt));
12029 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12030
12031 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12032 ins_encode %{
12033 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12034 $cnt$$Register, $result$$Register, $tmp3$$Register,
12035 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12036 %}
12037 ins_pipe( pipe_slow );
12038 %}
12039
12040 // fast search of substring with known size.
12041 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12042 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12043 predicate(UseSSE42Intrinsics);
12044 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12045 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12046
12047 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12048 ins_encode %{
12049 int icnt2 = (int)$int_cnt2$$constant;
12050 if (icnt2 >= 8) {
12051 // IndexOf for constant substrings with size >= 8 elements
12052 // which don't need to be loaded through stack.
12053 __ string_indexofC8($str1$$Register, $str2$$Register,
12054 $cnt1$$Register, $cnt2$$Register,
12055 icnt2, $result$$Register,
12056 $vec$$XMMRegister, $tmp$$Register);
12057 } else {
12058 // Small strings are loaded through stack if they cross page boundary.
12059 __ string_indexof($str1$$Register, $str2$$Register,
12060 $cnt1$$Register, $cnt2$$Register,
12061 icnt2, $result$$Register,
12062 $vec$$XMMRegister, $tmp$$Register);
12063 }
12064 %}
12065 ins_pipe( pipe_slow );
12066 %}
12067
12068 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12069 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
12070 predicate(UseSSE42Intrinsics);
12071 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12072 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12073
12074 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12075 ins_encode %{
12076 __ string_indexof($str1$$Register, $str2$$Register,
12077 $cnt1$$Register, $cnt2$$Register,
12078 (-1), $result$$Register,
12079 $vec$$XMMRegister, $tmp$$Register);
12080 %}
12081 ins_pipe( pipe_slow );
12082 %}
12083
12084 // fast array equals
12085 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12086 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12087 %{
12088 match(Set result (AryEq ary1 ary2));
12089 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12090 //ins_cost(300);
12091
12092 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12093 ins_encode %{
12094 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12095 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12096 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12097 %}
12098 ins_pipe( pipe_slow );
12099 %}
12100
12101 //----------Control Flow Instructions------------------------------------------
12102 // Signed compare Instructions
12103 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12104 match(Set cr (CmpI op1 op2));
12105 effect( DEF cr, USE op1, USE op2 );
12106 format %{ "CMP $op1,$op2" %}
12107 opcode(0x3B); /* Opcode 3B /r */
12108 ins_encode( OpcP, RegReg( op1, op2) );
12109 ins_pipe( ialu_cr_reg_reg );
12110 %}
12111
12112 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12113 match(Set cr (CmpI op1 op2));
12114 effect( DEF cr, USE op1 );
12115 format %{ "CMP $op1,$op2" %}
12116 opcode(0x81,0x07); /* Opcode 81 /7 */
12117 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12118 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12119 ins_pipe( ialu_cr_reg_imm );
12120 %}
12121
12122 // Cisc-spilled version of cmpI_eReg
12123 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12124 match(Set cr (CmpI op1 (LoadI op2)));
12125
12126 format %{ "CMP $op1,$op2" %}
12127 ins_cost(500);
12128 opcode(0x3B); /* Opcode 3B /r */
12129 ins_encode( OpcP, RegMem( op1, op2) );
12130 ins_pipe( ialu_cr_reg_mem );
12131 %}
12132
12133 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12134 match(Set cr (CmpI src zero));
12135 effect( DEF cr, USE src );
12136
12137 format %{ "TEST $src,$src" %}
12138 opcode(0x85);
12139 ins_encode( OpcP, RegReg( src, src ) );
12140 ins_pipe( ialu_cr_reg_imm );
12141 %}
12142
12143 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12144 match(Set cr (CmpI (AndI src con) zero));
12145
12146 format %{ "TEST $src,$con" %}
12147 opcode(0xF7,0x00);
12148 ins_encode( OpcP, RegOpc(src), Con32(con) );
12149 ins_pipe( ialu_cr_reg_imm );
12150 %}
12151
12152 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12153 match(Set cr (CmpI (AndI src mem) zero));
12154
12155 format %{ "TEST $src,$mem" %}
12156 opcode(0x85);
12157 ins_encode( OpcP, RegMem( src, mem ) );
12158 ins_pipe( ialu_cr_reg_mem );
12159 %}
12160
12161 // Unsigned compare Instructions; really, same as signed except they
12162 // produce an eFlagsRegU instead of eFlagsReg.
12163 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12164 match(Set cr (CmpU op1 op2));
12165
12166 format %{ "CMPu $op1,$op2" %}
12167 opcode(0x3B); /* Opcode 3B /r */
12168 ins_encode( OpcP, RegReg( op1, op2) );
12169 ins_pipe( ialu_cr_reg_reg );
12170 %}
12171
12172 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12173 match(Set cr (CmpU op1 op2));
12174
12175 format %{ "CMPu $op1,$op2" %}
12176 opcode(0x81,0x07); /* Opcode 81 /7 */
12177 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12178 ins_pipe( ialu_cr_reg_imm );
12179 %}
12180
12181 // // Cisc-spilled version of cmpU_eReg
12182 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12183 match(Set cr (CmpU op1 (LoadI op2)));
12184
12185 format %{ "CMPu $op1,$op2" %}
12186 ins_cost(500);
12187 opcode(0x3B); /* Opcode 3B /r */
12188 ins_encode( OpcP, RegMem( op1, op2) );
12189 ins_pipe( ialu_cr_reg_mem );
12190 %}
12191
12192 // // Cisc-spilled version of cmpU_eReg
12193 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12194 // match(Set cr (CmpU (LoadI op1) op2));
12195 //
12196 // format %{ "CMPu $op1,$op2" %}
12197 // ins_cost(500);
12198 // opcode(0x39); /* Opcode 39 /r */
12199 // ins_encode( OpcP, RegMem( op1, op2) );
12200 //%}
12201
12202 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12203 match(Set cr (CmpU src zero));
12204
12205 format %{ "TESTu $src,$src" %}
12206 opcode(0x85);
12207 ins_encode( OpcP, RegReg( src, src ) );
12208 ins_pipe( ialu_cr_reg_imm );
12209 %}
12210
12211 // Unsigned pointer compare Instructions
12212 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12213 match(Set cr (CmpP op1 op2));
12214
12215 format %{ "CMPu $op1,$op2" %}
12216 opcode(0x3B); /* Opcode 3B /r */
12217 ins_encode( OpcP, RegReg( op1, op2) );
12218 ins_pipe( ialu_cr_reg_reg );
12219 %}
12220
12221 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12222 match(Set cr (CmpP op1 op2));
12223
12224 format %{ "CMPu $op1,$op2" %}
12225 opcode(0x81,0x07); /* Opcode 81 /7 */
12226 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12227 ins_pipe( ialu_cr_reg_imm );
12228 %}
12229
12230 // // Cisc-spilled version of cmpP_eReg
12231 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12232 match(Set cr (CmpP op1 (LoadP op2)));
12233
12234 format %{ "CMPu $op1,$op2" %}
12235 ins_cost(500);
12236 opcode(0x3B); /* Opcode 3B /r */
12237 ins_encode( OpcP, RegMem( op1, op2) );
12238 ins_pipe( ialu_cr_reg_mem );
12239 %}
12240
12241 // // Cisc-spilled version of cmpP_eReg
12242 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12243 // match(Set cr (CmpP (LoadP op1) op2));
12244 //
12245 // format %{ "CMPu $op1,$op2" %}
12246 // ins_cost(500);
12247 // opcode(0x39); /* Opcode 39 /r */
12248 // ins_encode( OpcP, RegMem( op1, op2) );
12249 //%}
12250
12251 // Compare raw pointer (used in out-of-heap check).
12252 // Only works because non-oop pointers must be raw pointers
12253 // and raw pointers have no anti-dependencies.
12254 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12255 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12256 match(Set cr (CmpP op1 (LoadP op2)));
12257
12258 format %{ "CMPu $op1,$op2" %}
12259 opcode(0x3B); /* Opcode 3B /r */
12260 ins_encode( OpcP, RegMem( op1, op2) );
12261 ins_pipe( ialu_cr_reg_mem );
12262 %}
12263
12264 //
12265 // This will generate a signed flags result. This should be ok
12266 // since any compare to a zero should be eq/neq.
12267 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12268 match(Set cr (CmpP src zero));
12269
12270 format %{ "TEST $src,$src" %}
12271 opcode(0x85);
12272 ins_encode( OpcP, RegReg( src, src ) );
12273 ins_pipe( ialu_cr_reg_imm );
12274 %}
12275
12276 // Cisc-spilled version of testP_reg
12277 // This will generate a signed flags result. This should be ok
12278 // since any compare to a zero should be eq/neq.
12279 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12280 match(Set cr (CmpP (LoadP op) zero));
12281
12282 format %{ "TEST $op,0xFFFFFFFF" %}
12283 ins_cost(500);
12284 opcode(0xF7); /* Opcode F7 /0 */
12285 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12286 ins_pipe( ialu_cr_reg_imm );
12287 %}
12288
12289 // Yanked all unsigned pointer compare operations.
12290 // Pointer compares are done with CmpP which is already unsigned.
12291
12292 //----------Max and Min--------------------------------------------------------
12293 // Min Instructions
12294 ////
12295 // *** Min and Max using the conditional move are slower than the
12296 // *** branch version on a Pentium III.
12297 // // Conditional move for min
12298 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12299 // effect( USE_DEF op2, USE op1, USE cr );
12300 // format %{ "CMOVlt $op2,$op1\t! min" %}
12301 // opcode(0x4C,0x0F);
12302 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12303 // ins_pipe( pipe_cmov_reg );
12304 //%}
12305 //
12306 //// Min Register with Register (P6 version)
12307 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12308 // predicate(VM_Version::supports_cmov() );
12309 // match(Set op2 (MinI op1 op2));
12310 // ins_cost(200);
12311 // expand %{
12312 // eFlagsReg cr;
12313 // compI_eReg(cr,op1,op2);
12314 // cmovI_reg_lt(op2,op1,cr);
12315 // %}
12316 //%}
12317
12318 // Min Register with Register (generic version)
12319 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12320 match(Set dst (MinI dst src));
12321 effect(KILL flags);
12322 ins_cost(300);
12323
12324 format %{ "MIN $dst,$src" %}
12325 opcode(0xCC);
12326 ins_encode( min_enc(dst,src) );
12327 ins_pipe( pipe_slow );
12328 %}
12329
12330 // Max Register with Register
12331 // *** Min and Max using the conditional move are slower than the
12332 // *** branch version on a Pentium III.
12333 // // Conditional move for max
12334 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12335 // effect( USE_DEF op2, USE op1, USE cr );
12336 // format %{ "CMOVgt $op2,$op1\t! max" %}
12337 // opcode(0x4F,0x0F);
12338 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12339 // ins_pipe( pipe_cmov_reg );
12340 //%}
12341 //
12342 // // Max Register with Register (P6 version)
12343 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12344 // predicate(VM_Version::supports_cmov() );
12345 // match(Set op2 (MaxI op1 op2));
12346 // ins_cost(200);
12347 // expand %{
12348 // eFlagsReg cr;
12349 // compI_eReg(cr,op1,op2);
12350 // cmovI_reg_gt(op2,op1,cr);
12351 // %}
12352 //%}
12353
12354 // Max Register with Register (generic version)
12355 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12356 match(Set dst (MaxI dst src));
12357 effect(KILL flags);
12358 ins_cost(300);
12359
12360 format %{ "MAX $dst,$src" %}
12361 opcode(0xCC);
12362 ins_encode( max_enc(dst,src) );
12363 ins_pipe( pipe_slow );
12364 %}
12365
12366 // ============================================================================
12367 // Counted Loop limit node which represents exact final iterator value.
12368 // Note: the resulting value should fit into integer range since
12369 // counted loops have limit check on overflow.
12370 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12371 match(Set limit (LoopLimit (Binary init limit) stride));
12372 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12373 ins_cost(300);
12374
12375 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12376 ins_encode %{
12377 int strd = (int)$stride$$constant;
12378 assert(strd != 1 && strd != -1, "sanity");
12379 int m1 = (strd > 0) ? 1 : -1;
12380 // Convert limit to long (EAX:EDX)
12381 __ cdql();
12382 // Convert init to long (init:tmp)
12383 __ movl($tmp$$Register, $init$$Register);
12384 __ sarl($tmp$$Register, 31);
12385 // $limit - $init
12386 __ subl($limit$$Register, $init$$Register);
12387 __ sbbl($limit_hi$$Register, $tmp$$Register);
12388 // + ($stride - 1)
12389 if (strd > 0) {
12390 __ addl($limit$$Register, (strd - 1));
12391 __ adcl($limit_hi$$Register, 0);
12392 __ movl($tmp$$Register, strd);
12393 } else {
12394 __ addl($limit$$Register, (strd + 1));
12395 __ adcl($limit_hi$$Register, -1);
12396 __ lneg($limit_hi$$Register, $limit$$Register);
12397 __ movl($tmp$$Register, -strd);
12398 }
12399 // signed devision: (EAX:EDX) / pos_stride
12400 __ idivl($tmp$$Register);
12401 if (strd < 0) {
12402 // restore sign
12403 __ negl($tmp$$Register);
12404 }
12405 // (EAX) * stride
12406 __ mull($tmp$$Register);
12407 // + init (ignore upper bits)
12408 __ addl($limit$$Register, $init$$Register);
12409 %}
12410 ins_pipe( pipe_slow );
12411 %}
12412
12413 // ============================================================================
12414 // Branch Instructions
12415 // Jump Table
12416 instruct jumpXtnd(eRegI switch_val) %{
12417 match(Jump switch_val);
12418 ins_cost(350);
12419 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12420 ins_encode %{
12421 // Jump to Address(table_base + switch_reg)
12422 Address index(noreg, $switch_val$$Register, Address::times_1);
12423 __ jump(ArrayAddress($constantaddress, index));
12424 %}
12425 ins_pipe(pipe_jmp);
12426 %}
12427
12428 // Jump Direct - Label defines a relative address from JMP+1
12429 instruct jmpDir(label labl) %{
12430 match(Goto);
12431 effect(USE labl);
12432
12433 ins_cost(300);
12434 format %{ "JMP $labl" %}
12435 size(5);
12436 ins_encode %{
12437 Label* L = $labl$$label;
12438 __ jmp(*L, false); // Always long jump
12439 %}
12440 ins_pipe( pipe_jmp );
12441 %}
12442
12443 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12444 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12445 match(If cop cr);
12446 effect(USE labl);
12447
12448 ins_cost(300);
12449 format %{ "J$cop $labl" %}
12450 size(6);
12451 ins_encode %{
12452 Label* L = $labl$$label;
12453 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12454 %}
12455 ins_pipe( pipe_jcc );
12456 %}
12457
12458 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12459 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12460 match(CountedLoopEnd cop cr);
12461 effect(USE labl);
12462
12463 ins_cost(300);
12464 format %{ "J$cop $labl\t# Loop end" %}
12465 size(6);
12466 ins_encode %{
12467 Label* L = $labl$$label;
12468 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12469 %}
12470 ins_pipe( pipe_jcc );
12471 %}
12472
12473 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12474 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12475 match(CountedLoopEnd cop cmp);
12476 effect(USE labl);
12477
12478 ins_cost(300);
12479 format %{ "J$cop,u $labl\t# Loop end" %}
12480 size(6);
12481 ins_encode %{
12482 Label* L = $labl$$label;
12483 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12484 %}
12485 ins_pipe( pipe_jcc );
12486 %}
12487
12488 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12489 match(CountedLoopEnd cop cmp);
12490 effect(USE labl);
12491
12492 ins_cost(200);
12493 format %{ "J$cop,u $labl\t# Loop end" %}
12494 size(6);
12495 ins_encode %{
12496 Label* L = $labl$$label;
12497 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12498 %}
12499 ins_pipe( pipe_jcc );
12500 %}
12501
12502 // Jump Direct Conditional - using unsigned comparison
12503 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12504 match(If cop cmp);
12505 effect(USE labl);
12506
12507 ins_cost(300);
12508 format %{ "J$cop,u $labl" %}
12509 size(6);
12510 ins_encode %{
12511 Label* L = $labl$$label;
12512 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12513 %}
12514 ins_pipe(pipe_jcc);
12515 %}
12516
12517 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12518 match(If cop cmp);
12519 effect(USE labl);
12520
12521 ins_cost(200);
12522 format %{ "J$cop,u $labl" %}
12523 size(6);
12524 ins_encode %{
12525 Label* L = $labl$$label;
12526 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12527 %}
12528 ins_pipe(pipe_jcc);
12529 %}
12530
12531 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12532 match(If cop cmp);
12533 effect(USE labl);
12534
12535 ins_cost(200);
12536 format %{ $$template
12537 if ($cop$$cmpcode == Assembler::notEqual) {
12538 $$emit$$"JP,u $labl\n\t"
12539 $$emit$$"J$cop,u $labl"
12540 } else {
12541 $$emit$$"JP,u done\n\t"
12542 $$emit$$"J$cop,u $labl\n\t"
12543 $$emit$$"done:"
12544 }
12545 %}
12546 ins_encode %{
12547 Label* l = $labl$$label;
12548 if ($cop$$cmpcode == Assembler::notEqual) {
12549 __ jcc(Assembler::parity, *l, false);
12550 __ jcc(Assembler::notEqual, *l, false);
12551 } else if ($cop$$cmpcode == Assembler::equal) {
12552 Label done;
12553 __ jccb(Assembler::parity, done);
12554 __ jcc(Assembler::equal, *l, false);
12555 __ bind(done);
12556 } else {
12557 ShouldNotReachHere();
12558 }
12559 %}
12560 ins_pipe(pipe_jcc);
12561 %}
12562
12563 // ============================================================================
12564 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12565 // array for an instance of the superklass. Set a hidden internal cache on a
12566 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12567 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12568 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12569 match(Set result (PartialSubtypeCheck sub super));
12570 effect( KILL rcx, KILL cr );
12571
12572 ins_cost(1100); // slightly larger than the next version
12573 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12574 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12575 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12576 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12577 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12578 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12579 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12580 "miss:\t" %}
12581
12582 opcode(0x1); // Force a XOR of EDI
12583 ins_encode( enc_PartialSubtypeCheck() );
12584 ins_pipe( pipe_slow );
12585 %}
12586
12587 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12588 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12589 effect( KILL rcx, KILL result );
12590
12591 ins_cost(1000);
12592 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12593 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12594 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12595 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12596 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12597 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12598 "miss:\t" %}
12599
12600 opcode(0x0); // No need to XOR EDI
12601 ins_encode( enc_PartialSubtypeCheck() );
12602 ins_pipe( pipe_slow );
12603 %}
12604
12605 // ============================================================================
12606 // Branch Instructions -- short offset versions
12607 //
12608 // These instructions are used to replace jumps of a long offset (the default
12609 // match) with jumps of a shorter offset. These instructions are all tagged
12610 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12611 // match rules in general matching. Instead, the ADLC generates a conversion
12612 // method in the MachNode which can be used to do in-place replacement of the
12613 // long variant with the shorter variant. The compiler will determine if a
12614 // branch can be taken by the is_short_branch_offset() predicate in the machine
12615 // specific code section of the file.
12616
12617 // Jump Direct - Label defines a relative address from JMP+1
12618 instruct jmpDir_short(label labl) %{
12619 match(Goto);
12620 effect(USE labl);
12621
12622 ins_cost(300);
12623 format %{ "JMP,s $labl" %}
12624 size(2);
12625 ins_encode %{
12626 Label* L = $labl$$label;
12627 __ jmpb(*L);
12628 %}
12629 ins_pipe( pipe_jmp );
12630 ins_short_branch(1);
12631 %}
12632
12633 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12634 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12635 match(If cop cr);
12636 effect(USE labl);
12637
12638 ins_cost(300);
12639 format %{ "J$cop,s $labl" %}
12640 size(2);
12641 ins_encode %{
12642 Label* L = $labl$$label;
12643 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12644 %}
12645 ins_pipe( pipe_jcc );
12646 ins_short_branch(1);
12647 %}
12648
12649 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12650 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12651 match(CountedLoopEnd cop cr);
12652 effect(USE labl);
12653
12654 ins_cost(300);
12655 format %{ "J$cop,s $labl\t# Loop end" %}
12656 size(2);
12657 ins_encode %{
12658 Label* L = $labl$$label;
12659 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12660 %}
12661 ins_pipe( pipe_jcc );
12662 ins_short_branch(1);
12663 %}
12664
12665 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12666 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12667 match(CountedLoopEnd cop cmp);
12668 effect(USE labl);
12669
12670 ins_cost(300);
12671 format %{ "J$cop,us $labl\t# Loop end" %}
12672 size(2);
12673 ins_encode %{
12674 Label* L = $labl$$label;
12675 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12676 %}
12677 ins_pipe( pipe_jcc );
12678 ins_short_branch(1);
12679 %}
12680
12681 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12682 match(CountedLoopEnd cop cmp);
12683 effect(USE labl);
12684
12685 ins_cost(300);
12686 format %{ "J$cop,us $labl\t# Loop end" %}
12687 size(2);
12688 ins_encode %{
12689 Label* L = $labl$$label;
12690 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12691 %}
12692 ins_pipe( pipe_jcc );
12693 ins_short_branch(1);
12694 %}
12695
12696 // Jump Direct Conditional - using unsigned comparison
12697 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12698 match(If cop cmp);
12699 effect(USE labl);
12700
12701 ins_cost(300);
12702 format %{ "J$cop,us $labl" %}
12703 size(2);
12704 ins_encode %{
12705 Label* L = $labl$$label;
12706 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12707 %}
12708 ins_pipe( pipe_jcc );
12709 ins_short_branch(1);
12710 %}
12711
12712 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12713 match(If cop cmp);
12714 effect(USE labl);
12715
12716 ins_cost(300);
12717 format %{ "J$cop,us $labl" %}
12718 size(2);
12719 ins_encode %{
12720 Label* L = $labl$$label;
12721 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12722 %}
12723 ins_pipe( pipe_jcc );
12724 ins_short_branch(1);
12725 %}
12726
12727 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12728 match(If cop cmp);
12729 effect(USE labl);
12730
12731 ins_cost(300);
12732 format %{ $$template
12733 if ($cop$$cmpcode == Assembler::notEqual) {
12734 $$emit$$"JP,u,s $labl\n\t"
12735 $$emit$$"J$cop,u,s $labl"
12736 } else {
12737 $$emit$$"JP,u,s done\n\t"
12738 $$emit$$"J$cop,u,s $labl\n\t"
12739 $$emit$$"done:"
12740 }
12741 %}
12742 size(4);
12743 ins_encode %{
12744 Label* l = $labl$$label;
12745 if ($cop$$cmpcode == Assembler::notEqual) {
12746 __ jccb(Assembler::parity, *l);
12747 __ jccb(Assembler::notEqual, *l);
12748 } else if ($cop$$cmpcode == Assembler::equal) {
12749 Label done;
12750 __ jccb(Assembler::parity, done);
12751 __ jccb(Assembler::equal, *l);
12752 __ bind(done);
12753 } else {
12754 ShouldNotReachHere();
12755 }
12756 %}
12757 ins_pipe(pipe_jcc);
12758 ins_short_branch(1);
12759 %}
12760
12761 // ============================================================================
12762 // Long Compare
12763 //
12764 // Currently we hold longs in 2 registers. Comparing such values efficiently
12765 // is tricky. The flavor of compare used depends on whether we are testing
12766 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12767 // The GE test is the negated LT test. The LE test can be had by commuting
12768 // the operands (yielding a GE test) and then negating; negate again for the
12769 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12770 // NE test is negated from that.
12771
12772 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12773 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12774 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12775 // are collapsed internally in the ADLC's dfa-gen code. The match for
12776 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12777 // foo match ends up with the wrong leaf. One fix is to not match both
12778 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12779 // both forms beat the trinary form of long-compare and both are very useful
12780 // on Intel which has so few registers.
12781
12782 // Manifest a CmpL result in an integer register. Very painful.
12783 // This is the test to avoid.
12784 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12785 match(Set dst (CmpL3 src1 src2));
12786 effect( KILL flags );
12787 ins_cost(1000);
12788 format %{ "XOR $dst,$dst\n\t"
12789 "CMP $src1.hi,$src2.hi\n\t"
12790 "JLT,s m_one\n\t"
12791 "JGT,s p_one\n\t"
12792 "CMP $src1.lo,$src2.lo\n\t"
12793 "JB,s m_one\n\t"
12794 "JEQ,s done\n"
12795 "p_one:\tINC $dst\n\t"
12796 "JMP,s done\n"
12797 "m_one:\tDEC $dst\n"
12798 "done:" %}
12799 ins_encode %{
12800 Label p_one, m_one, done;
12801 __ xorptr($dst$$Register, $dst$$Register);
12802 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12803 __ jccb(Assembler::less, m_one);
12804 __ jccb(Assembler::greater, p_one);
12805 __ cmpl($src1$$Register, $src2$$Register);
12806 __ jccb(Assembler::below, m_one);
12807 __ jccb(Assembler::equal, done);
12808 __ bind(p_one);
12809 __ incrementl($dst$$Register);
12810 __ jmpb(done);
12811 __ bind(m_one);
12812 __ decrementl($dst$$Register);
12813 __ bind(done);
12814 %}
12815 ins_pipe( pipe_slow );
12816 %}
12817
12818 //======
12819 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12820 // compares. Can be used for LE or GT compares by reversing arguments.
12821 // NOT GOOD FOR EQ/NE tests.
12822 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12823 match( Set flags (CmpL src zero ));
12824 ins_cost(100);
12825 format %{ "TEST $src.hi,$src.hi" %}
12826 opcode(0x85);
12827 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12828 ins_pipe( ialu_cr_reg_reg );
12829 %}
12830
12831 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12832 // compares. Can be used for LE or GT compares by reversing arguments.
12833 // NOT GOOD FOR EQ/NE tests.
12834 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12835 match( Set flags (CmpL src1 src2 ));
12836 effect( TEMP tmp );
12837 ins_cost(300);
12838 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12839 "MOV $tmp,$src1.hi\n\t"
12840 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12841 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12842 ins_pipe( ialu_cr_reg_reg );
12843 %}
12844
12845 // Long compares reg < zero/req OR reg >= zero/req.
12846 // Just a wrapper for a normal branch, plus the predicate test.
12847 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12848 match(If cmp flags);
12849 effect(USE labl);
12850 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12851 expand %{
12852 jmpCon(cmp,flags,labl); // JLT or JGE...
12853 %}
12854 %}
12855
12856 // Compare 2 longs and CMOVE longs.
12857 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12858 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12859 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12860 ins_cost(400);
12861 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12862 "CMOV$cmp $dst.hi,$src.hi" %}
12863 opcode(0x0F,0x40);
12864 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12865 ins_pipe( pipe_cmov_reg_long );
12866 %}
12867
12868 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12869 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12870 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12871 ins_cost(500);
12872 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12873 "CMOV$cmp $dst.hi,$src.hi" %}
12874 opcode(0x0F,0x40);
12875 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12876 ins_pipe( pipe_cmov_reg_long );
12877 %}
12878
12879 // Compare 2 longs and CMOVE ints.
12880 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12881 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12882 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12883 ins_cost(200);
12884 format %{ "CMOV$cmp $dst,$src" %}
12885 opcode(0x0F,0x40);
12886 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12887 ins_pipe( pipe_cmov_reg );
12888 %}
12889
12890 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12891 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12892 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12893 ins_cost(250);
12894 format %{ "CMOV$cmp $dst,$src" %}
12895 opcode(0x0F,0x40);
12896 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12897 ins_pipe( pipe_cmov_mem );
12898 %}
12899
12900 // Compare 2 longs and CMOVE ints.
12901 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12902 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12903 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12904 ins_cost(200);
12905 format %{ "CMOV$cmp $dst,$src" %}
12906 opcode(0x0F,0x40);
12907 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12908 ins_pipe( pipe_cmov_reg );
12909 %}
12910
12911 // Compare 2 longs and CMOVE doubles
12912 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12913 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12914 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12915 ins_cost(200);
12916 expand %{
12917 fcmovDPR_regS(cmp,flags,dst,src);
12918 %}
12919 %}
12920
12921 // Compare 2 longs and CMOVE doubles
12922 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12923 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12924 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12925 ins_cost(200);
12926 expand %{
12927 fcmovD_regS(cmp,flags,dst,src);
12928 %}
12929 %}
12930
12931 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12932 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12933 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12934 ins_cost(200);
12935 expand %{
12936 fcmovFPR_regS(cmp,flags,dst,src);
12937 %}
12938 %}
12939
12940 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12941 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12942 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12943 ins_cost(200);
12944 expand %{
12945 fcmovF_regS(cmp,flags,dst,src);
12946 %}
12947 %}
12948
12949 //======
12950 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12951 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12952 match( Set flags (CmpL src zero ));
12953 effect(TEMP tmp);
12954 ins_cost(200);
12955 format %{ "MOV $tmp,$src.lo\n\t"
12956 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12957 ins_encode( long_cmp_flags0( src, tmp ) );
12958 ins_pipe( ialu_reg_reg_long );
12959 %}
12960
12961 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12962 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12963 match( Set flags (CmpL src1 src2 ));
12964 ins_cost(200+300);
12965 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12966 "JNE,s skip\n\t"
12967 "CMP $src1.hi,$src2.hi\n\t"
12968 "skip:\t" %}
12969 ins_encode( long_cmp_flags1( src1, src2 ) );
12970 ins_pipe( ialu_cr_reg_reg );
12971 %}
12972
12973 // Long compare reg == zero/reg OR reg != zero/reg
12974 // Just a wrapper for a normal branch, plus the predicate test.
12975 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12976 match(If cmp flags);
12977 effect(USE labl);
12978 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12979 expand %{
12980 jmpCon(cmp,flags,labl); // JEQ or JNE...
12981 %}
12982 %}
12983
12984 // Compare 2 longs and CMOVE longs.
12985 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12986 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12987 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12988 ins_cost(400);
12989 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12990 "CMOV$cmp $dst.hi,$src.hi" %}
12991 opcode(0x0F,0x40);
12992 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12993 ins_pipe( pipe_cmov_reg_long );
12994 %}
12995
12996 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12997 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12998 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12999 ins_cost(500);
13000 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13001 "CMOV$cmp $dst.hi,$src.hi" %}
13002 opcode(0x0F,0x40);
13003 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13004 ins_pipe( pipe_cmov_reg_long );
13005 %}
13006
13007 // Compare 2 longs and CMOVE ints.
13008 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13009 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13010 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13011 ins_cost(200);
13012 format %{ "CMOV$cmp $dst,$src" %}
13013 opcode(0x0F,0x40);
13014 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13015 ins_pipe( pipe_cmov_reg );
13016 %}
13017
13018 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13019 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13020 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13021 ins_cost(250);
13022 format %{ "CMOV$cmp $dst,$src" %}
13023 opcode(0x0F,0x40);
13024 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13025 ins_pipe( pipe_cmov_mem );
13026 %}
13027
13028 // Compare 2 longs and CMOVE ints.
13029 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13030 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13031 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13032 ins_cost(200);
13033 format %{ "CMOV$cmp $dst,$src" %}
13034 opcode(0x0F,0x40);
13035 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13036 ins_pipe( pipe_cmov_reg );
13037 %}
13038
13039 // Compare 2 longs and CMOVE doubles
13040 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
13041 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13042 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13043 ins_cost(200);
13044 expand %{
13045 fcmovDPR_regS(cmp,flags,dst,src);
13046 %}
13047 %}
13048
13049 // Compare 2 longs and CMOVE doubles
13050 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13051 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13052 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13053 ins_cost(200);
13054 expand %{
13055 fcmovD_regS(cmp,flags,dst,src);
13056 %}
13057 %}
13058
13059 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
13060 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13061 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13062 ins_cost(200);
13063 expand %{
13064 fcmovFPR_regS(cmp,flags,dst,src);
13065 %}
13066 %}
13067
13068 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13069 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13070 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13071 ins_cost(200);
13072 expand %{
13073 fcmovF_regS(cmp,flags,dst,src);
13074 %}
13075 %}
13076
13077 //======
13078 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13079 // Same as cmpL_reg_flags_LEGT except must negate src
13080 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13081 match( Set flags (CmpL src zero ));
13082 effect( TEMP tmp );
13083 ins_cost(300);
13084 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13085 "CMP $tmp,$src.lo\n\t"
13086 "SBB $tmp,$src.hi\n\t" %}
13087 ins_encode( long_cmp_flags3(src, tmp) );
13088 ins_pipe( ialu_reg_reg_long );
13089 %}
13090
13091 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13092 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13093 // requires a commuted test to get the same result.
13094 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13095 match( Set flags (CmpL src1 src2 ));
13096 effect( TEMP tmp );
13097 ins_cost(300);
13098 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13099 "MOV $tmp,$src2.hi\n\t"
13100 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13101 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13102 ins_pipe( ialu_cr_reg_reg );
13103 %}
13104
13105 // Long compares reg < zero/req OR reg >= zero/req.
13106 // Just a wrapper for a normal branch, plus the predicate test
13107 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13108 match(If cmp flags);
13109 effect(USE labl);
13110 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13111 ins_cost(300);
13112 expand %{
13113 jmpCon(cmp,flags,labl); // JGT or JLE...
13114 %}
13115 %}
13116
13117 // Compare 2 longs and CMOVE longs.
13118 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13119 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13120 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13121 ins_cost(400);
13122 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13123 "CMOV$cmp $dst.hi,$src.hi" %}
13124 opcode(0x0F,0x40);
13125 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13126 ins_pipe( pipe_cmov_reg_long );
13127 %}
13128
13129 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13130 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13131 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13132 ins_cost(500);
13133 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13134 "CMOV$cmp $dst.hi,$src.hi+4" %}
13135 opcode(0x0F,0x40);
13136 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13137 ins_pipe( pipe_cmov_reg_long );
13138 %}
13139
13140 // Compare 2 longs and CMOVE ints.
13141 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13142 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13143 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13144 ins_cost(200);
13145 format %{ "CMOV$cmp $dst,$src" %}
13146 opcode(0x0F,0x40);
13147 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13148 ins_pipe( pipe_cmov_reg );
13149 %}
13150
13151 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13152 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13153 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13154 ins_cost(250);
13155 format %{ "CMOV$cmp $dst,$src" %}
13156 opcode(0x0F,0x40);
13157 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13158 ins_pipe( pipe_cmov_mem );
13159 %}
13160
13161 // Compare 2 longs and CMOVE ptrs.
13162 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13163 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13164 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13165 ins_cost(200);
13166 format %{ "CMOV$cmp $dst,$src" %}
13167 opcode(0x0F,0x40);
13168 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13169 ins_pipe( pipe_cmov_reg );
13170 %}
13171
13172 // Compare 2 longs and CMOVE doubles
13173 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
13174 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13175 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13176 ins_cost(200);
13177 expand %{
13178 fcmovDPR_regS(cmp,flags,dst,src);
13179 %}
13180 %}
13181
13182 // Compare 2 longs and CMOVE doubles
13183 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13184 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13185 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13186 ins_cost(200);
13187 expand %{
13188 fcmovD_regS(cmp,flags,dst,src);
13189 %}
13190 %}
13191
13192 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
13193 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13194 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13195 ins_cost(200);
13196 expand %{
13197 fcmovFPR_regS(cmp,flags,dst,src);
13198 %}
13199 %}
13200
13201
13202 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13203 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13204 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13205 ins_cost(200);
13206 expand %{
13207 fcmovF_regS(cmp,flags,dst,src);
13208 %}
13209 %}
13210
13211
13212 // ============================================================================
13213 // Procedure Call/Return Instructions
13214 // Call Java Static Instruction
13215 // Note: If this code changes, the corresponding ret_addr_offset() and
13216 // compute_padding() functions will have to be adjusted.
13217 instruct CallStaticJavaDirect(method meth) %{
13218 match(CallStaticJava);
13219 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13220 effect(USE meth);
13221
13222 ins_cost(300);
13223 format %{ "CALL,static " %}
13224 opcode(0xE8); /* E8 cd */
13225 ins_encode( pre_call_FPU,
13226 Java_Static_Call( meth ),
13227 call_epilog,
13228 post_call_FPU );
13229 ins_pipe( pipe_slow );
13230 ins_alignment(4);
13231 %}
13232
13233 // Call Java Static Instruction (method handle version)
13234 // Note: If this code changes, the corresponding ret_addr_offset() and
13235 // compute_padding() functions will have to be adjusted.
13236 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13237 match(CallStaticJava);
13238 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13239 effect(USE meth);
13240 // EBP is saved by all callees (for interpreter stack correction).
13241 // We use it here for a similar purpose, in {preserve,restore}_SP.
13242
13243 ins_cost(300);
13244 format %{ "CALL,static/MethodHandle " %}
13245 opcode(0xE8); /* E8 cd */
13246 ins_encode( pre_call_FPU,
13247 preserve_SP,
13248 Java_Static_Call( meth ),
13249 restore_SP,
13250 call_epilog,
13251 post_call_FPU );
13252 ins_pipe( pipe_slow );
13253 ins_alignment(4);
13254 %}
13255
13256 // Call Java Dynamic Instruction
13257 // Note: If this code changes, the corresponding ret_addr_offset() and
13258 // compute_padding() functions will have to be adjusted.
13259 instruct CallDynamicJavaDirect(method meth) %{
13260 match(CallDynamicJava);
13261 effect(USE meth);
13262
13263 ins_cost(300);
13264 format %{ "MOV EAX,(oop)-1\n\t"
13265 "CALL,dynamic" %}
13266 opcode(0xE8); /* E8 cd */
13267 ins_encode( pre_call_FPU,
13268 Java_Dynamic_Call( meth ),
13269 call_epilog,
13270 post_call_FPU );
13271 ins_pipe( pipe_slow );
13272 ins_alignment(4);
13273 %}
13274
13275 // Call Runtime Instruction
13276 instruct CallRuntimeDirect(method meth) %{
13277 match(CallRuntime );
13278 effect(USE meth);
13279
13280 ins_cost(300);
13281 format %{ "CALL,runtime " %}
13282 opcode(0xE8); /* E8 cd */
13283 // Use FFREEs to clear entries in float stack
13284 ins_encode( pre_call_FPU,
13285 FFree_Float_Stack_All,
13286 Java_To_Runtime( meth ),
13287 post_call_FPU );
13288 ins_pipe( pipe_slow );
13289 %}
13290
13291 // Call runtime without safepoint
13292 instruct CallLeafDirect(method meth) %{
13293 match(CallLeaf);
13294 effect(USE meth);
13295
13296 ins_cost(300);
13297 format %{ "CALL_LEAF,runtime " %}
13298 opcode(0xE8); /* E8 cd */
13299 ins_encode( pre_call_FPU,
13300 FFree_Float_Stack_All,
13301 Java_To_Runtime( meth ),
13302 Verify_FPU_For_Leaf, post_call_FPU );
13303 ins_pipe( pipe_slow );
13304 %}
13305
13306 instruct CallLeafNoFPDirect(method meth) %{
13307 match(CallLeafNoFP);
13308 effect(USE meth);
13309
13310 ins_cost(300);
13311 format %{ "CALL_LEAF_NOFP,runtime " %}
13312 opcode(0xE8); /* E8 cd */
13313 ins_encode(Java_To_Runtime(meth));
13314 ins_pipe( pipe_slow );
13315 %}
13316
13317
13318 // Return Instruction
13319 // Remove the return address & jump to it.
13320 instruct Ret() %{
13321 match(Return);
13322 format %{ "RET" %}
13323 opcode(0xC3);
13324 ins_encode(OpcP);
13325 ins_pipe( pipe_jmp );
13326 %}
13327
13328 // Tail Call; Jump from runtime stub to Java code.
13329 // Also known as an 'interprocedural jump'.
13330 // Target of jump will eventually return to caller.
13331 // TailJump below removes the return address.
13332 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13333 match(TailCall jump_target method_oop );
13334 ins_cost(300);
13335 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13336 opcode(0xFF, 0x4); /* Opcode FF /4 */
13337 ins_encode( OpcP, RegOpc(jump_target) );
13338 ins_pipe( pipe_jmp );
13339 %}
13340
13341
13342 // Tail Jump; remove the return address; jump to target.
13343 // TailCall above leaves the return address around.
13344 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13345 match( TailJump jump_target ex_oop );
13346 ins_cost(300);
13347 format %{ "POP EDX\t# pop return address into dummy\n\t"
13348 "JMP $jump_target " %}
13349 opcode(0xFF, 0x4); /* Opcode FF /4 */
13350 ins_encode( enc_pop_rdx,
13351 OpcP, RegOpc(jump_target) );
13352 ins_pipe( pipe_jmp );
13353 %}
13354
13355 // Create exception oop: created by stack-crawling runtime code.
13356 // Created exception is now available to this handler, and is setup
13357 // just prior to jumping to this handler. No code emitted.
13358 instruct CreateException( eAXRegP ex_oop )
13359 %{
13360 match(Set ex_oop (CreateEx));
13361
13362 size(0);
13363 // use the following format syntax
13364 format %{ "# exception oop is in EAX; no code emitted" %}
13365 ins_encode();
13366 ins_pipe( empty );
13367 %}
13368
13369
13370 // Rethrow exception:
13371 // The exception oop will come in the first argument position.
13372 // Then JUMP (not call) to the rethrow stub code.
13373 instruct RethrowException()
13374 %{
13375 match(Rethrow);
13376
13377 // use the following format syntax
13378 format %{ "JMP rethrow_stub" %}
13379 ins_encode(enc_rethrow);
13380 ins_pipe( pipe_jmp );
13381 %}
13382
13383 // inlined locking and unlocking
13384
13385
13386 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13387 match( Set cr (FastLock object box) );
13388 effect( TEMP tmp, TEMP scr, USE_KILL box );
13389 ins_cost(300);
13390 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13391 ins_encode( Fast_Lock(object,box,tmp,scr) );
13392 ins_pipe( pipe_slow );
13393 %}
13394
13395 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13396 match( Set cr (FastUnlock object box) );
13397 effect( TEMP tmp, USE_KILL box );
13398 ins_cost(300);
13399 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13400 ins_encode( Fast_Unlock(object,box,tmp) );
13401 ins_pipe( pipe_slow );
13402 %}
13403
13404
13405
13406 // ============================================================================
13407 // Safepoint Instruction
13408 instruct safePoint_poll(eFlagsReg cr) %{
13409 match(SafePoint);
13410 effect(KILL cr);
13411
13412 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13413 // On SPARC that might be acceptable as we can generate the address with
13414 // just a sethi, saving an or. By polling at offset 0 we can end up
13415 // putting additional pressure on the index-0 in the D$. Because of
13416 // alignment (just like the situation at hand) the lower indices tend
13417 // to see more traffic. It'd be better to change the polling address
13418 // to offset 0 of the last $line in the polling page.
13419
13420 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13421 ins_cost(125);
13422 size(6) ;
13423 ins_encode( Safepoint_Poll() );
13424 ins_pipe( ialu_reg_mem );
13425 %}
13426
13427 //----------PEEPHOLE RULES-----------------------------------------------------
13428 // These must follow all instruction definitions as they use the names
13429 // defined in the instructions definitions.
13430 //
13431 // peepmatch ( root_instr_name [preceding_instruction]* );
13432 //
13433 // peepconstraint %{
13434 // (instruction_number.operand_name relational_op instruction_number.operand_name
13435 // [, ...] );
13436 // // instruction numbers are zero-based using left to right order in peepmatch
13437 //
13438 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13439 // // provide an instruction_number.operand_name for each operand that appears
13440 // // in the replacement instruction's match rule
13441 //
13442 // ---------VM FLAGS---------------------------------------------------------
13443 //
13444 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13445 //
13446 // Each peephole rule is given an identifying number starting with zero and
13447 // increasing by one in the order seen by the parser. An individual peephole
13448 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13449 // on the command-line.
13450 //
13451 // ---------CURRENT LIMITATIONS----------------------------------------------
13452 //
13453 // Only match adjacent instructions in same basic block
13454 // Only equality constraints
13455 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13456 // Only one replacement instruction
13457 //
13458 // ---------EXAMPLE----------------------------------------------------------
13459 //
13460 // // pertinent parts of existing instructions in architecture description
13461 // instruct movI(eRegI dst, eRegI src) %{
13462 // match(Set dst (CopyI src));
13463 // %}
13464 //
13465 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13466 // match(Set dst (AddI dst src));
13467 // effect(KILL cr);
13468 // %}
13469 //
13470 // // Change (inc mov) to lea
13471 // peephole %{
13472 // // increment preceeded by register-register move
13473 // peepmatch ( incI_eReg movI );
13474 // // require that the destination register of the increment
13475 // // match the destination register of the move
13476 // peepconstraint ( 0.dst == 1.dst );
13477 // // construct a replacement instruction that sets
13478 // // the destination to ( move's source register + one )
13479 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13480 // %}
13481 //
13482 // Implementation no longer uses movX instructions since
13483 // machine-independent system no longer uses CopyX nodes.
13484 //
13485 // peephole %{
13486 // peepmatch ( incI_eReg movI );
13487 // peepconstraint ( 0.dst == 1.dst );
13488 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13489 // %}
13490 //
13491 // peephole %{
13492 // peepmatch ( decI_eReg movI );
13493 // peepconstraint ( 0.dst == 1.dst );
13494 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13495 // %}
13496 //
13497 // peephole %{
13498 // peepmatch ( addI_eReg_imm movI );
13499 // peepconstraint ( 0.dst == 1.dst );
13500 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13501 // %}
13502 //
13503 // peephole %{
13504 // peepmatch ( addP_eReg_imm movP );
13505 // peepconstraint ( 0.dst == 1.dst );
13506 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13507 // %}
13508
13509 // // Change load of spilled value to only a spill
13510 // instruct storeI(memory mem, eRegI src) %{
13511 // match(Set mem (StoreI mem src));
13512 // %}
13513 //
13514 // instruct loadI(eRegI dst, memory mem) %{
13515 // match(Set dst (LoadI mem));
13516 // %}
13517 //
13518 peephole %{
13519 peepmatch ( loadI storeI );
13520 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13521 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13522 %}
13523
13524 //----------SMARTSPILL RULES---------------------------------------------------
13525 // These must follow all instruction definitions as they use the names
13526 // defined in the instructions definitions.