1 //
2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
143
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
146
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
149
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
152
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
155
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
158
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
161
162 #ifdef _WIN64
163
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
166
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
169
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
172
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
175
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
178
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
181
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
184
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
187
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
190
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
193
194 #else
195
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
198
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
201
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
204
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
207
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
210
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
213
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
216
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
219
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
222
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
225
226 #endif // _WIN64
227
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
229
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
237
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
254
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
272
273 alloc_class chunk2(RFLAGS);
274
275
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
302
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
317
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R13, R13_H,
330 R14, R14_H);
331
332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
333 RAX, RAX_H,
334 RDI, RDI_H,
335 RSI, RSI_H,
336 RCX, RCX_H,
337 RBX, RBX_H,
338 R8, R8_H,
339 R9, R9_H,
340 R10, R10_H,
341 R11, R11_H,
342 R13, R13_H,
343 R14, R14_H);
344
345 // Class for all pointer registers except RAX, RBX and RSP
346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
347 RBP, RBP_H,
348 RDI, RDI_H,
349 RSI, RSI_H,
350 RCX, RCX_H,
351 R8, R8_H,
352 R9, R9_H,
353 R10, R10_H,
354 R11, R11_H,
355 R13, R13_H,
356 R14, R14_H);
357
358 // Singleton class for RAX pointer register
359 reg_class ptr_rax_reg(RAX, RAX_H);
360
361 // Singleton class for RBX pointer register
362 reg_class ptr_rbx_reg(RBX, RBX_H);
363
364 // Singleton class for RSI pointer register
365 reg_class ptr_rsi_reg(RSI, RSI_H);
366
367 // Singleton class for RDI pointer register
368 reg_class ptr_rdi_reg(RDI, RDI_H);
369
370 // Singleton class for RBP pointer register
371 reg_class ptr_rbp_reg(RBP, RBP_H);
372
373 // Singleton class for stack pointer
374 reg_class ptr_rsp_reg(RSP, RSP_H);
375
376 // Singleton class for TLS pointer
377 reg_class ptr_r15_reg(R15, R15_H);
378
379 // Class for all long registers (except RSP)
380 reg_class long_reg(RAX, RAX_H,
381 RDX, RDX_H,
382 RBP, RBP_H,
383 RDI, RDI_H,
384 RSI, RSI_H,
385 RCX, RCX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers except RAX, RDX (and RSP)
395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
396 RDI, RDI_H,
397 RSI, RSI_H,
398 RCX, RCX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Class for all long registers except RCX (and RSP)
408 reg_class long_no_rcx_reg(RBP, RBP_H,
409 RDI, RDI_H,
410 RSI, RSI_H,
411 RAX, RAX_H,
412 RDX, RDX_H,
413 RBX, RBX_H,
414 R8, R8_H,
415 R9, R9_H,
416 R10, R10_H,
417 R11, R11_H,
418 R13, R13_H,
419 R14, R14_H);
420
421 // Class for all long registers except RAX (and RSP)
422 reg_class long_no_rax_reg(RBP, RBP_H,
423 RDX, RDX_H,
424 RDI, RDI_H,
425 RSI, RSI_H,
426 RCX, RCX_H,
427 RBX, RBX_H,
428 R8, R8_H,
429 R9, R9_H,
430 R10, R10_H,
431 R11, R11_H,
432 R13, R13_H,
433 R14, R14_H);
434
435 // Singleton class for RAX long register
436 reg_class long_rax_reg(RAX, RAX_H);
437
438 // Singleton class for RCX long register
439 reg_class long_rcx_reg(RCX, RCX_H);
440
441 // Singleton class for RDX long register
442 reg_class long_rdx_reg(RDX, RDX_H);
443
444 // Class for all int registers (except RSP)
445 reg_class int_reg(RAX,
446 RDX,
447 RBP,
448 RDI,
449 RSI,
450 RCX,
451 RBX,
452 R8,
453 R9,
454 R10,
455 R11,
456 R13,
457 R14);
458
459 // Class for all int registers except RCX (and RSP)
460 reg_class int_no_rcx_reg(RAX,
461 RDX,
462 RBP,
463 RDI,
464 RSI,
465 RBX,
466 R8,
467 R9,
468 R10,
469 R11,
470 R13,
471 R14);
472
473 // Class for all int registers except RAX, RDX (and RSP)
474 reg_class int_no_rax_rdx_reg(RBP,
475 RDI,
476 RSI,
477 RCX,
478 RBX,
479 R8,
480 R9,
481 R10,
482 R11,
483 R13,
484 R14);
485
486 // Singleton class for RAX int register
487 reg_class int_rax_reg(RAX);
488
489 // Singleton class for RBX int register
490 reg_class int_rbx_reg(RBX);
491
492 // Singleton class for RCX int register
493 reg_class int_rcx_reg(RCX);
494
495 // Singleton class for RCX int register
496 reg_class int_rdx_reg(RDX);
497
498 // Singleton class for RCX int register
499 reg_class int_rdi_reg(RDI);
500
501 // Singleton class for instruction pointer
502 // reg_class ip_reg(RIP);
503
504 // Singleton class for condition codes
505 reg_class int_flags(RFLAGS);
506
507 // Class for all float registers
508 reg_class float_reg(XMM0,
509 XMM1,
510 XMM2,
511 XMM3,
512 XMM4,
513 XMM5,
514 XMM6,
515 XMM7,
516 XMM8,
517 XMM9,
518 XMM10,
519 XMM11,
520 XMM12,
521 XMM13,
522 XMM14,
523 XMM15);
524
525 // Class for all double registers
526 reg_class double_reg(XMM0, XMM0_H,
527 XMM1, XMM1_H,
528 XMM2, XMM2_H,
529 XMM3, XMM3_H,
530 XMM4, XMM4_H,
531 XMM5, XMM5_H,
532 XMM6, XMM6_H,
533 XMM7, XMM7_H,
534 XMM8, XMM8_H,
535 XMM9, XMM9_H,
536 XMM10, XMM10_H,
537 XMM11, XMM11_H,
538 XMM12, XMM12_H,
539 XMM13, XMM13_H,
540 XMM14, XMM14_H,
541 XMM15, XMM15_H);
542 %}
543
544
545 //----------SOURCE BLOCK-------------------------------------------------------
546 // This is a block of C++ code which provides values, functions, and
547 // definitions necessary in the rest of the architecture description
548 source %{
549 #define RELOC_IMM64 Assembler::imm_operand
550 #define RELOC_DISP32 Assembler::disp32_operand
551
552 #define __ _masm.
553
554 static int preserve_SP_size() {
555 return 3; // rex.w, op, rm(reg/reg)
556 }
557
558 // !!!!! Special hack to get all types of calls to specify the byte offset
559 // from the start of the call to the point where the return address
560 // will point.
561 int MachCallStaticJavaNode::ret_addr_offset()
562 {
563 int offset = 5; // 5 bytes from start of call to where return address points
564 if (_method_handle_invoke)
565 offset += preserve_SP_size();
566 return offset;
567 }
568
569 int MachCallDynamicJavaNode::ret_addr_offset()
570 {
571 return 15; // 15 bytes from start of call to where return address points
572 }
573
574 // In os_cpu .ad file
575 // int MachCallRuntimeNode::ret_addr_offset()
576
577 // Indicate if the safepoint node needs the polling page as an input,
578 // it does if the polling page is more than disp32 away.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return Assembler::is_polling_page_far();
582 }
583
584 //
585 // Compute padding required for nodes which need alignment
586 //
587
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += 1; // skip call opcode byte
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
599 {
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
601 current_offset += 1; // skip call opcode byte
602 return round_to(current_offset, alignment_required()) - current_offset;
603 }
604
605 // The address of the call instruction needs to be 4-byte aligned to
606 // ensure that it does not span a cache line so that it can be patched.
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
608 {
609 current_offset += 11; // skip movq instruction + call opcode byte
610 return round_to(current_offset, alignment_required()) - current_offset;
611 }
612
613 #ifndef PRODUCT
614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
615 {
616 st->print("INT3");
617 }
618 #endif
619
620 // EMIT_RM()
621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
623 cbuf.insts()->emit_int8(c);
624 }
625
626 // EMIT_CC()
627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
628 unsigned char c = (unsigned char) (f1 | f2);
629 cbuf.insts()->emit_int8(c);
630 }
631
632 // EMIT_OPCODE()
633 void emit_opcode(CodeBuffer &cbuf, int code) {
634 cbuf.insts()->emit_int8((unsigned char) code);
635 }
636
637 // EMIT_OPCODE() w/ relocation information
638 void emit_opcode(CodeBuffer &cbuf,
639 int code, relocInfo::relocType reloc, int offset, int format)
640 {
641 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
642 emit_opcode(cbuf, code);
643 }
644
645 // EMIT_D8()
646 void emit_d8(CodeBuffer &cbuf, int d8) {
647 cbuf.insts()->emit_int8((unsigned char) d8);
648 }
649
650 // EMIT_D16()
651 void emit_d16(CodeBuffer &cbuf, int d16) {
652 cbuf.insts()->emit_int16(d16);
653 }
654
655 // EMIT_D32()
656 void emit_d32(CodeBuffer &cbuf, int d32) {
657 cbuf.insts()->emit_int32(d32);
658 }
659
660 // EMIT_D64()
661 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
662 cbuf.insts()->emit_int64(d64);
663 }
664
665 // emit 32 bit value and construct relocation entry from relocInfo::relocType
666 void emit_d32_reloc(CodeBuffer& cbuf,
667 int d32,
668 relocInfo::relocType reloc,
669 int format)
670 {
671 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
672 cbuf.relocate(cbuf.insts_mark(), reloc, format);
673 cbuf.insts()->emit_int32(d32);
674 }
675
676 // emit 32 bit value and construct relocation entry from RelocationHolder
677 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
678 #ifdef ASSERT
679 if (rspec.reloc()->type() == relocInfo::oop_type &&
680 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
681 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
682 }
683 #endif
684 cbuf.relocate(cbuf.insts_mark(), rspec, format);
685 cbuf.insts()->emit_int32(d32);
686 }
687
688 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
689 address next_ip = cbuf.insts_end() + 4;
690 emit_d32_reloc(cbuf, (int) (addr - next_ip),
691 external_word_Relocation::spec(addr),
692 RELOC_DISP32);
693 }
694
695
696 // emit 64 bit value and construct relocation entry from relocInfo::relocType
697 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
698 cbuf.relocate(cbuf.insts_mark(), reloc, format);
699 cbuf.insts()->emit_int64(d64);
700 }
701
702 // emit 64 bit value and construct relocation entry from RelocationHolder
703 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
704 #ifdef ASSERT
705 if (rspec.reloc()->type() == relocInfo::oop_type &&
706 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
707 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
708 "cannot embed scavengable oops in code");
709 }
710 #endif
711 cbuf.relocate(cbuf.insts_mark(), rspec, format);
712 cbuf.insts()->emit_int64(d64);
713 }
714
715 // Access stack slot for load or store
716 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
717 {
718 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
719 if (-0x80 <= disp && disp < 0x80) {
720 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
721 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
722 emit_d8(cbuf, disp); // Displacement // R/M byte
723 } else {
724 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
725 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
726 emit_d32(cbuf, disp); // Displacement // R/M byte
727 }
728 }
729
730 // rRegI ereg, memory mem) %{ // emit_reg_mem
731 void encode_RegMem(CodeBuffer &cbuf,
732 int reg,
733 int base, int index, int scale, int disp, bool disp_is_oop)
734 {
735 assert(!disp_is_oop, "cannot have disp");
736 int regenc = reg & 7;
737 int baseenc = base & 7;
738 int indexenc = index & 7;
739
740 // There is no index & no scale, use form without SIB byte
741 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
742 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
743 if (disp == 0 && base != RBP_enc && base != R13_enc) {
744 emit_rm(cbuf, 0x0, regenc, baseenc); // *
745 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
746 // If 8-bit displacement, mode 0x1
747 emit_rm(cbuf, 0x1, regenc, baseenc); // *
748 emit_d8(cbuf, disp);
749 } else {
750 // If 32-bit displacement
751 if (base == -1) { // Special flag for absolute address
752 emit_rm(cbuf, 0x0, regenc, 0x5); // *
753 if (disp_is_oop) {
754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
755 } else {
756 emit_d32(cbuf, disp);
757 }
758 } else {
759 // Normal base + offset
760 emit_rm(cbuf, 0x2, regenc, baseenc); // *
761 if (disp_is_oop) {
762 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
763 } else {
764 emit_d32(cbuf, disp);
765 }
766 }
767 }
768 } else {
769 // Else, encode with the SIB byte
770 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
771 if (disp == 0 && base != RBP_enc && base != R13_enc) {
772 // If no displacement
773 emit_rm(cbuf, 0x0, regenc, 0x4); // *
774 emit_rm(cbuf, scale, indexenc, baseenc);
775 } else {
776 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
777 // If 8-bit displacement, mode 0x1
778 emit_rm(cbuf, 0x1, regenc, 0x4); // *
779 emit_rm(cbuf, scale, indexenc, baseenc);
780 emit_d8(cbuf, disp);
781 } else {
782 // If 32-bit displacement
783 if (base == 0x04 ) {
784 emit_rm(cbuf, 0x2, regenc, 0x4);
785 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
786 } else {
787 emit_rm(cbuf, 0x2, regenc, 0x4);
788 emit_rm(cbuf, scale, indexenc, baseenc); // *
789 }
790 if (disp_is_oop) {
791 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
792 } else {
793 emit_d32(cbuf, disp);
794 }
795 }
796 }
797 }
798 }
799
800 // This could be in MacroAssembler but it's fairly C2 specific
801 void emit_cmpfp_fixup(MacroAssembler& _masm) {
802 Label exit;
803 __ jccb(Assembler::noParity, exit);
804 __ pushf();
805 //
806 // comiss/ucomiss instructions set ZF,PF,CF flags and
807 // zero OF,AF,SF for NaN values.
808 // Fixup flags by zeroing ZF,PF so that compare of NaN
809 // values returns 'less than' result (CF is set).
810 // Leave the rest of flags unchanged.
811 //
812 // 7 6 5 4 3 2 1 0
813 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
814 // 0 0 1 0 1 0 1 1 (0x2B)
815 //
816 __ andq(Address(rsp, 0), 0xffffff2b);
817 __ popf();
818 __ bind(exit);
819 }
820
821 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
822 Label done;
823 __ movl(dst, -1);
824 __ jcc(Assembler::parity, done);
825 __ jcc(Assembler::below, done);
826 __ setb(Assembler::notEqual, dst);
827 __ movzbl(dst, dst);
828 __ bind(done);
829 }
830
831
832 //=============================================================================
833 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
834
835 int Compile::ConstantTable::calculate_table_base_offset() const {
836 return 0; // absolute addressing, no offset
837 }
838
839 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
840 // Empty encoding
841 }
842
843 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
844 return 0;
845 }
846
847 #ifndef PRODUCT
848 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
849 st->print("# MachConstantBaseNode (empty encoding)");
850 }
851 #endif
852
853
854 //=============================================================================
855 #ifndef PRODUCT
856 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
857 {
858 Compile* C = ra_->C;
859
860 int framesize = C->frame_slots() << LogBytesPerInt;
861 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
862 // Remove wordSize for return adr already pushed
863 // and another for the RBP we are going to save
864 framesize -= 2*wordSize;
865 bool need_nop = true;
866
867 // Calls to C2R adapters often do not accept exceptional returns.
868 // We require that their callers must bang for them. But be
869 // careful, because some VM calls (such as call site linkage) can
870 // use several kilobytes of stack. But the stack safety zone should
871 // account for that. See bugs 4446381, 4468289, 4497237.
872 if (C->need_stack_bang(framesize)) {
873 st->print_cr("# stack bang"); st->print("\t");
874 need_nop = false;
875 }
876 st->print_cr("pushq rbp"); st->print("\t");
877
878 if (VerifyStackAtCalls) {
879 // Majik cookie to verify stack depth
880 st->print_cr("pushq 0xffffffffbadb100d"
881 "\t# Majik cookie for stack depth check");
882 st->print("\t");
883 framesize -= wordSize; // Remove 2 for cookie
884 need_nop = false;
885 }
886
887 if (framesize) {
888 st->print("subq rsp, #%d\t# Create frame", framesize);
889 if (framesize < 0x80 && need_nop) {
890 st->print("\n\tnop\t# nop for patch_verified_entry");
891 }
892 }
893 }
894 #endif
895
896 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
897 {
898 Compile* C = ra_->C;
899
900 // WARNING: Initial instruction MUST be 5 bytes or longer so that
901 // NativeJump::patch_verified_entry will be able to patch out the entry
902 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
903 // depth is ok at 5 bytes, the frame allocation can be either 3 or
904 // 6 bytes. So if we don't do the fldcw or the push then we must
905 // use the 6 byte frame allocation even if we have no frame. :-(
906 // If method sets FPU control word do it now
907
908 int framesize = C->frame_slots() << LogBytesPerInt;
909 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
910 // Remove wordSize for return adr already pushed
911 // and another for the RBP we are going to save
912 framesize -= 2*wordSize;
913 bool need_nop = true;
914
915 // Calls to C2R adapters often do not accept exceptional returns.
916 // We require that their callers must bang for them. But be
917 // careful, because some VM calls (such as call site linkage) can
918 // use several kilobytes of stack. But the stack safety zone should
919 // account for that. See bugs 4446381, 4468289, 4497237.
920 if (C->need_stack_bang(framesize)) {
921 MacroAssembler masm(&cbuf);
922 masm.generate_stack_overflow_check(framesize);
923 need_nop = false;
924 }
925
926 // We always push rbp so that on return to interpreter rbp will be
927 // restored correctly and we can correct the stack.
928 emit_opcode(cbuf, 0x50 | RBP_enc);
929
930 if (VerifyStackAtCalls) {
931 // Majik cookie to verify stack depth
932 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
933 emit_d32(cbuf, 0xbadb100d);
934 framesize -= wordSize; // Remove 2 for cookie
935 need_nop = false;
936 }
937
938 if (framesize) {
939 emit_opcode(cbuf, Assembler::REX_W);
940 if (framesize < 0x80) {
941 emit_opcode(cbuf, 0x83); // sub SP,#framesize
942 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
943 emit_d8(cbuf, framesize);
944 if (need_nop) {
945 emit_opcode(cbuf, 0x90); // nop
946 }
947 } else {
948 emit_opcode(cbuf, 0x81); // sub SP,#framesize
949 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
950 emit_d32(cbuf, framesize);
951 }
952 }
953
954 C->set_frame_complete(cbuf.insts_size());
955
956 #ifdef ASSERT
957 if (VerifyStackAtCalls) {
958 Label L;
959 MacroAssembler masm(&cbuf);
960 masm.push(rax);
961 masm.mov(rax, rsp);
962 masm.andptr(rax, StackAlignmentInBytes-1);
963 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
964 masm.pop(rax);
965 masm.jcc(Assembler::equal, L);
966 masm.stop("Stack is not properly aligned!");
967 masm.bind(L);
968 }
969 #endif
970
971 if (C->has_mach_constant_base_node()) {
972 // NOTE: We set the table base offset here because users might be
973 // emitted before MachConstantBaseNode.
974 Compile::ConstantTable& constant_table = C->constant_table();
975 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
976 }
977 }
978
979 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
980 {
981 return MachNode::size(ra_); // too many variables; just compute it
982 // the hard way
983 }
984
985 int MachPrologNode::reloc() const
986 {
987 return 0; // a large enough number
988 }
989
990 //=============================================================================
991 #ifndef PRODUCT
992 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
993 {
994 Compile* C = ra_->C;
995 int framesize = C->frame_slots() << LogBytesPerInt;
996 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
997 // Remove word for return adr already pushed
998 // and RBP
999 framesize -= 2*wordSize;
1000
1001 if (framesize) {
1002 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
1003 st->print("\t");
1004 }
1005
1006 st->print_cr("popq rbp");
1007 if (do_polling() && C->is_method_compilation()) {
1008 st->print("\t");
1009 if (Assembler::is_polling_page_far()) {
1010 st->print_cr("movq rscratch1, #polling_page_address\n\t"
1011 "testl rax, [rscratch1]\t"
1012 "# Safepoint: poll for GC");
1013 } else {
1014 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
1015 "# Safepoint: poll for GC");
1016 }
1017 }
1018 }
1019 #endif
1020
1021 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1022 {
1023 Compile* C = ra_->C;
1024 int framesize = C->frame_slots() << LogBytesPerInt;
1025 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1026 // Remove word for return adr already pushed
1027 // and RBP
1028 framesize -= 2*wordSize;
1029
1030 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1031
1032 if (framesize) {
1033 emit_opcode(cbuf, Assembler::REX_W);
1034 if (framesize < 0x80) {
1035 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1036 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1037 emit_d8(cbuf, framesize);
1038 } else {
1039 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1040 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1041 emit_d32(cbuf, framesize);
1042 }
1043 }
1044
1045 // popq rbp
1046 emit_opcode(cbuf, 0x58 | RBP_enc);
1047
1048 if (do_polling() && C->is_method_compilation()) {
1049 MacroAssembler _masm(&cbuf);
1050 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1051 if (Assembler::is_polling_page_far()) {
1052 __ lea(rscratch1, polling_page);
1053 __ relocate(relocInfo::poll_return_type);
1054 __ testl(rax, Address(rscratch1, 0));
1055 } else {
1056 __ testl(rax, polling_page);
1057 }
1058 }
1059 }
1060
1061 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1062 {
1063 return MachNode::size(ra_); // too many variables; just compute it
1064 // the hard way
1065 }
1066
1067 int MachEpilogNode::reloc() const
1068 {
1069 return 2; // a large enough number
1070 }
1071
1072 const Pipeline* MachEpilogNode::pipeline() const
1073 {
1074 return MachNode::pipeline_class();
1075 }
1076
1077 int MachEpilogNode::safepoint_offset() const
1078 {
1079 return 0;
1080 }
1081
1082 //=============================================================================
1083
1084 enum RC {
1085 rc_bad,
1086 rc_int,
1087 rc_float,
1088 rc_stack
1089 };
1090
1091 static enum RC rc_class(OptoReg::Name reg)
1092 {
1093 if( !OptoReg::is_valid(reg) ) return rc_bad;
1094
1095 if (OptoReg::is_stack(reg)) return rc_stack;
1096
1097 VMReg r = OptoReg::as_VMReg(reg);
1098
1099 if (r->is_Register()) return rc_int;
1100
1101 assert(r->is_XMMRegister(), "must be");
1102 return rc_float;
1103 }
1104
1105 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1106 PhaseRegAlloc* ra_,
1107 bool do_size,
1108 outputStream* st) const
1109 {
1110
1111 // Get registers to move
1112 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1113 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1114 OptoReg::Name dst_second = ra_->get_reg_second(this);
1115 OptoReg::Name dst_first = ra_->get_reg_first(this);
1116
1117 enum RC src_second_rc = rc_class(src_second);
1118 enum RC src_first_rc = rc_class(src_first);
1119 enum RC dst_second_rc = rc_class(dst_second);
1120 enum RC dst_first_rc = rc_class(dst_first);
1121
1122 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1123 "must move at least 1 register" );
1124
1125 if (src_first == dst_first && src_second == dst_second) {
1126 // Self copy, no move
1127 return 0;
1128 } else if (src_first_rc == rc_stack) {
1129 // mem ->
1130 if (dst_first_rc == rc_stack) {
1131 // mem -> mem
1132 assert(src_second != dst_first, "overlap");
1133 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1134 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1135 // 64-bit
1136 int src_offset = ra_->reg2offset(src_first);
1137 int dst_offset = ra_->reg2offset(dst_first);
1138 if (cbuf) {
1139 emit_opcode(*cbuf, 0xFF);
1140 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1141
1142 emit_opcode(*cbuf, 0x8F);
1143 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1144
1145 #ifndef PRODUCT
1146 } else if (!do_size) {
1147 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1148 "popq [rsp + #%d]",
1149 src_offset,
1150 dst_offset);
1151 #endif
1152 }
1153 return
1154 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1155 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1156 } else {
1157 // 32-bit
1158 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1159 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1160 // No pushl/popl, so:
1161 int src_offset = ra_->reg2offset(src_first);
1162 int dst_offset = ra_->reg2offset(dst_first);
1163 if (cbuf) {
1164 emit_opcode(*cbuf, Assembler::REX_W);
1165 emit_opcode(*cbuf, 0x89);
1166 emit_opcode(*cbuf, 0x44);
1167 emit_opcode(*cbuf, 0x24);
1168 emit_opcode(*cbuf, 0xF8);
1169
1170 emit_opcode(*cbuf, 0x8B);
1171 encode_RegMem(*cbuf,
1172 RAX_enc,
1173 RSP_enc, 0x4, 0, src_offset,
1174 false);
1175
1176 emit_opcode(*cbuf, 0x89);
1177 encode_RegMem(*cbuf,
1178 RAX_enc,
1179 RSP_enc, 0x4, 0, dst_offset,
1180 false);
1181
1182 emit_opcode(*cbuf, Assembler::REX_W);
1183 emit_opcode(*cbuf, 0x8B);
1184 emit_opcode(*cbuf, 0x44);
1185 emit_opcode(*cbuf, 0x24);
1186 emit_opcode(*cbuf, 0xF8);
1187
1188 #ifndef PRODUCT
1189 } else if (!do_size) {
1190 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1191 "movl rax, [rsp + #%d]\n\t"
1192 "movl [rsp + #%d], rax\n\t"
1193 "movq rax, [rsp - #8]",
1194 src_offset,
1195 dst_offset);
1196 #endif
1197 }
1198 return
1199 5 + // movq
1200 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1201 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1202 5; // movq
1203 }
1204 } else if (dst_first_rc == rc_int) {
1205 // mem -> gpr
1206 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1207 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1208 // 64-bit
1209 int offset = ra_->reg2offset(src_first);
1210 if (cbuf) {
1211 if (Matcher::_regEncode[dst_first] < 8) {
1212 emit_opcode(*cbuf, Assembler::REX_W);
1213 } else {
1214 emit_opcode(*cbuf, Assembler::REX_WR);
1215 }
1216 emit_opcode(*cbuf, 0x8B);
1217 encode_RegMem(*cbuf,
1218 Matcher::_regEncode[dst_first],
1219 RSP_enc, 0x4, 0, offset,
1220 false);
1221 #ifndef PRODUCT
1222 } else if (!do_size) {
1223 st->print("movq %s, [rsp + #%d]\t# spill",
1224 Matcher::regName[dst_first],
1225 offset);
1226 #endif
1227 }
1228 return
1229 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1230 } else {
1231 // 32-bit
1232 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1233 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1234 int offset = ra_->reg2offset(src_first);
1235 if (cbuf) {
1236 if (Matcher::_regEncode[dst_first] >= 8) {
1237 emit_opcode(*cbuf, Assembler::REX_R);
1238 }
1239 emit_opcode(*cbuf, 0x8B);
1240 encode_RegMem(*cbuf,
1241 Matcher::_regEncode[dst_first],
1242 RSP_enc, 0x4, 0, offset,
1243 false);
1244 #ifndef PRODUCT
1245 } else if (!do_size) {
1246 st->print("movl %s, [rsp + #%d]\t# spill",
1247 Matcher::regName[dst_first],
1248 offset);
1249 #endif
1250 }
1251 return
1252 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1253 ((Matcher::_regEncode[dst_first] < 8)
1254 ? 3
1255 : 4); // REX
1256 }
1257 } else if (dst_first_rc == rc_float) {
1258 // mem-> xmm
1259 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1260 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1261 // 64-bit
1262 int offset = ra_->reg2offset(src_first);
1263 if (cbuf) {
1264 MacroAssembler _masm(cbuf);
1265 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1266 #ifndef PRODUCT
1267 } else if (!do_size) {
1268 st->print("%s %s, [rsp + #%d]\t# spill",
1269 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1270 Matcher::regName[dst_first],
1271 offset);
1272 #endif
1273 }
1274 return
1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1276 ((Matcher::_regEncode[dst_first] >= 8)
1277 ? 6
1278 : (5 + ((UseAVX>0)?1:0))); // REX
1279 } else {
1280 // 32-bit
1281 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1282 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1283 int offset = ra_->reg2offset(src_first);
1284 if (cbuf) {
1285 MacroAssembler _masm(cbuf);
1286 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1287 #ifndef PRODUCT
1288 } else if (!do_size) {
1289 st->print("movss %s, [rsp + #%d]\t# spill",
1290 Matcher::regName[dst_first],
1291 offset);
1292 #endif
1293 }
1294 return
1295 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1296 ((Matcher::_regEncode[dst_first] >= 8)
1297 ? 6
1298 : (5 + ((UseAVX>0)?1:0))); // REX
1299 }
1300 }
1301 } else if (src_first_rc == rc_int) {
1302 // gpr ->
1303 if (dst_first_rc == rc_stack) {
1304 // gpr -> mem
1305 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1306 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1307 // 64-bit
1308 int offset = ra_->reg2offset(dst_first);
1309 if (cbuf) {
1310 if (Matcher::_regEncode[src_first] < 8) {
1311 emit_opcode(*cbuf, Assembler::REX_W);
1312 } else {
1313 emit_opcode(*cbuf, Assembler::REX_WR);
1314 }
1315 emit_opcode(*cbuf, 0x89);
1316 encode_RegMem(*cbuf,
1317 Matcher::_regEncode[src_first],
1318 RSP_enc, 0x4, 0, offset,
1319 false);
1320 #ifndef PRODUCT
1321 } else if (!do_size) {
1322 st->print("movq [rsp + #%d], %s\t# spill",
1323 offset,
1324 Matcher::regName[src_first]);
1325 #endif
1326 }
1327 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1328 } else {
1329 // 32-bit
1330 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1331 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1332 int offset = ra_->reg2offset(dst_first);
1333 if (cbuf) {
1334 if (Matcher::_regEncode[src_first] >= 8) {
1335 emit_opcode(*cbuf, Assembler::REX_R);
1336 }
1337 emit_opcode(*cbuf, 0x89);
1338 encode_RegMem(*cbuf,
1339 Matcher::_regEncode[src_first],
1340 RSP_enc, 0x4, 0, offset,
1341 false);
1342 #ifndef PRODUCT
1343 } else if (!do_size) {
1344 st->print("movl [rsp + #%d], %s\t# spill",
1345 offset,
1346 Matcher::regName[src_first]);
1347 #endif
1348 }
1349 return
1350 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1351 ((Matcher::_regEncode[src_first] < 8)
1352 ? 3
1353 : 4); // REX
1354 }
1355 } else if (dst_first_rc == rc_int) {
1356 // gpr -> gpr
1357 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1358 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1359 // 64-bit
1360 if (cbuf) {
1361 if (Matcher::_regEncode[dst_first] < 8) {
1362 if (Matcher::_regEncode[src_first] < 8) {
1363 emit_opcode(*cbuf, Assembler::REX_W);
1364 } else {
1365 emit_opcode(*cbuf, Assembler::REX_WB);
1366 }
1367 } else {
1368 if (Matcher::_regEncode[src_first] < 8) {
1369 emit_opcode(*cbuf, Assembler::REX_WR);
1370 } else {
1371 emit_opcode(*cbuf, Assembler::REX_WRB);
1372 }
1373 }
1374 emit_opcode(*cbuf, 0x8B);
1375 emit_rm(*cbuf, 0x3,
1376 Matcher::_regEncode[dst_first] & 7,
1377 Matcher::_regEncode[src_first] & 7);
1378 #ifndef PRODUCT
1379 } else if (!do_size) {
1380 st->print("movq %s, %s\t# spill",
1381 Matcher::regName[dst_first],
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 return 3; // REX
1386 } else {
1387 // 32-bit
1388 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1389 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1390 if (cbuf) {
1391 if (Matcher::_regEncode[dst_first] < 8) {
1392 if (Matcher::_regEncode[src_first] >= 8) {
1393 emit_opcode(*cbuf, Assembler::REX_B);
1394 }
1395 } else {
1396 if (Matcher::_regEncode[src_first] < 8) {
1397 emit_opcode(*cbuf, Assembler::REX_R);
1398 } else {
1399 emit_opcode(*cbuf, Assembler::REX_RB);
1400 }
1401 }
1402 emit_opcode(*cbuf, 0x8B);
1403 emit_rm(*cbuf, 0x3,
1404 Matcher::_regEncode[dst_first] & 7,
1405 Matcher::_regEncode[src_first] & 7);
1406 #ifndef PRODUCT
1407 } else if (!do_size) {
1408 st->print("movl %s, %s\t# spill",
1409 Matcher::regName[dst_first],
1410 Matcher::regName[src_first]);
1411 #endif
1412 }
1413 return
1414 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1415 ? 2
1416 : 3; // REX
1417 }
1418 } else if (dst_first_rc == rc_float) {
1419 // gpr -> xmm
1420 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1421 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1422 // 64-bit
1423 if (cbuf) {
1424 MacroAssembler _masm(cbuf);
1425 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1426 #ifndef PRODUCT
1427 } else if (!do_size) {
1428 st->print("movdq %s, %s\t# spill",
1429 Matcher::regName[dst_first],
1430 Matcher::regName[src_first]);
1431 #endif
1432 }
1433 return 5; // REX
1434 } else {
1435 // 32-bit
1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1438 if (cbuf) {
1439 MacroAssembler _masm(cbuf);
1440 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1441 #ifndef PRODUCT
1442 } else if (!do_size) {
1443 st->print("movdl %s, %s\t# spill",
1444 Matcher::regName[dst_first],
1445 Matcher::regName[src_first]);
1446 #endif
1447 }
1448 return
1449 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1450 ? 5
1451 : (4 + ((UseAVX>0)?1:0)); // REX
1452 }
1453 }
1454 } else if (src_first_rc == rc_float) {
1455 // xmm ->
1456 if (dst_first_rc == rc_stack) {
1457 // xmm -> mem
1458 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1459 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1460 // 64-bit
1461 int offset = ra_->reg2offset(dst_first);
1462 if (cbuf) {
1463 MacroAssembler _masm(cbuf);
1464 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1465 #ifndef PRODUCT
1466 } else if (!do_size) {
1467 st->print("movsd [rsp + #%d], %s\t# spill",
1468 offset,
1469 Matcher::regName[src_first]);
1470 #endif
1471 }
1472 return
1473 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1474 ((Matcher::_regEncode[src_first] >= 8)
1475 ? 6
1476 : (5 + ((UseAVX>0)?1:0))); // REX
1477 } else {
1478 // 32-bit
1479 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1480 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1481 int offset = ra_->reg2offset(dst_first);
1482 if (cbuf) {
1483 MacroAssembler _masm(cbuf);
1484 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1485 #ifndef PRODUCT
1486 } else if (!do_size) {
1487 st->print("movss [rsp + #%d], %s\t# spill",
1488 offset,
1489 Matcher::regName[src_first]);
1490 #endif
1491 }
1492 return
1493 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1494 ((Matcher::_regEncode[src_first] >=8)
1495 ? 6
1496 : (5 + ((UseAVX>0)?1:0))); // REX
1497 }
1498 } else if (dst_first_rc == rc_int) {
1499 // xmm -> gpr
1500 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1501 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1502 // 64-bit
1503 if (cbuf) {
1504 MacroAssembler _masm(cbuf);
1505 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1506 #ifndef PRODUCT
1507 } else if (!do_size) {
1508 st->print("movdq %s, %s\t# spill",
1509 Matcher::regName[dst_first],
1510 Matcher::regName[src_first]);
1511 #endif
1512 }
1513 return 5; // REX
1514 } else {
1515 // 32-bit
1516 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1517 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1518 if (cbuf) {
1519 MacroAssembler _masm(cbuf);
1520 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1521 #ifndef PRODUCT
1522 } else if (!do_size) {
1523 st->print("movdl %s, %s\t# spill",
1524 Matcher::regName[dst_first],
1525 Matcher::regName[src_first]);
1526 #endif
1527 }
1528 return
1529 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1530 ? 5
1531 : (4 + ((UseAVX>0)?1:0)); // REX
1532 }
1533 } else if (dst_first_rc == rc_float) {
1534 // xmm -> xmm
1535 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1536 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1537 // 64-bit
1538 if (cbuf) {
1539 MacroAssembler _masm(cbuf);
1540 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1541 #ifndef PRODUCT
1542 } else if (!do_size) {
1543 st->print("%s %s, %s\t# spill",
1544 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1545 Matcher::regName[dst_first],
1546 Matcher::regName[src_first]);
1547 #endif
1548 }
1549 return
1550 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1551 ? 5
1552 : (4 + ((UseAVX>0)?1:0)); // REX
1553 } else {
1554 // 32-bit
1555 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1556 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1557 if (cbuf) {
1558 MacroAssembler _masm(cbuf);
1559 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1560 #ifndef PRODUCT
1561 } else if (!do_size) {
1562 st->print("%s %s, %s\t# spill",
1563 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1564 Matcher::regName[dst_first],
1565 Matcher::regName[src_first]);
1566 #endif
1567 }
1568 return ((UseAVX>0) ? 5:
1569 ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)
1570 ? (UseXmmRegToRegMoveAll ? 4 : 5)
1571 : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX
1572 }
1573 }
1574 }
1575
1576 assert(0," foo ");
1577 Unimplemented();
1578
1579 return 0;
1580 }
1581
1582 #ifndef PRODUCT
1583 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1584 {
1585 implementation(NULL, ra_, false, st);
1586 }
1587 #endif
1588
1589 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1590 {
1591 implementation(&cbuf, ra_, false, NULL);
1592 }
1593
1594 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1595 {
1596 return implementation(NULL, ra_, true, NULL);
1597 }
1598
1599 //=============================================================================
1600 #ifndef PRODUCT
1601 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1602 {
1603 st->print("nop \t# %d bytes pad for loops and calls", _count);
1604 }
1605 #endif
1606
1607 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1608 {
1609 MacroAssembler _masm(&cbuf);
1610 __ nop(_count);
1611 }
1612
1613 uint MachNopNode::size(PhaseRegAlloc*) const
1614 {
1615 return _count;
1616 }
1617
1618
1619 //=============================================================================
1620 #ifndef PRODUCT
1621 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1622 {
1623 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1624 int reg = ra_->get_reg_first(this);
1625 st->print("leaq %s, [rsp + #%d]\t# box lock",
1626 Matcher::regName[reg], offset);
1627 }
1628 #endif
1629
1630 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1631 {
1632 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1633 int reg = ra_->get_encode(this);
1634 if (offset >= 0x80) {
1635 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1636 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1637 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1638 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1639 emit_d32(cbuf, offset);
1640 } else {
1641 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1642 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1643 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1644 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1645 emit_d8(cbuf, offset);
1646 }
1647 }
1648
1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1650 {
1651 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1652 return (offset < 0x80) ? 5 : 8; // REX
1653 }
1654
1655 //=============================================================================
1656
1657 // emit call stub, compiled java to interpreter
1658 void emit_java_to_interp(CodeBuffer& cbuf)
1659 {
1660 // Stub is fixed up when the corresponding call is converted from
1661 // calling compiled code to calling interpreted code.
1662 // movq rbx, 0
1663 // jmp -5 # to self
1664
1665 address mark = cbuf.insts_mark(); // get mark within main instrs section
1666
1667 // Note that the code buffer's insts_mark is always relative to insts.
1668 // That's why we must use the macroassembler to generate a stub.
1669 MacroAssembler _masm(&cbuf);
1670
1671 address base =
1672 __ start_a_stub(Compile::MAX_stubs_size);
1673 if (base == NULL) return; // CodeBuffer::expand failed
1674 // static stub relocation stores the instruction address of the call
1675 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1676 // static stub relocation also tags the methodOop in the code-stream.
1677 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1678 // This is recognized as unresolved by relocs/nativeinst/ic code
1679 __ jump(RuntimeAddress(__ pc()));
1680
1681 // Update current stubs pointer and restore insts_end.
1682 __ end_a_stub();
1683 }
1684
1685 // size of call stub, compiled java to interpretor
1686 uint size_java_to_interp()
1687 {
1688 return 15; // movq (1+1+8); jmp (1+4)
1689 }
1690
1691 // relocation entries for call stub, compiled java to interpretor
1692 uint reloc_java_to_interp()
1693 {
1694 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1695 }
1696
1697 //=============================================================================
1698 #ifndef PRODUCT
1699 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1700 {
1701 if (UseCompressedOops) {
1702 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1703 if (Universe::narrow_oop_shift() != 0) {
1704 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1705 }
1706 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1707 } else {
1708 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1709 "# Inline cache check");
1710 }
1711 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1712 st->print_cr("\tnop\t# nops to align entry point");
1713 }
1714 #endif
1715
1716 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1717 {
1718 MacroAssembler masm(&cbuf);
1719 uint insts_size = cbuf.insts_size();
1720 if (UseCompressedOops) {
1721 masm.load_klass(rscratch1, j_rarg0);
1722 masm.cmpptr(rax, rscratch1);
1723 } else {
1724 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1725 }
1726
1727 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1728
1729 /* WARNING these NOPs are critical so that verified entry point is properly
1730 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1731 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1732 if (OptoBreakpoint) {
1733 // Leave space for int3
1734 nops_cnt -= 1;
1735 }
1736 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1737 if (nops_cnt > 0)
1738 masm.nop(nops_cnt);
1739 }
1740
1741 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1742 {
1743 return MachNode::size(ra_); // too many variables; just compute it
1744 // the hard way
1745 }
1746
1747
1748 //=============================================================================
1749 uint size_exception_handler()
1750 {
1751 // NativeCall instruction size is the same as NativeJump.
1752 // Note that this value is also credited (in output.cpp) to
1753 // the size of the code section.
1754 return NativeJump::instruction_size;
1755 }
1756
1757 // Emit exception handler code.
1758 int emit_exception_handler(CodeBuffer& cbuf)
1759 {
1760
1761 // Note that the code buffer's insts_mark is always relative to insts.
1762 // That's why we must use the macroassembler to generate a handler.
1763 MacroAssembler _masm(&cbuf);
1764 address base =
1765 __ start_a_stub(size_exception_handler());
1766 if (base == NULL) return 0; // CodeBuffer::expand failed
1767 int offset = __ offset();
1768 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1769 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1770 __ end_a_stub();
1771 return offset;
1772 }
1773
1774 uint size_deopt_handler()
1775 {
1776 // three 5 byte instructions
1777 return 15;
1778 }
1779
1780 // Emit deopt handler code.
1781 int emit_deopt_handler(CodeBuffer& cbuf)
1782 {
1783
1784 // Note that the code buffer's insts_mark is always relative to insts.
1785 // That's why we must use the macroassembler to generate a handler.
1786 MacroAssembler _masm(&cbuf);
1787 address base =
1788 __ start_a_stub(size_deopt_handler());
1789 if (base == NULL) return 0; // CodeBuffer::expand failed
1790 int offset = __ offset();
1791 address the_pc = (address) __ pc();
1792 Label next;
1793 // push a "the_pc" on the stack without destroying any registers
1794 // as they all may be live.
1795
1796 // push address of "next"
1797 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1798 __ bind(next);
1799 // adjust it so it matches "the_pc"
1800 __ subptr(Address(rsp, 0), __ offset() - offset);
1801 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1803 __ end_a_stub();
1804 return offset;
1805 }
1806
1807
1808 const bool Matcher::match_rule_supported(int opcode) {
1809 if (!has_match_rule(opcode))
1810 return false;
1811
1812 return true; // Per default match rules are supported.
1813 }
1814
1815 int Matcher::regnum_to_fpu_offset(int regnum)
1816 {
1817 return regnum - 32; // The FP registers are in the second chunk
1818 }
1819
1820 // This is UltraSparc specific, true just means we have fast l2f conversion
1821 const bool Matcher::convL2FSupported(void) {
1822 return true;
1823 }
1824
1825 // Vector width in bytes
1826 const uint Matcher::vector_width_in_bytes(void) {
1827 return 8;
1828 }
1829
1830 // Vector ideal reg
1831 const uint Matcher::vector_ideal_reg(void) {
1832 return Op_RegD;
1833 }
1834
1835 // Is this branch offset short enough that a short branch can be used?
1836 //
1837 // NOTE: If the platform does not provide any short branch variants, then
1838 // this method should return false for offset 0.
1839 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1840 // The passed offset is relative to address of the branch.
1841 // On 86 a branch displacement is calculated relative to address
1842 // of a next instruction.
1843 offset -= br_size;
1844
1845 // the short version of jmpConUCF2 contains multiple branches,
1846 // making the reach slightly less
1847 if (rule == jmpConUCF2_rule)
1848 return (-126 <= offset && offset <= 125);
1849 return (-128 <= offset && offset <= 127);
1850 }
1851
1852 const bool Matcher::isSimpleConstant64(jlong value) {
1853 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1854 //return value == (int) value; // Cf. storeImmL and immL32.
1855
1856 // Probably always true, even if a temp register is required.
1857 return true;
1858 }
1859
1860 // The ecx parameter to rep stosq for the ClearArray node is in words.
1861 const bool Matcher::init_array_count_is_in_bytes = false;
1862
1863 // Threshold size for cleararray.
1864 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1865
1866 // No additional cost for CMOVL.
1867 const int Matcher::long_cmove_cost() { return 0; }
1868
1869 // No CMOVF/CMOVD with SSE2
1870 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1871
1872 // Should the Matcher clone shifts on addressing modes, expecting them
1873 // to be subsumed into complex addressing expressions or compute them
1874 // into registers? True for Intel but false for most RISCs
1875 const bool Matcher::clone_shift_expressions = true;
1876
1877 // Do we need to mask the count passed to shift instructions or does
1878 // the cpu only look at the lower 5/6 bits anyway?
1879 const bool Matcher::need_masked_shift_count = false;
1880
1881 bool Matcher::narrow_oop_use_complex_address() {
1882 assert(UseCompressedOops, "only for compressed oops code");
1883 return (LogMinObjAlignmentInBytes <= 3);
1884 }
1885
1886 // Is it better to copy float constants, or load them directly from
1887 // memory? Intel can load a float constant from a direct address,
1888 // requiring no extra registers. Most RISCs will have to materialize
1889 // an address into a register first, so they would do better to copy
1890 // the constant from stack.
1891 const bool Matcher::rematerialize_float_constants = true; // XXX
1892
1893 // If CPU can load and store mis-aligned doubles directly then no
1894 // fixup is needed. Else we split the double into 2 integer pieces
1895 // and move it piece-by-piece. Only happens when passing doubles into
1896 // C code as the Java calling convention forces doubles to be aligned.
1897 const bool Matcher::misaligned_doubles_ok = true;
1898
1899 // No-op on amd64
1900 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1901
1902 // Advertise here if the CPU requires explicit rounding operations to
1903 // implement the UseStrictFP mode.
1904 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1905
1906 // Are floats conerted to double when stored to stack during deoptimization?
1907 // On x64 it is stored without convertion so we can use normal access.
1908 bool Matcher::float_in_double() { return false; }
1909
1910 // Do ints take an entire long register or just half?
1911 const bool Matcher::int_in_long = true;
1912
1913 // Return whether or not this register is ever used as an argument.
1914 // This function is used on startup to build the trampoline stubs in
1915 // generateOptoStub. Registers not mentioned will be killed by the VM
1916 // call in the trampoline, and arguments in those registers not be
1917 // available to the callee.
1918 bool Matcher::can_be_java_arg(int reg)
1919 {
1920 return
1921 reg == RDI_num || reg == RDI_H_num ||
1922 reg == RSI_num || reg == RSI_H_num ||
1923 reg == RDX_num || reg == RDX_H_num ||
1924 reg == RCX_num || reg == RCX_H_num ||
1925 reg == R8_num || reg == R8_H_num ||
1926 reg == R9_num || reg == R9_H_num ||
1927 reg == R12_num || reg == R12_H_num ||
1928 reg == XMM0_num || reg == XMM0_H_num ||
1929 reg == XMM1_num || reg == XMM1_H_num ||
1930 reg == XMM2_num || reg == XMM2_H_num ||
1931 reg == XMM3_num || reg == XMM3_H_num ||
1932 reg == XMM4_num || reg == XMM4_H_num ||
1933 reg == XMM5_num || reg == XMM5_H_num ||
1934 reg == XMM6_num || reg == XMM6_H_num ||
1935 reg == XMM7_num || reg == XMM7_H_num;
1936 }
1937
1938 bool Matcher::is_spillable_arg(int reg)
1939 {
1940 return can_be_java_arg(reg);
1941 }
1942
1943 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1944 // In 64 bit mode a code which use multiply when
1945 // devisor is constant is faster than hardware
1946 // DIV instruction (it uses MulHiL).
1947 return false;
1948 }
1949
1950 // Register for DIVI projection of divmodI
1951 RegMask Matcher::divI_proj_mask() {
1952 return INT_RAX_REG_mask();
1953 }
1954
1955 // Register for MODI projection of divmodI
1956 RegMask Matcher::modI_proj_mask() {
1957 return INT_RDX_REG_mask();
1958 }
1959
1960 // Register for DIVL projection of divmodL
1961 RegMask Matcher::divL_proj_mask() {
1962 return LONG_RAX_REG_mask();
1963 }
1964
1965 // Register for MODL projection of divmodL
1966 RegMask Matcher::modL_proj_mask() {
1967 return LONG_RDX_REG_mask();
1968 }
1969
1970 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1971 return PTR_RBP_REG_mask();
1972 }
1973
1974 static Address build_address(int b, int i, int s, int d) {
1975 Register index = as_Register(i);
1976 Address::ScaleFactor scale = (Address::ScaleFactor)s;
1977 if (index == rsp) {
1978 index = noreg;
1979 scale = Address::no_scale;
1980 }
1981 Address addr(as_Register(b), index, scale, d);
1982 return addr;
1983 }
1984
1985 %}
1986
1987 //----------ENCODING BLOCK-----------------------------------------------------
1988 // This block specifies the encoding classes used by the compiler to
1989 // output byte streams. Encoding classes are parameterized macros
1990 // used by Machine Instruction Nodes in order to generate the bit
1991 // encoding of the instruction. Operands specify their base encoding
1992 // interface with the interface keyword. There are currently
1993 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1994 // COND_INTER. REG_INTER causes an operand to generate a function
1995 // which returns its register number when queried. CONST_INTER causes
1996 // an operand to generate a function which returns the value of the
1997 // constant when queried. MEMORY_INTER causes an operand to generate
1998 // four functions which return the Base Register, the Index Register,
1999 // the Scale Value, and the Offset Value of the operand when queried.
2000 // COND_INTER causes an operand to generate six functions which return
2001 // the encoding code (ie - encoding bits for the instruction)
2002 // associated with each basic boolean condition for a conditional
2003 // instruction.
2004 //
2005 // Instructions specify two basic values for encoding. Again, a
2006 // function is available to check if the constant displacement is an
2007 // oop. They use the ins_encode keyword to specify their encoding
2008 // classes (which must be a sequence of enc_class names, and their
2009 // parameters, specified in the encoding block), and they use the
2010 // opcode keyword to specify, in order, their primary, secondary, and
2011 // tertiary opcode. Only the opcode sections which a particular
2012 // instruction needs for encoding need to be specified.
2013 encode %{
2014 // Build emit functions for each basic byte or larger field in the
2015 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2016 // from C++ code in the enc_class source block. Emit functions will
2017 // live in the main source block for now. In future, we can
2018 // generalize this by adding a syntax that specifies the sizes of
2019 // fields in an order, so that the adlc can build the emit functions
2020 // automagically
2021
2022 // Emit primary opcode
2023 enc_class OpcP
2024 %{
2025 emit_opcode(cbuf, $primary);
2026 %}
2027
2028 // Emit secondary opcode
2029 enc_class OpcS
2030 %{
2031 emit_opcode(cbuf, $secondary);
2032 %}
2033
2034 // Emit tertiary opcode
2035 enc_class OpcT
2036 %{
2037 emit_opcode(cbuf, $tertiary);
2038 %}
2039
2040 // Emit opcode directly
2041 enc_class Opcode(immI d8)
2042 %{
2043 emit_opcode(cbuf, $d8$$constant);
2044 %}
2045
2046 // Emit size prefix
2047 enc_class SizePrefix
2048 %{
2049 emit_opcode(cbuf, 0x66);
2050 %}
2051
2052 enc_class reg(rRegI reg)
2053 %{
2054 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2055 %}
2056
2057 enc_class reg_reg(rRegI dst, rRegI src)
2058 %{
2059 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2060 %}
2061
2062 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2063 %{
2064 emit_opcode(cbuf, $opcode$$constant);
2065 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2066 %}
2067
2068 enc_class cdql_enc(no_rax_rdx_RegI div)
2069 %{
2070 // Full implementation of Java idiv and irem; checks for
2071 // special case as described in JVM spec., p.243 & p.271.
2072 //
2073 // normal case special case
2074 //
2075 // input : rax: dividend min_int
2076 // reg: divisor -1
2077 //
2078 // output: rax: quotient (= rax idiv reg) min_int
2079 // rdx: remainder (= rax irem reg) 0
2080 //
2081 // Code sequnce:
2082 //
2083 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2084 // 5: 75 07/08 jne e <normal>
2085 // 7: 33 d2 xor %edx,%edx
2086 // [div >= 8 -> offset + 1]
2087 // [REX_B]
2088 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2089 // c: 74 03/04 je 11 <done>
2090 // 000000000000000e <normal>:
2091 // e: 99 cltd
2092 // [div >= 8 -> offset + 1]
2093 // [REX_B]
2094 // f: f7 f9 idiv $div
2095 // 0000000000000011 <done>:
2096
2097 // cmp $0x80000000,%eax
2098 emit_opcode(cbuf, 0x3d);
2099 emit_d8(cbuf, 0x00);
2100 emit_d8(cbuf, 0x00);
2101 emit_d8(cbuf, 0x00);
2102 emit_d8(cbuf, 0x80);
2103
2104 // jne e <normal>
2105 emit_opcode(cbuf, 0x75);
2106 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2107
2108 // xor %edx,%edx
2109 emit_opcode(cbuf, 0x33);
2110 emit_d8(cbuf, 0xD2);
2111
2112 // cmp $0xffffffffffffffff,%ecx
2113 if ($div$$reg >= 8) {
2114 emit_opcode(cbuf, Assembler::REX_B);
2115 }
2116 emit_opcode(cbuf, 0x83);
2117 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2118 emit_d8(cbuf, 0xFF);
2119
2120 // je 11 <done>
2121 emit_opcode(cbuf, 0x74);
2122 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2123
2124 // <normal>
2125 // cltd
2126 emit_opcode(cbuf, 0x99);
2127
2128 // idivl (note: must be emitted by the user of this rule)
2129 // <done>
2130 %}
2131
2132 enc_class cdqq_enc(no_rax_rdx_RegL div)
2133 %{
2134 // Full implementation of Java ldiv and lrem; checks for
2135 // special case as described in JVM spec., p.243 & p.271.
2136 //
2137 // normal case special case
2138 //
2139 // input : rax: dividend min_long
2140 // reg: divisor -1
2141 //
2142 // output: rax: quotient (= rax idiv reg) min_long
2143 // rdx: remainder (= rax irem reg) 0
2144 //
2145 // Code sequnce:
2146 //
2147 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2148 // 7: 00 00 80
2149 // a: 48 39 d0 cmp %rdx,%rax
2150 // d: 75 08 jne 17 <normal>
2151 // f: 33 d2 xor %edx,%edx
2152 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2153 // 15: 74 05 je 1c <done>
2154 // 0000000000000017 <normal>:
2155 // 17: 48 99 cqto
2156 // 19: 48 f7 f9 idiv $div
2157 // 000000000000001c <done>:
2158
2159 // mov $0x8000000000000000,%rdx
2160 emit_opcode(cbuf, Assembler::REX_W);
2161 emit_opcode(cbuf, 0xBA);
2162 emit_d8(cbuf, 0x00);
2163 emit_d8(cbuf, 0x00);
2164 emit_d8(cbuf, 0x00);
2165 emit_d8(cbuf, 0x00);
2166 emit_d8(cbuf, 0x00);
2167 emit_d8(cbuf, 0x00);
2168 emit_d8(cbuf, 0x00);
2169 emit_d8(cbuf, 0x80);
2170
2171 // cmp %rdx,%rax
2172 emit_opcode(cbuf, Assembler::REX_W);
2173 emit_opcode(cbuf, 0x39);
2174 emit_d8(cbuf, 0xD0);
2175
2176 // jne 17 <normal>
2177 emit_opcode(cbuf, 0x75);
2178 emit_d8(cbuf, 0x08);
2179
2180 // xor %edx,%edx
2181 emit_opcode(cbuf, 0x33);
2182 emit_d8(cbuf, 0xD2);
2183
2184 // cmp $0xffffffffffffffff,$div
2185 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2186 emit_opcode(cbuf, 0x83);
2187 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2188 emit_d8(cbuf, 0xFF);
2189
2190 // je 1e <done>
2191 emit_opcode(cbuf, 0x74);
2192 emit_d8(cbuf, 0x05);
2193
2194 // <normal>
2195 // cqto
2196 emit_opcode(cbuf, Assembler::REX_W);
2197 emit_opcode(cbuf, 0x99);
2198
2199 // idivq (note: must be emitted by the user of this rule)
2200 // <done>
2201 %}
2202
2203 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2204 enc_class OpcSE(immI imm)
2205 %{
2206 // Emit primary opcode and set sign-extend bit
2207 // Check for 8-bit immediate, and set sign extend bit in opcode
2208 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2209 emit_opcode(cbuf, $primary | 0x02);
2210 } else {
2211 // 32-bit immediate
2212 emit_opcode(cbuf, $primary);
2213 }
2214 %}
2215
2216 enc_class OpcSErm(rRegI dst, immI imm)
2217 %{
2218 // OpcSEr/m
2219 int dstenc = $dst$$reg;
2220 if (dstenc >= 8) {
2221 emit_opcode(cbuf, Assembler::REX_B);
2222 dstenc -= 8;
2223 }
2224 // Emit primary opcode and set sign-extend bit
2225 // Check for 8-bit immediate, and set sign extend bit in opcode
2226 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2227 emit_opcode(cbuf, $primary | 0x02);
2228 } else {
2229 // 32-bit immediate
2230 emit_opcode(cbuf, $primary);
2231 }
2232 // Emit r/m byte with secondary opcode, after primary opcode.
2233 emit_rm(cbuf, 0x3, $secondary, dstenc);
2234 %}
2235
2236 enc_class OpcSErm_wide(rRegL dst, immI imm)
2237 %{
2238 // OpcSEr/m
2239 int dstenc = $dst$$reg;
2240 if (dstenc < 8) {
2241 emit_opcode(cbuf, Assembler::REX_W);
2242 } else {
2243 emit_opcode(cbuf, Assembler::REX_WB);
2244 dstenc -= 8;
2245 }
2246 // Emit primary opcode and set sign-extend bit
2247 // Check for 8-bit immediate, and set sign extend bit in opcode
2248 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2249 emit_opcode(cbuf, $primary | 0x02);
2250 } else {
2251 // 32-bit immediate
2252 emit_opcode(cbuf, $primary);
2253 }
2254 // Emit r/m byte with secondary opcode, after primary opcode.
2255 emit_rm(cbuf, 0x3, $secondary, dstenc);
2256 %}
2257
2258 enc_class Con8or32(immI imm)
2259 %{
2260 // Check for 8-bit immediate, and set sign extend bit in opcode
2261 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2262 $$$emit8$imm$$constant;
2263 } else {
2264 // 32-bit immediate
2265 $$$emit32$imm$$constant;
2266 }
2267 %}
2268
2269 enc_class opc2_reg(rRegI dst)
2270 %{
2271 // BSWAP
2272 emit_cc(cbuf, $secondary, $dst$$reg);
2273 %}
2274
2275 enc_class opc3_reg(rRegI dst)
2276 %{
2277 // BSWAP
2278 emit_cc(cbuf, $tertiary, $dst$$reg);
2279 %}
2280
2281 enc_class reg_opc(rRegI div)
2282 %{
2283 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2284 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2285 %}
2286
2287 enc_class enc_cmov(cmpOp cop)
2288 %{
2289 // CMOV
2290 $$$emit8$primary;
2291 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2292 %}
2293
2294 enc_class enc_PartialSubtypeCheck()
2295 %{
2296 Register Rrdi = as_Register(RDI_enc); // result register
2297 Register Rrax = as_Register(RAX_enc); // super class
2298 Register Rrcx = as_Register(RCX_enc); // killed
2299 Register Rrsi = as_Register(RSI_enc); // sub class
2300 Label miss;
2301 const bool set_cond_codes = true;
2302
2303 MacroAssembler _masm(&cbuf);
2304 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2305 NULL, &miss,
2306 /*set_cond_codes:*/ true);
2307 if ($primary) {
2308 __ xorptr(Rrdi, Rrdi);
2309 }
2310 __ bind(miss);
2311 %}
2312
2313 enc_class Java_To_Interpreter(method meth)
2314 %{
2315 // CALL Java_To_Interpreter
2316 // This is the instruction starting address for relocation info.
2317 cbuf.set_insts_mark();
2318 $$$emit8$primary;
2319 // CALL directly to the runtime
2320 emit_d32_reloc(cbuf,
2321 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2322 runtime_call_Relocation::spec(),
2323 RELOC_DISP32);
2324 %}
2325
2326 enc_class preserve_SP %{
2327 debug_only(int off0 = cbuf.insts_size());
2328 MacroAssembler _masm(&cbuf);
2329 // RBP is preserved across all calls, even compiled calls.
2330 // Use it to preserve RSP in places where the callee might change the SP.
2331 __ movptr(rbp_mh_SP_save, rsp);
2332 debug_only(int off1 = cbuf.insts_size());
2333 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
2334 %}
2335
2336 enc_class restore_SP %{
2337 MacroAssembler _masm(&cbuf);
2338 __ movptr(rsp, rbp_mh_SP_save);
2339 %}
2340
2341 enc_class Java_Static_Call(method meth)
2342 %{
2343 // JAVA STATIC CALL
2344 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2345 // determine who we intended to call.
2346 cbuf.set_insts_mark();
2347 $$$emit8$primary;
2348
2349 if (!_method) {
2350 emit_d32_reloc(cbuf,
2351 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2352 runtime_call_Relocation::spec(),
2353 RELOC_DISP32);
2354 } else if (_optimized_virtual) {
2355 emit_d32_reloc(cbuf,
2356 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2357 opt_virtual_call_Relocation::spec(),
2358 RELOC_DISP32);
2359 } else {
2360 emit_d32_reloc(cbuf,
2361 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2362 static_call_Relocation::spec(),
2363 RELOC_DISP32);
2364 }
2365 if (_method) {
2366 // Emit stub for static call
2367 emit_java_to_interp(cbuf);
2368 }
2369 %}
2370
2371 enc_class Java_Dynamic_Call(method meth)
2372 %{
2373 // JAVA DYNAMIC CALL
2374 // !!!!!
2375 // Generate "movq rax, -1", placeholder instruction to load oop-info
2376 // emit_call_dynamic_prologue( cbuf );
2377 cbuf.set_insts_mark();
2378
2379 // movq rax, -1
2380 emit_opcode(cbuf, Assembler::REX_W);
2381 emit_opcode(cbuf, 0xB8 | RAX_enc);
2382 emit_d64_reloc(cbuf,
2383 (int64_t) Universe::non_oop_word(),
2384 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2385 address virtual_call_oop_addr = cbuf.insts_mark();
2386 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2387 // who we intended to call.
2388 cbuf.set_insts_mark();
2389 $$$emit8$primary;
2390 emit_d32_reloc(cbuf,
2391 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2392 virtual_call_Relocation::spec(virtual_call_oop_addr),
2393 RELOC_DISP32);
2394 %}
2395
2396 enc_class Java_Compiled_Call(method meth)
2397 %{
2398 // JAVA COMPILED CALL
2399 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2400
2401 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2402 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2403
2404 // callq *disp(%rax)
2405 cbuf.set_insts_mark();
2406 $$$emit8$primary;
2407 if (disp < 0x80) {
2408 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2409 emit_d8(cbuf, disp); // Displacement
2410 } else {
2411 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2412 emit_d32(cbuf, disp); // Displacement
2413 }
2414 %}
2415
2416 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2417 %{
2418 // SAL, SAR, SHR
2419 int dstenc = $dst$$reg;
2420 if (dstenc >= 8) {
2421 emit_opcode(cbuf, Assembler::REX_B);
2422 dstenc -= 8;
2423 }
2424 $$$emit8$primary;
2425 emit_rm(cbuf, 0x3, $secondary, dstenc);
2426 $$$emit8$shift$$constant;
2427 %}
2428
2429 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2430 %{
2431 // SAL, SAR, SHR
2432 int dstenc = $dst$$reg;
2433 if (dstenc < 8) {
2434 emit_opcode(cbuf, Assembler::REX_W);
2435 } else {
2436 emit_opcode(cbuf, Assembler::REX_WB);
2437 dstenc -= 8;
2438 }
2439 $$$emit8$primary;
2440 emit_rm(cbuf, 0x3, $secondary, dstenc);
2441 $$$emit8$shift$$constant;
2442 %}
2443
2444 enc_class load_immI(rRegI dst, immI src)
2445 %{
2446 int dstenc = $dst$$reg;
2447 if (dstenc >= 8) {
2448 emit_opcode(cbuf, Assembler::REX_B);
2449 dstenc -= 8;
2450 }
2451 emit_opcode(cbuf, 0xB8 | dstenc);
2452 $$$emit32$src$$constant;
2453 %}
2454
2455 enc_class load_immL(rRegL dst, immL src)
2456 %{
2457 int dstenc = $dst$$reg;
2458 if (dstenc < 8) {
2459 emit_opcode(cbuf, Assembler::REX_W);
2460 } else {
2461 emit_opcode(cbuf, Assembler::REX_WB);
2462 dstenc -= 8;
2463 }
2464 emit_opcode(cbuf, 0xB8 | dstenc);
2465 emit_d64(cbuf, $src$$constant);
2466 %}
2467
2468 enc_class load_immUL32(rRegL dst, immUL32 src)
2469 %{
2470 // same as load_immI, but this time we care about zeroes in the high word
2471 int dstenc = $dst$$reg;
2472 if (dstenc >= 8) {
2473 emit_opcode(cbuf, Assembler::REX_B);
2474 dstenc -= 8;
2475 }
2476 emit_opcode(cbuf, 0xB8 | dstenc);
2477 $$$emit32$src$$constant;
2478 %}
2479
2480 enc_class load_immL32(rRegL dst, immL32 src)
2481 %{
2482 int dstenc = $dst$$reg;
2483 if (dstenc < 8) {
2484 emit_opcode(cbuf, Assembler::REX_W);
2485 } else {
2486 emit_opcode(cbuf, Assembler::REX_WB);
2487 dstenc -= 8;
2488 }
2489 emit_opcode(cbuf, 0xC7);
2490 emit_rm(cbuf, 0x03, 0x00, dstenc);
2491 $$$emit32$src$$constant;
2492 %}
2493
2494 enc_class load_immP31(rRegP dst, immP32 src)
2495 %{
2496 // same as load_immI, but this time we care about zeroes in the high word
2497 int dstenc = $dst$$reg;
2498 if (dstenc >= 8) {
2499 emit_opcode(cbuf, Assembler::REX_B);
2500 dstenc -= 8;
2501 }
2502 emit_opcode(cbuf, 0xB8 | dstenc);
2503 $$$emit32$src$$constant;
2504 %}
2505
2506 enc_class load_immP(rRegP dst, immP src)
2507 %{
2508 int dstenc = $dst$$reg;
2509 if (dstenc < 8) {
2510 emit_opcode(cbuf, Assembler::REX_W);
2511 } else {
2512 emit_opcode(cbuf, Assembler::REX_WB);
2513 dstenc -= 8;
2514 }
2515 emit_opcode(cbuf, 0xB8 | dstenc);
2516 // This next line should be generated from ADLC
2517 if ($src->constant_is_oop()) {
2518 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2519 } else {
2520 emit_d64(cbuf, $src$$constant);
2521 }
2522 %}
2523
2524 enc_class Con32(immI src)
2525 %{
2526 // Output immediate
2527 $$$emit32$src$$constant;
2528 %}
2529
2530 enc_class Con64(immL src)
2531 %{
2532 // Output immediate
2533 emit_d64($src$$constant);
2534 %}
2535
2536 enc_class Con32F_as_bits(immF src)
2537 %{
2538 // Output Float immediate bits
2539 jfloat jf = $src$$constant;
2540 jint jf_as_bits = jint_cast(jf);
2541 emit_d32(cbuf, jf_as_bits);
2542 %}
2543
2544 enc_class Con16(immI src)
2545 %{
2546 // Output immediate
2547 $$$emit16$src$$constant;
2548 %}
2549
2550 // How is this different from Con32??? XXX
2551 enc_class Con_d32(immI src)
2552 %{
2553 emit_d32(cbuf,$src$$constant);
2554 %}
2555
2556 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2557 // Output immediate memory reference
2558 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2559 emit_d32(cbuf, 0x00);
2560 %}
2561
2562 enc_class lock_prefix()
2563 %{
2564 if (os::is_MP()) {
2565 emit_opcode(cbuf, 0xF0); // lock
2566 }
2567 %}
2568
2569 enc_class REX_mem(memory mem)
2570 %{
2571 if ($mem$$base >= 8) {
2572 if ($mem$$index < 8) {
2573 emit_opcode(cbuf, Assembler::REX_B);
2574 } else {
2575 emit_opcode(cbuf, Assembler::REX_XB);
2576 }
2577 } else {
2578 if ($mem$$index >= 8) {
2579 emit_opcode(cbuf, Assembler::REX_X);
2580 }
2581 }
2582 %}
2583
2584 enc_class REX_mem_wide(memory mem)
2585 %{
2586 if ($mem$$base >= 8) {
2587 if ($mem$$index < 8) {
2588 emit_opcode(cbuf, Assembler::REX_WB);
2589 } else {
2590 emit_opcode(cbuf, Assembler::REX_WXB);
2591 }
2592 } else {
2593 if ($mem$$index < 8) {
2594 emit_opcode(cbuf, Assembler::REX_W);
2595 } else {
2596 emit_opcode(cbuf, Assembler::REX_WX);
2597 }
2598 }
2599 %}
2600
2601 // for byte regs
2602 enc_class REX_breg(rRegI reg)
2603 %{
2604 if ($reg$$reg >= 4) {
2605 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2606 }
2607 %}
2608
2609 // for byte regs
2610 enc_class REX_reg_breg(rRegI dst, rRegI src)
2611 %{
2612 if ($dst$$reg < 8) {
2613 if ($src$$reg >= 4) {
2614 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2615 }
2616 } else {
2617 if ($src$$reg < 8) {
2618 emit_opcode(cbuf, Assembler::REX_R);
2619 } else {
2620 emit_opcode(cbuf, Assembler::REX_RB);
2621 }
2622 }
2623 %}
2624
2625 // for byte regs
2626 enc_class REX_breg_mem(rRegI reg, memory mem)
2627 %{
2628 if ($reg$$reg < 8) {
2629 if ($mem$$base < 8) {
2630 if ($mem$$index >= 8) {
2631 emit_opcode(cbuf, Assembler::REX_X);
2632 } else if ($reg$$reg >= 4) {
2633 emit_opcode(cbuf, Assembler::REX);
2634 }
2635 } else {
2636 if ($mem$$index < 8) {
2637 emit_opcode(cbuf, Assembler::REX_B);
2638 } else {
2639 emit_opcode(cbuf, Assembler::REX_XB);
2640 }
2641 }
2642 } else {
2643 if ($mem$$base < 8) {
2644 if ($mem$$index < 8) {
2645 emit_opcode(cbuf, Assembler::REX_R);
2646 } else {
2647 emit_opcode(cbuf, Assembler::REX_RX);
2648 }
2649 } else {
2650 if ($mem$$index < 8) {
2651 emit_opcode(cbuf, Assembler::REX_RB);
2652 } else {
2653 emit_opcode(cbuf, Assembler::REX_RXB);
2654 }
2655 }
2656 }
2657 %}
2658
2659 enc_class REX_reg(rRegI reg)
2660 %{
2661 if ($reg$$reg >= 8) {
2662 emit_opcode(cbuf, Assembler::REX_B);
2663 }
2664 %}
2665
2666 enc_class REX_reg_wide(rRegI reg)
2667 %{
2668 if ($reg$$reg < 8) {
2669 emit_opcode(cbuf, Assembler::REX_W);
2670 } else {
2671 emit_opcode(cbuf, Assembler::REX_WB);
2672 }
2673 %}
2674
2675 enc_class REX_reg_reg(rRegI dst, rRegI src)
2676 %{
2677 if ($dst$$reg < 8) {
2678 if ($src$$reg >= 8) {
2679 emit_opcode(cbuf, Assembler::REX_B);
2680 }
2681 } else {
2682 if ($src$$reg < 8) {
2683 emit_opcode(cbuf, Assembler::REX_R);
2684 } else {
2685 emit_opcode(cbuf, Assembler::REX_RB);
2686 }
2687 }
2688 %}
2689
2690 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2691 %{
2692 if ($dst$$reg < 8) {
2693 if ($src$$reg < 8) {
2694 emit_opcode(cbuf, Assembler::REX_W);
2695 } else {
2696 emit_opcode(cbuf, Assembler::REX_WB);
2697 }
2698 } else {
2699 if ($src$$reg < 8) {
2700 emit_opcode(cbuf, Assembler::REX_WR);
2701 } else {
2702 emit_opcode(cbuf, Assembler::REX_WRB);
2703 }
2704 }
2705 %}
2706
2707 enc_class REX_reg_mem(rRegI reg, memory mem)
2708 %{
2709 if ($reg$$reg < 8) {
2710 if ($mem$$base < 8) {
2711 if ($mem$$index >= 8) {
2712 emit_opcode(cbuf, Assembler::REX_X);
2713 }
2714 } else {
2715 if ($mem$$index < 8) {
2716 emit_opcode(cbuf, Assembler::REX_B);
2717 } else {
2718 emit_opcode(cbuf, Assembler::REX_XB);
2719 }
2720 }
2721 } else {
2722 if ($mem$$base < 8) {
2723 if ($mem$$index < 8) {
2724 emit_opcode(cbuf, Assembler::REX_R);
2725 } else {
2726 emit_opcode(cbuf, Assembler::REX_RX);
2727 }
2728 } else {
2729 if ($mem$$index < 8) {
2730 emit_opcode(cbuf, Assembler::REX_RB);
2731 } else {
2732 emit_opcode(cbuf, Assembler::REX_RXB);
2733 }
2734 }
2735 }
2736 %}
2737
2738 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2739 %{
2740 if ($reg$$reg < 8) {
2741 if ($mem$$base < 8) {
2742 if ($mem$$index < 8) {
2743 emit_opcode(cbuf, Assembler::REX_W);
2744 } else {
2745 emit_opcode(cbuf, Assembler::REX_WX);
2746 }
2747 } else {
2748 if ($mem$$index < 8) {
2749 emit_opcode(cbuf, Assembler::REX_WB);
2750 } else {
2751 emit_opcode(cbuf, Assembler::REX_WXB);
2752 }
2753 }
2754 } else {
2755 if ($mem$$base < 8) {
2756 if ($mem$$index < 8) {
2757 emit_opcode(cbuf, Assembler::REX_WR);
2758 } else {
2759 emit_opcode(cbuf, Assembler::REX_WRX);
2760 }
2761 } else {
2762 if ($mem$$index < 8) {
2763 emit_opcode(cbuf, Assembler::REX_WRB);
2764 } else {
2765 emit_opcode(cbuf, Assembler::REX_WRXB);
2766 }
2767 }
2768 }
2769 %}
2770
2771 enc_class reg_mem(rRegI ereg, memory mem)
2772 %{
2773 // High registers handle in encode_RegMem
2774 int reg = $ereg$$reg;
2775 int base = $mem$$base;
2776 int index = $mem$$index;
2777 int scale = $mem$$scale;
2778 int disp = $mem$$disp;
2779 bool disp_is_oop = $mem->disp_is_oop();
2780
2781 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
2782 %}
2783
2784 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2785 %{
2786 int rm_byte_opcode = $rm_opcode$$constant;
2787
2788 // High registers handle in encode_RegMem
2789 int base = $mem$$base;
2790 int index = $mem$$index;
2791 int scale = $mem$$scale;
2792 int displace = $mem$$disp;
2793
2794 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
2795 // working with static
2796 // globals
2797 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2798 disp_is_oop);
2799 %}
2800
2801 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2802 %{
2803 int reg_encoding = $dst$$reg;
2804 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2805 int index = 0x04; // 0x04 indicates no index
2806 int scale = 0x00; // 0x00 indicates no scale
2807 int displace = $src1$$constant; // 0x00 indicates no displacement
2808 bool disp_is_oop = false;
2809 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2810 disp_is_oop);
2811 %}
2812
2813 enc_class neg_reg(rRegI dst)
2814 %{
2815 int dstenc = $dst$$reg;
2816 if (dstenc >= 8) {
2817 emit_opcode(cbuf, Assembler::REX_B);
2818 dstenc -= 8;
2819 }
2820 // NEG $dst
2821 emit_opcode(cbuf, 0xF7);
2822 emit_rm(cbuf, 0x3, 0x03, dstenc);
2823 %}
2824
2825 enc_class neg_reg_wide(rRegI dst)
2826 %{
2827 int dstenc = $dst$$reg;
2828 if (dstenc < 8) {
2829 emit_opcode(cbuf, Assembler::REX_W);
2830 } else {
2831 emit_opcode(cbuf, Assembler::REX_WB);
2832 dstenc -= 8;
2833 }
2834 // NEG $dst
2835 emit_opcode(cbuf, 0xF7);
2836 emit_rm(cbuf, 0x3, 0x03, dstenc);
2837 %}
2838
2839 enc_class setLT_reg(rRegI dst)
2840 %{
2841 int dstenc = $dst$$reg;
2842 if (dstenc >= 8) {
2843 emit_opcode(cbuf, Assembler::REX_B);
2844 dstenc -= 8;
2845 } else if (dstenc >= 4) {
2846 emit_opcode(cbuf, Assembler::REX);
2847 }
2848 // SETLT $dst
2849 emit_opcode(cbuf, 0x0F);
2850 emit_opcode(cbuf, 0x9C);
2851 emit_rm(cbuf, 0x3, 0x0, dstenc);
2852 %}
2853
2854 enc_class setNZ_reg(rRegI dst)
2855 %{
2856 int dstenc = $dst$$reg;
2857 if (dstenc >= 8) {
2858 emit_opcode(cbuf, Assembler::REX_B);
2859 dstenc -= 8;
2860 } else if (dstenc >= 4) {
2861 emit_opcode(cbuf, Assembler::REX);
2862 }
2863 // SETNZ $dst
2864 emit_opcode(cbuf, 0x0F);
2865 emit_opcode(cbuf, 0x95);
2866 emit_rm(cbuf, 0x3, 0x0, dstenc);
2867 %}
2868
2869
2870 // Compare the lonogs and set -1, 0, or 1 into dst
2871 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2872 %{
2873 int src1enc = $src1$$reg;
2874 int src2enc = $src2$$reg;
2875 int dstenc = $dst$$reg;
2876
2877 // cmpq $src1, $src2
2878 if (src1enc < 8) {
2879 if (src2enc < 8) {
2880 emit_opcode(cbuf, Assembler::REX_W);
2881 } else {
2882 emit_opcode(cbuf, Assembler::REX_WB);
2883 }
2884 } else {
2885 if (src2enc < 8) {
2886 emit_opcode(cbuf, Assembler::REX_WR);
2887 } else {
2888 emit_opcode(cbuf, Assembler::REX_WRB);
2889 }
2890 }
2891 emit_opcode(cbuf, 0x3B);
2892 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2893
2894 // movl $dst, -1
2895 if (dstenc >= 8) {
2896 emit_opcode(cbuf, Assembler::REX_B);
2897 }
2898 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2899 emit_d32(cbuf, -1);
2900
2901 // jl,s done
2902 emit_opcode(cbuf, 0x7C);
2903 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2904
2905 // setne $dst
2906 if (dstenc >= 4) {
2907 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2908 }
2909 emit_opcode(cbuf, 0x0F);
2910 emit_opcode(cbuf, 0x95);
2911 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2912
2913 // movzbl $dst, $dst
2914 if (dstenc >= 4) {
2915 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2916 }
2917 emit_opcode(cbuf, 0x0F);
2918 emit_opcode(cbuf, 0xB6);
2919 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2920 %}
2921
2922 enc_class Push_ResultXD(regD dst) %{
2923 MacroAssembler _masm(&cbuf);
2924 __ fstp_d(Address(rsp, 0));
2925 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2926 __ addptr(rsp, 8);
2927 %}
2928
2929 enc_class Push_SrcXD(regD src) %{
2930 MacroAssembler _masm(&cbuf);
2931 __ subptr(rsp, 8);
2932 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2933 __ fld_d(Address(rsp, 0));
2934 %}
2935
2936
2937 // obj: object to lock
2938 // box: box address (header location) -- killed
2939 // tmp: rax -- killed
2940 // scr: rbx -- killed
2941 //
2942 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2943 // from i486.ad. See that file for comments.
2944 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2945 // use the shorter encoding. (Movl clears the high-order 32-bits).
2946
2947
2948 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2949 %{
2950 Register objReg = as_Register((int)$obj$$reg);
2951 Register boxReg = as_Register((int)$box$$reg);
2952 Register tmpReg = as_Register($tmp$$reg);
2953 Register scrReg = as_Register($scr$$reg);
2954 MacroAssembler masm(&cbuf);
2955
2956 // Verify uniqueness of register assignments -- necessary but not sufficient
2957 assert (objReg != boxReg && objReg != tmpReg &&
2958 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2959
2960 if (_counters != NULL) {
2961 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2962 }
2963 if (EmitSync & 1) {
2964 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2965 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2966 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2967 } else
2968 if (EmitSync & 2) {
2969 Label DONE_LABEL;
2970 if (UseBiasedLocking) {
2971 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2972 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2973 }
2974 // QQQ was movl...
2975 masm.movptr(tmpReg, 0x1);
2976 masm.orptr(tmpReg, Address(objReg, 0));
2977 masm.movptr(Address(boxReg, 0), tmpReg);
2978 if (os::is_MP()) {
2979 masm.lock();
2980 }
2981 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2982 masm.jcc(Assembler::equal, DONE_LABEL);
2983
2984 // Recursive locking
2985 masm.subptr(tmpReg, rsp);
2986 masm.andptr(tmpReg, 7 - os::vm_page_size());
2987 masm.movptr(Address(boxReg, 0), tmpReg);
2988
2989 masm.bind(DONE_LABEL);
2990 masm.nop(); // avoid branch to branch
2991 } else {
2992 Label DONE_LABEL, IsInflated, Egress;
2993
2994 masm.movptr(tmpReg, Address(objReg, 0)) ;
2995 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2996 masm.jcc (Assembler::notZero, IsInflated) ;
2997
2998 // it's stack-locked, biased or neutral
2999 // TODO: optimize markword triage order to reduce the number of
3000 // conditional branches in the most common cases.
3001 // Beware -- there's a subtle invariant that fetch of the markword
3002 // at [FETCH], below, will never observe a biased encoding (*101b).
3003 // If this invariant is not held we'll suffer exclusion (safety) failure.
3004
3005 if (UseBiasedLocking && !UseOptoBiasInlining) {
3006 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3007 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3008 }
3009
3010 // was q will it destroy high?
3011 masm.orl (tmpReg, 1) ;
3012 masm.movptr(Address(boxReg, 0), tmpReg) ;
3013 if (os::is_MP()) { masm.lock(); }
3014 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3015 if (_counters != NULL) {
3016 masm.cond_inc32(Assembler::equal,
3017 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3018 }
3019 masm.jcc (Assembler::equal, DONE_LABEL);
3020
3021 // Recursive locking
3022 masm.subptr(tmpReg, rsp);
3023 masm.andptr(tmpReg, 7 - os::vm_page_size());
3024 masm.movptr(Address(boxReg, 0), tmpReg);
3025 if (_counters != NULL) {
3026 masm.cond_inc32(Assembler::equal,
3027 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3028 }
3029 masm.jmp (DONE_LABEL) ;
3030
3031 masm.bind (IsInflated) ;
3032 // It's inflated
3033
3034 // TODO: someday avoid the ST-before-CAS penalty by
3035 // relocating (deferring) the following ST.
3036 // We should also think about trying a CAS without having
3037 // fetched _owner. If the CAS is successful we may
3038 // avoid an RTO->RTS upgrade on the $line.
3039 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3040 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3041
3042 masm.mov (boxReg, tmpReg) ;
3043 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3044 masm.testptr(tmpReg, tmpReg) ;
3045 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3046
3047 // It's inflated and appears unlocked
3048 if (os::is_MP()) { masm.lock(); }
3049 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3050 // Intentional fall-through into DONE_LABEL ...
3051
3052 masm.bind (DONE_LABEL) ;
3053 masm.nop () ; // avoid jmp to jmp
3054 }
3055 %}
3056
3057 // obj: object to unlock
3058 // box: box address (displaced header location), killed
3059 // RBX: killed tmp; cannot be obj nor box
3060 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3061 %{
3062
3063 Register objReg = as_Register($obj$$reg);
3064 Register boxReg = as_Register($box$$reg);
3065 Register tmpReg = as_Register($tmp$$reg);
3066 MacroAssembler masm(&cbuf);
3067
3068 if (EmitSync & 4) {
3069 masm.cmpptr(rsp, 0) ;
3070 } else
3071 if (EmitSync & 8) {
3072 Label DONE_LABEL;
3073 if (UseBiasedLocking) {
3074 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3075 }
3076
3077 // Check whether the displaced header is 0
3078 //(=> recursive unlock)
3079 masm.movptr(tmpReg, Address(boxReg, 0));
3080 masm.testptr(tmpReg, tmpReg);
3081 masm.jcc(Assembler::zero, DONE_LABEL);
3082
3083 // If not recursive lock, reset the header to displaced header
3084 if (os::is_MP()) {
3085 masm.lock();
3086 }
3087 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3088 masm.bind(DONE_LABEL);
3089 masm.nop(); // avoid branch to branch
3090 } else {
3091 Label DONE_LABEL, Stacked, CheckSucc ;
3092
3093 if (UseBiasedLocking && !UseOptoBiasInlining) {
3094 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3095 }
3096
3097 masm.movptr(tmpReg, Address(objReg, 0)) ;
3098 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
3099 masm.jcc (Assembler::zero, DONE_LABEL) ;
3100 masm.testl (tmpReg, 0x02) ;
3101 masm.jcc (Assembler::zero, Stacked) ;
3102
3103 // It's inflated
3104 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3105 masm.xorptr(boxReg, r15_thread) ;
3106 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3107 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3108 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3109 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3110 masm.jcc (Assembler::notZero, CheckSucc) ;
3111 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3112 masm.jmp (DONE_LABEL) ;
3113
3114 if ((EmitSync & 65536) == 0) {
3115 Label LSuccess, LGoSlowPath ;
3116 masm.bind (CheckSucc) ;
3117 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3118 masm.jcc (Assembler::zero, LGoSlowPath) ;
3119
3120 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3121 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3122 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3123 // are all faster when the write buffer is populated.
3124 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3125 if (os::is_MP()) {
3126 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3127 }
3128 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3129 masm.jcc (Assembler::notZero, LSuccess) ;
3130
3131 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3132 if (os::is_MP()) { masm.lock(); }
3133 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3134 masm.jcc (Assembler::notEqual, LSuccess) ;
3135 // Intentional fall-through into slow-path
3136
3137 masm.bind (LGoSlowPath) ;
3138 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3139 masm.jmp (DONE_LABEL) ;
3140
3141 masm.bind (LSuccess) ;
3142 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3143 masm.jmp (DONE_LABEL) ;
3144 }
3145
3146 masm.bind (Stacked) ;
3147 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3148 if (os::is_MP()) { masm.lock(); }
3149 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3150
3151 if (EmitSync & 65536) {
3152 masm.bind (CheckSucc) ;
3153 }
3154 masm.bind(DONE_LABEL);
3155 if (EmitSync & 32768) {
3156 masm.nop(); // avoid branch to branch
3157 }
3158 }
3159 %}
3160
3161
3162 enc_class enc_rethrow()
3163 %{
3164 cbuf.set_insts_mark();
3165 emit_opcode(cbuf, 0xE9); // jmp entry
3166 emit_d32_reloc(cbuf,
3167 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
3168 runtime_call_Relocation::spec(),
3169 RELOC_DISP32);
3170 %}
3171
3172 %}
3173
3174
3175
3176 //----------FRAME--------------------------------------------------------------
3177 // Definition of frame structure and management information.
3178 //
3179 // S T A C K L A Y O U T Allocators stack-slot number
3180 // | (to get allocators register number
3181 // G Owned by | | v add OptoReg::stack0())
3182 // r CALLER | |
3183 // o | +--------+ pad to even-align allocators stack-slot
3184 // w V | pad0 | numbers; owned by CALLER
3185 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3186 // h ^ | in | 5
3187 // | | args | 4 Holes in incoming args owned by SELF
3188 // | | | | 3
3189 // | | +--------+
3190 // V | | old out| Empty on Intel, window on Sparc
3191 // | old |preserve| Must be even aligned.
3192 // | SP-+--------+----> Matcher::_old_SP, even aligned
3193 // | | in | 3 area for Intel ret address
3194 // Owned by |preserve| Empty on Sparc.
3195 // SELF +--------+
3196 // | | pad2 | 2 pad to align old SP
3197 // | +--------+ 1
3198 // | | locks | 0
3199 // | +--------+----> OptoReg::stack0(), even aligned
3200 // | | pad1 | 11 pad to align new SP
3201 // | +--------+
3202 // | | | 10
3203 // | | spills | 9 spills
3204 // V | | 8 (pad0 slot for callee)
3205 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3206 // ^ | out | 7
3207 // | | args | 6 Holes in outgoing args owned by CALLEE
3208 // Owned by +--------+
3209 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3210 // | new |preserve| Must be even-aligned.
3211 // | SP-+--------+----> Matcher::_new_SP, even aligned
3212 // | | |
3213 //
3214 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3215 // known from SELF's arguments and the Java calling convention.
3216 // Region 6-7 is determined per call site.
3217 // Note 2: If the calling convention leaves holes in the incoming argument
3218 // area, those holes are owned by SELF. Holes in the outgoing area
3219 // are owned by the CALLEE. Holes should not be nessecary in the
3220 // incoming area, as the Java calling convention is completely under
3221 // the control of the AD file. Doubles can be sorted and packed to
3222 // avoid holes. Holes in the outgoing arguments may be nessecary for
3223 // varargs C calling conventions.
3224 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3225 // even aligned with pad0 as needed.
3226 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3227 // region 6-11 is even aligned; it may be padded out more so that
3228 // the region from SP to FP meets the minimum stack alignment.
3229 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3230 // alignment. Region 11, pad1, may be dynamically extended so that
3231 // SP meets the minimum alignment.
3232
3233 frame
3234 %{
3235 // What direction does stack grow in (assumed to be same for C & Java)
3236 stack_direction(TOWARDS_LOW);
3237
3238 // These three registers define part of the calling convention
3239 // between compiled code and the interpreter.
3240 inline_cache_reg(RAX); // Inline Cache Register
3241 interpreter_method_oop_reg(RBX); // Method Oop Register when
3242 // calling interpreter
3243
3244 // Optional: name the operand used by cisc-spilling to access
3245 // [stack_pointer + offset]
3246 cisc_spilling_operand_name(indOffset32);
3247
3248 // Number of stack slots consumed by locking an object
3249 sync_stack_slots(2);
3250
3251 // Compiled code's Frame Pointer
3252 frame_pointer(RSP);
3253
3254 // Interpreter stores its frame pointer in a register which is
3255 // stored to the stack by I2CAdaptors.
3256 // I2CAdaptors convert from interpreted java to compiled java.
3257 interpreter_frame_pointer(RBP);
3258
3259 // Stack alignment requirement
3260 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3261
3262 // Number of stack slots between incoming argument block and the start of
3263 // a new frame. The PROLOG must add this many slots to the stack. The
3264 // EPILOG must remove this many slots. amd64 needs two slots for
3265 // return address.
3266 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
3267
3268 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3269 // for calls to C. Supports the var-args backing area for register parms.
3270 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3271
3272 // The after-PROLOG location of the return address. Location of
3273 // return address specifies a type (REG or STACK) and a number
3274 // representing the register number (i.e. - use a register name) or
3275 // stack slot.
3276 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3277 // Otherwise, it is above the locks and verification slot and alignment word
3278 return_addr(STACK - 2 +
3279 round_to(2 + 2 * VerifyStackAtCalls +
3280 Compile::current()->fixed_slots(),
3281 WordsPerLong * 2));
3282
3283 // Body of function which returns an integer array locating
3284 // arguments either in registers or in stack slots. Passed an array
3285 // of ideal registers called "sig" and a "length" count. Stack-slot
3286 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3287 // arguments for a CALLEE. Incoming stack arguments are
3288 // automatically biased by the preserve_stack_slots field above.
3289
3290 calling_convention
3291 %{
3292 // No difference between ingoing/outgoing just pass false
3293 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3294 %}
3295
3296 c_calling_convention
3297 %{
3298 // This is obviously always outgoing
3299 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3300 %}
3301
3302 // Location of compiled Java return values. Same as C for now.
3303 return_value
3304 %{
3305 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
3306 "only return normal values");
3307
3308 static const int lo[Op_RegL + 1] = {
3309 0,
3310 0,
3311 RAX_num, // Op_RegN
3312 RAX_num, // Op_RegI
3313 RAX_num, // Op_RegP
3314 XMM0_num, // Op_RegF
3315 XMM0_num, // Op_RegD
3316 RAX_num // Op_RegL
3317 };
3318 static const int hi[Op_RegL + 1] = {
3319 0,
3320 0,
3321 OptoReg::Bad, // Op_RegN
3322 OptoReg::Bad, // Op_RegI
3323 RAX_H_num, // Op_RegP
3324 OptoReg::Bad, // Op_RegF
3325 XMM0_H_num, // Op_RegD
3326 RAX_H_num // Op_RegL
3327 };
3328 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
3329 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3330 %}
3331 %}
3332
3333 //----------ATTRIBUTES---------------------------------------------------------
3334 //----------Operand Attributes-------------------------------------------------
3335 op_attrib op_cost(0); // Required cost attribute
3336
3337 //----------Instruction Attributes---------------------------------------------
3338 ins_attrib ins_cost(100); // Required cost attribute
3339 ins_attrib ins_size(8); // Required size attribute (in bits)
3340 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3341 // a non-matching short branch variant
3342 // of some long branch?
3343 ins_attrib ins_alignment(1); // Required alignment attribute (must
3344 // be a power of 2) specifies the
3345 // alignment that some part of the
3346 // instruction (not necessarily the
3347 // start) requires. If > 1, a
3348 // compute_padding() function must be
3349 // provided for the instruction
3350
3351 //----------OPERANDS-----------------------------------------------------------
3352 // Operand definitions must precede instruction definitions for correct parsing
3353 // in the ADLC because operands constitute user defined types which are used in
3354 // instruction definitions.
3355
3356 //----------Simple Operands----------------------------------------------------
3357 // Immediate Operands
3358 // Integer Immediate
3359 operand immI()
3360 %{
3361 match(ConI);
3362
3363 op_cost(10);
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3367
3368 // Constant for test vs zero
3369 operand immI0()
3370 %{
3371 predicate(n->get_int() == 0);
3372 match(ConI);
3373
3374 op_cost(0);
3375 format %{ %}
3376 interface(CONST_INTER);
3377 %}
3378
3379 // Constant for increment
3380 operand immI1()
3381 %{
3382 predicate(n->get_int() == 1);
3383 match(ConI);
3384
3385 op_cost(0);
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 // Constant for decrement
3391 operand immI_M1()
3392 %{
3393 predicate(n->get_int() == -1);
3394 match(ConI);
3395
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Valid scale values for addressing modes
3402 operand immI2()
3403 %{
3404 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3405 match(ConI);
3406
3407 format %{ %}
3408 interface(CONST_INTER);
3409 %}
3410
3411 operand immI8()
3412 %{
3413 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3414 match(ConI);
3415
3416 op_cost(5);
3417 format %{ %}
3418 interface(CONST_INTER);
3419 %}
3420
3421 operand immI16()
3422 %{
3423 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3424 match(ConI);
3425
3426 op_cost(10);
3427 format %{ %}
3428 interface(CONST_INTER);
3429 %}
3430
3431 // Constant for long shifts
3432 operand immI_32()
3433 %{
3434 predicate( n->get_int() == 32 );
3435 match(ConI);
3436
3437 op_cost(0);
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3441
3442 // Constant for long shifts
3443 operand immI_64()
3444 %{
3445 predicate( n->get_int() == 64 );
3446 match(ConI);
3447
3448 op_cost(0);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3452
3453 // Pointer Immediate
3454 operand immP()
3455 %{
3456 match(ConP);
3457
3458 op_cost(10);
3459 format %{ %}
3460 interface(CONST_INTER);
3461 %}
3462
3463 // NULL Pointer Immediate
3464 operand immP0()
3465 %{
3466 predicate(n->get_ptr() == 0);
3467 match(ConP);
3468
3469 op_cost(5);
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 operand immP_poll() %{
3475 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3476 match(ConP);
3477
3478 // formats are generated automatically for constants and base registers
3479 format %{ %}
3480 interface(CONST_INTER);
3481 %}
3482
3483 // Pointer Immediate
3484 operand immN() %{
3485 match(ConN);
3486
3487 op_cost(10);
3488 format %{ %}
3489 interface(CONST_INTER);
3490 %}
3491
3492 // NULL Pointer Immediate
3493 operand immN0() %{
3494 predicate(n->get_narrowcon() == 0);
3495 match(ConN);
3496
3497 op_cost(5);
3498 format %{ %}
3499 interface(CONST_INTER);
3500 %}
3501
3502 operand immP31()
3503 %{
3504 predicate(!n->as_Type()->type()->isa_oopptr()
3505 && (n->get_ptr() >> 31) == 0);
3506 match(ConP);
3507
3508 op_cost(5);
3509 format %{ %}
3510 interface(CONST_INTER);
3511 %}
3512
3513
3514 // Long Immediate
3515 operand immL()
3516 %{
3517 match(ConL);
3518
3519 op_cost(20);
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3523
3524 // Long Immediate 8-bit
3525 operand immL8()
3526 %{
3527 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3528 match(ConL);
3529
3530 op_cost(5);
3531 format %{ %}
3532 interface(CONST_INTER);
3533 %}
3534
3535 // Long Immediate 32-bit unsigned
3536 operand immUL32()
3537 %{
3538 predicate(n->get_long() == (unsigned int) (n->get_long()));
3539 match(ConL);
3540
3541 op_cost(10);
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3545
3546 // Long Immediate 32-bit signed
3547 operand immL32()
3548 %{
3549 predicate(n->get_long() == (int) (n->get_long()));
3550 match(ConL);
3551
3552 op_cost(15);
3553 format %{ %}
3554 interface(CONST_INTER);
3555 %}
3556
3557 // Long Immediate zero
3558 operand immL0()
3559 %{
3560 predicate(n->get_long() == 0L);
3561 match(ConL);
3562
3563 op_cost(10);
3564 format %{ %}
3565 interface(CONST_INTER);
3566 %}
3567
3568 // Constant for increment
3569 operand immL1()
3570 %{
3571 predicate(n->get_long() == 1);
3572 match(ConL);
3573
3574 format %{ %}
3575 interface(CONST_INTER);
3576 %}
3577
3578 // Constant for decrement
3579 operand immL_M1()
3580 %{
3581 predicate(n->get_long() == -1);
3582 match(ConL);
3583
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3587
3588 // Long Immediate: the value 10
3589 operand immL10()
3590 %{
3591 predicate(n->get_long() == 10);
3592 match(ConL);
3593
3594 format %{ %}
3595 interface(CONST_INTER);
3596 %}
3597
3598 // Long immediate from 0 to 127.
3599 // Used for a shorter form of long mul by 10.
3600 operand immL_127()
3601 %{
3602 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3603 match(ConL);
3604
3605 op_cost(10);
3606 format %{ %}
3607 interface(CONST_INTER);
3608 %}
3609
3610 // Long Immediate: low 32-bit mask
3611 operand immL_32bits()
3612 %{
3613 predicate(n->get_long() == 0xFFFFFFFFL);
3614 match(ConL);
3615 op_cost(20);
3616
3617 format %{ %}
3618 interface(CONST_INTER);
3619 %}
3620
3621 // Float Immediate zero
3622 operand immF0()
3623 %{
3624 predicate(jint_cast(n->getf()) == 0);
3625 match(ConF);
3626
3627 op_cost(5);
3628 format %{ %}
3629 interface(CONST_INTER);
3630 %}
3631
3632 // Float Immediate
3633 operand immF()
3634 %{
3635 match(ConF);
3636
3637 op_cost(15);
3638 format %{ %}
3639 interface(CONST_INTER);
3640 %}
3641
3642 // Double Immediate zero
3643 operand immD0()
3644 %{
3645 predicate(jlong_cast(n->getd()) == 0);
3646 match(ConD);
3647
3648 op_cost(5);
3649 format %{ %}
3650 interface(CONST_INTER);
3651 %}
3652
3653 // Double Immediate
3654 operand immD()
3655 %{
3656 match(ConD);
3657
3658 op_cost(15);
3659 format %{ %}
3660 interface(CONST_INTER);
3661 %}
3662
3663 // Immediates for special shifts (sign extend)
3664
3665 // Constants for increment
3666 operand immI_16()
3667 %{
3668 predicate(n->get_int() == 16);
3669 match(ConI);
3670
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3674
3675 operand immI_24()
3676 %{
3677 predicate(n->get_int() == 24);
3678 match(ConI);
3679
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 // Constant for byte-wide masking
3685 operand immI_255()
3686 %{
3687 predicate(n->get_int() == 255);
3688 match(ConI);
3689
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3693
3694 // Constant for short-wide masking
3695 operand immI_65535()
3696 %{
3697 predicate(n->get_int() == 65535);
3698 match(ConI);
3699
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Constant for byte-wide masking
3705 operand immL_255()
3706 %{
3707 predicate(n->get_long() == 255);
3708 match(ConL);
3709
3710 format %{ %}
3711 interface(CONST_INTER);
3712 %}
3713
3714 // Constant for short-wide masking
3715 operand immL_65535()
3716 %{
3717 predicate(n->get_long() == 65535);
3718 match(ConL);
3719
3720 format %{ %}
3721 interface(CONST_INTER);
3722 %}
3723
3724 // Register Operands
3725 // Integer Register
3726 operand rRegI()
3727 %{
3728 constraint(ALLOC_IN_RC(int_reg));
3729 match(RegI);
3730
3731 match(rax_RegI);
3732 match(rbx_RegI);
3733 match(rcx_RegI);
3734 match(rdx_RegI);
3735 match(rdi_RegI);
3736
3737 format %{ %}
3738 interface(REG_INTER);
3739 %}
3740
3741 // Special Registers
3742 operand rax_RegI()
3743 %{
3744 constraint(ALLOC_IN_RC(int_rax_reg));
3745 match(RegI);
3746 match(rRegI);
3747
3748 format %{ "RAX" %}
3749 interface(REG_INTER);
3750 %}
3751
3752 // Special Registers
3753 operand rbx_RegI()
3754 %{
3755 constraint(ALLOC_IN_RC(int_rbx_reg));
3756 match(RegI);
3757 match(rRegI);
3758
3759 format %{ "RBX" %}
3760 interface(REG_INTER);
3761 %}
3762
3763 operand rcx_RegI()
3764 %{
3765 constraint(ALLOC_IN_RC(int_rcx_reg));
3766 match(RegI);
3767 match(rRegI);
3768
3769 format %{ "RCX" %}
3770 interface(REG_INTER);
3771 %}
3772
3773 operand rdx_RegI()
3774 %{
3775 constraint(ALLOC_IN_RC(int_rdx_reg));
3776 match(RegI);
3777 match(rRegI);
3778
3779 format %{ "RDX" %}
3780 interface(REG_INTER);
3781 %}
3782
3783 operand rdi_RegI()
3784 %{
3785 constraint(ALLOC_IN_RC(int_rdi_reg));
3786 match(RegI);
3787 match(rRegI);
3788
3789 format %{ "RDI" %}
3790 interface(REG_INTER);
3791 %}
3792
3793 operand no_rcx_RegI()
3794 %{
3795 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3796 match(RegI);
3797 match(rax_RegI);
3798 match(rbx_RegI);
3799 match(rdx_RegI);
3800 match(rdi_RegI);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand no_rax_rdx_RegI()
3807 %{
3808 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3809 match(RegI);
3810 match(rbx_RegI);
3811 match(rcx_RegI);
3812 match(rdi_RegI);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 // Pointer Register
3819 operand any_RegP()
3820 %{
3821 constraint(ALLOC_IN_RC(any_reg));
3822 match(RegP);
3823 match(rax_RegP);
3824 match(rbx_RegP);
3825 match(rdi_RegP);
3826 match(rsi_RegP);
3827 match(rbp_RegP);
3828 match(r15_RegP);
3829 match(rRegP);
3830
3831 format %{ %}
3832 interface(REG_INTER);
3833 %}
3834
3835 operand rRegP()
3836 %{
3837 constraint(ALLOC_IN_RC(ptr_reg));
3838 match(RegP);
3839 match(rax_RegP);
3840 match(rbx_RegP);
3841 match(rdi_RegP);
3842 match(rsi_RegP);
3843 match(rbp_RegP);
3844 match(r15_RegP); // See Q&A below about r15_RegP.
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand rRegN() %{
3851 constraint(ALLOC_IN_RC(int_reg));
3852 match(RegN);
3853
3854 format %{ %}
3855 interface(REG_INTER);
3856 %}
3857
3858 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3859 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3860 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3861 // The output of an instruction is controlled by the allocator, which respects
3862 // register class masks, not match rules. Unless an instruction mentions
3863 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3864 // by the allocator as an input.
3865
3866 operand no_rax_RegP()
3867 %{
3868 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3869 match(RegP);
3870 match(rbx_RegP);
3871 match(rsi_RegP);
3872 match(rdi_RegP);
3873
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3877
3878 operand no_rbp_RegP()
3879 %{
3880 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3881 match(RegP);
3882 match(rbx_RegP);
3883 match(rsi_RegP);
3884 match(rdi_RegP);
3885
3886 format %{ %}
3887 interface(REG_INTER);
3888 %}
3889
3890 operand no_rax_rbx_RegP()
3891 %{
3892 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3893 match(RegP);
3894 match(rsi_RegP);
3895 match(rdi_RegP);
3896
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3900
3901 // Special Registers
3902 // Return a pointer value
3903 operand rax_RegP()
3904 %{
3905 constraint(ALLOC_IN_RC(ptr_rax_reg));
3906 match(RegP);
3907 match(rRegP);
3908
3909 format %{ %}
3910 interface(REG_INTER);
3911 %}
3912
3913 // Special Registers
3914 // Return a compressed pointer value
3915 operand rax_RegN()
3916 %{
3917 constraint(ALLOC_IN_RC(int_rax_reg));
3918 match(RegN);
3919 match(rRegN);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 // Used in AtomicAdd
3926 operand rbx_RegP()
3927 %{
3928 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3929 match(RegP);
3930 match(rRegP);
3931
3932 format %{ %}
3933 interface(REG_INTER);
3934 %}
3935
3936 operand rsi_RegP()
3937 %{
3938 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3939 match(RegP);
3940 match(rRegP);
3941
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3945
3946 // Used in rep stosq
3947 operand rdi_RegP()
3948 %{
3949 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3950 match(RegP);
3951 match(rRegP);
3952
3953 format %{ %}
3954 interface(REG_INTER);
3955 %}
3956
3957 operand rbp_RegP()
3958 %{
3959 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3960 match(RegP);
3961 match(rRegP);
3962
3963 format %{ %}
3964 interface(REG_INTER);
3965 %}
3966
3967 operand r15_RegP()
3968 %{
3969 constraint(ALLOC_IN_RC(ptr_r15_reg));
3970 match(RegP);
3971 match(rRegP);
3972
3973 format %{ %}
3974 interface(REG_INTER);
3975 %}
3976
3977 operand rRegL()
3978 %{
3979 constraint(ALLOC_IN_RC(long_reg));
3980 match(RegL);
3981 match(rax_RegL);
3982 match(rdx_RegL);
3983
3984 format %{ %}
3985 interface(REG_INTER);
3986 %}
3987
3988 // Special Registers
3989 operand no_rax_rdx_RegL()
3990 %{
3991 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3992 match(RegL);
3993 match(rRegL);
3994
3995 format %{ %}
3996 interface(REG_INTER);
3997 %}
3998
3999 operand no_rax_RegL()
4000 %{
4001 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4002 match(RegL);
4003 match(rRegL);
4004 match(rdx_RegL);
4005
4006 format %{ %}
4007 interface(REG_INTER);
4008 %}
4009
4010 operand no_rcx_RegL()
4011 %{
4012 constraint(ALLOC_IN_RC(long_no_rcx_reg));
4013 match(RegL);
4014 match(rRegL);
4015
4016 format %{ %}
4017 interface(REG_INTER);
4018 %}
4019
4020 operand rax_RegL()
4021 %{
4022 constraint(ALLOC_IN_RC(long_rax_reg));
4023 match(RegL);
4024 match(rRegL);
4025
4026 format %{ "RAX" %}
4027 interface(REG_INTER);
4028 %}
4029
4030 operand rcx_RegL()
4031 %{
4032 constraint(ALLOC_IN_RC(long_rcx_reg));
4033 match(RegL);
4034 match(rRegL);
4035
4036 format %{ %}
4037 interface(REG_INTER);
4038 %}
4039
4040 operand rdx_RegL()
4041 %{
4042 constraint(ALLOC_IN_RC(long_rdx_reg));
4043 match(RegL);
4044 match(rRegL);
4045
4046 format %{ %}
4047 interface(REG_INTER);
4048 %}
4049
4050 // Flags register, used as output of compare instructions
4051 operand rFlagsReg()
4052 %{
4053 constraint(ALLOC_IN_RC(int_flags));
4054 match(RegFlags);
4055
4056 format %{ "RFLAGS" %}
4057 interface(REG_INTER);
4058 %}
4059
4060 // Flags register, used as output of FLOATING POINT compare instructions
4061 operand rFlagsRegU()
4062 %{
4063 constraint(ALLOC_IN_RC(int_flags));
4064 match(RegFlags);
4065
4066 format %{ "RFLAGS_U" %}
4067 interface(REG_INTER);
4068 %}
4069
4070 operand rFlagsRegUCF() %{
4071 constraint(ALLOC_IN_RC(int_flags));
4072 match(RegFlags);
4073 predicate(false);
4074
4075 format %{ "RFLAGS_U_CF" %}
4076 interface(REG_INTER);
4077 %}
4078
4079 // Float register operands
4080 operand regF()
4081 %{
4082 constraint(ALLOC_IN_RC(float_reg));
4083 match(RegF);
4084
4085 format %{ %}
4086 interface(REG_INTER);
4087 %}
4088
4089 // Double register operands
4090 operand regD()
4091 %{
4092 constraint(ALLOC_IN_RC(double_reg));
4093 match(RegD);
4094
4095 format %{ %}
4096 interface(REG_INTER);
4097 %}
4098
4099
4100 //----------Memory Operands----------------------------------------------------
4101 // Direct Memory Operand
4102 // operand direct(immP addr)
4103 // %{
4104 // match(addr);
4105
4106 // format %{ "[$addr]" %}
4107 // interface(MEMORY_INTER) %{
4108 // base(0xFFFFFFFF);
4109 // index(0x4);
4110 // scale(0x0);
4111 // disp($addr);
4112 // %}
4113 // %}
4114
4115 // Indirect Memory Operand
4116 operand indirect(any_RegP reg)
4117 %{
4118 constraint(ALLOC_IN_RC(ptr_reg));
4119 match(reg);
4120
4121 format %{ "[$reg]" %}
4122 interface(MEMORY_INTER) %{
4123 base($reg);
4124 index(0x4);
4125 scale(0x0);
4126 disp(0x0);
4127 %}
4128 %}
4129
4130 // Indirect Memory Plus Short Offset Operand
4131 operand indOffset8(any_RegP reg, immL8 off)
4132 %{
4133 constraint(ALLOC_IN_RC(ptr_reg));
4134 match(AddP reg off);
4135
4136 format %{ "[$reg + $off (8-bit)]" %}
4137 interface(MEMORY_INTER) %{
4138 base($reg);
4139 index(0x4);
4140 scale(0x0);
4141 disp($off);
4142 %}
4143 %}
4144
4145 // Indirect Memory Plus Long Offset Operand
4146 operand indOffset32(any_RegP reg, immL32 off)
4147 %{
4148 constraint(ALLOC_IN_RC(ptr_reg));
4149 match(AddP reg off);
4150
4151 format %{ "[$reg + $off (32-bit)]" %}
4152 interface(MEMORY_INTER) %{
4153 base($reg);
4154 index(0x4);
4155 scale(0x0);
4156 disp($off);
4157 %}
4158 %}
4159
4160 // Indirect Memory Plus Index Register Plus Offset Operand
4161 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
4162 %{
4163 constraint(ALLOC_IN_RC(ptr_reg));
4164 match(AddP (AddP reg lreg) off);
4165
4166 op_cost(10);
4167 format %{"[$reg + $off + $lreg]" %}
4168 interface(MEMORY_INTER) %{
4169 base($reg);
4170 index($lreg);
4171 scale(0x0);
4172 disp($off);
4173 %}
4174 %}
4175
4176 // Indirect Memory Plus Index Register Plus Offset Operand
4177 operand indIndex(any_RegP reg, rRegL lreg)
4178 %{
4179 constraint(ALLOC_IN_RC(ptr_reg));
4180 match(AddP reg lreg);
4181
4182 op_cost(10);
4183 format %{"[$reg + $lreg]" %}
4184 interface(MEMORY_INTER) %{
4185 base($reg);
4186 index($lreg);
4187 scale(0x0);
4188 disp(0x0);
4189 %}
4190 %}
4191
4192 // Indirect Memory Times Scale Plus Index Register
4193 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
4194 %{
4195 constraint(ALLOC_IN_RC(ptr_reg));
4196 match(AddP reg (LShiftL lreg scale));
4197
4198 op_cost(10);
4199 format %{"[$reg + $lreg << $scale]" %}
4200 interface(MEMORY_INTER) %{
4201 base($reg);
4202 index($lreg);
4203 scale($scale);
4204 disp(0x0);
4205 %}
4206 %}
4207
4208 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4209 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
4210 %{
4211 constraint(ALLOC_IN_RC(ptr_reg));
4212 match(AddP (AddP reg (LShiftL lreg scale)) off);
4213
4214 op_cost(10);
4215 format %{"[$reg + $off + $lreg << $scale]" %}
4216 interface(MEMORY_INTER) %{
4217 base($reg);
4218 index($lreg);
4219 scale($scale);
4220 disp($off);
4221 %}
4222 %}
4223
4224 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4225 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
4226 %{
4227 constraint(ALLOC_IN_RC(ptr_reg));
4228 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4229 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
4230
4231 op_cost(10);
4232 format %{"[$reg + $off + $idx << $scale]" %}
4233 interface(MEMORY_INTER) %{
4234 base($reg);
4235 index($idx);
4236 scale($scale);
4237 disp($off);
4238 %}
4239 %}
4240
4241 // Indirect Narrow Oop Plus Offset Operand
4242 // Note: x86 architecture doesn't support "scale * index + offset" without a base
4243 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
4244 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
4245 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
4246 constraint(ALLOC_IN_RC(ptr_reg));
4247 match(AddP (DecodeN reg) off);
4248
4249 op_cost(10);
4250 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
4251 interface(MEMORY_INTER) %{
4252 base(0xc); // R12
4253 index($reg);
4254 scale(0x3);
4255 disp($off);
4256 %}
4257 %}
4258
4259 // Indirect Memory Operand
4260 operand indirectNarrow(rRegN reg)
4261 %{
4262 predicate(Universe::narrow_oop_shift() == 0);
4263 constraint(ALLOC_IN_RC(ptr_reg));
4264 match(DecodeN reg);
4265
4266 format %{ "[$reg]" %}
4267 interface(MEMORY_INTER) %{
4268 base($reg);
4269 index(0x4);
4270 scale(0x0);
4271 disp(0x0);
4272 %}
4273 %}
4274
4275 // Indirect Memory Plus Short Offset Operand
4276 operand indOffset8Narrow(rRegN reg, immL8 off)
4277 %{
4278 predicate(Universe::narrow_oop_shift() == 0);
4279 constraint(ALLOC_IN_RC(ptr_reg));
4280 match(AddP (DecodeN reg) off);
4281
4282 format %{ "[$reg + $off (8-bit)]" %}
4283 interface(MEMORY_INTER) %{
4284 base($reg);
4285 index(0x4);
4286 scale(0x0);
4287 disp($off);
4288 %}
4289 %}
4290
4291 // Indirect Memory Plus Long Offset Operand
4292 operand indOffset32Narrow(rRegN reg, immL32 off)
4293 %{
4294 predicate(Universe::narrow_oop_shift() == 0);
4295 constraint(ALLOC_IN_RC(ptr_reg));
4296 match(AddP (DecodeN reg) off);
4297
4298 format %{ "[$reg + $off (32-bit)]" %}
4299 interface(MEMORY_INTER) %{
4300 base($reg);
4301 index(0x4);
4302 scale(0x0);
4303 disp($off);
4304 %}
4305 %}
4306
4307 // Indirect Memory Plus Index Register Plus Offset Operand
4308 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4309 %{
4310 predicate(Universe::narrow_oop_shift() == 0);
4311 constraint(ALLOC_IN_RC(ptr_reg));
4312 match(AddP (AddP (DecodeN reg) lreg) off);
4313
4314 op_cost(10);
4315 format %{"[$reg + $off + $lreg]" %}
4316 interface(MEMORY_INTER) %{
4317 base($reg);
4318 index($lreg);
4319 scale(0x0);
4320 disp($off);
4321 %}
4322 %}
4323
4324 // Indirect Memory Plus Index Register Plus Offset Operand
4325 operand indIndexNarrow(rRegN reg, rRegL lreg)
4326 %{
4327 predicate(Universe::narrow_oop_shift() == 0);
4328 constraint(ALLOC_IN_RC(ptr_reg));
4329 match(AddP (DecodeN reg) lreg);
4330
4331 op_cost(10);
4332 format %{"[$reg + $lreg]" %}
4333 interface(MEMORY_INTER) %{
4334 base($reg);
4335 index($lreg);
4336 scale(0x0);
4337 disp(0x0);
4338 %}
4339 %}
4340
4341 // Indirect Memory Times Scale Plus Index Register
4342 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4343 %{
4344 predicate(Universe::narrow_oop_shift() == 0);
4345 constraint(ALLOC_IN_RC(ptr_reg));
4346 match(AddP (DecodeN reg) (LShiftL lreg scale));
4347
4348 op_cost(10);
4349 format %{"[$reg + $lreg << $scale]" %}
4350 interface(MEMORY_INTER) %{
4351 base($reg);
4352 index($lreg);
4353 scale($scale);
4354 disp(0x0);
4355 %}
4356 %}
4357
4358 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4359 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4360 %{
4361 predicate(Universe::narrow_oop_shift() == 0);
4362 constraint(ALLOC_IN_RC(ptr_reg));
4363 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4364
4365 op_cost(10);
4366 format %{"[$reg + $off + $lreg << $scale]" %}
4367 interface(MEMORY_INTER) %{
4368 base($reg);
4369 index($lreg);
4370 scale($scale);
4371 disp($off);
4372 %}
4373 %}
4374
4375 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4376 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4377 %{
4378 constraint(ALLOC_IN_RC(ptr_reg));
4379 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4380 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4381
4382 op_cost(10);
4383 format %{"[$reg + $off + $idx << $scale]" %}
4384 interface(MEMORY_INTER) %{
4385 base($reg);
4386 index($idx);
4387 scale($scale);
4388 disp($off);
4389 %}
4390 %}
4391
4392
4393 //----------Special Memory Operands--------------------------------------------
4394 // Stack Slot Operand - This operand is used for loading and storing temporary
4395 // values on the stack where a match requires a value to
4396 // flow through memory.
4397 operand stackSlotP(sRegP reg)
4398 %{
4399 constraint(ALLOC_IN_RC(stack_slots));
4400 // No match rule because this operand is only generated in matching
4401
4402 format %{ "[$reg]" %}
4403 interface(MEMORY_INTER) %{
4404 base(0x4); // RSP
4405 index(0x4); // No Index
4406 scale(0x0); // No Scale
4407 disp($reg); // Stack Offset
4408 %}
4409 %}
4410
4411 operand stackSlotI(sRegI reg)
4412 %{
4413 constraint(ALLOC_IN_RC(stack_slots));
4414 // No match rule because this operand is only generated in matching
4415
4416 format %{ "[$reg]" %}
4417 interface(MEMORY_INTER) %{
4418 base(0x4); // RSP
4419 index(0x4); // No Index
4420 scale(0x0); // No Scale
4421 disp($reg); // Stack Offset
4422 %}
4423 %}
4424
4425 operand stackSlotF(sRegF reg)
4426 %{
4427 constraint(ALLOC_IN_RC(stack_slots));
4428 // No match rule because this operand is only generated in matching
4429
4430 format %{ "[$reg]" %}
4431 interface(MEMORY_INTER) %{
4432 base(0x4); // RSP
4433 index(0x4); // No Index
4434 scale(0x0); // No Scale
4435 disp($reg); // Stack Offset
4436 %}
4437 %}
4438
4439 operand stackSlotD(sRegD reg)
4440 %{
4441 constraint(ALLOC_IN_RC(stack_slots));
4442 // No match rule because this operand is only generated in matching
4443
4444 format %{ "[$reg]" %}
4445 interface(MEMORY_INTER) %{
4446 base(0x4); // RSP
4447 index(0x4); // No Index
4448 scale(0x0); // No Scale
4449 disp($reg); // Stack Offset
4450 %}
4451 %}
4452 operand stackSlotL(sRegL reg)
4453 %{
4454 constraint(ALLOC_IN_RC(stack_slots));
4455 // No match rule because this operand is only generated in matching
4456
4457 format %{ "[$reg]" %}
4458 interface(MEMORY_INTER) %{
4459 base(0x4); // RSP
4460 index(0x4); // No Index
4461 scale(0x0); // No Scale
4462 disp($reg); // Stack Offset
4463 %}
4464 %}
4465
4466 //----------Conditional Branch Operands----------------------------------------
4467 // Comparison Op - This is the operation of the comparison, and is limited to
4468 // the following set of codes:
4469 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4470 //
4471 // Other attributes of the comparison, such as unsignedness, are specified
4472 // by the comparison instruction that sets a condition code flags register.
4473 // That result is represented by a flags operand whose subtype is appropriate
4474 // to the unsignedness (etc.) of the comparison.
4475 //
4476 // Later, the instruction which matches both the Comparison Op (a Bool) and
4477 // the flags (produced by the Cmp) specifies the coding of the comparison op
4478 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4479
4480 // Comparision Code
4481 operand cmpOp()
4482 %{
4483 match(Bool);
4484
4485 format %{ "" %}
4486 interface(COND_INTER) %{
4487 equal(0x4, "e");
4488 not_equal(0x5, "ne");
4489 less(0xC, "l");
4490 greater_equal(0xD, "ge");
4491 less_equal(0xE, "le");
4492 greater(0xF, "g");
4493 %}
4494 %}
4495
4496 // Comparison Code, unsigned compare. Used by FP also, with
4497 // C2 (unordered) turned into GT or LT already. The other bits
4498 // C0 and C3 are turned into Carry & Zero flags.
4499 operand cmpOpU()
4500 %{
4501 match(Bool);
4502
4503 format %{ "" %}
4504 interface(COND_INTER) %{
4505 equal(0x4, "e");
4506 not_equal(0x5, "ne");
4507 less(0x2, "b");
4508 greater_equal(0x3, "nb");
4509 less_equal(0x6, "be");
4510 greater(0x7, "nbe");
4511 %}
4512 %}
4513
4514
4515 // Floating comparisons that don't require any fixup for the unordered case
4516 operand cmpOpUCF() %{
4517 match(Bool);
4518 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4519 n->as_Bool()->_test._test == BoolTest::ge ||
4520 n->as_Bool()->_test._test == BoolTest::le ||
4521 n->as_Bool()->_test._test == BoolTest::gt);
4522 format %{ "" %}
4523 interface(COND_INTER) %{
4524 equal(0x4, "e");
4525 not_equal(0x5, "ne");
4526 less(0x2, "b");
4527 greater_equal(0x3, "nb");
4528 less_equal(0x6, "be");
4529 greater(0x7, "nbe");
4530 %}
4531 %}
4532
4533
4534 // Floating comparisons that can be fixed up with extra conditional jumps
4535 operand cmpOpUCF2() %{
4536 match(Bool);
4537 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4538 n->as_Bool()->_test._test == BoolTest::eq);
4539 format %{ "" %}
4540 interface(COND_INTER) %{
4541 equal(0x4, "e");
4542 not_equal(0x5, "ne");
4543 less(0x2, "b");
4544 greater_equal(0x3, "nb");
4545 less_equal(0x6, "be");
4546 greater(0x7, "nbe");
4547 %}
4548 %}
4549
4550
4551 //----------OPERAND CLASSES----------------------------------------------------
4552 // Operand Classes are groups of operands that are used as to simplify
4553 // instruction definitions by not requiring the AD writer to specify separate
4554 // instructions for every form of operand when the instruction accepts
4555 // multiple operand types with the same basic encoding and format. The classic
4556 // case of this is memory operands.
4557
4558 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4559 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4560 indCompressedOopOffset,
4561 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4562 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4563 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4564
4565 //----------PIPELINE-----------------------------------------------------------
4566 // Rules which define the behavior of the target architectures pipeline.
4567 pipeline %{
4568
4569 //----------ATTRIBUTES---------------------------------------------------------
4570 attributes %{
4571 variable_size_instructions; // Fixed size instructions
4572 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4573 instruction_unit_size = 1; // An instruction is 1 bytes long
4574 instruction_fetch_unit_size = 16; // The processor fetches one line
4575 instruction_fetch_units = 1; // of 16 bytes
4576
4577 // List of nop instructions
4578 nops( MachNop );
4579 %}
4580
4581 //----------RESOURCES----------------------------------------------------------
4582 // Resources are the functional units available to the machine
4583
4584 // Generic P2/P3 pipeline
4585 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4586 // 3 instructions decoded per cycle.
4587 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4588 // 3 ALU op, only ALU0 handles mul instructions.
4589 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4590 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4591 BR, FPU,
4592 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4593
4594 //----------PIPELINE DESCRIPTION-----------------------------------------------
4595 // Pipeline Description specifies the stages in the machine's pipeline
4596
4597 // Generic P2/P3 pipeline
4598 pipe_desc(S0, S1, S2, S3, S4, S5);
4599
4600 //----------PIPELINE CLASSES---------------------------------------------------
4601 // Pipeline Classes describe the stages in which input and output are
4602 // referenced by the hardware pipeline.
4603
4604 // Naming convention: ialu or fpu
4605 // Then: _reg
4606 // Then: _reg if there is a 2nd register
4607 // Then: _long if it's a pair of instructions implementing a long
4608 // Then: _fat if it requires the big decoder
4609 // Or: _mem if it requires the big decoder and a memory unit.
4610
4611 // Integer ALU reg operation
4612 pipe_class ialu_reg(rRegI dst)
4613 %{
4614 single_instruction;
4615 dst : S4(write);
4616 dst : S3(read);
4617 DECODE : S0; // any decoder
4618 ALU : S3; // any alu
4619 %}
4620
4621 // Long ALU reg operation
4622 pipe_class ialu_reg_long(rRegL dst)
4623 %{
4624 instruction_count(2);
4625 dst : S4(write);
4626 dst : S3(read);
4627 DECODE : S0(2); // any 2 decoders
4628 ALU : S3(2); // both alus
4629 %}
4630
4631 // Integer ALU reg operation using big decoder
4632 pipe_class ialu_reg_fat(rRegI dst)
4633 %{
4634 single_instruction;
4635 dst : S4(write);
4636 dst : S3(read);
4637 D0 : S0; // big decoder only
4638 ALU : S3; // any alu
4639 %}
4640
4641 // Long ALU reg operation using big decoder
4642 pipe_class ialu_reg_long_fat(rRegL dst)
4643 %{
4644 instruction_count(2);
4645 dst : S4(write);
4646 dst : S3(read);
4647 D0 : S0(2); // big decoder only; twice
4648 ALU : S3(2); // any 2 alus
4649 %}
4650
4651 // Integer ALU reg-reg operation
4652 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4653 %{
4654 single_instruction;
4655 dst : S4(write);
4656 src : S3(read);
4657 DECODE : S0; // any decoder
4658 ALU : S3; // any alu
4659 %}
4660
4661 // Long ALU reg-reg operation
4662 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4663 %{
4664 instruction_count(2);
4665 dst : S4(write);
4666 src : S3(read);
4667 DECODE : S0(2); // any 2 decoders
4668 ALU : S3(2); // both alus
4669 %}
4670
4671 // Integer ALU reg-reg operation
4672 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4673 %{
4674 single_instruction;
4675 dst : S4(write);
4676 src : S3(read);
4677 D0 : S0; // big decoder only
4678 ALU : S3; // any alu
4679 %}
4680
4681 // Long ALU reg-reg operation
4682 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4683 %{
4684 instruction_count(2);
4685 dst : S4(write);
4686 src : S3(read);
4687 D0 : S0(2); // big decoder only; twice
4688 ALU : S3(2); // both alus
4689 %}
4690
4691 // Integer ALU reg-mem operation
4692 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4693 %{
4694 single_instruction;
4695 dst : S5(write);
4696 mem : S3(read);
4697 D0 : S0; // big decoder only
4698 ALU : S4; // any alu
4699 MEM : S3; // any mem
4700 %}
4701
4702 // Integer mem operation (prefetch)
4703 pipe_class ialu_mem(memory mem)
4704 %{
4705 single_instruction;
4706 mem : S3(read);
4707 D0 : S0; // big decoder only
4708 MEM : S3; // any mem
4709 %}
4710
4711 // Integer Store to Memory
4712 pipe_class ialu_mem_reg(memory mem, rRegI src)
4713 %{
4714 single_instruction;
4715 mem : S3(read);
4716 src : S5(read);
4717 D0 : S0; // big decoder only
4718 ALU : S4; // any alu
4719 MEM : S3;
4720 %}
4721
4722 // // Long Store to Memory
4723 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4724 // %{
4725 // instruction_count(2);
4726 // mem : S3(read);
4727 // src : S5(read);
4728 // D0 : S0(2); // big decoder only; twice
4729 // ALU : S4(2); // any 2 alus
4730 // MEM : S3(2); // Both mems
4731 // %}
4732
4733 // Integer Store to Memory
4734 pipe_class ialu_mem_imm(memory mem)
4735 %{
4736 single_instruction;
4737 mem : S3(read);
4738 D0 : S0; // big decoder only
4739 ALU : S4; // any alu
4740 MEM : S3;
4741 %}
4742
4743 // Integer ALU0 reg-reg operation
4744 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4745 %{
4746 single_instruction;
4747 dst : S4(write);
4748 src : S3(read);
4749 D0 : S0; // Big decoder only
4750 ALU0 : S3; // only alu0
4751 %}
4752
4753 // Integer ALU0 reg-mem operation
4754 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4755 %{
4756 single_instruction;
4757 dst : S5(write);
4758 mem : S3(read);
4759 D0 : S0; // big decoder only
4760 ALU0 : S4; // ALU0 only
4761 MEM : S3; // any mem
4762 %}
4763
4764 // Integer ALU reg-reg operation
4765 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4766 %{
4767 single_instruction;
4768 cr : S4(write);
4769 src1 : S3(read);
4770 src2 : S3(read);
4771 DECODE : S0; // any decoder
4772 ALU : S3; // any alu
4773 %}
4774
4775 // Integer ALU reg-imm operation
4776 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4777 %{
4778 single_instruction;
4779 cr : S4(write);
4780 src1 : S3(read);
4781 DECODE : S0; // any decoder
4782 ALU : S3; // any alu
4783 %}
4784
4785 // Integer ALU reg-mem operation
4786 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4787 %{
4788 single_instruction;
4789 cr : S4(write);
4790 src1 : S3(read);
4791 src2 : S3(read);
4792 D0 : S0; // big decoder only
4793 ALU : S4; // any alu
4794 MEM : S3;
4795 %}
4796
4797 // Conditional move reg-reg
4798 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4799 %{
4800 instruction_count(4);
4801 y : S4(read);
4802 q : S3(read);
4803 p : S3(read);
4804 DECODE : S0(4); // any decoder
4805 %}
4806
4807 // Conditional move reg-reg
4808 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4809 %{
4810 single_instruction;
4811 dst : S4(write);
4812 src : S3(read);
4813 cr : S3(read);
4814 DECODE : S0; // any decoder
4815 %}
4816
4817 // Conditional move reg-mem
4818 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4819 %{
4820 single_instruction;
4821 dst : S4(write);
4822 src : S3(read);
4823 cr : S3(read);
4824 DECODE : S0; // any decoder
4825 MEM : S3;
4826 %}
4827
4828 // Conditional move reg-reg long
4829 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4830 %{
4831 single_instruction;
4832 dst : S4(write);
4833 src : S3(read);
4834 cr : S3(read);
4835 DECODE : S0(2); // any 2 decoders
4836 %}
4837
4838 // XXX
4839 // // Conditional move double reg-reg
4840 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4841 // %{
4842 // single_instruction;
4843 // dst : S4(write);
4844 // src : S3(read);
4845 // cr : S3(read);
4846 // DECODE : S0; // any decoder
4847 // %}
4848
4849 // Float reg-reg operation
4850 pipe_class fpu_reg(regD dst)
4851 %{
4852 instruction_count(2);
4853 dst : S3(read);
4854 DECODE : S0(2); // any 2 decoders
4855 FPU : S3;
4856 %}
4857
4858 // Float reg-reg operation
4859 pipe_class fpu_reg_reg(regD dst, regD src)
4860 %{
4861 instruction_count(2);
4862 dst : S4(write);
4863 src : S3(read);
4864 DECODE : S0(2); // any 2 decoders
4865 FPU : S3;
4866 %}
4867
4868 // Float reg-reg operation
4869 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4870 %{
4871 instruction_count(3);
4872 dst : S4(write);
4873 src1 : S3(read);
4874 src2 : S3(read);
4875 DECODE : S0(3); // any 3 decoders
4876 FPU : S3(2);
4877 %}
4878
4879 // Float reg-reg operation
4880 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4881 %{
4882 instruction_count(4);
4883 dst : S4(write);
4884 src1 : S3(read);
4885 src2 : S3(read);
4886 src3 : S3(read);
4887 DECODE : S0(4); // any 3 decoders
4888 FPU : S3(2);
4889 %}
4890
4891 // Float reg-reg operation
4892 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4893 %{
4894 instruction_count(4);
4895 dst : S4(write);
4896 src1 : S3(read);
4897 src2 : S3(read);
4898 src3 : S3(read);
4899 DECODE : S1(3); // any 3 decoders
4900 D0 : S0; // Big decoder only
4901 FPU : S3(2);
4902 MEM : S3;
4903 %}
4904
4905 // Float reg-mem operation
4906 pipe_class fpu_reg_mem(regD dst, memory mem)
4907 %{
4908 instruction_count(2);
4909 dst : S5(write);
4910 mem : S3(read);
4911 D0 : S0; // big decoder only
4912 DECODE : S1; // any decoder for FPU POP
4913 FPU : S4;
4914 MEM : S3; // any mem
4915 %}
4916
4917 // Float reg-mem operation
4918 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4919 %{
4920 instruction_count(3);
4921 dst : S5(write);
4922 src1 : S3(read);
4923 mem : S3(read);
4924 D0 : S0; // big decoder only
4925 DECODE : S1(2); // any decoder for FPU POP
4926 FPU : S4;
4927 MEM : S3; // any mem
4928 %}
4929
4930 // Float mem-reg operation
4931 pipe_class fpu_mem_reg(memory mem, regD src)
4932 %{
4933 instruction_count(2);
4934 src : S5(read);
4935 mem : S3(read);
4936 DECODE : S0; // any decoder for FPU PUSH
4937 D0 : S1; // big decoder only
4938 FPU : S4;
4939 MEM : S3; // any mem
4940 %}
4941
4942 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4943 %{
4944 instruction_count(3);
4945 src1 : S3(read);
4946 src2 : S3(read);
4947 mem : S3(read);
4948 DECODE : S0(2); // any decoder for FPU PUSH
4949 D0 : S1; // big decoder only
4950 FPU : S4;
4951 MEM : S3; // any mem
4952 %}
4953
4954 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4955 %{
4956 instruction_count(3);
4957 src1 : S3(read);
4958 src2 : S3(read);
4959 mem : S4(read);
4960 DECODE : S0; // any decoder for FPU PUSH
4961 D0 : S0(2); // big decoder only
4962 FPU : S4;
4963 MEM : S3(2); // any mem
4964 %}
4965
4966 pipe_class fpu_mem_mem(memory dst, memory src1)
4967 %{
4968 instruction_count(2);
4969 src1 : S3(read);
4970 dst : S4(read);
4971 D0 : S0(2); // big decoder only
4972 MEM : S3(2); // any mem
4973 %}
4974
4975 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4976 %{
4977 instruction_count(3);
4978 src1 : S3(read);
4979 src2 : S3(read);
4980 dst : S4(read);
4981 D0 : S0(3); // big decoder only
4982 FPU : S4;
4983 MEM : S3(3); // any mem
4984 %}
4985
4986 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4987 %{
4988 instruction_count(3);
4989 src1 : S4(read);
4990 mem : S4(read);
4991 DECODE : S0; // any decoder for FPU PUSH
4992 D0 : S0(2); // big decoder only
4993 FPU : S4;
4994 MEM : S3(2); // any mem
4995 %}
4996
4997 // Float load constant
4998 pipe_class fpu_reg_con(regD dst)
4999 %{
5000 instruction_count(2);
5001 dst : S5(write);
5002 D0 : S0; // big decoder only for the load
5003 DECODE : S1; // any decoder for FPU POP
5004 FPU : S4;
5005 MEM : S3; // any mem
5006 %}
5007
5008 // Float load constant
5009 pipe_class fpu_reg_reg_con(regD dst, regD src)
5010 %{
5011 instruction_count(3);
5012 dst : S5(write);
5013 src : S3(read);
5014 D0 : S0; // big decoder only for the load
5015 DECODE : S1(2); // any decoder for FPU POP
5016 FPU : S4;
5017 MEM : S3; // any mem
5018 %}
5019
5020 // UnConditional branch
5021 pipe_class pipe_jmp(label labl)
5022 %{
5023 single_instruction;
5024 BR : S3;
5025 %}
5026
5027 // Conditional branch
5028 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5029 %{
5030 single_instruction;
5031 cr : S1(read);
5032 BR : S3;
5033 %}
5034
5035 // Allocation idiom
5036 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5037 %{
5038 instruction_count(1); force_serialization;
5039 fixed_latency(6);
5040 heap_ptr : S3(read);
5041 DECODE : S0(3);
5042 D0 : S2;
5043 MEM : S3;
5044 ALU : S3(2);
5045 dst : S5(write);
5046 BR : S5;
5047 %}
5048
5049 // Generic big/slow expanded idiom
5050 pipe_class pipe_slow()
5051 %{
5052 instruction_count(10); multiple_bundles; force_serialization;
5053 fixed_latency(100);
5054 D0 : S0(2);
5055 MEM : S3(2);
5056 %}
5057
5058 // The real do-nothing guy
5059 pipe_class empty()
5060 %{
5061 instruction_count(0);
5062 %}
5063
5064 // Define the class for the Nop node
5065 define
5066 %{
5067 MachNop = empty;
5068 %}
5069
5070 %}
5071
5072 //----------INSTRUCTIONS-------------------------------------------------------
5073 //
5074 // match -- States which machine-independent subtree may be replaced
5075 // by this instruction.
5076 // ins_cost -- The estimated cost of this instruction is used by instruction
5077 // selection to identify a minimum cost tree of machine
5078 // instructions that matches a tree of machine-independent
5079 // instructions.
5080 // format -- A string providing the disassembly for this instruction.
5081 // The value of an instruction's operand may be inserted
5082 // by referring to it with a '$' prefix.
5083 // opcode -- Three instruction opcodes may be provided. These are referred
5084 // to within an encode class as $primary, $secondary, and $tertiary
5085 // rrspectively. The primary opcode is commonly used to
5086 // indicate the type of machine instruction, while secondary
5087 // and tertiary are often used for prefix options or addressing
5088 // modes.
5089 // ins_encode -- A list of encode classes with parameters. The encode class
5090 // name must have been defined in an 'enc_class' specification
5091 // in the encode section of the architecture description.
5092
5093
5094 //----------Load/Store/Move Instructions---------------------------------------
5095 //----------Load Instructions--------------------------------------------------
5096
5097 // Load Byte (8 bit signed)
5098 instruct loadB(rRegI dst, memory mem)
5099 %{
5100 match(Set dst (LoadB mem));
5101
5102 ins_cost(125);
5103 format %{ "movsbl $dst, $mem\t# byte" %}
5104
5105 ins_encode %{
5106 __ movsbl($dst$$Register, $mem$$Address);
5107 %}
5108
5109 ins_pipe(ialu_reg_mem);
5110 %}
5111
5112 // Load Byte (8 bit signed) into Long Register
5113 instruct loadB2L(rRegL dst, memory mem)
5114 %{
5115 match(Set dst (ConvI2L (LoadB mem)));
5116
5117 ins_cost(125);
5118 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5119
5120 ins_encode %{
5121 __ movsbq($dst$$Register, $mem$$Address);
5122 %}
5123
5124 ins_pipe(ialu_reg_mem);
5125 %}
5126
5127 // Load Unsigned Byte (8 bit UNsigned)
5128 instruct loadUB(rRegI dst, memory mem)
5129 %{
5130 match(Set dst (LoadUB mem));
5131
5132 ins_cost(125);
5133 format %{ "movzbl $dst, $mem\t# ubyte" %}
5134
5135 ins_encode %{
5136 __ movzbl($dst$$Register, $mem$$Address);
5137 %}
5138
5139 ins_pipe(ialu_reg_mem);
5140 %}
5141
5142 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5143 instruct loadUB2L(rRegL dst, memory mem)
5144 %{
5145 match(Set dst (ConvI2L (LoadUB mem)));
5146
5147 ins_cost(125);
5148 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5149
5150 ins_encode %{
5151 __ movzbq($dst$$Register, $mem$$Address);
5152 %}
5153
5154 ins_pipe(ialu_reg_mem);
5155 %}
5156
5157 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
5158 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
5159 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5160 effect(KILL cr);
5161
5162 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
5163 "andl $dst, $mask" %}
5164 ins_encode %{
5165 Register Rdst = $dst$$Register;
5166 __ movzbq(Rdst, $mem$$Address);
5167 __ andl(Rdst, $mask$$constant);
5168 %}
5169 ins_pipe(ialu_reg_mem);
5170 %}
5171
5172 // Load Short (16 bit signed)
5173 instruct loadS(rRegI dst, memory mem)
5174 %{
5175 match(Set dst (LoadS mem));
5176
5177 ins_cost(125);
5178 format %{ "movswl $dst, $mem\t# short" %}
5179
5180 ins_encode %{
5181 __ movswl($dst$$Register, $mem$$Address);
5182 %}
5183
5184 ins_pipe(ialu_reg_mem);
5185 %}
5186
5187 // Load Short (16 bit signed) to Byte (8 bit signed)
5188 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5189 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5190
5191 ins_cost(125);
5192 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5193 ins_encode %{
5194 __ movsbl($dst$$Register, $mem$$Address);
5195 %}
5196 ins_pipe(ialu_reg_mem);
5197 %}
5198
5199 // Load Short (16 bit signed) into Long Register
5200 instruct loadS2L(rRegL dst, memory mem)
5201 %{
5202 match(Set dst (ConvI2L (LoadS mem)));
5203
5204 ins_cost(125);
5205 format %{ "movswq $dst, $mem\t# short -> long" %}
5206
5207 ins_encode %{
5208 __ movswq($dst$$Register, $mem$$Address);
5209 %}
5210
5211 ins_pipe(ialu_reg_mem);
5212 %}
5213
5214 // Load Unsigned Short/Char (16 bit UNsigned)
5215 instruct loadUS(rRegI dst, memory mem)
5216 %{
5217 match(Set dst (LoadUS mem));
5218
5219 ins_cost(125);
5220 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5221
5222 ins_encode %{
5223 __ movzwl($dst$$Register, $mem$$Address);
5224 %}
5225
5226 ins_pipe(ialu_reg_mem);
5227 %}
5228
5229 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5230 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5231 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5232
5233 ins_cost(125);
5234 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5235 ins_encode %{
5236 __ movsbl($dst$$Register, $mem$$Address);
5237 %}
5238 ins_pipe(ialu_reg_mem);
5239 %}
5240
5241 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5242 instruct loadUS2L(rRegL dst, memory mem)
5243 %{
5244 match(Set dst (ConvI2L (LoadUS mem)));
5245
5246 ins_cost(125);
5247 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5248
5249 ins_encode %{
5250 __ movzwq($dst$$Register, $mem$$Address);
5251 %}
5252
5253 ins_pipe(ialu_reg_mem);
5254 %}
5255
5256 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5257 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5258 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5259
5260 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5261 ins_encode %{
5262 __ movzbq($dst$$Register, $mem$$Address);
5263 %}
5264 ins_pipe(ialu_reg_mem);
5265 %}
5266
5267 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
5268 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
5269 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5270 effect(KILL cr);
5271
5272 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5273 "andl $dst, $mask" %}
5274 ins_encode %{
5275 Register Rdst = $dst$$Register;
5276 __ movzwq(Rdst, $mem$$Address);
5277 __ andl(Rdst, $mask$$constant);
5278 %}
5279 ins_pipe(ialu_reg_mem);
5280 %}
5281
5282 // Load Integer
5283 instruct loadI(rRegI dst, memory mem)
5284 %{
5285 match(Set dst (LoadI mem));
5286
5287 ins_cost(125);
5288 format %{ "movl $dst, $mem\t# int" %}
5289
5290 ins_encode %{
5291 __ movl($dst$$Register, $mem$$Address);
5292 %}
5293
5294 ins_pipe(ialu_reg_mem);
5295 %}
5296
5297 // Load Integer (32 bit signed) to Byte (8 bit signed)
5298 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5299 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5300
5301 ins_cost(125);
5302 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5303 ins_encode %{
5304 __ movsbl($dst$$Register, $mem$$Address);
5305 %}
5306 ins_pipe(ialu_reg_mem);
5307 %}
5308
5309 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5310 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5311 match(Set dst (AndI (LoadI mem) mask));
5312
5313 ins_cost(125);
5314 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5315 ins_encode %{
5316 __ movzbl($dst$$Register, $mem$$Address);
5317 %}
5318 ins_pipe(ialu_reg_mem);
5319 %}
5320
5321 // Load Integer (32 bit signed) to Short (16 bit signed)
5322 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5323 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5324
5325 ins_cost(125);
5326 format %{ "movswl $dst, $mem\t# int -> short" %}
5327 ins_encode %{
5328 __ movswl($dst$$Register, $mem$$Address);
5329 %}
5330 ins_pipe(ialu_reg_mem);
5331 %}
5332
5333 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5334 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5335 match(Set dst (AndI (LoadI mem) mask));
5336
5337 ins_cost(125);
5338 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5339 ins_encode %{
5340 __ movzwl($dst$$Register, $mem$$Address);
5341 %}
5342 ins_pipe(ialu_reg_mem);
5343 %}
5344
5345 // Load Integer into Long Register
5346 instruct loadI2L(rRegL dst, memory mem)
5347 %{
5348 match(Set dst (ConvI2L (LoadI mem)));
5349
5350 ins_cost(125);
5351 format %{ "movslq $dst, $mem\t# int -> long" %}
5352
5353 ins_encode %{
5354 __ movslq($dst$$Register, $mem$$Address);
5355 %}
5356
5357 ins_pipe(ialu_reg_mem);
5358 %}
5359
5360 // Load Integer with mask 0xFF into Long Register
5361 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5362 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5363
5364 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5365 ins_encode %{
5366 __ movzbq($dst$$Register, $mem$$Address);
5367 %}
5368 ins_pipe(ialu_reg_mem);
5369 %}
5370
5371 // Load Integer with mask 0xFFFF into Long Register
5372 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5373 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5374
5375 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5376 ins_encode %{
5377 __ movzwq($dst$$Register, $mem$$Address);
5378 %}
5379 ins_pipe(ialu_reg_mem);
5380 %}
5381
5382 // Load Integer with a 32-bit mask into Long Register
5383 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5384 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5385 effect(KILL cr);
5386
5387 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
5388 "andl $dst, $mask" %}
5389 ins_encode %{
5390 Register Rdst = $dst$$Register;
5391 __ movl(Rdst, $mem$$Address);
5392 __ andl(Rdst, $mask$$constant);
5393 %}
5394 ins_pipe(ialu_reg_mem);
5395 %}
5396
5397 // Load Unsigned Integer into Long Register
5398 instruct loadUI2L(rRegL dst, memory mem)
5399 %{
5400 match(Set dst (LoadUI2L mem));
5401
5402 ins_cost(125);
5403 format %{ "movl $dst, $mem\t# uint -> long" %}
5404
5405 ins_encode %{
5406 __ movl($dst$$Register, $mem$$Address);
5407 %}
5408
5409 ins_pipe(ialu_reg_mem);
5410 %}
5411
5412 // Load Long
5413 instruct loadL(rRegL dst, memory mem)
5414 %{
5415 match(Set dst (LoadL mem));
5416
5417 ins_cost(125);
5418 format %{ "movq $dst, $mem\t# long" %}
5419
5420 ins_encode %{
5421 __ movq($dst$$Register, $mem$$Address);
5422 %}
5423
5424 ins_pipe(ialu_reg_mem); // XXX
5425 %}
5426
5427 // Load Range
5428 instruct loadRange(rRegI dst, memory mem)
5429 %{
5430 match(Set dst (LoadRange mem));
5431
5432 ins_cost(125); // XXX
5433 format %{ "movl $dst, $mem\t# range" %}
5434 opcode(0x8B);
5435 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5436 ins_pipe(ialu_reg_mem);
5437 %}
5438
5439 // Load Pointer
5440 instruct loadP(rRegP dst, memory mem)
5441 %{
5442 match(Set dst (LoadP mem));
5443
5444 ins_cost(125); // XXX
5445 format %{ "movq $dst, $mem\t# ptr" %}
5446 opcode(0x8B);
5447 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5448 ins_pipe(ialu_reg_mem); // XXX
5449 %}
5450
5451 // Load Compressed Pointer
5452 instruct loadN(rRegN dst, memory mem)
5453 %{
5454 match(Set dst (LoadN mem));
5455
5456 ins_cost(125); // XXX
5457 format %{ "movl $dst, $mem\t# compressed ptr" %}
5458 ins_encode %{
5459 __ movl($dst$$Register, $mem$$Address);
5460 %}
5461 ins_pipe(ialu_reg_mem); // XXX
5462 %}
5463
5464
5465 // Load Klass Pointer
5466 instruct loadKlass(rRegP dst, memory mem)
5467 %{
5468 match(Set dst (LoadKlass mem));
5469
5470 ins_cost(125); // XXX
5471 format %{ "movq $dst, $mem\t# class" %}
5472 opcode(0x8B);
5473 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5474 ins_pipe(ialu_reg_mem); // XXX
5475 %}
5476
5477 // Load narrow Klass Pointer
5478 instruct loadNKlass(rRegN dst, memory mem)
5479 %{
5480 match(Set dst (LoadNKlass mem));
5481
5482 ins_cost(125); // XXX
5483 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5484 ins_encode %{
5485 __ movl($dst$$Register, $mem$$Address);
5486 %}
5487 ins_pipe(ialu_reg_mem); // XXX
5488 %}
5489
5490 // Load Float
5491 instruct loadF(regF dst, memory mem)
5492 %{
5493 match(Set dst (LoadF mem));
5494
5495 ins_cost(145); // XXX
5496 format %{ "movss $dst, $mem\t# float" %}
5497 ins_encode %{
5498 __ movflt($dst$$XMMRegister, $mem$$Address);
5499 %}
5500 ins_pipe(pipe_slow); // XXX
5501 %}
5502
5503 // Load Double
5504 instruct loadD_partial(regD dst, memory mem)
5505 %{
5506 predicate(!UseXmmLoadAndClearUpper);
5507 match(Set dst (LoadD mem));
5508
5509 ins_cost(145); // XXX
5510 format %{ "movlpd $dst, $mem\t# double" %}
5511 ins_encode %{
5512 __ movdbl($dst$$XMMRegister, $mem$$Address);
5513 %}
5514 ins_pipe(pipe_slow); // XXX
5515 %}
5516
5517 instruct loadD(regD dst, memory mem)
5518 %{
5519 predicate(UseXmmLoadAndClearUpper);
5520 match(Set dst (LoadD mem));
5521
5522 ins_cost(145); // XXX
5523 format %{ "movsd $dst, $mem\t# double" %}
5524 ins_encode %{
5525 __ movdbl($dst$$XMMRegister, $mem$$Address);
5526 %}
5527 ins_pipe(pipe_slow); // XXX
5528 %}
5529
5530 // Load Aligned Packed Byte to XMM register
5531 instruct loadA8B(regD dst, memory mem) %{
5532 match(Set dst (Load8B mem));
5533 ins_cost(125);
5534 format %{ "MOVQ $dst,$mem\t! packed8B" %}
5535 ins_encode %{
5536 __ movq($dst$$XMMRegister, $mem$$Address);
5537 %}
5538 ins_pipe( pipe_slow );
5539 %}
5540
5541 // Load Aligned Packed Short to XMM register
5542 instruct loadA4S(regD dst, memory mem) %{
5543 match(Set dst (Load4S mem));
5544 ins_cost(125);
5545 format %{ "MOVQ $dst,$mem\t! packed4S" %}
5546 ins_encode %{
5547 __ movq($dst$$XMMRegister, $mem$$Address);
5548 %}
5549 ins_pipe( pipe_slow );
5550 %}
5551
5552 // Load Aligned Packed Char to XMM register
5553 instruct loadA4C(regD dst, memory mem) %{
5554 match(Set dst (Load4C mem));
5555 ins_cost(125);
5556 format %{ "MOVQ $dst,$mem\t! packed4C" %}
5557 ins_encode %{
5558 __ movq($dst$$XMMRegister, $mem$$Address);
5559 %}
5560 ins_pipe( pipe_slow );
5561 %}
5562
5563 // Load Aligned Packed Integer to XMM register
5564 instruct load2IU(regD dst, memory mem) %{
5565 match(Set dst (Load2I mem));
5566 ins_cost(125);
5567 format %{ "MOVQ $dst,$mem\t! packed2I" %}
5568 ins_encode %{
5569 __ movq($dst$$XMMRegister, $mem$$Address);
5570 %}
5571 ins_pipe( pipe_slow );
5572 %}
5573
5574 // Load Aligned Packed Single to XMM
5575 instruct loadA2F(regD dst, memory mem) %{
5576 match(Set dst (Load2F mem));
5577 ins_cost(125);
5578 format %{ "MOVQ $dst,$mem\t! packed2F" %}
5579 ins_encode %{
5580 __ movq($dst$$XMMRegister, $mem$$Address);
5581 %}
5582 ins_pipe( pipe_slow );
5583 %}
5584
5585 // Load Effective Address
5586 instruct leaP8(rRegP dst, indOffset8 mem)
5587 %{
5588 match(Set dst mem);
5589
5590 ins_cost(110); // XXX
5591 format %{ "leaq $dst, $mem\t# ptr 8" %}
5592 opcode(0x8D);
5593 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5594 ins_pipe(ialu_reg_reg_fat);
5595 %}
5596
5597 instruct leaP32(rRegP dst, indOffset32 mem)
5598 %{
5599 match(Set dst mem);
5600
5601 ins_cost(110);
5602 format %{ "leaq $dst, $mem\t# ptr 32" %}
5603 opcode(0x8D);
5604 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5605 ins_pipe(ialu_reg_reg_fat);
5606 %}
5607
5608 // instruct leaPIdx(rRegP dst, indIndex mem)
5609 // %{
5610 // match(Set dst mem);
5611
5612 // ins_cost(110);
5613 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5614 // opcode(0x8D);
5615 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5616 // ins_pipe(ialu_reg_reg_fat);
5617 // %}
5618
5619 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5620 %{
5621 match(Set dst mem);
5622
5623 ins_cost(110);
5624 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5625 opcode(0x8D);
5626 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5627 ins_pipe(ialu_reg_reg_fat);
5628 %}
5629
5630 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5631 %{
5632 match(Set dst mem);
5633
5634 ins_cost(110);
5635 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5636 opcode(0x8D);
5637 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5638 ins_pipe(ialu_reg_reg_fat);
5639 %}
5640
5641 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5642 %{
5643 match(Set dst mem);
5644
5645 ins_cost(110);
5646 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5647 opcode(0x8D);
5648 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5649 ins_pipe(ialu_reg_reg_fat);
5650 %}
5651
5652 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5653 %{
5654 match(Set dst mem);
5655
5656 ins_cost(110);
5657 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5658 opcode(0x8D);
5659 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5660 ins_pipe(ialu_reg_reg_fat);
5661 %}
5662
5663 // Load Effective Address which uses Narrow (32-bits) oop
5664 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5665 %{
5666 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5667 match(Set dst mem);
5668
5669 ins_cost(110);
5670 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5671 opcode(0x8D);
5672 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5673 ins_pipe(ialu_reg_reg_fat);
5674 %}
5675
5676 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5677 %{
5678 predicate(Universe::narrow_oop_shift() == 0);
5679 match(Set dst mem);
5680
5681 ins_cost(110); // XXX
5682 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5683 opcode(0x8D);
5684 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5685 ins_pipe(ialu_reg_reg_fat);
5686 %}
5687
5688 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5689 %{
5690 predicate(Universe::narrow_oop_shift() == 0);
5691 match(Set dst mem);
5692
5693 ins_cost(110);
5694 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5695 opcode(0x8D);
5696 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5697 ins_pipe(ialu_reg_reg_fat);
5698 %}
5699
5700 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5701 %{
5702 predicate(Universe::narrow_oop_shift() == 0);
5703 match(Set dst mem);
5704
5705 ins_cost(110);
5706 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5707 opcode(0x8D);
5708 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5709 ins_pipe(ialu_reg_reg_fat);
5710 %}
5711
5712 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5713 %{
5714 predicate(Universe::narrow_oop_shift() == 0);
5715 match(Set dst mem);
5716
5717 ins_cost(110);
5718 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5719 opcode(0x8D);
5720 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5721 ins_pipe(ialu_reg_reg_fat);
5722 %}
5723
5724 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5725 %{
5726 predicate(Universe::narrow_oop_shift() == 0);
5727 match(Set dst mem);
5728
5729 ins_cost(110);
5730 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5731 opcode(0x8D);
5732 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5733 ins_pipe(ialu_reg_reg_fat);
5734 %}
5735
5736 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5737 %{
5738 predicate(Universe::narrow_oop_shift() == 0);
5739 match(Set dst mem);
5740
5741 ins_cost(110);
5742 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5743 opcode(0x8D);
5744 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5745 ins_pipe(ialu_reg_reg_fat);
5746 %}
5747
5748 instruct loadConI(rRegI dst, immI src)
5749 %{
5750 match(Set dst src);
5751
5752 format %{ "movl $dst, $src\t# int" %}
5753 ins_encode(load_immI(dst, src));
5754 ins_pipe(ialu_reg_fat); // XXX
5755 %}
5756
5757 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5758 %{
5759 match(Set dst src);
5760 effect(KILL cr);
5761
5762 ins_cost(50);
5763 format %{ "xorl $dst, $dst\t# int" %}
5764 opcode(0x33); /* + rd */
5765 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 instruct loadConL(rRegL dst, immL src)
5770 %{
5771 match(Set dst src);
5772
5773 ins_cost(150);
5774 format %{ "movq $dst, $src\t# long" %}
5775 ins_encode(load_immL(dst, src));
5776 ins_pipe(ialu_reg);
5777 %}
5778
5779 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5780 %{
5781 match(Set dst src);
5782 effect(KILL cr);
5783
5784 ins_cost(50);
5785 format %{ "xorl $dst, $dst\t# long" %}
5786 opcode(0x33); /* + rd */
5787 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5788 ins_pipe(ialu_reg); // XXX
5789 %}
5790
5791 instruct loadConUL32(rRegL dst, immUL32 src)
5792 %{
5793 match(Set dst src);
5794
5795 ins_cost(60);
5796 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5797 ins_encode(load_immUL32(dst, src));
5798 ins_pipe(ialu_reg);
5799 %}
5800
5801 instruct loadConL32(rRegL dst, immL32 src)
5802 %{
5803 match(Set dst src);
5804
5805 ins_cost(70);
5806 format %{ "movq $dst, $src\t# long (32-bit)" %}
5807 ins_encode(load_immL32(dst, src));
5808 ins_pipe(ialu_reg);
5809 %}
5810
5811 instruct loadConP(rRegP dst, immP con) %{
5812 match(Set dst con);
5813
5814 format %{ "movq $dst, $con\t# ptr" %}
5815 ins_encode(load_immP(dst, con));
5816 ins_pipe(ialu_reg_fat); // XXX
5817 %}
5818
5819 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5820 %{
5821 match(Set dst src);
5822 effect(KILL cr);
5823
5824 ins_cost(50);
5825 format %{ "xorl $dst, $dst\t# ptr" %}
5826 opcode(0x33); /* + rd */
5827 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5828 ins_pipe(ialu_reg);
5829 %}
5830
5831 instruct loadConP_poll(rRegP dst, immP_poll src) %{
5832 match(Set dst src);
5833 format %{ "movq $dst, $src\t!ptr" %}
5834 ins_encode %{
5835 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
5836 __ lea($dst$$Register, polling_page);
5837 %}
5838 ins_pipe(ialu_reg_fat);
5839 %}
5840
5841 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5842 %{
5843 match(Set dst src);
5844 effect(KILL cr);
5845
5846 ins_cost(60);
5847 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5848 ins_encode(load_immP31(dst, src));
5849 ins_pipe(ialu_reg);
5850 %}
5851
5852 instruct loadConF(regF dst, immF con) %{
5853 match(Set dst con);
5854 ins_cost(125);
5855 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5856 ins_encode %{
5857 __ movflt($dst$$XMMRegister, $constantaddress($con));
5858 %}
5859 ins_pipe(pipe_slow);
5860 %}
5861
5862 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5863 match(Set dst src);
5864 effect(KILL cr);
5865 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5866 ins_encode %{
5867 __ xorq($dst$$Register, $dst$$Register);
5868 %}
5869 ins_pipe(ialu_reg);
5870 %}
5871
5872 instruct loadConN(rRegN dst, immN src) %{
5873 match(Set dst src);
5874
5875 ins_cost(125);
5876 format %{ "movl $dst, $src\t# compressed ptr" %}
5877 ins_encode %{
5878 address con = (address)$src$$constant;
5879 if (con == NULL) {
5880 ShouldNotReachHere();
5881 } else {
5882 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5883 }
5884 %}
5885 ins_pipe(ialu_reg_fat); // XXX
5886 %}
5887
5888 instruct loadConF0(regF dst, immF0 src)
5889 %{
5890 match(Set dst src);
5891 ins_cost(100);
5892
5893 format %{ "xorps $dst, $dst\t# float 0.0" %}
5894 ins_encode %{
5895 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5896 %}
5897 ins_pipe(pipe_slow);
5898 %}
5899
5900 // Use the same format since predicate() can not be used here.
5901 instruct loadConD(regD dst, immD con) %{
5902 match(Set dst con);
5903 ins_cost(125);
5904 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5905 ins_encode %{
5906 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5907 %}
5908 ins_pipe(pipe_slow);
5909 %}
5910
5911 instruct loadConD0(regD dst, immD0 src)
5912 %{
5913 match(Set dst src);
5914 ins_cost(100);
5915
5916 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5917 ins_encode %{
5918 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5919 %}
5920 ins_pipe(pipe_slow);
5921 %}
5922
5923 instruct loadSSI(rRegI dst, stackSlotI src)
5924 %{
5925 match(Set dst src);
5926
5927 ins_cost(125);
5928 format %{ "movl $dst, $src\t# int stk" %}
5929 opcode(0x8B);
5930 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5931 ins_pipe(ialu_reg_mem);
5932 %}
5933
5934 instruct loadSSL(rRegL dst, stackSlotL src)
5935 %{
5936 match(Set dst src);
5937
5938 ins_cost(125);
5939 format %{ "movq $dst, $src\t# long stk" %}
5940 opcode(0x8B);
5941 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5942 ins_pipe(ialu_reg_mem);
5943 %}
5944
5945 instruct loadSSP(rRegP dst, stackSlotP src)
5946 %{
5947 match(Set dst src);
5948
5949 ins_cost(125);
5950 format %{ "movq $dst, $src\t# ptr stk" %}
5951 opcode(0x8B);
5952 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5953 ins_pipe(ialu_reg_mem);
5954 %}
5955
5956 instruct loadSSF(regF dst, stackSlotF src)
5957 %{
5958 match(Set dst src);
5959
5960 ins_cost(125);
5961 format %{ "movss $dst, $src\t# float stk" %}
5962 ins_encode %{
5963 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5964 %}
5965 ins_pipe(pipe_slow); // XXX
5966 %}
5967
5968 // Use the same format since predicate() can not be used here.
5969 instruct loadSSD(regD dst, stackSlotD src)
5970 %{
5971 match(Set dst src);
5972
5973 ins_cost(125);
5974 format %{ "movsd $dst, $src\t# double stk" %}
5975 ins_encode %{
5976 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5977 %}
5978 ins_pipe(pipe_slow); // XXX
5979 %}
5980
5981 // Prefetch instructions.
5982 // Must be safe to execute with invalid address (cannot fault).
5983
5984 instruct prefetchr( memory mem ) %{
5985 predicate(ReadPrefetchInstr==3);
5986 match(PrefetchRead mem);
5987 ins_cost(125);
5988
5989 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5990 ins_encode %{
5991 __ prefetchr($mem$$Address);
5992 %}
5993 ins_pipe(ialu_mem);
5994 %}
5995
5996 instruct prefetchrNTA( memory mem ) %{
5997 predicate(ReadPrefetchInstr==0);
5998 match(PrefetchRead mem);
5999 ins_cost(125);
6000
6001 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6002 ins_encode %{
6003 __ prefetchnta($mem$$Address);
6004 %}
6005 ins_pipe(ialu_mem);
6006 %}
6007
6008 instruct prefetchrT0( memory mem ) %{
6009 predicate(ReadPrefetchInstr==1);
6010 match(PrefetchRead mem);
6011 ins_cost(125);
6012
6013 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6014 ins_encode %{
6015 __ prefetcht0($mem$$Address);
6016 %}
6017 ins_pipe(ialu_mem);
6018 %}
6019
6020 instruct prefetchrT2( memory mem ) %{
6021 predicate(ReadPrefetchInstr==2);
6022 match(PrefetchRead mem);
6023 ins_cost(125);
6024
6025 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6026 ins_encode %{
6027 __ prefetcht2($mem$$Address);
6028 %}
6029 ins_pipe(ialu_mem);
6030 %}
6031
6032 instruct prefetchwNTA( memory mem ) %{
6033 match(PrefetchWrite mem);
6034 ins_cost(125);
6035
6036 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6037 ins_encode %{
6038 __ prefetchnta($mem$$Address);
6039 %}
6040 ins_pipe(ialu_mem);
6041 %}
6042
6043 // Prefetch instructions for allocation.
6044
6045 instruct prefetchAlloc( memory mem ) %{
6046 predicate(AllocatePrefetchInstr==3);
6047 match(PrefetchAllocation mem);
6048 ins_cost(125);
6049
6050 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6051 ins_encode %{
6052 __ prefetchw($mem$$Address);
6053 %}
6054 ins_pipe(ialu_mem);
6055 %}
6056
6057 instruct prefetchAllocNTA( memory mem ) %{
6058 predicate(AllocatePrefetchInstr==0);
6059 match(PrefetchAllocation mem);
6060 ins_cost(125);
6061
6062 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6063 ins_encode %{
6064 __ prefetchnta($mem$$Address);
6065 %}
6066 ins_pipe(ialu_mem);
6067 %}
6068
6069 instruct prefetchAllocT0( memory mem ) %{
6070 predicate(AllocatePrefetchInstr==1);
6071 match(PrefetchAllocation mem);
6072 ins_cost(125);
6073
6074 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6075 ins_encode %{
6076 __ prefetcht0($mem$$Address);
6077 %}
6078 ins_pipe(ialu_mem);
6079 %}
6080
6081 instruct prefetchAllocT2( memory mem ) %{
6082 predicate(AllocatePrefetchInstr==2);
6083 match(PrefetchAllocation mem);
6084 ins_cost(125);
6085
6086 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6087 ins_encode %{
6088 __ prefetcht2($mem$$Address);
6089 %}
6090 ins_pipe(ialu_mem);
6091 %}
6092
6093 //----------Store Instructions-------------------------------------------------
6094
6095 // Store Byte
6096 instruct storeB(memory mem, rRegI src)
6097 %{
6098 match(Set mem (StoreB mem src));
6099
6100 ins_cost(125); // XXX
6101 format %{ "movb $mem, $src\t# byte" %}
6102 opcode(0x88);
6103 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6104 ins_pipe(ialu_mem_reg);
6105 %}
6106
6107 // Store Char/Short
6108 instruct storeC(memory mem, rRegI src)
6109 %{
6110 match(Set mem (StoreC mem src));
6111
6112 ins_cost(125); // XXX
6113 format %{ "movw $mem, $src\t# char/short" %}
6114 opcode(0x89);
6115 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6116 ins_pipe(ialu_mem_reg);
6117 %}
6118
6119 // Store Integer
6120 instruct storeI(memory mem, rRegI src)
6121 %{
6122 match(Set mem (StoreI mem src));
6123
6124 ins_cost(125); // XXX
6125 format %{ "movl $mem, $src\t# int" %}
6126 opcode(0x89);
6127 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6128 ins_pipe(ialu_mem_reg);
6129 %}
6130
6131 // Store Long
6132 instruct storeL(memory mem, rRegL src)
6133 %{
6134 match(Set mem (StoreL mem src));
6135
6136 ins_cost(125); // XXX
6137 format %{ "movq $mem, $src\t# long" %}
6138 opcode(0x89);
6139 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6140 ins_pipe(ialu_mem_reg); // XXX
6141 %}
6142
6143 // Store Pointer
6144 instruct storeP(memory mem, any_RegP src)
6145 %{
6146 match(Set mem (StoreP mem src));
6147
6148 ins_cost(125); // XXX
6149 format %{ "movq $mem, $src\t# ptr" %}
6150 opcode(0x89);
6151 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6152 ins_pipe(ialu_mem_reg);
6153 %}
6154
6155 instruct storeImmP0(memory mem, immP0 zero)
6156 %{
6157 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6158 match(Set mem (StoreP mem zero));
6159
6160 ins_cost(125); // XXX
6161 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6162 ins_encode %{
6163 __ movq($mem$$Address, r12);
6164 %}
6165 ins_pipe(ialu_mem_reg);
6166 %}
6167
6168 // Store NULL Pointer, mark word, or other simple pointer constant.
6169 instruct storeImmP(memory mem, immP31 src)
6170 %{
6171 match(Set mem (StoreP mem src));
6172
6173 ins_cost(150); // XXX
6174 format %{ "movq $mem, $src\t# ptr" %}
6175 opcode(0xC7); /* C7 /0 */
6176 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6177 ins_pipe(ialu_mem_imm);
6178 %}
6179
6180 // Store Compressed Pointer
6181 instruct storeN(memory mem, rRegN src)
6182 %{
6183 match(Set mem (StoreN mem src));
6184
6185 ins_cost(125); // XXX
6186 format %{ "movl $mem, $src\t# compressed ptr" %}
6187 ins_encode %{
6188 __ movl($mem$$Address, $src$$Register);
6189 %}
6190 ins_pipe(ialu_mem_reg);
6191 %}
6192
6193 instruct storeImmN0(memory mem, immN0 zero)
6194 %{
6195 predicate(Universe::narrow_oop_base() == NULL);
6196 match(Set mem (StoreN mem zero));
6197
6198 ins_cost(125); // XXX
6199 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6200 ins_encode %{
6201 __ movl($mem$$Address, r12);
6202 %}
6203 ins_pipe(ialu_mem_reg);
6204 %}
6205
6206 instruct storeImmN(memory mem, immN src)
6207 %{
6208 match(Set mem (StoreN mem src));
6209
6210 ins_cost(150); // XXX
6211 format %{ "movl $mem, $src\t# compressed ptr" %}
6212 ins_encode %{
6213 address con = (address)$src$$constant;
6214 if (con == NULL) {
6215 __ movl($mem$$Address, (int32_t)0);
6216 } else {
6217 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6218 }
6219 %}
6220 ins_pipe(ialu_mem_imm);
6221 %}
6222
6223 // Store Integer Immediate
6224 instruct storeImmI0(memory mem, immI0 zero)
6225 %{
6226 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6227 match(Set mem (StoreI mem zero));
6228
6229 ins_cost(125); // XXX
6230 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6231 ins_encode %{
6232 __ movl($mem$$Address, r12);
6233 %}
6234 ins_pipe(ialu_mem_reg);
6235 %}
6236
6237 instruct storeImmI(memory mem, immI src)
6238 %{
6239 match(Set mem (StoreI mem src));
6240
6241 ins_cost(150);
6242 format %{ "movl $mem, $src\t# int" %}
6243 opcode(0xC7); /* C7 /0 */
6244 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6245 ins_pipe(ialu_mem_imm);
6246 %}
6247
6248 // Store Long Immediate
6249 instruct storeImmL0(memory mem, immL0 zero)
6250 %{
6251 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6252 match(Set mem (StoreL mem zero));
6253
6254 ins_cost(125); // XXX
6255 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6256 ins_encode %{
6257 __ movq($mem$$Address, r12);
6258 %}
6259 ins_pipe(ialu_mem_reg);
6260 %}
6261
6262 instruct storeImmL(memory mem, immL32 src)
6263 %{
6264 match(Set mem (StoreL mem src));
6265
6266 ins_cost(150);
6267 format %{ "movq $mem, $src\t# long" %}
6268 opcode(0xC7); /* C7 /0 */
6269 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6270 ins_pipe(ialu_mem_imm);
6271 %}
6272
6273 // Store Short/Char Immediate
6274 instruct storeImmC0(memory mem, immI0 zero)
6275 %{
6276 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6277 match(Set mem (StoreC mem zero));
6278
6279 ins_cost(125); // XXX
6280 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6281 ins_encode %{
6282 __ movw($mem$$Address, r12);
6283 %}
6284 ins_pipe(ialu_mem_reg);
6285 %}
6286
6287 instruct storeImmI16(memory mem, immI16 src)
6288 %{
6289 predicate(UseStoreImmI16);
6290 match(Set mem (StoreC mem src));
6291
6292 ins_cost(150);
6293 format %{ "movw $mem, $src\t# short/char" %}
6294 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6295 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6296 ins_pipe(ialu_mem_imm);
6297 %}
6298
6299 // Store Byte Immediate
6300 instruct storeImmB0(memory mem, immI0 zero)
6301 %{
6302 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6303 match(Set mem (StoreB mem zero));
6304
6305 ins_cost(125); // XXX
6306 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6307 ins_encode %{
6308 __ movb($mem$$Address, r12);
6309 %}
6310 ins_pipe(ialu_mem_reg);
6311 %}
6312
6313 instruct storeImmB(memory mem, immI8 src)
6314 %{
6315 match(Set mem (StoreB mem src));
6316
6317 ins_cost(150); // XXX
6318 format %{ "movb $mem, $src\t# byte" %}
6319 opcode(0xC6); /* C6 /0 */
6320 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6321 ins_pipe(ialu_mem_imm);
6322 %}
6323
6324 // Store Aligned Packed Byte XMM register to memory
6325 instruct storeA8B(memory mem, regD src) %{
6326 match(Set mem (Store8B mem src));
6327 ins_cost(145);
6328 format %{ "MOVQ $mem,$src\t! packed8B" %}
6329 ins_encode %{
6330 __ movq($mem$$Address, $src$$XMMRegister);
6331 %}
6332 ins_pipe( pipe_slow );
6333 %}
6334
6335 // Store Aligned Packed Char/Short XMM register to memory
6336 instruct storeA4C(memory mem, regD src) %{
6337 match(Set mem (Store4C mem src));
6338 ins_cost(145);
6339 format %{ "MOVQ $mem,$src\t! packed4C" %}
6340 ins_encode %{
6341 __ movq($mem$$Address, $src$$XMMRegister);
6342 %}
6343 ins_pipe( pipe_slow );
6344 %}
6345
6346 // Store Aligned Packed Integer XMM register to memory
6347 instruct storeA2I(memory mem, regD src) %{
6348 match(Set mem (Store2I mem src));
6349 ins_cost(145);
6350 format %{ "MOVQ $mem,$src\t! packed2I" %}
6351 ins_encode %{
6352 __ movq($mem$$Address, $src$$XMMRegister);
6353 %}
6354 ins_pipe( pipe_slow );
6355 %}
6356
6357 // Store CMS card-mark Immediate
6358 instruct storeImmCM0_reg(memory mem, immI0 zero)
6359 %{
6360 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6361 match(Set mem (StoreCM mem zero));
6362
6363 ins_cost(125); // XXX
6364 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6365 ins_encode %{
6366 __ movb($mem$$Address, r12);
6367 %}
6368 ins_pipe(ialu_mem_reg);
6369 %}
6370
6371 instruct storeImmCM0(memory mem, immI0 src)
6372 %{
6373 match(Set mem (StoreCM mem src));
6374
6375 ins_cost(150); // XXX
6376 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6377 opcode(0xC6); /* C6 /0 */
6378 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6379 ins_pipe(ialu_mem_imm);
6380 %}
6381
6382 // Store Aligned Packed Single Float XMM register to memory
6383 instruct storeA2F(memory mem, regD src) %{
6384 match(Set mem (Store2F mem src));
6385 ins_cost(145);
6386 format %{ "MOVQ $mem,$src\t! packed2F" %}
6387 ins_encode %{
6388 __ movq($mem$$Address, $src$$XMMRegister);
6389 %}
6390 ins_pipe( pipe_slow );
6391 %}
6392
6393 // Store Float
6394 instruct storeF(memory mem, regF src)
6395 %{
6396 match(Set mem (StoreF mem src));
6397
6398 ins_cost(95); // XXX
6399 format %{ "movss $mem, $src\t# float" %}
6400 ins_encode %{
6401 __ movflt($mem$$Address, $src$$XMMRegister);
6402 %}
6403 ins_pipe(pipe_slow); // XXX
6404 %}
6405
6406 // Store immediate Float value (it is faster than store from XMM register)
6407 instruct storeF0(memory mem, immF0 zero)
6408 %{
6409 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6410 match(Set mem (StoreF mem zero));
6411
6412 ins_cost(25); // XXX
6413 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6414 ins_encode %{
6415 __ movl($mem$$Address, r12);
6416 %}
6417 ins_pipe(ialu_mem_reg);
6418 %}
6419
6420 instruct storeF_imm(memory mem, immF src)
6421 %{
6422 match(Set mem (StoreF mem src));
6423
6424 ins_cost(50);
6425 format %{ "movl $mem, $src\t# float" %}
6426 opcode(0xC7); /* C7 /0 */
6427 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6428 ins_pipe(ialu_mem_imm);
6429 %}
6430
6431 // Store Double
6432 instruct storeD(memory mem, regD src)
6433 %{
6434 match(Set mem (StoreD mem src));
6435
6436 ins_cost(95); // XXX
6437 format %{ "movsd $mem, $src\t# double" %}
6438 ins_encode %{
6439 __ movdbl($mem$$Address, $src$$XMMRegister);
6440 %}
6441 ins_pipe(pipe_slow); // XXX
6442 %}
6443
6444 // Store immediate double 0.0 (it is faster than store from XMM register)
6445 instruct storeD0_imm(memory mem, immD0 src)
6446 %{
6447 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6448 match(Set mem (StoreD mem src));
6449
6450 ins_cost(50);
6451 format %{ "movq $mem, $src\t# double 0." %}
6452 opcode(0xC7); /* C7 /0 */
6453 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6454 ins_pipe(ialu_mem_imm);
6455 %}
6456
6457 instruct storeD0(memory mem, immD0 zero)
6458 %{
6459 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6460 match(Set mem (StoreD mem zero));
6461
6462 ins_cost(25); // XXX
6463 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6464 ins_encode %{
6465 __ movq($mem$$Address, r12);
6466 %}
6467 ins_pipe(ialu_mem_reg);
6468 %}
6469
6470 instruct storeSSI(stackSlotI dst, rRegI src)
6471 %{
6472 match(Set dst src);
6473
6474 ins_cost(100);
6475 format %{ "movl $dst, $src\t# int stk" %}
6476 opcode(0x89);
6477 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6478 ins_pipe( ialu_mem_reg );
6479 %}
6480
6481 instruct storeSSL(stackSlotL dst, rRegL src)
6482 %{
6483 match(Set dst src);
6484
6485 ins_cost(100);
6486 format %{ "movq $dst, $src\t# long stk" %}
6487 opcode(0x89);
6488 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6489 ins_pipe(ialu_mem_reg);
6490 %}
6491
6492 instruct storeSSP(stackSlotP dst, rRegP src)
6493 %{
6494 match(Set dst src);
6495
6496 ins_cost(100);
6497 format %{ "movq $dst, $src\t# ptr stk" %}
6498 opcode(0x89);
6499 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6500 ins_pipe(ialu_mem_reg);
6501 %}
6502
6503 instruct storeSSF(stackSlotF dst, regF src)
6504 %{
6505 match(Set dst src);
6506
6507 ins_cost(95); // XXX
6508 format %{ "movss $dst, $src\t# float stk" %}
6509 ins_encode %{
6510 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6511 %}
6512 ins_pipe(pipe_slow); // XXX
6513 %}
6514
6515 instruct storeSSD(stackSlotD dst, regD src)
6516 %{
6517 match(Set dst src);
6518
6519 ins_cost(95); // XXX
6520 format %{ "movsd $dst, $src\t# double stk" %}
6521 ins_encode %{
6522 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6523 %}
6524 ins_pipe(pipe_slow); // XXX
6525 %}
6526
6527 //----------BSWAP Instructions-------------------------------------------------
6528 instruct bytes_reverse_int(rRegI dst) %{
6529 match(Set dst (ReverseBytesI dst));
6530
6531 format %{ "bswapl $dst" %}
6532 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6533 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6534 ins_pipe( ialu_reg );
6535 %}
6536
6537 instruct bytes_reverse_long(rRegL dst) %{
6538 match(Set dst (ReverseBytesL dst));
6539
6540 format %{ "bswapq $dst" %}
6541
6542 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6543 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6544 ins_pipe( ialu_reg);
6545 %}
6546
6547 instruct bytes_reverse_unsigned_short(rRegI dst) %{
6548 match(Set dst (ReverseBytesUS dst));
6549
6550 format %{ "bswapl $dst\n\t"
6551 "shrl $dst,16\n\t" %}
6552 ins_encode %{
6553 __ bswapl($dst$$Register);
6554 __ shrl($dst$$Register, 16);
6555 %}
6556 ins_pipe( ialu_reg );
6557 %}
6558
6559 instruct bytes_reverse_short(rRegI dst) %{
6560 match(Set dst (ReverseBytesS dst));
6561
6562 format %{ "bswapl $dst\n\t"
6563 "sar $dst,16\n\t" %}
6564 ins_encode %{
6565 __ bswapl($dst$$Register);
6566 __ sarl($dst$$Register, 16);
6567 %}
6568 ins_pipe( ialu_reg );
6569 %}
6570
6571 //---------- Zeros Count Instructions ------------------------------------------
6572
6573 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6574 predicate(UseCountLeadingZerosInstruction);
6575 match(Set dst (CountLeadingZerosI src));
6576 effect(KILL cr);
6577
6578 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6579 ins_encode %{
6580 __ lzcntl($dst$$Register, $src$$Register);
6581 %}
6582 ins_pipe(ialu_reg);
6583 %}
6584
6585 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6586 predicate(!UseCountLeadingZerosInstruction);
6587 match(Set dst (CountLeadingZerosI src));
6588 effect(KILL cr);
6589
6590 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6591 "jnz skip\n\t"
6592 "movl $dst, -1\n"
6593 "skip:\n\t"
6594 "negl $dst\n\t"
6595 "addl $dst, 31" %}
6596 ins_encode %{
6597 Register Rdst = $dst$$Register;
6598 Register Rsrc = $src$$Register;
6599 Label skip;
6600 __ bsrl(Rdst, Rsrc);
6601 __ jccb(Assembler::notZero, skip);
6602 __ movl(Rdst, -1);
6603 __ bind(skip);
6604 __ negl(Rdst);
6605 __ addl(Rdst, BitsPerInt - 1);
6606 %}
6607 ins_pipe(ialu_reg);
6608 %}
6609
6610 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6611 predicate(UseCountLeadingZerosInstruction);
6612 match(Set dst (CountLeadingZerosL src));
6613 effect(KILL cr);
6614
6615 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6616 ins_encode %{
6617 __ lzcntq($dst$$Register, $src$$Register);
6618 %}
6619 ins_pipe(ialu_reg);
6620 %}
6621
6622 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6623 predicate(!UseCountLeadingZerosInstruction);
6624 match(Set dst (CountLeadingZerosL src));
6625 effect(KILL cr);
6626
6627 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6628 "jnz skip\n\t"
6629 "movl $dst, -1\n"
6630 "skip:\n\t"
6631 "negl $dst\n\t"
6632 "addl $dst, 63" %}
6633 ins_encode %{
6634 Register Rdst = $dst$$Register;
6635 Register Rsrc = $src$$Register;
6636 Label skip;
6637 __ bsrq(Rdst, Rsrc);
6638 __ jccb(Assembler::notZero, skip);
6639 __ movl(Rdst, -1);
6640 __ bind(skip);
6641 __ negl(Rdst);
6642 __ addl(Rdst, BitsPerLong - 1);
6643 %}
6644 ins_pipe(ialu_reg);
6645 %}
6646
6647 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6648 match(Set dst (CountTrailingZerosI src));
6649 effect(KILL cr);
6650
6651 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6652 "jnz done\n\t"
6653 "movl $dst, 32\n"
6654 "done:" %}
6655 ins_encode %{
6656 Register Rdst = $dst$$Register;
6657 Label done;
6658 __ bsfl(Rdst, $src$$Register);
6659 __ jccb(Assembler::notZero, done);
6660 __ movl(Rdst, BitsPerInt);
6661 __ bind(done);
6662 %}
6663 ins_pipe(ialu_reg);
6664 %}
6665
6666 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6667 match(Set dst (CountTrailingZerosL src));
6668 effect(KILL cr);
6669
6670 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6671 "jnz done\n\t"
6672 "movl $dst, 64\n"
6673 "done:" %}
6674 ins_encode %{
6675 Register Rdst = $dst$$Register;
6676 Label done;
6677 __ bsfq(Rdst, $src$$Register);
6678 __ jccb(Assembler::notZero, done);
6679 __ movl(Rdst, BitsPerLong);
6680 __ bind(done);
6681 %}
6682 ins_pipe(ialu_reg);
6683 %}
6684
6685
6686 //---------- Population Count Instructions -------------------------------------
6687
6688 instruct popCountI(rRegI dst, rRegI src) %{
6689 predicate(UsePopCountInstruction);
6690 match(Set dst (PopCountI src));
6691
6692 format %{ "popcnt $dst, $src" %}
6693 ins_encode %{
6694 __ popcntl($dst$$Register, $src$$Register);
6695 %}
6696 ins_pipe(ialu_reg);
6697 %}
6698
6699 instruct popCountI_mem(rRegI dst, memory mem) %{
6700 predicate(UsePopCountInstruction);
6701 match(Set dst (PopCountI (LoadI mem)));
6702
6703 format %{ "popcnt $dst, $mem" %}
6704 ins_encode %{
6705 __ popcntl($dst$$Register, $mem$$Address);
6706 %}
6707 ins_pipe(ialu_reg);
6708 %}
6709
6710 // Note: Long.bitCount(long) returns an int.
6711 instruct popCountL(rRegI dst, rRegL src) %{
6712 predicate(UsePopCountInstruction);
6713 match(Set dst (PopCountL src));
6714
6715 format %{ "popcnt $dst, $src" %}
6716 ins_encode %{
6717 __ popcntq($dst$$Register, $src$$Register);
6718 %}
6719 ins_pipe(ialu_reg);
6720 %}
6721
6722 // Note: Long.bitCount(long) returns an int.
6723 instruct popCountL_mem(rRegI dst, memory mem) %{
6724 predicate(UsePopCountInstruction);
6725 match(Set dst (PopCountL (LoadL mem)));
6726
6727 format %{ "popcnt $dst, $mem" %}
6728 ins_encode %{
6729 __ popcntq($dst$$Register, $mem$$Address);
6730 %}
6731 ins_pipe(ialu_reg);
6732 %}
6733
6734
6735 //----------MemBar Instructions-----------------------------------------------
6736 // Memory barrier flavors
6737
6738 instruct membar_acquire()
6739 %{
6740 match(MemBarAcquire);
6741 ins_cost(0);
6742
6743 size(0);
6744 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6745 ins_encode();
6746 ins_pipe(empty);
6747 %}
6748
6749 instruct membar_acquire_lock()
6750 %{
6751 match(MemBarAcquireLock);
6752 ins_cost(0);
6753
6754 size(0);
6755 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6756 ins_encode();
6757 ins_pipe(empty);
6758 %}
6759
6760 instruct membar_release()
6761 %{
6762 match(MemBarRelease);
6763 ins_cost(0);
6764
6765 size(0);
6766 format %{ "MEMBAR-release ! (empty encoding)" %}
6767 ins_encode();
6768 ins_pipe(empty);
6769 %}
6770
6771 instruct membar_release_lock()
6772 %{
6773 match(MemBarReleaseLock);
6774 ins_cost(0);
6775
6776 size(0);
6777 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6778 ins_encode();
6779 ins_pipe(empty);
6780 %}
6781
6782 instruct membar_volatile(rFlagsReg cr) %{
6783 match(MemBarVolatile);
6784 effect(KILL cr);
6785 ins_cost(400);
6786
6787 format %{
6788 $$template
6789 if (os::is_MP()) {
6790 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6791 } else {
6792 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6793 }
6794 %}
6795 ins_encode %{
6796 __ membar(Assembler::StoreLoad);
6797 %}
6798 ins_pipe(pipe_slow);
6799 %}
6800
6801 instruct unnecessary_membar_volatile()
6802 %{
6803 match(MemBarVolatile);
6804 predicate(Matcher::post_store_load_barrier(n));
6805 ins_cost(0);
6806
6807 size(0);
6808 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6809 ins_encode();
6810 ins_pipe(empty);
6811 %}
6812
6813 instruct membar_storestore() %{
6814 match(MemBarStoreStore);
6815 ins_cost(0);
6816
6817 size(0);
6818 format %{ "MEMBAR-storestore (empty encoding)" %}
6819 ins_encode( );
6820 ins_pipe(empty);
6821 %}
6822
6823 //----------Move Instructions--------------------------------------------------
6824
6825 instruct castX2P(rRegP dst, rRegL src)
6826 %{
6827 match(Set dst (CastX2P src));
6828
6829 format %{ "movq $dst, $src\t# long->ptr" %}
6830 ins_encode %{
6831 if ($dst$$reg != $src$$reg) {
6832 __ movptr($dst$$Register, $src$$Register);
6833 }
6834 %}
6835 ins_pipe(ialu_reg_reg); // XXX
6836 %}
6837
6838 instruct castP2X(rRegL dst, rRegP src)
6839 %{
6840 match(Set dst (CastP2X src));
6841
6842 format %{ "movq $dst, $src\t# ptr -> long" %}
6843 ins_encode %{
6844 if ($dst$$reg != $src$$reg) {
6845 __ movptr($dst$$Register, $src$$Register);
6846 }
6847 %}
6848 ins_pipe(ialu_reg_reg); // XXX
6849 %}
6850
6851
6852 // Convert oop pointer into compressed form
6853 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6854 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6855 match(Set dst (EncodeP src));
6856 effect(KILL cr);
6857 format %{ "encode_heap_oop $dst,$src" %}
6858 ins_encode %{
6859 Register s = $src$$Register;
6860 Register d = $dst$$Register;
6861 if (s != d) {
6862 __ movq(d, s);
6863 }
6864 __ encode_heap_oop(d);
6865 %}
6866 ins_pipe(ialu_reg_long);
6867 %}
6868
6869 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6870 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6871 match(Set dst (EncodeP src));
6872 effect(KILL cr);
6873 format %{ "encode_heap_oop_not_null $dst,$src" %}
6874 ins_encode %{
6875 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6876 %}
6877 ins_pipe(ialu_reg_long);
6878 %}
6879
6880 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6881 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6882 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6883 match(Set dst (DecodeN src));
6884 effect(KILL cr);
6885 format %{ "decode_heap_oop $dst,$src" %}
6886 ins_encode %{
6887 Register s = $src$$Register;
6888 Register d = $dst$$Register;
6889 if (s != d) {
6890 __ movq(d, s);
6891 }
6892 __ decode_heap_oop(d);
6893 %}
6894 ins_pipe(ialu_reg_long);
6895 %}
6896
6897 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6898 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6899 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6900 match(Set dst (DecodeN src));
6901 effect(KILL cr);
6902 format %{ "decode_heap_oop_not_null $dst,$src" %}
6903 ins_encode %{
6904 Register s = $src$$Register;
6905 Register d = $dst$$Register;
6906 if (s != d) {
6907 __ decode_heap_oop_not_null(d, s);
6908 } else {
6909 __ decode_heap_oop_not_null(d);
6910 }
6911 %}
6912 ins_pipe(ialu_reg_long);
6913 %}
6914
6915
6916 //----------Conditional Move---------------------------------------------------
6917 // Jump
6918 // dummy instruction for generating temp registers
6919 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6920 match(Jump (LShiftL switch_val shift));
6921 ins_cost(350);
6922 predicate(false);
6923 effect(TEMP dest);
6924
6925 format %{ "leaq $dest, [$constantaddress]\n\t"
6926 "jmp [$dest + $switch_val << $shift]\n\t" %}
6927 ins_encode %{
6928 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6929 // to do that and the compiler is using that register as one it can allocate.
6930 // So we build it all by hand.
6931 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6932 // ArrayAddress dispatch(table, index);
6933 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6934 __ lea($dest$$Register, $constantaddress);
6935 __ jmp(dispatch);
6936 %}
6937 ins_pipe(pipe_jmp);
6938 %}
6939
6940 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6941 match(Jump (AddL (LShiftL switch_val shift) offset));
6942 ins_cost(350);
6943 effect(TEMP dest);
6944
6945 format %{ "leaq $dest, [$constantaddress]\n\t"
6946 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6947 ins_encode %{
6948 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6949 // to do that and the compiler is using that register as one it can allocate.
6950 // So we build it all by hand.
6951 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6952 // ArrayAddress dispatch(table, index);
6953 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6954 __ lea($dest$$Register, $constantaddress);
6955 __ jmp(dispatch);
6956 %}
6957 ins_pipe(pipe_jmp);
6958 %}
6959
6960 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6961 match(Jump switch_val);
6962 ins_cost(350);
6963 effect(TEMP dest);
6964
6965 format %{ "leaq $dest, [$constantaddress]\n\t"
6966 "jmp [$dest + $switch_val]\n\t" %}
6967 ins_encode %{
6968 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6969 // to do that and the compiler is using that register as one it can allocate.
6970 // So we build it all by hand.
6971 // Address index(noreg, switch_reg, Address::times_1);
6972 // ArrayAddress dispatch(table, index);
6973 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6974 __ lea($dest$$Register, $constantaddress);
6975 __ jmp(dispatch);
6976 %}
6977 ins_pipe(pipe_jmp);
6978 %}
6979
6980 // Conditional move
6981 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6982 %{
6983 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6984
6985 ins_cost(200); // XXX
6986 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6987 opcode(0x0F, 0x40);
6988 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6989 ins_pipe(pipe_cmov_reg);
6990 %}
6991
6992 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6993 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6994
6995 ins_cost(200); // XXX
6996 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6997 opcode(0x0F, 0x40);
6998 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6999 ins_pipe(pipe_cmov_reg);
7000 %}
7001
7002 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7003 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7004 ins_cost(200);
7005 expand %{
7006 cmovI_regU(cop, cr, dst, src);
7007 %}
7008 %}
7009
7010 // Conditional move
7011 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7012 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7013
7014 ins_cost(250); // XXX
7015 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7016 opcode(0x0F, 0x40);
7017 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7018 ins_pipe(pipe_cmov_mem);
7019 %}
7020
7021 // Conditional move
7022 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7023 %{
7024 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7025
7026 ins_cost(250); // XXX
7027 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7028 opcode(0x0F, 0x40);
7029 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7030 ins_pipe(pipe_cmov_mem);
7031 %}
7032
7033 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7034 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7035 ins_cost(250);
7036 expand %{
7037 cmovI_memU(cop, cr, dst, src);
7038 %}
7039 %}
7040
7041 // Conditional move
7042 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7043 %{
7044 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7045
7046 ins_cost(200); // XXX
7047 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7048 opcode(0x0F, 0x40);
7049 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7050 ins_pipe(pipe_cmov_reg);
7051 %}
7052
7053 // Conditional move
7054 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7055 %{
7056 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7057
7058 ins_cost(200); // XXX
7059 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7060 opcode(0x0F, 0x40);
7061 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7062 ins_pipe(pipe_cmov_reg);
7063 %}
7064
7065 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7066 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7067 ins_cost(200);
7068 expand %{
7069 cmovN_regU(cop, cr, dst, src);
7070 %}
7071 %}
7072
7073 // Conditional move
7074 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7075 %{
7076 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7077
7078 ins_cost(200); // XXX
7079 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7080 opcode(0x0F, 0x40);
7081 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7082 ins_pipe(pipe_cmov_reg); // XXX
7083 %}
7084
7085 // Conditional move
7086 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7087 %{
7088 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7089
7090 ins_cost(200); // XXX
7091 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7092 opcode(0x0F, 0x40);
7093 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7094 ins_pipe(pipe_cmov_reg); // XXX
7095 %}
7096
7097 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7098 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7099 ins_cost(200);
7100 expand %{
7101 cmovP_regU(cop, cr, dst, src);
7102 %}
7103 %}
7104
7105 // DISABLED: Requires the ADLC to emit a bottom_type call that
7106 // correctly meets the two pointer arguments; one is an incoming
7107 // register but the other is a memory operand. ALSO appears to
7108 // be buggy with implicit null checks.
7109 //
7110 //// Conditional move
7111 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7112 //%{
7113 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7114 // ins_cost(250);
7115 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7116 // opcode(0x0F,0x40);
7117 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7118 // ins_pipe( pipe_cmov_mem );
7119 //%}
7120 //
7121 //// Conditional move
7122 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7123 //%{
7124 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7125 // ins_cost(250);
7126 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7127 // opcode(0x0F,0x40);
7128 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7129 // ins_pipe( pipe_cmov_mem );
7130 //%}
7131
7132 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7133 %{
7134 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7135
7136 ins_cost(200); // XXX
7137 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7138 opcode(0x0F, 0x40);
7139 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7140 ins_pipe(pipe_cmov_reg); // XXX
7141 %}
7142
7143 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7144 %{
7145 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7146
7147 ins_cost(200); // XXX
7148 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7149 opcode(0x0F, 0x40);
7150 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7151 ins_pipe(pipe_cmov_mem); // XXX
7152 %}
7153
7154 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7155 %{
7156 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7157
7158 ins_cost(200); // XXX
7159 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7160 opcode(0x0F, 0x40);
7161 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7162 ins_pipe(pipe_cmov_reg); // XXX
7163 %}
7164
7165 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7166 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7167 ins_cost(200);
7168 expand %{
7169 cmovL_regU(cop, cr, dst, src);
7170 %}
7171 %}
7172
7173 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7174 %{
7175 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7176
7177 ins_cost(200); // XXX
7178 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7179 opcode(0x0F, 0x40);
7180 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7181 ins_pipe(pipe_cmov_mem); // XXX
7182 %}
7183
7184 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7185 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7186 ins_cost(200);
7187 expand %{
7188 cmovL_memU(cop, cr, dst, src);
7189 %}
7190 %}
7191
7192 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7193 %{
7194 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7195
7196 ins_cost(200); // XXX
7197 format %{ "jn$cop skip\t# signed cmove float\n\t"
7198 "movss $dst, $src\n"
7199 "skip:" %}
7200 ins_encode %{
7201 Label Lskip;
7202 // Invert sense of branch from sense of CMOV
7203 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7204 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7205 __ bind(Lskip);
7206 %}
7207 ins_pipe(pipe_slow);
7208 %}
7209
7210 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7211 // %{
7212 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7213
7214 // ins_cost(200); // XXX
7215 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7216 // "movss $dst, $src\n"
7217 // "skip:" %}
7218 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7219 // ins_pipe(pipe_slow);
7220 // %}
7221
7222 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7223 %{
7224 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7225
7226 ins_cost(200); // XXX
7227 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7228 "movss $dst, $src\n"
7229 "skip:" %}
7230 ins_encode %{
7231 Label Lskip;
7232 // Invert sense of branch from sense of CMOV
7233 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7234 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7235 __ bind(Lskip);
7236 %}
7237 ins_pipe(pipe_slow);
7238 %}
7239
7240 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7241 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7242 ins_cost(200);
7243 expand %{
7244 cmovF_regU(cop, cr, dst, src);
7245 %}
7246 %}
7247
7248 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7249 %{
7250 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7251
7252 ins_cost(200); // XXX
7253 format %{ "jn$cop skip\t# signed cmove double\n\t"
7254 "movsd $dst, $src\n"
7255 "skip:" %}
7256 ins_encode %{
7257 Label Lskip;
7258 // Invert sense of branch from sense of CMOV
7259 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7260 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7261 __ bind(Lskip);
7262 %}
7263 ins_pipe(pipe_slow);
7264 %}
7265
7266 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7267 %{
7268 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7269
7270 ins_cost(200); // XXX
7271 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7272 "movsd $dst, $src\n"
7273 "skip:" %}
7274 ins_encode %{
7275 Label Lskip;
7276 // Invert sense of branch from sense of CMOV
7277 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7278 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7279 __ bind(Lskip);
7280 %}
7281 ins_pipe(pipe_slow);
7282 %}
7283
7284 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7285 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7286 ins_cost(200);
7287 expand %{
7288 cmovD_regU(cop, cr, dst, src);
7289 %}
7290 %}
7291
7292 //----------Arithmetic Instructions--------------------------------------------
7293 //----------Addition Instructions----------------------------------------------
7294
7295 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7296 %{
7297 match(Set dst (AddI dst src));
7298 effect(KILL cr);
7299
7300 format %{ "addl $dst, $src\t# int" %}
7301 opcode(0x03);
7302 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7303 ins_pipe(ialu_reg_reg);
7304 %}
7305
7306 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7307 %{
7308 match(Set dst (AddI dst src));
7309 effect(KILL cr);
7310
7311 format %{ "addl $dst, $src\t# int" %}
7312 opcode(0x81, 0x00); /* /0 id */
7313 ins_encode(OpcSErm(dst, src), Con8or32(src));
7314 ins_pipe( ialu_reg );
7315 %}
7316
7317 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7318 %{
7319 match(Set dst (AddI dst (LoadI src)));
7320 effect(KILL cr);
7321
7322 ins_cost(125); // XXX
7323 format %{ "addl $dst, $src\t# int" %}
7324 opcode(0x03);
7325 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7326 ins_pipe(ialu_reg_mem);
7327 %}
7328
7329 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7330 %{
7331 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7332 effect(KILL cr);
7333
7334 ins_cost(150); // XXX
7335 format %{ "addl $dst, $src\t# int" %}
7336 opcode(0x01); /* Opcode 01 /r */
7337 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7338 ins_pipe(ialu_mem_reg);
7339 %}
7340
7341 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7342 %{
7343 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7344 effect(KILL cr);
7345
7346 ins_cost(125); // XXX
7347 format %{ "addl $dst, $src\t# int" %}
7348 opcode(0x81); /* Opcode 81 /0 id */
7349 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7350 ins_pipe(ialu_mem_imm);
7351 %}
7352
7353 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7354 %{
7355 predicate(UseIncDec);
7356 match(Set dst (AddI dst src));
7357 effect(KILL cr);
7358
7359 format %{ "incl $dst\t# int" %}
7360 opcode(0xFF, 0x00); // FF /0
7361 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7362 ins_pipe(ialu_reg);
7363 %}
7364
7365 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7366 %{
7367 predicate(UseIncDec);
7368 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7369 effect(KILL cr);
7370
7371 ins_cost(125); // XXX
7372 format %{ "incl $dst\t# int" %}
7373 opcode(0xFF); /* Opcode FF /0 */
7374 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7375 ins_pipe(ialu_mem_imm);
7376 %}
7377
7378 // XXX why does that use AddI
7379 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7380 %{
7381 predicate(UseIncDec);
7382 match(Set dst (AddI dst src));
7383 effect(KILL cr);
7384
7385 format %{ "decl $dst\t# int" %}
7386 opcode(0xFF, 0x01); // FF /1
7387 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7388 ins_pipe(ialu_reg);
7389 %}
7390
7391 // XXX why does that use AddI
7392 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7393 %{
7394 predicate(UseIncDec);
7395 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7396 effect(KILL cr);
7397
7398 ins_cost(125); // XXX
7399 format %{ "decl $dst\t# int" %}
7400 opcode(0xFF); /* Opcode FF /1 */
7401 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7402 ins_pipe(ialu_mem_imm);
7403 %}
7404
7405 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7406 %{
7407 match(Set dst (AddI src0 src1));
7408
7409 ins_cost(110);
7410 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7411 opcode(0x8D); /* 0x8D /r */
7412 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7413 ins_pipe(ialu_reg_reg);
7414 %}
7415
7416 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7417 %{
7418 match(Set dst (AddL dst src));
7419 effect(KILL cr);
7420
7421 format %{ "addq $dst, $src\t# long" %}
7422 opcode(0x03);
7423 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7424 ins_pipe(ialu_reg_reg);
7425 %}
7426
7427 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7428 %{
7429 match(Set dst (AddL dst src));
7430 effect(KILL cr);
7431
7432 format %{ "addq $dst, $src\t# long" %}
7433 opcode(0x81, 0x00); /* /0 id */
7434 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7435 ins_pipe( ialu_reg );
7436 %}
7437
7438 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7439 %{
7440 match(Set dst (AddL dst (LoadL src)));
7441 effect(KILL cr);
7442
7443 ins_cost(125); // XXX
7444 format %{ "addq $dst, $src\t# long" %}
7445 opcode(0x03);
7446 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7447 ins_pipe(ialu_reg_mem);
7448 %}
7449
7450 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7451 %{
7452 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7453 effect(KILL cr);
7454
7455 ins_cost(150); // XXX
7456 format %{ "addq $dst, $src\t# long" %}
7457 opcode(0x01); /* Opcode 01 /r */
7458 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7459 ins_pipe(ialu_mem_reg);
7460 %}
7461
7462 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7463 %{
7464 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7465 effect(KILL cr);
7466
7467 ins_cost(125); // XXX
7468 format %{ "addq $dst, $src\t# long" %}
7469 opcode(0x81); /* Opcode 81 /0 id */
7470 ins_encode(REX_mem_wide(dst),
7471 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7472 ins_pipe(ialu_mem_imm);
7473 %}
7474
7475 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7476 %{
7477 predicate(UseIncDec);
7478 match(Set dst (AddL dst src));
7479 effect(KILL cr);
7480
7481 format %{ "incq $dst\t# long" %}
7482 opcode(0xFF, 0x00); // FF /0
7483 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7484 ins_pipe(ialu_reg);
7485 %}
7486
7487 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7488 %{
7489 predicate(UseIncDec);
7490 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7491 effect(KILL cr);
7492
7493 ins_cost(125); // XXX
7494 format %{ "incq $dst\t# long" %}
7495 opcode(0xFF); /* Opcode FF /0 */
7496 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7497 ins_pipe(ialu_mem_imm);
7498 %}
7499
7500 // XXX why does that use AddL
7501 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7502 %{
7503 predicate(UseIncDec);
7504 match(Set dst (AddL dst src));
7505 effect(KILL cr);
7506
7507 format %{ "decq $dst\t# long" %}
7508 opcode(0xFF, 0x01); // FF /1
7509 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7510 ins_pipe(ialu_reg);
7511 %}
7512
7513 // XXX why does that use AddL
7514 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7515 %{
7516 predicate(UseIncDec);
7517 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7518 effect(KILL cr);
7519
7520 ins_cost(125); // XXX
7521 format %{ "decq $dst\t# long" %}
7522 opcode(0xFF); /* Opcode FF /1 */
7523 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7524 ins_pipe(ialu_mem_imm);
7525 %}
7526
7527 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7528 %{
7529 match(Set dst (AddL src0 src1));
7530
7531 ins_cost(110);
7532 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7533 opcode(0x8D); /* 0x8D /r */
7534 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7535 ins_pipe(ialu_reg_reg);
7536 %}
7537
7538 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7539 %{
7540 match(Set dst (AddP dst src));
7541 effect(KILL cr);
7542
7543 format %{ "addq $dst, $src\t# ptr" %}
7544 opcode(0x03);
7545 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7546 ins_pipe(ialu_reg_reg);
7547 %}
7548
7549 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7550 %{
7551 match(Set dst (AddP dst src));
7552 effect(KILL cr);
7553
7554 format %{ "addq $dst, $src\t# ptr" %}
7555 opcode(0x81, 0x00); /* /0 id */
7556 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7557 ins_pipe( ialu_reg );
7558 %}
7559
7560 // XXX addP mem ops ????
7561
7562 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7563 %{
7564 match(Set dst (AddP src0 src1));
7565
7566 ins_cost(110);
7567 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7568 opcode(0x8D); /* 0x8D /r */
7569 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7570 ins_pipe(ialu_reg_reg);
7571 %}
7572
7573 instruct checkCastPP(rRegP dst)
7574 %{
7575 match(Set dst (CheckCastPP dst));
7576
7577 size(0);
7578 format %{ "# checkcastPP of $dst" %}
7579 ins_encode(/* empty encoding */);
7580 ins_pipe(empty);
7581 %}
7582
7583 instruct castPP(rRegP dst)
7584 %{
7585 match(Set dst (CastPP dst));
7586
7587 size(0);
7588 format %{ "# castPP of $dst" %}
7589 ins_encode(/* empty encoding */);
7590 ins_pipe(empty);
7591 %}
7592
7593 instruct castII(rRegI dst)
7594 %{
7595 match(Set dst (CastII dst));
7596
7597 size(0);
7598 format %{ "# castII of $dst" %}
7599 ins_encode(/* empty encoding */);
7600 ins_cost(0);
7601 ins_pipe(empty);
7602 %}
7603
7604 // LoadP-locked same as a regular LoadP when used with compare-swap
7605 instruct loadPLocked(rRegP dst, memory mem)
7606 %{
7607 match(Set dst (LoadPLocked mem));
7608
7609 ins_cost(125); // XXX
7610 format %{ "movq $dst, $mem\t# ptr locked" %}
7611 opcode(0x8B);
7612 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7613 ins_pipe(ialu_reg_mem); // XXX
7614 %}
7615
7616 // LoadL-locked - same as a regular LoadL when used with compare-swap
7617 instruct loadLLocked(rRegL dst, memory mem)
7618 %{
7619 match(Set dst (LoadLLocked mem));
7620
7621 ins_cost(125); // XXX
7622 format %{ "movq $dst, $mem\t# long locked" %}
7623 opcode(0x8B);
7624 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7625 ins_pipe(ialu_reg_mem); // XXX
7626 %}
7627
7628 // Conditional-store of the updated heap-top.
7629 // Used during allocation of the shared heap.
7630 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7631
7632 instruct storePConditional(memory heap_top_ptr,
7633 rax_RegP oldval, rRegP newval,
7634 rFlagsReg cr)
7635 %{
7636 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7637
7638 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7639 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7640 opcode(0x0F, 0xB1);
7641 ins_encode(lock_prefix,
7642 REX_reg_mem_wide(newval, heap_top_ptr),
7643 OpcP, OpcS,
7644 reg_mem(newval, heap_top_ptr));
7645 ins_pipe(pipe_cmpxchg);
7646 %}
7647
7648 // Conditional-store of an int value.
7649 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7650 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7651 %{
7652 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7653 effect(KILL oldval);
7654
7655 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7656 opcode(0x0F, 0xB1);
7657 ins_encode(lock_prefix,
7658 REX_reg_mem(newval, mem),
7659 OpcP, OpcS,
7660 reg_mem(newval, mem));
7661 ins_pipe(pipe_cmpxchg);
7662 %}
7663
7664 // Conditional-store of a long value.
7665 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7666 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7667 %{
7668 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7669 effect(KILL oldval);
7670
7671 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7672 opcode(0x0F, 0xB1);
7673 ins_encode(lock_prefix,
7674 REX_reg_mem_wide(newval, mem),
7675 OpcP, OpcS,
7676 reg_mem(newval, mem));
7677 ins_pipe(pipe_cmpxchg);
7678 %}
7679
7680
7681 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7682 instruct compareAndSwapP(rRegI res,
7683 memory mem_ptr,
7684 rax_RegP oldval, rRegP newval,
7685 rFlagsReg cr)
7686 %{
7687 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7688 effect(KILL cr, KILL oldval);
7689
7690 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7691 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7692 "sete $res\n\t"
7693 "movzbl $res, $res" %}
7694 opcode(0x0F, 0xB1);
7695 ins_encode(lock_prefix,
7696 REX_reg_mem_wide(newval, mem_ptr),
7697 OpcP, OpcS,
7698 reg_mem(newval, mem_ptr),
7699 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7700 REX_reg_breg(res, res), // movzbl
7701 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7702 ins_pipe( pipe_cmpxchg );
7703 %}
7704
7705 instruct compareAndSwapL(rRegI res,
7706 memory mem_ptr,
7707 rax_RegL oldval, rRegL newval,
7708 rFlagsReg cr)
7709 %{
7710 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7711 effect(KILL cr, KILL oldval);
7712
7713 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7714 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7715 "sete $res\n\t"
7716 "movzbl $res, $res" %}
7717 opcode(0x0F, 0xB1);
7718 ins_encode(lock_prefix,
7719 REX_reg_mem_wide(newval, mem_ptr),
7720 OpcP, OpcS,
7721 reg_mem(newval, mem_ptr),
7722 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7723 REX_reg_breg(res, res), // movzbl
7724 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7725 ins_pipe( pipe_cmpxchg );
7726 %}
7727
7728 instruct compareAndSwapI(rRegI res,
7729 memory mem_ptr,
7730 rax_RegI oldval, rRegI newval,
7731 rFlagsReg cr)
7732 %{
7733 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7734 effect(KILL cr, KILL oldval);
7735
7736 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7737 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7738 "sete $res\n\t"
7739 "movzbl $res, $res" %}
7740 opcode(0x0F, 0xB1);
7741 ins_encode(lock_prefix,
7742 REX_reg_mem(newval, mem_ptr),
7743 OpcP, OpcS,
7744 reg_mem(newval, mem_ptr),
7745 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7746 REX_reg_breg(res, res), // movzbl
7747 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7748 ins_pipe( pipe_cmpxchg );
7749 %}
7750
7751
7752 instruct compareAndSwapN(rRegI res,
7753 memory mem_ptr,
7754 rax_RegN oldval, rRegN newval,
7755 rFlagsReg cr) %{
7756 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7757 effect(KILL cr, KILL oldval);
7758
7759 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7760 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7761 "sete $res\n\t"
7762 "movzbl $res, $res" %}
7763 opcode(0x0F, 0xB1);
7764 ins_encode(lock_prefix,
7765 REX_reg_mem(newval, mem_ptr),
7766 OpcP, OpcS,
7767 reg_mem(newval, mem_ptr),
7768 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7769 REX_reg_breg(res, res), // movzbl
7770 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7771 ins_pipe( pipe_cmpxchg );
7772 %}
7773
7774 //----------Subtraction Instructions-------------------------------------------
7775
7776 // Integer Subtraction Instructions
7777 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7778 %{
7779 match(Set dst (SubI dst src));
7780 effect(KILL cr);
7781
7782 format %{ "subl $dst, $src\t# int" %}
7783 opcode(0x2B);
7784 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7785 ins_pipe(ialu_reg_reg);
7786 %}
7787
7788 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7789 %{
7790 match(Set dst (SubI dst src));
7791 effect(KILL cr);
7792
7793 format %{ "subl $dst, $src\t# int" %}
7794 opcode(0x81, 0x05); /* Opcode 81 /5 */
7795 ins_encode(OpcSErm(dst, src), Con8or32(src));
7796 ins_pipe(ialu_reg);
7797 %}
7798
7799 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7800 %{
7801 match(Set dst (SubI dst (LoadI src)));
7802 effect(KILL cr);
7803
7804 ins_cost(125);
7805 format %{ "subl $dst, $src\t# int" %}
7806 opcode(0x2B);
7807 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7808 ins_pipe(ialu_reg_mem);
7809 %}
7810
7811 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7812 %{
7813 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7814 effect(KILL cr);
7815
7816 ins_cost(150);
7817 format %{ "subl $dst, $src\t# int" %}
7818 opcode(0x29); /* Opcode 29 /r */
7819 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7820 ins_pipe(ialu_mem_reg);
7821 %}
7822
7823 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7824 %{
7825 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7826 effect(KILL cr);
7827
7828 ins_cost(125); // XXX
7829 format %{ "subl $dst, $src\t# int" %}
7830 opcode(0x81); /* Opcode 81 /5 id */
7831 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7832 ins_pipe(ialu_mem_imm);
7833 %}
7834
7835 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7836 %{
7837 match(Set dst (SubL dst src));
7838 effect(KILL cr);
7839
7840 format %{ "subq $dst, $src\t# long" %}
7841 opcode(0x2B);
7842 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7843 ins_pipe(ialu_reg_reg);
7844 %}
7845
7846 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7847 %{
7848 match(Set dst (SubL dst src));
7849 effect(KILL cr);
7850
7851 format %{ "subq $dst, $src\t# long" %}
7852 opcode(0x81, 0x05); /* Opcode 81 /5 */
7853 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7854 ins_pipe(ialu_reg);
7855 %}
7856
7857 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7858 %{
7859 match(Set dst (SubL dst (LoadL src)));
7860 effect(KILL cr);
7861
7862 ins_cost(125);
7863 format %{ "subq $dst, $src\t# long" %}
7864 opcode(0x2B);
7865 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7866 ins_pipe(ialu_reg_mem);
7867 %}
7868
7869 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7870 %{
7871 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7872 effect(KILL cr);
7873
7874 ins_cost(150);
7875 format %{ "subq $dst, $src\t# long" %}
7876 opcode(0x29); /* Opcode 29 /r */
7877 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7878 ins_pipe(ialu_mem_reg);
7879 %}
7880
7881 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7882 %{
7883 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7884 effect(KILL cr);
7885
7886 ins_cost(125); // XXX
7887 format %{ "subq $dst, $src\t# long" %}
7888 opcode(0x81); /* Opcode 81 /5 id */
7889 ins_encode(REX_mem_wide(dst),
7890 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7891 ins_pipe(ialu_mem_imm);
7892 %}
7893
7894 // Subtract from a pointer
7895 // XXX hmpf???
7896 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7897 %{
7898 match(Set dst (AddP dst (SubI zero src)));
7899 effect(KILL cr);
7900
7901 format %{ "subq $dst, $src\t# ptr - int" %}
7902 opcode(0x2B);
7903 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7904 ins_pipe(ialu_reg_reg);
7905 %}
7906
7907 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7908 %{
7909 match(Set dst (SubI zero dst));
7910 effect(KILL cr);
7911
7912 format %{ "negl $dst\t# int" %}
7913 opcode(0xF7, 0x03); // Opcode F7 /3
7914 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7915 ins_pipe(ialu_reg);
7916 %}
7917
7918 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7919 %{
7920 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7921 effect(KILL cr);
7922
7923 format %{ "negl $dst\t# int" %}
7924 opcode(0xF7, 0x03); // Opcode F7 /3
7925 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7926 ins_pipe(ialu_reg);
7927 %}
7928
7929 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7930 %{
7931 match(Set dst (SubL zero dst));
7932 effect(KILL cr);
7933
7934 format %{ "negq $dst\t# long" %}
7935 opcode(0xF7, 0x03); // Opcode F7 /3
7936 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7937 ins_pipe(ialu_reg);
7938 %}
7939
7940 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7941 %{
7942 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7943 effect(KILL cr);
7944
7945 format %{ "negq $dst\t# long" %}
7946 opcode(0xF7, 0x03); // Opcode F7 /3
7947 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7948 ins_pipe(ialu_reg);
7949 %}
7950
7951
7952 //----------Multiplication/Division Instructions-------------------------------
7953 // Integer Multiplication Instructions
7954 // Multiply Register
7955
7956 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7957 %{
7958 match(Set dst (MulI dst src));
7959 effect(KILL cr);
7960
7961 ins_cost(300);
7962 format %{ "imull $dst, $src\t# int" %}
7963 opcode(0x0F, 0xAF);
7964 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7965 ins_pipe(ialu_reg_reg_alu0);
7966 %}
7967
7968 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7969 %{
7970 match(Set dst (MulI src imm));
7971 effect(KILL cr);
7972
7973 ins_cost(300);
7974 format %{ "imull $dst, $src, $imm\t# int" %}
7975 opcode(0x69); /* 69 /r id */
7976 ins_encode(REX_reg_reg(dst, src),
7977 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7978 ins_pipe(ialu_reg_reg_alu0);
7979 %}
7980
7981 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7982 %{
7983 match(Set dst (MulI dst (LoadI src)));
7984 effect(KILL cr);
7985
7986 ins_cost(350);
7987 format %{ "imull $dst, $src\t# int" %}
7988 opcode(0x0F, 0xAF);
7989 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7990 ins_pipe(ialu_reg_mem_alu0);
7991 %}
7992
7993 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7994 %{
7995 match(Set dst (MulI (LoadI src) imm));
7996 effect(KILL cr);
7997
7998 ins_cost(300);
7999 format %{ "imull $dst, $src, $imm\t# int" %}
8000 opcode(0x69); /* 69 /r id */
8001 ins_encode(REX_reg_mem(dst, src),
8002 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8003 ins_pipe(ialu_reg_mem_alu0);
8004 %}
8005
8006 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8007 %{
8008 match(Set dst (MulL dst src));
8009 effect(KILL cr);
8010
8011 ins_cost(300);
8012 format %{ "imulq $dst, $src\t# long" %}
8013 opcode(0x0F, 0xAF);
8014 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8015 ins_pipe(ialu_reg_reg_alu0);
8016 %}
8017
8018 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8019 %{
8020 match(Set dst (MulL src imm));
8021 effect(KILL cr);
8022
8023 ins_cost(300);
8024 format %{ "imulq $dst, $src, $imm\t# long" %}
8025 opcode(0x69); /* 69 /r id */
8026 ins_encode(REX_reg_reg_wide(dst, src),
8027 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8028 ins_pipe(ialu_reg_reg_alu0);
8029 %}
8030
8031 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8032 %{
8033 match(Set dst (MulL dst (LoadL src)));
8034 effect(KILL cr);
8035
8036 ins_cost(350);
8037 format %{ "imulq $dst, $src\t# long" %}
8038 opcode(0x0F, 0xAF);
8039 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8040 ins_pipe(ialu_reg_mem_alu0);
8041 %}
8042
8043 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8044 %{
8045 match(Set dst (MulL (LoadL src) imm));
8046 effect(KILL cr);
8047
8048 ins_cost(300);
8049 format %{ "imulq $dst, $src, $imm\t# long" %}
8050 opcode(0x69); /* 69 /r id */
8051 ins_encode(REX_reg_mem_wide(dst, src),
8052 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8053 ins_pipe(ialu_reg_mem_alu0);
8054 %}
8055
8056 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8057 %{
8058 match(Set dst (MulHiL src rax));
8059 effect(USE_KILL rax, KILL cr);
8060
8061 ins_cost(300);
8062 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8063 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8064 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8065 ins_pipe(ialu_reg_reg_alu0);
8066 %}
8067
8068 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8069 rFlagsReg cr)
8070 %{
8071 match(Set rax (DivI rax div));
8072 effect(KILL rdx, KILL cr);
8073
8074 ins_cost(30*100+10*100); // XXX
8075 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8076 "jne,s normal\n\t"
8077 "xorl rdx, rdx\n\t"
8078 "cmpl $div, -1\n\t"
8079 "je,s done\n"
8080 "normal: cdql\n\t"
8081 "idivl $div\n"
8082 "done:" %}
8083 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8084 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8085 ins_pipe(ialu_reg_reg_alu0);
8086 %}
8087
8088 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8089 rFlagsReg cr)
8090 %{
8091 match(Set rax (DivL rax div));
8092 effect(KILL rdx, KILL cr);
8093
8094 ins_cost(30*100+10*100); // XXX
8095 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8096 "cmpq rax, rdx\n\t"
8097 "jne,s normal\n\t"
8098 "xorl rdx, rdx\n\t"
8099 "cmpq $div, -1\n\t"
8100 "je,s done\n"
8101 "normal: cdqq\n\t"
8102 "idivq $div\n"
8103 "done:" %}
8104 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8105 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8106 ins_pipe(ialu_reg_reg_alu0);
8107 %}
8108
8109 // Integer DIVMOD with Register, both quotient and mod results
8110 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8111 rFlagsReg cr)
8112 %{
8113 match(DivModI rax div);
8114 effect(KILL cr);
8115
8116 ins_cost(30*100+10*100); // XXX
8117 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8118 "jne,s normal\n\t"
8119 "xorl rdx, rdx\n\t"
8120 "cmpl $div, -1\n\t"
8121 "je,s done\n"
8122 "normal: cdql\n\t"
8123 "idivl $div\n"
8124 "done:" %}
8125 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8126 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8127 ins_pipe(pipe_slow);
8128 %}
8129
8130 // Long DIVMOD with Register, both quotient and mod results
8131 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8132 rFlagsReg cr)
8133 %{
8134 match(DivModL rax div);
8135 effect(KILL cr);
8136
8137 ins_cost(30*100+10*100); // XXX
8138 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8139 "cmpq rax, rdx\n\t"
8140 "jne,s normal\n\t"
8141 "xorl rdx, rdx\n\t"
8142 "cmpq $div, -1\n\t"
8143 "je,s done\n"
8144 "normal: cdqq\n\t"
8145 "idivq $div\n"
8146 "done:" %}
8147 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8148 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8149 ins_pipe(pipe_slow);
8150 %}
8151
8152 //----------- DivL-By-Constant-Expansions--------------------------------------
8153 // DivI cases are handled by the compiler
8154
8155 // Magic constant, reciprocal of 10
8156 instruct loadConL_0x6666666666666667(rRegL dst)
8157 %{
8158 effect(DEF dst);
8159
8160 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8161 ins_encode(load_immL(dst, 0x6666666666666667));
8162 ins_pipe(ialu_reg);
8163 %}
8164
8165 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8166 %{
8167 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8168
8169 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8170 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8171 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8172 ins_pipe(ialu_reg_reg_alu0);
8173 %}
8174
8175 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8176 %{
8177 effect(USE_DEF dst, KILL cr);
8178
8179 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8180 opcode(0xC1, 0x7); /* C1 /7 ib */
8181 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8182 ins_pipe(ialu_reg);
8183 %}
8184
8185 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8186 %{
8187 effect(USE_DEF dst, KILL cr);
8188
8189 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8190 opcode(0xC1, 0x7); /* C1 /7 ib */
8191 ins_encode(reg_opc_imm_wide(dst, 0x2));
8192 ins_pipe(ialu_reg);
8193 %}
8194
8195 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8196 %{
8197 match(Set dst (DivL src div));
8198
8199 ins_cost((5+8)*100);
8200 expand %{
8201 rax_RegL rax; // Killed temp
8202 rFlagsReg cr; // Killed
8203 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8204 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8205 sarL_rReg_63(src, cr); // sarq src, 63
8206 sarL_rReg_2(dst, cr); // sarq rdx, 2
8207 subL_rReg(dst, src, cr); // subl rdx, src
8208 %}
8209 %}
8210
8211 //-----------------------------------------------------------------------------
8212
8213 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8214 rFlagsReg cr)
8215 %{
8216 match(Set rdx (ModI rax div));
8217 effect(KILL rax, KILL cr);
8218
8219 ins_cost(300); // XXX
8220 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8221 "jne,s normal\n\t"
8222 "xorl rdx, rdx\n\t"
8223 "cmpl $div, -1\n\t"
8224 "je,s done\n"
8225 "normal: cdql\n\t"
8226 "idivl $div\n"
8227 "done:" %}
8228 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8229 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8230 ins_pipe(ialu_reg_reg_alu0);
8231 %}
8232
8233 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8234 rFlagsReg cr)
8235 %{
8236 match(Set rdx (ModL rax div));
8237 effect(KILL rax, KILL cr);
8238
8239 ins_cost(300); // XXX
8240 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8241 "cmpq rax, rdx\n\t"
8242 "jne,s normal\n\t"
8243 "xorl rdx, rdx\n\t"
8244 "cmpq $div, -1\n\t"
8245 "je,s done\n"
8246 "normal: cdqq\n\t"
8247 "idivq $div\n"
8248 "done:" %}
8249 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8250 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8251 ins_pipe(ialu_reg_reg_alu0);
8252 %}
8253
8254 // Integer Shift Instructions
8255 // Shift Left by one
8256 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8257 %{
8258 match(Set dst (LShiftI dst shift));
8259 effect(KILL cr);
8260
8261 format %{ "sall $dst, $shift" %}
8262 opcode(0xD1, 0x4); /* D1 /4 */
8263 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8264 ins_pipe(ialu_reg);
8265 %}
8266
8267 // Shift Left by one
8268 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8269 %{
8270 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8271 effect(KILL cr);
8272
8273 format %{ "sall $dst, $shift\t" %}
8274 opcode(0xD1, 0x4); /* D1 /4 */
8275 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8276 ins_pipe(ialu_mem_imm);
8277 %}
8278
8279 // Shift Left by 8-bit immediate
8280 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8281 %{
8282 match(Set dst (LShiftI dst shift));
8283 effect(KILL cr);
8284
8285 format %{ "sall $dst, $shift" %}
8286 opcode(0xC1, 0x4); /* C1 /4 ib */
8287 ins_encode(reg_opc_imm(dst, shift));
8288 ins_pipe(ialu_reg);
8289 %}
8290
8291 // Shift Left by 8-bit immediate
8292 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8293 %{
8294 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8295 effect(KILL cr);
8296
8297 format %{ "sall $dst, $shift" %}
8298 opcode(0xC1, 0x4); /* C1 /4 ib */
8299 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8300 ins_pipe(ialu_mem_imm);
8301 %}
8302
8303 // Shift Left by variable
8304 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8305 %{
8306 match(Set dst (LShiftI dst shift));
8307 effect(KILL cr);
8308
8309 format %{ "sall $dst, $shift" %}
8310 opcode(0xD3, 0x4); /* D3 /4 */
8311 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8312 ins_pipe(ialu_reg_reg);
8313 %}
8314
8315 // Shift Left by variable
8316 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8317 %{
8318 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8319 effect(KILL cr);
8320
8321 format %{ "sall $dst, $shift" %}
8322 opcode(0xD3, 0x4); /* D3 /4 */
8323 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8324 ins_pipe(ialu_mem_reg);
8325 %}
8326
8327 // Arithmetic shift right by one
8328 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8329 %{
8330 match(Set dst (RShiftI dst shift));
8331 effect(KILL cr);
8332
8333 format %{ "sarl $dst, $shift" %}
8334 opcode(0xD1, 0x7); /* D1 /7 */
8335 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8336 ins_pipe(ialu_reg);
8337 %}
8338
8339 // Arithmetic shift right by one
8340 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8341 %{
8342 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8343 effect(KILL cr);
8344
8345 format %{ "sarl $dst, $shift" %}
8346 opcode(0xD1, 0x7); /* D1 /7 */
8347 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8348 ins_pipe(ialu_mem_imm);
8349 %}
8350
8351 // Arithmetic Shift Right by 8-bit immediate
8352 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8353 %{
8354 match(Set dst (RShiftI dst shift));
8355 effect(KILL cr);
8356
8357 format %{ "sarl $dst, $shift" %}
8358 opcode(0xC1, 0x7); /* C1 /7 ib */
8359 ins_encode(reg_opc_imm(dst, shift));
8360 ins_pipe(ialu_mem_imm);
8361 %}
8362
8363 // Arithmetic Shift Right by 8-bit immediate
8364 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8365 %{
8366 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8367 effect(KILL cr);
8368
8369 format %{ "sarl $dst, $shift" %}
8370 opcode(0xC1, 0x7); /* C1 /7 ib */
8371 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8372 ins_pipe(ialu_mem_imm);
8373 %}
8374
8375 // Arithmetic Shift Right by variable
8376 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8377 %{
8378 match(Set dst (RShiftI dst shift));
8379 effect(KILL cr);
8380
8381 format %{ "sarl $dst, $shift" %}
8382 opcode(0xD3, 0x7); /* D3 /7 */
8383 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8384 ins_pipe(ialu_reg_reg);
8385 %}
8386
8387 // Arithmetic Shift Right by variable
8388 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8389 %{
8390 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8391 effect(KILL cr);
8392
8393 format %{ "sarl $dst, $shift" %}
8394 opcode(0xD3, 0x7); /* D3 /7 */
8395 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8396 ins_pipe(ialu_mem_reg);
8397 %}
8398
8399 // Logical shift right by one
8400 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8401 %{
8402 match(Set dst (URShiftI dst shift));
8403 effect(KILL cr);
8404
8405 format %{ "shrl $dst, $shift" %}
8406 opcode(0xD1, 0x5); /* D1 /5 */
8407 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8408 ins_pipe(ialu_reg);
8409 %}
8410
8411 // Logical shift right by one
8412 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8413 %{
8414 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8415 effect(KILL cr);
8416
8417 format %{ "shrl $dst, $shift" %}
8418 opcode(0xD1, 0x5); /* D1 /5 */
8419 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8420 ins_pipe(ialu_mem_imm);
8421 %}
8422
8423 // Logical Shift Right by 8-bit immediate
8424 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8425 %{
8426 match(Set dst (URShiftI dst shift));
8427 effect(KILL cr);
8428
8429 format %{ "shrl $dst, $shift" %}
8430 opcode(0xC1, 0x5); /* C1 /5 ib */
8431 ins_encode(reg_opc_imm(dst, shift));
8432 ins_pipe(ialu_reg);
8433 %}
8434
8435 // Logical Shift Right by 8-bit immediate
8436 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8437 %{
8438 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8439 effect(KILL cr);
8440
8441 format %{ "shrl $dst, $shift" %}
8442 opcode(0xC1, 0x5); /* C1 /5 ib */
8443 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8444 ins_pipe(ialu_mem_imm);
8445 %}
8446
8447 // Logical Shift Right by variable
8448 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8449 %{
8450 match(Set dst (URShiftI dst shift));
8451 effect(KILL cr);
8452
8453 format %{ "shrl $dst, $shift" %}
8454 opcode(0xD3, 0x5); /* D3 /5 */
8455 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8456 ins_pipe(ialu_reg_reg);
8457 %}
8458
8459 // Logical Shift Right by variable
8460 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8461 %{
8462 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8463 effect(KILL cr);
8464
8465 format %{ "shrl $dst, $shift" %}
8466 opcode(0xD3, 0x5); /* D3 /5 */
8467 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8468 ins_pipe(ialu_mem_reg);
8469 %}
8470
8471 // Long Shift Instructions
8472 // Shift Left by one
8473 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8474 %{
8475 match(Set dst (LShiftL dst shift));
8476 effect(KILL cr);
8477
8478 format %{ "salq $dst, $shift" %}
8479 opcode(0xD1, 0x4); /* D1 /4 */
8480 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8481 ins_pipe(ialu_reg);
8482 %}
8483
8484 // Shift Left by one
8485 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8486 %{
8487 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8488 effect(KILL cr);
8489
8490 format %{ "salq $dst, $shift" %}
8491 opcode(0xD1, 0x4); /* D1 /4 */
8492 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8493 ins_pipe(ialu_mem_imm);
8494 %}
8495
8496 // Shift Left by 8-bit immediate
8497 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8498 %{
8499 match(Set dst (LShiftL dst shift));
8500 effect(KILL cr);
8501
8502 format %{ "salq $dst, $shift" %}
8503 opcode(0xC1, 0x4); /* C1 /4 ib */
8504 ins_encode(reg_opc_imm_wide(dst, shift));
8505 ins_pipe(ialu_reg);
8506 %}
8507
8508 // Shift Left by 8-bit immediate
8509 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8510 %{
8511 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8512 effect(KILL cr);
8513
8514 format %{ "salq $dst, $shift" %}
8515 opcode(0xC1, 0x4); /* C1 /4 ib */
8516 ins_encode(REX_mem_wide(dst), OpcP,
8517 RM_opc_mem(secondary, dst), Con8or32(shift));
8518 ins_pipe(ialu_mem_imm);
8519 %}
8520
8521 // Shift Left by variable
8522 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8523 %{
8524 match(Set dst (LShiftL dst shift));
8525 effect(KILL cr);
8526
8527 format %{ "salq $dst, $shift" %}
8528 opcode(0xD3, 0x4); /* D3 /4 */
8529 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8530 ins_pipe(ialu_reg_reg);
8531 %}
8532
8533 // Shift Left by variable
8534 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8535 %{
8536 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8537 effect(KILL cr);
8538
8539 format %{ "salq $dst, $shift" %}
8540 opcode(0xD3, 0x4); /* D3 /4 */
8541 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8542 ins_pipe(ialu_mem_reg);
8543 %}
8544
8545 // Arithmetic shift right by one
8546 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8547 %{
8548 match(Set dst (RShiftL dst shift));
8549 effect(KILL cr);
8550
8551 format %{ "sarq $dst, $shift" %}
8552 opcode(0xD1, 0x7); /* D1 /7 */
8553 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8554 ins_pipe(ialu_reg);
8555 %}
8556
8557 // Arithmetic shift right by one
8558 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8559 %{
8560 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8561 effect(KILL cr);
8562
8563 format %{ "sarq $dst, $shift" %}
8564 opcode(0xD1, 0x7); /* D1 /7 */
8565 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8566 ins_pipe(ialu_mem_imm);
8567 %}
8568
8569 // Arithmetic Shift Right by 8-bit immediate
8570 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8571 %{
8572 match(Set dst (RShiftL dst shift));
8573 effect(KILL cr);
8574
8575 format %{ "sarq $dst, $shift" %}
8576 opcode(0xC1, 0x7); /* C1 /7 ib */
8577 ins_encode(reg_opc_imm_wide(dst, shift));
8578 ins_pipe(ialu_mem_imm);
8579 %}
8580
8581 // Arithmetic Shift Right by 8-bit immediate
8582 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8583 %{
8584 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8585 effect(KILL cr);
8586
8587 format %{ "sarq $dst, $shift" %}
8588 opcode(0xC1, 0x7); /* C1 /7 ib */
8589 ins_encode(REX_mem_wide(dst), OpcP,
8590 RM_opc_mem(secondary, dst), Con8or32(shift));
8591 ins_pipe(ialu_mem_imm);
8592 %}
8593
8594 // Arithmetic Shift Right by variable
8595 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8596 %{
8597 match(Set dst (RShiftL dst shift));
8598 effect(KILL cr);
8599
8600 format %{ "sarq $dst, $shift" %}
8601 opcode(0xD3, 0x7); /* D3 /7 */
8602 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8603 ins_pipe(ialu_reg_reg);
8604 %}
8605
8606 // Arithmetic Shift Right by variable
8607 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8608 %{
8609 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8610 effect(KILL cr);
8611
8612 format %{ "sarq $dst, $shift" %}
8613 opcode(0xD3, 0x7); /* D3 /7 */
8614 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8615 ins_pipe(ialu_mem_reg);
8616 %}
8617
8618 // Logical shift right by one
8619 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8620 %{
8621 match(Set dst (URShiftL dst shift));
8622 effect(KILL cr);
8623
8624 format %{ "shrq $dst, $shift" %}
8625 opcode(0xD1, 0x5); /* D1 /5 */
8626 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8627 ins_pipe(ialu_reg);
8628 %}
8629
8630 // Logical shift right by one
8631 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8632 %{
8633 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8634 effect(KILL cr);
8635
8636 format %{ "shrq $dst, $shift" %}
8637 opcode(0xD1, 0x5); /* D1 /5 */
8638 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8639 ins_pipe(ialu_mem_imm);
8640 %}
8641
8642 // Logical Shift Right by 8-bit immediate
8643 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8644 %{
8645 match(Set dst (URShiftL dst shift));
8646 effect(KILL cr);
8647
8648 format %{ "shrq $dst, $shift" %}
8649 opcode(0xC1, 0x5); /* C1 /5 ib */
8650 ins_encode(reg_opc_imm_wide(dst, shift));
8651 ins_pipe(ialu_reg);
8652 %}
8653
8654
8655 // Logical Shift Right by 8-bit immediate
8656 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8657 %{
8658 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8659 effect(KILL cr);
8660
8661 format %{ "shrq $dst, $shift" %}
8662 opcode(0xC1, 0x5); /* C1 /5 ib */
8663 ins_encode(REX_mem_wide(dst), OpcP,
8664 RM_opc_mem(secondary, dst), Con8or32(shift));
8665 ins_pipe(ialu_mem_imm);
8666 %}
8667
8668 // Logical Shift Right by variable
8669 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8670 %{
8671 match(Set dst (URShiftL dst shift));
8672 effect(KILL cr);
8673
8674 format %{ "shrq $dst, $shift" %}
8675 opcode(0xD3, 0x5); /* D3 /5 */
8676 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8677 ins_pipe(ialu_reg_reg);
8678 %}
8679
8680 // Logical Shift Right by variable
8681 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8682 %{
8683 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8684 effect(KILL cr);
8685
8686 format %{ "shrq $dst, $shift" %}
8687 opcode(0xD3, 0x5); /* D3 /5 */
8688 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8689 ins_pipe(ialu_mem_reg);
8690 %}
8691
8692 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8693 // This idiom is used by the compiler for the i2b bytecode.
8694 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8695 %{
8696 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8697
8698 format %{ "movsbl $dst, $src\t# i2b" %}
8699 opcode(0x0F, 0xBE);
8700 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8701 ins_pipe(ialu_reg_reg);
8702 %}
8703
8704 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8705 // This idiom is used by the compiler the i2s bytecode.
8706 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8707 %{
8708 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8709
8710 format %{ "movswl $dst, $src\t# i2s" %}
8711 opcode(0x0F, 0xBF);
8712 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8713 ins_pipe(ialu_reg_reg);
8714 %}
8715
8716 // ROL/ROR instructions
8717
8718 // ROL expand
8719 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8720 effect(KILL cr, USE_DEF dst);
8721
8722 format %{ "roll $dst" %}
8723 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8724 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8725 ins_pipe(ialu_reg);
8726 %}
8727
8728 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8729 effect(USE_DEF dst, USE shift, KILL cr);
8730
8731 format %{ "roll $dst, $shift" %}
8732 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8733 ins_encode( reg_opc_imm(dst, shift) );
8734 ins_pipe(ialu_reg);
8735 %}
8736
8737 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8738 %{
8739 effect(USE_DEF dst, USE shift, KILL cr);
8740
8741 format %{ "roll $dst, $shift" %}
8742 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8743 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8744 ins_pipe(ialu_reg_reg);
8745 %}
8746 // end of ROL expand
8747
8748 // Rotate Left by one
8749 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8750 %{
8751 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8752
8753 expand %{
8754 rolI_rReg_imm1(dst, cr);
8755 %}
8756 %}
8757
8758 // Rotate Left by 8-bit immediate
8759 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8760 %{
8761 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8762 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8763
8764 expand %{
8765 rolI_rReg_imm8(dst, lshift, cr);
8766 %}
8767 %}
8768
8769 // Rotate Left by variable
8770 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8771 %{
8772 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8773
8774 expand %{
8775 rolI_rReg_CL(dst, shift, cr);
8776 %}
8777 %}
8778
8779 // Rotate Left by variable
8780 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8781 %{
8782 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8783
8784 expand %{
8785 rolI_rReg_CL(dst, shift, cr);
8786 %}
8787 %}
8788
8789 // ROR expand
8790 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8791 %{
8792 effect(USE_DEF dst, KILL cr);
8793
8794 format %{ "rorl $dst" %}
8795 opcode(0xD1, 0x1); /* D1 /1 */
8796 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8797 ins_pipe(ialu_reg);
8798 %}
8799
8800 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8801 %{
8802 effect(USE_DEF dst, USE shift, KILL cr);
8803
8804 format %{ "rorl $dst, $shift" %}
8805 opcode(0xC1, 0x1); /* C1 /1 ib */
8806 ins_encode(reg_opc_imm(dst, shift));
8807 ins_pipe(ialu_reg);
8808 %}
8809
8810 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8811 %{
8812 effect(USE_DEF dst, USE shift, KILL cr);
8813
8814 format %{ "rorl $dst, $shift" %}
8815 opcode(0xD3, 0x1); /* D3 /1 */
8816 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8817 ins_pipe(ialu_reg_reg);
8818 %}
8819 // end of ROR expand
8820
8821 // Rotate Right by one
8822 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8823 %{
8824 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8825
8826 expand %{
8827 rorI_rReg_imm1(dst, cr);
8828 %}
8829 %}
8830
8831 // Rotate Right by 8-bit immediate
8832 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8833 %{
8834 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8835 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8836
8837 expand %{
8838 rorI_rReg_imm8(dst, rshift, cr);
8839 %}
8840 %}
8841
8842 // Rotate Right by variable
8843 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8844 %{
8845 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8846
8847 expand %{
8848 rorI_rReg_CL(dst, shift, cr);
8849 %}
8850 %}
8851
8852 // Rotate Right by variable
8853 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8854 %{
8855 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8856
8857 expand %{
8858 rorI_rReg_CL(dst, shift, cr);
8859 %}
8860 %}
8861
8862 // for long rotate
8863 // ROL expand
8864 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8865 effect(USE_DEF dst, KILL cr);
8866
8867 format %{ "rolq $dst" %}
8868 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8869 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8874 effect(USE_DEF dst, USE shift, KILL cr);
8875
8876 format %{ "rolq $dst, $shift" %}
8877 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8878 ins_encode( reg_opc_imm_wide(dst, shift) );
8879 ins_pipe(ialu_reg);
8880 %}
8881
8882 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8883 %{
8884 effect(USE_DEF dst, USE shift, KILL cr);
8885
8886 format %{ "rolq $dst, $shift" %}
8887 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8888 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8889 ins_pipe(ialu_reg_reg);
8890 %}
8891 // end of ROL expand
8892
8893 // Rotate Left by one
8894 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8895 %{
8896 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8897
8898 expand %{
8899 rolL_rReg_imm1(dst, cr);
8900 %}
8901 %}
8902
8903 // Rotate Left by 8-bit immediate
8904 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8905 %{
8906 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8907 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8908
8909 expand %{
8910 rolL_rReg_imm8(dst, lshift, cr);
8911 %}
8912 %}
8913
8914 // Rotate Left by variable
8915 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8916 %{
8917 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8918
8919 expand %{
8920 rolL_rReg_CL(dst, shift, cr);
8921 %}
8922 %}
8923
8924 // Rotate Left by variable
8925 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8926 %{
8927 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8928
8929 expand %{
8930 rolL_rReg_CL(dst, shift, cr);
8931 %}
8932 %}
8933
8934 // ROR expand
8935 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8936 %{
8937 effect(USE_DEF dst, KILL cr);
8938
8939 format %{ "rorq $dst" %}
8940 opcode(0xD1, 0x1); /* D1 /1 */
8941 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8942 ins_pipe(ialu_reg);
8943 %}
8944
8945 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8946 %{
8947 effect(USE_DEF dst, USE shift, KILL cr);
8948
8949 format %{ "rorq $dst, $shift" %}
8950 opcode(0xC1, 0x1); /* C1 /1 ib */
8951 ins_encode(reg_opc_imm_wide(dst, shift));
8952 ins_pipe(ialu_reg);
8953 %}
8954
8955 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8956 %{
8957 effect(USE_DEF dst, USE shift, KILL cr);
8958
8959 format %{ "rorq $dst, $shift" %}
8960 opcode(0xD3, 0x1); /* D3 /1 */
8961 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8962 ins_pipe(ialu_reg_reg);
8963 %}
8964 // end of ROR expand
8965
8966 // Rotate Right by one
8967 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8968 %{
8969 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8970
8971 expand %{
8972 rorL_rReg_imm1(dst, cr);
8973 %}
8974 %}
8975
8976 // Rotate Right by 8-bit immediate
8977 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8978 %{
8979 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8980 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8981
8982 expand %{
8983 rorL_rReg_imm8(dst, rshift, cr);
8984 %}
8985 %}
8986
8987 // Rotate Right by variable
8988 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8989 %{
8990 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8991
8992 expand %{
8993 rorL_rReg_CL(dst, shift, cr);
8994 %}
8995 %}
8996
8997 // Rotate Right by variable
8998 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8999 %{
9000 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9001
9002 expand %{
9003 rorL_rReg_CL(dst, shift, cr);
9004 %}
9005 %}
9006
9007 // Logical Instructions
9008
9009 // Integer Logical Instructions
9010
9011 // And Instructions
9012 // And Register with Register
9013 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9014 %{
9015 match(Set dst (AndI dst src));
9016 effect(KILL cr);
9017
9018 format %{ "andl $dst, $src\t# int" %}
9019 opcode(0x23);
9020 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9021 ins_pipe(ialu_reg_reg);
9022 %}
9023
9024 // And Register with Immediate 255
9025 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9026 %{
9027 match(Set dst (AndI dst src));
9028
9029 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9030 opcode(0x0F, 0xB6);
9031 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9032 ins_pipe(ialu_reg);
9033 %}
9034
9035 // And Register with Immediate 255 and promote to long
9036 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9037 %{
9038 match(Set dst (ConvI2L (AndI src mask)));
9039
9040 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9041 opcode(0x0F, 0xB6);
9042 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9043 ins_pipe(ialu_reg);
9044 %}
9045
9046 // And Register with Immediate 65535
9047 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9048 %{
9049 match(Set dst (AndI dst src));
9050
9051 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9052 opcode(0x0F, 0xB7);
9053 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9054 ins_pipe(ialu_reg);
9055 %}
9056
9057 // And Register with Immediate 65535 and promote to long
9058 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9059 %{
9060 match(Set dst (ConvI2L (AndI src mask)));
9061
9062 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9063 opcode(0x0F, 0xB7);
9064 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9065 ins_pipe(ialu_reg);
9066 %}
9067
9068 // And Register with Immediate
9069 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9070 %{
9071 match(Set dst (AndI dst src));
9072 effect(KILL cr);
9073
9074 format %{ "andl $dst, $src\t# int" %}
9075 opcode(0x81, 0x04); /* Opcode 81 /4 */
9076 ins_encode(OpcSErm(dst, src), Con8or32(src));
9077 ins_pipe(ialu_reg);
9078 %}
9079
9080 // And Register with Memory
9081 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9082 %{
9083 match(Set dst (AndI dst (LoadI src)));
9084 effect(KILL cr);
9085
9086 ins_cost(125);
9087 format %{ "andl $dst, $src\t# int" %}
9088 opcode(0x23);
9089 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9090 ins_pipe(ialu_reg_mem);
9091 %}
9092
9093 // And Memory with Register
9094 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9095 %{
9096 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9097 effect(KILL cr);
9098
9099 ins_cost(150);
9100 format %{ "andl $dst, $src\t# int" %}
9101 opcode(0x21); /* Opcode 21 /r */
9102 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9103 ins_pipe(ialu_mem_reg);
9104 %}
9105
9106 // And Memory with Immediate
9107 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9108 %{
9109 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9110 effect(KILL cr);
9111
9112 ins_cost(125);
9113 format %{ "andl $dst, $src\t# int" %}
9114 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9115 ins_encode(REX_mem(dst), OpcSE(src),
9116 RM_opc_mem(secondary, dst), Con8or32(src));
9117 ins_pipe(ialu_mem_imm);
9118 %}
9119
9120 // Or Instructions
9121 // Or Register with Register
9122 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9123 %{
9124 match(Set dst (OrI dst src));
9125 effect(KILL cr);
9126
9127 format %{ "orl $dst, $src\t# int" %}
9128 opcode(0x0B);
9129 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9130 ins_pipe(ialu_reg_reg);
9131 %}
9132
9133 // Or Register with Immediate
9134 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9135 %{
9136 match(Set dst (OrI dst src));
9137 effect(KILL cr);
9138
9139 format %{ "orl $dst, $src\t# int" %}
9140 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9141 ins_encode(OpcSErm(dst, src), Con8or32(src));
9142 ins_pipe(ialu_reg);
9143 %}
9144
9145 // Or Register with Memory
9146 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9147 %{
9148 match(Set dst (OrI dst (LoadI src)));
9149 effect(KILL cr);
9150
9151 ins_cost(125);
9152 format %{ "orl $dst, $src\t# int" %}
9153 opcode(0x0B);
9154 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9155 ins_pipe(ialu_reg_mem);
9156 %}
9157
9158 // Or Memory with Register
9159 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9160 %{
9161 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9162 effect(KILL cr);
9163
9164 ins_cost(150);
9165 format %{ "orl $dst, $src\t# int" %}
9166 opcode(0x09); /* Opcode 09 /r */
9167 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9168 ins_pipe(ialu_mem_reg);
9169 %}
9170
9171 // Or Memory with Immediate
9172 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9173 %{
9174 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9175 effect(KILL cr);
9176
9177 ins_cost(125);
9178 format %{ "orl $dst, $src\t# int" %}
9179 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9180 ins_encode(REX_mem(dst), OpcSE(src),
9181 RM_opc_mem(secondary, dst), Con8or32(src));
9182 ins_pipe(ialu_mem_imm);
9183 %}
9184
9185 // Xor Instructions
9186 // Xor Register with Register
9187 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9188 %{
9189 match(Set dst (XorI dst src));
9190 effect(KILL cr);
9191
9192 format %{ "xorl $dst, $src\t# int" %}
9193 opcode(0x33);
9194 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9195 ins_pipe(ialu_reg_reg);
9196 %}
9197
9198 // Xor Register with Immediate -1
9199 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9200 match(Set dst (XorI dst imm));
9201
9202 format %{ "not $dst" %}
9203 ins_encode %{
9204 __ notl($dst$$Register);
9205 %}
9206 ins_pipe(ialu_reg);
9207 %}
9208
9209 // Xor Register with Immediate
9210 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9211 %{
9212 match(Set dst (XorI dst src));
9213 effect(KILL cr);
9214
9215 format %{ "xorl $dst, $src\t# int" %}
9216 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9217 ins_encode(OpcSErm(dst, src), Con8or32(src));
9218 ins_pipe(ialu_reg);
9219 %}
9220
9221 // Xor Register with Memory
9222 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9223 %{
9224 match(Set dst (XorI dst (LoadI src)));
9225 effect(KILL cr);
9226
9227 ins_cost(125);
9228 format %{ "xorl $dst, $src\t# int" %}
9229 opcode(0x33);
9230 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9231 ins_pipe(ialu_reg_mem);
9232 %}
9233
9234 // Xor Memory with Register
9235 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9236 %{
9237 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9238 effect(KILL cr);
9239
9240 ins_cost(150);
9241 format %{ "xorl $dst, $src\t# int" %}
9242 opcode(0x31); /* Opcode 31 /r */
9243 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9244 ins_pipe(ialu_mem_reg);
9245 %}
9246
9247 // Xor Memory with Immediate
9248 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9249 %{
9250 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9251 effect(KILL cr);
9252
9253 ins_cost(125);
9254 format %{ "xorl $dst, $src\t# int" %}
9255 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9256 ins_encode(REX_mem(dst), OpcSE(src),
9257 RM_opc_mem(secondary, dst), Con8or32(src));
9258 ins_pipe(ialu_mem_imm);
9259 %}
9260
9261
9262 // Long Logical Instructions
9263
9264 // And Instructions
9265 // And Register with Register
9266 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9267 %{
9268 match(Set dst (AndL dst src));
9269 effect(KILL cr);
9270
9271 format %{ "andq $dst, $src\t# long" %}
9272 opcode(0x23);
9273 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9274 ins_pipe(ialu_reg_reg);
9275 %}
9276
9277 // And Register with Immediate 255
9278 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9279 %{
9280 match(Set dst (AndL dst src));
9281
9282 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9283 opcode(0x0F, 0xB6);
9284 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9285 ins_pipe(ialu_reg);
9286 %}
9287
9288 // And Register with Immediate 65535
9289 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9290 %{
9291 match(Set dst (AndL dst src));
9292
9293 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9294 opcode(0x0F, 0xB7);
9295 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9296 ins_pipe(ialu_reg);
9297 %}
9298
9299 // And Register with Immediate
9300 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9301 %{
9302 match(Set dst (AndL dst src));
9303 effect(KILL cr);
9304
9305 format %{ "andq $dst, $src\t# long" %}
9306 opcode(0x81, 0x04); /* Opcode 81 /4 */
9307 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9308 ins_pipe(ialu_reg);
9309 %}
9310
9311 // And Register with Memory
9312 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9313 %{
9314 match(Set dst (AndL dst (LoadL src)));
9315 effect(KILL cr);
9316
9317 ins_cost(125);
9318 format %{ "andq $dst, $src\t# long" %}
9319 opcode(0x23);
9320 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9321 ins_pipe(ialu_reg_mem);
9322 %}
9323
9324 // And Memory with Register
9325 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9326 %{
9327 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9328 effect(KILL cr);
9329
9330 ins_cost(150);
9331 format %{ "andq $dst, $src\t# long" %}
9332 opcode(0x21); /* Opcode 21 /r */
9333 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9334 ins_pipe(ialu_mem_reg);
9335 %}
9336
9337 // And Memory with Immediate
9338 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9339 %{
9340 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9341 effect(KILL cr);
9342
9343 ins_cost(125);
9344 format %{ "andq $dst, $src\t# long" %}
9345 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9346 ins_encode(REX_mem_wide(dst), OpcSE(src),
9347 RM_opc_mem(secondary, dst), Con8or32(src));
9348 ins_pipe(ialu_mem_imm);
9349 %}
9350
9351 // Or Instructions
9352 // Or Register with Register
9353 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9354 %{
9355 match(Set dst (OrL dst src));
9356 effect(KILL cr);
9357
9358 format %{ "orq $dst, $src\t# long" %}
9359 opcode(0x0B);
9360 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9361 ins_pipe(ialu_reg_reg);
9362 %}
9363
9364 // Use any_RegP to match R15 (TLS register) without spilling.
9365 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9366 match(Set dst (OrL dst (CastP2X src)));
9367 effect(KILL cr);
9368
9369 format %{ "orq $dst, $src\t# long" %}
9370 opcode(0x0B);
9371 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9372 ins_pipe(ialu_reg_reg);
9373 %}
9374
9375
9376 // Or Register with Immediate
9377 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9378 %{
9379 match(Set dst (OrL dst src));
9380 effect(KILL cr);
9381
9382 format %{ "orq $dst, $src\t# long" %}
9383 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9384 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9385 ins_pipe(ialu_reg);
9386 %}
9387
9388 // Or Register with Memory
9389 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9390 %{
9391 match(Set dst (OrL dst (LoadL src)));
9392 effect(KILL cr);
9393
9394 ins_cost(125);
9395 format %{ "orq $dst, $src\t# long" %}
9396 opcode(0x0B);
9397 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9398 ins_pipe(ialu_reg_mem);
9399 %}
9400
9401 // Or Memory with Register
9402 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9403 %{
9404 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9405 effect(KILL cr);
9406
9407 ins_cost(150);
9408 format %{ "orq $dst, $src\t# long" %}
9409 opcode(0x09); /* Opcode 09 /r */
9410 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9411 ins_pipe(ialu_mem_reg);
9412 %}
9413
9414 // Or Memory with Immediate
9415 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9416 %{
9417 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9418 effect(KILL cr);
9419
9420 ins_cost(125);
9421 format %{ "orq $dst, $src\t# long" %}
9422 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9423 ins_encode(REX_mem_wide(dst), OpcSE(src),
9424 RM_opc_mem(secondary, dst), Con8or32(src));
9425 ins_pipe(ialu_mem_imm);
9426 %}
9427
9428 // Xor Instructions
9429 // Xor Register with Register
9430 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9431 %{
9432 match(Set dst (XorL dst src));
9433 effect(KILL cr);
9434
9435 format %{ "xorq $dst, $src\t# long" %}
9436 opcode(0x33);
9437 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9438 ins_pipe(ialu_reg_reg);
9439 %}
9440
9441 // Xor Register with Immediate -1
9442 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9443 match(Set dst (XorL dst imm));
9444
9445 format %{ "notq $dst" %}
9446 ins_encode %{
9447 __ notq($dst$$Register);
9448 %}
9449 ins_pipe(ialu_reg);
9450 %}
9451
9452 // Xor Register with Immediate
9453 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9454 %{
9455 match(Set dst (XorL dst src));
9456 effect(KILL cr);
9457
9458 format %{ "xorq $dst, $src\t# long" %}
9459 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9460 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9461 ins_pipe(ialu_reg);
9462 %}
9463
9464 // Xor Register with Memory
9465 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9466 %{
9467 match(Set dst (XorL dst (LoadL src)));
9468 effect(KILL cr);
9469
9470 ins_cost(125);
9471 format %{ "xorq $dst, $src\t# long" %}
9472 opcode(0x33);
9473 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9474 ins_pipe(ialu_reg_mem);
9475 %}
9476
9477 // Xor Memory with Register
9478 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9479 %{
9480 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9481 effect(KILL cr);
9482
9483 ins_cost(150);
9484 format %{ "xorq $dst, $src\t# long" %}
9485 opcode(0x31); /* Opcode 31 /r */
9486 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9487 ins_pipe(ialu_mem_reg);
9488 %}
9489
9490 // Xor Memory with Immediate
9491 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9492 %{
9493 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9494 effect(KILL cr);
9495
9496 ins_cost(125);
9497 format %{ "xorq $dst, $src\t# long" %}
9498 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9499 ins_encode(REX_mem_wide(dst), OpcSE(src),
9500 RM_opc_mem(secondary, dst), Con8or32(src));
9501 ins_pipe(ialu_mem_imm);
9502 %}
9503
9504 // Convert Int to Boolean
9505 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9506 %{
9507 match(Set dst (Conv2B src));
9508 effect(KILL cr);
9509
9510 format %{ "testl $src, $src\t# ci2b\n\t"
9511 "setnz $dst\n\t"
9512 "movzbl $dst, $dst" %}
9513 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9514 setNZ_reg(dst),
9515 REX_reg_breg(dst, dst), // movzbl
9516 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9517 ins_pipe(pipe_slow); // XXX
9518 %}
9519
9520 // Convert Pointer to Boolean
9521 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9522 %{
9523 match(Set dst (Conv2B src));
9524 effect(KILL cr);
9525
9526 format %{ "testq $src, $src\t# cp2b\n\t"
9527 "setnz $dst\n\t"
9528 "movzbl $dst, $dst" %}
9529 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9530 setNZ_reg(dst),
9531 REX_reg_breg(dst, dst), // movzbl
9532 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9533 ins_pipe(pipe_slow); // XXX
9534 %}
9535
9536 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9537 %{
9538 match(Set dst (CmpLTMask p q));
9539 effect(KILL cr);
9540
9541 ins_cost(400); // XXX
9542 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9543 "setlt $dst\n\t"
9544 "movzbl $dst, $dst\n\t"
9545 "negl $dst" %}
9546 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9547 setLT_reg(dst),
9548 REX_reg_breg(dst, dst), // movzbl
9549 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9550 neg_reg(dst));
9551 ins_pipe(pipe_slow);
9552 %}
9553
9554 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9555 %{
9556 match(Set dst (CmpLTMask dst zero));
9557 effect(KILL cr);
9558
9559 ins_cost(100); // XXX
9560 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9561 opcode(0xC1, 0x7); /* C1 /7 ib */
9562 ins_encode(reg_opc_imm(dst, 0x1F));
9563 ins_pipe(ialu_reg);
9564 %}
9565
9566
9567 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
9568 %{
9569 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9570 effect(TEMP tmp, KILL cr);
9571
9572 ins_cost(400); // XXX
9573 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9574 "sbbl $tmp, $tmp\n\t"
9575 "andl $tmp, $y\n\t"
9576 "addl $p, $tmp" %}
9577 ins_encode %{
9578 Register Rp = $p$$Register;
9579 Register Rq = $q$$Register;
9580 Register Ry = $y$$Register;
9581 Register Rt = $tmp$$Register;
9582 __ subl(Rp, Rq);
9583 __ sbbl(Rt, Rt);
9584 __ andl(Rt, Ry);
9585 __ addl(Rp, Rt);
9586 %}
9587 ins_pipe(pipe_cmplt);
9588 %}
9589
9590 //---------- FP Instructions------------------------------------------------
9591
9592 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9593 %{
9594 match(Set cr (CmpF src1 src2));
9595
9596 ins_cost(145);
9597 format %{ "ucomiss $src1, $src2\n\t"
9598 "jnp,s exit\n\t"
9599 "pushfq\t# saw NaN, set CF\n\t"
9600 "andq [rsp], #0xffffff2b\n\t"
9601 "popfq\n"
9602 "exit:" %}
9603 ins_encode %{
9604 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9605 emit_cmpfp_fixup(_masm);
9606 %}
9607 ins_pipe(pipe_slow);
9608 %}
9609
9610 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9611 match(Set cr (CmpF src1 src2));
9612
9613 ins_cost(100);
9614 format %{ "ucomiss $src1, $src2" %}
9615 ins_encode %{
9616 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9617 %}
9618 ins_pipe(pipe_slow);
9619 %}
9620
9621 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9622 %{
9623 match(Set cr (CmpF src1 (LoadF src2)));
9624
9625 ins_cost(145);
9626 format %{ "ucomiss $src1, $src2\n\t"
9627 "jnp,s exit\n\t"
9628 "pushfq\t# saw NaN, set CF\n\t"
9629 "andq [rsp], #0xffffff2b\n\t"
9630 "popfq\n"
9631 "exit:" %}
9632 ins_encode %{
9633 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9634 emit_cmpfp_fixup(_masm);
9635 %}
9636 ins_pipe(pipe_slow);
9637 %}
9638
9639 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9640 match(Set cr (CmpF src1 (LoadF src2)));
9641
9642 ins_cost(100);
9643 format %{ "ucomiss $src1, $src2" %}
9644 ins_encode %{
9645 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9646 %}
9647 ins_pipe(pipe_slow);
9648 %}
9649
9650 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9651 match(Set cr (CmpF src con));
9652
9653 ins_cost(145);
9654 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9655 "jnp,s exit\n\t"
9656 "pushfq\t# saw NaN, set CF\n\t"
9657 "andq [rsp], #0xffffff2b\n\t"
9658 "popfq\n"
9659 "exit:" %}
9660 ins_encode %{
9661 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9662 emit_cmpfp_fixup(_masm);
9663 %}
9664 ins_pipe(pipe_slow);
9665 %}
9666
9667 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9668 match(Set cr (CmpF src con));
9669 ins_cost(100);
9670 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9671 ins_encode %{
9672 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9673 %}
9674 ins_pipe(pipe_slow);
9675 %}
9676
9677 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9678 %{
9679 match(Set cr (CmpD src1 src2));
9680
9681 ins_cost(145);
9682 format %{ "ucomisd $src1, $src2\n\t"
9683 "jnp,s exit\n\t"
9684 "pushfq\t# saw NaN, set CF\n\t"
9685 "andq [rsp], #0xffffff2b\n\t"
9686 "popfq\n"
9687 "exit:" %}
9688 ins_encode %{
9689 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9690 emit_cmpfp_fixup(_masm);
9691 %}
9692 ins_pipe(pipe_slow);
9693 %}
9694
9695 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9696 match(Set cr (CmpD src1 src2));
9697
9698 ins_cost(100);
9699 format %{ "ucomisd $src1, $src2 test" %}
9700 ins_encode %{
9701 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9702 %}
9703 ins_pipe(pipe_slow);
9704 %}
9705
9706 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9707 %{
9708 match(Set cr (CmpD src1 (LoadD src2)));
9709
9710 ins_cost(145);
9711 format %{ "ucomisd $src1, $src2\n\t"
9712 "jnp,s exit\n\t"
9713 "pushfq\t# saw NaN, set CF\n\t"
9714 "andq [rsp], #0xffffff2b\n\t"
9715 "popfq\n"
9716 "exit:" %}
9717 ins_encode %{
9718 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9719 emit_cmpfp_fixup(_masm);
9720 %}
9721 ins_pipe(pipe_slow);
9722 %}
9723
9724 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9725 match(Set cr (CmpD src1 (LoadD src2)));
9726
9727 ins_cost(100);
9728 format %{ "ucomisd $src1, $src2" %}
9729 ins_encode %{
9730 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9731 %}
9732 ins_pipe(pipe_slow);
9733 %}
9734
9735 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9736 match(Set cr (CmpD src con));
9737
9738 ins_cost(145);
9739 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9740 "jnp,s exit\n\t"
9741 "pushfq\t# saw NaN, set CF\n\t"
9742 "andq [rsp], #0xffffff2b\n\t"
9743 "popfq\n"
9744 "exit:" %}
9745 ins_encode %{
9746 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9747 emit_cmpfp_fixup(_masm);
9748 %}
9749 ins_pipe(pipe_slow);
9750 %}
9751
9752 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9753 match(Set cr (CmpD src con));
9754 ins_cost(100);
9755 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9756 ins_encode %{
9757 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9758 %}
9759 ins_pipe(pipe_slow);
9760 %}
9761
9762 // Compare into -1,0,1
9763 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9764 %{
9765 match(Set dst (CmpF3 src1 src2));
9766 effect(KILL cr);
9767
9768 ins_cost(275);
9769 format %{ "ucomiss $src1, $src2\n\t"
9770 "movl $dst, #-1\n\t"
9771 "jp,s done\n\t"
9772 "jb,s done\n\t"
9773 "setne $dst\n\t"
9774 "movzbl $dst, $dst\n"
9775 "done:" %}
9776 ins_encode %{
9777 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9778 emit_cmpfp3(_masm, $dst$$Register);
9779 %}
9780 ins_pipe(pipe_slow);
9781 %}
9782
9783 // Compare into -1,0,1
9784 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9785 %{
9786 match(Set dst (CmpF3 src1 (LoadF src2)));
9787 effect(KILL cr);
9788
9789 ins_cost(275);
9790 format %{ "ucomiss $src1, $src2\n\t"
9791 "movl $dst, #-1\n\t"
9792 "jp,s done\n\t"
9793 "jb,s done\n\t"
9794 "setne $dst\n\t"
9795 "movzbl $dst, $dst\n"
9796 "done:" %}
9797 ins_encode %{
9798 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9799 emit_cmpfp3(_masm, $dst$$Register);
9800 %}
9801 ins_pipe(pipe_slow);
9802 %}
9803
9804 // Compare into -1,0,1
9805 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9806 match(Set dst (CmpF3 src con));
9807 effect(KILL cr);
9808
9809 ins_cost(275);
9810 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9811 "movl $dst, #-1\n\t"
9812 "jp,s done\n\t"
9813 "jb,s done\n\t"
9814 "setne $dst\n\t"
9815 "movzbl $dst, $dst\n"
9816 "done:" %}
9817 ins_encode %{
9818 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9819 emit_cmpfp3(_masm, $dst$$Register);
9820 %}
9821 ins_pipe(pipe_slow);
9822 %}
9823
9824 // Compare into -1,0,1
9825 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9826 %{
9827 match(Set dst (CmpD3 src1 src2));
9828 effect(KILL cr);
9829
9830 ins_cost(275);
9831 format %{ "ucomisd $src1, $src2\n\t"
9832 "movl $dst, #-1\n\t"
9833 "jp,s done\n\t"
9834 "jb,s done\n\t"
9835 "setne $dst\n\t"
9836 "movzbl $dst, $dst\n"
9837 "done:" %}
9838 ins_encode %{
9839 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9840 emit_cmpfp3(_masm, $dst$$Register);
9841 %}
9842 ins_pipe(pipe_slow);
9843 %}
9844
9845 // Compare into -1,0,1
9846 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9847 %{
9848 match(Set dst (CmpD3 src1 (LoadD src2)));
9849 effect(KILL cr);
9850
9851 ins_cost(275);
9852 format %{ "ucomisd $src1, $src2\n\t"
9853 "movl $dst, #-1\n\t"
9854 "jp,s done\n\t"
9855 "jb,s done\n\t"
9856 "setne $dst\n\t"
9857 "movzbl $dst, $dst\n"
9858 "done:" %}
9859 ins_encode %{
9860 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9861 emit_cmpfp3(_masm, $dst$$Register);
9862 %}
9863 ins_pipe(pipe_slow);
9864 %}
9865
9866 // Compare into -1,0,1
9867 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9868 match(Set dst (CmpD3 src con));
9869 effect(KILL cr);
9870
9871 ins_cost(275);
9872 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9873 "movl $dst, #-1\n\t"
9874 "jp,s done\n\t"
9875 "jb,s done\n\t"
9876 "setne $dst\n\t"
9877 "movzbl $dst, $dst\n"
9878 "done:" %}
9879 ins_encode %{
9880 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9881 emit_cmpfp3(_masm, $dst$$Register);
9882 %}
9883 ins_pipe(pipe_slow);
9884 %}
9885
9886 // -----------Trig and Trancendental Instructions------------------------------
9887 instruct cosD_reg(regD dst) %{
9888 match(Set dst (CosD dst));
9889
9890 format %{ "dcos $dst\n\t" %}
9891 opcode(0xD9, 0xFF);
9892 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9893 ins_pipe( pipe_slow );
9894 %}
9895
9896 instruct sinD_reg(regD dst) %{
9897 match(Set dst (SinD dst));
9898
9899 format %{ "dsin $dst\n\t" %}
9900 opcode(0xD9, 0xFE);
9901 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9902 ins_pipe( pipe_slow );
9903 %}
9904
9905 instruct tanD_reg(regD dst) %{
9906 match(Set dst (TanD dst));
9907
9908 format %{ "dtan $dst\n\t" %}
9909 ins_encode( Push_SrcXD(dst),
9910 Opcode(0xD9), Opcode(0xF2), //fptan
9911 Opcode(0xDD), Opcode(0xD8), //fstp st
9912 Push_ResultXD(dst) );
9913 ins_pipe( pipe_slow );
9914 %}
9915
9916 instruct log10D_reg(regD dst) %{
9917 // The source and result Double operands in XMM registers
9918 match(Set dst (Log10D dst));
9919 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9920 // fyl2x ; compute log_10(2) * log_2(x)
9921 format %{ "fldlg2\t\t\t#Log10\n\t"
9922 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9923 %}
9924 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9925 Push_SrcXD(dst),
9926 Opcode(0xD9), Opcode(0xF1), // fyl2x
9927 Push_ResultXD(dst));
9928
9929 ins_pipe( pipe_slow );
9930 %}
9931
9932 instruct logD_reg(regD dst) %{
9933 // The source and result Double operands in XMM registers
9934 match(Set dst (LogD dst));
9935 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9936 // fyl2x ; compute log_e(2) * log_2(x)
9937 format %{ "fldln2\t\t\t#Log_e\n\t"
9938 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9939 %}
9940 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9941 Push_SrcXD(dst),
9942 Opcode(0xD9), Opcode(0xF1), // fyl2x
9943 Push_ResultXD(dst));
9944 ins_pipe( pipe_slow );
9945 %}
9946
9947
9948
9949 //----------Arithmetic Conversion Instructions---------------------------------
9950
9951 instruct roundFloat_nop(regF dst)
9952 %{
9953 match(Set dst (RoundFloat dst));
9954
9955 ins_cost(0);
9956 ins_encode();
9957 ins_pipe(empty);
9958 %}
9959
9960 instruct roundDouble_nop(regD dst)
9961 %{
9962 match(Set dst (RoundDouble dst));
9963
9964 ins_cost(0);
9965 ins_encode();
9966 ins_pipe(empty);
9967 %}
9968
9969 instruct convF2D_reg_reg(regD dst, regF src)
9970 %{
9971 match(Set dst (ConvF2D src));
9972
9973 format %{ "cvtss2sd $dst, $src" %}
9974 ins_encode %{
9975 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9976 %}
9977 ins_pipe(pipe_slow); // XXX
9978 %}
9979
9980 instruct convF2D_reg_mem(regD dst, memory src)
9981 %{
9982 match(Set dst (ConvF2D (LoadF src)));
9983
9984 format %{ "cvtss2sd $dst, $src" %}
9985 ins_encode %{
9986 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9987 %}
9988 ins_pipe(pipe_slow); // XXX
9989 %}
9990
9991 instruct convD2F_reg_reg(regF dst, regD src)
9992 %{
9993 match(Set dst (ConvD2F src));
9994
9995 format %{ "cvtsd2ss $dst, $src" %}
9996 ins_encode %{
9997 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9998 %}
9999 ins_pipe(pipe_slow); // XXX
10000 %}
10001
10002 instruct convD2F_reg_mem(regF dst, memory src)
10003 %{
10004 match(Set dst (ConvD2F (LoadD src)));
10005
10006 format %{ "cvtsd2ss $dst, $src" %}
10007 ins_encode %{
10008 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10009 %}
10010 ins_pipe(pipe_slow); // XXX
10011 %}
10012
10013 // XXX do mem variants
10014 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10015 %{
10016 match(Set dst (ConvF2I src));
10017 effect(KILL cr);
10018
10019 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10020 "cmpl $dst, #0x80000000\n\t"
10021 "jne,s done\n\t"
10022 "subq rsp, #8\n\t"
10023 "movss [rsp], $src\n\t"
10024 "call f2i_fixup\n\t"
10025 "popq $dst\n"
10026 "done: "%}
10027 ins_encode %{
10028 Label done;
10029 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10030 __ cmpl($dst$$Register, 0x80000000);
10031 __ jccb(Assembler::notEqual, done);
10032 __ subptr(rsp, 8);
10033 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10034 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10035 __ pop($dst$$Register);
10036 __ bind(done);
10037 %}
10038 ins_pipe(pipe_slow);
10039 %}
10040
10041 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10042 %{
10043 match(Set dst (ConvF2L src));
10044 effect(KILL cr);
10045
10046 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10047 "cmpq $dst, [0x8000000000000000]\n\t"
10048 "jne,s done\n\t"
10049 "subq rsp, #8\n\t"
10050 "movss [rsp], $src\n\t"
10051 "call f2l_fixup\n\t"
10052 "popq $dst\n"
10053 "done: "%}
10054 ins_encode %{
10055 Label done;
10056 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10057 __ cmp64($dst$$Register,
10058 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10059 __ jccb(Assembler::notEqual, done);
10060 __ subptr(rsp, 8);
10061 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10062 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10063 __ pop($dst$$Register);
10064 __ bind(done);
10065 %}
10066 ins_pipe(pipe_slow);
10067 %}
10068
10069 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10070 %{
10071 match(Set dst (ConvD2I src));
10072 effect(KILL cr);
10073
10074 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10075 "cmpl $dst, #0x80000000\n\t"
10076 "jne,s done\n\t"
10077 "subq rsp, #8\n\t"
10078 "movsd [rsp], $src\n\t"
10079 "call d2i_fixup\n\t"
10080 "popq $dst\n"
10081 "done: "%}
10082 ins_encode %{
10083 Label done;
10084 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10085 __ cmpl($dst$$Register, 0x80000000);
10086 __ jccb(Assembler::notEqual, done);
10087 __ subptr(rsp, 8);
10088 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10089 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10090 __ pop($dst$$Register);
10091 __ bind(done);
10092 %}
10093 ins_pipe(pipe_slow);
10094 %}
10095
10096 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10097 %{
10098 match(Set dst (ConvD2L src));
10099 effect(KILL cr);
10100
10101 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10102 "cmpq $dst, [0x8000000000000000]\n\t"
10103 "jne,s done\n\t"
10104 "subq rsp, #8\n\t"
10105 "movsd [rsp], $src\n\t"
10106 "call d2l_fixup\n\t"
10107 "popq $dst\n"
10108 "done: "%}
10109 ins_encode %{
10110 Label done;
10111 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10112 __ cmp64($dst$$Register,
10113 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10114 __ jccb(Assembler::notEqual, done);
10115 __ subptr(rsp, 8);
10116 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10117 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10118 __ pop($dst$$Register);
10119 __ bind(done);
10120 %}
10121 ins_pipe(pipe_slow);
10122 %}
10123
10124 instruct convI2F_reg_reg(regF dst, rRegI src)
10125 %{
10126 predicate(!UseXmmI2F);
10127 match(Set dst (ConvI2F src));
10128
10129 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10130 ins_encode %{
10131 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10132 %}
10133 ins_pipe(pipe_slow); // XXX
10134 %}
10135
10136 instruct convI2F_reg_mem(regF dst, memory src)
10137 %{
10138 match(Set dst (ConvI2F (LoadI src)));
10139
10140 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10141 ins_encode %{
10142 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10143 %}
10144 ins_pipe(pipe_slow); // XXX
10145 %}
10146
10147 instruct convI2D_reg_reg(regD dst, rRegI src)
10148 %{
10149 predicate(!UseXmmI2D);
10150 match(Set dst (ConvI2D src));
10151
10152 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10153 ins_encode %{
10154 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10155 %}
10156 ins_pipe(pipe_slow); // XXX
10157 %}
10158
10159 instruct convI2D_reg_mem(regD dst, memory src)
10160 %{
10161 match(Set dst (ConvI2D (LoadI src)));
10162
10163 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10164 ins_encode %{
10165 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10166 %}
10167 ins_pipe(pipe_slow); // XXX
10168 %}
10169
10170 instruct convXI2F_reg(regF dst, rRegI src)
10171 %{
10172 predicate(UseXmmI2F);
10173 match(Set dst (ConvI2F src));
10174
10175 format %{ "movdl $dst, $src\n\t"
10176 "cvtdq2psl $dst, $dst\t# i2f" %}
10177 ins_encode %{
10178 __ movdl($dst$$XMMRegister, $src$$Register);
10179 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10180 %}
10181 ins_pipe(pipe_slow); // XXX
10182 %}
10183
10184 instruct convXI2D_reg(regD dst, rRegI src)
10185 %{
10186 predicate(UseXmmI2D);
10187 match(Set dst (ConvI2D src));
10188
10189 format %{ "movdl $dst, $src\n\t"
10190 "cvtdq2pdl $dst, $dst\t# i2d" %}
10191 ins_encode %{
10192 __ movdl($dst$$XMMRegister, $src$$Register);
10193 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10194 %}
10195 ins_pipe(pipe_slow); // XXX
10196 %}
10197
10198 instruct convL2F_reg_reg(regF dst, rRegL src)
10199 %{
10200 match(Set dst (ConvL2F src));
10201
10202 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10203 ins_encode %{
10204 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10205 %}
10206 ins_pipe(pipe_slow); // XXX
10207 %}
10208
10209 instruct convL2F_reg_mem(regF dst, memory src)
10210 %{
10211 match(Set dst (ConvL2F (LoadL src)));
10212
10213 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10214 ins_encode %{
10215 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10216 %}
10217 ins_pipe(pipe_slow); // XXX
10218 %}
10219
10220 instruct convL2D_reg_reg(regD dst, rRegL src)
10221 %{
10222 match(Set dst (ConvL2D src));
10223
10224 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10225 ins_encode %{
10226 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10227 %}
10228 ins_pipe(pipe_slow); // XXX
10229 %}
10230
10231 instruct convL2D_reg_mem(regD dst, memory src)
10232 %{
10233 match(Set dst (ConvL2D (LoadL src)));
10234
10235 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10236 ins_encode %{
10237 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10238 %}
10239 ins_pipe(pipe_slow); // XXX
10240 %}
10241
10242 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10243 %{
10244 match(Set dst (ConvI2L src));
10245
10246 ins_cost(125);
10247 format %{ "movslq $dst, $src\t# i2l" %}
10248 ins_encode %{
10249 __ movslq($dst$$Register, $src$$Register);
10250 %}
10251 ins_pipe(ialu_reg_reg);
10252 %}
10253
10254 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10255 // %{
10256 // match(Set dst (ConvI2L src));
10257 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10258 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10259 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10260 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10261 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10262 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10263
10264 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10265 // ins_encode(enc_copy(dst, src));
10266 // // opcode(0x63); // needs REX.W
10267 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10268 // ins_pipe(ialu_reg_reg);
10269 // %}
10270
10271 // Zero-extend convert int to long
10272 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10273 %{
10274 match(Set dst (AndL (ConvI2L src) mask));
10275
10276 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10277 ins_encode %{
10278 if ($dst$$reg != $src$$reg) {
10279 __ movl($dst$$Register, $src$$Register);
10280 }
10281 %}
10282 ins_pipe(ialu_reg_reg);
10283 %}
10284
10285 // Zero-extend convert int to long
10286 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10287 %{
10288 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10289
10290 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10291 ins_encode %{
10292 __ movl($dst$$Register, $src$$Address);
10293 %}
10294 ins_pipe(ialu_reg_mem);
10295 %}
10296
10297 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10298 %{
10299 match(Set dst (AndL src mask));
10300
10301 format %{ "movl $dst, $src\t# zero-extend long" %}
10302 ins_encode %{
10303 __ movl($dst$$Register, $src$$Register);
10304 %}
10305 ins_pipe(ialu_reg_reg);
10306 %}
10307
10308 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10309 %{
10310 match(Set dst (ConvL2I src));
10311
10312 format %{ "movl $dst, $src\t# l2i" %}
10313 ins_encode %{
10314 __ movl($dst$$Register, $src$$Register);
10315 %}
10316 ins_pipe(ialu_reg_reg);
10317 %}
10318
10319
10320 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10321 match(Set dst (MoveF2I src));
10322 effect(DEF dst, USE src);
10323
10324 ins_cost(125);
10325 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10326 ins_encode %{
10327 __ movl($dst$$Register, Address(rsp, $src$$disp));
10328 %}
10329 ins_pipe(ialu_reg_mem);
10330 %}
10331
10332 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10333 match(Set dst (MoveI2F src));
10334 effect(DEF dst, USE src);
10335
10336 ins_cost(125);
10337 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10338 ins_encode %{
10339 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10340 %}
10341 ins_pipe(pipe_slow);
10342 %}
10343
10344 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10345 match(Set dst (MoveD2L src));
10346 effect(DEF dst, USE src);
10347
10348 ins_cost(125);
10349 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10350 ins_encode %{
10351 __ movq($dst$$Register, Address(rsp, $src$$disp));
10352 %}
10353 ins_pipe(ialu_reg_mem);
10354 %}
10355
10356 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10357 predicate(!UseXmmLoadAndClearUpper);
10358 match(Set dst (MoveL2D src));
10359 effect(DEF dst, USE src);
10360
10361 ins_cost(125);
10362 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10363 ins_encode %{
10364 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10365 %}
10366 ins_pipe(pipe_slow);
10367 %}
10368
10369 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10370 predicate(UseXmmLoadAndClearUpper);
10371 match(Set dst (MoveL2D src));
10372 effect(DEF dst, USE src);
10373
10374 ins_cost(125);
10375 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10376 ins_encode %{
10377 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10378 %}
10379 ins_pipe(pipe_slow);
10380 %}
10381
10382
10383 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10384 match(Set dst (MoveF2I src));
10385 effect(DEF dst, USE src);
10386
10387 ins_cost(95); // XXX
10388 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10389 ins_encode %{
10390 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10391 %}
10392 ins_pipe(pipe_slow);
10393 %}
10394
10395 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10396 match(Set dst (MoveI2F src));
10397 effect(DEF dst, USE src);
10398
10399 ins_cost(100);
10400 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10401 ins_encode %{
10402 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10403 %}
10404 ins_pipe( ialu_mem_reg );
10405 %}
10406
10407 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10408 match(Set dst (MoveD2L src));
10409 effect(DEF dst, USE src);
10410
10411 ins_cost(95); // XXX
10412 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10413 ins_encode %{
10414 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10415 %}
10416 ins_pipe(pipe_slow);
10417 %}
10418
10419 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10420 match(Set dst (MoveL2D src));
10421 effect(DEF dst, USE src);
10422
10423 ins_cost(100);
10424 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10425 ins_encode %{
10426 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10427 %}
10428 ins_pipe(ialu_mem_reg);
10429 %}
10430
10431 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10432 match(Set dst (MoveF2I src));
10433 effect(DEF dst, USE src);
10434 ins_cost(85);
10435 format %{ "movd $dst,$src\t# MoveF2I" %}
10436 ins_encode %{
10437 __ movdl($dst$$Register, $src$$XMMRegister);
10438 %}
10439 ins_pipe( pipe_slow );
10440 %}
10441
10442 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10443 match(Set dst (MoveD2L src));
10444 effect(DEF dst, USE src);
10445 ins_cost(85);
10446 format %{ "movd $dst,$src\t# MoveD2L" %}
10447 ins_encode %{
10448 __ movdq($dst$$Register, $src$$XMMRegister);
10449 %}
10450 ins_pipe( pipe_slow );
10451 %}
10452
10453 // The next instructions have long latency and use Int unit. Set high cost.
10454 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10455 match(Set dst (MoveI2F src));
10456 effect(DEF dst, USE src);
10457 ins_cost(300);
10458 format %{ "movd $dst,$src\t# MoveI2F" %}
10459 ins_encode %{
10460 __ movdl($dst$$XMMRegister, $src$$Register);
10461 %}
10462 ins_pipe( pipe_slow );
10463 %}
10464
10465 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10466 match(Set dst (MoveL2D src));
10467 effect(DEF dst, USE src);
10468 ins_cost(300);
10469 format %{ "movd $dst,$src\t# MoveL2D" %}
10470 ins_encode %{
10471 __ movdq($dst$$XMMRegister, $src$$Register);
10472 %}
10473 ins_pipe( pipe_slow );
10474 %}
10475
10476 // Replicate scalar to packed byte (1 byte) values in xmm
10477 instruct Repl8B_reg(regD dst, regD src) %{
10478 match(Set dst (Replicate8B src));
10479 format %{ "MOVDQA $dst,$src\n\t"
10480 "PUNPCKLBW $dst,$dst\n\t"
10481 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10482 ins_encode %{
10483 if ($dst$$reg != $src$$reg) {
10484 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
10485 }
10486 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
10487 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10488 %}
10489 ins_pipe( pipe_slow );
10490 %}
10491
10492 // Replicate scalar to packed byte (1 byte) values in xmm
10493 instruct Repl8B_rRegI(regD dst, rRegI src) %{
10494 match(Set dst (Replicate8B src));
10495 format %{ "MOVD $dst,$src\n\t"
10496 "PUNPCKLBW $dst,$dst\n\t"
10497 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10498 ins_encode %{
10499 __ movdl($dst$$XMMRegister, $src$$Register);
10500 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
10501 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10502 %}
10503 ins_pipe( pipe_slow );
10504 %}
10505
10506 // Replicate scalar zero to packed byte (1 byte) values in xmm
10507 instruct Repl8B_immI0(regD dst, immI0 zero) %{
10508 match(Set dst (Replicate8B zero));
10509 format %{ "PXOR $dst,$dst\t! replicate8B" %}
10510 ins_encode %{
10511 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10512 %}
10513 ins_pipe( fpu_reg_reg );
10514 %}
10515
10516 // Replicate scalar to packed shore (2 byte) values in xmm
10517 instruct Repl4S_reg(regD dst, regD src) %{
10518 match(Set dst (Replicate4S src));
10519 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
10520 ins_encode %{
10521 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10522 %}
10523 ins_pipe( fpu_reg_reg );
10524 %}
10525
10526 // Replicate scalar to packed shore (2 byte) values in xmm
10527 instruct Repl4S_rRegI(regD dst, rRegI src) %{
10528 match(Set dst (Replicate4S src));
10529 format %{ "MOVD $dst,$src\n\t"
10530 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
10531 ins_encode %{
10532 __ movdl($dst$$XMMRegister, $src$$Register);
10533 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10534 %}
10535 ins_pipe( fpu_reg_reg );
10536 %}
10537
10538 // Replicate scalar zero to packed short (2 byte) values in xmm
10539 instruct Repl4S_immI0(regD dst, immI0 zero) %{
10540 match(Set dst (Replicate4S zero));
10541 format %{ "PXOR $dst,$dst\t! replicate4S" %}
10542 ins_encode %{
10543 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10544 %}
10545 ins_pipe( fpu_reg_reg );
10546 %}
10547
10548 // Replicate scalar to packed char (2 byte) values in xmm
10549 instruct Repl4C_reg(regD dst, regD src) %{
10550 match(Set dst (Replicate4C src));
10551 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
10552 ins_encode %{
10553 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10554 %}
10555 ins_pipe( fpu_reg_reg );
10556 %}
10557
10558 // Replicate scalar to packed char (2 byte) values in xmm
10559 instruct Repl4C_rRegI(regD dst, rRegI src) %{
10560 match(Set dst (Replicate4C src));
10561 format %{ "MOVD $dst,$src\n\t"
10562 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
10563 ins_encode %{
10564 __ movdl($dst$$XMMRegister, $src$$Register);
10565 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10566 %}
10567 ins_pipe( fpu_reg_reg );
10568 %}
10569
10570 // Replicate scalar zero to packed char (2 byte) values in xmm
10571 instruct Repl4C_immI0(regD dst, immI0 zero) %{
10572 match(Set dst (Replicate4C zero));
10573 format %{ "PXOR $dst,$dst\t! replicate4C" %}
10574 ins_encode %{
10575 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10576 %}
10577 ins_pipe( fpu_reg_reg );
10578 %}
10579
10580 // Replicate scalar to packed integer (4 byte) values in xmm
10581 instruct Repl2I_reg(regD dst, regD src) %{
10582 match(Set dst (Replicate2I src));
10583 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
10584 ins_encode %{
10585 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
10586 %}
10587 ins_pipe( fpu_reg_reg );
10588 %}
10589
10590 // Replicate scalar to packed integer (4 byte) values in xmm
10591 instruct Repl2I_rRegI(regD dst, rRegI src) %{
10592 match(Set dst (Replicate2I src));
10593 format %{ "MOVD $dst,$src\n\t"
10594 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
10595 ins_encode %{
10596 __ movdl($dst$$XMMRegister, $src$$Register);
10597 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
10598 %}
10599 ins_pipe( fpu_reg_reg );
10600 %}
10601
10602 // Replicate scalar zero to packed integer (2 byte) values in xmm
10603 instruct Repl2I_immI0(regD dst, immI0 zero) %{
10604 match(Set dst (Replicate2I zero));
10605 format %{ "PXOR $dst,$dst\t! replicate2I" %}
10606 ins_encode %{
10607 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10608 %}
10609 ins_pipe( fpu_reg_reg );
10610 %}
10611
10612 // Replicate scalar to packed single precision floating point values in xmm
10613 instruct Repl2F_reg(regD dst, regD src) %{
10614 match(Set dst (Replicate2F src));
10615 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10616 ins_encode %{
10617 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
10618 %}
10619 ins_pipe( fpu_reg_reg );
10620 %}
10621
10622 // Replicate scalar to packed single precision floating point values in xmm
10623 instruct Repl2F_regF(regD dst, regF src) %{
10624 match(Set dst (Replicate2F src));
10625 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10626 ins_encode %{
10627 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
10628 %}
10629 ins_pipe( fpu_reg_reg );
10630 %}
10631
10632 // Replicate scalar to packed single precision floating point values in xmm
10633 instruct Repl2F_immF0(regD dst, immF0 zero) %{
10634 match(Set dst (Replicate2F zero));
10635 format %{ "PXOR $dst,$dst\t! replicate2F" %}
10636 ins_encode %{
10637 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10638 %}
10639 ins_pipe( fpu_reg_reg );
10640 %}
10641
10642
10643 // =======================================================================
10644 // fast clearing of an array
10645 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10646 rFlagsReg cr)
10647 %{
10648 match(Set dummy (ClearArray cnt base));
10649 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10650
10651 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10652 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10653 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10654 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10655 ins_pipe(pipe_slow);
10656 %}
10657
10658 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10659 rax_RegI result, regD tmp1, rFlagsReg cr)
10660 %{
10661 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10662 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10663
10664 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10665 ins_encode %{
10666 __ string_compare($str1$$Register, $str2$$Register,
10667 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10668 $tmp1$$XMMRegister);
10669 %}
10670 ins_pipe( pipe_slow );
10671 %}
10672
10673 // fast search of substring with known size.
10674 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10675 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10676 %{
10677 predicate(UseSSE42Intrinsics);
10678 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10679 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10680
10681 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10682 ins_encode %{
10683 int icnt2 = (int)$int_cnt2$$constant;
10684 if (icnt2 >= 8) {
10685 // IndexOf for constant substrings with size >= 8 elements
10686 // which don't need to be loaded through stack.
10687 __ string_indexofC8($str1$$Register, $str2$$Register,
10688 $cnt1$$Register, $cnt2$$Register,
10689 icnt2, $result$$Register,
10690 $vec$$XMMRegister, $tmp$$Register);
10691 } else {
10692 // Small strings are loaded through stack if they cross page boundary.
10693 __ string_indexof($str1$$Register, $str2$$Register,
10694 $cnt1$$Register, $cnt2$$Register,
10695 icnt2, $result$$Register,
10696 $vec$$XMMRegister, $tmp$$Register);
10697 }
10698 %}
10699 ins_pipe( pipe_slow );
10700 %}
10701
10702 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10703 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10704 %{
10705 predicate(UseSSE42Intrinsics);
10706 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10707 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10708
10709 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10710 ins_encode %{
10711 __ string_indexof($str1$$Register, $str2$$Register,
10712 $cnt1$$Register, $cnt2$$Register,
10713 (-1), $result$$Register,
10714 $vec$$XMMRegister, $tmp$$Register);
10715 %}
10716 ins_pipe( pipe_slow );
10717 %}
10718
10719 // fast string equals
10720 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10721 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10722 %{
10723 match(Set result (StrEquals (Binary str1 str2) cnt));
10724 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10725
10726 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10727 ins_encode %{
10728 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10729 $cnt$$Register, $result$$Register, $tmp3$$Register,
10730 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10731 %}
10732 ins_pipe( pipe_slow );
10733 %}
10734
10735 // fast array equals
10736 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10737 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10738 %{
10739 match(Set result (AryEq ary1 ary2));
10740 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10741 //ins_cost(300);
10742
10743 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10744 ins_encode %{
10745 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10746 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10747 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10748 %}
10749 ins_pipe( pipe_slow );
10750 %}
10751
10752 //----------Control Flow Instructions------------------------------------------
10753 // Signed compare Instructions
10754
10755 // XXX more variants!!
10756 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10757 %{
10758 match(Set cr (CmpI op1 op2));
10759 effect(DEF cr, USE op1, USE op2);
10760
10761 format %{ "cmpl $op1, $op2" %}
10762 opcode(0x3B); /* Opcode 3B /r */
10763 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10764 ins_pipe(ialu_cr_reg_reg);
10765 %}
10766
10767 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10768 %{
10769 match(Set cr (CmpI op1 op2));
10770
10771 format %{ "cmpl $op1, $op2" %}
10772 opcode(0x81, 0x07); /* Opcode 81 /7 */
10773 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10774 ins_pipe(ialu_cr_reg_imm);
10775 %}
10776
10777 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10778 %{
10779 match(Set cr (CmpI op1 (LoadI op2)));
10780
10781 ins_cost(500); // XXX
10782 format %{ "cmpl $op1, $op2" %}
10783 opcode(0x3B); /* Opcode 3B /r */
10784 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10785 ins_pipe(ialu_cr_reg_mem);
10786 %}
10787
10788 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10789 %{
10790 match(Set cr (CmpI src zero));
10791
10792 format %{ "testl $src, $src" %}
10793 opcode(0x85);
10794 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10795 ins_pipe(ialu_cr_reg_imm);
10796 %}
10797
10798 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10799 %{
10800 match(Set cr (CmpI (AndI src con) zero));
10801
10802 format %{ "testl $src, $con" %}
10803 opcode(0xF7, 0x00);
10804 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10805 ins_pipe(ialu_cr_reg_imm);
10806 %}
10807
10808 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10809 %{
10810 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10811
10812 format %{ "testl $src, $mem" %}
10813 opcode(0x85);
10814 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10815 ins_pipe(ialu_cr_reg_mem);
10816 %}
10817
10818 // Unsigned compare Instructions; really, same as signed except they
10819 // produce an rFlagsRegU instead of rFlagsReg.
10820 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10821 %{
10822 match(Set cr (CmpU op1 op2));
10823
10824 format %{ "cmpl $op1, $op2\t# unsigned" %}
10825 opcode(0x3B); /* Opcode 3B /r */
10826 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10827 ins_pipe(ialu_cr_reg_reg);
10828 %}
10829
10830 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10831 %{
10832 match(Set cr (CmpU op1 op2));
10833
10834 format %{ "cmpl $op1, $op2\t# unsigned" %}
10835 opcode(0x81,0x07); /* Opcode 81 /7 */
10836 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10837 ins_pipe(ialu_cr_reg_imm);
10838 %}
10839
10840 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10841 %{
10842 match(Set cr (CmpU op1 (LoadI op2)));
10843
10844 ins_cost(500); // XXX
10845 format %{ "cmpl $op1, $op2\t# unsigned" %}
10846 opcode(0x3B); /* Opcode 3B /r */
10847 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10848 ins_pipe(ialu_cr_reg_mem);
10849 %}
10850
10851 // // // Cisc-spilled version of cmpU_rReg
10852 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10853 // //%{
10854 // // match(Set cr (CmpU (LoadI op1) op2));
10855 // //
10856 // // format %{ "CMPu $op1,$op2" %}
10857 // // ins_cost(500);
10858 // // opcode(0x39); /* Opcode 39 /r */
10859 // // ins_encode( OpcP, reg_mem( op1, op2) );
10860 // //%}
10861
10862 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10863 %{
10864 match(Set cr (CmpU src zero));
10865
10866 format %{ "testl $src, $src\t# unsigned" %}
10867 opcode(0x85);
10868 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10869 ins_pipe(ialu_cr_reg_imm);
10870 %}
10871
10872 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10873 %{
10874 match(Set cr (CmpP op1 op2));
10875
10876 format %{ "cmpq $op1, $op2\t# ptr" %}
10877 opcode(0x3B); /* Opcode 3B /r */
10878 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10879 ins_pipe(ialu_cr_reg_reg);
10880 %}
10881
10882 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10883 %{
10884 match(Set cr (CmpP op1 (LoadP op2)));
10885
10886 ins_cost(500); // XXX
10887 format %{ "cmpq $op1, $op2\t# ptr" %}
10888 opcode(0x3B); /* Opcode 3B /r */
10889 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10890 ins_pipe(ialu_cr_reg_mem);
10891 %}
10892
10893 // // // Cisc-spilled version of cmpP_rReg
10894 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10895 // //%{
10896 // // match(Set cr (CmpP (LoadP op1) op2));
10897 // //
10898 // // format %{ "CMPu $op1,$op2" %}
10899 // // ins_cost(500);
10900 // // opcode(0x39); /* Opcode 39 /r */
10901 // // ins_encode( OpcP, reg_mem( op1, op2) );
10902 // //%}
10903
10904 // XXX this is generalized by compP_rReg_mem???
10905 // Compare raw pointer (used in out-of-heap check).
10906 // Only works because non-oop pointers must be raw pointers
10907 // and raw pointers have no anti-dependencies.
10908 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10909 %{
10910 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
10911 match(Set cr (CmpP op1 (LoadP op2)));
10912
10913 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10914 opcode(0x3B); /* Opcode 3B /r */
10915 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10916 ins_pipe(ialu_cr_reg_mem);
10917 %}
10918
10919 // This will generate a signed flags result. This should be OK since
10920 // any compare to a zero should be eq/neq.
10921 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10922 %{
10923 match(Set cr (CmpP src zero));
10924
10925 format %{ "testq $src, $src\t# ptr" %}
10926 opcode(0x85);
10927 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10928 ins_pipe(ialu_cr_reg_imm);
10929 %}
10930
10931 // This will generate a signed flags result. This should be OK since
10932 // any compare to a zero should be eq/neq.
10933 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10934 %{
10935 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10936 match(Set cr (CmpP (LoadP op) zero));
10937
10938 ins_cost(500); // XXX
10939 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10940 opcode(0xF7); /* Opcode F7 /0 */
10941 ins_encode(REX_mem_wide(op),
10942 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10943 ins_pipe(ialu_cr_reg_imm);
10944 %}
10945
10946 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10947 %{
10948 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
10949 match(Set cr (CmpP (LoadP mem) zero));
10950
10951 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10952 ins_encode %{
10953 __ cmpq(r12, $mem$$Address);
10954 %}
10955 ins_pipe(ialu_cr_reg_mem);
10956 %}
10957
10958 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10959 %{
10960 match(Set cr (CmpN op1 op2));
10961
10962 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10963 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10964 ins_pipe(ialu_cr_reg_reg);
10965 %}
10966
10967 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10968 %{
10969 match(Set cr (CmpN src (LoadN mem)));
10970
10971 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10972 ins_encode %{
10973 __ cmpl($src$$Register, $mem$$Address);
10974 %}
10975 ins_pipe(ialu_cr_reg_mem);
10976 %}
10977
10978 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10979 match(Set cr (CmpN op1 op2));
10980
10981 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10982 ins_encode %{
10983 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10984 %}
10985 ins_pipe(ialu_cr_reg_imm);
10986 %}
10987
10988 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10989 %{
10990 match(Set cr (CmpN src (LoadN mem)));
10991
10992 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10993 ins_encode %{
10994 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10995 %}
10996 ins_pipe(ialu_cr_reg_mem);
10997 %}
10998
10999 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11000 match(Set cr (CmpN src zero));
11001
11002 format %{ "testl $src, $src\t# compressed ptr" %}
11003 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11004 ins_pipe(ialu_cr_reg_imm);
11005 %}
11006
11007 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11008 %{
11009 predicate(Universe::narrow_oop_base() != NULL);
11010 match(Set cr (CmpN (LoadN mem) zero));
11011
11012 ins_cost(500); // XXX
11013 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11014 ins_encode %{
11015 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11016 %}
11017 ins_pipe(ialu_cr_reg_mem);
11018 %}
11019
11020 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11021 %{
11022 predicate(Universe::narrow_oop_base() == NULL);
11023 match(Set cr (CmpN (LoadN mem) zero));
11024
11025 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11026 ins_encode %{
11027 __ cmpl(r12, $mem$$Address);
11028 %}
11029 ins_pipe(ialu_cr_reg_mem);
11030 %}
11031
11032 // Yanked all unsigned pointer compare operations.
11033 // Pointer compares are done with CmpP which is already unsigned.
11034
11035 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11036 %{
11037 match(Set cr (CmpL op1 op2));
11038
11039 format %{ "cmpq $op1, $op2" %}
11040 opcode(0x3B); /* Opcode 3B /r */
11041 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11042 ins_pipe(ialu_cr_reg_reg);
11043 %}
11044
11045 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11046 %{
11047 match(Set cr (CmpL op1 op2));
11048
11049 format %{ "cmpq $op1, $op2" %}
11050 opcode(0x81, 0x07); /* Opcode 81 /7 */
11051 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11052 ins_pipe(ialu_cr_reg_imm);
11053 %}
11054
11055 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11056 %{
11057 match(Set cr (CmpL op1 (LoadL op2)));
11058
11059 format %{ "cmpq $op1, $op2" %}
11060 opcode(0x3B); /* Opcode 3B /r */
11061 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11062 ins_pipe(ialu_cr_reg_mem);
11063 %}
11064
11065 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11066 %{
11067 match(Set cr (CmpL src zero));
11068
11069 format %{ "testq $src, $src" %}
11070 opcode(0x85);
11071 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11072 ins_pipe(ialu_cr_reg_imm);
11073 %}
11074
11075 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11076 %{
11077 match(Set cr (CmpL (AndL src con) zero));
11078
11079 format %{ "testq $src, $con\t# long" %}
11080 opcode(0xF7, 0x00);
11081 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11082 ins_pipe(ialu_cr_reg_imm);
11083 %}
11084
11085 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11086 %{
11087 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11088
11089 format %{ "testq $src, $mem" %}
11090 opcode(0x85);
11091 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11092 ins_pipe(ialu_cr_reg_mem);
11093 %}
11094
11095 // Manifest a CmpL result in an integer register. Very painful.
11096 // This is the test to avoid.
11097 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11098 %{
11099 match(Set dst (CmpL3 src1 src2));
11100 effect(KILL flags);
11101
11102 ins_cost(275); // XXX
11103 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11104 "movl $dst, -1\n\t"
11105 "jl,s done\n\t"
11106 "setne $dst\n\t"
11107 "movzbl $dst, $dst\n\t"
11108 "done:" %}
11109 ins_encode(cmpl3_flag(src1, src2, dst));
11110 ins_pipe(pipe_slow);
11111 %}
11112
11113 //----------Max and Min--------------------------------------------------------
11114 // Min Instructions
11115
11116 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11117 %{
11118 effect(USE_DEF dst, USE src, USE cr);
11119
11120 format %{ "cmovlgt $dst, $src\t# min" %}
11121 opcode(0x0F, 0x4F);
11122 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11123 ins_pipe(pipe_cmov_reg);
11124 %}
11125
11126
11127 instruct minI_rReg(rRegI dst, rRegI src)
11128 %{
11129 match(Set dst (MinI dst src));
11130
11131 ins_cost(200);
11132 expand %{
11133 rFlagsReg cr;
11134 compI_rReg(cr, dst, src);
11135 cmovI_reg_g(dst, src, cr);
11136 %}
11137 %}
11138
11139 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11140 %{
11141 effect(USE_DEF dst, USE src, USE cr);
11142
11143 format %{ "cmovllt $dst, $src\t# max" %}
11144 opcode(0x0F, 0x4C);
11145 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11146 ins_pipe(pipe_cmov_reg);
11147 %}
11148
11149
11150 instruct maxI_rReg(rRegI dst, rRegI src)
11151 %{
11152 match(Set dst (MaxI dst src));
11153
11154 ins_cost(200);
11155 expand %{
11156 rFlagsReg cr;
11157 compI_rReg(cr, dst, src);
11158 cmovI_reg_l(dst, src, cr);
11159 %}
11160 %}
11161
11162 // ============================================================================
11163 // Branch Instructions
11164
11165 // Jump Direct - Label defines a relative address from JMP+1
11166 instruct jmpDir(label labl)
11167 %{
11168 match(Goto);
11169 effect(USE labl);
11170
11171 ins_cost(300);
11172 format %{ "jmp $labl" %}
11173 size(5);
11174 ins_encode %{
11175 Label* L = $labl$$label;
11176 __ jmp(*L, false); // Always long jump
11177 %}
11178 ins_pipe(pipe_jmp);
11179 %}
11180
11181 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11182 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11183 %{
11184 match(If cop cr);
11185 effect(USE labl);
11186
11187 ins_cost(300);
11188 format %{ "j$cop $labl" %}
11189 size(6);
11190 ins_encode %{
11191 Label* L = $labl$$label;
11192 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11193 %}
11194 ins_pipe(pipe_jcc);
11195 %}
11196
11197 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11198 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11199 %{
11200 match(CountedLoopEnd cop cr);
11201 effect(USE labl);
11202
11203 ins_cost(300);
11204 format %{ "j$cop $labl\t# loop end" %}
11205 size(6);
11206 ins_encode %{
11207 Label* L = $labl$$label;
11208 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11209 %}
11210 ins_pipe(pipe_jcc);
11211 %}
11212
11213 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11214 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11215 match(CountedLoopEnd cop cmp);
11216 effect(USE labl);
11217
11218 ins_cost(300);
11219 format %{ "j$cop,u $labl\t# loop end" %}
11220 size(6);
11221 ins_encode %{
11222 Label* L = $labl$$label;
11223 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11224 %}
11225 ins_pipe(pipe_jcc);
11226 %}
11227
11228 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11229 match(CountedLoopEnd cop cmp);
11230 effect(USE labl);
11231
11232 ins_cost(200);
11233 format %{ "j$cop,u $labl\t# loop end" %}
11234 size(6);
11235 ins_encode %{
11236 Label* L = $labl$$label;
11237 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11238 %}
11239 ins_pipe(pipe_jcc);
11240 %}
11241
11242 // Jump Direct Conditional - using unsigned comparison
11243 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11244 match(If cop cmp);
11245 effect(USE labl);
11246
11247 ins_cost(300);
11248 format %{ "j$cop,u $labl" %}
11249 size(6);
11250 ins_encode %{
11251 Label* L = $labl$$label;
11252 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11253 %}
11254 ins_pipe(pipe_jcc);
11255 %}
11256
11257 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11258 match(If cop cmp);
11259 effect(USE labl);
11260
11261 ins_cost(200);
11262 format %{ "j$cop,u $labl" %}
11263 size(6);
11264 ins_encode %{
11265 Label* L = $labl$$label;
11266 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11267 %}
11268 ins_pipe(pipe_jcc);
11269 %}
11270
11271 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11272 match(If cop cmp);
11273 effect(USE labl);
11274
11275 ins_cost(200);
11276 format %{ $$template
11277 if ($cop$$cmpcode == Assembler::notEqual) {
11278 $$emit$$"jp,u $labl\n\t"
11279 $$emit$$"j$cop,u $labl"
11280 } else {
11281 $$emit$$"jp,u done\n\t"
11282 $$emit$$"j$cop,u $labl\n\t"
11283 $$emit$$"done:"
11284 }
11285 %}
11286 ins_encode %{
11287 Label* l = $labl$$label;
11288 if ($cop$$cmpcode == Assembler::notEqual) {
11289 __ jcc(Assembler::parity, *l, false);
11290 __ jcc(Assembler::notEqual, *l, false);
11291 } else if ($cop$$cmpcode == Assembler::equal) {
11292 Label done;
11293 __ jccb(Assembler::parity, done);
11294 __ jcc(Assembler::equal, *l, false);
11295 __ bind(done);
11296 } else {
11297 ShouldNotReachHere();
11298 }
11299 %}
11300 ins_pipe(pipe_jcc);
11301 %}
11302
11303 // ============================================================================
11304 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11305 // superklass array for an instance of the superklass. Set a hidden
11306 // internal cache on a hit (cache is checked with exposed code in
11307 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11308 // encoding ALSO sets flags.
11309
11310 instruct partialSubtypeCheck(rdi_RegP result,
11311 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11312 rFlagsReg cr)
11313 %{
11314 match(Set result (PartialSubtypeCheck sub super));
11315 effect(KILL rcx, KILL cr);
11316
11317 ins_cost(1100); // slightly larger than the next version
11318 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11319 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11320 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11321 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11322 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11323 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11324 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11325 "miss:\t" %}
11326
11327 opcode(0x1); // Force a XOR of RDI
11328 ins_encode(enc_PartialSubtypeCheck());
11329 ins_pipe(pipe_slow);
11330 %}
11331
11332 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11333 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11334 immP0 zero,
11335 rdi_RegP result)
11336 %{
11337 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11338 effect(KILL rcx, KILL result);
11339
11340 ins_cost(1000);
11341 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11342 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11343 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11344 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11345 "jne,s miss\t\t# Missed: flags nz\n\t"
11346 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11347 "miss:\t" %}
11348
11349 opcode(0x0); // No need to XOR RDI
11350 ins_encode(enc_PartialSubtypeCheck());
11351 ins_pipe(pipe_slow);
11352 %}
11353
11354 // ============================================================================
11355 // Branch Instructions -- short offset versions
11356 //
11357 // These instructions are used to replace jumps of a long offset (the default
11358 // match) with jumps of a shorter offset. These instructions are all tagged
11359 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11360 // match rules in general matching. Instead, the ADLC generates a conversion
11361 // method in the MachNode which can be used to do in-place replacement of the
11362 // long variant with the shorter variant. The compiler will determine if a
11363 // branch can be taken by the is_short_branch_offset() predicate in the machine
11364 // specific code section of the file.
11365
11366 // Jump Direct - Label defines a relative address from JMP+1
11367 instruct jmpDir_short(label labl) %{
11368 match(Goto);
11369 effect(USE labl);
11370
11371 ins_cost(300);
11372 format %{ "jmp,s $labl" %}
11373 size(2);
11374 ins_encode %{
11375 Label* L = $labl$$label;
11376 __ jmpb(*L);
11377 %}
11378 ins_pipe(pipe_jmp);
11379 ins_short_branch(1);
11380 %}
11381
11382 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11383 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11384 match(If cop cr);
11385 effect(USE labl);
11386
11387 ins_cost(300);
11388 format %{ "j$cop,s $labl" %}
11389 size(2);
11390 ins_encode %{
11391 Label* L = $labl$$label;
11392 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11393 %}
11394 ins_pipe(pipe_jcc);
11395 ins_short_branch(1);
11396 %}
11397
11398 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11399 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11400 match(CountedLoopEnd cop cr);
11401 effect(USE labl);
11402
11403 ins_cost(300);
11404 format %{ "j$cop,s $labl\t# loop end" %}
11405 size(2);
11406 ins_encode %{
11407 Label* L = $labl$$label;
11408 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11409 %}
11410 ins_pipe(pipe_jcc);
11411 ins_short_branch(1);
11412 %}
11413
11414 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11415 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11416 match(CountedLoopEnd cop cmp);
11417 effect(USE labl);
11418
11419 ins_cost(300);
11420 format %{ "j$cop,us $labl\t# loop end" %}
11421 size(2);
11422 ins_encode %{
11423 Label* L = $labl$$label;
11424 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11425 %}
11426 ins_pipe(pipe_jcc);
11427 ins_short_branch(1);
11428 %}
11429
11430 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11431 match(CountedLoopEnd cop cmp);
11432 effect(USE labl);
11433
11434 ins_cost(300);
11435 format %{ "j$cop,us $labl\t# loop end" %}
11436 size(2);
11437 ins_encode %{
11438 Label* L = $labl$$label;
11439 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11440 %}
11441 ins_pipe(pipe_jcc);
11442 ins_short_branch(1);
11443 %}
11444
11445 // Jump Direct Conditional - using unsigned comparison
11446 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11447 match(If cop cmp);
11448 effect(USE labl);
11449
11450 ins_cost(300);
11451 format %{ "j$cop,us $labl" %}
11452 size(2);
11453 ins_encode %{
11454 Label* L = $labl$$label;
11455 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11456 %}
11457 ins_pipe(pipe_jcc);
11458 ins_short_branch(1);
11459 %}
11460
11461 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11462 match(If cop cmp);
11463 effect(USE labl);
11464
11465 ins_cost(300);
11466 format %{ "j$cop,us $labl" %}
11467 size(2);
11468 ins_encode %{
11469 Label* L = $labl$$label;
11470 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11471 %}
11472 ins_pipe(pipe_jcc);
11473 ins_short_branch(1);
11474 %}
11475
11476 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11477 match(If cop cmp);
11478 effect(USE labl);
11479
11480 ins_cost(300);
11481 format %{ $$template
11482 if ($cop$$cmpcode == Assembler::notEqual) {
11483 $$emit$$"jp,u,s $labl\n\t"
11484 $$emit$$"j$cop,u,s $labl"
11485 } else {
11486 $$emit$$"jp,u,s done\n\t"
11487 $$emit$$"j$cop,u,s $labl\n\t"
11488 $$emit$$"done:"
11489 }
11490 %}
11491 size(4);
11492 ins_encode %{
11493 Label* l = $labl$$label;
11494 if ($cop$$cmpcode == Assembler::notEqual) {
11495 __ jccb(Assembler::parity, *l);
11496 __ jccb(Assembler::notEqual, *l);
11497 } else if ($cop$$cmpcode == Assembler::equal) {
11498 Label done;
11499 __ jccb(Assembler::parity, done);
11500 __ jccb(Assembler::equal, *l);
11501 __ bind(done);
11502 } else {
11503 ShouldNotReachHere();
11504 }
11505 %}
11506 ins_pipe(pipe_jcc);
11507 ins_short_branch(1);
11508 %}
11509
11510 // ============================================================================
11511 // inlined locking and unlocking
11512
11513 instruct cmpFastLock(rFlagsReg cr,
11514 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
11515 %{
11516 match(Set cr (FastLock object box));
11517 effect(TEMP tmp, TEMP scr, USE_KILL box);
11518
11519 ins_cost(300);
11520 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11521 ins_encode(Fast_Lock(object, box, tmp, scr));
11522 ins_pipe(pipe_slow);
11523 %}
11524
11525 instruct cmpFastUnlock(rFlagsReg cr,
11526 rRegP object, rax_RegP box, rRegP tmp)
11527 %{
11528 match(Set cr (FastUnlock object box));
11529 effect(TEMP tmp, USE_KILL box);
11530
11531 ins_cost(300);
11532 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11533 ins_encode(Fast_Unlock(object, box, tmp));
11534 ins_pipe(pipe_slow);
11535 %}
11536
11537
11538 // ============================================================================
11539 // Safepoint Instructions
11540 instruct safePoint_poll(rFlagsReg cr)
11541 %{
11542 predicate(!Assembler::is_polling_page_far());
11543 match(SafePoint);
11544 effect(KILL cr);
11545
11546 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11547 "# Safepoint: poll for GC" %}
11548 ins_cost(125);
11549 ins_encode %{
11550 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11551 __ testl(rax, addr);
11552 %}
11553 ins_pipe(ialu_reg_mem);
11554 %}
11555
11556 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11557 %{
11558 predicate(Assembler::is_polling_page_far());
11559 match(SafePoint poll);
11560 effect(KILL cr, USE poll);
11561
11562 format %{ "testl rax, [$poll]\t"
11563 "# Safepoint: poll for GC" %}
11564 ins_cost(125);
11565 ins_encode %{
11566 __ relocate(relocInfo::poll_type);
11567 __ testl(rax, Address($poll$$Register, 0));
11568 %}
11569 ins_pipe(ialu_reg_mem);
11570 %}
11571
11572 // ============================================================================
11573 // Procedure Call/Return Instructions
11574 // Call Java Static Instruction
11575 // Note: If this code changes, the corresponding ret_addr_offset() and
11576 // compute_padding() functions will have to be adjusted.
11577 instruct CallStaticJavaDirect(method meth) %{
11578 match(CallStaticJava);
11579 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11580 effect(USE meth);
11581
11582 ins_cost(300);
11583 format %{ "call,static " %}
11584 opcode(0xE8); /* E8 cd */
11585 ins_encode(Java_Static_Call(meth), call_epilog);
11586 ins_pipe(pipe_slow);
11587 ins_alignment(4);
11588 %}
11589
11590 // Call Java Static Instruction (method handle version)
11591 // Note: If this code changes, the corresponding ret_addr_offset() and
11592 // compute_padding() functions will have to be adjusted.
11593 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11594 match(CallStaticJava);
11595 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11596 effect(USE meth);
11597 // RBP is saved by all callees (for interpreter stack correction).
11598 // We use it here for a similar purpose, in {preserve,restore}_SP.
11599
11600 ins_cost(300);
11601 format %{ "call,static/MethodHandle " %}
11602 opcode(0xE8); /* E8 cd */
11603 ins_encode(preserve_SP,
11604 Java_Static_Call(meth),
11605 restore_SP,
11606 call_epilog);
11607 ins_pipe(pipe_slow);
11608 ins_alignment(4);
11609 %}
11610
11611 // Call Java Dynamic Instruction
11612 // Note: If this code changes, the corresponding ret_addr_offset() and
11613 // compute_padding() functions will have to be adjusted.
11614 instruct CallDynamicJavaDirect(method meth)
11615 %{
11616 match(CallDynamicJava);
11617 effect(USE meth);
11618
11619 ins_cost(300);
11620 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11621 "call,dynamic " %}
11622 opcode(0xE8); /* E8 cd */
11623 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11624 ins_pipe(pipe_slow);
11625 ins_alignment(4);
11626 %}
11627
11628 // Call Runtime Instruction
11629 instruct CallRuntimeDirect(method meth)
11630 %{
11631 match(CallRuntime);
11632 effect(USE meth);
11633
11634 ins_cost(300);
11635 format %{ "call,runtime " %}
11636 opcode(0xE8); /* E8 cd */
11637 ins_encode(Java_To_Runtime(meth));
11638 ins_pipe(pipe_slow);
11639 %}
11640
11641 // Call runtime without safepoint
11642 instruct CallLeafDirect(method meth)
11643 %{
11644 match(CallLeaf);
11645 effect(USE meth);
11646
11647 ins_cost(300);
11648 format %{ "call_leaf,runtime " %}
11649 opcode(0xE8); /* E8 cd */
11650 ins_encode(Java_To_Runtime(meth));
11651 ins_pipe(pipe_slow);
11652 %}
11653
11654 // Call runtime without safepoint
11655 instruct CallLeafNoFPDirect(method meth)
11656 %{
11657 match(CallLeafNoFP);
11658 effect(USE meth);
11659
11660 ins_cost(300);
11661 format %{ "call_leaf_nofp,runtime " %}
11662 opcode(0xE8); /* E8 cd */
11663 ins_encode(Java_To_Runtime(meth));
11664 ins_pipe(pipe_slow);
11665 %}
11666
11667 // Return Instruction
11668 // Remove the return address & jump to it.
11669 // Notice: We always emit a nop after a ret to make sure there is room
11670 // for safepoint patching
11671 instruct Ret()
11672 %{
11673 match(Return);
11674
11675 format %{ "ret" %}
11676 opcode(0xC3);
11677 ins_encode(OpcP);
11678 ins_pipe(pipe_jmp);
11679 %}
11680
11681 // Tail Call; Jump from runtime stub to Java code.
11682 // Also known as an 'interprocedural jump'.
11683 // Target of jump will eventually return to caller.
11684 // TailJump below removes the return address.
11685 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11686 %{
11687 match(TailCall jump_target method_oop);
11688
11689 ins_cost(300);
11690 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11691 opcode(0xFF, 0x4); /* Opcode FF /4 */
11692 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11693 ins_pipe(pipe_jmp);
11694 %}
11695
11696 // Tail Jump; remove the return address; jump to target.
11697 // TailCall above leaves the return address around.
11698 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11699 %{
11700 match(TailJump jump_target ex_oop);
11701
11702 ins_cost(300);
11703 format %{ "popq rdx\t# pop return address\n\t"
11704 "jmp $jump_target" %}
11705 opcode(0xFF, 0x4); /* Opcode FF /4 */
11706 ins_encode(Opcode(0x5a), // popq rdx
11707 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11708 ins_pipe(pipe_jmp);
11709 %}
11710
11711 // Create exception oop: created by stack-crawling runtime code.
11712 // Created exception is now available to this handler, and is setup
11713 // just prior to jumping to this handler. No code emitted.
11714 instruct CreateException(rax_RegP ex_oop)
11715 %{
11716 match(Set ex_oop (CreateEx));
11717
11718 size(0);
11719 // use the following format syntax
11720 format %{ "# exception oop is in rax; no code emitted" %}
11721 ins_encode();
11722 ins_pipe(empty);
11723 %}
11724
11725 // Rethrow exception:
11726 // The exception oop will come in the first argument position.
11727 // Then JUMP (not call) to the rethrow stub code.
11728 instruct RethrowException()
11729 %{
11730 match(Rethrow);
11731
11732 // use the following format syntax
11733 format %{ "jmp rethrow_stub" %}
11734 ins_encode(enc_rethrow);
11735 ins_pipe(pipe_jmp);
11736 %}
11737
11738
11739 //----------PEEPHOLE RULES-----------------------------------------------------
11740 // These must follow all instruction definitions as they use the names
11741 // defined in the instructions definitions.
11742 //
11743 // peepmatch ( root_instr_name [preceding_instruction]* );
11744 //
11745 // peepconstraint %{
11746 // (instruction_number.operand_name relational_op instruction_number.operand_name
11747 // [, ...] );
11748 // // instruction numbers are zero-based using left to right order in peepmatch
11749 //
11750 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11751 // // provide an instruction_number.operand_name for each operand that appears
11752 // // in the replacement instruction's match rule
11753 //
11754 // ---------VM FLAGS---------------------------------------------------------
11755 //
11756 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11757 //
11758 // Each peephole rule is given an identifying number starting with zero and
11759 // increasing by one in the order seen by the parser. An individual peephole
11760 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11761 // on the command-line.
11762 //
11763 // ---------CURRENT LIMITATIONS----------------------------------------------
11764 //
11765 // Only match adjacent instructions in same basic block
11766 // Only equality constraints
11767 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11768 // Only one replacement instruction
11769 //
11770 // ---------EXAMPLE----------------------------------------------------------
11771 //
11772 // // pertinent parts of existing instructions in architecture description
11773 // instruct movI(rRegI dst, rRegI src)
11774 // %{
11775 // match(Set dst (CopyI src));
11776 // %}
11777 //
11778 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11779 // %{
11780 // match(Set dst (AddI dst src));
11781 // effect(KILL cr);
11782 // %}
11783 //
11784 // // Change (inc mov) to lea
11785 // peephole %{
11786 // // increment preceeded by register-register move
11787 // peepmatch ( incI_rReg movI );
11788 // // require that the destination register of the increment
11789 // // match the destination register of the move
11790 // peepconstraint ( 0.dst == 1.dst );
11791 // // construct a replacement instruction that sets
11792 // // the destination to ( move's source register + one )
11793 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11794 // %}
11795 //
11796
11797 // Implementation no longer uses movX instructions since
11798 // machine-independent system no longer uses CopyX nodes.
11799 //
11800 // peephole
11801 // %{
11802 // peepmatch (incI_rReg movI);
11803 // peepconstraint (0.dst == 1.dst);
11804 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11805 // %}
11806
11807 // peephole
11808 // %{
11809 // peepmatch (decI_rReg movI);
11810 // peepconstraint (0.dst == 1.dst);
11811 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11812 // %}
11813
11814 // peephole
11815 // %{
11816 // peepmatch (addI_rReg_imm movI);
11817 // peepconstraint (0.dst == 1.dst);
11818 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11819 // %}
11820
11821 // peephole
11822 // %{
11823 // peepmatch (incL_rReg movL);
11824 // peepconstraint (0.dst == 1.dst);
11825 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11826 // %}
11827
11828 // peephole
11829 // %{
11830 // peepmatch (decL_rReg movL);
11831 // peepconstraint (0.dst == 1.dst);
11832 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11833 // %}
11834
11835 // peephole
11836 // %{
11837 // peepmatch (addL_rReg_imm movL);
11838 // peepconstraint (0.dst == 1.dst);
11839 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11840 // %}
11841
11842 // peephole
11843 // %{
11844 // peepmatch (addP_rReg_imm movP);
11845 // peepconstraint (0.dst == 1.dst);
11846 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11847 // %}
11848
11849 // // Change load of spilled value to only a spill
11850 // instruct storeI(memory mem, rRegI src)
11851 // %{
11852 // match(Set mem (StoreI mem src));
11853 // %}
11854 //
11855 // instruct loadI(rRegI dst, memory mem)
11856 // %{
11857 // match(Set dst (LoadI mem));
11858 // %}
11859 //
11860
11861 peephole
11862 %{
11863 peepmatch (loadI storeI);
11864 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11865 peepreplace (storeI(1.mem 1.mem 1.src));
11866 %}
11867
11868 peephole
11869 %{
11870 peepmatch (loadL storeL);
11871 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11872 peepreplace (storeL(1.mem 1.mem 1.src));
11873 %}
11874
11875 //----------SMARTSPILL RULES---------------------------------------------------
11876 // These must follow all instruction definitions as they use the names
11877 // defined in the instructions definitions.