src/cpu/x86/vm/x86_32.ad
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src/cpu/x86/vm/x86_32.ad

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*** 1,7 **** // ! // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation. --- 1,7 ---- // ! // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation.
*** 339,354 **** current_offset += 5; // skip MOV instruction current_offset += 1; // skip call opcode byte return round_to(current_offset, alignment_required()) - current_offset; } - #ifndef PRODUCT - void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { - st->print("INT3"); - } - #endif - // EMIT_RM() void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); cbuf.insts()->emit_int8(c); } --- 339,348 ----
*** 1115,1125 **** Unimplemented(); } #ifndef PRODUCT ! void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { implementation( NULL, ra_, false, st ); } #endif void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { --- 1109,1119 ---- Unimplemented(); } #ifndef PRODUCT ! void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { implementation( NULL, ra_, false, st ); } #endif void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
*** 1128,1154 **** uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { return implementation( NULL, ra_, true, NULL ); } - //============================================================================= - #ifndef PRODUCT - void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { - st->print("NOP \t# %d bytes pad for loops and calls", _count); - } - #endif - void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { - MacroAssembler _masm(&cbuf); - __ nop(_count); - } - - uint MachNopNode::size(PhaseRegAlloc *) const { - return _count; - } - - //============================================================================= #ifndef PRODUCT void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); int reg = ra_->get_reg_first(this); --- 1122,1132 ----
*** 1829,1853 **** MacroAssembler masm(&cbuf); masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); } %} - enc_class preserve_SP %{ - debug_only(int off0 = cbuf.insts_size()); - MacroAssembler _masm(&cbuf); - // RBP is preserved across all calls, even compiled calls. - // Use it to preserve RSP in places where the callee might change the SP. - __ movptr(rbp_mh_SP_save, rsp); - debug_only(int off1 = cbuf.insts_size()); - assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); - %} - - enc_class restore_SP %{ - MacroAssembler _masm(&cbuf); - __ movptr(rsp, rbp_mh_SP_save); - %} - enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine // who we intended to call. cbuf.set_insts_mark(); $$$emit8$primary; --- 1807,1816 ----
*** 3792,3804 **** // representing the register number (i.e. - use a register name) or // stack slot. // Ret Addr is on stack in slot 0 if no locks or verification or alignment. // Otherwise, it is above the locks and verification slot and alignment word return_addr(STACK - 1 + ! round_to(1+VerifyStackAtCalls+ ! Compile::current()->fixed_slots(), ! (StackAlignmentInBytes/wordSize))); // Body of function which returns an integer array locating // arguments either in registers or in stack slots. Passed an array // of ideal registers called "sig" and a "length" count. Stack-slot // offsets are based on outgoing arguments, i.e. a CALLER setting up --- 3755,3767 ---- // representing the register number (i.e. - use a register name) or // stack slot. // Ret Addr is on stack in slot 0 if no locks or verification or alignment. // Otherwise, it is above the locks and verification slot and alignment word return_addr(STACK - 1 + ! round_to((Compile::current()->in_preserve_stack_slots() + ! Compile::current()->fixed_slots()), ! stack_alignment_in_slots())); // Body of function which returns an integer array locating // arguments either in registers or in stack slots. Passed an array // of ideal registers called "sig" and a "length" count. Stack-slot // offsets are based on outgoing arguments, i.e. a CALLER setting up
*** 13422,13431 **** --- 13385,13413 ---- size(6) ; ins_encode( Safepoint_Poll() ); ins_pipe( ialu_reg_mem ); %} + + // ============================================================================ + // This name is KNOWN by the ADLC and cannot be changed. + // The ADLC forces a 'TypeRawPtr::BOTTOM' output type + // for this guy. + instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ + match(Set dst (ThreadLocal)); + effect(DEF dst, KILL cr); + + format %{ "MOV $dst, Thread::current()" %} + ins_encode %{ + Register dstReg = as_Register($dst$$reg); + __ get_thread(dstReg); + %} + ins_pipe( ialu_reg_fat ); + %} + + + //----------PEEPHOLE RULES----------------------------------------------------- // These must follow all instruction definitions as they use the names // defined in the instructions definitions. // // peepmatch ( root_instr_name [preceding_instruction]* );
src/cpu/x86/vm/x86_32.ad
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