1 //
2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
599 {
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
601 current_offset += 1; // skip call opcode byte
602 return round_to(current_offset, alignment_required()) - current_offset;
603 }
604
605 // The address of the call instruction needs to be 4-byte aligned to
606 // ensure that it does not span a cache line so that it can be patched.
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
608 {
609 current_offset += 11; // skip movq instruction + call opcode byte
610 return round_to(current_offset, alignment_required()) - current_offset;
611 }
612
613 #ifndef PRODUCT
614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
615 {
616 st->print("INT3");
617 }
618 #endif
619
620 // EMIT_RM()
621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
623 cbuf.insts()->emit_int8(c);
624 }
625
626 // EMIT_CC()
627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
628 unsigned char c = (unsigned char) (f1 | f2);
629 cbuf.insts()->emit_int8(c);
630 }
631
632 // EMIT_OPCODE()
633 void emit_opcode(CodeBuffer &cbuf, int code) {
634 cbuf.insts()->emit_int8((unsigned char) code);
635 }
636
637 // EMIT_OPCODE() w/ relocation information
638 void emit_opcode(CodeBuffer &cbuf,
639 int code, relocInfo::relocType reloc, int offset, int format)
1513
1514 #ifndef PRODUCT
1515 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1516 {
1517 implementation(NULL, ra_, false, st);
1518 }
1519 #endif
1520
1521 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1522 {
1523 implementation(&cbuf, ra_, false, NULL);
1524 }
1525
1526 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1527 {
1528 return implementation(NULL, ra_, true, NULL);
1529 }
1530
1531 //=============================================================================
1532 #ifndef PRODUCT
1533 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1534 {
1535 st->print("nop \t# %d bytes pad for loops and calls", _count);
1536 }
1537 #endif
1538
1539 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1540 {
1541 MacroAssembler _masm(&cbuf);
1542 __ nop(_count);
1543 }
1544
1545 uint MachNopNode::size(PhaseRegAlloc*) const
1546 {
1547 return _count;
1548 }
1549
1550
1551 //=============================================================================
1552 #ifndef PRODUCT
1553 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1554 {
1555 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1556 int reg = ra_->get_reg_first(this);
1557 st->print("leaq %s, [rsp + #%d]\t# box lock",
1558 Matcher::regName[reg], offset);
1559 }
1560 #endif
1561
1562 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1563 {
1564 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1565 int reg = ra_->get_encode(this);
1566 if (offset >= 0x80) {
1567 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1568 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1569 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1570 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1571 emit_d32(cbuf, offset);
1572 } else {
2238 /*set_cond_codes:*/ true);
2239 if ($primary) {
2240 __ xorptr(Rrdi, Rrdi);
2241 }
2242 __ bind(miss);
2243 %}
2244
2245 enc_class Java_To_Interpreter(method meth)
2246 %{
2247 // CALL Java_To_Interpreter
2248 // This is the instruction starting address for relocation info.
2249 cbuf.set_insts_mark();
2250 $$$emit8$primary;
2251 // CALL directly to the runtime
2252 emit_d32_reloc(cbuf,
2253 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2254 runtime_call_Relocation::spec(),
2255 RELOC_DISP32);
2256 %}
2257
2258 enc_class preserve_SP %{
2259 debug_only(int off0 = cbuf.insts_size());
2260 MacroAssembler _masm(&cbuf);
2261 // RBP is preserved across all calls, even compiled calls.
2262 // Use it to preserve RSP in places where the callee might change the SP.
2263 __ movptr(rbp_mh_SP_save, rsp);
2264 debug_only(int off1 = cbuf.insts_size());
2265 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
2266 %}
2267
2268 enc_class restore_SP %{
2269 MacroAssembler _masm(&cbuf);
2270 __ movptr(rsp, rbp_mh_SP_save);
2271 %}
2272
2273 enc_class Java_Static_Call(method meth)
2274 %{
2275 // JAVA STATIC CALL
2276 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2277 // determine who we intended to call.
2278 cbuf.set_insts_mark();
2279 $$$emit8$primary;
2280
2281 if (!_method) {
2282 emit_d32_reloc(cbuf,
2283 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2284 runtime_call_Relocation::spec(),
2285 RELOC_DISP32);
2286 } else if (_optimized_virtual) {
2287 emit_d32_reloc(cbuf,
2288 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2289 opt_virtual_call_Relocation::spec(),
2290 RELOC_DISP32);
2291 } else {
2292 emit_d32_reloc(cbuf,
3191 // Stack alignment requirement
3192 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3193
3194 // Number of stack slots between incoming argument block and the start of
3195 // a new frame. The PROLOG must add this many slots to the stack. The
3196 // EPILOG must remove this many slots. amd64 needs two slots for
3197 // return address.
3198 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
3199
3200 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3201 // for calls to C. Supports the var-args backing area for register parms.
3202 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3203
3204 // The after-PROLOG location of the return address. Location of
3205 // return address specifies a type (REG or STACK) and a number
3206 // representing the register number (i.e. - use a register name) or
3207 // stack slot.
3208 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3209 // Otherwise, it is above the locks and verification slot and alignment word
3210 return_addr(STACK - 2 +
3211 round_to(2 + 2 * VerifyStackAtCalls +
3212 Compile::current()->fixed_slots(),
3213 WordsPerLong * 2));
3214
3215 // Body of function which returns an integer array locating
3216 // arguments either in registers or in stack slots. Passed an array
3217 // of ideal registers called "sig" and a "length" count. Stack-slot
3218 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3219 // arguments for a CALLEE. Incoming stack arguments are
3220 // automatically biased by the preserve_stack_slots field above.
3221
3222 calling_convention
3223 %{
3224 // No difference between ingoing/outgoing just pass false
3225 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3226 %}
3227
3228 c_calling_convention
3229 %{
3230 // This is obviously always outgoing
3231 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3232 %}
3233
11650 size(0);
11651 // use the following format syntax
11652 format %{ "# exception oop is in rax; no code emitted" %}
11653 ins_encode();
11654 ins_pipe(empty);
11655 %}
11656
11657 // Rethrow exception:
11658 // The exception oop will come in the first argument position.
11659 // Then JUMP (not call) to the rethrow stub code.
11660 instruct RethrowException()
11661 %{
11662 match(Rethrow);
11663
11664 // use the following format syntax
11665 format %{ "jmp rethrow_stub" %}
11666 ins_encode(enc_rethrow);
11667 ins_pipe(pipe_jmp);
11668 %}
11669
11670
11671 //----------PEEPHOLE RULES-----------------------------------------------------
11672 // These must follow all instruction definitions as they use the names
11673 // defined in the instructions definitions.
11674 //
11675 // peepmatch ( root_instr_name [preceding_instruction]* );
11676 //
11677 // peepconstraint %{
11678 // (instruction_number.operand_name relational_op instruction_number.operand_name
11679 // [, ...] );
11680 // // instruction numbers are zero-based using left to right order in peepmatch
11681 //
11682 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11683 // // provide an instruction_number.operand_name for each operand that appears
11684 // // in the replacement instruction's match rule
11685 //
11686 // ---------VM FLAGS---------------------------------------------------------
11687 //
11688 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11689 //
|
1 //
2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
599 {
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
601 current_offset += 1; // skip call opcode byte
602 return round_to(current_offset, alignment_required()) - current_offset;
603 }
604
605 // The address of the call instruction needs to be 4-byte aligned to
606 // ensure that it does not span a cache line so that it can be patched.
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
608 {
609 current_offset += 11; // skip movq instruction + call opcode byte
610 return round_to(current_offset, alignment_required()) - current_offset;
611 }
612
613 // EMIT_RM()
614 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
615 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
616 cbuf.insts()->emit_int8(c);
617 }
618
619 // EMIT_CC()
620 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
621 unsigned char c = (unsigned char) (f1 | f2);
622 cbuf.insts()->emit_int8(c);
623 }
624
625 // EMIT_OPCODE()
626 void emit_opcode(CodeBuffer &cbuf, int code) {
627 cbuf.insts()->emit_int8((unsigned char) code);
628 }
629
630 // EMIT_OPCODE() w/ relocation information
631 void emit_opcode(CodeBuffer &cbuf,
632 int code, relocInfo::relocType reloc, int offset, int format)
1506
1507 #ifndef PRODUCT
1508 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1509 {
1510 implementation(NULL, ra_, false, st);
1511 }
1512 #endif
1513
1514 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1515 {
1516 implementation(&cbuf, ra_, false, NULL);
1517 }
1518
1519 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1520 {
1521 return implementation(NULL, ra_, true, NULL);
1522 }
1523
1524 //=============================================================================
1525 #ifndef PRODUCT
1526 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_reg_first(this);
1530 st->print("leaq %s, [rsp + #%d]\t# box lock",
1531 Matcher::regName[reg], offset);
1532 }
1533 #endif
1534
1535 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1536 {
1537 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1538 int reg = ra_->get_encode(this);
1539 if (offset >= 0x80) {
1540 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1541 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1542 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1543 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1544 emit_d32(cbuf, offset);
1545 } else {
2211 /*set_cond_codes:*/ true);
2212 if ($primary) {
2213 __ xorptr(Rrdi, Rrdi);
2214 }
2215 __ bind(miss);
2216 %}
2217
2218 enc_class Java_To_Interpreter(method meth)
2219 %{
2220 // CALL Java_To_Interpreter
2221 // This is the instruction starting address for relocation info.
2222 cbuf.set_insts_mark();
2223 $$$emit8$primary;
2224 // CALL directly to the runtime
2225 emit_d32_reloc(cbuf,
2226 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2227 runtime_call_Relocation::spec(),
2228 RELOC_DISP32);
2229 %}
2230
2231 enc_class Java_Static_Call(method meth)
2232 %{
2233 // JAVA STATIC CALL
2234 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2235 // determine who we intended to call.
2236 cbuf.set_insts_mark();
2237 $$$emit8$primary;
2238
2239 if (!_method) {
2240 emit_d32_reloc(cbuf,
2241 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2242 runtime_call_Relocation::spec(),
2243 RELOC_DISP32);
2244 } else if (_optimized_virtual) {
2245 emit_d32_reloc(cbuf,
2246 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2247 opt_virtual_call_Relocation::spec(),
2248 RELOC_DISP32);
2249 } else {
2250 emit_d32_reloc(cbuf,
3149 // Stack alignment requirement
3150 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3151
3152 // Number of stack slots between incoming argument block and the start of
3153 // a new frame. The PROLOG must add this many slots to the stack. The
3154 // EPILOG must remove this many slots. amd64 needs two slots for
3155 // return address.
3156 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
3157
3158 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3159 // for calls to C. Supports the var-args backing area for register parms.
3160 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3161
3162 // The after-PROLOG location of the return address. Location of
3163 // return address specifies a type (REG or STACK) and a number
3164 // representing the register number (i.e. - use a register name) or
3165 // stack slot.
3166 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3167 // Otherwise, it is above the locks and verification slot and alignment word
3168 return_addr(STACK - 2 +
3169 round_to((Compile::current()->in_preserve_stack_slots() +
3170 Compile::current()->fixed_slots()),
3171 stack_alignment_in_slots()));
3172
3173 // Body of function which returns an integer array locating
3174 // arguments either in registers or in stack slots. Passed an array
3175 // of ideal registers called "sig" and a "length" count. Stack-slot
3176 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3177 // arguments for a CALLEE. Incoming stack arguments are
3178 // automatically biased by the preserve_stack_slots field above.
3179
3180 calling_convention
3181 %{
3182 // No difference between ingoing/outgoing just pass false
3183 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3184 %}
3185
3186 c_calling_convention
3187 %{
3188 // This is obviously always outgoing
3189 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3190 %}
3191
11608 size(0);
11609 // use the following format syntax
11610 format %{ "# exception oop is in rax; no code emitted" %}
11611 ins_encode();
11612 ins_pipe(empty);
11613 %}
11614
11615 // Rethrow exception:
11616 // The exception oop will come in the first argument position.
11617 // Then JUMP (not call) to the rethrow stub code.
11618 instruct RethrowException()
11619 %{
11620 match(Rethrow);
11621
11622 // use the following format syntax
11623 format %{ "jmp rethrow_stub" %}
11624 ins_encode(enc_rethrow);
11625 ins_pipe(pipe_jmp);
11626 %}
11627
11628
11629 // ============================================================================
11630 // This name is KNOWN by the ADLC and cannot be changed.
11631 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11632 // for this guy.
11633 instruct tlsLoadP(r15_RegP dst) %{
11634 match(Set dst (ThreadLocal));
11635 effect(DEF dst);
11636
11637 size(0);
11638 format %{ "# TLS is in R15" %}
11639 ins_encode( /*empty encoding*/ );
11640 ins_pipe(ialu_reg_reg);
11641 %}
11642
11643
11644 //----------PEEPHOLE RULES-----------------------------------------------------
11645 // These must follow all instruction definitions as they use the names
11646 // defined in the instructions definitions.
11647 //
11648 // peepmatch ( root_instr_name [preceding_instruction]* );
11649 //
11650 // peepconstraint %{
11651 // (instruction_number.operand_name relational_op instruction_number.operand_name
11652 // [, ...] );
11653 // // instruction numbers are zero-based using left to right order in peepmatch
11654 //
11655 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11656 // // provide an instruction_number.operand_name for each operand that appears
11657 // // in the replacement instruction's match rule
11658 //
11659 // ---------VM FLAGS---------------------------------------------------------
11660 //
11661 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11662 //
|