*** old/src/cpu/x86/vm/x86_64.ad	Thu Feb 16 10:56:34 2012
--- new/src/cpu/x86/vm/x86_64.ad	Thu Feb 16 10:56:34 2012

*** 1,7 ****
--- 1,7 ----
  //
! // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
! // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  //
  // This code is free software; you can redistribute it and/or modify it
  // under the terms of the GNU General Public License version 2 only, as
  // published by the Free Software Foundation.

*** 608,624 ****
--- 608,617 ----
  {
    current_offset += 11; // skip movq instruction + call opcode byte
    return round_to(current_offset, alignment_required()) - current_offset;
  }
  
  #ifndef PRODUCT
  void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
  {
    st->print("INT3");
  }
  #endif
  
  // EMIT_RM()
  void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
    unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
    cbuf.insts()->emit_int8(c);
  }

*** 1528,1557 ****
--- 1521,1530 ----
    return implementation(NULL, ra_, true, NULL);
  }
  
  //=============================================================================
  #ifndef PRODUCT
  void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
  {
    st->print("nop \t# %d bytes pad for loops and calls", _count);
  }
  #endif
  
  void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
  {
    MacroAssembler _masm(&cbuf);
    __ nop(_count);
  }
  
  uint MachNopNode::size(PhaseRegAlloc*) const
  {
    return _count;
  }
  
  
  //=============================================================================
  #ifndef PRODUCT
  void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
  {
    int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
    int reg = ra_->get_reg_first(this);
    st->print("leaq    %s, [rsp + #%d]\t# box lock",

*** 2253,2277 ****
--- 2226,2235 ----
                     (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
                     runtime_call_Relocation::spec(),
                     RELOC_DISP32);
    %}
  
    enc_class preserve_SP %{
      debug_only(int off0 = cbuf.insts_size());
      MacroAssembler _masm(&cbuf);
      // RBP is preserved across all calls, even compiled calls.
      // Use it to preserve RSP in places where the callee might change the SP.
      __ movptr(rbp_mh_SP_save, rsp);
      debug_only(int off1 = cbuf.insts_size());
      assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
    %}
  
    enc_class restore_SP %{
      MacroAssembler _masm(&cbuf);
      __ movptr(rsp, rbp_mh_SP_save);
    %}
  
    enc_class Java_Static_Call(method meth)
    %{
      // JAVA STATIC CALL
      // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
      // determine who we intended to call.

*** 3206,3218 ****
--- 3164,3176 ----
    // representing the register number (i.e. - use a register name) or
    // stack slot.
    // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
    // Otherwise, it is above the locks and verification slot and alignment word
    return_addr(STACK - 2 +
!               round_to(2 + 2 * VerifyStackAtCalls +
!                        Compile::current()->fixed_slots(),
!                        WordsPerLong * 2));
!               round_to((Compile::current()->in_preserve_stack_slots() +
!                         Compile::current()->fixed_slots()),
!                        stack_alignment_in_slots()));
  
    // Body of function which returns an integer array locating
    // arguments either in registers or in stack slots.  Passed an array
    // of ideal registers called "sig" and a "length" count.  Stack-slot
    // offsets are based on outgoing arguments, i.e. a CALLER setting up

*** 11665,11674 ****
--- 11623,11647 ----
    format %{ "jmp     rethrow_stub" %}
    ins_encode(enc_rethrow);
    ins_pipe(pipe_jmp);
  %}
  
+ 
+ // ============================================================================
+ // This name is KNOWN by the ADLC and cannot be changed.
+ // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
+ // for this guy.
+ instruct tlsLoadP(r15_RegP dst) %{
+   match(Set dst (ThreadLocal));
+   effect(DEF dst);
+ 
+   size(0);
+   format %{ "# TLS is in R15" %}
+   ins_encode( /*empty encoding*/ );
+   ins_pipe(ialu_reg_reg);
+ %}
+ 
  
  //----------PEEPHOLE RULES-----------------------------------------------------
  // These must follow all instruction definitions as they use the names
  // defined in the instructions definitions.
  //