1 //
2 // Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Bsd Architecture Description File
26
27 //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
28 // This block specifies the encoding classes used by the compiler to
29 // output byte streams. Encoding classes generate functions which are
30 // called by Machine Instruction Nodes in order to generate the bit
31 // encoding of the instruction. Operands specify their base encoding
32 // interface with the interface keyword. There are currently
33 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
34 // COND_INTER. REG_INTER causes an operand to generate a function
35 // which returns its register number when queried. CONST_INTER causes
36 // an operand to generate a function which returns the value of the
37 // constant when queried. MEMORY_INTER causes an operand to generate
38 // four functions which return the Base Register, the Index Register,
39 // the Scale Value, and the Offset Value of the operand when queried.
40 // COND_INTER causes an operand to generate six functions which return
41 // the encoding code (ie - encoding bits for the instruction)
42 // associated with each basic boolean condition for a conditional
43 // instruction. Instructions specify two basic values for encoding.
44 // They use the ins_encode keyword to specify their encoding class
45 // (which must be one of the class names specified in the encoding
46 // block), and they use the opcode keyword to specify, in order, their
47 // primary, secondary, and tertiary opcode. Only the opcode sections
48 // which a particular instruction needs for encoding need to be
49 // specified.
50 encode %{
51 // Build emit functions for each basic byte or larger field in the intel
52 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
53 // code in the enc_class source block. Emit functions will live in the
54 // main source block for now. In future, we can generalize this by
55 // adding a syntax that specifies the sizes of fields in an order,
56 // so that the adlc can build the emit functions automagically
57
58 enc_class Java_To_Runtime(method meth)
59 %{
60 // No relocation needed
61
62 // movq r10, <meth>
63 emit_opcode(cbuf, Assembler::REX_WB);
64 emit_opcode(cbuf, 0xB8 | (R10_enc - 8));
65 emit_d64(cbuf, (int64_t) $meth$$method);
66
67 // call (r10)
68 emit_opcode(cbuf, Assembler::REX_B);
69 emit_opcode(cbuf, 0xFF);
70 emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
71 %}
72
73 enc_class bsd_breakpoint
74 %{
75 MacroAssembler* masm = new MacroAssembler(&cbuf);
76 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
77 %}
78
79 enc_class call_epilog
80 %{
81 if (VerifyStackAtCalls) {
82 // Check that stack depth is unchanged: find majik cookie on stack
83 int framesize =
84 ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
85 if (framesize) {
86 if (framesize < 0x80) {
87 emit_opcode(cbuf, Assembler::REX_W);
88 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
89 emit_d8(cbuf, 0x7C);
90 emit_d8(cbuf, 0x24);
91 emit_d8(cbuf, framesize); // Find majik cookie from ESP
92 emit_d32(cbuf, 0xbadb100d);
93 } else {
94 emit_opcode(cbuf, Assembler::REX_W);
95 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood
96 emit_d8(cbuf, 0xBC);
97 emit_d8(cbuf, 0x24);
98 emit_d32(cbuf, framesize); // Find majik cookie from ESP
99 emit_d32(cbuf, 0xbadb100d);
100 }
101 }
102 // jmp EQ around INT3
103 // QQQ TODO
104 const int jump_around = 5; // size of call to breakpoint, 1 for CC
105 emit_opcode(cbuf, 0x74);
106 emit_d8(cbuf, jump_around);
107 // QQQ temporary
108 emit_break(cbuf);
109 // Die if stack mismatch
110 // emit_opcode(cbuf,0xCC);
111 }
112 %}
113
114 %}
115
116 // INSTRUCTIONS -- Platform dependent
117
118 //----------OS and Locking Instructions----------------------------------------
119
120 // This name is KNOWN by the ADLC and cannot be changed.
121 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
122 // for this guy.
123 instruct tlsLoadP(r15_RegP dst)
124 %{
125 match(Set dst (ThreadLocal));
126 effect(DEF dst);
127
128 size(0);
129 format %{ "# TLS is in R15" %}
130 ins_encode( /*empty encoding*/ );
131 ins_pipe(ialu_reg_reg);
132 %}
133
134 // Die now
135 instruct ShouldNotReachHere()
136 %{
137 match(Halt);
138
139 // Use the following format syntax
140 format %{ "int3\t# ShouldNotReachHere" %}
141 // QQQ TODO for now call breakpoint
142 // opcode(0xCC);
143 // ins_encode(Opc);
144 ins_encode(bsd_breakpoint);
145 ins_pipe(pipe_slow);
146 %}
147
148
149 // Platform dependent source
150
151 source
152 %{
153
154 int MachCallRuntimeNode::ret_addr_offset() {
155 return 13; // movq r10,#addr; callq (r10)
156 }
157
158 // emit an interrupt that is caught by the debugger
159 void emit_break(CodeBuffer& cbuf) {
160 // Debugger doesn't really catch this but best we can do so far QQQ
161 MacroAssembler* masm = new MacroAssembler(&cbuf);
162 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
163 }
164
165 void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
166 emit_break(cbuf);
167 }
168
169 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
170 return 5;
171 }
172
173 %}