1 //
   2 // Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // AMD64 Solaris Architecture Description File
  26 
  27 //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
  28 // This block specifies the encoding classes used by the compiler to
  29 // output byte streams.  Encoding classes generate functions which are
  30 // called by Machine Instruction Nodes in order to generate the bit
  31 // encoding of the instruction.  Operands specify their base encoding
  32 // interface with the interface keyword.  There are currently
  33 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
  34 // COND_INTER.  REG_INTER causes an operand to generate a function
  35 // which returns its register number when queried.  CONST_INTER causes
  36 // an operand to generate a function which returns the value of the
  37 // constant when queried.  MEMORY_INTER causes an operand to generate
  38 // four functions which return the Base Register, the Index Register,
  39 // the Scale Value, and the Offset Value of the operand when queried.
  40 // COND_INTER causes an operand to generate six functions which return
  41 // the encoding code (ie - encoding bits for the instruction)
  42 // associated with each basic boolean condition for a conditional
  43 // instruction.  Instructions specify two basic values for encoding.
  44 // They use the ins_encode keyword to specify their encoding class
  45 // (which must be one of the class names specified in the encoding
  46 // block), and they use the opcode keyword to specify, in order, their
  47 // primary, secondary, and tertiary opcode.  Only the opcode sections
  48 // which a particular instruction needs for encoding need to be
  49 // specified.
  50 encode %{
  51   // Build emit functions for each basic byte or larger field in the intel
  52   // encoding scheme (opcode, rm, sib, immediate), and call them from C++
  53   // code in the enc_class source block.  Emit functions will live in the
  54   // main source block for now.  In future, we can generalize this by
  55   // adding a syntax that specifies the sizes of fields in an order,
  56   // so that the adlc can build the emit functions automagically
  57 
  58   enc_class Java_To_Runtime(method meth) %{
  59     // No relocation needed
  60 
  61     // movq r10, <meth>
  62     emit_opcode(cbuf, Assembler::REX_WB);
  63     emit_opcode(cbuf, 0xB8 | (R10_enc - 8));
  64     emit_d64(cbuf, (int64_t) $meth$$method);
  65 
  66     // call (r10)
  67     emit_opcode(cbuf, Assembler::REX_B);
  68     emit_opcode(cbuf, 0xFF);
  69     emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
  70   %}
  71 
  72   enc_class post_call_verify_mxcsr %{
  73     MacroAssembler _masm(&cbuf);
  74     if (RestoreMXCSROnJNICalls) {
  75       __ ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
  76     }
  77     else if (CheckJNICalls) {
  78       __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::amd64::verify_mxcsr_entry())));
  79     }
  80   %}
  81 %}
  82 
  83 
  84 // Platform dependent source
  85 
  86 source %{
  87 
  88 int MachCallRuntimeNode::ret_addr_offset() {
  89   return 13; // movq r10,#addr; callq (r10)
  90 }
  91 
  92 // emit an interrupt that is caught by the debugger
  93 void emit_break(MacroAssembler &_masm) {
  94   // __ emit_byte(0xCC);
  95   // TODO for now call breakpoint instead of INT3.
  96   // Debugger doesn't really catch this but best we can do so far QQQ.
  97   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
  98 }
  99 
 100 %}