1 //
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedOops && UseCompressedKlassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_oop_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
721 (f0 << 0);
722 cbuf.insts()->emit_int32(op);
723 }
724
725 // Standard Sparc opcode form3 field breakdown
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
727 int op = (f30 << 30) |
728 (f25 << 25) |
729 (f19 << 19) |
730 (f14 << 14) |
731 (f5 << 5) |
732 (f0 << 0);
733 cbuf.insts()->emit_int32(op);
734 }
735
736 // Standard Sparc opcode form3 field breakdown
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
738 simm13 &= (1<<13)-1; // Mask to 13 bits
739 int op = (f30 << 30) |
740 (f25 << 25) |
741 (f19 << 19) |
742 (f14 << 14) |
743 (1 << 13) | // bit to indicate immediate-mode
744 (simm13<<0);
745 cbuf.insts()->emit_int32(op);
746 }
747
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
749 simm10 &= (1<<10)-1; // Mask to 10 bits
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
751 }
752
753 #ifdef ASSERT
754 // Helper function for VerifyOops in emit_form3_mem_reg
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
756 warning("VerifyOops encountered unexpected instruction:");
757 n->dump(2);
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
759 }
760 #endif
761
762
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
764 int src1_enc, int disp32, int src2_enc, int dst_enc) {
765
766 #ifdef ASSERT
767 // The following code implements the +VerifyOops feature.
768 // It verifies oop values which are loaded into or stored out of
769 // the current method activation. +VerifyOops complements techniques
770 // like ScavengeALot, because it eagerly inspects oops in transit,
771 // as they enter or leave the stack, as opposed to ScavengeALot,
772 // which inspects oops "at rest", in the stack or heap, at safepoints.
773 // For this reason, +VerifyOops can sometimes detect bugs very close
774 // to their point of creation. It can also serve as a cross-check
775 // on the validity of oop maps, when used toegether with ScavengeALot.
776
777 // It would be good to verify oops at other points, especially
778 // when an oop is used as a base pointer for a load or store.
779 // This is presently difficult, because it is hard to know when
780 // a base address is biased or not. (If we had such information,
781 // it would be easy and useful to make a two-argument version of
782 // verify_oop which unbiases the base, and performs verification.)
783
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
785 bool is_verified_oop_base = false;
786 bool is_verified_oop_load = false;
787 bool is_verified_oop_store = false;
788 int tmp_enc = -1;
789 if (VerifyOops && src1_enc != R_SP_enc) {
790 // classify the op, mainly for an assert check
791 int st_op = 0, ld_op = 0;
792 switch (primary) {
793 case Assembler::stb_op3: st_op = Op_StoreB; break;
794 case Assembler::sth_op3: st_op = Op_StoreC; break;
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
796 case Assembler::stw_op3: st_op = Op_StoreI; break;
797 case Assembler::std_op3: st_op = Op_StoreL; break;
798 case Assembler::stf_op3: st_op = Op_StoreF; break;
799 case Assembler::stdf_op3: st_op = Op_StoreD; break;
800
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
812
813 default: ShouldNotReachHere();
814 }
815 if (tertiary == REGP_OP) {
816 if (st_op == Op_StoreI) st_op = Op_StoreP;
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
818 else ShouldNotReachHere();
819 if (st_op) {
820 // a store
821 // inputs are (0:control, 1:memory, 2:address, 3:value)
822 Node* n2 = n->in(3);
823 if (n2 != NULL) {
824 const Type* t = n2->bottom_type();
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
826 }
827 } else {
828 // a load
829 const Type* t = n->bottom_type();
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
831 }
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
852 !(n->rule() == loadUB_rule)) {
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
854 }
855 } else if (st_op) {
856 // a Store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
865 verify_oops_warning(n, n->ideal_Opcode(), st_op);
866 }
867 }
868
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
870 Node* addr = n->in(2);
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
873 if (atype != NULL) {
874 intptr_t offset = get_offset_from_base(n, atype, disp32);
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
876 if (offset != offset_2) {
877 get_offset_from_base(n, atype, disp32);
878 get_offset_from_base_2(n, atype, disp32);
879 }
880 assert(offset == offset_2, "different offsets");
881 if (offset == disp32) {
882 // we now know that src1 is a true oop pointer
883 is_verified_oop_base = true;
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
885 if( primary == Assembler::ldd_op3 ) {
886 is_verified_oop_base = false; // Cannot 'ldd' into O7
887 } else {
888 tmp_enc = dst_enc;
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop
890 assert(src1_enc != dst_enc, "");
891 }
892 }
893 }
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
895 || offset == oopDesc::mark_offset_in_bytes())) {
896 // loading the mark should not be allowed either, but
897 // we don't check this since it conflicts with InlineObjectHash
898 // usage of LoadINode to get the mark. We could keep the
899 // check if we create a new LoadMarkNode
900 // but do not verify the object before its header is initialized
901 ShouldNotReachHere();
902 }
903 }
904 }
905 }
906 }
907 #endif
908
909 uint instr;
910 instr = (Assembler::ldst_op << 30)
911 | (dst_enc << 25)
912 | (primary << 19)
913 | (src1_enc << 14);
914
915 uint index = src2_enc;
916 int disp = disp32;
917
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
919 disp += STACK_BIAS;
920
921 // We should have a compiler bailout here rather than a guarantee.
922 // Better yet would be some mechanism to handle variable-size matches correctly.
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
924
925 if( disp == 0 ) {
926 // use reg-reg form
927 // bit 13 is already zero
928 instr |= index;
929 } else {
930 // use reg-imm form
931 instr |= 0x00002000; // set bit 13 to one
932 instr |= disp & 0x1FFF;
933 }
934
935 cbuf.insts()->emit_int32(instr);
936
937 #ifdef ASSERT
938 {
939 MacroAssembler _masm(&cbuf);
940 if (is_verified_oop_base) {
941 __ verify_oop(reg_to_register_object(src1_enc));
942 }
943 if (is_verified_oop_store) {
944 __ verify_oop(reg_to_register_object(dst_enc));
945 }
946 if (tmp_enc != -1) {
947 __ mov(O7, reg_to_register_object(tmp_enc));
948 }
949 if (is_verified_oop_load) {
950 __ verify_oop(reg_to_register_object(dst_enc));
951 }
952 }
953 #endif
954 }
955
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
957 // The method which records debug information at every safepoint
958 // expects the call to be the first instruction in the snippet as
959 // it creates a PcDesc structure which tracks the offset of a call
960 // from the start of the codeBlob. This offset is computed as
961 // code_end() - code_begin() of the code which has been emitted
962 // so far.
963 // In this particular case we have skirted around the problem by
964 // putting the "mov" instruction in the delay slot but the problem
965 // may bite us again at some other point and a cleaner/generic
966 // solution using relocations would be needed.
967 MacroAssembler _masm(&cbuf);
968 __ set_inst_mark();
969
970 // We flush the current window just so that there is a valid stack copy
971 // the fact that the current window becomes active again instantly is
972 // not a problem there is nothing live in it.
973
974 #ifdef ASSERT
975 int startpos = __ offset();
976 #endif /* ASSERT */
977
978 __ call((address)entry_point, rtype);
979
980 if (preserve_g2) __ delayed()->mov(G2, L7);
981 else __ delayed()->nop();
982
983 if (preserve_g2) __ mov(L7, G2);
984
985 #ifdef ASSERT
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
987 #ifdef _LP64
988 // Trash argument dump slots.
989 __ set(0xb0b8ac0db0b8ac0d, G1);
990 __ mov(G1, G5);
991 __ stx(G1, SP, STACK_BIAS + 0x80);
992 __ stx(G1, SP, STACK_BIAS + 0x88);
993 __ stx(G1, SP, STACK_BIAS + 0x90);
994 __ stx(G1, SP, STACK_BIAS + 0x98);
995 __ stx(G1, SP, STACK_BIAS + 0xA0);
996 __ stx(G1, SP, STACK_BIAS + 0xA8);
997 #else // _LP64
998 // this is also a native call, so smash the first 7 stack locations,
999 // and the various registers
1000
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1002 // while [SP+0x44..0x58] are the argument dump slots.
1003 __ set((intptr_t)0xbaadf00d, G1);
1004 __ mov(G1, G5);
1005 __ sllx(G1, 32, G1);
1006 __ or3(G1, G5, G1);
1007 __ mov(G1, G5);
1008 __ stx(G1, SP, 0x40);
1009 __ stx(G1, SP, 0x48);
1010 __ stx(G1, SP, 0x50);
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1012 #endif // _LP64
1013 }
1014 #endif /*ASSERT*/
1015 }
1016
1017 //=============================================================================
1018 // REQUIRED FUNCTIONALITY for encoding
1019 void emit_lo(CodeBuffer &cbuf, int val) { }
1020 void emit_hi(CodeBuffer &cbuf, int val) { }
1021
1022
1023 //=============================================================================
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1025
1026 int Compile::ConstantTable::calculate_table_base_offset() const {
1027 if (UseRDPCForConstantTableBase) {
1028 // The table base offset might be less but then it fits into
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1030 return Assembler::min_simm13();
1031 } else {
1032 int offset = -(size() / 2);
1033 if (!Assembler::is_simm13(offset)) {
1034 offset = Assembler::min_simm13();
1035 }
1036 return offset;
1037 }
1038 }
1039
1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1041 Compile* C = ra_->C;
1042 Compile::ConstantTable& constant_table = C->constant_table();
1043 MacroAssembler _masm(&cbuf);
1044
1045 Register r = as_Register(ra_->get_encode(this));
1046 CodeSection* consts_section = __ code()->consts();
1047 int consts_size = consts_section->align_at_start(consts_section->size());
1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1049
1050 if (UseRDPCForConstantTableBase) {
1051 // For the following RDPC logic to work correctly the consts
1052 // section must be allocated right before the insts section. This
1053 // assert checks for that. The layout and the SECT_* constants
1054 // are defined in src/share/vm/asm/codeBuffer.hpp.
1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1056 int insts_offset = __ offset();
1057
1058 // Layout:
1059 //
1060 // |----------- consts section ------------|----------- insts section -----------...
1061 // |------ constant table -----|- padding -|------------------x----
1062 // \ current PC (RDPC instruction)
1063 // |<------------- consts_size ----------->|<- insts_offset ->|
1064 // \ table base
1065 // The table base offset is later added to the load displacement
1066 // so it has to be negative.
1067 int table_base_offset = -(consts_size + insts_offset);
1068 int disp;
1069
1070 // If the displacement from the current PC to the constant table
1071 // base fits into simm13 we set the constant table base to the
1072 // current PC.
1073 if (Assembler::is_simm13(table_base_offset)) {
1074 constant_table.set_table_base_offset(table_base_offset);
1075 disp = 0;
1076 } else {
1077 // Otherwise we set the constant table base offset to the
1078 // maximum negative displacement of load instructions to keep
1079 // the disp as small as possible:
1080 //
1081 // |<------------- consts_size ----------->|<- insts_offset ->|
1082 // |<--------- min_simm13 --------->|<-------- disp --------->|
1083 // \ table base
1084 table_base_offset = Assembler::min_simm13();
1085 constant_table.set_table_base_offset(table_base_offset);
1086 disp = (consts_size + insts_offset) + table_base_offset;
1087 }
1088
1089 __ rdpc(r);
1090
1091 if (disp != 0) {
1092 assert(r != O7, "need temporary");
1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1094 }
1095 }
1096 else {
1097 // Materialize the constant table base.
1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1100 AddressLiteral base(baseaddr, rspec);
1101 __ set(base, r);
1102 }
1103 }
1104
1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1106 if (UseRDPCForConstantTableBase) {
1107 // This is really the worst case but generally it's only 1 instruction.
1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1109 } else {
1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1111 }
1112 }
1113
1114 #ifndef PRODUCT
1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1116 char reg[128];
1117 ra_->dump_register(this, reg);
1118 if (UseRDPCForConstantTableBase) {
1119 st->print("RDPC %s\t! constant table base", reg);
1120 } else {
1121 st->print("SET &constanttable,%s\t! constant table base", reg);
1122 }
1123 }
1124 #endif
1125
1126
1127 //=============================================================================
1128
1129 #ifndef PRODUCT
1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1131 Compile* C = ra_->C;
1132
1133 for (int i = 0; i < OptoPrologueNops; i++) {
1134 st->print_cr("NOP"); st->print("\t");
1135 }
1136
1137 if( VerifyThread ) {
1138 st->print_cr("Verify_Thread"); st->print("\t");
1139 }
1140
1141 size_t framesize = C->frame_slots() << LogBytesPerInt;
1142
1143 // Calls to C2R adapters often do not accept exceptional returns.
1144 // We require that their callers must bang for them. But be careful, because
1145 // some VM calls (such as call site linkage) can use several kilobytes of
1146 // stack. But the stack safety zone should account for that.
1147 // See bugs 4446381, 4468289, 4497237.
1148 if (C->need_stack_bang(framesize)) {
1149 st->print_cr("! stack bang"); st->print("\t");
1150 }
1151
1152 if (Assembler::is_simm13(-framesize)) {
1153 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1154 } else {
1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1157 st->print ("SAVE R_SP,R_G3,R_SP");
1158 }
1159
1160 }
1161 #endif
1162
1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1164 Compile* C = ra_->C;
1165 MacroAssembler _masm(&cbuf);
1166
1167 for (int i = 0; i < OptoPrologueNops; i++) {
1168 __ nop();
1169 }
1170
1171 __ verify_thread();
1172
1173 size_t framesize = C->frame_slots() << LogBytesPerInt;
1174 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1176
1177 // Calls to C2R adapters often do not accept exceptional returns.
1178 // We require that their callers must bang for them. But be careful, because
1179 // some VM calls (such as call site linkage) can use several kilobytes of
1180 // stack. But the stack safety zone should account for that.
1181 // See bugs 4446381, 4468289, 4497237.
1182 if (C->need_stack_bang(framesize)) {
1183 __ generate_stack_overflow_check(framesize);
1184 }
1185
1186 if (Assembler::is_simm13(-framesize)) {
1187 __ save(SP, -framesize, SP);
1188 } else {
1189 __ sethi(-framesize & ~0x3ff, G3);
1190 __ add(G3, -framesize & 0x3ff, G3);
1191 __ save(SP, G3, SP);
1192 }
1193 C->set_frame_complete( __ offset() );
1194
1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1196 // NOTE: We set the table base offset here because users might be
1197 // emitted before MachConstantBaseNode.
1198 Compile::ConstantTable& constant_table = C->constant_table();
1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1200 }
1201 }
1202
1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1204 return MachNode::size(ra_);
1205 }
1206
1207 int MachPrologNode::reloc() const {
1208 return 10; // a large enough number
1209 }
1210
1211 //=============================================================================
1212 #ifndef PRODUCT
1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1214 Compile* C = ra_->C;
1215
1216 if( do_polling() && ra_->C->is_method_compilation() ) {
1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1218 #ifdef _LP64
1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1220 #else
1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1222 #endif
1223 }
1224
1225 if( do_polling() )
1226 st->print("RET\n\t");
1227
1228 st->print("RESTORE");
1229 }
1230 #endif
1231
1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 MacroAssembler _masm(&cbuf);
1234 Compile* C = ra_->C;
1235
1236 __ verify_thread();
1237
1238 // If this does safepoint polling, then do it here
1239 if( do_polling() && ra_->C->is_method_compilation() ) {
1240 AddressLiteral polling_page(os::get_polling_page());
1241 __ sethi(polling_page, L0);
1242 __ relocate(relocInfo::poll_return_type);
1243 __ ld_ptr( L0, 0, G0 );
1244 }
1245
1246 // If this is a return, then stuff the restore in the delay slot
1247 if( do_polling() ) {
1248 __ ret();
1249 __ delayed()->restore();
1250 } else {
1251 __ restore();
1252 }
1253 }
1254
1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1256 return MachNode::size(ra_);
1257 }
1258
1259 int MachEpilogNode::reloc() const {
1260 return 16; // a large enough number
1261 }
1262
1263 const Pipeline * MachEpilogNode::pipeline() const {
1264 return MachNode::pipeline_class();
1265 }
1266
1267 int MachEpilogNode::safepoint_offset() const {
1268 assert( do_polling(), "no return for this epilog node");
1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1270 }
1271
1272 //=============================================================================
1273
1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1275 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1276 static enum RC rc_class( OptoReg::Name reg ) {
1277 if( !OptoReg::is_valid(reg) ) return rc_bad;
1278 if (OptoReg::is_stack(reg)) return rc_stack;
1279 VMReg r = OptoReg::as_VMReg(reg);
1280 if (r->is_Register()) return rc_int;
1281 assert(r->is_FloatRegister(), "must be");
1282 return rc_float;
1283 }
1284
1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1286 if( cbuf ) {
1287 // Better yet would be some mechanism to handle variable-size matches correctly
1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1290 } else {
1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1292 }
1293 }
1294 #ifndef PRODUCT
1295 else if( !do_size ) {
1296 if( size != 0 ) st->print("\n\t");
1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1299 }
1300 #endif
1301 return size+4;
1302 }
1303
1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1306 #ifndef PRODUCT
1307 else if( !do_size ) {
1308 if( size != 0 ) st->print("\n\t");
1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1310 }
1311 #endif
1312 return size+4;
1313 }
1314
1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1316 PhaseRegAlloc *ra_,
1317 bool do_size,
1318 outputStream* st ) const {
1319 // Get registers to move
1320 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1321 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1322 OptoReg::Name dst_second = ra_->get_reg_second(this );
1323 OptoReg::Name dst_first = ra_->get_reg_first(this );
1324
1325 enum RC src_second_rc = rc_class(src_second);
1326 enum RC src_first_rc = rc_class(src_first);
1327 enum RC dst_second_rc = rc_class(dst_second);
1328 enum RC dst_first_rc = rc_class(dst_first);
1329
1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1331
1332 // Generate spill code!
1333 int size = 0;
1334
1335 if( src_first == dst_first && src_second == dst_second )
1336 return size; // Self copy, no move
1337
1338 // --------------------------------------
1339 // Check for mem-mem move. Load into unused float registers and fall into
1340 // the float-store case.
1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1342 int offset = ra_->reg2offset(src_first);
1343 // Further check for aligned-adjacent pair, so we can use a double load
1344 if( (src_first&1)==0 && src_first+1 == src_second ) {
1345 src_second = OptoReg::Name(R_F31_num);
1346 src_second_rc = rc_float;
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1348 } else {
1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1350 }
1351 src_first = OptoReg::Name(R_F30_num);
1352 src_first_rc = rc_float;
1353 }
1354
1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1356 int offset = ra_->reg2offset(src_second);
1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1358 src_second = OptoReg::Name(R_F31_num);
1359 src_second_rc = rc_float;
1360 }
1361
1362 // --------------------------------------
1363 // Check for float->int copy; requires a trip through memory
1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1365 int offset = frame::register_save_words*wordSize;
1366 if (cbuf) {
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1371 }
1372 #ifndef PRODUCT
1373 else if (!do_size) {
1374 if (size != 0) st->print("\n\t");
1375 st->print( "SUB R_SP,16,R_SP\n");
1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1378 st->print("\tADD R_SP,16,R_SP\n");
1379 }
1380 #endif
1381 size += 16;
1382 }
1383
1384 // Check for float->int copy on T4
1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1386 // Further check for aligned-adjacent pair, so we can use a double move
1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1390 }
1391 // Check for int->float copy on T4
1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1393 // Further check for aligned-adjacent pair, so we can use a double move
1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1397 }
1398
1399 // --------------------------------------
1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1401 // In such cases, I have to do the big-endian swap. For aligned targets, the
1402 // hardware does the flop for me. Doubles are always aligned, so no problem
1403 // there. Misaligned sources only come from native-long-returns (handled
1404 // special below).
1405 #ifndef _LP64
1406 if( src_first_rc == rc_int && // source is already big-endian
1407 src_second_rc != rc_bad && // 64-bit move
1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1410 // Do the big-endian flop.
1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1413 }
1414 #endif
1415
1416 // --------------------------------------
1417 // Check for integer reg-reg copy
1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1419 #ifndef _LP64
1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1423 // operand contains the least significant word of the 64-bit value and vice versa.
1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1427 if( cbuf ) {
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1431 #ifndef PRODUCT
1432 } else if( !do_size ) {
1433 if( size != 0 ) st->print("\n\t");
1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1437 #endif
1438 }
1439 return size+12;
1440 }
1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1442 // returning a long value in I0/I1
1443 // a SpillCopy must be able to target a return instruction's reg_class
1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1446 // operand contains the least significant word of the 64-bit value and vice versa.
1447 OptoReg::Name tdest = dst_first;
1448
1449 if (src_first == dst_first) {
1450 tdest = OptoReg::Name(R_O7_num);
1451 size += 4;
1452 }
1453
1454 if( cbuf ) {
1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1457 // ShrL_reg_imm6
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1459 // ShrR_reg_imm6 src, 0, dst
1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1461 if (tdest != dst_first) {
1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1463 }
1464 }
1465 #ifndef PRODUCT
1466 else if( !do_size ) {
1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1470 if (tdest != dst_first) {
1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1472 }
1473 }
1474 #endif // PRODUCT
1475 return size+8;
1476 }
1477 #endif // !_LP64
1478 // Else normal reg-reg copy
1479 assert( src_second != dst_first, "smashed second before evacuating it" );
1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1482 // This moves an aligned adjacent pair.
1483 // See if we are done.
1484 if( src_first+1 == src_second && dst_first+1 == dst_second )
1485 return size;
1486 }
1487
1488 // Check for integer store
1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(dst_first);
1491 // Further check for aligned-adjacent pair, so we can use a double store
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1495 }
1496
1497 // Check for integer load
1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1499 int offset = ra_->reg2offset(src_first);
1500 // Further check for aligned-adjacent pair, so we can use a double load
1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1504 }
1505
1506 // Check for float reg-reg copy
1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1508 // Further check for aligned-adjacent pair, so we can use a double move
1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1512 }
1513
1514 // Check for float store
1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1516 int offset = ra_->reg2offset(dst_first);
1517 // Further check for aligned-adjacent pair, so we can use a double store
1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1521 }
1522
1523 // Check for float load
1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1525 int offset = ra_->reg2offset(src_first);
1526 // Further check for aligned-adjacent pair, so we can use a double load
1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1530 }
1531
1532 // --------------------------------------------------------------------
1533 // Check for hi bits still needing moving. Only happens for misaligned
1534 // arguments to native calls.
1535 if( src_second == dst_second )
1536 return size; // Self copy; no move
1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1538
1539 #ifndef _LP64
1540 // In the LP64 build, all registers can be moved as aligned/adjacent
1541 // pairs, so there's never any need to move the high bits separately.
1542 // The 32-bit builds have to deal with the 32-bit ABI which can force
1543 // all sorts of silly alignment problems.
1544
1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1546 // 32-bits of a 64-bit register, but are needed in low bits of another
1547 // register (else it's a hi-bits-to-hi-bits copy which should have
1548 // happened already as part of a 64-bit move)
1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1552 // Shift src_second down to dst_second's low bits.
1553 if( cbuf ) {
1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1555 #ifndef PRODUCT
1556 } else if( !do_size ) {
1557 if( size != 0 ) st->print("\n\t");
1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1559 #endif
1560 }
1561 return size+4;
1562 }
1563
1564 // Check for high word integer store. Must down-shift the hi bits
1565 // into a temp register, then fall into the case of storing int bits.
1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1567 // Shift src_second down to dst_second's low bits.
1568 if( cbuf ) {
1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1570 #ifndef PRODUCT
1571 } else if( !do_size ) {
1572 if( size != 0 ) st->print("\n\t");
1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1574 #endif
1575 }
1576 size+=4;
1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1578 }
1579
1580 // Check for high word integer load
1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1583
1584 // Check for high word integer store
1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1587
1588 // Check for high word float store
1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1591
1592 #endif // !_LP64
1593
1594 Unimplemented();
1595 }
1596
1597 #ifndef PRODUCT
1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1599 implementation( NULL, ra_, false, st );
1600 }
1601 #endif
1602
1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1604 implementation( &cbuf, ra_, false, NULL );
1605 }
1606
1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1608 return implementation( NULL, ra_, true, NULL );
1609 }
1610
1611 //=============================================================================
1612 #ifndef PRODUCT
1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1615 }
1616 #endif
1617
1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1619 MacroAssembler _masm(&cbuf);
1620 for(int i = 0; i < _count; i += 1) {
1621 __ nop();
1622 }
1623 }
1624
1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1626 return 4 * _count;
1627 }
1628
1629
1630 //=============================================================================
1631 #ifndef PRODUCT
1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1634 int reg = ra_->get_reg_first(this);
1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1636 }
1637 #endif
1638
1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1640 MacroAssembler _masm(&cbuf);
1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1642 int reg = ra_->get_encode(this);
1643
1644 if (Assembler::is_simm13(offset)) {
1645 __ add(SP, offset, reg_to_register_object(reg));
1646 } else {
1647 __ set(offset, O7);
1648 __ add(SP, O7, reg_to_register_object(reg));
1649 }
1650 }
1651
1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1654 assert(ra_ == ra_->C->regalloc(), "sanity");
1655 return ra_->C->scratch_emit_size(this);
1656 }
1657
1658 //=============================================================================
1659
1660 // emit call stub, compiled java to interpretor
1661 void emit_java_to_interp(CodeBuffer &cbuf ) {
1662
1663 // Stub is fixed up when the corresponding call is converted from calling
1664 // compiled code to calling interpreted code.
1665 // set (empty), G5
1666 // jmp -1
1667
1668 address mark = cbuf.insts_mark(); // get mark within main instrs section
1669
1670 MacroAssembler _masm(&cbuf);
1671
1672 address base =
1673 __ start_a_stub(Compile::MAX_stubs_size);
1674 if (base == NULL) return; // CodeBuffer::expand failed
1675
1676 // static stub relocation stores the instruction address of the call
1677 __ relocate(static_stub_Relocation::spec(mark));
1678
1679 __ set_metadata(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1680
1681 __ set_inst_mark();
1682 AddressLiteral addrlit(-1);
1683 __ JUMP(addrlit, G3, 0);
1684
1685 __ delayed()->nop();
1686
1687 // Update current stubs pointer and restore code_end.
1688 __ end_a_stub();
1689 }
1690
1691 // size of call stub, compiled java to interpretor
1692 uint size_java_to_interp() {
1693 // This doesn't need to be accurate but it must be larger or equal to
1694 // the real size of the stub.
1695 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1696 NativeJump::instruction_size + // sethi; jmp; nop
1697 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1698 }
1699 // relocation entries for call stub, compiled java to interpretor
1700 uint reloc_java_to_interp() {
1701 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1702 }
1703
1704
1705 //=============================================================================
1706 #ifndef PRODUCT
1707 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1708 st->print_cr("\nUEP:");
1709 #ifdef _LP64
1710 if (UseCompressedOops) {
1711 assert(Universe::heap() != NULL, "java heap should be initialized");
1712 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1713 st->print_cr("\tSLL R_G5,3,R_G5");
1714 if (Universe::narrow_oop_base() != NULL)
1715 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1716 } else {
1717 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1718 }
1719 st->print_cr("\tCMP R_G5,R_G3" );
1720 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1721 #else // _LP64
1722 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1723 st->print_cr("\tCMP R_G5,R_G3" );
1724 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1725 #endif // _LP64
1726 }
1727 #endif
1728
1729 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1730 MacroAssembler _masm(&cbuf);
1731 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1732 Register temp_reg = G3;
1733 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1734
1735 // Load klass from receiver
1736 __ load_klass(O0, temp_reg);
1737 // Compare against expected klass
1738 __ cmp(temp_reg, G5_ic_reg);
1739 // Branch to miss code, checks xcc or icc depending
1740 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1741 }
1742
1743 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1744 return MachNode::size(ra_);
1745 }
1746
1747
1748 //=============================================================================
1749
1750 uint size_exception_handler() {
1751 if (TraceJumps) {
1752 return (400); // just a guess
1753 }
1754 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1755 }
1756
1757 uint size_deopt_handler() {
1758 if (TraceJumps) {
1759 return (400); // just a guess
1760 }
1761 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1762 }
1763
1764 // Emit exception handler code.
1765 int emit_exception_handler(CodeBuffer& cbuf) {
1766 Register temp_reg = G3;
1767 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1768 MacroAssembler _masm(&cbuf);
1769
1770 address base =
1771 __ start_a_stub(size_exception_handler());
1772 if (base == NULL) return 0; // CodeBuffer::expand failed
1773
1774 int offset = __ offset();
1775
1776 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1777 __ delayed()->nop();
1778
1779 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1780
1781 __ end_a_stub();
1782
1783 return offset;
1784 }
1785
1786 int emit_deopt_handler(CodeBuffer& cbuf) {
1787 // Can't use any of the current frame's registers as we may have deopted
1788 // at a poll and everything (including G3) can be live.
1789 Register temp_reg = L0;
1790 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1791 MacroAssembler _masm(&cbuf);
1792
1793 address base =
1794 __ start_a_stub(size_deopt_handler());
1795 if (base == NULL) return 0; // CodeBuffer::expand failed
1796
1797 int offset = __ offset();
1798 __ save_frame(0);
1799 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1800 __ delayed()->restore();
1801
1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1803
1804 __ end_a_stub();
1805 return offset;
1806
1807 }
1808
1809 // Given a register encoding, produce a Integer Register object
1810 static Register reg_to_register_object(int register_encoding) {
1811 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1812 return as_Register(register_encoding);
1813 }
1814
1815 // Given a register encoding, produce a single-precision Float Register object
1816 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1817 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1818 return as_SingleFloatRegister(register_encoding);
1819 }
1820
1821 // Given a register encoding, produce a double-precision Float Register object
1822 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1823 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1824 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1825 return as_DoubleFloatRegister(register_encoding);
1826 }
1827
1828 const bool Matcher::match_rule_supported(int opcode) {
1829 if (!has_match_rule(opcode))
1830 return false;
1831
1832 switch (opcode) {
1833 case Op_CountLeadingZerosI:
1834 case Op_CountLeadingZerosL:
1835 case Op_CountTrailingZerosI:
1836 case Op_CountTrailingZerosL:
1837 case Op_PopCountI:
1838 case Op_PopCountL:
1839 if (!UsePopCountInstruction)
1840 return false;
1841 case Op_CompareAndSwapL:
1842 #ifdef _LP64
1843 case Op_CompareAndSwapP:
1844 #endif
1845 if (!VM_Version::supports_cx8())
1846 return false;
1847 break;
1848 }
1849
1850 return true; // Per default match rules are supported.
1851 }
1852
1853 int Matcher::regnum_to_fpu_offset(int regnum) {
1854 return regnum - 32; // The FP registers are in the second chunk
1855 }
1856
1857 #ifdef ASSERT
1858 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1859 #endif
1860
1861 // Vector width in bytes
1862 const int Matcher::vector_width_in_bytes(BasicType bt) {
1863 assert(MaxVectorSize == 8, "");
1864 return 8;
1865 }
1866
1867 // Vector ideal reg
1868 const int Matcher::vector_ideal_reg(int size) {
1869 assert(MaxVectorSize == 8, "");
1870 return Op_RegD;
1871 }
1872
1873 const int Matcher::vector_shift_count_ideal_reg(int size) {
1874 fatal("vector shift is not supported");
1875 return Node::NotAMachineReg;
1876 }
1877
1878 // Limits on vector size (number of elements) loaded into vector.
1879 const int Matcher::max_vector_size(const BasicType bt) {
1880 assert(is_java_primitive(bt), "only primitive type vectors");
1881 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1882 }
1883
1884 const int Matcher::min_vector_size(const BasicType bt) {
1885 return max_vector_size(bt); // Same as max.
1886 }
1887
1888 // SPARC doesn't support misaligned vectors store/load.
1889 const bool Matcher::misaligned_vectors_ok() {
1890 return false;
1891 }
1892
1893 // USII supports fxtof through the whole range of number, USIII doesn't
1894 const bool Matcher::convL2FSupported(void) {
1895 return VM_Version::has_fast_fxtof();
1896 }
1897
1898 // Is this branch offset short enough that a short branch can be used?
1899 //
1900 // NOTE: If the platform does not provide any short branch variants, then
1901 // this method should return false for offset 0.
1902 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1903 // The passed offset is relative to address of the branch.
1904 // Don't need to adjust the offset.
1905 return UseCBCond && Assembler::is_simm12(offset);
1906 }
1907
1908 const bool Matcher::isSimpleConstant64(jlong value) {
1909 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1910 // Depends on optimizations in MacroAssembler::setx.
1911 int hi = (int)(value >> 32);
1912 int lo = (int)(value & ~0);
1913 return (hi == 0) || (hi == -1) || (lo == 0);
1914 }
1915
1916 // No scaling for the parameter the ClearArray node.
1917 const bool Matcher::init_array_count_is_in_bytes = true;
1918
1919 // Threshold size for cleararray.
1920 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1921
1922 // No additional cost for CMOVL.
1923 const int Matcher::long_cmove_cost() { return 0; }
1924
1925 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1926 const int Matcher::float_cmove_cost() {
1927 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1928 }
1929
1930 // Should the Matcher clone shifts on addressing modes, expecting them to
1931 // be subsumed into complex addressing expressions or compute them into
1932 // registers? True for Intel but false for most RISCs
1933 const bool Matcher::clone_shift_expressions = false;
1934
1935 // Do we need to mask the count passed to shift instructions or does
1936 // the cpu only look at the lower 5/6 bits anyway?
1937 const bool Matcher::need_masked_shift_count = false;
1938
1939 bool Matcher::narrow_oop_use_complex_address() {
1940 NOT_LP64(ShouldNotCallThis());
1941 assert(UseCompressedOops, "only for compressed oops code");
1942 return false;
1943 }
1944
1945 // Is it better to copy float constants, or load them directly from memory?
1946 // Intel can load a float constant from a direct address, requiring no
1947 // extra registers. Most RISCs will have to materialize an address into a
1948 // register first, so they would do better to copy the constant from stack.
1949 const bool Matcher::rematerialize_float_constants = false;
1950
1951 // If CPU can load and store mis-aligned doubles directly then no fixup is
1952 // needed. Else we split the double into 2 integer pieces and move it
1953 // piece-by-piece. Only happens when passing doubles into C code as the
1954 // Java calling convention forces doubles to be aligned.
1955 #ifdef _LP64
1956 const bool Matcher::misaligned_doubles_ok = true;
1957 #else
1958 const bool Matcher::misaligned_doubles_ok = false;
1959 #endif
1960
1961 // No-op on SPARC.
1962 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1963 }
1964
1965 // Advertise here if the CPU requires explicit rounding operations
1966 // to implement the UseStrictFP mode.
1967 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1968
1969 // Are floats conerted to double when stored to stack during deoptimization?
1970 // Sparc does not handle callee-save floats.
1971 bool Matcher::float_in_double() { return false; }
1972
1973 // Do ints take an entire long register or just half?
1974 // Note that we if-def off of _LP64.
1975 // The relevant question is how the int is callee-saved. In _LP64
1976 // the whole long is written but de-opt'ing will have to extract
1977 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1978 #ifdef _LP64
1979 const bool Matcher::int_in_long = true;
1980 #else
1981 const bool Matcher::int_in_long = false;
1982 #endif
1983
1984 // Return whether or not this register is ever used as an argument. This
1985 // function is used on startup to build the trampoline stubs in generateOptoStub.
1986 // Registers not mentioned will be killed by the VM call in the trampoline, and
1987 // arguments in those registers not be available to the callee.
1988 bool Matcher::can_be_java_arg( int reg ) {
1989 // Standard sparc 6 args in registers
1990 if( reg == R_I0_num ||
1991 reg == R_I1_num ||
1992 reg == R_I2_num ||
1993 reg == R_I3_num ||
1994 reg == R_I4_num ||
1995 reg == R_I5_num ) return true;
1996 #ifdef _LP64
1997 // 64-bit builds can pass 64-bit pointers and longs in
1998 // the high I registers
1999 if( reg == R_I0H_num ||
2000 reg == R_I1H_num ||
2001 reg == R_I2H_num ||
2002 reg == R_I3H_num ||
2003 reg == R_I4H_num ||
2004 reg == R_I5H_num ) return true;
2005
2006 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2007 return true;
2008 }
2009
2010 #else
2011 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2012 // Longs cannot be passed in O regs, because O regs become I regs
2013 // after a 'save' and I regs get their high bits chopped off on
2014 // interrupt.
2015 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2016 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2017 #endif
2018 // A few float args in registers
2019 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2020
2021 return false;
2022 }
2023
2024 bool Matcher::is_spillable_arg( int reg ) {
2025 return can_be_java_arg(reg);
2026 }
2027
2028 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2029 // Use hardware SDIVX instruction when it is
2030 // faster than a code which use multiply.
2031 return VM_Version::has_fast_idiv();
2032 }
2033
2034 // Register for DIVI projection of divmodI
2035 RegMask Matcher::divI_proj_mask() {
2036 ShouldNotReachHere();
2037 return RegMask();
2038 }
2039
2040 // Register for MODI projection of divmodI
2041 RegMask Matcher::modI_proj_mask() {
2042 ShouldNotReachHere();
2043 return RegMask();
2044 }
2045
2046 // Register for DIVL projection of divmodL
2047 RegMask Matcher::divL_proj_mask() {
2048 ShouldNotReachHere();
2049 return RegMask();
2050 }
2051
2052 // Register for MODL projection of divmodL
2053 RegMask Matcher::modL_proj_mask() {
2054 ShouldNotReachHere();
2055 return RegMask();
2056 }
2057
2058 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2059 return L7_REGP_mask();
2060 }
2061
2062 %}
2063
2064
2065 // The intptr_t operand types, defined by textual substitution.
2066 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2067 #ifdef _LP64
2068 #define immX immL
2069 #define immX13 immL13
2070 #define immX13m7 immL13m7
2071 #define iRegX iRegL
2072 #define g1RegX g1RegL
2073 #else
2074 #define immX immI
2075 #define immX13 immI13
2076 #define immX13m7 immI13m7
2077 #define iRegX iRegI
2078 #define g1RegX g1RegI
2079 #endif
2080
2081 //----------ENCODING BLOCK-----------------------------------------------------
2082 // This block specifies the encoding classes used by the compiler to output
2083 // byte streams. Encoding classes are parameterized macros used by
2084 // Machine Instruction Nodes in order to generate the bit encoding of the
2085 // instruction. Operands specify their base encoding interface with the
2086 // interface keyword. There are currently supported four interfaces,
2087 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2088 // operand to generate a function which returns its register number when
2089 // queried. CONST_INTER causes an operand to generate a function which
2090 // returns the value of the constant when queried. MEMORY_INTER causes an
2091 // operand to generate four functions which return the Base Register, the
2092 // Index Register, the Scale Value, and the Offset Value of the operand when
2093 // queried. COND_INTER causes an operand to generate six functions which
2094 // return the encoding code (ie - encoding bits for the instruction)
2095 // associated with each basic boolean condition for a conditional instruction.
2096 //
2097 // Instructions specify two basic values for encoding. Again, a function
2098 // is available to check if the constant displacement is an oop. They use the
2099 // ins_encode keyword to specify their encoding classes (which must be
2100 // a sequence of enc_class names, and their parameters, specified in
2101 // the encoding block), and they use the
2102 // opcode keyword to specify, in order, their primary, secondary, and
2103 // tertiary opcode. Only the opcode sections which a particular instruction
2104 // needs for encoding need to be specified.
2105 encode %{
2106 enc_class enc_untested %{
2107 #ifdef ASSERT
2108 MacroAssembler _masm(&cbuf);
2109 __ untested("encoding");
2110 #endif
2111 %}
2112
2113 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2114 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2115 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2116 %}
2117
2118 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2119 emit_form3_mem_reg(cbuf, this, $primary, -1,
2120 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2121 %}
2122
2123 enc_class form3_mem_prefetch_read( memory mem ) %{
2124 emit_form3_mem_reg(cbuf, this, $primary, -1,
2125 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2126 %}
2127
2128 enc_class form3_mem_prefetch_write( memory mem ) %{
2129 emit_form3_mem_reg(cbuf, this, $primary, -1,
2130 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2131 %}
2132
2133 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2134 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2135 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2136 guarantee($mem$$index == R_G0_enc, "double index?");
2137 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2138 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2139 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2140 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2141 %}
2142
2143 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2144 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2145 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2146 guarantee($mem$$index == R_G0_enc, "double index?");
2147 // Load long with 2 instructions
2148 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2149 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2150 %}
2151
2152 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2153 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2154 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2155 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2156 %}
2157
2158 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2159 // Encode a reg-reg copy. If it is useless, then empty encoding.
2160 if( $rs2$$reg != $rd$$reg )
2161 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2162 %}
2163
2164 // Target lo half of long
2165 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2166 // Encode a reg-reg copy. If it is useless, then empty encoding.
2167 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2168 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2169 %}
2170
2171 // Source lo half of long
2172 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2173 // Encode a reg-reg copy. If it is useless, then empty encoding.
2174 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2175 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2176 %}
2177
2178 // Target hi half of long
2179 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2180 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2181 %}
2182
2183 // Source lo half of long, and leave it sign extended.
2184 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2185 // Sign extend low half
2186 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2187 %}
2188
2189 // Source hi half of long, and leave it sign extended.
2190 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2191 // Shift high half to low half
2192 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2193 %}
2194
2195 // Source hi half of long
2196 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2197 // Encode a reg-reg copy. If it is useless, then empty encoding.
2198 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2199 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2200 %}
2201
2202 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2203 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2204 %}
2205
2206 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2207 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2208 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2209 %}
2210
2211 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2212 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2213 // clear if nothing else is happening
2214 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2215 // blt,a,pn done
2216 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2217 // mov dst,-1 in delay slot
2218 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2219 %}
2220
2221 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2222 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2223 %}
2224
2225 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2226 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2227 %}
2228
2229 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2230 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2231 %}
2232
2233 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2234 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2235 %}
2236
2237 enc_class move_return_pc_to_o1() %{
2238 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2239 %}
2240
2241 #ifdef _LP64
2242 /* %%% merge with enc_to_bool */
2243 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2244 MacroAssembler _masm(&cbuf);
2245
2246 Register src_reg = reg_to_register_object($src$$reg);
2247 Register dst_reg = reg_to_register_object($dst$$reg);
2248 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2249 %}
2250 #endif
2251
2252 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2253 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2254 MacroAssembler _masm(&cbuf);
2255
2256 Register p_reg = reg_to_register_object($p$$reg);
2257 Register q_reg = reg_to_register_object($q$$reg);
2258 Register y_reg = reg_to_register_object($y$$reg);
2259 Register tmp_reg = reg_to_register_object($tmp$$reg);
2260
2261 __ subcc( p_reg, q_reg, p_reg );
2262 __ add ( p_reg, y_reg, tmp_reg );
2263 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2264 %}
2265
2266 enc_class form_d2i_helper(regD src, regF dst) %{
2267 // fcmp %fcc0,$src,$src
2268 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2269 // branch %fcc0 not-nan, predict taken
2270 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2271 // fdtoi $src,$dst
2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2273 // fitos $dst,$dst (if nan)
2274 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2275 // clear $dst (if nan)
2276 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2277 // carry on here...
2278 %}
2279
2280 enc_class form_d2l_helper(regD src, regD dst) %{
2281 // fcmp %fcc0,$src,$src check for NAN
2282 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2283 // branch %fcc0 not-nan, predict taken
2284 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2285 // fdtox $src,$dst convert in delay slot
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2287 // fxtod $dst,$dst (if nan)
2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2289 // clear $dst (if nan)
2290 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2291 // carry on here...
2292 %}
2293
2294 enc_class form_f2i_helper(regF src, regF dst) %{
2295 // fcmps %fcc0,$src,$src
2296 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2297 // branch %fcc0 not-nan, predict taken
2298 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2299 // fstoi $src,$dst
2300 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2301 // fitos $dst,$dst (if nan)
2302 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2303 // clear $dst (if nan)
2304 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2305 // carry on here...
2306 %}
2307
2308 enc_class form_f2l_helper(regF src, regD dst) %{
2309 // fcmps %fcc0,$src,$src
2310 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2311 // branch %fcc0 not-nan, predict taken
2312 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2313 // fstox $src,$dst
2314 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2315 // fxtod $dst,$dst (if nan)
2316 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2317 // clear $dst (if nan)
2318 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2319 // carry on here...
2320 %}
2321
2322 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2323 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2324 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2325 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2326
2327 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2328
2329 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2330 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2331
2332 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2333 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2334 %}
2335
2336 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2337 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2338 %}
2339
2340 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2341 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2342 %}
2343
2344 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2345 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2346 %}
2347
2348 enc_class form3_convI2F(regF rs2, regF rd) %{
2349 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2350 %}
2351
2352 // Encloding class for traceable jumps
2353 enc_class form_jmpl(g3RegP dest) %{
2354 emit_jmpl(cbuf, $dest$$reg);
2355 %}
2356
2357 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2358 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2359 %}
2360
2361 enc_class form2_nop() %{
2362 emit_nop(cbuf);
2363 %}
2364
2365 enc_class form2_illtrap() %{
2366 emit_illtrap(cbuf);
2367 %}
2368
2369
2370 // Compare longs and convert into -1, 0, 1.
2371 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2372 // CMP $src1,$src2
2373 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2374 // blt,a,pn done
2375 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2376 // mov dst,-1 in delay slot
2377 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2378 // bgt,a,pn done
2379 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2380 // mov dst,1 in delay slot
2381 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2382 // CLR $dst
2383 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2384 %}
2385
2386 enc_class enc_PartialSubtypeCheck() %{
2387 MacroAssembler _masm(&cbuf);
2388 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2389 __ delayed()->nop();
2390 %}
2391
2392 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2393 MacroAssembler _masm(&cbuf);
2394 Label* L = $labl$$label;
2395 Assembler::Predict predict_taken =
2396 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2397
2398 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2399 __ delayed()->nop();
2400 %}
2401
2402 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2403 MacroAssembler _masm(&cbuf);
2404 Label* L = $labl$$label;
2405 Assembler::Predict predict_taken =
2406 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2407
2408 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2409 __ delayed()->nop();
2410 %}
2411
2412 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2413 int op = (Assembler::arith_op << 30) |
2414 ($dst$$reg << 25) |
2415 (Assembler::movcc_op3 << 19) |
2416 (1 << 18) | // cc2 bit for 'icc'
2417 ($cmp$$cmpcode << 14) |
2418 (0 << 13) | // select register move
2419 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2420 ($src$$reg << 0);
2421 cbuf.insts()->emit_int32(op);
2422 %}
2423
2424 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2425 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2426 int op = (Assembler::arith_op << 30) |
2427 ($dst$$reg << 25) |
2428 (Assembler::movcc_op3 << 19) |
2429 (1 << 18) | // cc2 bit for 'icc'
2430 ($cmp$$cmpcode << 14) |
2431 (1 << 13) | // select immediate move
2432 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2433 (simm11 << 0);
2434 cbuf.insts()->emit_int32(op);
2435 %}
2436
2437 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2438 int op = (Assembler::arith_op << 30) |
2439 ($dst$$reg << 25) |
2440 (Assembler::movcc_op3 << 19) |
2441 (0 << 18) | // cc2 bit for 'fccX'
2442 ($cmp$$cmpcode << 14) |
2443 (0 << 13) | // select register move
2444 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2445 ($src$$reg << 0);
2446 cbuf.insts()->emit_int32(op);
2447 %}
2448
2449 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2450 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2451 int op = (Assembler::arith_op << 30) |
2452 ($dst$$reg << 25) |
2453 (Assembler::movcc_op3 << 19) |
2454 (0 << 18) | // cc2 bit for 'fccX'
2455 ($cmp$$cmpcode << 14) |
2456 (1 << 13) | // select immediate move
2457 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2458 (simm11 << 0);
2459 cbuf.insts()->emit_int32(op);
2460 %}
2461
2462 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2463 int op = (Assembler::arith_op << 30) |
2464 ($dst$$reg << 25) |
2465 (Assembler::fpop2_op3 << 19) |
2466 (0 << 18) |
2467 ($cmp$$cmpcode << 14) |
2468 (1 << 13) | // select register move
2469 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2470 ($primary << 5) | // select single, double or quad
2471 ($src$$reg << 0);
2472 cbuf.insts()->emit_int32(op);
2473 %}
2474
2475 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2476 int op = (Assembler::arith_op << 30) |
2477 ($dst$$reg << 25) |
2478 (Assembler::fpop2_op3 << 19) |
2479 (0 << 18) |
2480 ($cmp$$cmpcode << 14) |
2481 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2482 ($primary << 5) | // select single, double or quad
2483 ($src$$reg << 0);
2484 cbuf.insts()->emit_int32(op);
2485 %}
2486
2487 // Used by the MIN/MAX encodings. Same as a CMOV, but
2488 // the condition comes from opcode-field instead of an argument.
2489 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2490 int op = (Assembler::arith_op << 30) |
2491 ($dst$$reg << 25) |
2492 (Assembler::movcc_op3 << 19) |
2493 (1 << 18) | // cc2 bit for 'icc'
2494 ($primary << 14) |
2495 (0 << 13) | // select register move
2496 (0 << 11) | // cc1, cc0 bits for 'icc'
2497 ($src$$reg << 0);
2498 cbuf.insts()->emit_int32(op);
2499 %}
2500
2501 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2502 int op = (Assembler::arith_op << 30) |
2503 ($dst$$reg << 25) |
2504 (Assembler::movcc_op3 << 19) |
2505 (6 << 16) | // cc2 bit for 'xcc'
2506 ($primary << 14) |
2507 (0 << 13) | // select register move
2508 (0 << 11) | // cc1, cc0 bits for 'icc'
2509 ($src$$reg << 0);
2510 cbuf.insts()->emit_int32(op);
2511 %}
2512
2513 enc_class Set13( immI13 src, iRegI rd ) %{
2514 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2515 %}
2516
2517 enc_class SetHi22( immI src, iRegI rd ) %{
2518 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2519 %}
2520
2521 enc_class Set32( immI src, iRegI rd ) %{
2522 MacroAssembler _masm(&cbuf);
2523 __ set($src$$constant, reg_to_register_object($rd$$reg));
2524 %}
2525
2526 enc_class call_epilog %{
2527 if( VerifyStackAtCalls ) {
2528 MacroAssembler _masm(&cbuf);
2529 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2530 Register temp_reg = G3;
2531 __ add(SP, framesize, temp_reg);
2532 __ cmp(temp_reg, FP);
2533 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2534 }
2535 %}
2536
2537 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2538 // to G1 so the register allocator will not have to deal with the misaligned register
2539 // pair.
2540 enc_class adjust_long_from_native_call %{
2541 #ifndef _LP64
2542 if (returns_long()) {
2543 // sllx O0,32,O0
2544 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2545 // srl O1,0,O1
2546 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2547 // or O0,O1,G1
2548 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2549 }
2550 #endif
2551 %}
2552
2553 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2554 // CALL directly to the runtime
2555 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2556 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2557 /*preserve_g2=*/true);
2558 %}
2559
2560 enc_class preserve_SP %{
2561 MacroAssembler _masm(&cbuf);
2562 __ mov(SP, L7_mh_SP_save);
2563 %}
2564
2565 enc_class restore_SP %{
2566 MacroAssembler _masm(&cbuf);
2567 __ mov(L7_mh_SP_save, SP);
2568 %}
2569
2570 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2571 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2572 // who we intended to call.
2573 if ( !_method ) {
2574 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2575 } else if (_optimized_virtual) {
2576 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2577 } else {
2578 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2579 }
2580 if( _method ) { // Emit stub for static call
2581 emit_java_to_interp(cbuf);
2582 }
2583 %}
2584
2585 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2586 MacroAssembler _masm(&cbuf);
2587 __ set_inst_mark();
2588 int vtable_index = this->_vtable_index;
2589 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2590 if (vtable_index < 0) {
2591 // must be invalid_vtable_index, not nonvirtual_vtable_index
2592 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2594 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2595 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2596 __ ic_call((address)$meth$$method);
2597 } else {
2598 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2599 // Just go thru the vtable
2600 // get receiver klass (receiver already checked for non-null)
2601 // If we end up going thru a c2i adapter interpreter expects method in G5
2602 int off = __ offset();
2603 __ load_klass(O0, G3_scratch);
2604 int klass_load_size;
2605 if (UseCompressedOops && UseCompressedKlassPointers) {
2606 assert(Universe::heap() != NULL, "java heap should be initialized");
2607 if (Universe::narrow_oop_base() == NULL)
2608 klass_load_size = 2*BytesPerInstWord;
2609 else
2610 klass_load_size = 3*BytesPerInstWord;
2611 } else {
2612 klass_load_size = 1*BytesPerInstWord;
2613 }
2614 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2615 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2616 if (Assembler::is_simm13(v_off)) {
2617 __ ld_ptr(G3, v_off, G5_method);
2618 } else {
2619 // Generate 2 instructions
2620 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2621 __ or3(G5_method, v_off & 0x3ff, G5_method);
2622 // ld_ptr, set_hi, set
2623 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2624 "Unexpected instruction size(s)");
2625 __ ld_ptr(G3, G5_method, G5_method);
2626 }
2627 // NOTE: for vtable dispatches, the vtable entry will never be null.
2628 // However it may very well end up in handle_wrong_method if the
2629 // method is abstract for the particular class.
2630 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2631 // jump to target (either compiled code or c2iadapter)
2632 __ jmpl(G3_scratch, G0, O7);
2633 __ delayed()->nop();
2634 }
2635 %}
2636
2637 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2638 MacroAssembler _masm(&cbuf);
2639
2640 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2641 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2642 // we might be calling a C2I adapter which needs it.
2643
2644 assert(temp_reg != G5_ic_reg, "conflicting registers");
2645 // Load nmethod
2646 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2647
2648 // CALL to compiled java, indirect the contents of G3
2649 __ set_inst_mark();
2650 __ callr(temp_reg, G0);
2651 __ delayed()->nop();
2652 %}
2653
2654 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2655 MacroAssembler _masm(&cbuf);
2656 Register Rdividend = reg_to_register_object($src1$$reg);
2657 Register Rdivisor = reg_to_register_object($src2$$reg);
2658 Register Rresult = reg_to_register_object($dst$$reg);
2659
2660 __ sra(Rdivisor, 0, Rdivisor);
2661 __ sra(Rdividend, 0, Rdividend);
2662 __ sdivx(Rdividend, Rdivisor, Rresult);
2663 %}
2664
2665 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2666 MacroAssembler _masm(&cbuf);
2667
2668 Register Rdividend = reg_to_register_object($src1$$reg);
2669 int divisor = $imm$$constant;
2670 Register Rresult = reg_to_register_object($dst$$reg);
2671
2672 __ sra(Rdividend, 0, Rdividend);
2673 __ sdivx(Rdividend, divisor, Rresult);
2674 %}
2675
2676 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2677 MacroAssembler _masm(&cbuf);
2678 Register Rsrc1 = reg_to_register_object($src1$$reg);
2679 Register Rsrc2 = reg_to_register_object($src2$$reg);
2680 Register Rdst = reg_to_register_object($dst$$reg);
2681
2682 __ sra( Rsrc1, 0, Rsrc1 );
2683 __ sra( Rsrc2, 0, Rsrc2 );
2684 __ mulx( Rsrc1, Rsrc2, Rdst );
2685 __ srlx( Rdst, 32, Rdst );
2686 %}
2687
2688 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2689 MacroAssembler _masm(&cbuf);
2690 Register Rdividend = reg_to_register_object($src1$$reg);
2691 Register Rdivisor = reg_to_register_object($src2$$reg);
2692 Register Rresult = reg_to_register_object($dst$$reg);
2693 Register Rscratch = reg_to_register_object($scratch$$reg);
2694
2695 assert(Rdividend != Rscratch, "");
2696 assert(Rdivisor != Rscratch, "");
2697
2698 __ sra(Rdividend, 0, Rdividend);
2699 __ sra(Rdivisor, 0, Rdivisor);
2700 __ sdivx(Rdividend, Rdivisor, Rscratch);
2701 __ mulx(Rscratch, Rdivisor, Rscratch);
2702 __ sub(Rdividend, Rscratch, Rresult);
2703 %}
2704
2705 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2706 MacroAssembler _masm(&cbuf);
2707
2708 Register Rdividend = reg_to_register_object($src1$$reg);
2709 int divisor = $imm$$constant;
2710 Register Rresult = reg_to_register_object($dst$$reg);
2711 Register Rscratch = reg_to_register_object($scratch$$reg);
2712
2713 assert(Rdividend != Rscratch, "");
2714
2715 __ sra(Rdividend, 0, Rdividend);
2716 __ sdivx(Rdividend, divisor, Rscratch);
2717 __ mulx(Rscratch, divisor, Rscratch);
2718 __ sub(Rdividend, Rscratch, Rresult);
2719 %}
2720
2721 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2722 MacroAssembler _masm(&cbuf);
2723
2724 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2725 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2726
2727 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2728 %}
2729
2730 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2731 MacroAssembler _masm(&cbuf);
2732
2733 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2734 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2735
2736 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2737 %}
2738
2739 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2740 MacroAssembler _masm(&cbuf);
2741
2742 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2743 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2744
2745 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2746 %}
2747
2748 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2749 MacroAssembler _masm(&cbuf);
2750
2751 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2752 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2753
2754 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2755 %}
2756
2757 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2758 MacroAssembler _masm(&cbuf);
2759
2760 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2761 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2762
2763 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2764 %}
2765
2766 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2767 MacroAssembler _masm(&cbuf);
2768
2769 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2770 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2771
2772 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2773 %}
2774
2775 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2776 MacroAssembler _masm(&cbuf);
2777
2778 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2779 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2780
2781 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2782 %}
2783
2784 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2785 MacroAssembler _masm(&cbuf);
2786
2787 Register Roop = reg_to_register_object($oop$$reg);
2788 Register Rbox = reg_to_register_object($box$$reg);
2789 Register Rscratch = reg_to_register_object($scratch$$reg);
2790 Register Rmark = reg_to_register_object($scratch2$$reg);
2791
2792 assert(Roop != Rscratch, "");
2793 assert(Roop != Rmark, "");
2794 assert(Rbox != Rscratch, "");
2795 assert(Rbox != Rmark, "");
2796
2797 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2798 %}
2799
2800 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2801 MacroAssembler _masm(&cbuf);
2802
2803 Register Roop = reg_to_register_object($oop$$reg);
2804 Register Rbox = reg_to_register_object($box$$reg);
2805 Register Rscratch = reg_to_register_object($scratch$$reg);
2806 Register Rmark = reg_to_register_object($scratch2$$reg);
2807
2808 assert(Roop != Rscratch, "");
2809 assert(Roop != Rmark, "");
2810 assert(Rbox != Rscratch, "");
2811 assert(Rbox != Rmark, "");
2812
2813 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2814 %}
2815
2816 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2817 MacroAssembler _masm(&cbuf);
2818 Register Rmem = reg_to_register_object($mem$$reg);
2819 Register Rold = reg_to_register_object($old$$reg);
2820 Register Rnew = reg_to_register_object($new$$reg);
2821
2822 // casx_under_lock picks 1 of 3 encodings:
2823 // For 32-bit pointers you get a 32-bit CAS
2824 // For 64-bit pointers you get a 64-bit CASX
2825 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2826 __ cmp( Rold, Rnew );
2827 %}
2828
2829 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2830 Register Rmem = reg_to_register_object($mem$$reg);
2831 Register Rold = reg_to_register_object($old$$reg);
2832 Register Rnew = reg_to_register_object($new$$reg);
2833
2834 MacroAssembler _masm(&cbuf);
2835 __ mov(Rnew, O7);
2836 __ casx(Rmem, Rold, O7);
2837 __ cmp( Rold, O7 );
2838 %}
2839
2840 // raw int cas, used for compareAndSwap
2841 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2842 Register Rmem = reg_to_register_object($mem$$reg);
2843 Register Rold = reg_to_register_object($old$$reg);
2844 Register Rnew = reg_to_register_object($new$$reg);
2845
2846 MacroAssembler _masm(&cbuf);
2847 __ mov(Rnew, O7);
2848 __ cas(Rmem, Rold, O7);
2849 __ cmp( Rold, O7 );
2850 %}
2851
2852 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2853 Register Rres = reg_to_register_object($res$$reg);
2854
2855 MacroAssembler _masm(&cbuf);
2856 __ mov(1, Rres);
2857 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2858 %}
2859
2860 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2861 Register Rres = reg_to_register_object($res$$reg);
2862
2863 MacroAssembler _masm(&cbuf);
2864 __ mov(1, Rres);
2865 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2866 %}
2867
2868 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2869 MacroAssembler _masm(&cbuf);
2870 Register Rdst = reg_to_register_object($dst$$reg);
2871 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2872 : reg_to_DoubleFloatRegister_object($src1$$reg);
2873 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2874 : reg_to_DoubleFloatRegister_object($src2$$reg);
2875
2876 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2877 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2878 %}
2879
2880
2881 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2882 Label Ldone, Lloop;
2883 MacroAssembler _masm(&cbuf);
2884
2885 Register str1_reg = reg_to_register_object($str1$$reg);
2886 Register str2_reg = reg_to_register_object($str2$$reg);
2887 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2888 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2889 Register result_reg = reg_to_register_object($result$$reg);
2890
2891 assert(result_reg != str1_reg &&
2892 result_reg != str2_reg &&
2893 result_reg != cnt1_reg &&
2894 result_reg != cnt2_reg ,
2895 "need different registers");
2896
2897 // Compute the minimum of the string lengths(str1_reg) and the
2898 // difference of the string lengths (stack)
2899
2900 // See if the lengths are different, and calculate min in str1_reg.
2901 // Stash diff in O7 in case we need it for a tie-breaker.
2902 Label Lskip;
2903 __ subcc(cnt1_reg, cnt2_reg, O7);
2904 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2905 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2906 // cnt2 is shorter, so use its count:
2907 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2908 __ bind(Lskip);
2909
2910 // reallocate cnt1_reg, cnt2_reg, result_reg
2911 // Note: limit_reg holds the string length pre-scaled by 2
2912 Register limit_reg = cnt1_reg;
2913 Register chr2_reg = cnt2_reg;
2914 Register chr1_reg = result_reg;
2915 // str{12} are the base pointers
2916
2917 // Is the minimum length zero?
2918 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2919 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2920 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2921
2922 // Load first characters
2923 __ lduh(str1_reg, 0, chr1_reg);
2924 __ lduh(str2_reg, 0, chr2_reg);
2925
2926 // Compare first characters
2927 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2928 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2929 assert(chr1_reg == result_reg, "result must be pre-placed");
2930 __ delayed()->nop();
2931
2932 {
2933 // Check after comparing first character to see if strings are equivalent
2934 Label LSkip2;
2935 // Check if the strings start at same location
2936 __ cmp(str1_reg, str2_reg);
2937 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2938 __ delayed()->nop();
2939
2940 // Check if the length difference is zero (in O7)
2941 __ cmp(G0, O7);
2942 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2943 __ delayed()->mov(G0, result_reg); // result is zero
2944
2945 // Strings might not be equal
2946 __ bind(LSkip2);
2947 }
2948
2949 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2950 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2951 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2952
2953 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2954 __ add(str1_reg, limit_reg, str1_reg);
2955 __ add(str2_reg, limit_reg, str2_reg);
2956 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2957
2958 // Compare the rest of the characters
2959 __ lduh(str1_reg, limit_reg, chr1_reg);
2960 __ bind(Lloop);
2961 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2962 __ lduh(str2_reg, limit_reg, chr2_reg);
2963 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2964 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2965 assert(chr1_reg == result_reg, "result must be pre-placed");
2966 __ delayed()->inccc(limit_reg, sizeof(jchar));
2967 // annul LDUH if branch is not taken to prevent access past end of string
2968 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2969 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2970
2971 // If strings are equal up to min length, return the length difference.
2972 __ mov(O7, result_reg);
2973
2974 // Otherwise, return the difference between the first mismatched chars.
2975 __ bind(Ldone);
2976 %}
2977
2978 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2979 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2980 MacroAssembler _masm(&cbuf);
2981
2982 Register str1_reg = reg_to_register_object($str1$$reg);
2983 Register str2_reg = reg_to_register_object($str2$$reg);
2984 Register cnt_reg = reg_to_register_object($cnt$$reg);
2985 Register tmp1_reg = O7;
2986 Register result_reg = reg_to_register_object($result$$reg);
2987
2988 assert(result_reg != str1_reg &&
2989 result_reg != str2_reg &&
2990 result_reg != cnt_reg &&
2991 result_reg != tmp1_reg ,
2992 "need different registers");
2993
2994 __ cmp(str1_reg, str2_reg); //same char[] ?
2995 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2996 __ delayed()->add(G0, 1, result_reg);
2997
2998 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2999 __ delayed()->add(G0, 1, result_reg); // count == 0
3000
3001 //rename registers
3002 Register limit_reg = cnt_reg;
3003 Register chr1_reg = result_reg;
3004 Register chr2_reg = tmp1_reg;
3005
3006 //check for alignment and position the pointers to the ends
3007 __ or3(str1_reg, str2_reg, chr1_reg);
3008 __ andcc(chr1_reg, 0x3, chr1_reg);
3009 // notZero means at least one not 4-byte aligned.
3010 // We could optimize the case when both arrays are not aligned
3011 // but it is not frequent case and it requires additional checks.
3012 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3013 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3014
3015 // Compare char[] arrays aligned to 4 bytes.
3016 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3017 chr1_reg, chr2_reg, Ldone);
3018 __ ba(Ldone);
3019 __ delayed()->add(G0, 1, result_reg);
3020
3021 // char by char compare
3022 __ bind(Lchar);
3023 __ add(str1_reg, limit_reg, str1_reg);
3024 __ add(str2_reg, limit_reg, str2_reg);
3025 __ neg(limit_reg); //negate count
3026
3027 __ lduh(str1_reg, limit_reg, chr1_reg);
3028 // Lchar_loop
3029 __ bind(Lchar_loop);
3030 __ lduh(str2_reg, limit_reg, chr2_reg);
3031 __ cmp(chr1_reg, chr2_reg);
3032 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3033 __ delayed()->mov(G0, result_reg); //not equal
3034 __ inccc(limit_reg, sizeof(jchar));
3035 // annul LDUH if branch is not taken to prevent access past end of string
3036 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3037 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3038
3039 __ add(G0, 1, result_reg); //equal
3040
3041 __ bind(Ldone);
3042 %}
3043
3044 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3045 Label Lvector, Ldone, Lloop;
3046 MacroAssembler _masm(&cbuf);
3047
3048 Register ary1_reg = reg_to_register_object($ary1$$reg);
3049 Register ary2_reg = reg_to_register_object($ary2$$reg);
3050 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3051 Register tmp2_reg = O7;
3052 Register result_reg = reg_to_register_object($result$$reg);
3053
3054 int length_offset = arrayOopDesc::length_offset_in_bytes();
3055 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3056
3057 // return true if the same array
3058 __ cmp(ary1_reg, ary2_reg);
3059 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3060 __ delayed()->add(G0, 1, result_reg); // equal
3061
3062 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3063 __ delayed()->mov(G0, result_reg); // not equal
3064
3065 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3066 __ delayed()->mov(G0, result_reg); // not equal
3067
3068 //load the lengths of arrays
3069 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3070 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3071
3072 // return false if the two arrays are not equal length
3073 __ cmp(tmp1_reg, tmp2_reg);
3074 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3075 __ delayed()->mov(G0, result_reg); // not equal
3076
3077 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3078 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3079
3080 // load array addresses
3081 __ add(ary1_reg, base_offset, ary1_reg);
3082 __ add(ary2_reg, base_offset, ary2_reg);
3083
3084 // renaming registers
3085 Register chr1_reg = result_reg; // for characters in ary1
3086 Register chr2_reg = tmp2_reg; // for characters in ary2
3087 Register limit_reg = tmp1_reg; // length
3088
3089 // set byte count
3090 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3091
3092 // Compare char[] arrays aligned to 4 bytes.
3093 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3094 chr1_reg, chr2_reg, Ldone);
3095 __ add(G0, 1, result_reg); // equals
3096
3097 __ bind(Ldone);
3098 %}
3099
3100 enc_class enc_rethrow() %{
3101 cbuf.set_insts_mark();
3102 Register temp_reg = G3;
3103 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3104 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3105 MacroAssembler _masm(&cbuf);
3106 #ifdef ASSERT
3107 __ save_frame(0);
3108 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3109 __ sethi(last_rethrow_addrlit, L1);
3110 Address addr(L1, last_rethrow_addrlit.low10());
3111 __ get_pc(L2);
3112 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3113 __ st_ptr(L2, addr);
3114 __ restore();
3115 #endif
3116 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3117 __ delayed()->nop();
3118 %}
3119
3120 enc_class emit_mem_nop() %{
3121 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3122 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3123 %}
3124
3125 enc_class emit_fadd_nop() %{
3126 // Generates the instruction FMOVS f31,f31
3127 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3128 %}
3129
3130 enc_class emit_br_nop() %{
3131 // Generates the instruction BPN,PN .
3132 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3133 %}
3134
3135 enc_class enc_membar_acquire %{
3136 MacroAssembler _masm(&cbuf);
3137 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3138 %}
3139
3140 enc_class enc_membar_release %{
3141 MacroAssembler _masm(&cbuf);
3142 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3143 %}
3144
3145 enc_class enc_membar_volatile %{
3146 MacroAssembler _masm(&cbuf);
3147 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3148 %}
3149
3150 %}
3151
3152 //----------FRAME--------------------------------------------------------------
3153 // Definition of frame structure and management information.
3154 //
3155 // S T A C K L A Y O U T Allocators stack-slot number
3156 // | (to get allocators register number
3157 // G Owned by | | v add VMRegImpl::stack0)
3158 // r CALLER | |
3159 // o | +--------+ pad to even-align allocators stack-slot
3160 // w V | pad0 | numbers; owned by CALLER
3161 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3162 // h ^ | in | 5
3163 // | | args | 4 Holes in incoming args owned by SELF
3164 // | | | | 3
3165 // | | +--------+
3166 // V | | old out| Empty on Intel, window on Sparc
3167 // | old |preserve| Must be even aligned.
3168 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3169 // | | in | 3 area for Intel ret address
3170 // Owned by |preserve| Empty on Sparc.
3171 // SELF +--------+
3172 // | | pad2 | 2 pad to align old SP
3173 // | +--------+ 1
3174 // | | locks | 0
3175 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3176 // | | pad1 | 11 pad to align new SP
3177 // | +--------+
3178 // | | | 10
3179 // | | spills | 9 spills
3180 // V | | 8 (pad0 slot for callee)
3181 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3182 // ^ | out | 7
3183 // | | args | 6 Holes in outgoing args owned by CALLEE
3184 // Owned by +--------+
3185 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3186 // | new |preserve| Must be even-aligned.
3187 // | SP-+--------+----> Matcher::_new_SP, even aligned
3188 // | | |
3189 //
3190 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3191 // known from SELF's arguments and the Java calling convention.
3192 // Region 6-7 is determined per call site.
3193 // Note 2: If the calling convention leaves holes in the incoming argument
3194 // area, those holes are owned by SELF. Holes in the outgoing area
3195 // are owned by the CALLEE. Holes should not be nessecary in the
3196 // incoming area, as the Java calling convention is completely under
3197 // the control of the AD file. Doubles can be sorted and packed to
3198 // avoid holes. Holes in the outgoing arguments may be nessecary for
3199 // varargs C calling conventions.
3200 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3201 // even aligned with pad0 as needed.
3202 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3203 // region 6-11 is even aligned; it may be padded out more so that
3204 // the region from SP to FP meets the minimum stack alignment.
3205
3206 frame %{
3207 // What direction does stack grow in (assumed to be same for native & Java)
3208 stack_direction(TOWARDS_LOW);
3209
3210 // These two registers define part of the calling convention
3211 // between compiled code and the interpreter.
3212 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3213 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3214
3215 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3216 cisc_spilling_operand_name(indOffset);
3217
3218 // Number of stack slots consumed by a Monitor enter
3219 #ifdef _LP64
3220 sync_stack_slots(2);
3221 #else
3222 sync_stack_slots(1);
3223 #endif
3224
3225 // Compiled code's Frame Pointer
3226 frame_pointer(R_SP);
3227
3228 // Stack alignment requirement
3229 stack_alignment(StackAlignmentInBytes);
3230 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3231 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3232
3233 // Number of stack slots between incoming argument block and the start of
3234 // a new frame. The PROLOG must add this many slots to the stack. The
3235 // EPILOG must remove this many slots.
3236 in_preserve_stack_slots(0);
3237
3238 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3239 // for calls to C. Supports the var-args backing area for register parms.
3240 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3241 #ifdef _LP64
3242 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3243 varargs_C_out_slots_killed(12);
3244 #else
3245 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3246 varargs_C_out_slots_killed( 7);
3247 #endif
3248
3249 // The after-PROLOG location of the return address. Location of
3250 // return address specifies a type (REG or STACK) and a number
3251 // representing the register number (i.e. - use a register name) or
3252 // stack slot.
3253 return_addr(REG R_I7); // Ret Addr is in register I7
3254
3255 // Body of function which returns an OptoRegs array locating
3256 // arguments either in registers or in stack slots for calling
3257 // java
3258 calling_convention %{
3259 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3260
3261 %}
3262
3263 // Body of function which returns an OptoRegs array locating
3264 // arguments either in registers or in stack slots for callin
3265 // C.
3266 c_calling_convention %{
3267 // This is obviously always outgoing
3268 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3269 %}
3270
3271 // Location of native (C/C++) and interpreter return values. This is specified to
3272 // be the same as Java. In the 32-bit VM, long values are actually returned from
3273 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3274 // to and from the register pairs is done by the appropriate call and epilog
3275 // opcodes. This simplifies the register allocator.
3276 c_return_value %{
3277 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3278 #ifdef _LP64
3279 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3280 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3281 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3282 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3283 #else // !_LP64
3284 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3285 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3286 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3287 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3288 #endif
3289 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3290 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3291 %}
3292
3293 // Location of compiled Java return values. Same as C
3294 return_value %{
3295 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3296 #ifdef _LP64
3297 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3298 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3299 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3300 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3301 #else // !_LP64
3302 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3303 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3304 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3305 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3306 #endif
3307 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3308 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3309 %}
3310
3311 %}
3312
3313
3314 //----------ATTRIBUTES---------------------------------------------------------
3315 //----------Operand Attributes-------------------------------------------------
3316 op_attrib op_cost(1); // Required cost attribute
3317
3318 //----------Instruction Attributes---------------------------------------------
3319 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3320 ins_attrib ins_size(32); // Required size attribute (in bits)
3321 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3322 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3323 // non-matching short branch variant of some
3324 // long branch?
3325
3326 //----------OPERANDS-----------------------------------------------------------
3327 // Operand definitions must precede instruction definitions for correct parsing
3328 // in the ADLC because operands constitute user defined types which are used in
3329 // instruction definitions.
3330
3331 //----------Simple Operands----------------------------------------------------
3332 // Immediate Operands
3333 // Integer Immediate: 32-bit
3334 operand immI() %{
3335 match(ConI);
3336
3337 op_cost(0);
3338 // formats are generated automatically for constants and base registers
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3342
3343 // Integer Immediate: 8-bit
3344 operand immI8() %{
3345 predicate(Assembler::is_simm8(n->get_int()));
3346 match(ConI);
3347 op_cost(0);
3348 format %{ %}
3349 interface(CONST_INTER);
3350 %}
3351
3352 // Integer Immediate: 13-bit
3353 operand immI13() %{
3354 predicate(Assembler::is_simm13(n->get_int()));
3355 match(ConI);
3356 op_cost(0);
3357
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3361
3362 // Integer Immediate: 13-bit minus 7
3363 operand immI13m7() %{
3364 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3365 match(ConI);
3366 op_cost(0);
3367
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Integer Immediate: 16-bit
3373 operand immI16() %{
3374 predicate(Assembler::is_simm16(n->get_int()));
3375 match(ConI);
3376 op_cost(0);
3377 format %{ %}
3378 interface(CONST_INTER);
3379 %}
3380
3381 // Unsigned (positive) Integer Immediate: 13-bit
3382 operand immU13() %{
3383 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3384 match(ConI);
3385 op_cost(0);
3386
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3390
3391 // Integer Immediate: 6-bit
3392 operand immU6() %{
3393 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3394 match(ConI);
3395 op_cost(0);
3396 format %{ %}
3397 interface(CONST_INTER);
3398 %}
3399
3400 // Integer Immediate: 11-bit
3401 operand immI11() %{
3402 predicate(Assembler::is_simm11(n->get_int()));
3403 match(ConI);
3404 op_cost(0);
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Integer Immediate: 5-bit
3410 operand immI5() %{
3411 predicate(Assembler::is_simm5(n->get_int()));
3412 match(ConI);
3413 op_cost(0);
3414 format %{ %}
3415 interface(CONST_INTER);
3416 %}
3417
3418 // Integer Immediate: 0-bit
3419 operand immI0() %{
3420 predicate(n->get_int() == 0);
3421 match(ConI);
3422 op_cost(0);
3423
3424 format %{ %}
3425 interface(CONST_INTER);
3426 %}
3427
3428 // Integer Immediate: the value 10
3429 operand immI10() %{
3430 predicate(n->get_int() == 10);
3431 match(ConI);
3432 op_cost(0);
3433
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 // Integer Immediate: the values 0-31
3439 operand immU5() %{
3440 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3441 match(ConI);
3442 op_cost(0);
3443
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Integer Immediate: the values 1-31
3449 operand immI_1_31() %{
3450 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3451 match(ConI);
3452 op_cost(0);
3453
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Integer Immediate: the values 32-63
3459 operand immI_32_63() %{
3460 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3461 match(ConI);
3462 op_cost(0);
3463
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 // Immediates for special shifts (sign extend)
3469
3470 // Integer Immediate: the value 16
3471 operand immI_16() %{
3472 predicate(n->get_int() == 16);
3473 match(ConI);
3474 op_cost(0);
3475
3476 format %{ %}
3477 interface(CONST_INTER);
3478 %}
3479
3480 // Integer Immediate: the value 24
3481 operand immI_24() %{
3482 predicate(n->get_int() == 24);
3483 match(ConI);
3484 op_cost(0);
3485
3486 format %{ %}
3487 interface(CONST_INTER);
3488 %}
3489
3490 // Integer Immediate: the value 255
3491 operand immI_255() %{
3492 predicate( n->get_int() == 255 );
3493 match(ConI);
3494 op_cost(0);
3495
3496 format %{ %}
3497 interface(CONST_INTER);
3498 %}
3499
3500 // Integer Immediate: the value 65535
3501 operand immI_65535() %{
3502 predicate(n->get_int() == 65535);
3503 match(ConI);
3504 op_cost(0);
3505
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3509
3510 // Long Immediate: the value FF
3511 operand immL_FF() %{
3512 predicate( n->get_long() == 0xFFL );
3513 match(ConL);
3514 op_cost(0);
3515
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 // Long Immediate: the value FFFF
3521 operand immL_FFFF() %{
3522 predicate( n->get_long() == 0xFFFFL );
3523 match(ConL);
3524 op_cost(0);
3525
3526 format %{ %}
3527 interface(CONST_INTER);
3528 %}
3529
3530 // Pointer Immediate: 32 or 64-bit
3531 operand immP() %{
3532 match(ConP);
3533
3534 op_cost(5);
3535 // formats are generated automatically for constants and base registers
3536 format %{ %}
3537 interface(CONST_INTER);
3538 %}
3539
3540 #ifdef _LP64
3541 // Pointer Immediate: 64-bit
3542 operand immP_set() %{
3543 predicate(!VM_Version::is_niagara_plus());
3544 match(ConP);
3545
3546 op_cost(5);
3547 // formats are generated automatically for constants and base registers
3548 format %{ %}
3549 interface(CONST_INTER);
3550 %}
3551
3552 // Pointer Immediate: 64-bit
3553 // From Niagara2 processors on a load should be better than materializing.
3554 operand immP_load() %{
3555 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3556 match(ConP);
3557
3558 op_cost(5);
3559 // formats are generated automatically for constants and base registers
3560 format %{ %}
3561 interface(CONST_INTER);
3562 %}
3563
3564 // Pointer Immediate: 64-bit
3565 operand immP_no_oop_cheap() %{
3566 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3567 match(ConP);
3568
3569 op_cost(5);
3570 // formats are generated automatically for constants and base registers
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574 #endif
3575
3576 operand immP13() %{
3577 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3578 match(ConP);
3579 op_cost(0);
3580
3581 format %{ %}
3582 interface(CONST_INTER);
3583 %}
3584
3585 operand immP0() %{
3586 predicate(n->get_ptr() == 0);
3587 match(ConP);
3588 op_cost(0);
3589
3590 format %{ %}
3591 interface(CONST_INTER);
3592 %}
3593
3594 operand immP_poll() %{
3595 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3596 match(ConP);
3597
3598 // formats are generated automatically for constants and base registers
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 // Pointer Immediate
3604 operand immN()
3605 %{
3606 match(ConN);
3607
3608 op_cost(10);
3609 format %{ %}
3610 interface(CONST_INTER);
3611 %}
3612
3613 // NULL Pointer Immediate
3614 operand immN0()
3615 %{
3616 predicate(n->get_narrowcon() == 0);
3617 match(ConN);
3618
3619 op_cost(0);
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3623
3624 operand immL() %{
3625 match(ConL);
3626 op_cost(40);
3627 // formats are generated automatically for constants and base registers
3628 format %{ %}
3629 interface(CONST_INTER);
3630 %}
3631
3632 operand immL0() %{
3633 predicate(n->get_long() == 0L);
3634 match(ConL);
3635 op_cost(0);
3636 // formats are generated automatically for constants and base registers
3637 format %{ %}
3638 interface(CONST_INTER);
3639 %}
3640
3641 // Integer Immediate: 5-bit
3642 operand immL5() %{
3643 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3644 match(ConL);
3645 op_cost(0);
3646 format %{ %}
3647 interface(CONST_INTER);
3648 %}
3649
3650 // Long Immediate: 13-bit
3651 operand immL13() %{
3652 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3653 match(ConL);
3654 op_cost(0);
3655
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Long Immediate: 13-bit minus 7
3661 operand immL13m7() %{
3662 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3663 match(ConL);
3664 op_cost(0);
3665
3666 format %{ %}
3667 interface(CONST_INTER);
3668 %}
3669
3670 // Long Immediate: low 32-bit mask
3671 operand immL_32bits() %{
3672 predicate(n->get_long() == 0xFFFFFFFFL);
3673 match(ConL);
3674 op_cost(0);
3675
3676 format %{ %}
3677 interface(CONST_INTER);
3678 %}
3679
3680 // Long Immediate: cheap (materialize in <= 3 instructions)
3681 operand immL_cheap() %{
3682 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3683 match(ConL);
3684 op_cost(0);
3685
3686 format %{ %}
3687 interface(CONST_INTER);
3688 %}
3689
3690 // Long Immediate: expensive (materialize in > 3 instructions)
3691 operand immL_expensive() %{
3692 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3693 match(ConL);
3694 op_cost(0);
3695
3696 format %{ %}
3697 interface(CONST_INTER);
3698 %}
3699
3700 // Double Immediate
3701 operand immD() %{
3702 match(ConD);
3703
3704 op_cost(40);
3705 format %{ %}
3706 interface(CONST_INTER);
3707 %}
3708
3709 operand immD0() %{
3710 #ifdef _LP64
3711 // on 64-bit architectures this comparision is faster
3712 predicate(jlong_cast(n->getd()) == 0);
3713 #else
3714 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3715 #endif
3716 match(ConD);
3717
3718 op_cost(0);
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 // Float Immediate
3724 operand immF() %{
3725 match(ConF);
3726
3727 op_cost(20);
3728 format %{ %}
3729 interface(CONST_INTER);
3730 %}
3731
3732 // Float Immediate: 0
3733 operand immF0() %{
3734 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3735 match(ConF);
3736
3737 op_cost(0);
3738 format %{ %}
3739 interface(CONST_INTER);
3740 %}
3741
3742 // Integer Register Operands
3743 // Integer Register
3744 operand iRegI() %{
3745 constraint(ALLOC_IN_RC(int_reg));
3746 match(RegI);
3747
3748 match(notemp_iRegI);
3749 match(g1RegI);
3750 match(o0RegI);
3751 match(iRegIsafe);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 operand notemp_iRegI() %{
3758 constraint(ALLOC_IN_RC(notemp_int_reg));
3759 match(RegI);
3760
3761 match(o0RegI);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 operand o0RegI() %{
3768 constraint(ALLOC_IN_RC(o0_regI));
3769 match(iRegI);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 // Pointer Register
3776 operand iRegP() %{
3777 constraint(ALLOC_IN_RC(ptr_reg));
3778 match(RegP);
3779
3780 match(lock_ptr_RegP);
3781 match(g1RegP);
3782 match(g2RegP);
3783 match(g3RegP);
3784 match(g4RegP);
3785 match(i0RegP);
3786 match(o0RegP);
3787 match(o1RegP);
3788 match(l7RegP);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand sp_ptr_RegP() %{
3795 constraint(ALLOC_IN_RC(sp_ptr_reg));
3796 match(RegP);
3797 match(iRegP);
3798
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 operand lock_ptr_RegP() %{
3804 constraint(ALLOC_IN_RC(lock_ptr_reg));
3805 match(RegP);
3806 match(i0RegP);
3807 match(o0RegP);
3808 match(o1RegP);
3809 match(l7RegP);
3810
3811 format %{ %}
3812 interface(REG_INTER);
3813 %}
3814
3815 operand g1RegP() %{
3816 constraint(ALLOC_IN_RC(g1_regP));
3817 match(iRegP);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand g2RegP() %{
3824 constraint(ALLOC_IN_RC(g2_regP));
3825 match(iRegP);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand g3RegP() %{
3832 constraint(ALLOC_IN_RC(g3_regP));
3833 match(iRegP);
3834
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand g1RegI() %{
3840 constraint(ALLOC_IN_RC(g1_regI));
3841 match(iRegI);
3842
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand g3RegI() %{
3848 constraint(ALLOC_IN_RC(g3_regI));
3849 match(iRegI);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand g4RegI() %{
3856 constraint(ALLOC_IN_RC(g4_regI));
3857 match(iRegI);
3858
3859 format %{ %}
3860 interface(REG_INTER);
3861 %}
3862
3863 operand g4RegP() %{
3864 constraint(ALLOC_IN_RC(g4_regP));
3865 match(iRegP);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand i0RegP() %{
3872 constraint(ALLOC_IN_RC(i0_regP));
3873 match(iRegP);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand o0RegP() %{
3880 constraint(ALLOC_IN_RC(o0_regP));
3881 match(iRegP);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand o1RegP() %{
3888 constraint(ALLOC_IN_RC(o1_regP));
3889 match(iRegP);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 operand o2RegP() %{
3896 constraint(ALLOC_IN_RC(o2_regP));
3897 match(iRegP);
3898
3899 format %{ %}
3900 interface(REG_INTER);
3901 %}
3902
3903 operand o7RegP() %{
3904 constraint(ALLOC_IN_RC(o7_regP));
3905 match(iRegP);
3906
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3910
3911 operand l7RegP() %{
3912 constraint(ALLOC_IN_RC(l7_regP));
3913 match(iRegP);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand o7RegI() %{
3920 constraint(ALLOC_IN_RC(o7_regI));
3921 match(iRegI);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 operand iRegN() %{
3928 constraint(ALLOC_IN_RC(int_reg));
3929 match(RegN);
3930
3931 format %{ %}
3932 interface(REG_INTER);
3933 %}
3934
3935 // Long Register
3936 operand iRegL() %{
3937 constraint(ALLOC_IN_RC(long_reg));
3938 match(RegL);
3939
3940 format %{ %}
3941 interface(REG_INTER);
3942 %}
3943
3944 operand o2RegL() %{
3945 constraint(ALLOC_IN_RC(o2_regL));
3946 match(iRegL);
3947
3948 format %{ %}
3949 interface(REG_INTER);
3950 %}
3951
3952 operand o7RegL() %{
3953 constraint(ALLOC_IN_RC(o7_regL));
3954 match(iRegL);
3955
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960 operand g1RegL() %{
3961 constraint(ALLOC_IN_RC(g1_regL));
3962 match(iRegL);
3963
3964 format %{ %}
3965 interface(REG_INTER);
3966 %}
3967
3968 operand g3RegL() %{
3969 constraint(ALLOC_IN_RC(g3_regL));
3970 match(iRegL);
3971
3972 format %{ %}
3973 interface(REG_INTER);
3974 %}
3975
3976 // Int Register safe
3977 // This is 64bit safe
3978 operand iRegIsafe() %{
3979 constraint(ALLOC_IN_RC(long_reg));
3980
3981 match(iRegI);
3982
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3986
3987 // Condition Code Flag Register
3988 operand flagsReg() %{
3989 constraint(ALLOC_IN_RC(int_flags));
3990 match(RegFlags);
3991
3992 format %{ "ccr" %} // both ICC and XCC
3993 interface(REG_INTER);
3994 %}
3995
3996 // Condition Code Register, unsigned comparisons.
3997 operand flagsRegU() %{
3998 constraint(ALLOC_IN_RC(int_flags));
3999 match(RegFlags);
4000
4001 format %{ "icc_U" %}
4002 interface(REG_INTER);
4003 %}
4004
4005 // Condition Code Register, pointer comparisons.
4006 operand flagsRegP() %{
4007 constraint(ALLOC_IN_RC(int_flags));
4008 match(RegFlags);
4009
4010 #ifdef _LP64
4011 format %{ "xcc_P" %}
4012 #else
4013 format %{ "icc_P" %}
4014 #endif
4015 interface(REG_INTER);
4016 %}
4017
4018 // Condition Code Register, long comparisons.
4019 operand flagsRegL() %{
4020 constraint(ALLOC_IN_RC(int_flags));
4021 match(RegFlags);
4022
4023 format %{ "xcc_L" %}
4024 interface(REG_INTER);
4025 %}
4026
4027 // Condition Code Register, floating comparisons, unordered same as "less".
4028 operand flagsRegF() %{
4029 constraint(ALLOC_IN_RC(float_flags));
4030 match(RegFlags);
4031 match(flagsRegF0);
4032
4033 format %{ %}
4034 interface(REG_INTER);
4035 %}
4036
4037 operand flagsRegF0() %{
4038 constraint(ALLOC_IN_RC(float_flag0));
4039 match(RegFlags);
4040
4041 format %{ %}
4042 interface(REG_INTER);
4043 %}
4044
4045
4046 // Condition Code Flag Register used by long compare
4047 operand flagsReg_long_LTGE() %{
4048 constraint(ALLOC_IN_RC(int_flags));
4049 match(RegFlags);
4050 format %{ "icc_LTGE" %}
4051 interface(REG_INTER);
4052 %}
4053 operand flagsReg_long_EQNE() %{
4054 constraint(ALLOC_IN_RC(int_flags));
4055 match(RegFlags);
4056 format %{ "icc_EQNE" %}
4057 interface(REG_INTER);
4058 %}
4059 operand flagsReg_long_LEGT() %{
4060 constraint(ALLOC_IN_RC(int_flags));
4061 match(RegFlags);
4062 format %{ "icc_LEGT" %}
4063 interface(REG_INTER);
4064 %}
4065
4066
4067 operand regD() %{
4068 constraint(ALLOC_IN_RC(dflt_reg));
4069 match(RegD);
4070
4071 match(regD_low);
4072
4073 format %{ %}
4074 interface(REG_INTER);
4075 %}
4076
4077 operand regF() %{
4078 constraint(ALLOC_IN_RC(sflt_reg));
4079 match(RegF);
4080
4081 format %{ %}
4082 interface(REG_INTER);
4083 %}
4084
4085 operand regD_low() %{
4086 constraint(ALLOC_IN_RC(dflt_low_reg));
4087 match(regD);
4088
4089 format %{ %}
4090 interface(REG_INTER);
4091 %}
4092
4093 // Special Registers
4094
4095 // Method Register
4096 operand inline_cache_regP(iRegP reg) %{
4097 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4098 match(reg);
4099 format %{ %}
4100 interface(REG_INTER);
4101 %}
4102
4103 operand interpreter_method_oop_regP(iRegP reg) %{
4104 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4105 match(reg);
4106 format %{ %}
4107 interface(REG_INTER);
4108 %}
4109
4110
4111 //----------Complex Operands---------------------------------------------------
4112 // Indirect Memory Reference
4113 operand indirect(sp_ptr_RegP reg) %{
4114 constraint(ALLOC_IN_RC(sp_ptr_reg));
4115 match(reg);
4116
4117 op_cost(100);
4118 format %{ "[$reg]" %}
4119 interface(MEMORY_INTER) %{
4120 base($reg);
4121 index(0x0);
4122 scale(0x0);
4123 disp(0x0);
4124 %}
4125 %}
4126
4127 // Indirect with simm13 Offset
4128 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4129 constraint(ALLOC_IN_RC(sp_ptr_reg));
4130 match(AddP reg offset);
4131
4132 op_cost(100);
4133 format %{ "[$reg + $offset]" %}
4134 interface(MEMORY_INTER) %{
4135 base($reg);
4136 index(0x0);
4137 scale(0x0);
4138 disp($offset);
4139 %}
4140 %}
4141
4142 // Indirect with simm13 Offset minus 7
4143 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4144 constraint(ALLOC_IN_RC(sp_ptr_reg));
4145 match(AddP reg offset);
4146
4147 op_cost(100);
4148 format %{ "[$reg + $offset]" %}
4149 interface(MEMORY_INTER) %{
4150 base($reg);
4151 index(0x0);
4152 scale(0x0);
4153 disp($offset);
4154 %}
4155 %}
4156
4157 // Note: Intel has a swapped version also, like this:
4158 //operand indOffsetX(iRegI reg, immP offset) %{
4159 // constraint(ALLOC_IN_RC(int_reg));
4160 // match(AddP offset reg);
4161 //
4162 // op_cost(100);
4163 // format %{ "[$reg + $offset]" %}
4164 // interface(MEMORY_INTER) %{
4165 // base($reg);
4166 // index(0x0);
4167 // scale(0x0);
4168 // disp($offset);
4169 // %}
4170 //%}
4171 //// However, it doesn't make sense for SPARC, since
4172 // we have no particularly good way to embed oops in
4173 // single instructions.
4174
4175 // Indirect with Register Index
4176 operand indIndex(iRegP addr, iRegX index) %{
4177 constraint(ALLOC_IN_RC(ptr_reg));
4178 match(AddP addr index);
4179
4180 op_cost(100);
4181 format %{ "[$addr + $index]" %}
4182 interface(MEMORY_INTER) %{
4183 base($addr);
4184 index($index);
4185 scale(0x0);
4186 disp(0x0);
4187 %}
4188 %}
4189
4190 //----------Special Memory Operands--------------------------------------------
4191 // Stack Slot Operand - This operand is used for loading and storing temporary
4192 // values on the stack where a match requires a value to
4193 // flow through memory.
4194 operand stackSlotI(sRegI reg) %{
4195 constraint(ALLOC_IN_RC(stack_slots));
4196 op_cost(100);
4197 //match(RegI);
4198 format %{ "[$reg]" %}
4199 interface(MEMORY_INTER) %{
4200 base(0xE); // R_SP
4201 index(0x0);
4202 scale(0x0);
4203 disp($reg); // Stack Offset
4204 %}
4205 %}
4206
4207 operand stackSlotP(sRegP reg) %{
4208 constraint(ALLOC_IN_RC(stack_slots));
4209 op_cost(100);
4210 //match(RegP);
4211 format %{ "[$reg]" %}
4212 interface(MEMORY_INTER) %{
4213 base(0xE); // R_SP
4214 index(0x0);
4215 scale(0x0);
4216 disp($reg); // Stack Offset
4217 %}
4218 %}
4219
4220 operand stackSlotF(sRegF reg) %{
4221 constraint(ALLOC_IN_RC(stack_slots));
4222 op_cost(100);
4223 //match(RegF);
4224 format %{ "[$reg]" %}
4225 interface(MEMORY_INTER) %{
4226 base(0xE); // R_SP
4227 index(0x0);
4228 scale(0x0);
4229 disp($reg); // Stack Offset
4230 %}
4231 %}
4232 operand stackSlotD(sRegD reg) %{
4233 constraint(ALLOC_IN_RC(stack_slots));
4234 op_cost(100);
4235 //match(RegD);
4236 format %{ "[$reg]" %}
4237 interface(MEMORY_INTER) %{
4238 base(0xE); // R_SP
4239 index(0x0);
4240 scale(0x0);
4241 disp($reg); // Stack Offset
4242 %}
4243 %}
4244 operand stackSlotL(sRegL reg) %{
4245 constraint(ALLOC_IN_RC(stack_slots));
4246 op_cost(100);
4247 //match(RegL);
4248 format %{ "[$reg]" %}
4249 interface(MEMORY_INTER) %{
4250 base(0xE); // R_SP
4251 index(0x0);
4252 scale(0x0);
4253 disp($reg); // Stack Offset
4254 %}
4255 %}
4256
4257 // Operands for expressing Control Flow
4258 // NOTE: Label is a predefined operand which should not be redefined in
4259 // the AD file. It is generically handled within the ADLC.
4260
4261 //----------Conditional Branch Operands----------------------------------------
4262 // Comparison Op - This is the operation of the comparison, and is limited to
4263 // the following set of codes:
4264 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4265 //
4266 // Other attributes of the comparison, such as unsignedness, are specified
4267 // by the comparison instruction that sets a condition code flags register.
4268 // That result is represented by a flags operand whose subtype is appropriate
4269 // to the unsignedness (etc.) of the comparison.
4270 //
4271 // Later, the instruction which matches both the Comparison Op (a Bool) and
4272 // the flags (produced by the Cmp) specifies the coding of the comparison op
4273 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4274
4275 operand cmpOp() %{
4276 match(Bool);
4277
4278 format %{ "" %}
4279 interface(COND_INTER) %{
4280 equal(0x1);
4281 not_equal(0x9);
4282 less(0x3);
4283 greater_equal(0xB);
4284 less_equal(0x2);
4285 greater(0xA);
4286 %}
4287 %}
4288
4289 // Comparison Op, unsigned
4290 operand cmpOpU() %{
4291 match(Bool);
4292
4293 format %{ "u" %}
4294 interface(COND_INTER) %{
4295 equal(0x1);
4296 not_equal(0x9);
4297 less(0x5);
4298 greater_equal(0xD);
4299 less_equal(0x4);
4300 greater(0xC);
4301 %}
4302 %}
4303
4304 // Comparison Op, pointer (same as unsigned)
4305 operand cmpOpP() %{
4306 match(Bool);
4307
4308 format %{ "p" %}
4309 interface(COND_INTER) %{
4310 equal(0x1);
4311 not_equal(0x9);
4312 less(0x5);
4313 greater_equal(0xD);
4314 less_equal(0x4);
4315 greater(0xC);
4316 %}
4317 %}
4318
4319 // Comparison Op, branch-register encoding
4320 operand cmpOp_reg() %{
4321 match(Bool);
4322
4323 format %{ "" %}
4324 interface(COND_INTER) %{
4325 equal (0x1);
4326 not_equal (0x5);
4327 less (0x3);
4328 greater_equal(0x7);
4329 less_equal (0x2);
4330 greater (0x6);
4331 %}
4332 %}
4333
4334 // Comparison Code, floating, unordered same as less
4335 operand cmpOpF() %{
4336 match(Bool);
4337
4338 format %{ "fl" %}
4339 interface(COND_INTER) %{
4340 equal(0x9);
4341 not_equal(0x1);
4342 less(0x3);
4343 greater_equal(0xB);
4344 less_equal(0xE);
4345 greater(0x6);
4346 %}
4347 %}
4348
4349 // Used by long compare
4350 operand cmpOp_commute() %{
4351 match(Bool);
4352
4353 format %{ "" %}
4354 interface(COND_INTER) %{
4355 equal(0x1);
4356 not_equal(0x9);
4357 less(0xA);
4358 greater_equal(0x2);
4359 less_equal(0xB);
4360 greater(0x3);
4361 %}
4362 %}
4363
4364 //----------OPERAND CLASSES----------------------------------------------------
4365 // Operand Classes are groups of operands that are used to simplify
4366 // instruction definitions by not requiring the AD writer to specify separate
4367 // instructions for every form of operand when the instruction accepts
4368 // multiple operand types with the same basic encoding and format. The classic
4369 // case of this is memory operands.
4370 opclass memory( indirect, indOffset13, indIndex );
4371 opclass indIndexMemory( indIndex );
4372
4373 //----------PIPELINE-----------------------------------------------------------
4374 pipeline %{
4375
4376 //----------ATTRIBUTES---------------------------------------------------------
4377 attributes %{
4378 fixed_size_instructions; // Fixed size instructions
4379 branch_has_delay_slot; // Branch has delay slot following
4380 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4381 instruction_unit_size = 4; // An instruction is 4 bytes long
4382 instruction_fetch_unit_size = 16; // The processor fetches one line
4383 instruction_fetch_units = 1; // of 16 bytes
4384
4385 // List of nop instructions
4386 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4387 %}
4388
4389 //----------RESOURCES----------------------------------------------------------
4390 // Resources are the functional units available to the machine
4391 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4392
4393 //----------PIPELINE DESCRIPTION-----------------------------------------------
4394 // Pipeline Description specifies the stages in the machine's pipeline
4395
4396 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4397
4398 //----------PIPELINE CLASSES---------------------------------------------------
4399 // Pipeline Classes describe the stages in which input and output are
4400 // referenced by the hardware pipeline.
4401
4402 // Integer ALU reg-reg operation
4403 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4404 single_instruction;
4405 dst : E(write);
4406 src1 : R(read);
4407 src2 : R(read);
4408 IALU : R;
4409 %}
4410
4411 // Integer ALU reg-reg long operation
4412 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4413 instruction_count(2);
4414 dst : E(write);
4415 src1 : R(read);
4416 src2 : R(read);
4417 IALU : R;
4418 IALU : R;
4419 %}
4420
4421 // Integer ALU reg-reg long dependent operation
4422 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4423 instruction_count(1); multiple_bundles;
4424 dst : E(write);
4425 src1 : R(read);
4426 src2 : R(read);
4427 cr : E(write);
4428 IALU : R(2);
4429 %}
4430
4431 // Integer ALU reg-imm operaion
4432 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4433 single_instruction;
4434 dst : E(write);
4435 src1 : R(read);
4436 IALU : R;
4437 %}
4438
4439 // Integer ALU reg-reg operation with condition code
4440 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4441 single_instruction;
4442 dst : E(write);
4443 cr : E(write);
4444 src1 : R(read);
4445 src2 : R(read);
4446 IALU : R;
4447 %}
4448
4449 // Integer ALU reg-imm operation with condition code
4450 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4451 single_instruction;
4452 dst : E(write);
4453 cr : E(write);
4454 src1 : R(read);
4455 IALU : R;
4456 %}
4457
4458 // Integer ALU zero-reg operation
4459 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4460 single_instruction;
4461 dst : E(write);
4462 src2 : R(read);
4463 IALU : R;
4464 %}
4465
4466 // Integer ALU zero-reg operation with condition code only
4467 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4468 single_instruction;
4469 cr : E(write);
4470 src : R(read);
4471 IALU : R;
4472 %}
4473
4474 // Integer ALU reg-reg operation with condition code only
4475 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4476 single_instruction;
4477 cr : E(write);
4478 src1 : R(read);
4479 src2 : R(read);
4480 IALU : R;
4481 %}
4482
4483 // Integer ALU reg-imm operation with condition code only
4484 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4485 single_instruction;
4486 cr : E(write);
4487 src1 : R(read);
4488 IALU : R;
4489 %}
4490
4491 // Integer ALU reg-reg-zero operation with condition code only
4492 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4493 single_instruction;
4494 cr : E(write);
4495 src1 : R(read);
4496 src2 : R(read);
4497 IALU : R;
4498 %}
4499
4500 // Integer ALU reg-imm-zero operation with condition code only
4501 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4502 single_instruction;
4503 cr : E(write);
4504 src1 : R(read);
4505 IALU : R;
4506 %}
4507
4508 // Integer ALU reg-reg operation with condition code, src1 modified
4509 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4510 single_instruction;
4511 cr : E(write);
4512 src1 : E(write);
4513 src1 : R(read);
4514 src2 : R(read);
4515 IALU : R;
4516 %}
4517
4518 // Integer ALU reg-imm operation with condition code, src1 modified
4519 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4520 single_instruction;
4521 cr : E(write);
4522 src1 : E(write);
4523 src1 : R(read);
4524 IALU : R;
4525 %}
4526
4527 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4528 multiple_bundles;
4529 dst : E(write)+4;
4530 cr : E(write);
4531 src1 : R(read);
4532 src2 : R(read);
4533 IALU : R(3);
4534 BR : R(2);
4535 %}
4536
4537 // Integer ALU operation
4538 pipe_class ialu_none(iRegI dst) %{
4539 single_instruction;
4540 dst : E(write);
4541 IALU : R;
4542 %}
4543
4544 // Integer ALU reg operation
4545 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4546 single_instruction; may_have_no_code;
4547 dst : E(write);
4548 src : R(read);
4549 IALU : R;
4550 %}
4551
4552 // Integer ALU reg conditional operation
4553 // This instruction has a 1 cycle stall, and cannot execute
4554 // in the same cycle as the instruction setting the condition
4555 // code. We kludge this by pretending to read the condition code
4556 // 1 cycle earlier, and by marking the functional units as busy
4557 // for 2 cycles with the result available 1 cycle later than
4558 // is really the case.
4559 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4560 single_instruction;
4561 op2_out : C(write);
4562 op1 : R(read);
4563 cr : R(read); // This is really E, with a 1 cycle stall
4564 BR : R(2);
4565 MS : R(2);
4566 %}
4567
4568 #ifdef _LP64
4569 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4570 instruction_count(1); multiple_bundles;
4571 dst : C(write)+1;
4572 src : R(read)+1;
4573 IALU : R(1);
4574 BR : E(2);
4575 MS : E(2);
4576 %}
4577 #endif
4578
4579 // Integer ALU reg operation
4580 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4581 single_instruction; may_have_no_code;
4582 dst : E(write);
4583 src : R(read);
4584 IALU : R;
4585 %}
4586 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4587 single_instruction; may_have_no_code;
4588 dst : E(write);
4589 src : R(read);
4590 IALU : R;
4591 %}
4592
4593 // Two integer ALU reg operations
4594 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4595 instruction_count(2);
4596 dst : E(write);
4597 src : R(read);
4598 A0 : R;
4599 A1 : R;
4600 %}
4601
4602 // Two integer ALU reg operations
4603 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4604 instruction_count(2); may_have_no_code;
4605 dst : E(write);
4606 src : R(read);
4607 A0 : R;
4608 A1 : R;
4609 %}
4610
4611 // Integer ALU imm operation
4612 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4613 single_instruction;
4614 dst : E(write);
4615 IALU : R;
4616 %}
4617
4618 // Integer ALU reg-reg with carry operation
4619 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4620 single_instruction;
4621 dst : E(write);
4622 src1 : R(read);
4623 src2 : R(read);
4624 IALU : R;
4625 %}
4626
4627 // Integer ALU cc operation
4628 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4629 single_instruction;
4630 dst : E(write);
4631 cc : R(read);
4632 IALU : R;
4633 %}
4634
4635 // Integer ALU cc / second IALU operation
4636 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4637 instruction_count(1); multiple_bundles;
4638 dst : E(write)+1;
4639 src : R(read);
4640 IALU : R;
4641 %}
4642
4643 // Integer ALU cc / second IALU operation
4644 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4645 instruction_count(1); multiple_bundles;
4646 dst : E(write)+1;
4647 p : R(read);
4648 q : R(read);
4649 IALU : R;
4650 %}
4651
4652 // Integer ALU hi-lo-reg operation
4653 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4654 instruction_count(1); multiple_bundles;
4655 dst : E(write)+1;
4656 IALU : R(2);
4657 %}
4658
4659 // Float ALU hi-lo-reg operation (with temp)
4660 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4661 instruction_count(1); multiple_bundles;
4662 dst : E(write)+1;
4663 IALU : R(2);
4664 %}
4665
4666 // Long Constant
4667 pipe_class loadConL( iRegL dst, immL src ) %{
4668 instruction_count(2); multiple_bundles;
4669 dst : E(write)+1;
4670 IALU : R(2);
4671 IALU : R(2);
4672 %}
4673
4674 // Pointer Constant
4675 pipe_class loadConP( iRegP dst, immP src ) %{
4676 instruction_count(0); multiple_bundles;
4677 fixed_latency(6);
4678 %}
4679
4680 // Polling Address
4681 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4682 #ifdef _LP64
4683 instruction_count(0); multiple_bundles;
4684 fixed_latency(6);
4685 #else
4686 dst : E(write);
4687 IALU : R;
4688 #endif
4689 %}
4690
4691 // Long Constant small
4692 pipe_class loadConLlo( iRegL dst, immL src ) %{
4693 instruction_count(2);
4694 dst : E(write);
4695 IALU : R;
4696 IALU : R;
4697 %}
4698
4699 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4700 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4701 instruction_count(1); multiple_bundles;
4702 src : R(read);
4703 dst : M(write)+1;
4704 IALU : R;
4705 MS : E;
4706 %}
4707
4708 // Integer ALU nop operation
4709 pipe_class ialu_nop() %{
4710 single_instruction;
4711 IALU : R;
4712 %}
4713
4714 // Integer ALU nop operation
4715 pipe_class ialu_nop_A0() %{
4716 single_instruction;
4717 A0 : R;
4718 %}
4719
4720 // Integer ALU nop operation
4721 pipe_class ialu_nop_A1() %{
4722 single_instruction;
4723 A1 : R;
4724 %}
4725
4726 // Integer Multiply reg-reg operation
4727 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4728 single_instruction;
4729 dst : E(write);
4730 src1 : R(read);
4731 src2 : R(read);
4732 MS : R(5);
4733 %}
4734
4735 // Integer Multiply reg-imm operation
4736 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4737 single_instruction;
4738 dst : E(write);
4739 src1 : R(read);
4740 MS : R(5);
4741 %}
4742
4743 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4744 single_instruction;
4745 dst : E(write)+4;
4746 src1 : R(read);
4747 src2 : R(read);
4748 MS : R(6);
4749 %}
4750
4751 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4752 single_instruction;
4753 dst : E(write)+4;
4754 src1 : R(read);
4755 MS : R(6);
4756 %}
4757
4758 // Integer Divide reg-reg
4759 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4760 instruction_count(1); multiple_bundles;
4761 dst : E(write);
4762 temp : E(write);
4763 src1 : R(read);
4764 src2 : R(read);
4765 temp : R(read);
4766 MS : R(38);
4767 %}
4768
4769 // Integer Divide reg-imm
4770 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4771 instruction_count(1); multiple_bundles;
4772 dst : E(write);
4773 temp : E(write);
4774 src1 : R(read);
4775 temp : R(read);
4776 MS : R(38);
4777 %}
4778
4779 // Long Divide
4780 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4781 dst : E(write)+71;
4782 src1 : R(read);
4783 src2 : R(read)+1;
4784 MS : R(70);
4785 %}
4786
4787 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4788 dst : E(write)+71;
4789 src1 : R(read);
4790 MS : R(70);
4791 %}
4792
4793 // Floating Point Add Float
4794 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4795 single_instruction;
4796 dst : X(write);
4797 src1 : E(read);
4798 src2 : E(read);
4799 FA : R;
4800 %}
4801
4802 // Floating Point Add Double
4803 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4804 single_instruction;
4805 dst : X(write);
4806 src1 : E(read);
4807 src2 : E(read);
4808 FA : R;
4809 %}
4810
4811 // Floating Point Conditional Move based on integer flags
4812 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4813 single_instruction;
4814 dst : X(write);
4815 src : E(read);
4816 cr : R(read);
4817 FA : R(2);
4818 BR : R(2);
4819 %}
4820
4821 // Floating Point Conditional Move based on integer flags
4822 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4823 single_instruction;
4824 dst : X(write);
4825 src : E(read);
4826 cr : R(read);
4827 FA : R(2);
4828 BR : R(2);
4829 %}
4830
4831 // Floating Point Multiply Float
4832 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4833 single_instruction;
4834 dst : X(write);
4835 src1 : E(read);
4836 src2 : E(read);
4837 FM : R;
4838 %}
4839
4840 // Floating Point Multiply Double
4841 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4842 single_instruction;
4843 dst : X(write);
4844 src1 : E(read);
4845 src2 : E(read);
4846 FM : R;
4847 %}
4848
4849 // Floating Point Divide Float
4850 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4851 single_instruction;
4852 dst : X(write);
4853 src1 : E(read);
4854 src2 : E(read);
4855 FM : R;
4856 FDIV : C(14);
4857 %}
4858
4859 // Floating Point Divide Double
4860 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4861 single_instruction;
4862 dst : X(write);
4863 src1 : E(read);
4864 src2 : E(read);
4865 FM : R;
4866 FDIV : C(17);
4867 %}
4868
4869 // Floating Point Move/Negate/Abs Float
4870 pipe_class faddF_reg(regF dst, regF src) %{
4871 single_instruction;
4872 dst : W(write);
4873 src : E(read);
4874 FA : R(1);
4875 %}
4876
4877 // Floating Point Move/Negate/Abs Double
4878 pipe_class faddD_reg(regD dst, regD src) %{
4879 single_instruction;
4880 dst : W(write);
4881 src : E(read);
4882 FA : R;
4883 %}
4884
4885 // Floating Point Convert F->D
4886 pipe_class fcvtF2D(regD dst, regF src) %{
4887 single_instruction;
4888 dst : X(write);
4889 src : E(read);
4890 FA : R;
4891 %}
4892
4893 // Floating Point Convert I->D
4894 pipe_class fcvtI2D(regD dst, regF src) %{
4895 single_instruction;
4896 dst : X(write);
4897 src : E(read);
4898 FA : R;
4899 %}
4900
4901 // Floating Point Convert LHi->D
4902 pipe_class fcvtLHi2D(regD dst, regD src) %{
4903 single_instruction;
4904 dst : X(write);
4905 src : E(read);
4906 FA : R;
4907 %}
4908
4909 // Floating Point Convert L->D
4910 pipe_class fcvtL2D(regD dst, regF src) %{
4911 single_instruction;
4912 dst : X(write);
4913 src : E(read);
4914 FA : R;
4915 %}
4916
4917 // Floating Point Convert L->F
4918 pipe_class fcvtL2F(regD dst, regF src) %{
4919 single_instruction;
4920 dst : X(write);
4921 src : E(read);
4922 FA : R;
4923 %}
4924
4925 // Floating Point Convert D->F
4926 pipe_class fcvtD2F(regD dst, regF src) %{
4927 single_instruction;
4928 dst : X(write);
4929 src : E(read);
4930 FA : R;
4931 %}
4932
4933 // Floating Point Convert I->L
4934 pipe_class fcvtI2L(regD dst, regF src) %{
4935 single_instruction;
4936 dst : X(write);
4937 src : E(read);
4938 FA : R;
4939 %}
4940
4941 // Floating Point Convert D->F
4942 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4943 instruction_count(1); multiple_bundles;
4944 dst : X(write)+6;
4945 src : E(read);
4946 FA : R;
4947 %}
4948
4949 // Floating Point Convert D->L
4950 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4951 instruction_count(1); multiple_bundles;
4952 dst : X(write)+6;
4953 src : E(read);
4954 FA : R;
4955 %}
4956
4957 // Floating Point Convert F->I
4958 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4959 instruction_count(1); multiple_bundles;
4960 dst : X(write)+6;
4961 src : E(read);
4962 FA : R;
4963 %}
4964
4965 // Floating Point Convert F->L
4966 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4967 instruction_count(1); multiple_bundles;
4968 dst : X(write)+6;
4969 src : E(read);
4970 FA : R;
4971 %}
4972
4973 // Floating Point Convert I->F
4974 pipe_class fcvtI2F(regF dst, regF src) %{
4975 single_instruction;
4976 dst : X(write);
4977 src : E(read);
4978 FA : R;
4979 %}
4980
4981 // Floating Point Compare
4982 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4983 single_instruction;
4984 cr : X(write);
4985 src1 : E(read);
4986 src2 : E(read);
4987 FA : R;
4988 %}
4989
4990 // Floating Point Compare
4991 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4992 single_instruction;
4993 cr : X(write);
4994 src1 : E(read);
4995 src2 : E(read);
4996 FA : R;
4997 %}
4998
4999 // Floating Add Nop
5000 pipe_class fadd_nop() %{
5001 single_instruction;
5002 FA : R;
5003 %}
5004
5005 // Integer Store to Memory
5006 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5007 single_instruction;
5008 mem : R(read);
5009 src : C(read);
5010 MS : R;
5011 %}
5012
5013 // Integer Store to Memory
5014 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5015 single_instruction;
5016 mem : R(read);
5017 src : C(read);
5018 MS : R;
5019 %}
5020
5021 // Integer Store Zero to Memory
5022 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5023 single_instruction;
5024 mem : R(read);
5025 MS : R;
5026 %}
5027
5028 // Special Stack Slot Store
5029 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5030 single_instruction;
5031 stkSlot : R(read);
5032 src : C(read);
5033 MS : R;
5034 %}
5035
5036 // Special Stack Slot Store
5037 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5038 instruction_count(2); multiple_bundles;
5039 stkSlot : R(read);
5040 src : C(read);
5041 MS : R(2);
5042 %}
5043
5044 // Float Store
5045 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5046 single_instruction;
5047 mem : R(read);
5048 src : C(read);
5049 MS : R;
5050 %}
5051
5052 // Float Store
5053 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5054 single_instruction;
5055 mem : R(read);
5056 MS : R;
5057 %}
5058
5059 // Double Store
5060 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5061 instruction_count(1);
5062 mem : R(read);
5063 src : C(read);
5064 MS : R;
5065 %}
5066
5067 // Double Store
5068 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5069 single_instruction;
5070 mem : R(read);
5071 MS : R;
5072 %}
5073
5074 // Special Stack Slot Float Store
5075 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5076 single_instruction;
5077 stkSlot : R(read);
5078 src : C(read);
5079 MS : R;
5080 %}
5081
5082 // Special Stack Slot Double Store
5083 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5084 single_instruction;
5085 stkSlot : R(read);
5086 src : C(read);
5087 MS : R;
5088 %}
5089
5090 // Integer Load (when sign bit propagation not needed)
5091 pipe_class iload_mem(iRegI dst, memory mem) %{
5092 single_instruction;
5093 mem : R(read);
5094 dst : C(write);
5095 MS : R;
5096 %}
5097
5098 // Integer Load from stack operand
5099 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5100 single_instruction;
5101 mem : R(read);
5102 dst : C(write);
5103 MS : R;
5104 %}
5105
5106 // Integer Load (when sign bit propagation or masking is needed)
5107 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5108 single_instruction;
5109 mem : R(read);
5110 dst : M(write);
5111 MS : R;
5112 %}
5113
5114 // Float Load
5115 pipe_class floadF_mem(regF dst, memory mem) %{
5116 single_instruction;
5117 mem : R(read);
5118 dst : M(write);
5119 MS : R;
5120 %}
5121
5122 // Float Load
5123 pipe_class floadD_mem(regD dst, memory mem) %{
5124 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5125 mem : R(read);
5126 dst : M(write);
5127 MS : R;
5128 %}
5129
5130 // Float Load
5131 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5132 single_instruction;
5133 stkSlot : R(read);
5134 dst : M(write);
5135 MS : R;
5136 %}
5137
5138 // Float Load
5139 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5140 single_instruction;
5141 stkSlot : R(read);
5142 dst : M(write);
5143 MS : R;
5144 %}
5145
5146 // Memory Nop
5147 pipe_class mem_nop() %{
5148 single_instruction;
5149 MS : R;
5150 %}
5151
5152 pipe_class sethi(iRegP dst, immI src) %{
5153 single_instruction;
5154 dst : E(write);
5155 IALU : R;
5156 %}
5157
5158 pipe_class loadPollP(iRegP poll) %{
5159 single_instruction;
5160 poll : R(read);
5161 MS : R;
5162 %}
5163
5164 pipe_class br(Universe br, label labl) %{
5165 single_instruction_with_delay_slot;
5166 BR : R;
5167 %}
5168
5169 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5170 single_instruction_with_delay_slot;
5171 cr : E(read);
5172 BR : R;
5173 %}
5174
5175 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5176 single_instruction_with_delay_slot;
5177 op1 : E(read);
5178 BR : R;
5179 MS : R;
5180 %}
5181
5182 // Compare and branch
5183 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5184 instruction_count(2); has_delay_slot;
5185 cr : E(write);
5186 src1 : R(read);
5187 src2 : R(read);
5188 IALU : R;
5189 BR : R;
5190 %}
5191
5192 // Compare and branch
5193 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5194 instruction_count(2); has_delay_slot;
5195 cr : E(write);
5196 src1 : R(read);
5197 IALU : R;
5198 BR : R;
5199 %}
5200
5201 // Compare and branch using cbcond
5202 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5203 single_instruction;
5204 src1 : E(read);
5205 src2 : E(read);
5206 IALU : R;
5207 BR : R;
5208 %}
5209
5210 // Compare and branch using cbcond
5211 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5212 single_instruction;
5213 src1 : E(read);
5214 IALU : R;
5215 BR : R;
5216 %}
5217
5218 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5219 single_instruction_with_delay_slot;
5220 cr : E(read);
5221 BR : R;
5222 %}
5223
5224 pipe_class br_nop() %{
5225 single_instruction;
5226 BR : R;
5227 %}
5228
5229 pipe_class simple_call(method meth) %{
5230 instruction_count(2); multiple_bundles; force_serialization;
5231 fixed_latency(100);
5232 BR : R(1);
5233 MS : R(1);
5234 A0 : R(1);
5235 %}
5236
5237 pipe_class compiled_call(method meth) %{
5238 instruction_count(1); multiple_bundles; force_serialization;
5239 fixed_latency(100);
5240 MS : R(1);
5241 %}
5242
5243 pipe_class call(method meth) %{
5244 instruction_count(0); multiple_bundles; force_serialization;
5245 fixed_latency(100);
5246 %}
5247
5248 pipe_class tail_call(Universe ignore, label labl) %{
5249 single_instruction; has_delay_slot;
5250 fixed_latency(100);
5251 BR : R(1);
5252 MS : R(1);
5253 %}
5254
5255 pipe_class ret(Universe ignore) %{
5256 single_instruction; has_delay_slot;
5257 BR : R(1);
5258 MS : R(1);
5259 %}
5260
5261 pipe_class ret_poll(g3RegP poll) %{
5262 instruction_count(3); has_delay_slot;
5263 poll : E(read);
5264 MS : R;
5265 %}
5266
5267 // The real do-nothing guy
5268 pipe_class empty( ) %{
5269 instruction_count(0);
5270 %}
5271
5272 pipe_class long_memory_op() %{
5273 instruction_count(0); multiple_bundles; force_serialization;
5274 fixed_latency(25);
5275 MS : R(1);
5276 %}
5277
5278 // Check-cast
5279 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5280 array : R(read);
5281 match : R(read);
5282 IALU : R(2);
5283 BR : R(2);
5284 MS : R;
5285 %}
5286
5287 // Convert FPU flags into +1,0,-1
5288 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5289 src1 : E(read);
5290 src2 : E(read);
5291 dst : E(write);
5292 FA : R;
5293 MS : R(2);
5294 BR : R(2);
5295 %}
5296
5297 // Compare for p < q, and conditionally add y
5298 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5299 p : E(read);
5300 q : E(read);
5301 y : E(read);
5302 IALU : R(3)
5303 %}
5304
5305 // Perform a compare, then move conditionally in a branch delay slot.
5306 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5307 src2 : E(read);
5308 srcdst : E(read);
5309 IALU : R;
5310 BR : R;
5311 %}
5312
5313 // Define the class for the Nop node
5314 define %{
5315 MachNop = ialu_nop;
5316 %}
5317
5318 %}
5319
5320 //----------INSTRUCTIONS-------------------------------------------------------
5321
5322 //------------Special Stack Slot instructions - no match rules-----------------
5323 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5324 // No match rule to avoid chain rule match.
5325 effect(DEF dst, USE src);
5326 ins_cost(MEMORY_REF_COST);
5327 size(4);
5328 format %{ "LDF $src,$dst\t! stkI to regF" %}
5329 opcode(Assembler::ldf_op3);
5330 ins_encode(simple_form3_mem_reg(src, dst));
5331 ins_pipe(floadF_stk);
5332 %}
5333
5334 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5335 // No match rule to avoid chain rule match.
5336 effect(DEF dst, USE src);
5337 ins_cost(MEMORY_REF_COST);
5338 size(4);
5339 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5340 opcode(Assembler::lddf_op3);
5341 ins_encode(simple_form3_mem_reg(src, dst));
5342 ins_pipe(floadD_stk);
5343 %}
5344
5345 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5346 // No match rule to avoid chain rule match.
5347 effect(DEF dst, USE src);
5348 ins_cost(MEMORY_REF_COST);
5349 size(4);
5350 format %{ "STF $src,$dst\t! regF to stkI" %}
5351 opcode(Assembler::stf_op3);
5352 ins_encode(simple_form3_mem_reg(dst, src));
5353 ins_pipe(fstoreF_stk_reg);
5354 %}
5355
5356 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5357 // No match rule to avoid chain rule match.
5358 effect(DEF dst, USE src);
5359 ins_cost(MEMORY_REF_COST);
5360 size(4);
5361 format %{ "STDF $src,$dst\t! regD to stkL" %}
5362 opcode(Assembler::stdf_op3);
5363 ins_encode(simple_form3_mem_reg(dst, src));
5364 ins_pipe(fstoreD_stk_reg);
5365 %}
5366
5367 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5368 effect(DEF dst, USE src);
5369 ins_cost(MEMORY_REF_COST*2);
5370 size(8);
5371 format %{ "STW $src,$dst.hi\t! long\n\t"
5372 "STW R_G0,$dst.lo" %}
5373 opcode(Assembler::stw_op3);
5374 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5375 ins_pipe(lstoreI_stk_reg);
5376 %}
5377
5378 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5379 // No match rule to avoid chain rule match.
5380 effect(DEF dst, USE src);
5381 ins_cost(MEMORY_REF_COST);
5382 size(4);
5383 format %{ "STX $src,$dst\t! regL to stkD" %}
5384 opcode(Assembler::stx_op3);
5385 ins_encode(simple_form3_mem_reg( dst, src ) );
5386 ins_pipe(istore_stk_reg);
5387 %}
5388
5389 //---------- Chain stack slots between similar types --------
5390
5391 // Load integer from stack slot
5392 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5393 match(Set dst src);
5394 ins_cost(MEMORY_REF_COST);
5395
5396 size(4);
5397 format %{ "LDUW $src,$dst\t!stk" %}
5398 opcode(Assembler::lduw_op3);
5399 ins_encode(simple_form3_mem_reg( src, dst ) );
5400 ins_pipe(iload_mem);
5401 %}
5402
5403 // Store integer to stack slot
5404 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5405 match(Set dst src);
5406 ins_cost(MEMORY_REF_COST);
5407
5408 size(4);
5409 format %{ "STW $src,$dst\t!stk" %}
5410 opcode(Assembler::stw_op3);
5411 ins_encode(simple_form3_mem_reg( dst, src ) );
5412 ins_pipe(istore_mem_reg);
5413 %}
5414
5415 // Load long from stack slot
5416 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5417 match(Set dst src);
5418
5419 ins_cost(MEMORY_REF_COST);
5420 size(4);
5421 format %{ "LDX $src,$dst\t! long" %}
5422 opcode(Assembler::ldx_op3);
5423 ins_encode(simple_form3_mem_reg( src, dst ) );
5424 ins_pipe(iload_mem);
5425 %}
5426
5427 // Store long to stack slot
5428 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5429 match(Set dst src);
5430
5431 ins_cost(MEMORY_REF_COST);
5432 size(4);
5433 format %{ "STX $src,$dst\t! long" %}
5434 opcode(Assembler::stx_op3);
5435 ins_encode(simple_form3_mem_reg( dst, src ) );
5436 ins_pipe(istore_mem_reg);
5437 %}
5438
5439 #ifdef _LP64
5440 // Load pointer from stack slot, 64-bit encoding
5441 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5442 match(Set dst src);
5443 ins_cost(MEMORY_REF_COST);
5444 size(4);
5445 format %{ "LDX $src,$dst\t!ptr" %}
5446 opcode(Assembler::ldx_op3);
5447 ins_encode(simple_form3_mem_reg( src, dst ) );
5448 ins_pipe(iload_mem);
5449 %}
5450
5451 // Store pointer to stack slot
5452 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5453 match(Set dst src);
5454 ins_cost(MEMORY_REF_COST);
5455 size(4);
5456 format %{ "STX $src,$dst\t!ptr" %}
5457 opcode(Assembler::stx_op3);
5458 ins_encode(simple_form3_mem_reg( dst, src ) );
5459 ins_pipe(istore_mem_reg);
5460 %}
5461 #else // _LP64
5462 // Load pointer from stack slot, 32-bit encoding
5463 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5464 match(Set dst src);
5465 ins_cost(MEMORY_REF_COST);
5466 format %{ "LDUW $src,$dst\t!ptr" %}
5467 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5468 ins_encode(simple_form3_mem_reg( src, dst ) );
5469 ins_pipe(iload_mem);
5470 %}
5471
5472 // Store pointer to stack slot
5473 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5474 match(Set dst src);
5475 ins_cost(MEMORY_REF_COST);
5476 format %{ "STW $src,$dst\t!ptr" %}
5477 opcode(Assembler::stw_op3, Assembler::ldst_op);
5478 ins_encode(simple_form3_mem_reg( dst, src ) );
5479 ins_pipe(istore_mem_reg);
5480 %}
5481 #endif // _LP64
5482
5483 //------------Special Nop instructions for bundling - no match rules-----------
5484 // Nop using the A0 functional unit
5485 instruct Nop_A0() %{
5486 ins_cost(0);
5487
5488 format %{ "NOP ! Alu Pipeline" %}
5489 opcode(Assembler::or_op3, Assembler::arith_op);
5490 ins_encode( form2_nop() );
5491 ins_pipe(ialu_nop_A0);
5492 %}
5493
5494 // Nop using the A1 functional unit
5495 instruct Nop_A1( ) %{
5496 ins_cost(0);
5497
5498 format %{ "NOP ! Alu Pipeline" %}
5499 opcode(Assembler::or_op3, Assembler::arith_op);
5500 ins_encode( form2_nop() );
5501 ins_pipe(ialu_nop_A1);
5502 %}
5503
5504 // Nop using the memory functional unit
5505 instruct Nop_MS( ) %{
5506 ins_cost(0);
5507
5508 format %{ "NOP ! Memory Pipeline" %}
5509 ins_encode( emit_mem_nop );
5510 ins_pipe(mem_nop);
5511 %}
5512
5513 // Nop using the floating add functional unit
5514 instruct Nop_FA( ) %{
5515 ins_cost(0);
5516
5517 format %{ "NOP ! Floating Add Pipeline" %}
5518 ins_encode( emit_fadd_nop );
5519 ins_pipe(fadd_nop);
5520 %}
5521
5522 // Nop using the branch functional unit
5523 instruct Nop_BR( ) %{
5524 ins_cost(0);
5525
5526 format %{ "NOP ! Branch Pipeline" %}
5527 ins_encode( emit_br_nop );
5528 ins_pipe(br_nop);
5529 %}
5530
5531 //----------Load/Store/Move Instructions---------------------------------------
5532 //----------Load Instructions--------------------------------------------------
5533 // Load Byte (8bit signed)
5534 instruct loadB(iRegI dst, memory mem) %{
5535 match(Set dst (LoadB mem));
5536 ins_cost(MEMORY_REF_COST);
5537
5538 size(4);
5539 format %{ "LDSB $mem,$dst\t! byte" %}
5540 ins_encode %{
5541 __ ldsb($mem$$Address, $dst$$Register);
5542 %}
5543 ins_pipe(iload_mask_mem);
5544 %}
5545
5546 // Load Byte (8bit signed) into a Long Register
5547 instruct loadB2L(iRegL dst, memory mem) %{
5548 match(Set dst (ConvI2L (LoadB mem)));
5549 ins_cost(MEMORY_REF_COST);
5550
5551 size(4);
5552 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5553 ins_encode %{
5554 __ ldsb($mem$$Address, $dst$$Register);
5555 %}
5556 ins_pipe(iload_mask_mem);
5557 %}
5558
5559 // Load Unsigned Byte (8bit UNsigned) into an int reg
5560 instruct loadUB(iRegI dst, memory mem) %{
5561 match(Set dst (LoadUB mem));
5562 ins_cost(MEMORY_REF_COST);
5563
5564 size(4);
5565 format %{ "LDUB $mem,$dst\t! ubyte" %}
5566 ins_encode %{
5567 __ ldub($mem$$Address, $dst$$Register);
5568 %}
5569 ins_pipe(iload_mem);
5570 %}
5571
5572 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5573 instruct loadUB2L(iRegL dst, memory mem) %{
5574 match(Set dst (ConvI2L (LoadUB mem)));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5579 ins_encode %{
5580 __ ldub($mem$$Address, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mem);
5583 %}
5584
5585 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5586 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5587 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5588 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5589
5590 size(2*4);
5591 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5592 "AND $dst,$mask,$dst" %}
5593 ins_encode %{
5594 __ ldub($mem$$Address, $dst$$Register);
5595 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5596 %}
5597 ins_pipe(iload_mem);
5598 %}
5599
5600 // Load Short (16bit signed)
5601 instruct loadS(iRegI dst, memory mem) %{
5602 match(Set dst (LoadS mem));
5603 ins_cost(MEMORY_REF_COST);
5604
5605 size(4);
5606 format %{ "LDSH $mem,$dst\t! short" %}
5607 ins_encode %{
5608 __ ldsh($mem$$Address, $dst$$Register);
5609 %}
5610 ins_pipe(iload_mask_mem);
5611 %}
5612
5613 // Load Short (16 bit signed) to Byte (8 bit signed)
5614 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5615 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5616 ins_cost(MEMORY_REF_COST);
5617
5618 size(4);
5619
5620 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5621 ins_encode %{
5622 __ ldsb($mem$$Address, $dst$$Register, 1);
5623 %}
5624 ins_pipe(iload_mask_mem);
5625 %}
5626
5627 // Load Short (16bit signed) into a Long Register
5628 instruct loadS2L(iRegL dst, memory mem) %{
5629 match(Set dst (ConvI2L (LoadS mem)));
5630 ins_cost(MEMORY_REF_COST);
5631
5632 size(4);
5633 format %{ "LDSH $mem,$dst\t! short -> long" %}
5634 ins_encode %{
5635 __ ldsh($mem$$Address, $dst$$Register);
5636 %}
5637 ins_pipe(iload_mask_mem);
5638 %}
5639
5640 // Load Unsigned Short/Char (16bit UNsigned)
5641 instruct loadUS(iRegI dst, memory mem) %{
5642 match(Set dst (LoadUS mem));
5643 ins_cost(MEMORY_REF_COST);
5644
5645 size(4);
5646 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5647 ins_encode %{
5648 __ lduh($mem$$Address, $dst$$Register);
5649 %}
5650 ins_pipe(iload_mem);
5651 %}
5652
5653 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5654 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5655 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 size(4);
5659 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5660 ins_encode %{
5661 __ ldsb($mem$$Address, $dst$$Register, 1);
5662 %}
5663 ins_pipe(iload_mask_mem);
5664 %}
5665
5666 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5667 instruct loadUS2L(iRegL dst, memory mem) %{
5668 match(Set dst (ConvI2L (LoadUS mem)));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5673 ins_encode %{
5674 __ lduh($mem$$Address, $dst$$Register);
5675 %}
5676 ins_pipe(iload_mem);
5677 %}
5678
5679 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5680 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5681 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 size(4);
5685 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5686 ins_encode %{
5687 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5688 %}
5689 ins_pipe(iload_mem);
5690 %}
5691
5692 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5693 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5694 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5695 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5696
5697 size(2*4);
5698 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5699 "AND $dst,$mask,$dst" %}
5700 ins_encode %{
5701 Register Rdst = $dst$$Register;
5702 __ lduh($mem$$Address, Rdst);
5703 __ and3(Rdst, $mask$$constant, Rdst);
5704 %}
5705 ins_pipe(iload_mem);
5706 %}
5707
5708 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5709 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5710 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5711 effect(TEMP dst, TEMP tmp);
5712 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5713
5714 size((3+1)*4); // set may use two instructions.
5715 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5716 "SET $mask,$tmp\n\t"
5717 "AND $dst,$tmp,$dst" %}
5718 ins_encode %{
5719 Register Rdst = $dst$$Register;
5720 Register Rtmp = $tmp$$Register;
5721 __ lduh($mem$$Address, Rdst);
5722 __ set($mask$$constant, Rtmp);
5723 __ and3(Rdst, Rtmp, Rdst);
5724 %}
5725 ins_pipe(iload_mem);
5726 %}
5727
5728 // Load Integer
5729 instruct loadI(iRegI dst, memory mem) %{
5730 match(Set dst (LoadI mem));
5731 ins_cost(MEMORY_REF_COST);
5732
5733 size(4);
5734 format %{ "LDUW $mem,$dst\t! int" %}
5735 ins_encode %{
5736 __ lduw($mem$$Address, $dst$$Register);
5737 %}
5738 ins_pipe(iload_mem);
5739 %}
5740
5741 // Load Integer to Byte (8 bit signed)
5742 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5743 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5744 ins_cost(MEMORY_REF_COST);
5745
5746 size(4);
5747
5748 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5749 ins_encode %{
5750 __ ldsb($mem$$Address, $dst$$Register, 3);
5751 %}
5752 ins_pipe(iload_mask_mem);
5753 %}
5754
5755 // Load Integer to Unsigned Byte (8 bit UNsigned)
5756 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5757 match(Set dst (AndI (LoadI mem) mask));
5758 ins_cost(MEMORY_REF_COST);
5759
5760 size(4);
5761
5762 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5763 ins_encode %{
5764 __ ldub($mem$$Address, $dst$$Register, 3);
5765 %}
5766 ins_pipe(iload_mask_mem);
5767 %}
5768
5769 // Load Integer to Short (16 bit signed)
5770 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5771 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5772 ins_cost(MEMORY_REF_COST);
5773
5774 size(4);
5775
5776 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5777 ins_encode %{
5778 __ ldsh($mem$$Address, $dst$$Register, 2);
5779 %}
5780 ins_pipe(iload_mask_mem);
5781 %}
5782
5783 // Load Integer to Unsigned Short (16 bit UNsigned)
5784 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5785 match(Set dst (AndI (LoadI mem) mask));
5786 ins_cost(MEMORY_REF_COST);
5787
5788 size(4);
5789
5790 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5791 ins_encode %{
5792 __ lduh($mem$$Address, $dst$$Register, 2);
5793 %}
5794 ins_pipe(iload_mask_mem);
5795 %}
5796
5797 // Load Integer into a Long Register
5798 instruct loadI2L(iRegL dst, memory mem) %{
5799 match(Set dst (ConvI2L (LoadI mem)));
5800 ins_cost(MEMORY_REF_COST);
5801
5802 size(4);
5803 format %{ "LDSW $mem,$dst\t! int -> long" %}
5804 ins_encode %{
5805 __ ldsw($mem$$Address, $dst$$Register);
5806 %}
5807 ins_pipe(iload_mask_mem);
5808 %}
5809
5810 // Load Integer with mask 0xFF into a Long Register
5811 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5812 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5813 ins_cost(MEMORY_REF_COST);
5814
5815 size(4);
5816 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5817 ins_encode %{
5818 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5819 %}
5820 ins_pipe(iload_mem);
5821 %}
5822
5823 // Load Integer with mask 0xFFFF into a Long Register
5824 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5825 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5826 ins_cost(MEMORY_REF_COST);
5827
5828 size(4);
5829 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5830 ins_encode %{
5831 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5832 %}
5833 ins_pipe(iload_mem);
5834 %}
5835
5836 // Load Integer with a 13-bit mask into a Long Register
5837 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5838 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5839 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5840
5841 size(2*4);
5842 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5843 "AND $dst,$mask,$dst" %}
5844 ins_encode %{
5845 Register Rdst = $dst$$Register;
5846 __ lduw($mem$$Address, Rdst);
5847 __ and3(Rdst, $mask$$constant, Rdst);
5848 %}
5849 ins_pipe(iload_mem);
5850 %}
5851
5852 // Load Integer with a 32-bit mask into a Long Register
5853 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5854 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5855 effect(TEMP dst, TEMP tmp);
5856 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5857
5858 size((3+1)*4); // set may use two instructions.
5859 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5860 "SET $mask,$tmp\n\t"
5861 "AND $dst,$tmp,$dst" %}
5862 ins_encode %{
5863 Register Rdst = $dst$$Register;
5864 Register Rtmp = $tmp$$Register;
5865 __ lduw($mem$$Address, Rdst);
5866 __ set($mask$$constant, Rtmp);
5867 __ and3(Rdst, Rtmp, Rdst);
5868 %}
5869 ins_pipe(iload_mem);
5870 %}
5871
5872 // Load Unsigned Integer into a Long Register
5873 instruct loadUI2L(iRegL dst, memory mem) %{
5874 match(Set dst (LoadUI2L mem));
5875 ins_cost(MEMORY_REF_COST);
5876
5877 size(4);
5878 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5879 ins_encode %{
5880 __ lduw($mem$$Address, $dst$$Register);
5881 %}
5882 ins_pipe(iload_mem);
5883 %}
5884
5885 // Load Long - aligned
5886 instruct loadL(iRegL dst, memory mem ) %{
5887 match(Set dst (LoadL mem));
5888 ins_cost(MEMORY_REF_COST);
5889
5890 size(4);
5891 format %{ "LDX $mem,$dst\t! long" %}
5892 ins_encode %{
5893 __ ldx($mem$$Address, $dst$$Register);
5894 %}
5895 ins_pipe(iload_mem);
5896 %}
5897
5898 // Load Long - UNaligned
5899 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5900 match(Set dst (LoadL_unaligned mem));
5901 effect(KILL tmp);
5902 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5903 size(16);
5904 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5905 "\tLDUW $mem ,$dst\n"
5906 "\tSLLX #32, $dst, $dst\n"
5907 "\tOR $dst, R_O7, $dst" %}
5908 opcode(Assembler::lduw_op3);
5909 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5910 ins_pipe(iload_mem);
5911 %}
5912
5913 // Load Range
5914 instruct loadRange(iRegI dst, memory mem) %{
5915 match(Set dst (LoadRange mem));
5916 ins_cost(MEMORY_REF_COST);
5917
5918 size(4);
5919 format %{ "LDUW $mem,$dst\t! range" %}
5920 opcode(Assembler::lduw_op3);
5921 ins_encode(simple_form3_mem_reg( mem, dst ) );
5922 ins_pipe(iload_mem);
5923 %}
5924
5925 // Load Integer into %f register (for fitos/fitod)
5926 instruct loadI_freg(regF dst, memory mem) %{
5927 match(Set dst (LoadI mem));
5928 ins_cost(MEMORY_REF_COST);
5929 size(4);
5930
5931 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5932 opcode(Assembler::ldf_op3);
5933 ins_encode(simple_form3_mem_reg( mem, dst ) );
5934 ins_pipe(floadF_mem);
5935 %}
5936
5937 // Load Pointer
5938 instruct loadP(iRegP dst, memory mem) %{
5939 match(Set dst (LoadP mem));
5940 ins_cost(MEMORY_REF_COST);
5941 size(4);
5942
5943 #ifndef _LP64
5944 format %{ "LDUW $mem,$dst\t! ptr" %}
5945 ins_encode %{
5946 __ lduw($mem$$Address, $dst$$Register);
5947 %}
5948 #else
5949 format %{ "LDX $mem,$dst\t! ptr" %}
5950 ins_encode %{
5951 __ ldx($mem$$Address, $dst$$Register);
5952 %}
5953 #endif
5954 ins_pipe(iload_mem);
5955 %}
5956
5957 // Load Compressed Pointer
5958 instruct loadN(iRegN dst, memory mem) %{
5959 match(Set dst (LoadN mem));
5960 ins_cost(MEMORY_REF_COST);
5961 size(4);
5962
5963 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5964 ins_encode %{
5965 __ lduw($mem$$Address, $dst$$Register);
5966 %}
5967 ins_pipe(iload_mem);
5968 %}
5969
5970 // Load Klass Pointer
5971 instruct loadKlass(iRegP dst, memory mem) %{
5972 match(Set dst (LoadKlass mem));
5973 ins_cost(MEMORY_REF_COST);
5974 size(4);
5975
5976 #ifndef _LP64
5977 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5978 ins_encode %{
5979 __ lduw($mem$$Address, $dst$$Register);
5980 %}
5981 #else
5982 format %{ "LDX $mem,$dst\t! klass ptr" %}
5983 ins_encode %{
5984 __ ldx($mem$$Address, $dst$$Register);
5985 %}
5986 #endif
5987 ins_pipe(iload_mem);
5988 %}
5989
5990 // Load narrow Klass Pointer
5991 instruct loadNKlass(iRegN dst, memory mem) %{
5992 match(Set dst (LoadNKlass mem));
5993 ins_cost(MEMORY_REF_COST);
5994 size(4);
5995
5996 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5997 ins_encode %{
5998 __ lduw($mem$$Address, $dst$$Register);
5999 %}
6000 ins_pipe(iload_mem);
6001 %}
6002
6003 // Load Double
6004 instruct loadD(regD dst, memory mem) %{
6005 match(Set dst (LoadD mem));
6006 ins_cost(MEMORY_REF_COST);
6007
6008 size(4);
6009 format %{ "LDDF $mem,$dst" %}
6010 opcode(Assembler::lddf_op3);
6011 ins_encode(simple_form3_mem_reg( mem, dst ) );
6012 ins_pipe(floadD_mem);
6013 %}
6014
6015 // Load Double - UNaligned
6016 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6017 match(Set dst (LoadD_unaligned mem));
6018 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6019 size(8);
6020 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6021 "\tLDF $mem+4,$dst.lo\t!" %}
6022 opcode(Assembler::ldf_op3);
6023 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6024 ins_pipe(iload_mem);
6025 %}
6026
6027 // Load Float
6028 instruct loadF(regF dst, memory mem) %{
6029 match(Set dst (LoadF mem));
6030 ins_cost(MEMORY_REF_COST);
6031
6032 size(4);
6033 format %{ "LDF $mem,$dst" %}
6034 opcode(Assembler::ldf_op3);
6035 ins_encode(simple_form3_mem_reg( mem, dst ) );
6036 ins_pipe(floadF_mem);
6037 %}
6038
6039 // Load Constant
6040 instruct loadConI( iRegI dst, immI src ) %{
6041 match(Set dst src);
6042 ins_cost(DEFAULT_COST * 3/2);
6043 format %{ "SET $src,$dst" %}
6044 ins_encode( Set32(src, dst) );
6045 ins_pipe(ialu_hi_lo_reg);
6046 %}
6047
6048 instruct loadConI13( iRegI dst, immI13 src ) %{
6049 match(Set dst src);
6050
6051 size(4);
6052 format %{ "MOV $src,$dst" %}
6053 ins_encode( Set13( src, dst ) );
6054 ins_pipe(ialu_imm);
6055 %}
6056
6057 #ifndef _LP64
6058 instruct loadConP(iRegP dst, immP con) %{
6059 match(Set dst con);
6060 ins_cost(DEFAULT_COST * 3/2);
6061 format %{ "SET $con,$dst\t!ptr" %}
6062 ins_encode %{
6063 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6064 intptr_t val = $con$$constant;
6065 if (constant_reloc == relocInfo::oop_type) {
6066 __ set_oop_constant((jobject) val, $dst$$Register);
6067 } else if (constant_reloc == relocInfo::metadata_type) {
6068 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6069 } else { // non-oop pointers, e.g. card mark base, heap top
6070 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6071 __ set(val, $dst$$Register);
6072 }
6073 %}
6074 ins_pipe(loadConP);
6075 %}
6076 #else
6077 instruct loadConP_set(iRegP dst, immP_set con) %{
6078 match(Set dst con);
6079 ins_cost(DEFAULT_COST * 3/2);
6080 format %{ "SET $con,$dst\t! ptr" %}
6081 ins_encode %{
6082 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6083 intptr_t val = $con$$constant;
6084 if (constant_reloc == relocInfo::oop_type) {
6085 __ set_oop_constant((jobject) val, $dst$$Register);
6086 } else if (constant_reloc == relocInfo::metadata_type) {
6087 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6088 } else { // non-oop pointers, e.g. card mark base, heap top
6089 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6090 __ set(val, $dst$$Register);
6091 }
6092 %}
6093 ins_pipe(loadConP);
6094 %}
6095
6096 instruct loadConP_load(iRegP dst, immP_load con) %{
6097 match(Set dst con);
6098 ins_cost(MEMORY_REF_COST);
6099 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6100 ins_encode %{
6101 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6102 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6103 %}
6104 ins_pipe(loadConP);
6105 %}
6106
6107 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6108 match(Set dst con);
6109 ins_cost(DEFAULT_COST * 3/2);
6110 format %{ "SET $con,$dst\t! non-oop ptr" %}
6111 ins_encode %{
6112 __ set($con$$constant, $dst$$Register);
6113 %}
6114 ins_pipe(loadConP);
6115 %}
6116 #endif // _LP64
6117
6118 instruct loadConP0(iRegP dst, immP0 src) %{
6119 match(Set dst src);
6120
6121 size(4);
6122 format %{ "CLR $dst\t!ptr" %}
6123 ins_encode %{
6124 __ clr($dst$$Register);
6125 %}
6126 ins_pipe(ialu_imm);
6127 %}
6128
6129 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6130 match(Set dst src);
6131 ins_cost(DEFAULT_COST);
6132 format %{ "SET $src,$dst\t!ptr" %}
6133 ins_encode %{
6134 AddressLiteral polling_page(os::get_polling_page());
6135 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6136 %}
6137 ins_pipe(loadConP_poll);
6138 %}
6139
6140 instruct loadConN0(iRegN dst, immN0 src) %{
6141 match(Set dst src);
6142
6143 size(4);
6144 format %{ "CLR $dst\t! compressed NULL ptr" %}
6145 ins_encode %{
6146 __ clr($dst$$Register);
6147 %}
6148 ins_pipe(ialu_imm);
6149 %}
6150
6151 instruct loadConN(iRegN dst, immN src) %{
6152 match(Set dst src);
6153 ins_cost(DEFAULT_COST * 3/2);
6154 format %{ "SET $src,$dst\t! compressed ptr" %}
6155 ins_encode %{
6156 Register dst = $dst$$Register;
6157 __ set_narrow_oop((jobject)$src$$constant, dst);
6158 %}
6159 ins_pipe(ialu_hi_lo_reg);
6160 %}
6161
6162 // Materialize long value (predicated by immL_cheap).
6163 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6164 match(Set dst con);
6165 effect(KILL tmp);
6166 ins_cost(DEFAULT_COST * 3);
6167 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6168 ins_encode %{
6169 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6170 %}
6171 ins_pipe(loadConL);
6172 %}
6173
6174 // Load long value from constant table (predicated by immL_expensive).
6175 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6176 match(Set dst con);
6177 ins_cost(MEMORY_REF_COST);
6178 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6179 ins_encode %{
6180 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6181 __ ldx($constanttablebase, con_offset, $dst$$Register);
6182 %}
6183 ins_pipe(loadConL);
6184 %}
6185
6186 instruct loadConL0( iRegL dst, immL0 src ) %{
6187 match(Set dst src);
6188 ins_cost(DEFAULT_COST);
6189 size(4);
6190 format %{ "CLR $dst\t! long" %}
6191 ins_encode( Set13( src, dst ) );
6192 ins_pipe(ialu_imm);
6193 %}
6194
6195 instruct loadConL13( iRegL dst, immL13 src ) %{
6196 match(Set dst src);
6197 ins_cost(DEFAULT_COST * 2);
6198
6199 size(4);
6200 format %{ "MOV $src,$dst\t! long" %}
6201 ins_encode( Set13( src, dst ) );
6202 ins_pipe(ialu_imm);
6203 %}
6204
6205 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6206 match(Set dst con);
6207 effect(KILL tmp);
6208 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6209 ins_encode %{
6210 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6211 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6212 %}
6213 ins_pipe(loadConFD);
6214 %}
6215
6216 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6217 match(Set dst con);
6218 effect(KILL tmp);
6219 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6220 ins_encode %{
6221 // XXX This is a quick fix for 6833573.
6222 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6223 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6224 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6225 %}
6226 ins_pipe(loadConFD);
6227 %}
6228
6229 // Prefetch instructions.
6230 // Must be safe to execute with invalid address (cannot fault).
6231
6232 instruct prefetchr( memory mem ) %{
6233 match( PrefetchRead mem );
6234 ins_cost(MEMORY_REF_COST);
6235 size(4);
6236
6237 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6238 opcode(Assembler::prefetch_op3);
6239 ins_encode( form3_mem_prefetch_read( mem ) );
6240 ins_pipe(iload_mem);
6241 %}
6242
6243 instruct prefetchw( memory mem ) %{
6244 match( PrefetchWrite mem );
6245 ins_cost(MEMORY_REF_COST);
6246 size(4);
6247
6248 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6249 opcode(Assembler::prefetch_op3);
6250 ins_encode( form3_mem_prefetch_write( mem ) );
6251 ins_pipe(iload_mem);
6252 %}
6253
6254 // Prefetch instructions for allocation.
6255
6256 instruct prefetchAlloc( memory mem ) %{
6257 predicate(AllocatePrefetchInstr == 0);
6258 match( PrefetchAllocation mem );
6259 ins_cost(MEMORY_REF_COST);
6260 size(4);
6261
6262 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6263 opcode(Assembler::prefetch_op3);
6264 ins_encode( form3_mem_prefetch_write( mem ) );
6265 ins_pipe(iload_mem);
6266 %}
6267
6268 // Use BIS instruction to prefetch for allocation.
6269 // Could fault, need space at the end of TLAB.
6270 instruct prefetchAlloc_bis( iRegP dst ) %{
6271 predicate(AllocatePrefetchInstr == 1);
6272 match( PrefetchAllocation dst );
6273 ins_cost(MEMORY_REF_COST);
6274 size(4);
6275
6276 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6277 ins_encode %{
6278 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6279 %}
6280 ins_pipe(istore_mem_reg);
6281 %}
6282
6283 // Next code is used for finding next cache line address to prefetch.
6284 #ifndef _LP64
6285 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6286 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6287 ins_cost(DEFAULT_COST);
6288 size(4);
6289
6290 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6291 ins_encode %{
6292 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6293 %}
6294 ins_pipe(ialu_reg_imm);
6295 %}
6296 #else
6297 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6298 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6299 ins_cost(DEFAULT_COST);
6300 size(4);
6301
6302 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6303 ins_encode %{
6304 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6305 %}
6306 ins_pipe(ialu_reg_imm);
6307 %}
6308 #endif
6309
6310 //----------Store Instructions-------------------------------------------------
6311 // Store Byte
6312 instruct storeB(memory mem, iRegI src) %{
6313 match(Set mem (StoreB mem src));
6314 ins_cost(MEMORY_REF_COST);
6315
6316 size(4);
6317 format %{ "STB $src,$mem\t! byte" %}
6318 opcode(Assembler::stb_op3);
6319 ins_encode(simple_form3_mem_reg( mem, src ) );
6320 ins_pipe(istore_mem_reg);
6321 %}
6322
6323 instruct storeB0(memory mem, immI0 src) %{
6324 match(Set mem (StoreB mem src));
6325 ins_cost(MEMORY_REF_COST);
6326
6327 size(4);
6328 format %{ "STB $src,$mem\t! byte" %}
6329 opcode(Assembler::stb_op3);
6330 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6331 ins_pipe(istore_mem_zero);
6332 %}
6333
6334 instruct storeCM0(memory mem, immI0 src) %{
6335 match(Set mem (StoreCM mem src));
6336 ins_cost(MEMORY_REF_COST);
6337
6338 size(4);
6339 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6340 opcode(Assembler::stb_op3);
6341 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6342 ins_pipe(istore_mem_zero);
6343 %}
6344
6345 // Store Char/Short
6346 instruct storeC(memory mem, iRegI src) %{
6347 match(Set mem (StoreC mem src));
6348 ins_cost(MEMORY_REF_COST);
6349
6350 size(4);
6351 format %{ "STH $src,$mem\t! short" %}
6352 opcode(Assembler::sth_op3);
6353 ins_encode(simple_form3_mem_reg( mem, src ) );
6354 ins_pipe(istore_mem_reg);
6355 %}
6356
6357 instruct storeC0(memory mem, immI0 src) %{
6358 match(Set mem (StoreC mem src));
6359 ins_cost(MEMORY_REF_COST);
6360
6361 size(4);
6362 format %{ "STH $src,$mem\t! short" %}
6363 opcode(Assembler::sth_op3);
6364 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6365 ins_pipe(istore_mem_zero);
6366 %}
6367
6368 // Store Integer
6369 instruct storeI(memory mem, iRegI src) %{
6370 match(Set mem (StoreI mem src));
6371 ins_cost(MEMORY_REF_COST);
6372
6373 size(4);
6374 format %{ "STW $src,$mem" %}
6375 opcode(Assembler::stw_op3);
6376 ins_encode(simple_form3_mem_reg( mem, src ) );
6377 ins_pipe(istore_mem_reg);
6378 %}
6379
6380 // Store Long
6381 instruct storeL(memory mem, iRegL src) %{
6382 match(Set mem (StoreL mem src));
6383 ins_cost(MEMORY_REF_COST);
6384 size(4);
6385 format %{ "STX $src,$mem\t! long" %}
6386 opcode(Assembler::stx_op3);
6387 ins_encode(simple_form3_mem_reg( mem, src ) );
6388 ins_pipe(istore_mem_reg);
6389 %}
6390
6391 instruct storeI0(memory mem, immI0 src) %{
6392 match(Set mem (StoreI mem src));
6393 ins_cost(MEMORY_REF_COST);
6394
6395 size(4);
6396 format %{ "STW $src,$mem" %}
6397 opcode(Assembler::stw_op3);
6398 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6399 ins_pipe(istore_mem_zero);
6400 %}
6401
6402 instruct storeL0(memory mem, immL0 src) %{
6403 match(Set mem (StoreL mem src));
6404 ins_cost(MEMORY_REF_COST);
6405
6406 size(4);
6407 format %{ "STX $src,$mem" %}
6408 opcode(Assembler::stx_op3);
6409 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6410 ins_pipe(istore_mem_zero);
6411 %}
6412
6413 // Store Integer from float register (used after fstoi)
6414 instruct storeI_Freg(memory mem, regF src) %{
6415 match(Set mem (StoreI mem src));
6416 ins_cost(MEMORY_REF_COST);
6417
6418 size(4);
6419 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6420 opcode(Assembler::stf_op3);
6421 ins_encode(simple_form3_mem_reg( mem, src ) );
6422 ins_pipe(fstoreF_mem_reg);
6423 %}
6424
6425 // Store Pointer
6426 instruct storeP(memory dst, sp_ptr_RegP src) %{
6427 match(Set dst (StoreP dst src));
6428 ins_cost(MEMORY_REF_COST);
6429 size(4);
6430
6431 #ifndef _LP64
6432 format %{ "STW $src,$dst\t! ptr" %}
6433 opcode(Assembler::stw_op3, 0, REGP_OP);
6434 #else
6435 format %{ "STX $src,$dst\t! ptr" %}
6436 opcode(Assembler::stx_op3, 0, REGP_OP);
6437 #endif
6438 ins_encode( form3_mem_reg( dst, src ) );
6439 ins_pipe(istore_mem_spORreg);
6440 %}
6441
6442 instruct storeP0(memory dst, immP0 src) %{
6443 match(Set dst (StoreP dst src));
6444 ins_cost(MEMORY_REF_COST);
6445 size(4);
6446
6447 #ifndef _LP64
6448 format %{ "STW $src,$dst\t! ptr" %}
6449 opcode(Assembler::stw_op3, 0, REGP_OP);
6450 #else
6451 format %{ "STX $src,$dst\t! ptr" %}
6452 opcode(Assembler::stx_op3, 0, REGP_OP);
6453 #endif
6454 ins_encode( form3_mem_reg( dst, R_G0 ) );
6455 ins_pipe(istore_mem_zero);
6456 %}
6457
6458 // Store Compressed Pointer
6459 instruct storeN(memory dst, iRegN src) %{
6460 match(Set dst (StoreN dst src));
6461 ins_cost(MEMORY_REF_COST);
6462 size(4);
6463
6464 format %{ "STW $src,$dst\t! compressed ptr" %}
6465 ins_encode %{
6466 Register base = as_Register($dst$$base);
6467 Register index = as_Register($dst$$index);
6468 Register src = $src$$Register;
6469 if (index != G0) {
6470 __ stw(src, base, index);
6471 } else {
6472 __ stw(src, base, $dst$$disp);
6473 }
6474 %}
6475 ins_pipe(istore_mem_spORreg);
6476 %}
6477
6478 instruct storeN0(memory dst, immN0 src) %{
6479 match(Set dst (StoreN dst src));
6480 ins_cost(MEMORY_REF_COST);
6481 size(4);
6482
6483 format %{ "STW $src,$dst\t! compressed ptr" %}
6484 ins_encode %{
6485 Register base = as_Register($dst$$base);
6486 Register index = as_Register($dst$$index);
6487 if (index != G0) {
6488 __ stw(0, base, index);
6489 } else {
6490 __ stw(0, base, $dst$$disp);
6491 }
6492 %}
6493 ins_pipe(istore_mem_zero);
6494 %}
6495
6496 // Store Double
6497 instruct storeD( memory mem, regD src) %{
6498 match(Set mem (StoreD mem src));
6499 ins_cost(MEMORY_REF_COST);
6500
6501 size(4);
6502 format %{ "STDF $src,$mem" %}
6503 opcode(Assembler::stdf_op3);
6504 ins_encode(simple_form3_mem_reg( mem, src ) );
6505 ins_pipe(fstoreD_mem_reg);
6506 %}
6507
6508 instruct storeD0( memory mem, immD0 src) %{
6509 match(Set mem (StoreD mem src));
6510 ins_cost(MEMORY_REF_COST);
6511
6512 size(4);
6513 format %{ "STX $src,$mem" %}
6514 opcode(Assembler::stx_op3);
6515 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6516 ins_pipe(fstoreD_mem_zero);
6517 %}
6518
6519 // Store Float
6520 instruct storeF( memory mem, regF src) %{
6521 match(Set mem (StoreF mem src));
6522 ins_cost(MEMORY_REF_COST);
6523
6524 size(4);
6525 format %{ "STF $src,$mem" %}
6526 opcode(Assembler::stf_op3);
6527 ins_encode(simple_form3_mem_reg( mem, src ) );
6528 ins_pipe(fstoreF_mem_reg);
6529 %}
6530
6531 instruct storeF0( memory mem, immF0 src) %{
6532 match(Set mem (StoreF mem src));
6533 ins_cost(MEMORY_REF_COST);
6534
6535 size(4);
6536 format %{ "STW $src,$mem\t! storeF0" %}
6537 opcode(Assembler::stw_op3);
6538 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6539 ins_pipe(fstoreF_mem_zero);
6540 %}
6541
6542 // Convert oop pointer into compressed form
6543 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6544 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6545 match(Set dst (EncodeP src));
6546 format %{ "encode_heap_oop $src, $dst" %}
6547 ins_encode %{
6548 __ encode_heap_oop($src$$Register, $dst$$Register);
6549 %}
6550 ins_pipe(ialu_reg);
6551 %}
6552
6553 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6554 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6555 match(Set dst (EncodeP src));
6556 format %{ "encode_heap_oop_not_null $src, $dst" %}
6557 ins_encode %{
6558 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6559 %}
6560 ins_pipe(ialu_reg);
6561 %}
6562
6563 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6564 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6565 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6566 match(Set dst (DecodeN src));
6567 format %{ "decode_heap_oop $src, $dst" %}
6568 ins_encode %{
6569 __ decode_heap_oop($src$$Register, $dst$$Register);
6570 %}
6571 ins_pipe(ialu_reg);
6572 %}
6573
6574 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6575 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6576 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6577 match(Set dst (DecodeN src));
6578 format %{ "decode_heap_oop_not_null $src, $dst" %}
6579 ins_encode %{
6580 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6581 %}
6582 ins_pipe(ialu_reg);
6583 %}
6584
6585
6586 //----------MemBar Instructions-----------------------------------------------
6587 // Memory barrier flavors
6588
6589 instruct membar_acquire() %{
6590 match(MemBarAcquire);
6591 ins_cost(4*MEMORY_REF_COST);
6592
6593 size(0);
6594 format %{ "MEMBAR-acquire" %}
6595 ins_encode( enc_membar_acquire );
6596 ins_pipe(long_memory_op);
6597 %}
6598
6599 instruct membar_acquire_lock() %{
6600 match(MemBarAcquireLock);
6601 ins_cost(0);
6602
6603 size(0);
6604 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6605 ins_encode( );
6606 ins_pipe(empty);
6607 %}
6608
6609 instruct membar_release() %{
6610 match(MemBarRelease);
6611 ins_cost(4*MEMORY_REF_COST);
6612
6613 size(0);
6614 format %{ "MEMBAR-release" %}
6615 ins_encode( enc_membar_release );
6616 ins_pipe(long_memory_op);
6617 %}
6618
6619 instruct membar_release_lock() %{
6620 match(MemBarReleaseLock);
6621 ins_cost(0);
6622
6623 size(0);
6624 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6625 ins_encode( );
6626 ins_pipe(empty);
6627 %}
6628
6629 instruct membar_volatile() %{
6630 match(MemBarVolatile);
6631 ins_cost(4*MEMORY_REF_COST);
6632
6633 size(4);
6634 format %{ "MEMBAR-volatile" %}
6635 ins_encode( enc_membar_volatile );
6636 ins_pipe(long_memory_op);
6637 %}
6638
6639 instruct unnecessary_membar_volatile() %{
6640 match(MemBarVolatile);
6641 predicate(Matcher::post_store_load_barrier(n));
6642 ins_cost(0);
6643
6644 size(0);
6645 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6646 ins_encode( );
6647 ins_pipe(empty);
6648 %}
6649
6650 instruct membar_storestore() %{
6651 match(MemBarStoreStore);
6652 ins_cost(0);
6653
6654 size(0);
6655 format %{ "!MEMBAR-storestore (empty encoding)" %}
6656 ins_encode( );
6657 ins_pipe(empty);
6658 %}
6659
6660 //----------Register Move Instructions-----------------------------------------
6661 instruct roundDouble_nop(regD dst) %{
6662 match(Set dst (RoundDouble dst));
6663 ins_cost(0);
6664 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6665 ins_encode( );
6666 ins_pipe(empty);
6667 %}
6668
6669
6670 instruct roundFloat_nop(regF dst) %{
6671 match(Set dst (RoundFloat dst));
6672 ins_cost(0);
6673 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6674 ins_encode( );
6675 ins_pipe(empty);
6676 %}
6677
6678
6679 // Cast Index to Pointer for unsafe natives
6680 instruct castX2P(iRegX src, iRegP dst) %{
6681 match(Set dst (CastX2P src));
6682
6683 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6684 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6685 ins_pipe(ialu_reg);
6686 %}
6687
6688 // Cast Pointer to Index for unsafe natives
6689 instruct castP2X(iRegP src, iRegX dst) %{
6690 match(Set dst (CastP2X src));
6691
6692 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6693 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6694 ins_pipe(ialu_reg);
6695 %}
6696
6697 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6698 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6699 match(Set stkSlot src); // chain rule
6700 ins_cost(MEMORY_REF_COST);
6701 format %{ "STDF $src,$stkSlot\t!stk" %}
6702 opcode(Assembler::stdf_op3);
6703 ins_encode(simple_form3_mem_reg(stkSlot, src));
6704 ins_pipe(fstoreD_stk_reg);
6705 %}
6706
6707 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6708 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6709 match(Set dst stkSlot); // chain rule
6710 ins_cost(MEMORY_REF_COST);
6711 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6712 opcode(Assembler::lddf_op3);
6713 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6714 ins_pipe(floadD_stk);
6715 %}
6716
6717 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6718 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6719 match(Set stkSlot src); // chain rule
6720 ins_cost(MEMORY_REF_COST);
6721 format %{ "STF $src,$stkSlot\t!stk" %}
6722 opcode(Assembler::stf_op3);
6723 ins_encode(simple_form3_mem_reg(stkSlot, src));
6724 ins_pipe(fstoreF_stk_reg);
6725 %}
6726
6727 //----------Conditional Move---------------------------------------------------
6728 // Conditional move
6729 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6730 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6731 ins_cost(150);
6732 format %{ "MOV$cmp $pcc,$src,$dst" %}
6733 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6734 ins_pipe(ialu_reg);
6735 %}
6736
6737 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6738 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6739 ins_cost(140);
6740 format %{ "MOV$cmp $pcc,$src,$dst" %}
6741 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6742 ins_pipe(ialu_imm);
6743 %}
6744
6745 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6746 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6747 ins_cost(150);
6748 size(4);
6749 format %{ "MOV$cmp $icc,$src,$dst" %}
6750 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6755 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6756 ins_cost(140);
6757 size(4);
6758 format %{ "MOV$cmp $icc,$src,$dst" %}
6759 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6760 ins_pipe(ialu_imm);
6761 %}
6762
6763 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6764 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6765 ins_cost(150);
6766 size(4);
6767 format %{ "MOV$cmp $icc,$src,$dst" %}
6768 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6769 ins_pipe(ialu_reg);
6770 %}
6771
6772 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6773 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6774 ins_cost(140);
6775 size(4);
6776 format %{ "MOV$cmp $icc,$src,$dst" %}
6777 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6778 ins_pipe(ialu_imm);
6779 %}
6780
6781 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6782 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6783 ins_cost(150);
6784 size(4);
6785 format %{ "MOV$cmp $fcc,$src,$dst" %}
6786 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6787 ins_pipe(ialu_reg);
6788 %}
6789
6790 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6791 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6792 ins_cost(140);
6793 size(4);
6794 format %{ "MOV$cmp $fcc,$src,$dst" %}
6795 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6796 ins_pipe(ialu_imm);
6797 %}
6798
6799 // Conditional move for RegN. Only cmov(reg,reg).
6800 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6801 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6802 ins_cost(150);
6803 format %{ "MOV$cmp $pcc,$src,$dst" %}
6804 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6805 ins_pipe(ialu_reg);
6806 %}
6807
6808 // This instruction also works with CmpN so we don't need cmovNN_reg.
6809 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6810 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6811 ins_cost(150);
6812 size(4);
6813 format %{ "MOV$cmp $icc,$src,$dst" %}
6814 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6815 ins_pipe(ialu_reg);
6816 %}
6817
6818 // This instruction also works with CmpN so we don't need cmovNN_reg.
6819 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6820 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6821 ins_cost(150);
6822 size(4);
6823 format %{ "MOV$cmp $icc,$src,$dst" %}
6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6825 ins_pipe(ialu_reg);
6826 %}
6827
6828 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6829 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6830 ins_cost(150);
6831 size(4);
6832 format %{ "MOV$cmp $fcc,$src,$dst" %}
6833 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6834 ins_pipe(ialu_reg);
6835 %}
6836
6837 // Conditional move
6838 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6839 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6840 ins_cost(150);
6841 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6842 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6843 ins_pipe(ialu_reg);
6844 %}
6845
6846 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6847 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6848 ins_cost(140);
6849 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6850 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6851 ins_pipe(ialu_imm);
6852 %}
6853
6854 // This instruction also works with CmpN so we don't need cmovPN_reg.
6855 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6856 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6857 ins_cost(150);
6858
6859 size(4);
6860 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6861 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6862 ins_pipe(ialu_reg);
6863 %}
6864
6865 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6866 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6867 ins_cost(150);
6868
6869 size(4);
6870 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6871 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6872 ins_pipe(ialu_reg);
6873 %}
6874
6875 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6876 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6877 ins_cost(140);
6878
6879 size(4);
6880 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6881 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6882 ins_pipe(ialu_imm);
6883 %}
6884
6885 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6886 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6887 ins_cost(140);
6888
6889 size(4);
6890 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6891 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6892 ins_pipe(ialu_imm);
6893 %}
6894
6895 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6896 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6897 ins_cost(150);
6898 size(4);
6899 format %{ "MOV$cmp $fcc,$src,$dst" %}
6900 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6901 ins_pipe(ialu_imm);
6902 %}
6903
6904 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6905 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6906 ins_cost(140);
6907 size(4);
6908 format %{ "MOV$cmp $fcc,$src,$dst" %}
6909 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6910 ins_pipe(ialu_imm);
6911 %}
6912
6913 // Conditional move
6914 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6915 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6916 ins_cost(150);
6917 opcode(0x101);
6918 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6919 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6920 ins_pipe(int_conditional_float_move);
6921 %}
6922
6923 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6924 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6925 ins_cost(150);
6926
6927 size(4);
6928 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6929 opcode(0x101);
6930 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6931 ins_pipe(int_conditional_float_move);
6932 %}
6933
6934 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6935 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6936 ins_cost(150);
6937
6938 size(4);
6939 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6940 opcode(0x101);
6941 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6942 ins_pipe(int_conditional_float_move);
6943 %}
6944
6945 // Conditional move,
6946 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6947 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6948 ins_cost(150);
6949 size(4);
6950 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6951 opcode(0x1);
6952 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6953 ins_pipe(int_conditional_double_move);
6954 %}
6955
6956 // Conditional move
6957 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6958 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6959 ins_cost(150);
6960 size(4);
6961 opcode(0x102);
6962 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6963 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6964 ins_pipe(int_conditional_double_move);
6965 %}
6966
6967 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6968 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6969 ins_cost(150);
6970
6971 size(4);
6972 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6973 opcode(0x102);
6974 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6975 ins_pipe(int_conditional_double_move);
6976 %}
6977
6978 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6979 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6980 ins_cost(150);
6981
6982 size(4);
6983 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6984 opcode(0x102);
6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6986 ins_pipe(int_conditional_double_move);
6987 %}
6988
6989 // Conditional move,
6990 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6991 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6992 ins_cost(150);
6993 size(4);
6994 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6995 opcode(0x2);
6996 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6997 ins_pipe(int_conditional_double_move);
6998 %}
6999
7000 // Conditional move
7001 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7002 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7003 ins_cost(150);
7004 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7005 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7006 ins_pipe(ialu_reg);
7007 %}
7008
7009 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7010 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7011 ins_cost(140);
7012 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7013 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7014 ins_pipe(ialu_imm);
7015 %}
7016
7017 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7018 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7019 ins_cost(150);
7020
7021 size(4);
7022 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7023 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7024 ins_pipe(ialu_reg);
7025 %}
7026
7027
7028 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7029 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7030 ins_cost(150);
7031
7032 size(4);
7033 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7034 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7035 ins_pipe(ialu_reg);
7036 %}
7037
7038
7039 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7040 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7041 ins_cost(150);
7042
7043 size(4);
7044 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7045 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7046 ins_pipe(ialu_reg);
7047 %}
7048
7049
7050
7051 //----------OS and Locking Instructions----------------------------------------
7052
7053 // This name is KNOWN by the ADLC and cannot be changed.
7054 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7055 // for this guy.
7056 instruct tlsLoadP(g2RegP dst) %{
7057 match(Set dst (ThreadLocal));
7058
7059 size(0);
7060 ins_cost(0);
7061 format %{ "# TLS is in G2" %}
7062 ins_encode( /*empty encoding*/ );
7063 ins_pipe(ialu_none);
7064 %}
7065
7066 instruct checkCastPP( iRegP dst ) %{
7067 match(Set dst (CheckCastPP dst));
7068
7069 size(0);
7070 format %{ "# checkcastPP of $dst" %}
7071 ins_encode( /*empty encoding*/ );
7072 ins_pipe(empty);
7073 %}
7074
7075
7076 instruct castPP( iRegP dst ) %{
7077 match(Set dst (CastPP dst));
7078 format %{ "# castPP of $dst" %}
7079 ins_encode( /*empty encoding*/ );
7080 ins_pipe(empty);
7081 %}
7082
7083 instruct castII( iRegI dst ) %{
7084 match(Set dst (CastII dst));
7085 format %{ "# castII of $dst" %}
7086 ins_encode( /*empty encoding*/ );
7087 ins_cost(0);
7088 ins_pipe(empty);
7089 %}
7090
7091 //----------Arithmetic Instructions--------------------------------------------
7092 // Addition Instructions
7093 // Register Addition
7094 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7095 match(Set dst (AddI src1 src2));
7096
7097 size(4);
7098 format %{ "ADD $src1,$src2,$dst" %}
7099 ins_encode %{
7100 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7101 %}
7102 ins_pipe(ialu_reg_reg);
7103 %}
7104
7105 // Immediate Addition
7106 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7107 match(Set dst (AddI src1 src2));
7108
7109 size(4);
7110 format %{ "ADD $src1,$src2,$dst" %}
7111 opcode(Assembler::add_op3, Assembler::arith_op);
7112 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7113 ins_pipe(ialu_reg_imm);
7114 %}
7115
7116 // Pointer Register Addition
7117 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7118 match(Set dst (AddP src1 src2));
7119
7120 size(4);
7121 format %{ "ADD $src1,$src2,$dst" %}
7122 opcode(Assembler::add_op3, Assembler::arith_op);
7123 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7124 ins_pipe(ialu_reg_reg);
7125 %}
7126
7127 // Pointer Immediate Addition
7128 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7129 match(Set dst (AddP src1 src2));
7130
7131 size(4);
7132 format %{ "ADD $src1,$src2,$dst" %}
7133 opcode(Assembler::add_op3, Assembler::arith_op);
7134 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7135 ins_pipe(ialu_reg_imm);
7136 %}
7137
7138 // Long Addition
7139 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7140 match(Set dst (AddL src1 src2));
7141
7142 size(4);
7143 format %{ "ADD $src1,$src2,$dst\t! long" %}
7144 opcode(Assembler::add_op3, Assembler::arith_op);
7145 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7146 ins_pipe(ialu_reg_reg);
7147 %}
7148
7149 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7150 match(Set dst (AddL src1 con));
7151
7152 size(4);
7153 format %{ "ADD $src1,$con,$dst" %}
7154 opcode(Assembler::add_op3, Assembler::arith_op);
7155 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7156 ins_pipe(ialu_reg_imm);
7157 %}
7158
7159 //----------Conditional_store--------------------------------------------------
7160 // Conditional-store of the updated heap-top.
7161 // Used during allocation of the shared heap.
7162 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7163
7164 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7165 instruct loadPLocked(iRegP dst, memory mem) %{
7166 match(Set dst (LoadPLocked mem));
7167 ins_cost(MEMORY_REF_COST);
7168
7169 #ifndef _LP64
7170 size(4);
7171 format %{ "LDUW $mem,$dst\t! ptr" %}
7172 opcode(Assembler::lduw_op3, 0, REGP_OP);
7173 #else
7174 format %{ "LDX $mem,$dst\t! ptr" %}
7175 opcode(Assembler::ldx_op3, 0, REGP_OP);
7176 #endif
7177 ins_encode( form3_mem_reg( mem, dst ) );
7178 ins_pipe(iload_mem);
7179 %}
7180
7181 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7182 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7183 effect( KILL newval );
7184 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7185 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7186 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7187 ins_pipe( long_memory_op );
7188 %}
7189
7190 // Conditional-store of an int value.
7191 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7192 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7193 effect( KILL newval );
7194 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7195 "CMP $oldval,$newval\t\t! See if we made progress" %}
7196 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7197 ins_pipe( long_memory_op );
7198 %}
7199
7200 // Conditional-store of a long value.
7201 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7202 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7203 effect( KILL newval );
7204 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7205 "CMP $oldval,$newval\t\t! See if we made progress" %}
7206 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7207 ins_pipe( long_memory_op );
7208 %}
7209
7210 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7211
7212 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7213 predicate(VM_Version::supports_cx8());
7214 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7215 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7216 format %{
7217 "MOV $newval,O7\n\t"
7218 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7219 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7220 "MOV 1,$res\n\t"
7221 "MOVne xcc,R_G0,$res"
7222 %}
7223 ins_encode( enc_casx(mem_ptr, oldval, newval),
7224 enc_lflags_ne_to_boolean(res) );
7225 ins_pipe( long_memory_op );
7226 %}
7227
7228
7229 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7230 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7231 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7232 format %{
7233 "MOV $newval,O7\n\t"
7234 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7235 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7236 "MOV 1,$res\n\t"
7237 "MOVne icc,R_G0,$res"
7238 %}
7239 ins_encode( enc_casi(mem_ptr, oldval, newval),
7240 enc_iflags_ne_to_boolean(res) );
7241 ins_pipe( long_memory_op );
7242 %}
7243
7244 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7245 #ifdef _LP64
7246 predicate(VM_Version::supports_cx8());
7247 #endif
7248 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7249 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7250 format %{
7251 "MOV $newval,O7\n\t"
7252 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7253 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7254 "MOV 1,$res\n\t"
7255 "MOVne xcc,R_G0,$res"
7256 %}
7257 #ifdef _LP64
7258 ins_encode( enc_casx(mem_ptr, oldval, newval),
7259 enc_lflags_ne_to_boolean(res) );
7260 #else
7261 ins_encode( enc_casi(mem_ptr, oldval, newval),
7262 enc_iflags_ne_to_boolean(res) );
7263 #endif
7264 ins_pipe( long_memory_op );
7265 %}
7266
7267 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7268 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7269 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7270 format %{
7271 "MOV $newval,O7\n\t"
7272 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7273 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7274 "MOV 1,$res\n\t"
7275 "MOVne icc,R_G0,$res"
7276 %}
7277 ins_encode( enc_casi(mem_ptr, oldval, newval),
7278 enc_iflags_ne_to_boolean(res) );
7279 ins_pipe( long_memory_op );
7280 %}
7281
7282 instruct xchgI( memory mem, iRegI newval) %{
7283 match(Set newval (GetAndSetI mem newval));
7284 format %{ "SWAP [$mem],$newval" %}
7285 size(4);
7286 ins_encode %{
7287 __ swap($mem$$Address, $newval$$Register);
7288 %}
7289 ins_pipe( long_memory_op );
7290 %}
7291
7292 #ifndef _LP64
7293 instruct xchgP( memory mem, iRegP newval) %{
7294 match(Set newval (GetAndSetP mem newval));
7295 format %{ "SWAP [$mem],$newval" %}
7296 size(4);
7297 ins_encode %{
7298 __ swap($mem$$Address, $newval$$Register);
7299 %}
7300 ins_pipe( long_memory_op );
7301 %}
7302 #endif
7303
7304 instruct xchgN( memory mem, iRegN newval) %{
7305 match(Set newval (GetAndSetN mem newval));
7306 format %{ "SWAP [$mem],$newval" %}
7307 size(4);
7308 ins_encode %{
7309 __ swap($mem$$Address, $newval$$Register);
7310 %}
7311 ins_pipe( long_memory_op );
7312 %}
7313
7314 //---------------------
7315 // Subtraction Instructions
7316 // Register Subtraction
7317 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7318 match(Set dst (SubI src1 src2));
7319
7320 size(4);
7321 format %{ "SUB $src1,$src2,$dst" %}
7322 opcode(Assembler::sub_op3, Assembler::arith_op);
7323 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7324 ins_pipe(ialu_reg_reg);
7325 %}
7326
7327 // Immediate Subtraction
7328 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7329 match(Set dst (SubI src1 src2));
7330
7331 size(4);
7332 format %{ "SUB $src1,$src2,$dst" %}
7333 opcode(Assembler::sub_op3, Assembler::arith_op);
7334 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7335 ins_pipe(ialu_reg_imm);
7336 %}
7337
7338 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7339 match(Set dst (SubI zero src2));
7340
7341 size(4);
7342 format %{ "NEG $src2,$dst" %}
7343 opcode(Assembler::sub_op3, Assembler::arith_op);
7344 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7345 ins_pipe(ialu_zero_reg);
7346 %}
7347
7348 // Long subtraction
7349 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7350 match(Set dst (SubL src1 src2));
7351
7352 size(4);
7353 format %{ "SUB $src1,$src2,$dst\t! long" %}
7354 opcode(Assembler::sub_op3, Assembler::arith_op);
7355 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7356 ins_pipe(ialu_reg_reg);
7357 %}
7358
7359 // Immediate Subtraction
7360 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7361 match(Set dst (SubL src1 con));
7362
7363 size(4);
7364 format %{ "SUB $src1,$con,$dst\t! long" %}
7365 opcode(Assembler::sub_op3, Assembler::arith_op);
7366 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7367 ins_pipe(ialu_reg_imm);
7368 %}
7369
7370 // Long negation
7371 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7372 match(Set dst (SubL zero src2));
7373
7374 size(4);
7375 format %{ "NEG $src2,$dst\t! long" %}
7376 opcode(Assembler::sub_op3, Assembler::arith_op);
7377 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7378 ins_pipe(ialu_zero_reg);
7379 %}
7380
7381 // Multiplication Instructions
7382 // Integer Multiplication
7383 // Register Multiplication
7384 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7385 match(Set dst (MulI src1 src2));
7386
7387 size(4);
7388 format %{ "MULX $src1,$src2,$dst" %}
7389 opcode(Assembler::mulx_op3, Assembler::arith_op);
7390 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7391 ins_pipe(imul_reg_reg);
7392 %}
7393
7394 // Immediate Multiplication
7395 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7396 match(Set dst (MulI src1 src2));
7397
7398 size(4);
7399 format %{ "MULX $src1,$src2,$dst" %}
7400 opcode(Assembler::mulx_op3, Assembler::arith_op);
7401 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7402 ins_pipe(imul_reg_imm);
7403 %}
7404
7405 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7406 match(Set dst (MulL src1 src2));
7407 ins_cost(DEFAULT_COST * 5);
7408 size(4);
7409 format %{ "MULX $src1,$src2,$dst\t! long" %}
7410 opcode(Assembler::mulx_op3, Assembler::arith_op);
7411 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7412 ins_pipe(mulL_reg_reg);
7413 %}
7414
7415 // Immediate Multiplication
7416 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7417 match(Set dst (MulL src1 src2));
7418 ins_cost(DEFAULT_COST * 5);
7419 size(4);
7420 format %{ "MULX $src1,$src2,$dst" %}
7421 opcode(Assembler::mulx_op3, Assembler::arith_op);
7422 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7423 ins_pipe(mulL_reg_imm);
7424 %}
7425
7426 // Integer Division
7427 // Register Division
7428 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7429 match(Set dst (DivI src1 src2));
7430 ins_cost((2+71)*DEFAULT_COST);
7431
7432 format %{ "SRA $src2,0,$src2\n\t"
7433 "SRA $src1,0,$src1\n\t"
7434 "SDIVX $src1,$src2,$dst" %}
7435 ins_encode( idiv_reg( src1, src2, dst ) );
7436 ins_pipe(sdiv_reg_reg);
7437 %}
7438
7439 // Immediate Division
7440 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7441 match(Set dst (DivI src1 src2));
7442 ins_cost((2+71)*DEFAULT_COST);
7443
7444 format %{ "SRA $src1,0,$src1\n\t"
7445 "SDIVX $src1,$src2,$dst" %}
7446 ins_encode( idiv_imm( src1, src2, dst ) );
7447 ins_pipe(sdiv_reg_imm);
7448 %}
7449
7450 //----------Div-By-10-Expansion------------------------------------------------
7451 // Extract hi bits of a 32x32->64 bit multiply.
7452 // Expand rule only, not matched
7453 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7454 effect( DEF dst, USE src1, USE src2 );
7455 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7456 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7457 ins_encode( enc_mul_hi(dst,src1,src2));
7458 ins_pipe(sdiv_reg_reg);
7459 %}
7460
7461 // Magic constant, reciprocal of 10
7462 instruct loadConI_x66666667(iRegIsafe dst) %{
7463 effect( DEF dst );
7464
7465 size(8);
7466 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7467 ins_encode( Set32(0x66666667, dst) );
7468 ins_pipe(ialu_hi_lo_reg);
7469 %}
7470
7471 // Register Shift Right Arithmetic Long by 32-63
7472 instruct sra_31( iRegI dst, iRegI src ) %{
7473 effect( DEF dst, USE src );
7474 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7475 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7476 ins_pipe(ialu_reg_reg);
7477 %}
7478
7479 // Arithmetic Shift Right by 8-bit immediate
7480 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7481 effect( DEF dst, USE src );
7482 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7483 opcode(Assembler::sra_op3, Assembler::arith_op);
7484 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7485 ins_pipe(ialu_reg_imm);
7486 %}
7487
7488 // Integer DIV with 10
7489 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7490 match(Set dst (DivI src div));
7491 ins_cost((6+6)*DEFAULT_COST);
7492 expand %{
7493 iRegIsafe tmp1; // Killed temps;
7494 iRegIsafe tmp2; // Killed temps;
7495 iRegI tmp3; // Killed temps;
7496 iRegI tmp4; // Killed temps;
7497 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7498 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7499 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7500 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7501 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7502 %}
7503 %}
7504
7505 // Register Long Division
7506 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7507 match(Set dst (DivL src1 src2));
7508 ins_cost(DEFAULT_COST*71);
7509 size(4);
7510 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7511 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7512 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7513 ins_pipe(divL_reg_reg);
7514 %}
7515
7516 // Register Long Division
7517 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7518 match(Set dst (DivL src1 src2));
7519 ins_cost(DEFAULT_COST*71);
7520 size(4);
7521 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7522 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7523 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7524 ins_pipe(divL_reg_imm);
7525 %}
7526
7527 // Integer Remainder
7528 // Register Remainder
7529 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7530 match(Set dst (ModI src1 src2));
7531 effect( KILL ccr, KILL temp);
7532
7533 format %{ "SREM $src1,$src2,$dst" %}
7534 ins_encode( irem_reg(src1, src2, dst, temp) );
7535 ins_pipe(sdiv_reg_reg);
7536 %}
7537
7538 // Immediate Remainder
7539 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7540 match(Set dst (ModI src1 src2));
7541 effect( KILL ccr, KILL temp);
7542
7543 format %{ "SREM $src1,$src2,$dst" %}
7544 ins_encode( irem_imm(src1, src2, dst, temp) );
7545 ins_pipe(sdiv_reg_imm);
7546 %}
7547
7548 // Register Long Remainder
7549 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7550 effect(DEF dst, USE src1, USE src2);
7551 size(4);
7552 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7553 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7554 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7555 ins_pipe(divL_reg_reg);
7556 %}
7557
7558 // Register Long Division
7559 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7560 effect(DEF dst, USE src1, USE src2);
7561 size(4);
7562 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7563 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7564 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7565 ins_pipe(divL_reg_imm);
7566 %}
7567
7568 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7569 effect(DEF dst, USE src1, USE src2);
7570 size(4);
7571 format %{ "MULX $src1,$src2,$dst\t! long" %}
7572 opcode(Assembler::mulx_op3, Assembler::arith_op);
7573 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7574 ins_pipe(mulL_reg_reg);
7575 %}
7576
7577 // Immediate Multiplication
7578 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7579 effect(DEF dst, USE src1, USE src2);
7580 size(4);
7581 format %{ "MULX $src1,$src2,$dst" %}
7582 opcode(Assembler::mulx_op3, Assembler::arith_op);
7583 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7584 ins_pipe(mulL_reg_imm);
7585 %}
7586
7587 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7588 effect(DEF dst, USE src1, USE src2);
7589 size(4);
7590 format %{ "SUB $src1,$src2,$dst\t! long" %}
7591 opcode(Assembler::sub_op3, Assembler::arith_op);
7592 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7593 ins_pipe(ialu_reg_reg);
7594 %}
7595
7596 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7597 effect(DEF dst, USE src1, USE src2);
7598 size(4);
7599 format %{ "SUB $src1,$src2,$dst\t! long" %}
7600 opcode(Assembler::sub_op3, Assembler::arith_op);
7601 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7602 ins_pipe(ialu_reg_reg);
7603 %}
7604
7605 // Register Long Remainder
7606 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7607 match(Set dst (ModL src1 src2));
7608 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7609 expand %{
7610 iRegL tmp1;
7611 iRegL tmp2;
7612 divL_reg_reg_1(tmp1, src1, src2);
7613 mulL_reg_reg_1(tmp2, tmp1, src2);
7614 subL_reg_reg_1(dst, src1, tmp2);
7615 %}
7616 %}
7617
7618 // Register Long Remainder
7619 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7620 match(Set dst (ModL src1 src2));
7621 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7622 expand %{
7623 iRegL tmp1;
7624 iRegL tmp2;
7625 divL_reg_imm13_1(tmp1, src1, src2);
7626 mulL_reg_imm13_1(tmp2, tmp1, src2);
7627 subL_reg_reg_2 (dst, src1, tmp2);
7628 %}
7629 %}
7630
7631 // Integer Shift Instructions
7632 // Register Shift Left
7633 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7634 match(Set dst (LShiftI src1 src2));
7635
7636 size(4);
7637 format %{ "SLL $src1,$src2,$dst" %}
7638 opcode(Assembler::sll_op3, Assembler::arith_op);
7639 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7640 ins_pipe(ialu_reg_reg);
7641 %}
7642
7643 // Register Shift Left Immediate
7644 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7645 match(Set dst (LShiftI src1 src2));
7646
7647 size(4);
7648 format %{ "SLL $src1,$src2,$dst" %}
7649 opcode(Assembler::sll_op3, Assembler::arith_op);
7650 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7651 ins_pipe(ialu_reg_imm);
7652 %}
7653
7654 // Register Shift Left
7655 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7656 match(Set dst (LShiftL src1 src2));
7657
7658 size(4);
7659 format %{ "SLLX $src1,$src2,$dst" %}
7660 opcode(Assembler::sllx_op3, Assembler::arith_op);
7661 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7662 ins_pipe(ialu_reg_reg);
7663 %}
7664
7665 // Register Shift Left Immediate
7666 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7667 match(Set dst (LShiftL src1 src2));
7668
7669 size(4);
7670 format %{ "SLLX $src1,$src2,$dst" %}
7671 opcode(Assembler::sllx_op3, Assembler::arith_op);
7672 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7673 ins_pipe(ialu_reg_imm);
7674 %}
7675
7676 // Register Arithmetic Shift Right
7677 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7678 match(Set dst (RShiftI src1 src2));
7679 size(4);
7680 format %{ "SRA $src1,$src2,$dst" %}
7681 opcode(Assembler::sra_op3, Assembler::arith_op);
7682 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7683 ins_pipe(ialu_reg_reg);
7684 %}
7685
7686 // Register Arithmetic Shift Right Immediate
7687 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7688 match(Set dst (RShiftI src1 src2));
7689
7690 size(4);
7691 format %{ "SRA $src1,$src2,$dst" %}
7692 opcode(Assembler::sra_op3, Assembler::arith_op);
7693 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7694 ins_pipe(ialu_reg_imm);
7695 %}
7696
7697 // Register Shift Right Arithmatic Long
7698 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7699 match(Set dst (RShiftL src1 src2));
7700
7701 size(4);
7702 format %{ "SRAX $src1,$src2,$dst" %}
7703 opcode(Assembler::srax_op3, Assembler::arith_op);
7704 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7705 ins_pipe(ialu_reg_reg);
7706 %}
7707
7708 // Register Shift Left Immediate
7709 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7710 match(Set dst (RShiftL src1 src2));
7711
7712 size(4);
7713 format %{ "SRAX $src1,$src2,$dst" %}
7714 opcode(Assembler::srax_op3, Assembler::arith_op);
7715 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7716 ins_pipe(ialu_reg_imm);
7717 %}
7718
7719 // Register Shift Right
7720 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7721 match(Set dst (URShiftI src1 src2));
7722
7723 size(4);
7724 format %{ "SRL $src1,$src2,$dst" %}
7725 opcode(Assembler::srl_op3, Assembler::arith_op);
7726 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7727 ins_pipe(ialu_reg_reg);
7728 %}
7729
7730 // Register Shift Right Immediate
7731 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7732 match(Set dst (URShiftI src1 src2));
7733
7734 size(4);
7735 format %{ "SRL $src1,$src2,$dst" %}
7736 opcode(Assembler::srl_op3, Assembler::arith_op);
7737 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7738 ins_pipe(ialu_reg_imm);
7739 %}
7740
7741 // Register Shift Right
7742 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7743 match(Set dst (URShiftL src1 src2));
7744
7745 size(4);
7746 format %{ "SRLX $src1,$src2,$dst" %}
7747 opcode(Assembler::srlx_op3, Assembler::arith_op);
7748 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7749 ins_pipe(ialu_reg_reg);
7750 %}
7751
7752 // Register Shift Right Immediate
7753 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7754 match(Set dst (URShiftL src1 src2));
7755
7756 size(4);
7757 format %{ "SRLX $src1,$src2,$dst" %}
7758 opcode(Assembler::srlx_op3, Assembler::arith_op);
7759 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7760 ins_pipe(ialu_reg_imm);
7761 %}
7762
7763 // Register Shift Right Immediate with a CastP2X
7764 #ifdef _LP64
7765 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7766 match(Set dst (URShiftL (CastP2X src1) src2));
7767 size(4);
7768 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7769 opcode(Assembler::srlx_op3, Assembler::arith_op);
7770 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7771 ins_pipe(ialu_reg_imm);
7772 %}
7773 #else
7774 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7775 match(Set dst (URShiftI (CastP2X src1) src2));
7776 size(4);
7777 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7778 opcode(Assembler::srl_op3, Assembler::arith_op);
7779 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7780 ins_pipe(ialu_reg_imm);
7781 %}
7782 #endif
7783
7784
7785 //----------Floating Point Arithmetic Instructions-----------------------------
7786
7787 // Add float single precision
7788 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7789 match(Set dst (AddF src1 src2));
7790
7791 size(4);
7792 format %{ "FADDS $src1,$src2,$dst" %}
7793 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7794 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7795 ins_pipe(faddF_reg_reg);
7796 %}
7797
7798 // Add float double precision
7799 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7800 match(Set dst (AddD src1 src2));
7801
7802 size(4);
7803 format %{ "FADDD $src1,$src2,$dst" %}
7804 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7805 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7806 ins_pipe(faddD_reg_reg);
7807 %}
7808
7809 // Sub float single precision
7810 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7811 match(Set dst (SubF src1 src2));
7812
7813 size(4);
7814 format %{ "FSUBS $src1,$src2,$dst" %}
7815 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7816 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7817 ins_pipe(faddF_reg_reg);
7818 %}
7819
7820 // Sub float double precision
7821 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7822 match(Set dst (SubD src1 src2));
7823
7824 size(4);
7825 format %{ "FSUBD $src1,$src2,$dst" %}
7826 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7827 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7828 ins_pipe(faddD_reg_reg);
7829 %}
7830
7831 // Mul float single precision
7832 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7833 match(Set dst (MulF src1 src2));
7834
7835 size(4);
7836 format %{ "FMULS $src1,$src2,$dst" %}
7837 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7838 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7839 ins_pipe(fmulF_reg_reg);
7840 %}
7841
7842 // Mul float double precision
7843 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7844 match(Set dst (MulD src1 src2));
7845
7846 size(4);
7847 format %{ "FMULD $src1,$src2,$dst" %}
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7849 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7850 ins_pipe(fmulD_reg_reg);
7851 %}
7852
7853 // Div float single precision
7854 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7855 match(Set dst (DivF src1 src2));
7856
7857 size(4);
7858 format %{ "FDIVS $src1,$src2,$dst" %}
7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7860 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7861 ins_pipe(fdivF_reg_reg);
7862 %}
7863
7864 // Div float double precision
7865 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7866 match(Set dst (DivD src1 src2));
7867
7868 size(4);
7869 format %{ "FDIVD $src1,$src2,$dst" %}
7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7871 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7872 ins_pipe(fdivD_reg_reg);
7873 %}
7874
7875 // Absolute float double precision
7876 instruct absD_reg(regD dst, regD src) %{
7877 match(Set dst (AbsD src));
7878
7879 format %{ "FABSd $src,$dst" %}
7880 ins_encode(fabsd(dst, src));
7881 ins_pipe(faddD_reg);
7882 %}
7883
7884 // Absolute float single precision
7885 instruct absF_reg(regF dst, regF src) %{
7886 match(Set dst (AbsF src));
7887
7888 format %{ "FABSs $src,$dst" %}
7889 ins_encode(fabss(dst, src));
7890 ins_pipe(faddF_reg);
7891 %}
7892
7893 instruct negF_reg(regF dst, regF src) %{
7894 match(Set dst (NegF src));
7895
7896 size(4);
7897 format %{ "FNEGs $src,$dst" %}
7898 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7899 ins_encode(form3_opf_rs2F_rdF(src, dst));
7900 ins_pipe(faddF_reg);
7901 %}
7902
7903 instruct negD_reg(regD dst, regD src) %{
7904 match(Set dst (NegD src));
7905
7906 format %{ "FNEGd $src,$dst" %}
7907 ins_encode(fnegd(dst, src));
7908 ins_pipe(faddD_reg);
7909 %}
7910
7911 // Sqrt float double precision
7912 instruct sqrtF_reg_reg(regF dst, regF src) %{
7913 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7914
7915 size(4);
7916 format %{ "FSQRTS $src,$dst" %}
7917 ins_encode(fsqrts(dst, src));
7918 ins_pipe(fdivF_reg_reg);
7919 %}
7920
7921 // Sqrt float double precision
7922 instruct sqrtD_reg_reg(regD dst, regD src) %{
7923 match(Set dst (SqrtD src));
7924
7925 size(4);
7926 format %{ "FSQRTD $src,$dst" %}
7927 ins_encode(fsqrtd(dst, src));
7928 ins_pipe(fdivD_reg_reg);
7929 %}
7930
7931 //----------Logical Instructions-----------------------------------------------
7932 // And Instructions
7933 // Register And
7934 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7935 match(Set dst (AndI src1 src2));
7936
7937 size(4);
7938 format %{ "AND $src1,$src2,$dst" %}
7939 opcode(Assembler::and_op3, Assembler::arith_op);
7940 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7941 ins_pipe(ialu_reg_reg);
7942 %}
7943
7944 // Immediate And
7945 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7946 match(Set dst (AndI src1 src2));
7947
7948 size(4);
7949 format %{ "AND $src1,$src2,$dst" %}
7950 opcode(Assembler::and_op3, Assembler::arith_op);
7951 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7952 ins_pipe(ialu_reg_imm);
7953 %}
7954
7955 // Register And Long
7956 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7957 match(Set dst (AndL src1 src2));
7958
7959 ins_cost(DEFAULT_COST);
7960 size(4);
7961 format %{ "AND $src1,$src2,$dst\t! long" %}
7962 opcode(Assembler::and_op3, Assembler::arith_op);
7963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7964 ins_pipe(ialu_reg_reg);
7965 %}
7966
7967 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7968 match(Set dst (AndL src1 con));
7969
7970 ins_cost(DEFAULT_COST);
7971 size(4);
7972 format %{ "AND $src1,$con,$dst\t! long" %}
7973 opcode(Assembler::and_op3, Assembler::arith_op);
7974 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7975 ins_pipe(ialu_reg_imm);
7976 %}
7977
7978 // Or Instructions
7979 // Register Or
7980 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7981 match(Set dst (OrI src1 src2));
7982
7983 size(4);
7984 format %{ "OR $src1,$src2,$dst" %}
7985 opcode(Assembler::or_op3, Assembler::arith_op);
7986 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7987 ins_pipe(ialu_reg_reg);
7988 %}
7989
7990 // Immediate Or
7991 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7992 match(Set dst (OrI src1 src2));
7993
7994 size(4);
7995 format %{ "OR $src1,$src2,$dst" %}
7996 opcode(Assembler::or_op3, Assembler::arith_op);
7997 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7998 ins_pipe(ialu_reg_imm);
7999 %}
8000
8001 // Register Or Long
8002 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8003 match(Set dst (OrL src1 src2));
8004
8005 ins_cost(DEFAULT_COST);
8006 size(4);
8007 format %{ "OR $src1,$src2,$dst\t! long" %}
8008 opcode(Assembler::or_op3, Assembler::arith_op);
8009 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8010 ins_pipe(ialu_reg_reg);
8011 %}
8012
8013 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8014 match(Set dst (OrL src1 con));
8015 ins_cost(DEFAULT_COST*2);
8016
8017 ins_cost(DEFAULT_COST);
8018 size(4);
8019 format %{ "OR $src1,$con,$dst\t! long" %}
8020 opcode(Assembler::or_op3, Assembler::arith_op);
8021 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8022 ins_pipe(ialu_reg_imm);
8023 %}
8024
8025 #ifndef _LP64
8026
8027 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8028 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8029 match(Set dst (OrI src1 (CastP2X src2)));
8030
8031 size(4);
8032 format %{ "OR $src1,$src2,$dst" %}
8033 opcode(Assembler::or_op3, Assembler::arith_op);
8034 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8035 ins_pipe(ialu_reg_reg);
8036 %}
8037
8038 #else
8039
8040 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8041 match(Set dst (OrL src1 (CastP2X src2)));
8042
8043 ins_cost(DEFAULT_COST);
8044 size(4);
8045 format %{ "OR $src1,$src2,$dst\t! long" %}
8046 opcode(Assembler::or_op3, Assembler::arith_op);
8047 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8048 ins_pipe(ialu_reg_reg);
8049 %}
8050
8051 #endif
8052
8053 // Xor Instructions
8054 // Register Xor
8055 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8056 match(Set dst (XorI src1 src2));
8057
8058 size(4);
8059 format %{ "XOR $src1,$src2,$dst" %}
8060 opcode(Assembler::xor_op3, Assembler::arith_op);
8061 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8062 ins_pipe(ialu_reg_reg);
8063 %}
8064
8065 // Immediate Xor
8066 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8067 match(Set dst (XorI src1 src2));
8068
8069 size(4);
8070 format %{ "XOR $src1,$src2,$dst" %}
8071 opcode(Assembler::xor_op3, Assembler::arith_op);
8072 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8073 ins_pipe(ialu_reg_imm);
8074 %}
8075
8076 // Register Xor Long
8077 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8078 match(Set dst (XorL src1 src2));
8079
8080 ins_cost(DEFAULT_COST);
8081 size(4);
8082 format %{ "XOR $src1,$src2,$dst\t! long" %}
8083 opcode(Assembler::xor_op3, Assembler::arith_op);
8084 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8085 ins_pipe(ialu_reg_reg);
8086 %}
8087
8088 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8089 match(Set dst (XorL src1 con));
8090
8091 ins_cost(DEFAULT_COST);
8092 size(4);
8093 format %{ "XOR $src1,$con,$dst\t! long" %}
8094 opcode(Assembler::xor_op3, Assembler::arith_op);
8095 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8096 ins_pipe(ialu_reg_imm);
8097 %}
8098
8099 //----------Convert to Boolean-------------------------------------------------
8100 // Nice hack for 32-bit tests but doesn't work for
8101 // 64-bit pointers.
8102 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8103 match(Set dst (Conv2B src));
8104 effect( KILL ccr );
8105 ins_cost(DEFAULT_COST*2);
8106 format %{ "CMP R_G0,$src\n\t"
8107 "ADDX R_G0,0,$dst" %}
8108 ins_encode( enc_to_bool( src, dst ) );
8109 ins_pipe(ialu_reg_ialu);
8110 %}
8111
8112 #ifndef _LP64
8113 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8114 match(Set dst (Conv2B src));
8115 effect( KILL ccr );
8116 ins_cost(DEFAULT_COST*2);
8117 format %{ "CMP R_G0,$src\n\t"
8118 "ADDX R_G0,0,$dst" %}
8119 ins_encode( enc_to_bool( src, dst ) );
8120 ins_pipe(ialu_reg_ialu);
8121 %}
8122 #else
8123 instruct convP2B( iRegI dst, iRegP src ) %{
8124 match(Set dst (Conv2B src));
8125 ins_cost(DEFAULT_COST*2);
8126 format %{ "MOV $src,$dst\n\t"
8127 "MOVRNZ $src,1,$dst" %}
8128 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8129 ins_pipe(ialu_clr_and_mover);
8130 %}
8131 #endif
8132
8133 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8134 match(Set dst (CmpLTMask src zero));
8135 effect(KILL ccr);
8136 size(4);
8137 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8138 ins_encode %{
8139 __ sra($src$$Register, 31, $dst$$Register);
8140 %}
8141 ins_pipe(ialu_reg_imm);
8142 %}
8143
8144 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8145 match(Set dst (CmpLTMask p q));
8146 effect( KILL ccr );
8147 ins_cost(DEFAULT_COST*4);
8148 format %{ "CMP $p,$q\n\t"
8149 "MOV #0,$dst\n\t"
8150 "BLT,a .+8\n\t"
8151 "MOV #-1,$dst" %}
8152 ins_encode( enc_ltmask(p,q,dst) );
8153 ins_pipe(ialu_reg_reg_ialu);
8154 %}
8155
8156 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8157 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8158 effect(KILL ccr, TEMP tmp);
8159 ins_cost(DEFAULT_COST*3);
8160
8161 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8162 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8163 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8164 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8165 ins_pipe( cadd_cmpltmask );
8166 %}
8167
8168
8169 //-----------------------------------------------------------------
8170 // Direct raw moves between float and general registers using VIS3.
8171
8172 // ins_pipe(faddF_reg);
8173 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8174 predicate(UseVIS >= 3);
8175 match(Set dst (MoveF2I src));
8176
8177 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8178 ins_encode %{
8179 __ movstouw($src$$FloatRegister, $dst$$Register);
8180 %}
8181 ins_pipe(ialu_reg_reg);
8182 %}
8183
8184 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8185 predicate(UseVIS >= 3);
8186 match(Set dst (MoveI2F src));
8187
8188 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8189 ins_encode %{
8190 __ movwtos($src$$Register, $dst$$FloatRegister);
8191 %}
8192 ins_pipe(ialu_reg_reg);
8193 %}
8194
8195 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8196 predicate(UseVIS >= 3);
8197 match(Set dst (MoveD2L src));
8198
8199 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8200 ins_encode %{
8201 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8202 %}
8203 ins_pipe(ialu_reg_reg);
8204 %}
8205
8206 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8207 predicate(UseVIS >= 3);
8208 match(Set dst (MoveL2D src));
8209
8210 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8211 ins_encode %{
8212 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8213 %}
8214 ins_pipe(ialu_reg_reg);
8215 %}
8216
8217
8218 // Raw moves between float and general registers using stack.
8219
8220 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8221 match(Set dst (MoveF2I src));
8222 effect(DEF dst, USE src);
8223 ins_cost(MEMORY_REF_COST);
8224
8225 size(4);
8226 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8227 opcode(Assembler::lduw_op3);
8228 ins_encode(simple_form3_mem_reg( src, dst ) );
8229 ins_pipe(iload_mem);
8230 %}
8231
8232 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8233 match(Set dst (MoveI2F src));
8234 effect(DEF dst, USE src);
8235 ins_cost(MEMORY_REF_COST);
8236
8237 size(4);
8238 format %{ "LDF $src,$dst\t! MoveI2F" %}
8239 opcode(Assembler::ldf_op3);
8240 ins_encode(simple_form3_mem_reg(src, dst));
8241 ins_pipe(floadF_stk);
8242 %}
8243
8244 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8245 match(Set dst (MoveD2L src));
8246 effect(DEF dst, USE src);
8247 ins_cost(MEMORY_REF_COST);
8248
8249 size(4);
8250 format %{ "LDX $src,$dst\t! MoveD2L" %}
8251 opcode(Assembler::ldx_op3);
8252 ins_encode(simple_form3_mem_reg( src, dst ) );
8253 ins_pipe(iload_mem);
8254 %}
8255
8256 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8257 match(Set dst (MoveL2D src));
8258 effect(DEF dst, USE src);
8259 ins_cost(MEMORY_REF_COST);
8260
8261 size(4);
8262 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8263 opcode(Assembler::lddf_op3);
8264 ins_encode(simple_form3_mem_reg(src, dst));
8265 ins_pipe(floadD_stk);
8266 %}
8267
8268 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8269 match(Set dst (MoveF2I src));
8270 effect(DEF dst, USE src);
8271 ins_cost(MEMORY_REF_COST);
8272
8273 size(4);
8274 format %{ "STF $src,$dst\t! MoveF2I" %}
8275 opcode(Assembler::stf_op3);
8276 ins_encode(simple_form3_mem_reg(dst, src));
8277 ins_pipe(fstoreF_stk_reg);
8278 %}
8279
8280 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8281 match(Set dst (MoveI2F src));
8282 effect(DEF dst, USE src);
8283 ins_cost(MEMORY_REF_COST);
8284
8285 size(4);
8286 format %{ "STW $src,$dst\t! MoveI2F" %}
8287 opcode(Assembler::stw_op3);
8288 ins_encode(simple_form3_mem_reg( dst, src ) );
8289 ins_pipe(istore_mem_reg);
8290 %}
8291
8292 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8293 match(Set dst (MoveD2L src));
8294 effect(DEF dst, USE src);
8295 ins_cost(MEMORY_REF_COST);
8296
8297 size(4);
8298 format %{ "STDF $src,$dst\t! MoveD2L" %}
8299 opcode(Assembler::stdf_op3);
8300 ins_encode(simple_form3_mem_reg(dst, src));
8301 ins_pipe(fstoreD_stk_reg);
8302 %}
8303
8304 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8305 match(Set dst (MoveL2D src));
8306 effect(DEF dst, USE src);
8307 ins_cost(MEMORY_REF_COST);
8308
8309 size(4);
8310 format %{ "STX $src,$dst\t! MoveL2D" %}
8311 opcode(Assembler::stx_op3);
8312 ins_encode(simple_form3_mem_reg( dst, src ) );
8313 ins_pipe(istore_mem_reg);
8314 %}
8315
8316
8317 //----------Arithmetic Conversion Instructions---------------------------------
8318 // The conversions operations are all Alpha sorted. Please keep it that way!
8319
8320 instruct convD2F_reg(regF dst, regD src) %{
8321 match(Set dst (ConvD2F src));
8322 size(4);
8323 format %{ "FDTOS $src,$dst" %}
8324 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8325 ins_encode(form3_opf_rs2D_rdF(src, dst));
8326 ins_pipe(fcvtD2F);
8327 %}
8328
8329
8330 // Convert a double to an int in a float register.
8331 // If the double is a NAN, stuff a zero in instead.
8332 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8333 effect(DEF dst, USE src, KILL fcc0);
8334 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8335 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8336 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8337 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8338 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8339 "skip:" %}
8340 ins_encode(form_d2i_helper(src,dst));
8341 ins_pipe(fcvtD2I);
8342 %}
8343
8344 instruct convD2I_stk(stackSlotI dst, regD src) %{
8345 match(Set dst (ConvD2I src));
8346 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8347 expand %{
8348 regF tmp;
8349 convD2I_helper(tmp, src);
8350 regF_to_stkI(dst, tmp);
8351 %}
8352 %}
8353
8354 instruct convD2I_reg(iRegI dst, regD src) %{
8355 predicate(UseVIS >= 3);
8356 match(Set dst (ConvD2I src));
8357 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8358 expand %{
8359 regF tmp;
8360 convD2I_helper(tmp, src);
8361 MoveF2I_reg_reg(dst, tmp);
8362 %}
8363 %}
8364
8365
8366 // Convert a double to a long in a double register.
8367 // If the double is a NAN, stuff a zero in instead.
8368 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8369 effect(DEF dst, USE src, KILL fcc0);
8370 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8371 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8372 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8373 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8374 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8375 "skip:" %}
8376 ins_encode(form_d2l_helper(src,dst));
8377 ins_pipe(fcvtD2L);
8378 %}
8379
8380 instruct convD2L_stk(stackSlotL dst, regD src) %{
8381 match(Set dst (ConvD2L src));
8382 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8383 expand %{
8384 regD tmp;
8385 convD2L_helper(tmp, src);
8386 regD_to_stkL(dst, tmp);
8387 %}
8388 %}
8389
8390 instruct convD2L_reg(iRegL dst, regD src) %{
8391 predicate(UseVIS >= 3);
8392 match(Set dst (ConvD2L src));
8393 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8394 expand %{
8395 regD tmp;
8396 convD2L_helper(tmp, src);
8397 MoveD2L_reg_reg(dst, tmp);
8398 %}
8399 %}
8400
8401
8402 instruct convF2D_reg(regD dst, regF src) %{
8403 match(Set dst (ConvF2D src));
8404 format %{ "FSTOD $src,$dst" %}
8405 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8406 ins_encode(form3_opf_rs2F_rdD(src, dst));
8407 ins_pipe(fcvtF2D);
8408 %}
8409
8410
8411 // Convert a float to an int in a float register.
8412 // If the float is a NAN, stuff a zero in instead.
8413 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8414 effect(DEF dst, USE src, KILL fcc0);
8415 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8416 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8417 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8418 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8419 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8420 "skip:" %}
8421 ins_encode(form_f2i_helper(src,dst));
8422 ins_pipe(fcvtF2I);
8423 %}
8424
8425 instruct convF2I_stk(stackSlotI dst, regF src) %{
8426 match(Set dst (ConvF2I src));
8427 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8428 expand %{
8429 regF tmp;
8430 convF2I_helper(tmp, src);
8431 regF_to_stkI(dst, tmp);
8432 %}
8433 %}
8434
8435 instruct convF2I_reg(iRegI dst, regF src) %{
8436 predicate(UseVIS >= 3);
8437 match(Set dst (ConvF2I src));
8438 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8439 expand %{
8440 regF tmp;
8441 convF2I_helper(tmp, src);
8442 MoveF2I_reg_reg(dst, tmp);
8443 %}
8444 %}
8445
8446
8447 // Convert a float to a long in a float register.
8448 // If the float is a NAN, stuff a zero in instead.
8449 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8450 effect(DEF dst, USE src, KILL fcc0);
8451 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8452 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8453 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8454 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8455 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8456 "skip:" %}
8457 ins_encode(form_f2l_helper(src,dst));
8458 ins_pipe(fcvtF2L);
8459 %}
8460
8461 instruct convF2L_stk(stackSlotL dst, regF src) %{
8462 match(Set dst (ConvF2L src));
8463 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8464 expand %{
8465 regD tmp;
8466 convF2L_helper(tmp, src);
8467 regD_to_stkL(dst, tmp);
8468 %}
8469 %}
8470
8471 instruct convF2L_reg(iRegL dst, regF src) %{
8472 predicate(UseVIS >= 3);
8473 match(Set dst (ConvF2L src));
8474 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8475 expand %{
8476 regD tmp;
8477 convF2L_helper(tmp, src);
8478 MoveD2L_reg_reg(dst, tmp);
8479 %}
8480 %}
8481
8482
8483 instruct convI2D_helper(regD dst, regF tmp) %{
8484 effect(USE tmp, DEF dst);
8485 format %{ "FITOD $tmp,$dst" %}
8486 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8487 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8488 ins_pipe(fcvtI2D);
8489 %}
8490
8491 instruct convI2D_stk(stackSlotI src, regD dst) %{
8492 match(Set dst (ConvI2D src));
8493 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8494 expand %{
8495 regF tmp;
8496 stkI_to_regF(tmp, src);
8497 convI2D_helper(dst, tmp);
8498 %}
8499 %}
8500
8501 instruct convI2D_reg(regD_low dst, iRegI src) %{
8502 predicate(UseVIS >= 3);
8503 match(Set dst (ConvI2D src));
8504 expand %{
8505 regF tmp;
8506 MoveI2F_reg_reg(tmp, src);
8507 convI2D_helper(dst, tmp);
8508 %}
8509 %}
8510
8511 instruct convI2D_mem(regD_low dst, memory mem) %{
8512 match(Set dst (ConvI2D (LoadI mem)));
8513 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8514 size(8);
8515 format %{ "LDF $mem,$dst\n\t"
8516 "FITOD $dst,$dst" %}
8517 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8518 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8519 ins_pipe(floadF_mem);
8520 %}
8521
8522
8523 instruct convI2F_helper(regF dst, regF tmp) %{
8524 effect(DEF dst, USE tmp);
8525 format %{ "FITOS $tmp,$dst" %}
8526 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8527 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8528 ins_pipe(fcvtI2F);
8529 %}
8530
8531 instruct convI2F_stk(regF dst, stackSlotI src) %{
8532 match(Set dst (ConvI2F src));
8533 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8534 expand %{
8535 regF tmp;
8536 stkI_to_regF(tmp,src);
8537 convI2F_helper(dst, tmp);
8538 %}
8539 %}
8540
8541 instruct convI2F_reg(regF dst, iRegI src) %{
8542 predicate(UseVIS >= 3);
8543 match(Set dst (ConvI2F src));
8544 ins_cost(DEFAULT_COST);
8545 expand %{
8546 regF tmp;
8547 MoveI2F_reg_reg(tmp, src);
8548 convI2F_helper(dst, tmp);
8549 %}
8550 %}
8551
8552 instruct convI2F_mem( regF dst, memory mem ) %{
8553 match(Set dst (ConvI2F (LoadI mem)));
8554 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8555 size(8);
8556 format %{ "LDF $mem,$dst\n\t"
8557 "FITOS $dst,$dst" %}
8558 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8559 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8560 ins_pipe(floadF_mem);
8561 %}
8562
8563
8564 instruct convI2L_reg(iRegL dst, iRegI src) %{
8565 match(Set dst (ConvI2L src));
8566 size(4);
8567 format %{ "SRA $src,0,$dst\t! int->long" %}
8568 opcode(Assembler::sra_op3, Assembler::arith_op);
8569 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8570 ins_pipe(ialu_reg_reg);
8571 %}
8572
8573 // Zero-extend convert int to long
8574 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8575 match(Set dst (AndL (ConvI2L src) mask) );
8576 size(4);
8577 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8578 opcode(Assembler::srl_op3, Assembler::arith_op);
8579 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8580 ins_pipe(ialu_reg_reg);
8581 %}
8582
8583 // Zero-extend long
8584 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8585 match(Set dst (AndL src mask) );
8586 size(4);
8587 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8588 opcode(Assembler::srl_op3, Assembler::arith_op);
8589 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8590 ins_pipe(ialu_reg_reg);
8591 %}
8592
8593
8594 //-----------
8595 // Long to Double conversion using V8 opcodes.
8596 // Still useful because cheetah traps and becomes
8597 // amazingly slow for some common numbers.
8598
8599 // Magic constant, 0x43300000
8600 instruct loadConI_x43300000(iRegI dst) %{
8601 effect(DEF dst);
8602 size(4);
8603 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8604 ins_encode(SetHi22(0x43300000, dst));
8605 ins_pipe(ialu_none);
8606 %}
8607
8608 // Magic constant, 0x41f00000
8609 instruct loadConI_x41f00000(iRegI dst) %{
8610 effect(DEF dst);
8611 size(4);
8612 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8613 ins_encode(SetHi22(0x41f00000, dst));
8614 ins_pipe(ialu_none);
8615 %}
8616
8617 // Construct a double from two float halves
8618 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8619 effect(DEF dst, USE src1, USE src2);
8620 size(8);
8621 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8622 "FMOVS $src2.lo,$dst.lo" %}
8623 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8624 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8625 ins_pipe(faddD_reg_reg);
8626 %}
8627
8628 // Convert integer in high half of a double register (in the lower half of
8629 // the double register file) to double
8630 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8631 effect(DEF dst, USE src);
8632 size(4);
8633 format %{ "FITOD $src,$dst" %}
8634 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8635 ins_encode(form3_opf_rs2D_rdD(src, dst));
8636 ins_pipe(fcvtLHi2D);
8637 %}
8638
8639 // Add float double precision
8640 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8641 effect(DEF dst, USE src1, USE src2);
8642 size(4);
8643 format %{ "FADDD $src1,$src2,$dst" %}
8644 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8645 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8646 ins_pipe(faddD_reg_reg);
8647 %}
8648
8649 // Sub float double precision
8650 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8651 effect(DEF dst, USE src1, USE src2);
8652 size(4);
8653 format %{ "FSUBD $src1,$src2,$dst" %}
8654 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8655 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8656 ins_pipe(faddD_reg_reg);
8657 %}
8658
8659 // Mul float double precision
8660 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8661 effect(DEF dst, USE src1, USE src2);
8662 size(4);
8663 format %{ "FMULD $src1,$src2,$dst" %}
8664 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8665 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8666 ins_pipe(fmulD_reg_reg);
8667 %}
8668
8669 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8670 match(Set dst (ConvL2D src));
8671 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8672
8673 expand %{
8674 regD_low tmpsrc;
8675 iRegI ix43300000;
8676 iRegI ix41f00000;
8677 stackSlotL lx43300000;
8678 stackSlotL lx41f00000;
8679 regD_low dx43300000;
8680 regD dx41f00000;
8681 regD tmp1;
8682 regD_low tmp2;
8683 regD tmp3;
8684 regD tmp4;
8685
8686 stkL_to_regD(tmpsrc, src);
8687
8688 loadConI_x43300000(ix43300000);
8689 loadConI_x41f00000(ix41f00000);
8690 regI_to_stkLHi(lx43300000, ix43300000);
8691 regI_to_stkLHi(lx41f00000, ix41f00000);
8692 stkL_to_regD(dx43300000, lx43300000);
8693 stkL_to_regD(dx41f00000, lx41f00000);
8694
8695 convI2D_regDHi_regD(tmp1, tmpsrc);
8696 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8697 subD_regD_regD(tmp3, tmp2, dx43300000);
8698 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8699 addD_regD_regD(dst, tmp3, tmp4);
8700 %}
8701 %}
8702
8703 // Long to Double conversion using fast fxtof
8704 instruct convL2D_helper(regD dst, regD tmp) %{
8705 effect(DEF dst, USE tmp);
8706 size(4);
8707 format %{ "FXTOD $tmp,$dst" %}
8708 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8709 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8710 ins_pipe(fcvtL2D);
8711 %}
8712
8713 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8714 predicate(VM_Version::has_fast_fxtof());
8715 match(Set dst (ConvL2D src));
8716 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8717 expand %{
8718 regD tmp;
8719 stkL_to_regD(tmp, src);
8720 convL2D_helper(dst, tmp);
8721 %}
8722 %}
8723
8724 instruct convL2D_reg(regD dst, iRegL src) %{
8725 predicate(UseVIS >= 3);
8726 match(Set dst (ConvL2D src));
8727 expand %{
8728 regD tmp;
8729 MoveL2D_reg_reg(tmp, src);
8730 convL2D_helper(dst, tmp);
8731 %}
8732 %}
8733
8734 // Long to Float conversion using fast fxtof
8735 instruct convL2F_helper(regF dst, regD tmp) %{
8736 effect(DEF dst, USE tmp);
8737 size(4);
8738 format %{ "FXTOS $tmp,$dst" %}
8739 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8740 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8741 ins_pipe(fcvtL2F);
8742 %}
8743
8744 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8745 match(Set dst (ConvL2F src));
8746 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8747 expand %{
8748 regD tmp;
8749 stkL_to_regD(tmp, src);
8750 convL2F_helper(dst, tmp);
8751 %}
8752 %}
8753
8754 instruct convL2F_reg(regF dst, iRegL src) %{
8755 predicate(UseVIS >= 3);
8756 match(Set dst (ConvL2F src));
8757 ins_cost(DEFAULT_COST);
8758 expand %{
8759 regD tmp;
8760 MoveL2D_reg_reg(tmp, src);
8761 convL2F_helper(dst, tmp);
8762 %}
8763 %}
8764
8765 //-----------
8766
8767 instruct convL2I_reg(iRegI dst, iRegL src) %{
8768 match(Set dst (ConvL2I src));
8769 #ifndef _LP64
8770 format %{ "MOV $src.lo,$dst\t! long->int" %}
8771 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8772 ins_pipe(ialu_move_reg_I_to_L);
8773 #else
8774 size(4);
8775 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8776 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8777 ins_pipe(ialu_reg);
8778 #endif
8779 %}
8780
8781 // Register Shift Right Immediate
8782 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8783 match(Set dst (ConvL2I (RShiftL src cnt)));
8784
8785 size(4);
8786 format %{ "SRAX $src,$cnt,$dst" %}
8787 opcode(Assembler::srax_op3, Assembler::arith_op);
8788 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8789 ins_pipe(ialu_reg_imm);
8790 %}
8791
8792 //----------Control Flow Instructions------------------------------------------
8793 // Compare Instructions
8794 // Compare Integers
8795 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8796 match(Set icc (CmpI op1 op2));
8797 effect( DEF icc, USE op1, USE op2 );
8798
8799 size(4);
8800 format %{ "CMP $op1,$op2" %}
8801 opcode(Assembler::subcc_op3, Assembler::arith_op);
8802 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8803 ins_pipe(ialu_cconly_reg_reg);
8804 %}
8805
8806 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8807 match(Set icc (CmpU op1 op2));
8808
8809 size(4);
8810 format %{ "CMP $op1,$op2\t! unsigned" %}
8811 opcode(Assembler::subcc_op3, Assembler::arith_op);
8812 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8813 ins_pipe(ialu_cconly_reg_reg);
8814 %}
8815
8816 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8817 match(Set icc (CmpI op1 op2));
8818 effect( DEF icc, USE op1 );
8819
8820 size(4);
8821 format %{ "CMP $op1,$op2" %}
8822 opcode(Assembler::subcc_op3, Assembler::arith_op);
8823 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8824 ins_pipe(ialu_cconly_reg_imm);
8825 %}
8826
8827 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8828 match(Set icc (CmpI (AndI op1 op2) zero));
8829
8830 size(4);
8831 format %{ "BTST $op2,$op1" %}
8832 opcode(Assembler::andcc_op3, Assembler::arith_op);
8833 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8834 ins_pipe(ialu_cconly_reg_reg_zero);
8835 %}
8836
8837 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8838 match(Set icc (CmpI (AndI op1 op2) zero));
8839
8840 size(4);
8841 format %{ "BTST $op2,$op1" %}
8842 opcode(Assembler::andcc_op3, Assembler::arith_op);
8843 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8844 ins_pipe(ialu_cconly_reg_imm_zero);
8845 %}
8846
8847 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8848 match(Set xcc (CmpL op1 op2));
8849 effect( DEF xcc, USE op1, USE op2 );
8850
8851 size(4);
8852 format %{ "CMP $op1,$op2\t\t! long" %}
8853 opcode(Assembler::subcc_op3, Assembler::arith_op);
8854 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8855 ins_pipe(ialu_cconly_reg_reg);
8856 %}
8857
8858 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8859 match(Set xcc (CmpL op1 con));
8860 effect( DEF xcc, USE op1, USE con );
8861
8862 size(4);
8863 format %{ "CMP $op1,$con\t\t! long" %}
8864 opcode(Assembler::subcc_op3, Assembler::arith_op);
8865 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8866 ins_pipe(ialu_cconly_reg_reg);
8867 %}
8868
8869 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8870 match(Set xcc (CmpL (AndL op1 op2) zero));
8871 effect( DEF xcc, USE op1, USE op2 );
8872
8873 size(4);
8874 format %{ "BTST $op1,$op2\t\t! long" %}
8875 opcode(Assembler::andcc_op3, Assembler::arith_op);
8876 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8877 ins_pipe(ialu_cconly_reg_reg);
8878 %}
8879
8880 // useful for checking the alignment of a pointer:
8881 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8882 match(Set xcc (CmpL (AndL op1 con) zero));
8883 effect( DEF xcc, USE op1, USE con );
8884
8885 size(4);
8886 format %{ "BTST $op1,$con\t\t! long" %}
8887 opcode(Assembler::andcc_op3, Assembler::arith_op);
8888 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8889 ins_pipe(ialu_cconly_reg_reg);
8890 %}
8891
8892 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8893 match(Set icc (CmpU op1 op2));
8894
8895 size(4);
8896 format %{ "CMP $op1,$op2\t! unsigned" %}
8897 opcode(Assembler::subcc_op3, Assembler::arith_op);
8898 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8899 ins_pipe(ialu_cconly_reg_imm);
8900 %}
8901
8902 // Compare Pointers
8903 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8904 match(Set pcc (CmpP op1 op2));
8905
8906 size(4);
8907 format %{ "CMP $op1,$op2\t! ptr" %}
8908 opcode(Assembler::subcc_op3, Assembler::arith_op);
8909 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8910 ins_pipe(ialu_cconly_reg_reg);
8911 %}
8912
8913 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8914 match(Set pcc (CmpP op1 op2));
8915
8916 size(4);
8917 format %{ "CMP $op1,$op2\t! ptr" %}
8918 opcode(Assembler::subcc_op3, Assembler::arith_op);
8919 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8920 ins_pipe(ialu_cconly_reg_imm);
8921 %}
8922
8923 // Compare Narrow oops
8924 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8925 match(Set icc (CmpN op1 op2));
8926
8927 size(4);
8928 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8929 opcode(Assembler::subcc_op3, Assembler::arith_op);
8930 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8931 ins_pipe(ialu_cconly_reg_reg);
8932 %}
8933
8934 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8935 match(Set icc (CmpN op1 op2));
8936
8937 size(4);
8938 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8939 opcode(Assembler::subcc_op3, Assembler::arith_op);
8940 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8941 ins_pipe(ialu_cconly_reg_imm);
8942 %}
8943
8944 //----------Max and Min--------------------------------------------------------
8945 // Min Instructions
8946 // Conditional move for min
8947 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8948 effect( USE_DEF op2, USE op1, USE icc );
8949
8950 size(4);
8951 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8952 opcode(Assembler::less);
8953 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8954 ins_pipe(ialu_reg_flags);
8955 %}
8956
8957 // Min Register with Register.
8958 instruct minI_eReg(iRegI op1, iRegI op2) %{
8959 match(Set op2 (MinI op1 op2));
8960 ins_cost(DEFAULT_COST*2);
8961 expand %{
8962 flagsReg icc;
8963 compI_iReg(icc,op1,op2);
8964 cmovI_reg_lt(op2,op1,icc);
8965 %}
8966 %}
8967
8968 // Max Instructions
8969 // Conditional move for max
8970 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8971 effect( USE_DEF op2, USE op1, USE icc );
8972 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8973 opcode(Assembler::greater);
8974 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8975 ins_pipe(ialu_reg_flags);
8976 %}
8977
8978 // Max Register with Register
8979 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8980 match(Set op2 (MaxI op1 op2));
8981 ins_cost(DEFAULT_COST*2);
8982 expand %{
8983 flagsReg icc;
8984 compI_iReg(icc,op1,op2);
8985 cmovI_reg_gt(op2,op1,icc);
8986 %}
8987 %}
8988
8989
8990 //----------Float Compares----------------------------------------------------
8991 // Compare floating, generate condition code
8992 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8993 match(Set fcc (CmpF src1 src2));
8994
8995 size(4);
8996 format %{ "FCMPs $fcc,$src1,$src2" %}
8997 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8998 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8999 ins_pipe(faddF_fcc_reg_reg_zero);
9000 %}
9001
9002 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9003 match(Set fcc (CmpD src1 src2));
9004
9005 size(4);
9006 format %{ "FCMPd $fcc,$src1,$src2" %}
9007 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9008 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9009 ins_pipe(faddD_fcc_reg_reg_zero);
9010 %}
9011
9012
9013 // Compare floating, generate -1,0,1
9014 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9015 match(Set dst (CmpF3 src1 src2));
9016 effect(KILL fcc0);
9017 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9018 format %{ "fcmpl $dst,$src1,$src2" %}
9019 // Primary = float
9020 opcode( true );
9021 ins_encode( floating_cmp( dst, src1, src2 ) );
9022 ins_pipe( floating_cmp );
9023 %}
9024
9025 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9026 match(Set dst (CmpD3 src1 src2));
9027 effect(KILL fcc0);
9028 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9029 format %{ "dcmpl $dst,$src1,$src2" %}
9030 // Primary = double (not float)
9031 opcode( false );
9032 ins_encode( floating_cmp( dst, src1, src2 ) );
9033 ins_pipe( floating_cmp );
9034 %}
9035
9036 //----------Branches---------------------------------------------------------
9037 // Jump
9038 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9039 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9040 match(Jump switch_val);
9041 effect(TEMP table);
9042
9043 ins_cost(350);
9044
9045 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9046 "LD [O7 + $switch_val], O7\n\t"
9047 "JUMP O7" %}
9048 ins_encode %{
9049 // Calculate table address into a register.
9050 Register table_reg;
9051 Register label_reg = O7;
9052 // If we are calculating the size of this instruction don't trust
9053 // zero offsets because they might change when
9054 // MachConstantBaseNode decides to optimize the constant table
9055 // base.
9056 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9057 table_reg = $constanttablebase;
9058 } else {
9059 table_reg = O7;
9060 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9061 __ add($constanttablebase, con_offset, table_reg);
9062 }
9063
9064 // Jump to base address + switch value
9065 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9066 __ jmp(label_reg, G0);
9067 __ delayed()->nop();
9068 %}
9069 ins_pipe(ialu_reg_reg);
9070 %}
9071
9072 // Direct Branch. Use V8 version with longer range.
9073 instruct branch(label labl) %{
9074 match(Goto);
9075 effect(USE labl);
9076
9077 size(8);
9078 ins_cost(BRANCH_COST);
9079 format %{ "BA $labl" %}
9080 ins_encode %{
9081 Label* L = $labl$$label;
9082 __ ba(*L);
9083 __ delayed()->nop();
9084 %}
9085 ins_pipe(br);
9086 %}
9087
9088 // Direct Branch, short with no delay slot
9089 instruct branch_short(label labl) %{
9090 match(Goto);
9091 predicate(UseCBCond);
9092 effect(USE labl);
9093
9094 size(4);
9095 ins_cost(BRANCH_COST);
9096 format %{ "BA $labl\t! short branch" %}
9097 ins_encode %{
9098 Label* L = $labl$$label;
9099 assert(__ use_cbcond(*L), "back to back cbcond");
9100 __ ba_short(*L);
9101 %}
9102 ins_short_branch(1);
9103 ins_avoid_back_to_back(1);
9104 ins_pipe(cbcond_reg_imm);
9105 %}
9106
9107 // Conditional Direct Branch
9108 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9109 match(If cmp icc);
9110 effect(USE labl);
9111
9112 size(8);
9113 ins_cost(BRANCH_COST);
9114 format %{ "BP$cmp $icc,$labl" %}
9115 // Prim = bits 24-22, Secnd = bits 31-30
9116 ins_encode( enc_bp( labl, cmp, icc ) );
9117 ins_pipe(br_cc);
9118 %}
9119
9120 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9121 match(If cmp icc);
9122 effect(USE labl);
9123
9124 ins_cost(BRANCH_COST);
9125 format %{ "BP$cmp $icc,$labl" %}
9126 // Prim = bits 24-22, Secnd = bits 31-30
9127 ins_encode( enc_bp( labl, cmp, icc ) );
9128 ins_pipe(br_cc);
9129 %}
9130
9131 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9132 match(If cmp pcc);
9133 effect(USE labl);
9134
9135 size(8);
9136 ins_cost(BRANCH_COST);
9137 format %{ "BP$cmp $pcc,$labl" %}
9138 ins_encode %{
9139 Label* L = $labl$$label;
9140 Assembler::Predict predict_taken =
9141 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9142
9143 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9144 __ delayed()->nop();
9145 %}
9146 ins_pipe(br_cc);
9147 %}
9148
9149 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9150 match(If cmp fcc);
9151 effect(USE labl);
9152
9153 size(8);
9154 ins_cost(BRANCH_COST);
9155 format %{ "FBP$cmp $fcc,$labl" %}
9156 ins_encode %{
9157 Label* L = $labl$$label;
9158 Assembler::Predict predict_taken =
9159 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9160
9161 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9162 __ delayed()->nop();
9163 %}
9164 ins_pipe(br_fcc);
9165 %}
9166
9167 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9168 match(CountedLoopEnd cmp icc);
9169 effect(USE labl);
9170
9171 size(8);
9172 ins_cost(BRANCH_COST);
9173 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9174 // Prim = bits 24-22, Secnd = bits 31-30
9175 ins_encode( enc_bp( labl, cmp, icc ) );
9176 ins_pipe(br_cc);
9177 %}
9178
9179 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9180 match(CountedLoopEnd cmp icc);
9181 effect(USE labl);
9182
9183 size(8);
9184 ins_cost(BRANCH_COST);
9185 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9186 // Prim = bits 24-22, Secnd = bits 31-30
9187 ins_encode( enc_bp( labl, cmp, icc ) );
9188 ins_pipe(br_cc);
9189 %}
9190
9191 // Compare and branch instructions
9192 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9193 match(If cmp (CmpI op1 op2));
9194 effect(USE labl, KILL icc);
9195
9196 size(12);
9197 ins_cost(BRANCH_COST);
9198 format %{ "CMP $op1,$op2\t! int\n\t"
9199 "BP$cmp $labl" %}
9200 ins_encode %{
9201 Label* L = $labl$$label;
9202 Assembler::Predict predict_taken =
9203 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9204 __ cmp($op1$$Register, $op2$$Register);
9205 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9206 __ delayed()->nop();
9207 %}
9208 ins_pipe(cmp_br_reg_reg);
9209 %}
9210
9211 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9212 match(If cmp (CmpI op1 op2));
9213 effect(USE labl, KILL icc);
9214
9215 size(12);
9216 ins_cost(BRANCH_COST);
9217 format %{ "CMP $op1,$op2\t! int\n\t"
9218 "BP$cmp $labl" %}
9219 ins_encode %{
9220 Label* L = $labl$$label;
9221 Assembler::Predict predict_taken =
9222 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9223 __ cmp($op1$$Register, $op2$$constant);
9224 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9225 __ delayed()->nop();
9226 %}
9227 ins_pipe(cmp_br_reg_imm);
9228 %}
9229
9230 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9231 match(If cmp (CmpU op1 op2));
9232 effect(USE labl, KILL icc);
9233
9234 size(12);
9235 ins_cost(BRANCH_COST);
9236 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9237 "BP$cmp $labl" %}
9238 ins_encode %{
9239 Label* L = $labl$$label;
9240 Assembler::Predict predict_taken =
9241 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9242 __ cmp($op1$$Register, $op2$$Register);
9243 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9244 __ delayed()->nop();
9245 %}
9246 ins_pipe(cmp_br_reg_reg);
9247 %}
9248
9249 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9250 match(If cmp (CmpU op1 op2));
9251 effect(USE labl, KILL icc);
9252
9253 size(12);
9254 ins_cost(BRANCH_COST);
9255 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9256 "BP$cmp $labl" %}
9257 ins_encode %{
9258 Label* L = $labl$$label;
9259 Assembler::Predict predict_taken =
9260 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9261 __ cmp($op1$$Register, $op2$$constant);
9262 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9263 __ delayed()->nop();
9264 %}
9265 ins_pipe(cmp_br_reg_imm);
9266 %}
9267
9268 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9269 match(If cmp (CmpL op1 op2));
9270 effect(USE labl, KILL xcc);
9271
9272 size(12);
9273 ins_cost(BRANCH_COST);
9274 format %{ "CMP $op1,$op2\t! long\n\t"
9275 "BP$cmp $labl" %}
9276 ins_encode %{
9277 Label* L = $labl$$label;
9278 Assembler::Predict predict_taken =
9279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9280 __ cmp($op1$$Register, $op2$$Register);
9281 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9282 __ delayed()->nop();
9283 %}
9284 ins_pipe(cmp_br_reg_reg);
9285 %}
9286
9287 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9288 match(If cmp (CmpL op1 op2));
9289 effect(USE labl, KILL xcc);
9290
9291 size(12);
9292 ins_cost(BRANCH_COST);
9293 format %{ "CMP $op1,$op2\t! long\n\t"
9294 "BP$cmp $labl" %}
9295 ins_encode %{
9296 Label* L = $labl$$label;
9297 Assembler::Predict predict_taken =
9298 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9299 __ cmp($op1$$Register, $op2$$constant);
9300 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9301 __ delayed()->nop();
9302 %}
9303 ins_pipe(cmp_br_reg_imm);
9304 %}
9305
9306 // Compare Pointers and branch
9307 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9308 match(If cmp (CmpP op1 op2));
9309 effect(USE labl, KILL pcc);
9310
9311 size(12);
9312 ins_cost(BRANCH_COST);
9313 format %{ "CMP $op1,$op2\t! ptr\n\t"
9314 "B$cmp $labl" %}
9315 ins_encode %{
9316 Label* L = $labl$$label;
9317 Assembler::Predict predict_taken =
9318 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9319 __ cmp($op1$$Register, $op2$$Register);
9320 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9321 __ delayed()->nop();
9322 %}
9323 ins_pipe(cmp_br_reg_reg);
9324 %}
9325
9326 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9327 match(If cmp (CmpP op1 null));
9328 effect(USE labl, KILL pcc);
9329
9330 size(12);
9331 ins_cost(BRANCH_COST);
9332 format %{ "CMP $op1,0\t! ptr\n\t"
9333 "B$cmp $labl" %}
9334 ins_encode %{
9335 Label* L = $labl$$label;
9336 Assembler::Predict predict_taken =
9337 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9338 __ cmp($op1$$Register, G0);
9339 // bpr() is not used here since it has shorter distance.
9340 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9341 __ delayed()->nop();
9342 %}
9343 ins_pipe(cmp_br_reg_reg);
9344 %}
9345
9346 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9347 match(If cmp (CmpN op1 op2));
9348 effect(USE labl, KILL icc);
9349
9350 size(12);
9351 ins_cost(BRANCH_COST);
9352 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9353 "BP$cmp $labl" %}
9354 ins_encode %{
9355 Label* L = $labl$$label;
9356 Assembler::Predict predict_taken =
9357 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9358 __ cmp($op1$$Register, $op2$$Register);
9359 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9360 __ delayed()->nop();
9361 %}
9362 ins_pipe(cmp_br_reg_reg);
9363 %}
9364
9365 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9366 match(If cmp (CmpN op1 null));
9367 effect(USE labl, KILL icc);
9368
9369 size(12);
9370 ins_cost(BRANCH_COST);
9371 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9372 "BP$cmp $labl" %}
9373 ins_encode %{
9374 Label* L = $labl$$label;
9375 Assembler::Predict predict_taken =
9376 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9377 __ cmp($op1$$Register, G0);
9378 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9379 __ delayed()->nop();
9380 %}
9381 ins_pipe(cmp_br_reg_reg);
9382 %}
9383
9384 // Loop back branch
9385 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9386 match(CountedLoopEnd cmp (CmpI op1 op2));
9387 effect(USE labl, KILL icc);
9388
9389 size(12);
9390 ins_cost(BRANCH_COST);
9391 format %{ "CMP $op1,$op2\t! int\n\t"
9392 "BP$cmp $labl\t! Loop end" %}
9393 ins_encode %{
9394 Label* L = $labl$$label;
9395 Assembler::Predict predict_taken =
9396 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9397 __ cmp($op1$$Register, $op2$$Register);
9398 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9399 __ delayed()->nop();
9400 %}
9401 ins_pipe(cmp_br_reg_reg);
9402 %}
9403
9404 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9405 match(CountedLoopEnd cmp (CmpI op1 op2));
9406 effect(USE labl, KILL icc);
9407
9408 size(12);
9409 ins_cost(BRANCH_COST);
9410 format %{ "CMP $op1,$op2\t! int\n\t"
9411 "BP$cmp $labl\t! Loop end" %}
9412 ins_encode %{
9413 Label* L = $labl$$label;
9414 Assembler::Predict predict_taken =
9415 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9416 __ cmp($op1$$Register, $op2$$constant);
9417 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9418 __ delayed()->nop();
9419 %}
9420 ins_pipe(cmp_br_reg_imm);
9421 %}
9422
9423 // Short compare and branch instructions
9424 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9425 match(If cmp (CmpI op1 op2));
9426 predicate(UseCBCond);
9427 effect(USE labl, KILL icc);
9428
9429 size(4);
9430 ins_cost(BRANCH_COST);
9431 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9432 ins_encode %{
9433 Label* L = $labl$$label;
9434 assert(__ use_cbcond(*L), "back to back cbcond");
9435 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9436 %}
9437 ins_short_branch(1);
9438 ins_avoid_back_to_back(1);
9439 ins_pipe(cbcond_reg_reg);
9440 %}
9441
9442 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9443 match(If cmp (CmpI op1 op2));
9444 predicate(UseCBCond);
9445 effect(USE labl, KILL icc);
9446
9447 size(4);
9448 ins_cost(BRANCH_COST);
9449 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9450 ins_encode %{
9451 Label* L = $labl$$label;
9452 assert(__ use_cbcond(*L), "back to back cbcond");
9453 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9454 %}
9455 ins_short_branch(1);
9456 ins_avoid_back_to_back(1);
9457 ins_pipe(cbcond_reg_imm);
9458 %}
9459
9460 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9461 match(If cmp (CmpU op1 op2));
9462 predicate(UseCBCond);
9463 effect(USE labl, KILL icc);
9464
9465 size(4);
9466 ins_cost(BRANCH_COST);
9467 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9468 ins_encode %{
9469 Label* L = $labl$$label;
9470 assert(__ use_cbcond(*L), "back to back cbcond");
9471 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9472 %}
9473 ins_short_branch(1);
9474 ins_avoid_back_to_back(1);
9475 ins_pipe(cbcond_reg_reg);
9476 %}
9477
9478 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9479 match(If cmp (CmpU op1 op2));
9480 predicate(UseCBCond);
9481 effect(USE labl, KILL icc);
9482
9483 size(4);
9484 ins_cost(BRANCH_COST);
9485 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9486 ins_encode %{
9487 Label* L = $labl$$label;
9488 assert(__ use_cbcond(*L), "back to back cbcond");
9489 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9490 %}
9491 ins_short_branch(1);
9492 ins_avoid_back_to_back(1);
9493 ins_pipe(cbcond_reg_imm);
9494 %}
9495
9496 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9497 match(If cmp (CmpL op1 op2));
9498 predicate(UseCBCond);
9499 effect(USE labl, KILL xcc);
9500
9501 size(4);
9502 ins_cost(BRANCH_COST);
9503 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9504 ins_encode %{
9505 Label* L = $labl$$label;
9506 assert(__ use_cbcond(*L), "back to back cbcond");
9507 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9508 %}
9509 ins_short_branch(1);
9510 ins_avoid_back_to_back(1);
9511 ins_pipe(cbcond_reg_reg);
9512 %}
9513
9514 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9515 match(If cmp (CmpL op1 op2));
9516 predicate(UseCBCond);
9517 effect(USE labl, KILL xcc);
9518
9519 size(4);
9520 ins_cost(BRANCH_COST);
9521 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9522 ins_encode %{
9523 Label* L = $labl$$label;
9524 assert(__ use_cbcond(*L), "back to back cbcond");
9525 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9526 %}
9527 ins_short_branch(1);
9528 ins_avoid_back_to_back(1);
9529 ins_pipe(cbcond_reg_imm);
9530 %}
9531
9532 // Compare Pointers and branch
9533 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9534 match(If cmp (CmpP op1 op2));
9535 predicate(UseCBCond);
9536 effect(USE labl, KILL pcc);
9537
9538 size(4);
9539 ins_cost(BRANCH_COST);
9540 #ifdef _LP64
9541 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9542 #else
9543 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9544 #endif
9545 ins_encode %{
9546 Label* L = $labl$$label;
9547 assert(__ use_cbcond(*L), "back to back cbcond");
9548 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9549 %}
9550 ins_short_branch(1);
9551 ins_avoid_back_to_back(1);
9552 ins_pipe(cbcond_reg_reg);
9553 %}
9554
9555 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9556 match(If cmp (CmpP op1 null));
9557 predicate(UseCBCond);
9558 effect(USE labl, KILL pcc);
9559
9560 size(4);
9561 ins_cost(BRANCH_COST);
9562 #ifdef _LP64
9563 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9564 #else
9565 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9566 #endif
9567 ins_encode %{
9568 Label* L = $labl$$label;
9569 assert(__ use_cbcond(*L), "back to back cbcond");
9570 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9571 %}
9572 ins_short_branch(1);
9573 ins_avoid_back_to_back(1);
9574 ins_pipe(cbcond_reg_reg);
9575 %}
9576
9577 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9578 match(If cmp (CmpN op1 op2));
9579 predicate(UseCBCond);
9580 effect(USE labl, KILL icc);
9581
9582 size(4);
9583 ins_cost(BRANCH_COST);
9584 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9585 ins_encode %{
9586 Label* L = $labl$$label;
9587 assert(__ use_cbcond(*L), "back to back cbcond");
9588 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9589 %}
9590 ins_short_branch(1);
9591 ins_avoid_back_to_back(1);
9592 ins_pipe(cbcond_reg_reg);
9593 %}
9594
9595 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9596 match(If cmp (CmpN op1 null));
9597 predicate(UseCBCond);
9598 effect(USE labl, KILL icc);
9599
9600 size(4);
9601 ins_cost(BRANCH_COST);
9602 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9603 ins_encode %{
9604 Label* L = $labl$$label;
9605 assert(__ use_cbcond(*L), "back to back cbcond");
9606 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9607 %}
9608 ins_short_branch(1);
9609 ins_avoid_back_to_back(1);
9610 ins_pipe(cbcond_reg_reg);
9611 %}
9612
9613 // Loop back branch
9614 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9615 match(CountedLoopEnd cmp (CmpI op1 op2));
9616 predicate(UseCBCond);
9617 effect(USE labl, KILL icc);
9618
9619 size(4);
9620 ins_cost(BRANCH_COST);
9621 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9622 ins_encode %{
9623 Label* L = $labl$$label;
9624 assert(__ use_cbcond(*L), "back to back cbcond");
9625 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9626 %}
9627 ins_short_branch(1);
9628 ins_avoid_back_to_back(1);
9629 ins_pipe(cbcond_reg_reg);
9630 %}
9631
9632 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9633 match(CountedLoopEnd cmp (CmpI op1 op2));
9634 predicate(UseCBCond);
9635 effect(USE labl, KILL icc);
9636
9637 size(4);
9638 ins_cost(BRANCH_COST);
9639 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9640 ins_encode %{
9641 Label* L = $labl$$label;
9642 assert(__ use_cbcond(*L), "back to back cbcond");
9643 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9644 %}
9645 ins_short_branch(1);
9646 ins_avoid_back_to_back(1);
9647 ins_pipe(cbcond_reg_imm);
9648 %}
9649
9650 // Branch-on-register tests all 64 bits. We assume that values
9651 // in 64-bit registers always remains zero or sign extended
9652 // unless our code munges the high bits. Interrupts can chop
9653 // the high order bits to zero or sign at any time.
9654 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9655 match(If cmp (CmpI op1 zero));
9656 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9657 effect(USE labl);
9658
9659 size(8);
9660 ins_cost(BRANCH_COST);
9661 format %{ "BR$cmp $op1,$labl" %}
9662 ins_encode( enc_bpr( labl, cmp, op1 ) );
9663 ins_pipe(br_reg);
9664 %}
9665
9666 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9667 match(If cmp (CmpP op1 null));
9668 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9669 effect(USE labl);
9670
9671 size(8);
9672 ins_cost(BRANCH_COST);
9673 format %{ "BR$cmp $op1,$labl" %}
9674 ins_encode( enc_bpr( labl, cmp, op1 ) );
9675 ins_pipe(br_reg);
9676 %}
9677
9678 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9679 match(If cmp (CmpL op1 zero));
9680 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9681 effect(USE labl);
9682
9683 size(8);
9684 ins_cost(BRANCH_COST);
9685 format %{ "BR$cmp $op1,$labl" %}
9686 ins_encode( enc_bpr( labl, cmp, op1 ) );
9687 ins_pipe(br_reg);
9688 %}
9689
9690
9691 // ============================================================================
9692 // Long Compare
9693 //
9694 // Currently we hold longs in 2 registers. Comparing such values efficiently
9695 // is tricky. The flavor of compare used depends on whether we are testing
9696 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9697 // The GE test is the negated LT test. The LE test can be had by commuting
9698 // the operands (yielding a GE test) and then negating; negate again for the
9699 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9700 // NE test is negated from that.
9701
9702 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9703 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9704 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9705 // are collapsed internally in the ADLC's dfa-gen code. The match for
9706 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9707 // foo match ends up with the wrong leaf. One fix is to not match both
9708 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9709 // both forms beat the trinary form of long-compare and both are very useful
9710 // on Intel which has so few registers.
9711
9712 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9713 match(If cmp xcc);
9714 effect(USE labl);
9715
9716 size(8);
9717 ins_cost(BRANCH_COST);
9718 format %{ "BP$cmp $xcc,$labl" %}
9719 ins_encode %{
9720 Label* L = $labl$$label;
9721 Assembler::Predict predict_taken =
9722 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9723
9724 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9725 __ delayed()->nop();
9726 %}
9727 ins_pipe(br_cc);
9728 %}
9729
9730 // Manifest a CmpL3 result in an integer register. Very painful.
9731 // This is the test to avoid.
9732 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9733 match(Set dst (CmpL3 src1 src2) );
9734 effect( KILL ccr );
9735 ins_cost(6*DEFAULT_COST);
9736 size(24);
9737 format %{ "CMP $src1,$src2\t\t! long\n"
9738 "\tBLT,a,pn done\n"
9739 "\tMOV -1,$dst\t! delay slot\n"
9740 "\tBGT,a,pn done\n"
9741 "\tMOV 1,$dst\t! delay slot\n"
9742 "\tCLR $dst\n"
9743 "done:" %}
9744 ins_encode( cmpl_flag(src1,src2,dst) );
9745 ins_pipe(cmpL_reg);
9746 %}
9747
9748 // Conditional move
9749 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9750 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9751 ins_cost(150);
9752 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9753 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9754 ins_pipe(ialu_reg);
9755 %}
9756
9757 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9758 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9759 ins_cost(140);
9760 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9761 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9762 ins_pipe(ialu_imm);
9763 %}
9764
9765 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9766 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9767 ins_cost(150);
9768 format %{ "MOV$cmp $xcc,$src,$dst" %}
9769 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9770 ins_pipe(ialu_reg);
9771 %}
9772
9773 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9774 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9775 ins_cost(140);
9776 format %{ "MOV$cmp $xcc,$src,$dst" %}
9777 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9778 ins_pipe(ialu_imm);
9779 %}
9780
9781 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9782 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9783 ins_cost(150);
9784 format %{ "MOV$cmp $xcc,$src,$dst" %}
9785 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9786 ins_pipe(ialu_reg);
9787 %}
9788
9789 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9790 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9791 ins_cost(150);
9792 format %{ "MOV$cmp $xcc,$src,$dst" %}
9793 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9794 ins_pipe(ialu_reg);
9795 %}
9796
9797 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9798 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9799 ins_cost(140);
9800 format %{ "MOV$cmp $xcc,$src,$dst" %}
9801 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9802 ins_pipe(ialu_imm);
9803 %}
9804
9805 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9806 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9807 ins_cost(150);
9808 opcode(0x101);
9809 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9810 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9811 ins_pipe(int_conditional_float_move);
9812 %}
9813
9814 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9815 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9816 ins_cost(150);
9817 opcode(0x102);
9818 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9819 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9820 ins_pipe(int_conditional_float_move);
9821 %}
9822
9823 // ============================================================================
9824 // Safepoint Instruction
9825 instruct safePoint_poll(iRegP poll) %{
9826 match(SafePoint poll);
9827 effect(USE poll);
9828
9829 size(4);
9830 #ifdef _LP64
9831 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9832 #else
9833 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9834 #endif
9835 ins_encode %{
9836 __ relocate(relocInfo::poll_type);
9837 __ ld_ptr($poll$$Register, 0, G0);
9838 %}
9839 ins_pipe(loadPollP);
9840 %}
9841
9842 // ============================================================================
9843 // Call Instructions
9844 // Call Java Static Instruction
9845 instruct CallStaticJavaDirect( method meth ) %{
9846 match(CallStaticJava);
9847 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9848 effect(USE meth);
9849
9850 size(8);
9851 ins_cost(CALL_COST);
9852 format %{ "CALL,static ; NOP ==> " %}
9853 ins_encode( Java_Static_Call( meth ), call_epilog );
9854 ins_pipe(simple_call);
9855 %}
9856
9857 // Call Java Static Instruction (method handle version)
9858 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9859 match(CallStaticJava);
9860 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9861 effect(USE meth, KILL l7_mh_SP_save);
9862
9863 size(16);
9864 ins_cost(CALL_COST);
9865 format %{ "CALL,static/MethodHandle" %}
9866 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9867 ins_pipe(simple_call);
9868 %}
9869
9870 // Call Java Dynamic Instruction
9871 instruct CallDynamicJavaDirect( method meth ) %{
9872 match(CallDynamicJava);
9873 effect(USE meth);
9874
9875 ins_cost(CALL_COST);
9876 format %{ "SET (empty),R_G5\n\t"
9877 "CALL,dynamic ; NOP ==> " %}
9878 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9879 ins_pipe(call);
9880 %}
9881
9882 // Call Runtime Instruction
9883 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9884 match(CallRuntime);
9885 effect(USE meth, KILL l7);
9886 ins_cost(CALL_COST);
9887 format %{ "CALL,runtime" %}
9888 ins_encode( Java_To_Runtime( meth ),
9889 call_epilog, adjust_long_from_native_call );
9890 ins_pipe(simple_call);
9891 %}
9892
9893 // Call runtime without safepoint - same as CallRuntime
9894 instruct CallLeafDirect(method meth, l7RegP l7) %{
9895 match(CallLeaf);
9896 effect(USE meth, KILL l7);
9897 ins_cost(CALL_COST);
9898 format %{ "CALL,runtime leaf" %}
9899 ins_encode( Java_To_Runtime( meth ),
9900 call_epilog,
9901 adjust_long_from_native_call );
9902 ins_pipe(simple_call);
9903 %}
9904
9905 // Call runtime without safepoint - same as CallLeaf
9906 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9907 match(CallLeafNoFP);
9908 effect(USE meth, KILL l7);
9909 ins_cost(CALL_COST);
9910 format %{ "CALL,runtime leaf nofp" %}
9911 ins_encode( Java_To_Runtime( meth ),
9912 call_epilog,
9913 adjust_long_from_native_call );
9914 ins_pipe(simple_call);
9915 %}
9916
9917 // Tail Call; Jump from runtime stub to Java code.
9918 // Also known as an 'interprocedural jump'.
9919 // Target of jump will eventually return to caller.
9920 // TailJump below removes the return address.
9921 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9922 match(TailCall jump_target method_oop );
9923
9924 ins_cost(CALL_COST);
9925 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9926 ins_encode(form_jmpl(jump_target));
9927 ins_pipe(tail_call);
9928 %}
9929
9930
9931 // Return Instruction
9932 instruct Ret() %{
9933 match(Return);
9934
9935 // The epilogue node did the ret already.
9936 size(0);
9937 format %{ "! return" %}
9938 ins_encode();
9939 ins_pipe(empty);
9940 %}
9941
9942
9943 // Tail Jump; remove the return address; jump to target.
9944 // TailCall above leaves the return address around.
9945 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9946 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9947 // "restore" before this instruction (in Epilogue), we need to materialize it
9948 // in %i0.
9949 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9950 match( TailJump jump_target ex_oop );
9951 ins_cost(CALL_COST);
9952 format %{ "! discard R_O7\n\t"
9953 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9954 ins_encode(form_jmpl_set_exception_pc(jump_target));
9955 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9956 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9957 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9958 ins_pipe(tail_call);
9959 %}
9960
9961 // Create exception oop: created by stack-crawling runtime code.
9962 // Created exception is now available to this handler, and is setup
9963 // just prior to jumping to this handler. No code emitted.
9964 instruct CreateException( o0RegP ex_oop )
9965 %{
9966 match(Set ex_oop (CreateEx));
9967 ins_cost(0);
9968
9969 size(0);
9970 // use the following format syntax
9971 format %{ "! exception oop is in R_O0; no code emitted" %}
9972 ins_encode();
9973 ins_pipe(empty);
9974 %}
9975
9976
9977 // Rethrow exception:
9978 // The exception oop will come in the first argument position.
9979 // Then JUMP (not call) to the rethrow stub code.
9980 instruct RethrowException()
9981 %{
9982 match(Rethrow);
9983 ins_cost(CALL_COST);
9984
9985 // use the following format syntax
9986 format %{ "Jmp rethrow_stub" %}
9987 ins_encode(enc_rethrow);
9988 ins_pipe(tail_call);
9989 %}
9990
9991
9992 // Die now
9993 instruct ShouldNotReachHere( )
9994 %{
9995 match(Halt);
9996 ins_cost(CALL_COST);
9997
9998 size(4);
9999 // Use the following format syntax
10000 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10001 ins_encode( form2_illtrap() );
10002 ins_pipe(tail_call);
10003 %}
10004
10005 // ============================================================================
10006 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10007 // array for an instance of the superklass. Set a hidden internal cache on a
10008 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10009 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10010 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10011 match(Set index (PartialSubtypeCheck sub super));
10012 effect( KILL pcc, KILL o7 );
10013 ins_cost(DEFAULT_COST*10);
10014 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10015 ins_encode( enc_PartialSubtypeCheck() );
10016 ins_pipe(partial_subtype_check_pipe);
10017 %}
10018
10019 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10020 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10021 effect( KILL idx, KILL o7 );
10022 ins_cost(DEFAULT_COST*10);
10023 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10024 ins_encode( enc_PartialSubtypeCheck() );
10025 ins_pipe(partial_subtype_check_pipe);
10026 %}
10027
10028
10029 // ============================================================================
10030 // inlined locking and unlocking
10031
10032 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10033 match(Set pcc (FastLock object box));
10034
10035 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10036 ins_cost(100);
10037
10038 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10039 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10040 ins_pipe(long_memory_op);
10041 %}
10042
10043
10044 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10045 match(Set pcc (FastUnlock object box));
10046 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10047 ins_cost(100);
10048
10049 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10050 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10051 ins_pipe(long_memory_op);
10052 %}
10053
10054 // The encodings are generic.
10055 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10056 predicate(!use_block_zeroing(n->in(2)) );
10057 match(Set dummy (ClearArray cnt base));
10058 effect(TEMP temp, KILL ccr);
10059 ins_cost(300);
10060 format %{ "MOV $cnt,$temp\n"
10061 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10062 " BRge loop\t\t! Clearing loop\n"
10063 " STX G0,[$base+$temp]\t! delay slot" %}
10064
10065 ins_encode %{
10066 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10067 Register nof_bytes_arg = $cnt$$Register;
10068 Register nof_bytes_tmp = $temp$$Register;
10069 Register base_pointer_arg = $base$$Register;
10070
10071 Label loop;
10072 __ mov(nof_bytes_arg, nof_bytes_tmp);
10073
10074 // Loop and clear, walking backwards through the array.
10075 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10076 __ bind(loop);
10077 __ deccc(nof_bytes_tmp, 8);
10078 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10079 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10080 // %%%% this mini-loop must not cross a cache boundary!
10081 %}
10082 ins_pipe(long_memory_op);
10083 %}
10084
10085 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10086 predicate(use_block_zeroing(n->in(2)));
10087 match(Set dummy (ClearArray cnt base));
10088 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10089 ins_cost(300);
10090 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10091
10092 ins_encode %{
10093
10094 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10095 Register to = $base$$Register;
10096 Register count = $cnt$$Register;
10097
10098 Label Ldone;
10099 __ nop(); // Separate short branches
10100 // Use BIS for zeroing (temp is not used).
10101 __ bis_zeroing(to, count, G0, Ldone);
10102 __ bind(Ldone);
10103
10104 %}
10105 ins_pipe(long_memory_op);
10106 %}
10107
10108 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10109 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10110 match(Set dummy (ClearArray cnt base));
10111 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10112 ins_cost(300);
10113 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10114
10115 ins_encode %{
10116
10117 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10118 Register to = $base$$Register;
10119 Register count = $cnt$$Register;
10120 Register temp = $tmp$$Register;
10121
10122 Label Ldone;
10123 __ nop(); // Separate short branches
10124 // Use BIS for zeroing
10125 __ bis_zeroing(to, count, temp, Ldone);
10126 __ bind(Ldone);
10127
10128 %}
10129 ins_pipe(long_memory_op);
10130 %}
10131
10132 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10133 o7RegI tmp, flagsReg ccr) %{
10134 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10135 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10136 ins_cost(300);
10137 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10138 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10139 ins_pipe(long_memory_op);
10140 %}
10141
10142 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10143 o7RegI tmp, flagsReg ccr) %{
10144 match(Set result (StrEquals (Binary str1 str2) cnt));
10145 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10146 ins_cost(300);
10147 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10148 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10149 ins_pipe(long_memory_op);
10150 %}
10151
10152 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10153 o7RegI tmp2, flagsReg ccr) %{
10154 match(Set result (AryEq ary1 ary2));
10155 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10156 ins_cost(300);
10157 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10158 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10159 ins_pipe(long_memory_op);
10160 %}
10161
10162
10163 //---------- Zeros Count Instructions ------------------------------------------
10164
10165 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10166 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10167 match(Set dst (CountLeadingZerosI src));
10168 effect(TEMP dst, TEMP tmp, KILL cr);
10169
10170 // x |= (x >> 1);
10171 // x |= (x >> 2);
10172 // x |= (x >> 4);
10173 // x |= (x >> 8);
10174 // x |= (x >> 16);
10175 // return (WORDBITS - popc(x));
10176 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10177 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10178 "OR $dst,$tmp,$dst\n\t"
10179 "SRL $dst,2,$tmp\n\t"
10180 "OR $dst,$tmp,$dst\n\t"
10181 "SRL $dst,4,$tmp\n\t"
10182 "OR $dst,$tmp,$dst\n\t"
10183 "SRL $dst,8,$tmp\n\t"
10184 "OR $dst,$tmp,$dst\n\t"
10185 "SRL $dst,16,$tmp\n\t"
10186 "OR $dst,$tmp,$dst\n\t"
10187 "POPC $dst,$dst\n\t"
10188 "MOV 32,$tmp\n\t"
10189 "SUB $tmp,$dst,$dst" %}
10190 ins_encode %{
10191 Register Rdst = $dst$$Register;
10192 Register Rsrc = $src$$Register;
10193 Register Rtmp = $tmp$$Register;
10194 __ srl(Rsrc, 1, Rtmp);
10195 __ srl(Rsrc, 0, Rdst);
10196 __ or3(Rdst, Rtmp, Rdst);
10197 __ srl(Rdst, 2, Rtmp);
10198 __ or3(Rdst, Rtmp, Rdst);
10199 __ srl(Rdst, 4, Rtmp);
10200 __ or3(Rdst, Rtmp, Rdst);
10201 __ srl(Rdst, 8, Rtmp);
10202 __ or3(Rdst, Rtmp, Rdst);
10203 __ srl(Rdst, 16, Rtmp);
10204 __ or3(Rdst, Rtmp, Rdst);
10205 __ popc(Rdst, Rdst);
10206 __ mov(BitsPerInt, Rtmp);
10207 __ sub(Rtmp, Rdst, Rdst);
10208 %}
10209 ins_pipe(ialu_reg);
10210 %}
10211
10212 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10213 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10214 match(Set dst (CountLeadingZerosL src));
10215 effect(TEMP dst, TEMP tmp, KILL cr);
10216
10217 // x |= (x >> 1);
10218 // x |= (x >> 2);
10219 // x |= (x >> 4);
10220 // x |= (x >> 8);
10221 // x |= (x >> 16);
10222 // x |= (x >> 32);
10223 // return (WORDBITS - popc(x));
10224 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10225 "OR $src,$tmp,$dst\n\t"
10226 "SRLX $dst,2,$tmp\n\t"
10227 "OR $dst,$tmp,$dst\n\t"
10228 "SRLX $dst,4,$tmp\n\t"
10229 "OR $dst,$tmp,$dst\n\t"
10230 "SRLX $dst,8,$tmp\n\t"
10231 "OR $dst,$tmp,$dst\n\t"
10232 "SRLX $dst,16,$tmp\n\t"
10233 "OR $dst,$tmp,$dst\n\t"
10234 "SRLX $dst,32,$tmp\n\t"
10235 "OR $dst,$tmp,$dst\n\t"
10236 "POPC $dst,$dst\n\t"
10237 "MOV 64,$tmp\n\t"
10238 "SUB $tmp,$dst,$dst" %}
10239 ins_encode %{
10240 Register Rdst = $dst$$Register;
10241 Register Rsrc = $src$$Register;
10242 Register Rtmp = $tmp$$Register;
10243 __ srlx(Rsrc, 1, Rtmp);
10244 __ or3( Rsrc, Rtmp, Rdst);
10245 __ srlx(Rdst, 2, Rtmp);
10246 __ or3( Rdst, Rtmp, Rdst);
10247 __ srlx(Rdst, 4, Rtmp);
10248 __ or3( Rdst, Rtmp, Rdst);
10249 __ srlx(Rdst, 8, Rtmp);
10250 __ or3( Rdst, Rtmp, Rdst);
10251 __ srlx(Rdst, 16, Rtmp);
10252 __ or3( Rdst, Rtmp, Rdst);
10253 __ srlx(Rdst, 32, Rtmp);
10254 __ or3( Rdst, Rtmp, Rdst);
10255 __ popc(Rdst, Rdst);
10256 __ mov(BitsPerLong, Rtmp);
10257 __ sub(Rtmp, Rdst, Rdst);
10258 %}
10259 ins_pipe(ialu_reg);
10260 %}
10261
10262 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10263 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10264 match(Set dst (CountTrailingZerosI src));
10265 effect(TEMP dst, KILL cr);
10266
10267 // return popc(~x & (x - 1));
10268 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10269 "ANDN $dst,$src,$dst\n\t"
10270 "SRL $dst,R_G0,$dst\n\t"
10271 "POPC $dst,$dst" %}
10272 ins_encode %{
10273 Register Rdst = $dst$$Register;
10274 Register Rsrc = $src$$Register;
10275 __ sub(Rsrc, 1, Rdst);
10276 __ andn(Rdst, Rsrc, Rdst);
10277 __ srl(Rdst, G0, Rdst);
10278 __ popc(Rdst, Rdst);
10279 %}
10280 ins_pipe(ialu_reg);
10281 %}
10282
10283 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10284 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10285 match(Set dst (CountTrailingZerosL src));
10286 effect(TEMP dst, KILL cr);
10287
10288 // return popc(~x & (x - 1));
10289 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10290 "ANDN $dst,$src,$dst\n\t"
10291 "POPC $dst,$dst" %}
10292 ins_encode %{
10293 Register Rdst = $dst$$Register;
10294 Register Rsrc = $src$$Register;
10295 __ sub(Rsrc, 1, Rdst);
10296 __ andn(Rdst, Rsrc, Rdst);
10297 __ popc(Rdst, Rdst);
10298 %}
10299 ins_pipe(ialu_reg);
10300 %}
10301
10302
10303 //---------- Population Count Instructions -------------------------------------
10304
10305 instruct popCountI(iRegI dst, iRegI src) %{
10306 predicate(UsePopCountInstruction);
10307 match(Set dst (PopCountI src));
10308
10309 format %{ "POPC $src, $dst" %}
10310 ins_encode %{
10311 __ popc($src$$Register, $dst$$Register);
10312 %}
10313 ins_pipe(ialu_reg);
10314 %}
10315
10316 // Note: Long.bitCount(long) returns an int.
10317 instruct popCountL(iRegI dst, iRegL src) %{
10318 predicate(UsePopCountInstruction);
10319 match(Set dst (PopCountL src));
10320
10321 format %{ "POPC $src, $dst" %}
10322 ins_encode %{
10323 __ popc($src$$Register, $dst$$Register);
10324 %}
10325 ins_pipe(ialu_reg);
10326 %}
10327
10328
10329 // ============================================================================
10330 //------------Bytes reverse--------------------------------------------------
10331
10332 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10333 match(Set dst (ReverseBytesI src));
10334
10335 // Op cost is artificially doubled to make sure that load or store
10336 // instructions are preferred over this one which requires a spill
10337 // onto a stack slot.
10338 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10339 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10340
10341 ins_encode %{
10342 __ set($src$$disp + STACK_BIAS, O7);
10343 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10344 %}
10345 ins_pipe( iload_mem );
10346 %}
10347
10348 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10349 match(Set dst (ReverseBytesL src));
10350
10351 // Op cost is artificially doubled to make sure that load or store
10352 // instructions are preferred over this one which requires a spill
10353 // onto a stack slot.
10354 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10355 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10356
10357 ins_encode %{
10358 __ set($src$$disp + STACK_BIAS, O7);
10359 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10360 %}
10361 ins_pipe( iload_mem );
10362 %}
10363
10364 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10365 match(Set dst (ReverseBytesUS src));
10366
10367 // Op cost is artificially doubled to make sure that load or store
10368 // instructions are preferred over this one which requires a spill
10369 // onto a stack slot.
10370 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10371 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10372
10373 ins_encode %{
10374 // the value was spilled as an int so bias the load
10375 __ set($src$$disp + STACK_BIAS + 2, O7);
10376 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10377 %}
10378 ins_pipe( iload_mem );
10379 %}
10380
10381 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10382 match(Set dst (ReverseBytesS src));
10383
10384 // Op cost is artificially doubled to make sure that load or store
10385 // instructions are preferred over this one which requires a spill
10386 // onto a stack slot.
10387 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10388 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10389
10390 ins_encode %{
10391 // the value was spilled as an int so bias the load
10392 __ set($src$$disp + STACK_BIAS + 2, O7);
10393 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10394 %}
10395 ins_pipe( iload_mem );
10396 %}
10397
10398 // Load Integer reversed byte order
10399 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10400 match(Set dst (ReverseBytesI (LoadI src)));
10401
10402 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10403 size(4);
10404 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10405
10406 ins_encode %{
10407 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10408 %}
10409 ins_pipe(iload_mem);
10410 %}
10411
10412 // Load Long - aligned and reversed
10413 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10414 match(Set dst (ReverseBytesL (LoadL src)));
10415
10416 ins_cost(MEMORY_REF_COST);
10417 size(4);
10418 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10419
10420 ins_encode %{
10421 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10422 %}
10423 ins_pipe(iload_mem);
10424 %}
10425
10426 // Load unsigned short / char reversed byte order
10427 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10428 match(Set dst (ReverseBytesUS (LoadUS src)));
10429
10430 ins_cost(MEMORY_REF_COST);
10431 size(4);
10432 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10433
10434 ins_encode %{
10435 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10436 %}
10437 ins_pipe(iload_mem);
10438 %}
10439
10440 // Load short reversed byte order
10441 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10442 match(Set dst (ReverseBytesS (LoadS src)));
10443
10444 ins_cost(MEMORY_REF_COST);
10445 size(4);
10446 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10447
10448 ins_encode %{
10449 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10450 %}
10451 ins_pipe(iload_mem);
10452 %}
10453
10454 // Store Integer reversed byte order
10455 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10456 match(Set dst (StoreI dst (ReverseBytesI src)));
10457
10458 ins_cost(MEMORY_REF_COST);
10459 size(4);
10460 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10461
10462 ins_encode %{
10463 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10464 %}
10465 ins_pipe(istore_mem_reg);
10466 %}
10467
10468 // Store Long reversed byte order
10469 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10470 match(Set dst (StoreL dst (ReverseBytesL src)));
10471
10472 ins_cost(MEMORY_REF_COST);
10473 size(4);
10474 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10475
10476 ins_encode %{
10477 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10478 %}
10479 ins_pipe(istore_mem_reg);
10480 %}
10481
10482 // Store unsighed short/char reversed byte order
10483 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10484 match(Set dst (StoreC dst (ReverseBytesUS src)));
10485
10486 ins_cost(MEMORY_REF_COST);
10487 size(4);
10488 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10489
10490 ins_encode %{
10491 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10492 %}
10493 ins_pipe(istore_mem_reg);
10494 %}
10495
10496 // Store short reversed byte order
10497 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10498 match(Set dst (StoreC dst (ReverseBytesS src)));
10499
10500 ins_cost(MEMORY_REF_COST);
10501 size(4);
10502 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10503
10504 ins_encode %{
10505 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10506 %}
10507 ins_pipe(istore_mem_reg);
10508 %}
10509
10510 // ====================VECTOR INSTRUCTIONS=====================================
10511
10512 // Load Aligned Packed values into a Double Register
10513 instruct loadV8(regD dst, memory mem) %{
10514 predicate(n->as_LoadVector()->memory_size() == 8);
10515 match(Set dst (LoadVector mem));
10516 ins_cost(MEMORY_REF_COST);
10517 size(4);
10518 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10519 ins_encode %{
10520 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10521 %}
10522 ins_pipe(floadD_mem);
10523 %}
10524
10525 // Store Vector in Double register to memory
10526 instruct storeV8(memory mem, regD src) %{
10527 predicate(n->as_StoreVector()->memory_size() == 8);
10528 match(Set mem (StoreVector mem src));
10529 ins_cost(MEMORY_REF_COST);
10530 size(4);
10531 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10532 ins_encode %{
10533 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10534 %}
10535 ins_pipe(fstoreD_mem_reg);
10536 %}
10537
10538 // Store Zero into vector in memory
10539 instruct storeV8B_zero(memory mem, immI0 zero) %{
10540 predicate(n->as_StoreVector()->memory_size() == 8);
10541 match(Set mem (StoreVector mem (ReplicateB zero)));
10542 ins_cost(MEMORY_REF_COST);
10543 size(4);
10544 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10545 ins_encode %{
10546 __ stx(G0, $mem$$Address);
10547 %}
10548 ins_pipe(fstoreD_mem_zero);
10549 %}
10550
10551 instruct storeV4S_zero(memory mem, immI0 zero) %{
10552 predicate(n->as_StoreVector()->memory_size() == 8);
10553 match(Set mem (StoreVector mem (ReplicateS zero)));
10554 ins_cost(MEMORY_REF_COST);
10555 size(4);
10556 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10557 ins_encode %{
10558 __ stx(G0, $mem$$Address);
10559 %}
10560 ins_pipe(fstoreD_mem_zero);
10561 %}
10562
10563 instruct storeV2I_zero(memory mem, immI0 zero) %{
10564 predicate(n->as_StoreVector()->memory_size() == 8);
10565 match(Set mem (StoreVector mem (ReplicateI zero)));
10566 ins_cost(MEMORY_REF_COST);
10567 size(4);
10568 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10569 ins_encode %{
10570 __ stx(G0, $mem$$Address);
10571 %}
10572 ins_pipe(fstoreD_mem_zero);
10573 %}
10574
10575 instruct storeV2F_zero(memory mem, immF0 zero) %{
10576 predicate(n->as_StoreVector()->memory_size() == 8);
10577 match(Set mem (StoreVector mem (ReplicateF zero)));
10578 ins_cost(MEMORY_REF_COST);
10579 size(4);
10580 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10581 ins_encode %{
10582 __ stx(G0, $mem$$Address);
10583 %}
10584 ins_pipe(fstoreD_mem_zero);
10585 %}
10586
10587 // Replicate scalar to packed byte values into Double register
10588 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10589 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10590 match(Set dst (ReplicateB src));
10591 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10592 format %{ "SLLX $src,56,$tmp\n\t"
10593 "SRLX $tmp, 8,$tmp2\n\t"
10594 "OR $tmp,$tmp2,$tmp\n\t"
10595 "SRLX $tmp,16,$tmp2\n\t"
10596 "OR $tmp,$tmp2,$tmp\n\t"
10597 "SRLX $tmp,32,$tmp2\n\t"
10598 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10599 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10600 ins_encode %{
10601 Register Rsrc = $src$$Register;
10602 Register Rtmp = $tmp$$Register;
10603 Register Rtmp2 = $tmp2$$Register;
10604 __ sllx(Rsrc, 56, Rtmp);
10605 __ srlx(Rtmp, 8, Rtmp2);
10606 __ or3 (Rtmp, Rtmp2, Rtmp);
10607 __ srlx(Rtmp, 16, Rtmp2);
10608 __ or3 (Rtmp, Rtmp2, Rtmp);
10609 __ srlx(Rtmp, 32, Rtmp2);
10610 __ or3 (Rtmp, Rtmp2, Rtmp);
10611 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10612 %}
10613 ins_pipe(ialu_reg);
10614 %}
10615
10616 // Replicate scalar to packed byte values into Double stack
10617 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10618 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10619 match(Set dst (ReplicateB src));
10620 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10621 format %{ "SLLX $src,56,$tmp\n\t"
10622 "SRLX $tmp, 8,$tmp2\n\t"
10623 "OR $tmp,$tmp2,$tmp\n\t"
10624 "SRLX $tmp,16,$tmp2\n\t"
10625 "OR $tmp,$tmp2,$tmp\n\t"
10626 "SRLX $tmp,32,$tmp2\n\t"
10627 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10628 "STX $tmp,$dst\t! regL to stkD" %}
10629 ins_encode %{
10630 Register Rsrc = $src$$Register;
10631 Register Rtmp = $tmp$$Register;
10632 Register Rtmp2 = $tmp2$$Register;
10633 __ sllx(Rsrc, 56, Rtmp);
10634 __ srlx(Rtmp, 8, Rtmp2);
10635 __ or3 (Rtmp, Rtmp2, Rtmp);
10636 __ srlx(Rtmp, 16, Rtmp2);
10637 __ or3 (Rtmp, Rtmp2, Rtmp);
10638 __ srlx(Rtmp, 32, Rtmp2);
10639 __ or3 (Rtmp, Rtmp2, Rtmp);
10640 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10641 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10642 %}
10643 ins_pipe(ialu_reg);
10644 %}
10645
10646 // Replicate scalar constant to packed byte values in Double register
10647 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10648 predicate(n->as_Vector()->length() == 8);
10649 match(Set dst (ReplicateB con));
10650 effect(KILL tmp);
10651 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10652 ins_encode %{
10653 // XXX This is a quick fix for 6833573.
10654 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10655 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10656 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10657 %}
10658 ins_pipe(loadConFD);
10659 %}
10660
10661 // Replicate scalar to packed char/short values into Double register
10662 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10663 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10664 match(Set dst (ReplicateS src));
10665 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10666 format %{ "SLLX $src,48,$tmp\n\t"
10667 "SRLX $tmp,16,$tmp2\n\t"
10668 "OR $tmp,$tmp2,$tmp\n\t"
10669 "SRLX $tmp,32,$tmp2\n\t"
10670 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10671 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10672 ins_encode %{
10673 Register Rsrc = $src$$Register;
10674 Register Rtmp = $tmp$$Register;
10675 Register Rtmp2 = $tmp2$$Register;
10676 __ sllx(Rsrc, 48, Rtmp);
10677 __ srlx(Rtmp, 16, Rtmp2);
10678 __ or3 (Rtmp, Rtmp2, Rtmp);
10679 __ srlx(Rtmp, 32, Rtmp2);
10680 __ or3 (Rtmp, Rtmp2, Rtmp);
10681 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10682 %}
10683 ins_pipe(ialu_reg);
10684 %}
10685
10686 // Replicate scalar to packed char/short values into Double stack
10687 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10688 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10689 match(Set dst (ReplicateS src));
10690 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10691 format %{ "SLLX $src,48,$tmp\n\t"
10692 "SRLX $tmp,16,$tmp2\n\t"
10693 "OR $tmp,$tmp2,$tmp\n\t"
10694 "SRLX $tmp,32,$tmp2\n\t"
10695 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10696 "STX $tmp,$dst\t! regL to stkD" %}
10697 ins_encode %{
10698 Register Rsrc = $src$$Register;
10699 Register Rtmp = $tmp$$Register;
10700 Register Rtmp2 = $tmp2$$Register;
10701 __ sllx(Rsrc, 48, Rtmp);
10702 __ srlx(Rtmp, 16, Rtmp2);
10703 __ or3 (Rtmp, Rtmp2, Rtmp);
10704 __ srlx(Rtmp, 32, Rtmp2);
10705 __ or3 (Rtmp, Rtmp2, Rtmp);
10706 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10707 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10708 %}
10709 ins_pipe(ialu_reg);
10710 %}
10711
10712 // Replicate scalar constant to packed char/short values in Double register
10713 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10714 predicate(n->as_Vector()->length() == 4);
10715 match(Set dst (ReplicateS con));
10716 effect(KILL tmp);
10717 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10718 ins_encode %{
10719 // XXX This is a quick fix for 6833573.
10720 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10721 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10722 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10723 %}
10724 ins_pipe(loadConFD);
10725 %}
10726
10727 // Replicate scalar to packed int values into Double register
10728 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10729 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10730 match(Set dst (ReplicateI src));
10731 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10732 format %{ "SLLX $src,32,$tmp\n\t"
10733 "SRLX $tmp,32,$tmp2\n\t"
10734 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10735 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10736 ins_encode %{
10737 Register Rsrc = $src$$Register;
10738 Register Rtmp = $tmp$$Register;
10739 Register Rtmp2 = $tmp2$$Register;
10740 __ sllx(Rsrc, 32, Rtmp);
10741 __ srlx(Rtmp, 32, Rtmp2);
10742 __ or3 (Rtmp, Rtmp2, Rtmp);
10743 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10744 %}
10745 ins_pipe(ialu_reg);
10746 %}
10747
10748 // Replicate scalar to packed int values into Double stack
10749 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10750 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10751 match(Set dst (ReplicateI src));
10752 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10753 format %{ "SLLX $src,32,$tmp\n\t"
10754 "SRLX $tmp,32,$tmp2\n\t"
10755 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10756 "STX $tmp,$dst\t! regL to stkD" %}
10757 ins_encode %{
10758 Register Rsrc = $src$$Register;
10759 Register Rtmp = $tmp$$Register;
10760 Register Rtmp2 = $tmp2$$Register;
10761 __ sllx(Rsrc, 32, Rtmp);
10762 __ srlx(Rtmp, 32, Rtmp2);
10763 __ or3 (Rtmp, Rtmp2, Rtmp);
10764 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10765 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10766 %}
10767 ins_pipe(ialu_reg);
10768 %}
10769
10770 // Replicate scalar zero constant to packed int values in Double register
10771 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10772 predicate(n->as_Vector()->length() == 2);
10773 match(Set dst (ReplicateI con));
10774 effect(KILL tmp);
10775 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10776 ins_encode %{
10777 // XXX This is a quick fix for 6833573.
10778 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10779 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10780 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10781 %}
10782 ins_pipe(loadConFD);
10783 %}
10784
10785 // Replicate scalar to packed float values into Double stack
10786 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10787 predicate(n->as_Vector()->length() == 2);
10788 match(Set dst (ReplicateF src));
10789 ins_cost(MEMORY_REF_COST*2);
10790 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10791 "STF $src,$dst.lo" %}
10792 opcode(Assembler::stf_op3);
10793 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10794 ins_pipe(fstoreF_stk_reg);
10795 %}
10796
10797 // Replicate scalar zero constant to packed float values in Double register
10798 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10799 predicate(n->as_Vector()->length() == 2);
10800 match(Set dst (ReplicateF con));
10801 effect(KILL tmp);
10802 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10803 ins_encode %{
10804 // XXX This is a quick fix for 6833573.
10805 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10806 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10807 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10808 %}
10809 ins_pipe(loadConFD);
10810 %}
10811
10812 //----------PEEPHOLE RULES-----------------------------------------------------
10813 // These must follow all instruction definitions as they use the names
10814 // defined in the instructions definitions.
10815 //
10816 // peepmatch ( root_instr_name [preceding_instruction]* );
10817 //
10818 // peepconstraint %{
10819 // (instruction_number.operand_name relational_op instruction_number.operand_name
10820 // [, ...] );
10821 // // instruction numbers are zero-based using left to right order in peepmatch
10822 //
10823 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10824 // // provide an instruction_number.operand_name for each operand that appears
10825 // // in the replacement instruction's match rule
10826 //
10827 // ---------VM FLAGS---------------------------------------------------------
10828 //
10829 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10830 //
10831 // Each peephole rule is given an identifying number starting with zero and
10832 // increasing by one in the order seen by the parser. An individual peephole
10833 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10834 // on the command-line.
10835 //
10836 // ---------CURRENT LIMITATIONS----------------------------------------------
10837 //
10838 // Only match adjacent instructions in same basic block
10839 // Only equality constraints
10840 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10841 // Only one replacement instruction
10842 //
10843 // ---------EXAMPLE----------------------------------------------------------
10844 //
10845 // // pertinent parts of existing instructions in architecture description
10846 // instruct movI(eRegI dst, eRegI src) %{
10847 // match(Set dst (CopyI src));
10848 // %}
10849 //
10850 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10851 // match(Set dst (AddI dst src));
10852 // effect(KILL cr);
10853 // %}
10854 //
10855 // // Change (inc mov) to lea
10856 // peephole %{
10857 // // increment preceeded by register-register move
10858 // peepmatch ( incI_eReg movI );
10859 // // require that the destination register of the increment
10860 // // match the destination register of the move
10861 // peepconstraint ( 0.dst == 1.dst );
10862 // // construct a replacement instruction that sets
10863 // // the destination to ( move's source register + one )
10864 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10865 // %}
10866 //
10867
10868 // // Change load of spilled value to only a spill
10869 // instruct storeI(memory mem, eRegI src) %{
10870 // match(Set mem (StoreI mem src));
10871 // %}
10872 //
10873 // instruct loadI(eRegI dst, memory mem) %{
10874 // match(Set dst (LoadI mem));
10875 // %}
10876 //
10877 // peephole %{
10878 // peepmatch ( loadI storeI );
10879 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10880 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10881 // %}
10882
10883 //----------SMARTSPILL RULES---------------------------------------------------
10884 // These must follow all instruction definitions as they use the names
10885 // defined in the instructions definitions.
10886 //
10887 // SPARC will probably not have any of these rules due to RISC instruction set.
10888
10889 //----------PIPELINE-----------------------------------------------------------
10890 // Rules which define the behavior of the target architectures pipeline.