554 const int Matcher::min_vector_size(const BasicType bt) {
555 int max_size = max_vector_size(bt);
556 // Min size which can be loaded into vector is 4 bytes.
557 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
558 return MIN2(size,max_size);
559 }
560
561 // Vector ideal reg corresponding to specidied size in bytes
562 const int Matcher::vector_ideal_reg(int size) {
563 assert(MaxVectorSize >= size, "");
564 switch(size) {
565 case 4: return Op_VecS;
566 case 8: return Op_VecD;
567 case 16: return Op_VecX;
568 case 32: return Op_VecY;
569 }
570 ShouldNotReachHere();
571 return 0;
572 }
573
574 // x86 supports misaligned vectors store/load.
575 const bool Matcher::misaligned_vectors_ok() {
576 return !AlignVector; // can be changed by flag
577 }
578
579 // Helper methods for MachSpillCopyNode::implementation().
580 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
581 int src_hi, int dst_hi, uint ireg, outputStream* st) {
582 // In 64-bit VM size calculation is very complex. Emitting instructions
583 // into scratch buffer is used to get size in 64-bit VM.
584 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
585 assert(ireg == Op_VecS || // 32bit vector
586 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
587 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
588 "no non-adjacent vector moves" );
589 if (cbuf) {
590 MacroAssembler _masm(cbuf);
591 int offset = __ offset();
592 switch (ireg) {
593 case Op_VecS: // copy whole register
3741 match(Set dst (DivVD src1 src2));
3742 format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %}
3743 ins_encode %{
3744 bool vector256 = true;
3745 __ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256);
3746 %}
3747 ins_pipe( pipe_slow );
3748 %}
3749
3750 instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{
3751 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3752 match(Set dst (DivVD src (LoadVector mem)));
3753 format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %}
3754 ins_encode %{
3755 bool vector256 = true;
3756 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
3757 %}
3758 ins_pipe( pipe_slow );
3759 %}
3760
3761 // ------------------------------ LeftShift -----------------------------------
3762
3763 // Shorts/Chars vector left shift
3764 instruct vsll2S(vecS dst, regF shift) %{
3765 predicate(n->as_Vector()->length() == 2);
3766 match(Set dst (LShiftVS dst shift));
3767 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3768 ins_encode %{
3769 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3770 %}
3771 ins_pipe( pipe_slow );
3772 %}
3773
3774 instruct vsll2S_imm(vecS dst, immI8 shift) %{
3775 predicate(n->as_Vector()->length() == 2);
3776 match(Set dst (LShiftVS dst shift));
3777 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3778 ins_encode %{
3779 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3780 %}
3781 ins_pipe( pipe_slow );
3782 %}
3783
3784 instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{
3785 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3786 match(Set dst (LShiftVS src shift));
3787 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3788 ins_encode %{
3789 bool vector256 = false;
3790 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3791 %}
3792 ins_pipe( pipe_slow );
3793 %}
3794
3795 instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
3796 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3797 match(Set dst (LShiftVS src shift));
3798 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3799 ins_encode %{
3800 bool vector256 = false;
3801 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3802 %}
3803 ins_pipe( pipe_slow );
3804 %}
3805
3806 instruct vsll4S(vecD dst, regF shift) %{
3807 predicate(n->as_Vector()->length() == 4);
3808 match(Set dst (LShiftVS dst shift));
3809 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3810 ins_encode %{
3811 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3812 %}
3813 ins_pipe( pipe_slow );
3814 %}
3815
3816 instruct vsll4S_imm(vecD dst, immI8 shift) %{
3817 predicate(n->as_Vector()->length() == 4);
3818 match(Set dst (LShiftVS dst shift));
3819 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3820 ins_encode %{
3821 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3822 %}
3823 ins_pipe( pipe_slow );
3824 %}
3825
3826 instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{
3827 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3828 match(Set dst (LShiftVS src shift));
3829 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3830 ins_encode %{
3831 bool vector256 = false;
3832 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3833 %}
3834 ins_pipe( pipe_slow );
3835 %}
3836
3837 instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
3838 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3839 match(Set dst (LShiftVS src shift));
3840 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3841 ins_encode %{
3842 bool vector256 = false;
3843 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3844 %}
3845 ins_pipe( pipe_slow );
3846 %}
3847
3848 instruct vsll8S(vecX dst, regF shift) %{
3849 predicate(n->as_Vector()->length() == 8);
3850 match(Set dst (LShiftVS dst shift));
3851 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3852 ins_encode %{
3853 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3854 %}
3855 ins_pipe( pipe_slow );
3856 %}
3857
3858 instruct vsll8S_imm(vecX dst, immI8 shift) %{
3859 predicate(n->as_Vector()->length() == 8);
3860 match(Set dst (LShiftVS dst shift));
3861 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3862 ins_encode %{
3863 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3864 %}
3865 ins_pipe( pipe_slow );
3866 %}
3867
3868 instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{
3869 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3870 match(Set dst (LShiftVS src shift));
3871 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3872 ins_encode %{
3873 bool vector256 = false;
3874 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3875 %}
3876 ins_pipe( pipe_slow );
3877 %}
3878
3879 instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
3880 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3881 match(Set dst (LShiftVS src shift));
3882 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3883 ins_encode %{
3884 bool vector256 = false;
3885 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3886 %}
3887 ins_pipe( pipe_slow );
3888 %}
3889
3890 instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{
3891 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3892 match(Set dst (LShiftVS src shift));
3893 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3894 ins_encode %{
3895 bool vector256 = true;
3896 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3897 %}
3898 ins_pipe( pipe_slow );
3899 %}
3900
3901 instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
3902 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3903 match(Set dst (LShiftVS src shift));
3904 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3905 ins_encode %{
3906 bool vector256 = true;
3907 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3908 %}
3909 ins_pipe( pipe_slow );
3910 %}
3911
3912 // Integers vector left shift
3913 instruct vsll2I(vecD dst, regF shift) %{
3914 predicate(n->as_Vector()->length() == 2);
3915 match(Set dst (LShiftVI dst shift));
3916 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3917 ins_encode %{
3918 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3919 %}
3920 ins_pipe( pipe_slow );
3921 %}
3922
3923 instruct vsll2I_imm(vecD dst, immI8 shift) %{
3924 predicate(n->as_Vector()->length() == 2);
3925 match(Set dst (LShiftVI dst shift));
3926 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3927 ins_encode %{
3928 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3929 %}
3930 ins_pipe( pipe_slow );
3931 %}
3932
3933 instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{
3934 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3935 match(Set dst (LShiftVI src shift));
3936 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3937 ins_encode %{
3938 bool vector256 = false;
3939 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3940 %}
3941 ins_pipe( pipe_slow );
3942 %}
3943
3944 instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
3945 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3946 match(Set dst (LShiftVI src shift));
3947 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3948 ins_encode %{
3949 bool vector256 = false;
3950 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3951 %}
3952 ins_pipe( pipe_slow );
3953 %}
3954
3955 instruct vsll4I(vecX dst, regF shift) %{
3956 predicate(n->as_Vector()->length() == 4);
3957 match(Set dst (LShiftVI dst shift));
3958 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3959 ins_encode %{
3960 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3961 %}
3962 ins_pipe( pipe_slow );
3963 %}
3964
3965 instruct vsll4I_imm(vecX dst, immI8 shift) %{
3966 predicate(n->as_Vector()->length() == 4);
3967 match(Set dst (LShiftVI dst shift));
3968 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3969 ins_encode %{
3970 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3971 %}
3972 ins_pipe( pipe_slow );
3973 %}
3974
3975 instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{
3976 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3977 match(Set dst (LShiftVI src shift));
3978 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3979 ins_encode %{
3980 bool vector256 = false;
3981 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3982 %}
3983 ins_pipe( pipe_slow );
3984 %}
3985
3986 instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
3987 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3988 match(Set dst (LShiftVI src shift));
3989 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3990 ins_encode %{
3991 bool vector256 = false;
3992 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3993 %}
3994 ins_pipe( pipe_slow );
3995 %}
3996
3997 instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{
3998 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
3999 match(Set dst (LShiftVI src shift));
4000 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4001 ins_encode %{
4002 bool vector256 = true;
4003 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4004 %}
4005 ins_pipe( pipe_slow );
4006 %}
4007
4008 instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4009 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4010 match(Set dst (LShiftVI src shift));
4011 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4012 ins_encode %{
4013 bool vector256 = true;
4014 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4015 %}
4016 ins_pipe( pipe_slow );
4017 %}
4018
4019 // Longs vector left shift
4020 instruct vsll2L(vecX dst, regF shift) %{
4021 predicate(n->as_Vector()->length() == 2);
4022 match(Set dst (LShiftVL dst shift));
4023 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4024 ins_encode %{
4025 __ psllq($dst$$XMMRegister, $shift$$XMMRegister);
4026 %}
4027 ins_pipe( pipe_slow );
4028 %}
4029
4030 instruct vsll2L_imm(vecX dst, immI8 shift) %{
4031 predicate(n->as_Vector()->length() == 2);
4032 match(Set dst (LShiftVL dst shift));
4033 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4034 ins_encode %{
4035 __ psllq($dst$$XMMRegister, (int)$shift$$constant);
4036 %}
4037 ins_pipe( pipe_slow );
4038 %}
4039
4040 instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{
4041 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4042 match(Set dst (LShiftVL src shift));
4043 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4044 ins_encode %{
4045 bool vector256 = false;
4046 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4047 %}
4048 ins_pipe( pipe_slow );
4049 %}
4050
4051 instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4052 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4053 match(Set dst (LShiftVL src shift));
4054 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4055 ins_encode %{
4056 bool vector256 = false;
4057 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4058 %}
4059 ins_pipe( pipe_slow );
4060 %}
4061
4062 instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{
4063 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4064 match(Set dst (LShiftVL src shift));
4065 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4066 ins_encode %{
4067 bool vector256 = true;
4068 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4069 %}
4070 ins_pipe( pipe_slow );
4071 %}
4072
4073 instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4074 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4075 match(Set dst (LShiftVL src shift));
4076 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4077 ins_encode %{
4078 bool vector256 = true;
4079 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4080 %}
4081 ins_pipe( pipe_slow );
4082 %}
4083
4084 // ----------------------- LogicalRightShift -----------------------------------
4085
4086 // Shorts/Chars vector logical right shift produces incorrect Java result
4087 // for negative data because java code convert short value into int with
4088 // sign extension before a shift.
4089
4090 // Integers vector logical right shift
4091 instruct vsrl2I(vecD dst, regF shift) %{
4092 predicate(n->as_Vector()->length() == 2);
4093 match(Set dst (URShiftVI dst shift));
4094 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4095 ins_encode %{
4096 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4097 %}
4098 ins_pipe( pipe_slow );
4099 %}
4100
4101 instruct vsrl2I_imm(vecD dst, immI8 shift) %{
4102 predicate(n->as_Vector()->length() == 2);
4103 match(Set dst (URShiftVI dst shift));
4104 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4105 ins_encode %{
4106 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4107 %}
4108 ins_pipe( pipe_slow );
4109 %}
4110
4111 instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{
4112 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4113 match(Set dst (URShiftVI src shift));
4114 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4115 ins_encode %{
4116 bool vector256 = false;
4117 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4118 %}
4119 ins_pipe( pipe_slow );
4120 %}
4121
4122 instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4123 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4124 match(Set dst (URShiftVI src shift));
4125 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4126 ins_encode %{
4127 bool vector256 = false;
4128 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4129 %}
4130 ins_pipe( pipe_slow );
4131 %}
4132
4133 instruct vsrl4I(vecX dst, regF shift) %{
4134 predicate(n->as_Vector()->length() == 4);
4135 match(Set dst (URShiftVI dst shift));
4136 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4137 ins_encode %{
4138 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4139 %}
4140 ins_pipe( pipe_slow );
4141 %}
4142
4143 instruct vsrl4I_imm(vecX dst, immI8 shift) %{
4144 predicate(n->as_Vector()->length() == 4);
4145 match(Set dst (URShiftVI dst shift));
4146 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4147 ins_encode %{
4148 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4149 %}
4150 ins_pipe( pipe_slow );
4151 %}
4152
4153 instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{
4154 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4155 match(Set dst (URShiftVI src shift));
4156 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4157 ins_encode %{
4158 bool vector256 = false;
4159 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4160 %}
4161 ins_pipe( pipe_slow );
4162 %}
4163
4164 instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4165 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4166 match(Set dst (URShiftVI src shift));
4167 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4168 ins_encode %{
4169 bool vector256 = false;
4170 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4171 %}
4172 ins_pipe( pipe_slow );
4173 %}
4174
4175 instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{
4176 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4177 match(Set dst (URShiftVI src shift));
4178 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4179 ins_encode %{
4180 bool vector256 = true;
4181 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4182 %}
4183 ins_pipe( pipe_slow );
4184 %}
4185
4186 instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4187 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4188 match(Set dst (URShiftVI src shift));
4189 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4190 ins_encode %{
4191 bool vector256 = true;
4192 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4193 %}
4194 ins_pipe( pipe_slow );
4195 %}
4196
4197 // Longs vector logical right shift
4198 instruct vsrl2L(vecX dst, regF shift) %{
4199 predicate(n->as_Vector()->length() == 2);
4200 match(Set dst (URShiftVL dst shift));
4201 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4202 ins_encode %{
4203 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
4204 %}
4205 ins_pipe( pipe_slow );
4206 %}
4207
4208 instruct vsrl2L_imm(vecX dst, immI8 shift) %{
4209 predicate(n->as_Vector()->length() == 2);
4210 match(Set dst (URShiftVL dst shift));
4211 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4212 ins_encode %{
4213 __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
4214 %}
4215 ins_pipe( pipe_slow );
4216 %}
4217
4218 instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{
4219 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4220 match(Set dst (URShiftVL src shift));
4221 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4222 ins_encode %{
4223 bool vector256 = false;
4224 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4225 %}
4226 ins_pipe( pipe_slow );
4227 %}
4228
4229 instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4230 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4231 match(Set dst (URShiftVL src shift));
4232 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4233 ins_encode %{
4234 bool vector256 = false;
4235 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4236 %}
4237 ins_pipe( pipe_slow );
4238 %}
4239
4240 instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{
4241 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4242 match(Set dst (URShiftVL src shift));
4243 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4244 ins_encode %{
4245 bool vector256 = true;
4246 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4247 %}
4248 ins_pipe( pipe_slow );
4249 %}
4250
4251 instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4252 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4253 match(Set dst (URShiftVL src shift));
4254 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4255 ins_encode %{
4256 bool vector256 = true;
4257 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4258 %}
4259 ins_pipe( pipe_slow );
4260 %}
4261
4262 // ------------------- ArithmeticRightShift -----------------------------------
4263
4264 // Shorts/Chars vector arithmetic right shift
4265 instruct vsra2S(vecS dst, regF shift) %{
4266 predicate(n->as_Vector()->length() == 2);
4267 match(Set dst (RShiftVS dst shift));
4268 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4269 ins_encode %{
4270 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4271 %}
4272 ins_pipe( pipe_slow );
4273 %}
4274
4275 instruct vsra2S_imm(vecS dst, immI8 shift) %{
4276 predicate(n->as_Vector()->length() == 2);
4277 match(Set dst (RShiftVS dst shift));
4278 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4279 ins_encode %{
4280 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4281 %}
4282 ins_pipe( pipe_slow );
4283 %}
4284
4285 instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{
4286 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4287 match(Set dst (RShiftVS src shift));
4288 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4289 ins_encode %{
4290 bool vector256 = false;
4291 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4292 %}
4293 ins_pipe( pipe_slow );
4294 %}
4295
4296 instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
4297 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4298 match(Set dst (RShiftVS src shift));
4299 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4300 ins_encode %{
4301 bool vector256 = false;
4302 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4303 %}
4304 ins_pipe( pipe_slow );
4305 %}
4306
4307 instruct vsra4S(vecD dst, regF shift) %{
4308 predicate(n->as_Vector()->length() == 4);
4309 match(Set dst (RShiftVS dst shift));
4310 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4311 ins_encode %{
4312 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4313 %}
4314 ins_pipe( pipe_slow );
4315 %}
4316
4317 instruct vsra4S_imm(vecD dst, immI8 shift) %{
4318 predicate(n->as_Vector()->length() == 4);
4319 match(Set dst (RShiftVS dst shift));
4320 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4321 ins_encode %{
4322 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4323 %}
4324 ins_pipe( pipe_slow );
4325 %}
4326
4327 instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{
4328 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4329 match(Set dst (RShiftVS src shift));
4330 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4331 ins_encode %{
4332 bool vector256 = false;
4333 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4334 %}
4335 ins_pipe( pipe_slow );
4336 %}
4337
4338 instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
4339 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4340 match(Set dst (RShiftVS src shift));
4341 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4342 ins_encode %{
4343 bool vector256 = false;
4344 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4345 %}
4346 ins_pipe( pipe_slow );
4347 %}
4348
4349 instruct vsra8S(vecX dst, regF shift) %{
4350 predicate(n->as_Vector()->length() == 8);
4351 match(Set dst (RShiftVS dst shift));
4352 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4353 ins_encode %{
4354 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4355 %}
4356 ins_pipe( pipe_slow );
4357 %}
4358
4359 instruct vsra8S_imm(vecX dst, immI8 shift) %{
4360 predicate(n->as_Vector()->length() == 8);
4361 match(Set dst (RShiftVS dst shift));
4362 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4363 ins_encode %{
4364 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4365 %}
4366 ins_pipe( pipe_slow );
4367 %}
4368
4369 instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{
4370 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4371 match(Set dst (RShiftVS src shift));
4372 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4373 ins_encode %{
4374 bool vector256 = false;
4375 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4376 %}
4377 ins_pipe( pipe_slow );
4378 %}
4379
4380 instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
4381 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4382 match(Set dst (RShiftVS src shift));
4383 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4384 ins_encode %{
4385 bool vector256 = false;
4386 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4387 %}
4388 ins_pipe( pipe_slow );
4389 %}
4390
4391 instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{
4392 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4393 match(Set dst (RShiftVS src shift));
4394 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4395 ins_encode %{
4396 bool vector256 = true;
4397 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4398 %}
4399 ins_pipe( pipe_slow );
4400 %}
4401
4402 instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
4403 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4404 match(Set dst (RShiftVS src shift));
4405 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4406 ins_encode %{
4407 bool vector256 = true;
4408 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4409 %}
4410 ins_pipe( pipe_slow );
4411 %}
4412
4413 // Integers vector arithmetic right shift
4414 instruct vsra2I(vecD dst, regF shift) %{
4415 predicate(n->as_Vector()->length() == 2);
4416 match(Set dst (RShiftVI dst shift));
4417 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4418 ins_encode %{
4419 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4420 %}
4421 ins_pipe( pipe_slow );
4422 %}
4423
4424 instruct vsra2I_imm(vecD dst, immI8 shift) %{
4425 predicate(n->as_Vector()->length() == 2);
4426 match(Set dst (RShiftVI dst shift));
4427 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4428 ins_encode %{
4429 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4430 %}
4431 ins_pipe( pipe_slow );
4432 %}
4433
4434 instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{
4435 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4436 match(Set dst (RShiftVI src shift));
4437 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4438 ins_encode %{
4439 bool vector256 = false;
4440 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4441 %}
4442 ins_pipe( pipe_slow );
4443 %}
4444
4445 instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4446 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4447 match(Set dst (RShiftVI src shift));
4448 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4449 ins_encode %{
4450 bool vector256 = false;
4451 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4452 %}
4453 ins_pipe( pipe_slow );
4454 %}
4455
4456 instruct vsra4I(vecX dst, regF shift) %{
4457 predicate(n->as_Vector()->length() == 4);
4458 match(Set dst (RShiftVI dst shift));
4459 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4460 ins_encode %{
4461 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4462 %}
4463 ins_pipe( pipe_slow );
4464 %}
4465
4466 instruct vsra4I_imm(vecX dst, immI8 shift) %{
4467 predicate(n->as_Vector()->length() == 4);
4468 match(Set dst (RShiftVI dst shift));
4469 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4470 ins_encode %{
4471 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4472 %}
4473 ins_pipe( pipe_slow );
4474 %}
4475
4476 instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{
4477 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4478 match(Set dst (RShiftVI src shift));
4479 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4480 ins_encode %{
4481 bool vector256 = false;
4482 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4483 %}
4484 ins_pipe( pipe_slow );
4485 %}
4486
4487 instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4488 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4489 match(Set dst (RShiftVI src shift));
4490 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4491 ins_encode %{
4492 bool vector256 = false;
4493 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4494 %}
4495 ins_pipe( pipe_slow );
4496 %}
4497
4498 instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{
4499 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4500 match(Set dst (RShiftVI src shift));
4501 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4502 ins_encode %{
4503 bool vector256 = true;
4504 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4505 %}
4506 ins_pipe( pipe_slow );
4507 %}
4508
4509 instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4510 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4511 match(Set dst (RShiftVI src shift));
4512 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4513 ins_encode %{
4514 bool vector256 = true;
4515 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4516 %}
4517 ins_pipe( pipe_slow );
4518 %}
|
554 const int Matcher::min_vector_size(const BasicType bt) {
555 int max_size = max_vector_size(bt);
556 // Min size which can be loaded into vector is 4 bytes.
557 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
558 return MIN2(size,max_size);
559 }
560
561 // Vector ideal reg corresponding to specidied size in bytes
562 const int Matcher::vector_ideal_reg(int size) {
563 assert(MaxVectorSize >= size, "");
564 switch(size) {
565 case 4: return Op_VecS;
566 case 8: return Op_VecD;
567 case 16: return Op_VecX;
568 case 32: return Op_VecY;
569 }
570 ShouldNotReachHere();
571 return 0;
572 }
573
574 // Only lowest bits of xmm reg are used for vector shift count.
575 const int Matcher::vector_shift_count_ideal_reg(int size) {
576 return Op_VecS;
577 }
578
579 // x86 supports misaligned vectors store/load.
580 const bool Matcher::misaligned_vectors_ok() {
581 return !AlignVector; // can be changed by flag
582 }
583
584 // Helper methods for MachSpillCopyNode::implementation().
585 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
586 int src_hi, int dst_hi, uint ireg, outputStream* st) {
587 // In 64-bit VM size calculation is very complex. Emitting instructions
588 // into scratch buffer is used to get size in 64-bit VM.
589 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
590 assert(ireg == Op_VecS || // 32bit vector
591 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
592 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
593 "no non-adjacent vector moves" );
594 if (cbuf) {
595 MacroAssembler _masm(cbuf);
596 int offset = __ offset();
597 switch (ireg) {
598 case Op_VecS: // copy whole register
3746 match(Set dst (DivVD src1 src2));
3747 format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %}
3748 ins_encode %{
3749 bool vector256 = true;
3750 __ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256);
3751 %}
3752 ins_pipe( pipe_slow );
3753 %}
3754
3755 instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{
3756 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3757 match(Set dst (DivVD src (LoadVector mem)));
3758 format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %}
3759 ins_encode %{
3760 bool vector256 = true;
3761 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
3762 %}
3763 ins_pipe( pipe_slow );
3764 %}
3765
3766 // ------------------------------ Shift ---------------------------------------
3767
3768 // Left and right shift count vectors are the same on x86
3769 // (only lowest bits of xmm reg are used for count).
3770 instruct vshiftcnt(vecS dst, rRegI cnt) %{
3771 match(Set dst (LShiftCntV cnt));
3772 match(Set dst (RShiftCntV cnt));
3773 format %{ "movd $dst,$cnt\t! load shift count" %}
3774 ins_encode %{
3775 __ movdl($dst$$XMMRegister, $cnt$$Register);
3776 %}
3777 ins_pipe( pipe_slow );
3778 %}
3779
3780 // ------------------------------ LeftShift -----------------------------------
3781
3782 // Shorts/Chars vector left shift
3783 instruct vsll2S(vecS dst, vecS shift) %{
3784 predicate(n->as_Vector()->length() == 2);
3785 match(Set dst (LShiftVS dst shift));
3786 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3787 ins_encode %{
3788 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3789 %}
3790 ins_pipe( pipe_slow );
3791 %}
3792
3793 instruct vsll2S_imm(vecS dst, immI8 shift) %{
3794 predicate(n->as_Vector()->length() == 2);
3795 match(Set dst (LShiftVS dst shift));
3796 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3797 ins_encode %{
3798 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3799 %}
3800 ins_pipe( pipe_slow );
3801 %}
3802
3803 instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
3804 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3805 match(Set dst (LShiftVS src shift));
3806 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3807 ins_encode %{
3808 bool vector256 = false;
3809 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3810 %}
3811 ins_pipe( pipe_slow );
3812 %}
3813
3814 instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
3815 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3816 match(Set dst (LShiftVS src shift));
3817 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3818 ins_encode %{
3819 bool vector256 = false;
3820 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3821 %}
3822 ins_pipe( pipe_slow );
3823 %}
3824
3825 instruct vsll4S(vecD dst, vecS shift) %{
3826 predicate(n->as_Vector()->length() == 4);
3827 match(Set dst (LShiftVS dst shift));
3828 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3829 ins_encode %{
3830 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3831 %}
3832 ins_pipe( pipe_slow );
3833 %}
3834
3835 instruct vsll4S_imm(vecD dst, immI8 shift) %{
3836 predicate(n->as_Vector()->length() == 4);
3837 match(Set dst (LShiftVS dst shift));
3838 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3839 ins_encode %{
3840 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3841 %}
3842 ins_pipe( pipe_slow );
3843 %}
3844
3845 instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
3846 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3847 match(Set dst (LShiftVS src shift));
3848 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3849 ins_encode %{
3850 bool vector256 = false;
3851 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3852 %}
3853 ins_pipe( pipe_slow );
3854 %}
3855
3856 instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
3857 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3858 match(Set dst (LShiftVS src shift));
3859 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3860 ins_encode %{
3861 bool vector256 = false;
3862 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3863 %}
3864 ins_pipe( pipe_slow );
3865 %}
3866
3867 instruct vsll8S(vecX dst, vecS shift) %{
3868 predicate(n->as_Vector()->length() == 8);
3869 match(Set dst (LShiftVS dst shift));
3870 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3871 ins_encode %{
3872 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3873 %}
3874 ins_pipe( pipe_slow );
3875 %}
3876
3877 instruct vsll8S_imm(vecX dst, immI8 shift) %{
3878 predicate(n->as_Vector()->length() == 8);
3879 match(Set dst (LShiftVS dst shift));
3880 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3881 ins_encode %{
3882 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3883 %}
3884 ins_pipe( pipe_slow );
3885 %}
3886
3887 instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
3888 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3889 match(Set dst (LShiftVS src shift));
3890 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3891 ins_encode %{
3892 bool vector256 = false;
3893 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3894 %}
3895 ins_pipe( pipe_slow );
3896 %}
3897
3898 instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
3899 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3900 match(Set dst (LShiftVS src shift));
3901 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3902 ins_encode %{
3903 bool vector256 = false;
3904 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3905 %}
3906 ins_pipe( pipe_slow );
3907 %}
3908
3909 instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
3910 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3911 match(Set dst (LShiftVS src shift));
3912 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3913 ins_encode %{
3914 bool vector256 = true;
3915 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3916 %}
3917 ins_pipe( pipe_slow );
3918 %}
3919
3920 instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
3921 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3922 match(Set dst (LShiftVS src shift));
3923 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3924 ins_encode %{
3925 bool vector256 = true;
3926 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3927 %}
3928 ins_pipe( pipe_slow );
3929 %}
3930
3931 // Integers vector left shift
3932 instruct vsll2I(vecD dst, vecS shift) %{
3933 predicate(n->as_Vector()->length() == 2);
3934 match(Set dst (LShiftVI dst shift));
3935 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3936 ins_encode %{
3937 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3938 %}
3939 ins_pipe( pipe_slow );
3940 %}
3941
3942 instruct vsll2I_imm(vecD dst, immI8 shift) %{
3943 predicate(n->as_Vector()->length() == 2);
3944 match(Set dst (LShiftVI dst shift));
3945 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3946 ins_encode %{
3947 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3948 %}
3949 ins_pipe( pipe_slow );
3950 %}
3951
3952 instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
3953 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3954 match(Set dst (LShiftVI src shift));
3955 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3956 ins_encode %{
3957 bool vector256 = false;
3958 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3959 %}
3960 ins_pipe( pipe_slow );
3961 %}
3962
3963 instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
3964 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3965 match(Set dst (LShiftVI src shift));
3966 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3967 ins_encode %{
3968 bool vector256 = false;
3969 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3970 %}
3971 ins_pipe( pipe_slow );
3972 %}
3973
3974 instruct vsll4I(vecX dst, vecS shift) %{
3975 predicate(n->as_Vector()->length() == 4);
3976 match(Set dst (LShiftVI dst shift));
3977 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3978 ins_encode %{
3979 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3980 %}
3981 ins_pipe( pipe_slow );
3982 %}
3983
3984 instruct vsll4I_imm(vecX dst, immI8 shift) %{
3985 predicate(n->as_Vector()->length() == 4);
3986 match(Set dst (LShiftVI dst shift));
3987 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3988 ins_encode %{
3989 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3990 %}
3991 ins_pipe( pipe_slow );
3992 %}
3993
3994 instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
3995 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3996 match(Set dst (LShiftVI src shift));
3997 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3998 ins_encode %{
3999 bool vector256 = false;
4000 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4001 %}
4002 ins_pipe( pipe_slow );
4003 %}
4004
4005 instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4006 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4007 match(Set dst (LShiftVI src shift));
4008 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
4009 ins_encode %{
4010 bool vector256 = false;
4011 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4012 %}
4013 ins_pipe( pipe_slow );
4014 %}
4015
4016 instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
4017 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4018 match(Set dst (LShiftVI src shift));
4019 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4020 ins_encode %{
4021 bool vector256 = true;
4022 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4023 %}
4024 ins_pipe( pipe_slow );
4025 %}
4026
4027 instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4028 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4029 match(Set dst (LShiftVI src shift));
4030 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4031 ins_encode %{
4032 bool vector256 = true;
4033 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4034 %}
4035 ins_pipe( pipe_slow );
4036 %}
4037
4038 // Longs vector left shift
4039 instruct vsll2L(vecX dst, vecS shift) %{
4040 predicate(n->as_Vector()->length() == 2);
4041 match(Set dst (LShiftVL dst shift));
4042 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4043 ins_encode %{
4044 __ psllq($dst$$XMMRegister, $shift$$XMMRegister);
4045 %}
4046 ins_pipe( pipe_slow );
4047 %}
4048
4049 instruct vsll2L_imm(vecX dst, immI8 shift) %{
4050 predicate(n->as_Vector()->length() == 2);
4051 match(Set dst (LShiftVL dst shift));
4052 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4053 ins_encode %{
4054 __ psllq($dst$$XMMRegister, (int)$shift$$constant);
4055 %}
4056 ins_pipe( pipe_slow );
4057 %}
4058
4059 instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
4060 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4061 match(Set dst (LShiftVL src shift));
4062 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4063 ins_encode %{
4064 bool vector256 = false;
4065 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4066 %}
4067 ins_pipe( pipe_slow );
4068 %}
4069
4070 instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4071 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4072 match(Set dst (LShiftVL src shift));
4073 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4074 ins_encode %{
4075 bool vector256 = false;
4076 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4077 %}
4078 ins_pipe( pipe_slow );
4079 %}
4080
4081 instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
4082 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4083 match(Set dst (LShiftVL src shift));
4084 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4085 ins_encode %{
4086 bool vector256 = true;
4087 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4088 %}
4089 ins_pipe( pipe_slow );
4090 %}
4091
4092 instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4093 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4094 match(Set dst (LShiftVL src shift));
4095 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4096 ins_encode %{
4097 bool vector256 = true;
4098 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4099 %}
4100 ins_pipe( pipe_slow );
4101 %}
4102
4103 // ----------------------- LogicalRightShift -----------------------------------
4104
4105 // Shorts/Chars vector logical right shift produces incorrect Java result
4106 // for negative data because java code convert short value into int with
4107 // sign extension before a shift.
4108
4109 // Integers vector logical right shift
4110 instruct vsrl2I(vecD dst, vecS shift) %{
4111 predicate(n->as_Vector()->length() == 2);
4112 match(Set dst (URShiftVI dst shift));
4113 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4114 ins_encode %{
4115 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4116 %}
4117 ins_pipe( pipe_slow );
4118 %}
4119
4120 instruct vsrl2I_imm(vecD dst, immI8 shift) %{
4121 predicate(n->as_Vector()->length() == 2);
4122 match(Set dst (URShiftVI dst shift));
4123 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4124 ins_encode %{
4125 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4126 %}
4127 ins_pipe( pipe_slow );
4128 %}
4129
4130 instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
4131 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4132 match(Set dst (URShiftVI src shift));
4133 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4134 ins_encode %{
4135 bool vector256 = false;
4136 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4137 %}
4138 ins_pipe( pipe_slow );
4139 %}
4140
4141 instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4142 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4143 match(Set dst (URShiftVI src shift));
4144 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4145 ins_encode %{
4146 bool vector256 = false;
4147 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4148 %}
4149 ins_pipe( pipe_slow );
4150 %}
4151
4152 instruct vsrl4I(vecX dst, vecS shift) %{
4153 predicate(n->as_Vector()->length() == 4);
4154 match(Set dst (URShiftVI dst shift));
4155 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4156 ins_encode %{
4157 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4158 %}
4159 ins_pipe( pipe_slow );
4160 %}
4161
4162 instruct vsrl4I_imm(vecX dst, immI8 shift) %{
4163 predicate(n->as_Vector()->length() == 4);
4164 match(Set dst (URShiftVI dst shift));
4165 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4166 ins_encode %{
4167 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4168 %}
4169 ins_pipe( pipe_slow );
4170 %}
4171
4172 instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
4173 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4174 match(Set dst (URShiftVI src shift));
4175 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4176 ins_encode %{
4177 bool vector256 = false;
4178 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4179 %}
4180 ins_pipe( pipe_slow );
4181 %}
4182
4183 instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4184 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4185 match(Set dst (URShiftVI src shift));
4186 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4187 ins_encode %{
4188 bool vector256 = false;
4189 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4190 %}
4191 ins_pipe( pipe_slow );
4192 %}
4193
4194 instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
4195 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4196 match(Set dst (URShiftVI src shift));
4197 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4198 ins_encode %{
4199 bool vector256 = true;
4200 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4201 %}
4202 ins_pipe( pipe_slow );
4203 %}
4204
4205 instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4206 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4207 match(Set dst (URShiftVI src shift));
4208 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4209 ins_encode %{
4210 bool vector256 = true;
4211 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4212 %}
4213 ins_pipe( pipe_slow );
4214 %}
4215
4216 // Longs vector logical right shift
4217 instruct vsrl2L(vecX dst, vecS shift) %{
4218 predicate(n->as_Vector()->length() == 2);
4219 match(Set dst (URShiftVL dst shift));
4220 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4221 ins_encode %{
4222 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
4223 %}
4224 ins_pipe( pipe_slow );
4225 %}
4226
4227 instruct vsrl2L_imm(vecX dst, immI8 shift) %{
4228 predicate(n->as_Vector()->length() == 2);
4229 match(Set dst (URShiftVL dst shift));
4230 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4231 ins_encode %{
4232 __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
4233 %}
4234 ins_pipe( pipe_slow );
4235 %}
4236
4237 instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
4238 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4239 match(Set dst (URShiftVL src shift));
4240 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4241 ins_encode %{
4242 bool vector256 = false;
4243 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4244 %}
4245 ins_pipe( pipe_slow );
4246 %}
4247
4248 instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4249 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4250 match(Set dst (URShiftVL src shift));
4251 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4252 ins_encode %{
4253 bool vector256 = false;
4254 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4255 %}
4256 ins_pipe( pipe_slow );
4257 %}
4258
4259 instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
4260 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4261 match(Set dst (URShiftVL src shift));
4262 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4263 ins_encode %{
4264 bool vector256 = true;
4265 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4266 %}
4267 ins_pipe( pipe_slow );
4268 %}
4269
4270 instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4271 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4272 match(Set dst (URShiftVL src shift));
4273 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4274 ins_encode %{
4275 bool vector256 = true;
4276 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4277 %}
4278 ins_pipe( pipe_slow );
4279 %}
4280
4281 // ------------------- ArithmeticRightShift -----------------------------------
4282
4283 // Shorts/Chars vector arithmetic right shift
4284 instruct vsra2S(vecS dst, vecS shift) %{
4285 predicate(n->as_Vector()->length() == 2);
4286 match(Set dst (RShiftVS dst shift));
4287 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4288 ins_encode %{
4289 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4290 %}
4291 ins_pipe( pipe_slow );
4292 %}
4293
4294 instruct vsra2S_imm(vecS dst, immI8 shift) %{
4295 predicate(n->as_Vector()->length() == 2);
4296 match(Set dst (RShiftVS dst shift));
4297 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4298 ins_encode %{
4299 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4300 %}
4301 ins_pipe( pipe_slow );
4302 %}
4303
4304 instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
4305 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4306 match(Set dst (RShiftVS src shift));
4307 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4308 ins_encode %{
4309 bool vector256 = false;
4310 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4311 %}
4312 ins_pipe( pipe_slow );
4313 %}
4314
4315 instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
4316 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4317 match(Set dst (RShiftVS src shift));
4318 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4319 ins_encode %{
4320 bool vector256 = false;
4321 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4322 %}
4323 ins_pipe( pipe_slow );
4324 %}
4325
4326 instruct vsra4S(vecD dst, vecS shift) %{
4327 predicate(n->as_Vector()->length() == 4);
4328 match(Set dst (RShiftVS dst shift));
4329 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4330 ins_encode %{
4331 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4332 %}
4333 ins_pipe( pipe_slow );
4334 %}
4335
4336 instruct vsra4S_imm(vecD dst, immI8 shift) %{
4337 predicate(n->as_Vector()->length() == 4);
4338 match(Set dst (RShiftVS dst shift));
4339 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4340 ins_encode %{
4341 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4342 %}
4343 ins_pipe( pipe_slow );
4344 %}
4345
4346 instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
4347 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4348 match(Set dst (RShiftVS src shift));
4349 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4350 ins_encode %{
4351 bool vector256 = false;
4352 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4353 %}
4354 ins_pipe( pipe_slow );
4355 %}
4356
4357 instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
4358 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4359 match(Set dst (RShiftVS src shift));
4360 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4361 ins_encode %{
4362 bool vector256 = false;
4363 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4364 %}
4365 ins_pipe( pipe_slow );
4366 %}
4367
4368 instruct vsra8S(vecX dst, vecS shift) %{
4369 predicate(n->as_Vector()->length() == 8);
4370 match(Set dst (RShiftVS dst shift));
4371 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4372 ins_encode %{
4373 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4374 %}
4375 ins_pipe( pipe_slow );
4376 %}
4377
4378 instruct vsra8S_imm(vecX dst, immI8 shift) %{
4379 predicate(n->as_Vector()->length() == 8);
4380 match(Set dst (RShiftVS dst shift));
4381 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4382 ins_encode %{
4383 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4384 %}
4385 ins_pipe( pipe_slow );
4386 %}
4387
4388 instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
4389 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4390 match(Set dst (RShiftVS src shift));
4391 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4392 ins_encode %{
4393 bool vector256 = false;
4394 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4395 %}
4396 ins_pipe( pipe_slow );
4397 %}
4398
4399 instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
4400 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4401 match(Set dst (RShiftVS src shift));
4402 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4403 ins_encode %{
4404 bool vector256 = false;
4405 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4406 %}
4407 ins_pipe( pipe_slow );
4408 %}
4409
4410 instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
4411 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4412 match(Set dst (RShiftVS src shift));
4413 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4414 ins_encode %{
4415 bool vector256 = true;
4416 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4417 %}
4418 ins_pipe( pipe_slow );
4419 %}
4420
4421 instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
4422 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4423 match(Set dst (RShiftVS src shift));
4424 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4425 ins_encode %{
4426 bool vector256 = true;
4427 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4428 %}
4429 ins_pipe( pipe_slow );
4430 %}
4431
4432 // Integers vector arithmetic right shift
4433 instruct vsra2I(vecD dst, vecS shift) %{
4434 predicate(n->as_Vector()->length() == 2);
4435 match(Set dst (RShiftVI dst shift));
4436 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4437 ins_encode %{
4438 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4439 %}
4440 ins_pipe( pipe_slow );
4441 %}
4442
4443 instruct vsra2I_imm(vecD dst, immI8 shift) %{
4444 predicate(n->as_Vector()->length() == 2);
4445 match(Set dst (RShiftVI dst shift));
4446 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4447 ins_encode %{
4448 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4449 %}
4450 ins_pipe( pipe_slow );
4451 %}
4452
4453 instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
4454 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4455 match(Set dst (RShiftVI src shift));
4456 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4457 ins_encode %{
4458 bool vector256 = false;
4459 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4460 %}
4461 ins_pipe( pipe_slow );
4462 %}
4463
4464 instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4465 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4466 match(Set dst (RShiftVI src shift));
4467 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4468 ins_encode %{
4469 bool vector256 = false;
4470 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4471 %}
4472 ins_pipe( pipe_slow );
4473 %}
4474
4475 instruct vsra4I(vecX dst, vecS shift) %{
4476 predicate(n->as_Vector()->length() == 4);
4477 match(Set dst (RShiftVI dst shift));
4478 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4479 ins_encode %{
4480 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4481 %}
4482 ins_pipe( pipe_slow );
4483 %}
4484
4485 instruct vsra4I_imm(vecX dst, immI8 shift) %{
4486 predicate(n->as_Vector()->length() == 4);
4487 match(Set dst (RShiftVI dst shift));
4488 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4489 ins_encode %{
4490 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4491 %}
4492 ins_pipe( pipe_slow );
4493 %}
4494
4495 instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
4496 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4497 match(Set dst (RShiftVI src shift));
4498 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4499 ins_encode %{
4500 bool vector256 = false;
4501 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4502 %}
4503 ins_pipe( pipe_slow );
4504 %}
4505
4506 instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4507 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4508 match(Set dst (RShiftVI src shift));
4509 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4510 ins_encode %{
4511 bool vector256 = false;
4512 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4513 %}
4514 ins_pipe( pipe_slow );
4515 %}
4516
4517 instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
4518 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4519 match(Set dst (RShiftVI src shift));
4520 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4521 ins_encode %{
4522 bool vector256 = true;
4523 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4524 %}
4525 ins_pipe( pipe_slow );
4526 %}
4527
4528 instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4529 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4530 match(Set dst (RShiftVI src shift));
4531 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4532 ins_encode %{
4533 bool vector256 = true;
4534 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4535 %}
4536 ins_pipe( pipe_slow );
4537 %}
|