*** old/src/cpu/x86/vm/x86.ad	Mon Oct  1 15:59:04 2012
--- new/src/cpu/x86/vm/x86.ad	Mon Oct  1 15:59:04 2012

*** 569,578 ****
--- 569,583 ----
    }
    ShouldNotReachHere();
    return 0;
  }
  
+ // Only lowest bits of xmm reg are used for vector shift count.
+ const int Matcher::vector_shift_count_ideal_reg(int size) {
+   return Op_VecS;
+ }
+ 
  // x86 supports misaligned vectors store/load.
  const bool Matcher::misaligned_vectors_ok() {
    return !AlignVector; // can be changed by flag
  }
  

*** 3756,3769 ****
--- 3761,3788 ----
      __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
+ // ------------------------------ Shift ---------------------------------------
+ 
+ // Left and right shift count vectors are the same on x86
+ // (only lowest bits of xmm reg are used for count).
+ instruct vshiftcnt(vecS dst, rRegI cnt) %{
+   match(Set dst (LShiftCntV cnt));
+   match(Set dst (RShiftCntV cnt));
+   format %{ "movd    $dst,$cnt\t! load shift count" %}
+   ins_encode %{
+     __ movdl($dst$$XMMRegister, $cnt$$Register);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
  // ------------------------------ LeftShift -----------------------------------
  
  // Shorts/Chars vector left shift
! instruct vsll2S(vecS dst, regF shift) %{
! instruct vsll2S(vecS dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (LShiftVS dst shift));
    format %{ "psllw   $dst,$shift\t! left shift packed2S" %}
    ins_encode %{
      __ psllw($dst$$XMMRegister, $shift$$XMMRegister);

*** 3779,3789 ****
--- 3798,3808 ----
      __ psllw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{
! instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (LShiftVS src shift));
    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed2S" %}
    ins_encode %{
      bool vector256 = false;

*** 3801,3811 ****
--- 3820,3830 ----
      __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll4S(vecD dst, regF shift) %{
! instruct vsll4S(vecD dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 4);
    match(Set dst (LShiftVS dst shift));
    format %{ "psllw   $dst,$shift\t! left shift packed4S" %}
    ins_encode %{
      __ psllw($dst$$XMMRegister, $shift$$XMMRegister);

*** 3821,3831 ****
--- 3840,3850 ----
      __ psllw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{
! instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    match(Set dst (LShiftVS src shift));
    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed4S" %}
    ins_encode %{
      bool vector256 = false;

*** 3843,3853 ****
--- 3862,3872 ----
      __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll8S(vecX dst, regF shift) %{
! instruct vsll8S(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 8);
    match(Set dst (LShiftVS dst shift));
    format %{ "psllw   $dst,$shift\t! left shift packed8S" %}
    ins_encode %{
      __ psllw($dst$$XMMRegister, $shift$$XMMRegister);

*** 3863,3873 ****
--- 3882,3892 ----
      __ psllw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{
! instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
    match(Set dst (LShiftVS src shift));
    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed8S" %}
    ins_encode %{
      bool vector256 = false;

*** 3885,3895 ****
--- 3904,3914 ----
      __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{
! instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
    match(Set dst (LShiftVS src shift));
    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed16S" %}
    ins_encode %{
      bool vector256 = true;

*** 3908,3918 ****
--- 3927,3937 ----
    %}
    ins_pipe( pipe_slow );
  %}
  
  // Integers vector left shift
! instruct vsll2I(vecD dst, regF shift) %{
! instruct vsll2I(vecD dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (LShiftVI dst shift));
    format %{ "pslld   $dst,$shift\t! left shift packed2I" %}
    ins_encode %{
      __ pslld($dst$$XMMRegister, $shift$$XMMRegister);

*** 3928,3938 ****
--- 3947,3957 ----
      __ pslld($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{
! instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (LShiftVI src shift));
    format %{ "vpslld  $dst,$src,$shift\t! left shift packed2I" %}
    ins_encode %{
      bool vector256 = false;

*** 3950,3960 ****
--- 3969,3979 ----
      __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll4I(vecX dst, regF shift) %{
! instruct vsll4I(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 4);
    match(Set dst (LShiftVI dst shift));
    format %{ "pslld   $dst,$shift\t! left shift packed4I" %}
    ins_encode %{
      __ pslld($dst$$XMMRegister, $shift$$XMMRegister);

*** 3970,3980 ****
--- 3989,3999 ----
      __ pslld($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{
! instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    match(Set dst (LShiftVI src shift));
    format %{ "vpslld  $dst,$src,$shift\t! left shift packed4I" %}
    ins_encode %{
      bool vector256 = false;

*** 3992,4002 ****
--- 4011,4021 ----
      __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{
! instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
    match(Set dst (LShiftVI src shift));
    format %{ "vpslld  $dst,$src,$shift\t! left shift packed8I" %}
    ins_encode %{
      bool vector256 = true;

*** 4015,4025 ****
--- 4034,4044 ----
    %}
    ins_pipe( pipe_slow );
  %}
  
  // Longs vector left shift
! instruct vsll2L(vecX dst, regF shift) %{
! instruct vsll2L(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (LShiftVL dst shift));
    format %{ "psllq   $dst,$shift\t! left shift packed2L" %}
    ins_encode %{
      __ psllq($dst$$XMMRegister, $shift$$XMMRegister);

*** 4035,4045 ****
--- 4054,4064 ----
      __ psllq($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{
! instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (LShiftVL src shift));
    format %{ "vpsllq  $dst,$src,$shift\t! left shift packed2L" %}
    ins_encode %{
      bool vector256 = false;

*** 4057,4067 ****
--- 4076,4086 ----
      __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{
! instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
    match(Set dst (LShiftVL src shift));
    format %{ "vpsllq  $dst,$src,$shift\t! left shift packed4L" %}
    ins_encode %{
      bool vector256 = true;

*** 4086,4096 ****
--- 4105,4115 ----
  // Shorts/Chars vector logical right shift produces incorrect Java result
  // for negative data because java code convert short value into int with
  // sign extension before a shift.
  
  // Integers vector logical right shift
! instruct vsrl2I(vecD dst, regF shift) %{
! instruct vsrl2I(vecD dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (URShiftVI dst shift));
    format %{ "psrld   $dst,$shift\t! logical right shift packed2I" %}
    ins_encode %{
      __ psrld($dst$$XMMRegister, $shift$$XMMRegister);

*** 4106,4116 ****
--- 4125,4135 ----
      __ psrld($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{
! instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (URShiftVI src shift));
    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed2I" %}
    ins_encode %{
      bool vector256 = false;

*** 4128,4138 ****
--- 4147,4157 ----
      __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl4I(vecX dst, regF shift) %{
! instruct vsrl4I(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 4);
    match(Set dst (URShiftVI dst shift));
    format %{ "psrld   $dst,$shift\t! logical right shift packed4I" %}
    ins_encode %{
      __ psrld($dst$$XMMRegister, $shift$$XMMRegister);

*** 4148,4158 ****
--- 4167,4177 ----
      __ psrld($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{
! instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    match(Set dst (URShiftVI src shift));
    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed4I" %}
    ins_encode %{
      bool vector256 = false;

*** 4170,4180 ****
--- 4189,4199 ----
      __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{
! instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
    match(Set dst (URShiftVI src shift));
    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed8I" %}
    ins_encode %{
      bool vector256 = true;

*** 4193,4203 ****
--- 4212,4222 ----
    %}
    ins_pipe( pipe_slow );
  %}
  
  // Longs vector logical right shift
! instruct vsrl2L(vecX dst, regF shift) %{
! instruct vsrl2L(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (URShiftVL dst shift));
    format %{ "psrlq   $dst,$shift\t! logical right shift packed2L" %}
    ins_encode %{
      __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);

*** 4213,4223 ****
--- 4232,4242 ----
      __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{
! instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (URShiftVL src shift));
    format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed2L" %}
    ins_encode %{
      bool vector256 = false;

*** 4235,4245 ****
--- 4254,4264 ----
      __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{
! instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
    match(Set dst (URShiftVL src shift));
    format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed4L" %}
    ins_encode %{
      bool vector256 = true;

*** 4260,4270 ****
--- 4279,4289 ----
  %}
  
  // ------------------- ArithmeticRightShift -----------------------------------
  
  // Shorts/Chars vector arithmetic right shift
! instruct vsra2S(vecS dst, regF shift) %{
! instruct vsra2S(vecS dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (RShiftVS dst shift));
    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed2S" %}
    ins_encode %{
      __ psraw($dst$$XMMRegister, $shift$$XMMRegister);

*** 4280,4290 ****
--- 4299,4309 ----
      __ psraw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{
! instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (RShiftVS src shift));
    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed2S" %}
    ins_encode %{
      bool vector256 = false;

*** 4302,4312 ****
--- 4321,4331 ----
      __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra4S(vecD dst, regF shift) %{
! instruct vsra4S(vecD dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 4);
    match(Set dst (RShiftVS dst shift));
    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed4S" %}
    ins_encode %{
      __ psraw($dst$$XMMRegister, $shift$$XMMRegister);

*** 4322,4332 ****
--- 4341,4351 ----
      __ psraw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{
! instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    match(Set dst (RShiftVS src shift));
    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed4S" %}
    ins_encode %{
      bool vector256 = false;

*** 4344,4354 ****
--- 4363,4373 ----
      __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra8S(vecX dst, regF shift) %{
! instruct vsra8S(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 8);
    match(Set dst (RShiftVS dst shift));
    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed8S" %}
    ins_encode %{
      __ psraw($dst$$XMMRegister, $shift$$XMMRegister);

*** 4364,4374 ****
--- 4383,4393 ----
      __ psraw($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{
! instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
    match(Set dst (RShiftVS src shift));
    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed8S" %}
    ins_encode %{
      bool vector256 = false;

*** 4386,4396 ****
--- 4405,4415 ----
      __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{
! instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
    match(Set dst (RShiftVS src shift));
    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed16S" %}
    ins_encode %{
      bool vector256 = true;

*** 4409,4419 ****
--- 4428,4438 ----
    %}
    ins_pipe( pipe_slow );
  %}
  
  // Integers vector arithmetic right shift
! instruct vsra2I(vecD dst, regF shift) %{
! instruct vsra2I(vecD dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 2);
    match(Set dst (RShiftVI dst shift));
    format %{ "psrad   $dst,$shift\t! arithmetic right shift packed2I" %}
    ins_encode %{
      __ psrad($dst$$XMMRegister, $shift$$XMMRegister);

*** 4429,4439 ****
--- 4448,4458 ----
      __ psrad($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{
! instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (RShiftVI src shift));
    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed2I" %}
    ins_encode %{
      bool vector256 = false;

*** 4451,4461 ****
--- 4470,4480 ----
      __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra4I(vecX dst, regF shift) %{
! instruct vsra4I(vecX dst, vecS shift) %{
    predicate(n->as_Vector()->length() == 4);
    match(Set dst (RShiftVI dst shift));
    format %{ "psrad   $dst,$shift\t! arithmetic right shift packed4I" %}
    ins_encode %{
      __ psrad($dst$$XMMRegister, $shift$$XMMRegister);

*** 4471,4481 ****
--- 4490,4500 ----
      __ psrad($dst$$XMMRegister, (int)$shift$$constant);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{
! instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    match(Set dst (RShiftVI src shift));
    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed4I" %}
    ins_encode %{
      bool vector256 = false;

*** 4493,4503 ****
--- 4512,4522 ----
      __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
    %}
    ins_pipe( pipe_slow );
  %}
  
! instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{
! instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
    match(Set dst (RShiftVI src shift));
    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed8I" %}
    ins_encode %{
      bool vector256 = true;