*** old/src/share/vm/opto/superword.cpp	Mon Oct  1 15:59:07 2012
--- new/src/share/vm/opto/superword.cpp	Mon Oct  1 15:59:07 2012

*** 1434,1447 ****
--- 1434,1446 ----
      if (opd->is_Vector() || opd->is_LoadVector()) {
        assert(((opd_idx != 2) || !VectorNode::is_shift(p0)), "shift's count can't be vector");
        return opd; // input is matching vector
      }
      if ((opd_idx == 2) && VectorNode::is_shift(p0)) {
        // No vector is needed for shift count.
        // Vector instructions do not mask shift count, do it here.
        Compile* C = _phase->C;
        Node* cnt = opd;
+       // Vector instructions do not mask shift count, do it here.
        juint mask = (p0->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
        const TypeInt* t = opd->find_int_type();
        if (t != NULL && t->is_con()) {
          juint shift = t->get_con();
          if (shift > mask) { // Unsigned cmp

*** 1454,1465 ****
--- 1453,1464 ----
            cnt = new (C) AndINode(opd, cnt);
            _igvn.register_new_node_with_optimizer(cnt);
            _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
          }
          assert(opd->bottom_type()->isa_int(), "int type only");
!         // Move non constant shift count into XMM register.
!         cnt = new (C) MoveI2FNode(cnt);
!         // Move non constant shift count into vector register.
!         cnt = VectorNode::shift_count(C, p0, cnt, vlen, velt_basic_type(p0));
        }
        if (cnt != opd) {
          _igvn.register_new_node_with_optimizer(cnt);
          _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
        }