554 const int Matcher::min_vector_size(const BasicType bt) {
555 int max_size = max_vector_size(bt);
556 // Min size which can be loaded into vector is 4 bytes.
557 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
558 return MIN2(size,max_size);
559 }
560
561 // Vector ideal reg corresponding to specidied size in bytes
562 const int Matcher::vector_ideal_reg(int size) {
563 assert(MaxVectorSize >= size, "");
564 switch(size) {
565 case 4: return Op_VecS;
566 case 8: return Op_VecD;
567 case 16: return Op_VecX;
568 case 32: return Op_VecY;
569 }
570 ShouldNotReachHere();
571 return 0;
572 }
573
574 // x86 supports misaligned vectors store/load.
575 const bool Matcher::misaligned_vectors_ok() {
576 return !AlignVector; // can be changed by flag
577 }
578
579 // Helper methods for MachSpillCopyNode::implementation().
580 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
581 int src_hi, int dst_hi, uint ireg, outputStream* st) {
582 // In 64-bit VM size calculation is very complex. Emitting instructions
583 // into scratch buffer is used to get size in 64-bit VM.
584 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
585 assert(ireg == Op_VecS || // 32bit vector
586 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
587 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
588 "no non-adjacent vector moves" );
589 if (cbuf) {
590 MacroAssembler _masm(cbuf);
591 int offset = __ offset();
592 switch (ireg) {
593 case Op_VecS: // copy whole register
3741 match(Set dst (DivVD src1 src2));
3742 format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %}
3743 ins_encode %{
3744 bool vector256 = true;
3745 __ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256);
3746 %}
3747 ins_pipe( pipe_slow );
3748 %}
3749
3750 instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{
3751 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3752 match(Set dst (DivVD src (LoadVector mem)));
3753 format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %}
3754 ins_encode %{
3755 bool vector256 = true;
3756 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
3757 %}
3758 ins_pipe( pipe_slow );
3759 %}
3760
3761 // ------------------------------ LeftShift -----------------------------------
3762
3763 // Shorts/Chars vector left shift
3764 instruct vsll2S(vecS dst, regF shift) %{
3765 predicate(n->as_Vector()->length() == 2);
3766 match(Set dst (LShiftVS dst shift));
3767 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3768 ins_encode %{
3769 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3770 %}
3771 ins_pipe( pipe_slow );
3772 %}
3773
3774 instruct vsll2S_imm(vecS dst, immI8 shift) %{
3775 predicate(n->as_Vector()->length() == 2);
3776 match(Set dst (LShiftVS dst shift));
3777 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3778 ins_encode %{
3779 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3780 %}
3781 ins_pipe( pipe_slow );
3782 %}
3783
3784 instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{
3785 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3786 match(Set dst (LShiftVS src shift));
3787 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3788 ins_encode %{
3789 bool vector256 = false;
3790 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3791 %}
3792 ins_pipe( pipe_slow );
3793 %}
3794
3795 instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
3796 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3797 match(Set dst (LShiftVS src shift));
3798 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3799 ins_encode %{
3800 bool vector256 = false;
3801 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3802 %}
3803 ins_pipe( pipe_slow );
3804 %}
3805
3806 instruct vsll4S(vecD dst, regF shift) %{
3807 predicate(n->as_Vector()->length() == 4);
3808 match(Set dst (LShiftVS dst shift));
3809 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3810 ins_encode %{
3811 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3812 %}
3813 ins_pipe( pipe_slow );
3814 %}
3815
3816 instruct vsll4S_imm(vecD dst, immI8 shift) %{
3817 predicate(n->as_Vector()->length() == 4);
3818 match(Set dst (LShiftVS dst shift));
3819 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3820 ins_encode %{
3821 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3822 %}
3823 ins_pipe( pipe_slow );
3824 %}
3825
3826 instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{
3827 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3828 match(Set dst (LShiftVS src shift));
3829 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3830 ins_encode %{
3831 bool vector256 = false;
3832 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3833 %}
3834 ins_pipe( pipe_slow );
3835 %}
3836
3837 instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
3838 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3839 match(Set dst (LShiftVS src shift));
3840 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3841 ins_encode %{
3842 bool vector256 = false;
3843 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3844 %}
3845 ins_pipe( pipe_slow );
3846 %}
3847
3848 instruct vsll8S(vecX dst, regF shift) %{
3849 predicate(n->as_Vector()->length() == 8);
3850 match(Set dst (LShiftVS dst shift));
3851 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3852 ins_encode %{
3853 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3854 %}
3855 ins_pipe( pipe_slow );
3856 %}
3857
3858 instruct vsll8S_imm(vecX dst, immI8 shift) %{
3859 predicate(n->as_Vector()->length() == 8);
3860 match(Set dst (LShiftVS dst shift));
3861 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3862 ins_encode %{
3863 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3864 %}
3865 ins_pipe( pipe_slow );
3866 %}
3867
3868 instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{
3869 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3870 match(Set dst (LShiftVS src shift));
3871 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3872 ins_encode %{
3873 bool vector256 = false;
3874 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3875 %}
3876 ins_pipe( pipe_slow );
3877 %}
3878
3879 instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
3880 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3881 match(Set dst (LShiftVS src shift));
3882 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3883 ins_encode %{
3884 bool vector256 = false;
3885 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3886 %}
3887 ins_pipe( pipe_slow );
3888 %}
3889
3890 instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{
3891 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3892 match(Set dst (LShiftVS src shift));
3893 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3894 ins_encode %{
3895 bool vector256 = true;
3896 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3897 %}
3898 ins_pipe( pipe_slow );
3899 %}
3900
3901 instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
3902 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3903 match(Set dst (LShiftVS src shift));
3904 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3905 ins_encode %{
3906 bool vector256 = true;
3907 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3908 %}
3909 ins_pipe( pipe_slow );
3910 %}
3911
3912 // Integers vector left shift
3913 instruct vsll2I(vecD dst, regF shift) %{
3914 predicate(n->as_Vector()->length() == 2);
3915 match(Set dst (LShiftVI dst shift));
3916 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3917 ins_encode %{
3918 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3919 %}
3920 ins_pipe( pipe_slow );
3921 %}
3922
3923 instruct vsll2I_imm(vecD dst, immI8 shift) %{
3924 predicate(n->as_Vector()->length() == 2);
3925 match(Set dst (LShiftVI dst shift));
3926 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3927 ins_encode %{
3928 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3929 %}
3930 ins_pipe( pipe_slow );
3931 %}
3932
3933 instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{
3934 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3935 match(Set dst (LShiftVI src shift));
3936 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3937 ins_encode %{
3938 bool vector256 = false;
3939 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3940 %}
3941 ins_pipe( pipe_slow );
3942 %}
3943
3944 instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
3945 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3946 match(Set dst (LShiftVI src shift));
3947 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3948 ins_encode %{
3949 bool vector256 = false;
3950 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3951 %}
3952 ins_pipe( pipe_slow );
3953 %}
3954
3955 instruct vsll4I(vecX dst, regF shift) %{
3956 predicate(n->as_Vector()->length() == 4);
3957 match(Set dst (LShiftVI dst shift));
3958 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3959 ins_encode %{
3960 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3961 %}
3962 ins_pipe( pipe_slow );
3963 %}
3964
3965 instruct vsll4I_imm(vecX dst, immI8 shift) %{
3966 predicate(n->as_Vector()->length() == 4);
3967 match(Set dst (LShiftVI dst shift));
3968 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3969 ins_encode %{
3970 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3971 %}
3972 ins_pipe( pipe_slow );
3973 %}
3974
3975 instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{
3976 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3977 match(Set dst (LShiftVI src shift));
3978 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3979 ins_encode %{
3980 bool vector256 = false;
3981 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3982 %}
3983 ins_pipe( pipe_slow );
3984 %}
3985
3986 instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
3987 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3988 match(Set dst (LShiftVI src shift));
3989 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
3990 ins_encode %{
3991 bool vector256 = false;
3992 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3993 %}
3994 ins_pipe( pipe_slow );
3995 %}
3996
3997 instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{
3998 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
3999 match(Set dst (LShiftVI src shift));
4000 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4001 ins_encode %{
4002 bool vector256 = true;
4003 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4004 %}
4005 ins_pipe( pipe_slow );
4006 %}
4007
4008 instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4009 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4010 match(Set dst (LShiftVI src shift));
4011 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4012 ins_encode %{
4013 bool vector256 = true;
4014 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4015 %}
4016 ins_pipe( pipe_slow );
4017 %}
4018
4019 // Longs vector left shift
4020 instruct vsll2L(vecX dst, regF shift) %{
4021 predicate(n->as_Vector()->length() == 2);
4022 match(Set dst (LShiftVL dst shift));
4023 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4024 ins_encode %{
4025 __ psllq($dst$$XMMRegister, $shift$$XMMRegister);
4026 %}
4027 ins_pipe( pipe_slow );
4028 %}
4029
4030 instruct vsll2L_imm(vecX dst, immI8 shift) %{
4031 predicate(n->as_Vector()->length() == 2);
4032 match(Set dst (LShiftVL dst shift));
4033 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4034 ins_encode %{
4035 __ psllq($dst$$XMMRegister, (int)$shift$$constant);
4036 %}
4037 ins_pipe( pipe_slow );
4038 %}
4039
4040 instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{
4041 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4042 match(Set dst (LShiftVL src shift));
4043 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4044 ins_encode %{
4045 bool vector256 = false;
4046 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4047 %}
4048 ins_pipe( pipe_slow );
4049 %}
4050
4051 instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4052 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4053 match(Set dst (LShiftVL src shift));
4054 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4055 ins_encode %{
4056 bool vector256 = false;
4057 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4058 %}
4059 ins_pipe( pipe_slow );
4060 %}
4061
4062 instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{
4063 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4064 match(Set dst (LShiftVL src shift));
4065 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4066 ins_encode %{
4067 bool vector256 = true;
4068 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4069 %}
4070 ins_pipe( pipe_slow );
4071 %}
4072
4073 instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4074 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4075 match(Set dst (LShiftVL src shift));
4076 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4077 ins_encode %{
4078 bool vector256 = true;
4079 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4080 %}
4081 ins_pipe( pipe_slow );
4082 %}
4083
4084 // ----------------------- LogicalRightShift -----------------------------------
4085
4086 // Shorts/Chars vector logical right shift produces incorrect Java result
4087 // for negative data because java code convert short value into int with
4088 // sign extension before a shift.
4089
4090 // Integers vector logical right shift
4091 instruct vsrl2I(vecD dst, regF shift) %{
4092 predicate(n->as_Vector()->length() == 2);
4093 match(Set dst (URShiftVI dst shift));
4094 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4095 ins_encode %{
4096 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4097 %}
4098 ins_pipe( pipe_slow );
4099 %}
4100
4101 instruct vsrl2I_imm(vecD dst, immI8 shift) %{
4102 predicate(n->as_Vector()->length() == 2);
4103 match(Set dst (URShiftVI dst shift));
4104 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4105 ins_encode %{
4106 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4107 %}
4108 ins_pipe( pipe_slow );
4109 %}
4110
4111 instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{
4112 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4113 match(Set dst (URShiftVI src shift));
4114 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4115 ins_encode %{
4116 bool vector256 = false;
4117 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4118 %}
4119 ins_pipe( pipe_slow );
4120 %}
4121
4122 instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4123 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4124 match(Set dst (URShiftVI src shift));
4125 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4126 ins_encode %{
4127 bool vector256 = false;
4128 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4129 %}
4130 ins_pipe( pipe_slow );
4131 %}
4132
4133 instruct vsrl4I(vecX dst, regF shift) %{
4134 predicate(n->as_Vector()->length() == 4);
4135 match(Set dst (URShiftVI dst shift));
4136 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4137 ins_encode %{
4138 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4139 %}
4140 ins_pipe( pipe_slow );
4141 %}
4142
4143 instruct vsrl4I_imm(vecX dst, immI8 shift) %{
4144 predicate(n->as_Vector()->length() == 4);
4145 match(Set dst (URShiftVI dst shift));
4146 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4147 ins_encode %{
4148 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4149 %}
4150 ins_pipe( pipe_slow );
4151 %}
4152
4153 instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{
4154 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4155 match(Set dst (URShiftVI src shift));
4156 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4157 ins_encode %{
4158 bool vector256 = false;
4159 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4160 %}
4161 ins_pipe( pipe_slow );
4162 %}
4163
4164 instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4165 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4166 match(Set dst (URShiftVI src shift));
4167 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4168 ins_encode %{
4169 bool vector256 = false;
4170 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4171 %}
4172 ins_pipe( pipe_slow );
4173 %}
4174
4175 instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{
4176 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4177 match(Set dst (URShiftVI src shift));
4178 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4179 ins_encode %{
4180 bool vector256 = true;
4181 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4182 %}
4183 ins_pipe( pipe_slow );
4184 %}
4185
4186 instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4187 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4188 match(Set dst (URShiftVI src shift));
4189 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4190 ins_encode %{
4191 bool vector256 = true;
4192 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4193 %}
4194 ins_pipe( pipe_slow );
4195 %}
4196
4197 // Longs vector logical right shift
4198 instruct vsrl2L(vecX dst, regF shift) %{
4199 predicate(n->as_Vector()->length() == 2);
4200 match(Set dst (URShiftVL dst shift));
4201 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4202 ins_encode %{
4203 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
4204 %}
4205 ins_pipe( pipe_slow );
4206 %}
4207
4208 instruct vsrl2L_imm(vecX dst, immI8 shift) %{
4209 predicate(n->as_Vector()->length() == 2);
4210 match(Set dst (URShiftVL dst shift));
4211 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4212 ins_encode %{
4213 __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
4214 %}
4215 ins_pipe( pipe_slow );
4216 %}
4217
4218 instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{
4219 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4220 match(Set dst (URShiftVL src shift));
4221 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4222 ins_encode %{
4223 bool vector256 = false;
4224 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4225 %}
4226 ins_pipe( pipe_slow );
4227 %}
4228
4229 instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4230 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4231 match(Set dst (URShiftVL src shift));
4232 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4233 ins_encode %{
4234 bool vector256 = false;
4235 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4236 %}
4237 ins_pipe( pipe_slow );
4238 %}
4239
4240 instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{
4241 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4242 match(Set dst (URShiftVL src shift));
4243 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4244 ins_encode %{
4245 bool vector256 = true;
4246 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4247 %}
4248 ins_pipe( pipe_slow );
4249 %}
4250
4251 instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4252 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4253 match(Set dst (URShiftVL src shift));
4254 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4255 ins_encode %{
4256 bool vector256 = true;
4257 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4258 %}
4259 ins_pipe( pipe_slow );
4260 %}
4261
4262 // ------------------- ArithmeticRightShift -----------------------------------
4263
4264 // Shorts/Chars vector arithmetic right shift
4265 instruct vsra2S(vecS dst, regF shift) %{
4266 predicate(n->as_Vector()->length() == 2);
4267 match(Set dst (RShiftVS dst shift));
4268 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4269 ins_encode %{
4270 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4271 %}
4272 ins_pipe( pipe_slow );
4273 %}
4274
4275 instruct vsra2S_imm(vecS dst, immI8 shift) %{
4276 predicate(n->as_Vector()->length() == 2);
4277 match(Set dst (RShiftVS dst shift));
4278 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4279 ins_encode %{
4280 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4281 %}
4282 ins_pipe( pipe_slow );
4283 %}
4284
4285 instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{
4286 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4287 match(Set dst (RShiftVS src shift));
4288 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4289 ins_encode %{
4290 bool vector256 = false;
4291 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4292 %}
4293 ins_pipe( pipe_slow );
4294 %}
4295
4296 instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
4297 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4298 match(Set dst (RShiftVS src shift));
4299 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4300 ins_encode %{
4301 bool vector256 = false;
4302 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4303 %}
4304 ins_pipe( pipe_slow );
4305 %}
4306
4307 instruct vsra4S(vecD dst, regF shift) %{
4308 predicate(n->as_Vector()->length() == 4);
4309 match(Set dst (RShiftVS dst shift));
4310 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4311 ins_encode %{
4312 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4313 %}
4314 ins_pipe( pipe_slow );
4315 %}
4316
4317 instruct vsra4S_imm(vecD dst, immI8 shift) %{
4318 predicate(n->as_Vector()->length() == 4);
4319 match(Set dst (RShiftVS dst shift));
4320 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4321 ins_encode %{
4322 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4323 %}
4324 ins_pipe( pipe_slow );
4325 %}
4326
4327 instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{
4328 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4329 match(Set dst (RShiftVS src shift));
4330 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4331 ins_encode %{
4332 bool vector256 = false;
4333 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4334 %}
4335 ins_pipe( pipe_slow );
4336 %}
4337
4338 instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
4339 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4340 match(Set dst (RShiftVS src shift));
4341 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4342 ins_encode %{
4343 bool vector256 = false;
4344 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4345 %}
4346 ins_pipe( pipe_slow );
4347 %}
4348
4349 instruct vsra8S(vecX dst, regF shift) %{
4350 predicate(n->as_Vector()->length() == 8);
4351 match(Set dst (RShiftVS dst shift));
4352 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4353 ins_encode %{
4354 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4355 %}
4356 ins_pipe( pipe_slow );
4357 %}
4358
4359 instruct vsra8S_imm(vecX dst, immI8 shift) %{
4360 predicate(n->as_Vector()->length() == 8);
4361 match(Set dst (RShiftVS dst shift));
4362 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4363 ins_encode %{
4364 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4365 %}
4366 ins_pipe( pipe_slow );
4367 %}
4368
4369 instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{
4370 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4371 match(Set dst (RShiftVS src shift));
4372 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4373 ins_encode %{
4374 bool vector256 = false;
4375 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4376 %}
4377 ins_pipe( pipe_slow );
4378 %}
4379
4380 instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
4381 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4382 match(Set dst (RShiftVS src shift));
4383 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4384 ins_encode %{
4385 bool vector256 = false;
4386 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4387 %}
4388 ins_pipe( pipe_slow );
4389 %}
4390
4391 instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{
4392 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4393 match(Set dst (RShiftVS src shift));
4394 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4395 ins_encode %{
4396 bool vector256 = true;
4397 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4398 %}
4399 ins_pipe( pipe_slow );
4400 %}
4401
4402 instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
4403 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4404 match(Set dst (RShiftVS src shift));
4405 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4406 ins_encode %{
4407 bool vector256 = true;
4408 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4409 %}
4410 ins_pipe( pipe_slow );
4411 %}
4412
4413 // Integers vector arithmetic right shift
4414 instruct vsra2I(vecD dst, regF shift) %{
4415 predicate(n->as_Vector()->length() == 2);
4416 match(Set dst (RShiftVI dst shift));
4417 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4418 ins_encode %{
4419 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4420 %}
4421 ins_pipe( pipe_slow );
4422 %}
4423
4424 instruct vsra2I_imm(vecD dst, immI8 shift) %{
4425 predicate(n->as_Vector()->length() == 2);
4426 match(Set dst (RShiftVI dst shift));
4427 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4428 ins_encode %{
4429 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4430 %}
4431 ins_pipe( pipe_slow );
4432 %}
4433
4434 instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{
4435 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4436 match(Set dst (RShiftVI src shift));
4437 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4438 ins_encode %{
4439 bool vector256 = false;
4440 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4441 %}
4442 ins_pipe( pipe_slow );
4443 %}
4444
4445 instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4446 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4447 match(Set dst (RShiftVI src shift));
4448 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4449 ins_encode %{
4450 bool vector256 = false;
4451 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4452 %}
4453 ins_pipe( pipe_slow );
4454 %}
4455
4456 instruct vsra4I(vecX dst, regF shift) %{
4457 predicate(n->as_Vector()->length() == 4);
4458 match(Set dst (RShiftVI dst shift));
4459 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4460 ins_encode %{
4461 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4462 %}
4463 ins_pipe( pipe_slow );
4464 %}
4465
4466 instruct vsra4I_imm(vecX dst, immI8 shift) %{
4467 predicate(n->as_Vector()->length() == 4);
4468 match(Set dst (RShiftVI dst shift));
4469 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4470 ins_encode %{
4471 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4472 %}
4473 ins_pipe( pipe_slow );
4474 %}
4475
4476 instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{
4477 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4478 match(Set dst (RShiftVI src shift));
4479 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4480 ins_encode %{
4481 bool vector256 = false;
4482 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4483 %}
4484 ins_pipe( pipe_slow );
4485 %}
4486
4487 instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4488 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4489 match(Set dst (RShiftVI src shift));
4490 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4491 ins_encode %{
4492 bool vector256 = false;
4493 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4494 %}
4495 ins_pipe( pipe_slow );
4496 %}
4497
4498 instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{
4499 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4500 match(Set dst (RShiftVI src shift));
4501 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4502 ins_encode %{
4503 bool vector256 = true;
4504 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4505 %}
4506 ins_pipe( pipe_slow );
4507 %}
4508
4509 instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4510 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4511 match(Set dst (RShiftVI src shift));
4512 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4513 ins_encode %{
4514 bool vector256 = true;
4515 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4516 %}
4517 ins_pipe( pipe_slow );
4518 %}
|
554 const int Matcher::min_vector_size(const BasicType bt) {
555 int max_size = max_vector_size(bt);
556 // Min size which can be loaded into vector is 4 bytes.
557 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
558 return MIN2(size,max_size);
559 }
560
561 // Vector ideal reg corresponding to specidied size in bytes
562 const int Matcher::vector_ideal_reg(int size) {
563 assert(MaxVectorSize >= size, "");
564 switch(size) {
565 case 4: return Op_VecS;
566 case 8: return Op_VecD;
567 case 16: return Op_VecX;
568 case 32: return Op_VecY;
569 }
570 ShouldNotReachHere();
571 return 0;
572 }
573
574 // Only lowest bits of xmm reg are used for vector shift count.
575 const int Matcher::vector_shift_count_ideal_reg(int size) {
576 return Op_VecS;
577 }
578
579 // x86 supports misaligned vectors store/load.
580 const bool Matcher::misaligned_vectors_ok() {
581 return !AlignVector; // can be changed by flag
582 }
583
584 // Helper methods for MachSpillCopyNode::implementation().
585 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
586 int src_hi, int dst_hi, uint ireg, outputStream* st) {
587 // In 64-bit VM size calculation is very complex. Emitting instructions
588 // into scratch buffer is used to get size in 64-bit VM.
589 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
590 assert(ireg == Op_VecS || // 32bit vector
591 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
592 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
593 "no non-adjacent vector moves" );
594 if (cbuf) {
595 MacroAssembler _masm(cbuf);
596 int offset = __ offset();
597 switch (ireg) {
598 case Op_VecS: // copy whole register
3746 match(Set dst (DivVD src1 src2));
3747 format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %}
3748 ins_encode %{
3749 bool vector256 = true;
3750 __ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256);
3751 %}
3752 ins_pipe( pipe_slow );
3753 %}
3754
3755 instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{
3756 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3757 match(Set dst (DivVD src (LoadVector mem)));
3758 format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %}
3759 ins_encode %{
3760 bool vector256 = true;
3761 __ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256);
3762 %}
3763 ins_pipe( pipe_slow );
3764 %}
3765
3766 // ------------------------------ Shift ---------------------------------------
3767
3768 // Shift left count vector (only lowest bits of xmm reg are used for count).
3769 instruct vslcnt(vecS dst, rRegI cnt) %{
3770 match(Set dst (LShiftCntV cnt));
3771 format %{ "movd $dst,$cnt\t! load shift count" %}
3772 ins_encode %{
3773 __ movdl($dst$$XMMRegister, $cnt$$Register);
3774 %}
3775 ins_pipe( pipe_slow );
3776 %}
3777
3778 // Shift right count vector (on x86 it is the same)
3779 instruct vsrcnt(vecS dst, rRegI cnt) %{
3780 match(Set dst (RShiftCntV cnt));
3781 format %{ "movd $dst,$cnt\t! load shift count" %}
3782 ins_encode %{
3783 __ movdl($dst$$XMMRegister, $cnt$$Register);
3784 %}
3785 ins_pipe( pipe_slow );
3786 %}
3787
3788 // ------------------------------ LeftShift -----------------------------------
3789
3790 // Shorts/Chars vector left shift
3791 instruct vsll2S(vecS dst, vecS shift) %{
3792 predicate(n->as_Vector()->length() == 2);
3793 match(Set dst (LShiftVS dst shift));
3794 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3795 ins_encode %{
3796 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3797 %}
3798 ins_pipe( pipe_slow );
3799 %}
3800
3801 instruct vsll2S_imm(vecS dst, immI8 shift) %{
3802 predicate(n->as_Vector()->length() == 2);
3803 match(Set dst (LShiftVS dst shift));
3804 format %{ "psllw $dst,$shift\t! left shift packed2S" %}
3805 ins_encode %{
3806 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3807 %}
3808 ins_pipe( pipe_slow );
3809 %}
3810
3811 instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
3812 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3813 match(Set dst (LShiftVS src shift));
3814 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3815 ins_encode %{
3816 bool vector256 = false;
3817 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3818 %}
3819 ins_pipe( pipe_slow );
3820 %}
3821
3822 instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
3823 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3824 match(Set dst (LShiftVS src shift));
3825 format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %}
3826 ins_encode %{
3827 bool vector256 = false;
3828 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3829 %}
3830 ins_pipe( pipe_slow );
3831 %}
3832
3833 instruct vsll4S(vecD dst, vecS shift) %{
3834 predicate(n->as_Vector()->length() == 4);
3835 match(Set dst (LShiftVS dst shift));
3836 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3837 ins_encode %{
3838 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3839 %}
3840 ins_pipe( pipe_slow );
3841 %}
3842
3843 instruct vsll4S_imm(vecD dst, immI8 shift) %{
3844 predicate(n->as_Vector()->length() == 4);
3845 match(Set dst (LShiftVS dst shift));
3846 format %{ "psllw $dst,$shift\t! left shift packed4S" %}
3847 ins_encode %{
3848 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3849 %}
3850 ins_pipe( pipe_slow );
3851 %}
3852
3853 instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
3854 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3855 match(Set dst (LShiftVS src shift));
3856 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3857 ins_encode %{
3858 bool vector256 = false;
3859 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3860 %}
3861 ins_pipe( pipe_slow );
3862 %}
3863
3864 instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
3865 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
3866 match(Set dst (LShiftVS src shift));
3867 format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %}
3868 ins_encode %{
3869 bool vector256 = false;
3870 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3871 %}
3872 ins_pipe( pipe_slow );
3873 %}
3874
3875 instruct vsll8S(vecX dst, vecS shift) %{
3876 predicate(n->as_Vector()->length() == 8);
3877 match(Set dst (LShiftVS dst shift));
3878 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3879 ins_encode %{
3880 __ psllw($dst$$XMMRegister, $shift$$XMMRegister);
3881 %}
3882 ins_pipe( pipe_slow );
3883 %}
3884
3885 instruct vsll8S_imm(vecX dst, immI8 shift) %{
3886 predicate(n->as_Vector()->length() == 8);
3887 match(Set dst (LShiftVS dst shift));
3888 format %{ "psllw $dst,$shift\t! left shift packed8S" %}
3889 ins_encode %{
3890 __ psllw($dst$$XMMRegister, (int)$shift$$constant);
3891 %}
3892 ins_pipe( pipe_slow );
3893 %}
3894
3895 instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
3896 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3897 match(Set dst (LShiftVS src shift));
3898 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3899 ins_encode %{
3900 bool vector256 = false;
3901 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3902 %}
3903 ins_pipe( pipe_slow );
3904 %}
3905
3906 instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
3907 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
3908 match(Set dst (LShiftVS src shift));
3909 format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %}
3910 ins_encode %{
3911 bool vector256 = false;
3912 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3913 %}
3914 ins_pipe( pipe_slow );
3915 %}
3916
3917 instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
3918 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3919 match(Set dst (LShiftVS src shift));
3920 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3921 ins_encode %{
3922 bool vector256 = true;
3923 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3924 %}
3925 ins_pipe( pipe_slow );
3926 %}
3927
3928 instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
3929 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
3930 match(Set dst (LShiftVS src shift));
3931 format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %}
3932 ins_encode %{
3933 bool vector256 = true;
3934 __ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3935 %}
3936 ins_pipe( pipe_slow );
3937 %}
3938
3939 // Integers vector left shift
3940 instruct vsll2I(vecD dst, vecS shift) %{
3941 predicate(n->as_Vector()->length() == 2);
3942 match(Set dst (LShiftVI dst shift));
3943 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3944 ins_encode %{
3945 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3946 %}
3947 ins_pipe( pipe_slow );
3948 %}
3949
3950 instruct vsll2I_imm(vecD dst, immI8 shift) %{
3951 predicate(n->as_Vector()->length() == 2);
3952 match(Set dst (LShiftVI dst shift));
3953 format %{ "pslld $dst,$shift\t! left shift packed2I" %}
3954 ins_encode %{
3955 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3956 %}
3957 ins_pipe( pipe_slow );
3958 %}
3959
3960 instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
3961 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3962 match(Set dst (LShiftVI src shift));
3963 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3964 ins_encode %{
3965 bool vector256 = false;
3966 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
3967 %}
3968 ins_pipe( pipe_slow );
3969 %}
3970
3971 instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
3972 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
3973 match(Set dst (LShiftVI src shift));
3974 format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %}
3975 ins_encode %{
3976 bool vector256 = false;
3977 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
3978 %}
3979 ins_pipe( pipe_slow );
3980 %}
3981
3982 instruct vsll4I(vecX dst, vecS shift) %{
3983 predicate(n->as_Vector()->length() == 4);
3984 match(Set dst (LShiftVI dst shift));
3985 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3986 ins_encode %{
3987 __ pslld($dst$$XMMRegister, $shift$$XMMRegister);
3988 %}
3989 ins_pipe( pipe_slow );
3990 %}
3991
3992 instruct vsll4I_imm(vecX dst, immI8 shift) %{
3993 predicate(n->as_Vector()->length() == 4);
3994 match(Set dst (LShiftVI dst shift));
3995 format %{ "pslld $dst,$shift\t! left shift packed4I" %}
3996 ins_encode %{
3997 __ pslld($dst$$XMMRegister, (int)$shift$$constant);
3998 %}
3999 ins_pipe( pipe_slow );
4000 %}
4001
4002 instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
4003 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4004 match(Set dst (LShiftVI src shift));
4005 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
4006 ins_encode %{
4007 bool vector256 = false;
4008 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4009 %}
4010 ins_pipe( pipe_slow );
4011 %}
4012
4013 instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4014 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4015 match(Set dst (LShiftVI src shift));
4016 format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %}
4017 ins_encode %{
4018 bool vector256 = false;
4019 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4020 %}
4021 ins_pipe( pipe_slow );
4022 %}
4023
4024 instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
4025 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4026 match(Set dst (LShiftVI src shift));
4027 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4028 ins_encode %{
4029 bool vector256 = true;
4030 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4031 %}
4032 ins_pipe( pipe_slow );
4033 %}
4034
4035 instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4036 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4037 match(Set dst (LShiftVI src shift));
4038 format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %}
4039 ins_encode %{
4040 bool vector256 = true;
4041 __ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4042 %}
4043 ins_pipe( pipe_slow );
4044 %}
4045
4046 // Longs vector left shift
4047 instruct vsll2L(vecX dst, vecS shift) %{
4048 predicate(n->as_Vector()->length() == 2);
4049 match(Set dst (LShiftVL dst shift));
4050 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4051 ins_encode %{
4052 __ psllq($dst$$XMMRegister, $shift$$XMMRegister);
4053 %}
4054 ins_pipe( pipe_slow );
4055 %}
4056
4057 instruct vsll2L_imm(vecX dst, immI8 shift) %{
4058 predicate(n->as_Vector()->length() == 2);
4059 match(Set dst (LShiftVL dst shift));
4060 format %{ "psllq $dst,$shift\t! left shift packed2L" %}
4061 ins_encode %{
4062 __ psllq($dst$$XMMRegister, (int)$shift$$constant);
4063 %}
4064 ins_pipe( pipe_slow );
4065 %}
4066
4067 instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
4068 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4069 match(Set dst (LShiftVL src shift));
4070 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4071 ins_encode %{
4072 bool vector256 = false;
4073 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4074 %}
4075 ins_pipe( pipe_slow );
4076 %}
4077
4078 instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4079 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4080 match(Set dst (LShiftVL src shift));
4081 format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %}
4082 ins_encode %{
4083 bool vector256 = false;
4084 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4085 %}
4086 ins_pipe( pipe_slow );
4087 %}
4088
4089 instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
4090 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4091 match(Set dst (LShiftVL src shift));
4092 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4093 ins_encode %{
4094 bool vector256 = true;
4095 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4096 %}
4097 ins_pipe( pipe_slow );
4098 %}
4099
4100 instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4101 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4102 match(Set dst (LShiftVL src shift));
4103 format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %}
4104 ins_encode %{
4105 bool vector256 = true;
4106 __ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4107 %}
4108 ins_pipe( pipe_slow );
4109 %}
4110
4111 // ----------------------- LogicalRightShift -----------------------------------
4112
4113 // Shorts/Chars vector logical right shift produces incorrect Java result
4114 // for negative data because java code convert short value into int with
4115 // sign extension before a shift.
4116
4117 // Integers vector logical right shift
4118 instruct vsrl2I(vecD dst, vecS shift) %{
4119 predicate(n->as_Vector()->length() == 2);
4120 match(Set dst (URShiftVI dst shift));
4121 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4122 ins_encode %{
4123 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4124 %}
4125 ins_pipe( pipe_slow );
4126 %}
4127
4128 instruct vsrl2I_imm(vecD dst, immI8 shift) %{
4129 predicate(n->as_Vector()->length() == 2);
4130 match(Set dst (URShiftVI dst shift));
4131 format %{ "psrld $dst,$shift\t! logical right shift packed2I" %}
4132 ins_encode %{
4133 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4134 %}
4135 ins_pipe( pipe_slow );
4136 %}
4137
4138 instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
4139 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4140 match(Set dst (URShiftVI src shift));
4141 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4142 ins_encode %{
4143 bool vector256 = false;
4144 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4145 %}
4146 ins_pipe( pipe_slow );
4147 %}
4148
4149 instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4150 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4151 match(Set dst (URShiftVI src shift));
4152 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %}
4153 ins_encode %{
4154 bool vector256 = false;
4155 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4156 %}
4157 ins_pipe( pipe_slow );
4158 %}
4159
4160 instruct vsrl4I(vecX dst, vecS shift) %{
4161 predicate(n->as_Vector()->length() == 4);
4162 match(Set dst (URShiftVI dst shift));
4163 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4164 ins_encode %{
4165 __ psrld($dst$$XMMRegister, $shift$$XMMRegister);
4166 %}
4167 ins_pipe( pipe_slow );
4168 %}
4169
4170 instruct vsrl4I_imm(vecX dst, immI8 shift) %{
4171 predicate(n->as_Vector()->length() == 4);
4172 match(Set dst (URShiftVI dst shift));
4173 format %{ "psrld $dst,$shift\t! logical right shift packed4I" %}
4174 ins_encode %{
4175 __ psrld($dst$$XMMRegister, (int)$shift$$constant);
4176 %}
4177 ins_pipe( pipe_slow );
4178 %}
4179
4180 instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
4181 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4182 match(Set dst (URShiftVI src shift));
4183 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4184 ins_encode %{
4185 bool vector256 = false;
4186 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4187 %}
4188 ins_pipe( pipe_slow );
4189 %}
4190
4191 instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4192 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4193 match(Set dst (URShiftVI src shift));
4194 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %}
4195 ins_encode %{
4196 bool vector256 = false;
4197 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4198 %}
4199 ins_pipe( pipe_slow );
4200 %}
4201
4202 instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
4203 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4204 match(Set dst (URShiftVI src shift));
4205 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4206 ins_encode %{
4207 bool vector256 = true;
4208 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4209 %}
4210 ins_pipe( pipe_slow );
4211 %}
4212
4213 instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4214 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4215 match(Set dst (URShiftVI src shift));
4216 format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %}
4217 ins_encode %{
4218 bool vector256 = true;
4219 __ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4220 %}
4221 ins_pipe( pipe_slow );
4222 %}
4223
4224 // Longs vector logical right shift
4225 instruct vsrl2L(vecX dst, vecS shift) %{
4226 predicate(n->as_Vector()->length() == 2);
4227 match(Set dst (URShiftVL dst shift));
4228 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4229 ins_encode %{
4230 __ psrlq($dst$$XMMRegister, $shift$$XMMRegister);
4231 %}
4232 ins_pipe( pipe_slow );
4233 %}
4234
4235 instruct vsrl2L_imm(vecX dst, immI8 shift) %{
4236 predicate(n->as_Vector()->length() == 2);
4237 match(Set dst (URShiftVL dst shift));
4238 format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %}
4239 ins_encode %{
4240 __ psrlq($dst$$XMMRegister, (int)$shift$$constant);
4241 %}
4242 ins_pipe( pipe_slow );
4243 %}
4244
4245 instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
4246 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4247 match(Set dst (URShiftVL src shift));
4248 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4249 ins_encode %{
4250 bool vector256 = false;
4251 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4252 %}
4253 ins_pipe( pipe_slow );
4254 %}
4255
4256 instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
4257 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4258 match(Set dst (URShiftVL src shift));
4259 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %}
4260 ins_encode %{
4261 bool vector256 = false;
4262 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4263 %}
4264 ins_pipe( pipe_slow );
4265 %}
4266
4267 instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
4268 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4269 match(Set dst (URShiftVL src shift));
4270 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4271 ins_encode %{
4272 bool vector256 = true;
4273 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4274 %}
4275 ins_pipe( pipe_slow );
4276 %}
4277
4278 instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
4279 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
4280 match(Set dst (URShiftVL src shift));
4281 format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %}
4282 ins_encode %{
4283 bool vector256 = true;
4284 __ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4285 %}
4286 ins_pipe( pipe_slow );
4287 %}
4288
4289 // ------------------- ArithmeticRightShift -----------------------------------
4290
4291 // Shorts/Chars vector arithmetic right shift
4292 instruct vsra2S(vecS dst, vecS shift) %{
4293 predicate(n->as_Vector()->length() == 2);
4294 match(Set dst (RShiftVS dst shift));
4295 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4296 ins_encode %{
4297 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4298 %}
4299 ins_pipe( pipe_slow );
4300 %}
4301
4302 instruct vsra2S_imm(vecS dst, immI8 shift) %{
4303 predicate(n->as_Vector()->length() == 2);
4304 match(Set dst (RShiftVS dst shift));
4305 format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %}
4306 ins_encode %{
4307 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4308 %}
4309 ins_pipe( pipe_slow );
4310 %}
4311
4312 instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
4313 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4314 match(Set dst (RShiftVS src shift));
4315 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4316 ins_encode %{
4317 bool vector256 = false;
4318 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4319 %}
4320 ins_pipe( pipe_slow );
4321 %}
4322
4323 instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
4324 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4325 match(Set dst (RShiftVS src shift));
4326 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %}
4327 ins_encode %{
4328 bool vector256 = false;
4329 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4330 %}
4331 ins_pipe( pipe_slow );
4332 %}
4333
4334 instruct vsra4S(vecD dst, vecS shift) %{
4335 predicate(n->as_Vector()->length() == 4);
4336 match(Set dst (RShiftVS dst shift));
4337 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4338 ins_encode %{
4339 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4340 %}
4341 ins_pipe( pipe_slow );
4342 %}
4343
4344 instruct vsra4S_imm(vecD dst, immI8 shift) %{
4345 predicate(n->as_Vector()->length() == 4);
4346 match(Set dst (RShiftVS dst shift));
4347 format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %}
4348 ins_encode %{
4349 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4350 %}
4351 ins_pipe( pipe_slow );
4352 %}
4353
4354 instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
4355 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4356 match(Set dst (RShiftVS src shift));
4357 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4358 ins_encode %{
4359 bool vector256 = false;
4360 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4361 %}
4362 ins_pipe( pipe_slow );
4363 %}
4364
4365 instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
4366 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4367 match(Set dst (RShiftVS src shift));
4368 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %}
4369 ins_encode %{
4370 bool vector256 = false;
4371 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4372 %}
4373 ins_pipe( pipe_slow );
4374 %}
4375
4376 instruct vsra8S(vecX dst, vecS shift) %{
4377 predicate(n->as_Vector()->length() == 8);
4378 match(Set dst (RShiftVS dst shift));
4379 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4380 ins_encode %{
4381 __ psraw($dst$$XMMRegister, $shift$$XMMRegister);
4382 %}
4383 ins_pipe( pipe_slow );
4384 %}
4385
4386 instruct vsra8S_imm(vecX dst, immI8 shift) %{
4387 predicate(n->as_Vector()->length() == 8);
4388 match(Set dst (RShiftVS dst shift));
4389 format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %}
4390 ins_encode %{
4391 __ psraw($dst$$XMMRegister, (int)$shift$$constant);
4392 %}
4393 ins_pipe( pipe_slow );
4394 %}
4395
4396 instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
4397 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4398 match(Set dst (RShiftVS src shift));
4399 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4400 ins_encode %{
4401 bool vector256 = false;
4402 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4403 %}
4404 ins_pipe( pipe_slow );
4405 %}
4406
4407 instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
4408 predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
4409 match(Set dst (RShiftVS src shift));
4410 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %}
4411 ins_encode %{
4412 bool vector256 = false;
4413 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4414 %}
4415 ins_pipe( pipe_slow );
4416 %}
4417
4418 instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
4419 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4420 match(Set dst (RShiftVS src shift));
4421 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4422 ins_encode %{
4423 bool vector256 = true;
4424 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4425 %}
4426 ins_pipe( pipe_slow );
4427 %}
4428
4429 instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
4430 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
4431 match(Set dst (RShiftVS src shift));
4432 format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %}
4433 ins_encode %{
4434 bool vector256 = true;
4435 __ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4436 %}
4437 ins_pipe( pipe_slow );
4438 %}
4439
4440 // Integers vector arithmetic right shift
4441 instruct vsra2I(vecD dst, vecS shift) %{
4442 predicate(n->as_Vector()->length() == 2);
4443 match(Set dst (RShiftVI dst shift));
4444 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4445 ins_encode %{
4446 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4447 %}
4448 ins_pipe( pipe_slow );
4449 %}
4450
4451 instruct vsra2I_imm(vecD dst, immI8 shift) %{
4452 predicate(n->as_Vector()->length() == 2);
4453 match(Set dst (RShiftVI dst shift));
4454 format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %}
4455 ins_encode %{
4456 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4457 %}
4458 ins_pipe( pipe_slow );
4459 %}
4460
4461 instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
4462 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4463 match(Set dst (RShiftVI src shift));
4464 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4465 ins_encode %{
4466 bool vector256 = false;
4467 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4468 %}
4469 ins_pipe( pipe_slow );
4470 %}
4471
4472 instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
4473 predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
4474 match(Set dst (RShiftVI src shift));
4475 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %}
4476 ins_encode %{
4477 bool vector256 = false;
4478 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4479 %}
4480 ins_pipe( pipe_slow );
4481 %}
4482
4483 instruct vsra4I(vecX dst, vecS shift) %{
4484 predicate(n->as_Vector()->length() == 4);
4485 match(Set dst (RShiftVI dst shift));
4486 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4487 ins_encode %{
4488 __ psrad($dst$$XMMRegister, $shift$$XMMRegister);
4489 %}
4490 ins_pipe( pipe_slow );
4491 %}
4492
4493 instruct vsra4I_imm(vecX dst, immI8 shift) %{
4494 predicate(n->as_Vector()->length() == 4);
4495 match(Set dst (RShiftVI dst shift));
4496 format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %}
4497 ins_encode %{
4498 __ psrad($dst$$XMMRegister, (int)$shift$$constant);
4499 %}
4500 ins_pipe( pipe_slow );
4501 %}
4502
4503 instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
4504 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4505 match(Set dst (RShiftVI src shift));
4506 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4507 ins_encode %{
4508 bool vector256 = false;
4509 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4510 %}
4511 ins_pipe( pipe_slow );
4512 %}
4513
4514 instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
4515 predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
4516 match(Set dst (RShiftVI src shift));
4517 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %}
4518 ins_encode %{
4519 bool vector256 = false;
4520 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4521 %}
4522 ins_pipe( pipe_slow );
4523 %}
4524
4525 instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
4526 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4527 match(Set dst (RShiftVI src shift));
4528 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4529 ins_encode %{
4530 bool vector256 = true;
4531 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);
4532 %}
4533 ins_pipe( pipe_slow );
4534 %}
4535
4536 instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
4537 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
4538 match(Set dst (RShiftVI src shift));
4539 format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %}
4540 ins_encode %{
4541 bool vector256 = true;
4542 __ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);
4543 %}
4544 ins_pipe( pipe_slow );
4545 %}
|