1419       }
1420 #endif
1421     }
1422   }
1423   C->set_max_vector_size(max_vlen_in_bytes);
1424 }
1425 
1426 //------------------------------vector_opd---------------------------
1427 // Create a vector operand for the nodes in pack p for operand: in(opd_idx)
1428 Node* SuperWord::vector_opd(Node_List* p, int opd_idx) {
1429   Node* p0 = p->at(0);
1430   uint vlen = p->size();
1431   Node* opd = p0->in(opd_idx);
1432 
1433   if (same_inputs(p, opd_idx)) {
1434     if (opd->is_Vector() || opd->is_LoadVector()) {
1435       assert(((opd_idx != 2) || !VectorNode::is_shift(p0)), "shift's count can't be vector");
1436       return opd; // input is matching vector
1437     }
1438     if ((opd_idx == 2) && VectorNode::is_shift(p0)) {
1439       // No vector is needed for shift count.
1440       // Vector instructions do not mask shift count, do it here.
1441       Compile* C = _phase->C;
1442       Node* cnt = opd;

1443       juint mask = (p0->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
1444       const TypeInt* t = opd->find_int_type();
1445       if (t != NULL && t->is_con()) {
1446         juint shift = t->get_con();
1447         if (shift > mask) { // Unsigned cmp
1448           cnt = ConNode::make(C, TypeInt::make(shift & mask));
1449         }
1450       } else {
1451         if (t == NULL || t->_lo < 0 || t->_hi > (int)mask) {
1452           cnt = ConNode::make(C, TypeInt::make(mask));
1453           _igvn.register_new_node_with_optimizer(cnt);
1454           cnt = new (C, 3) AndINode(opd, cnt);
1455           _igvn.register_new_node_with_optimizer(cnt);
1456           _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
1457         }
1458         assert(opd->bottom_type()->isa_int(), "int type only");
1459         // Move non constant shift count into XMM register.
1460         cnt = new (C, 2) MoveI2FNode(cnt);
1461       }
1462       if (cnt != opd) {
1463         _igvn.register_new_node_with_optimizer(cnt);
1464         _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
1465       }
1466       return cnt;
1467     }
1468     assert(!opd->is_StoreVector(), "such vector is not expected here");
1469     // Convert scalar input to vector with the same number of elements as
1470     // p0's vector. Use p0's type because size of operand's container in
1471     // vector should match p0's size regardless operand's size.
1472     const Type* p0_t = velt_type(p0);
1473     VectorNode* vn = VectorNode::scalar2vector(_phase->C, opd, vlen, p0_t);
1474 
1475     _igvn.register_new_node_with_optimizer(vn);
1476     _phase->set_ctrl(vn, _phase->get_ctrl(opd));
1477 #ifdef ASSERT
1478     if (TraceNewVectors) {
1479       tty->print("new Vector node: ");
1480       vn->dump();

1419       }
1420 #endif
1421     }
1422   }
1423   C->set_max_vector_size(max_vlen_in_bytes);
1424 }
1425 
1426 //------------------------------vector_opd---------------------------
1427 // Create a vector operand for the nodes in pack p for operand: in(opd_idx)
1428 Node* SuperWord::vector_opd(Node_List* p, int opd_idx) {
1429   Node* p0 = p->at(0);
1430   uint vlen = p->size();
1431   Node* opd = p0->in(opd_idx);
1432 
1433   if (same_inputs(p, opd_idx)) {
1434     if (opd->is_Vector() || opd->is_LoadVector()) {
1435       assert(((opd_idx != 2) || !VectorNode::is_shift(p0)), "shift's count can't be vector");
1436       return opd; // input is matching vector
1437     }
1438     if ((opd_idx == 2) && VectorNode::is_shift(p0)) {


1439       Compile* C = _phase->C;
1440       Node* cnt = opd;
1441       // Vector instructions do not mask shift count, do it here.
1442       juint mask = (p0->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
1443       const TypeInt* t = opd->find_int_type();
1444       if (t != NULL && t->is_con()) {
1445         juint shift = t->get_con();
1446         if (shift > mask) { // Unsigned cmp
1447           cnt = ConNode::make(C, TypeInt::make(shift & mask));
1448         }
1449       } else {
1450         if (t == NULL || t->_lo < 0 || t->_hi > (int)mask) {
1451           cnt = ConNode::make(C, TypeInt::make(mask));
1452           _igvn.register_new_node_with_optimizer(cnt);
1453           cnt = new (C, 3) AndINode(opd, cnt);
1454           _igvn.register_new_node_with_optimizer(cnt);
1455           _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
1456         }
1457         assert(opd->bottom_type()->isa_int(), "int type only");
1458         // Move non constant shift count into vector register.
1459         cnt = VectorNode::shift_count(C, p0, cnt, vlen, velt_basic_type(p0));
1460       }
1461       if (cnt != opd) {
1462         _igvn.register_new_node_with_optimizer(cnt);
1463         _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
1464       }
1465       return cnt;
1466     }
1467     assert(!opd->is_StoreVector(), "such vector is not expected here");
1468     // Convert scalar input to vector with the same number of elements as
1469     // p0's vector. Use p0's type because size of operand's container in
1470     // vector should match p0's size regardless operand's size.
1471     const Type* p0_t = velt_type(p0);
1472     VectorNode* vn = VectorNode::scalar2vector(_phase->C, opd, vlen, p0_t);
1473 
1474     _igvn.register_new_node_with_optimizer(vn);
1475     _phase->set_ctrl(vn, _phase->get_ctrl(opd));
1476 #ifdef ASSERT
1477     if (TraceNewVectors) {
1478       tty->print("new Vector node: ");
1479       vn->dump();