src/cpu/x86/vm/assembler_x86.cpp
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src/cpu/x86/vm/assembler_x86.cpp

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*** 2389,2401 **** int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); emit_byte(0x00); emit_byte(0xC0 | encode); } ! void Assembler::pshufb(XMMRegister dst, Address src) { assert(VM_Version::supports_ssse3(), ""); ! assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); InstructionMark im(this); simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); emit_byte(0x00); emit_operand(dst, src); } --- 2389,2401 ---- int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); emit_byte(0x00); emit_byte(0xC0 | encode); } ! void Assembler::pshufb(XMMRegister dst, Address src, bool aligned_adr) { assert(VM_Version::supports_ssse3(), ""); ! assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); InstructionMark im(this); simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); emit_byte(0x00); emit_operand(dst, src); }
src/cpu/x86/vm/assembler_x86.cpp
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