2374 
2375 void Assembler::prefetchw(Address src) {
2376   assert(VM_Version::supports_3dnow_prefetch(), "must support");
2377   InstructionMark im(this);
2378   prefetch_prefix(src);
2379   emit_byte(0x0D);
2380   emit_operand(rcx, src); // 1, src
2381 }
2382 
2383 void Assembler::prefix(Prefix p) {
2384   a_byte(p);
2385 }
2386 
2387 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2388   assert(VM_Version::supports_ssse3(), "");
2389   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2390   emit_byte(0x00);
2391   emit_byte(0xC0 | encode);
2392 }
2393 
2394 void Assembler::pshufb(XMMRegister dst, Address src) {
2395   assert(VM_Version::supports_ssse3(), "");
2396   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2397   InstructionMark im(this);
2398   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2399   emit_byte(0x00);
2400   emit_operand(dst, src);
2401 }
2402 
2403 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2404   assert(isByte(mode), "invalid value");
2405   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2406   emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2407   emit_byte(mode & 0xFF);
2408 
2409 }
2410 
2411 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2412   assert(isByte(mode), "invalid value");
2413   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2414   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2415   InstructionMark im(this);
2416   simd_prefix(dst, src, VEX_SIMD_66);

2374 
2375 void Assembler::prefetchw(Address src) {
2376   assert(VM_Version::supports_3dnow_prefetch(), "must support");
2377   InstructionMark im(this);
2378   prefetch_prefix(src);
2379   emit_byte(0x0D);
2380   emit_operand(rcx, src); // 1, src
2381 }
2382 
2383 void Assembler::prefix(Prefix p) {
2384   a_byte(p);
2385 }
2386 
2387 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2388   assert(VM_Version::supports_ssse3(), "");
2389   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2390   emit_byte(0x00);
2391   emit_byte(0xC0 | encode);
2392 }
2393 
2394 void Assembler::pshufb(XMMRegister dst, Address src, bool aligned_adr) {
2395   assert(VM_Version::supports_ssse3(), "");
2396   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2397   InstructionMark im(this);
2398   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2399   emit_byte(0x00);
2400   emit_operand(dst, src);
2401 }
2402 
2403 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2404   assert(isByte(mode), "invalid value");
2405   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2406   emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2407   emit_byte(mode & 0xFF);
2408 
2409 }
2410 
2411 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2412   assert(isByte(mode), "invalid value");
2413   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2414   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2415   InstructionMark im(this);
2416   simd_prefix(dst, src, VEX_SIMD_66);