1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "memory/resourceArea.hpp"
  29 #include "runtime/java.hpp"
  30 #include "runtime/stubCodeGenerator.hpp"
  31 #include "vm_version_x86.hpp"
  32 #ifdef TARGET_OS_FAMILY_linux
  33 # include "os_linux.inline.hpp"
  34 #endif
  35 #ifdef TARGET_OS_FAMILY_solaris
  36 # include "os_solaris.inline.hpp"
  37 #endif
  38 #ifdef TARGET_OS_FAMILY_windows
  39 # include "os_windows.inline.hpp"
  40 #endif
  41 #ifdef TARGET_OS_FAMILY_bsd
  42 # include "os_bsd.inline.hpp"
  43 #endif
  44 
  45 
  46 int VM_Version::_cpu;
  47 int VM_Version::_model;
  48 int VM_Version::_stepping;
  49 int VM_Version::_cpuFeatures;
  50 const char*           VM_Version::_features_str = "";
  51 VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
  52 
  53 static BufferBlob* stub_blob;
  54 static const int stub_size = 550;
  55 
  56 extern "C" {
  57   typedef void (*getPsrInfo_stub_t)(void*);
  58 }
  59 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
  60 
  61 
  62 class VM_Version_StubGenerator: public StubCodeGenerator {
  63  public:
  64 
  65   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  66 
  67   address generate_getPsrInfo() {
  68     // Flags to test CPU type.
  69     const uint32_t HS_EFL_AC           = 0x40000;
  70     const uint32_t HS_EFL_ID           = 0x200000;
  71     // Values for when we don't have a CPUID instruction.
  72     const int      CPU_FAMILY_SHIFT = 8;
  73     const uint32_t CPU_FAMILY_386   = (3 << CPU_FAMILY_SHIFT);
  74     const uint32_t CPU_FAMILY_486   = (4 << CPU_FAMILY_SHIFT);
  75 
  76     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  77     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
  78 
  79     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
  80 #   define __ _masm->
  81 
  82     address start = __ pc();
  83 
  84     //
  85     // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
  86     //
  87     // LP64: rcx and rdx are first and second argument registers on windows
  88 
  89     __ push(rbp);
  90 #ifdef _LP64
  91     __ mov(rbp, c_rarg0); // cpuid_info address
  92 #else
  93     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  94 #endif
  95     __ push(rbx);
  96     __ push(rsi);
  97     __ pushf();          // preserve rbx, and flags
  98     __ pop(rax);
  99     __ push(rax);
 100     __ mov(rcx, rax);
 101     //
 102     // if we are unable to change the AC flag, we have a 386
 103     //
 104     __ xorl(rax, HS_EFL_AC);
 105     __ push(rax);
 106     __ popf();
 107     __ pushf();
 108     __ pop(rax);
 109     __ cmpptr(rax, rcx);
 110     __ jccb(Assembler::notEqual, detect_486);
 111 
 112     __ movl(rax, CPU_FAMILY_386);
 113     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 114     __ jmp(done);
 115 
 116     //
 117     // If we are unable to change the ID flag, we have a 486 which does
 118     // not support the "cpuid" instruction.
 119     //
 120     __ bind(detect_486);
 121     __ mov(rax, rcx);
 122     __ xorl(rax, HS_EFL_ID);
 123     __ push(rax);
 124     __ popf();
 125     __ pushf();
 126     __ pop(rax);
 127     __ cmpptr(rcx, rax);
 128     __ jccb(Assembler::notEqual, detect_586);
 129 
 130     __ bind(cpu486);
 131     __ movl(rax, CPU_FAMILY_486);
 132     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 133     __ jmp(done);
 134 
 135     //
 136     // At this point, we have a chip which supports the "cpuid" instruction
 137     //
 138     __ bind(detect_586);
 139     __ xorl(rax, rax);
 140     __ cpuid();
 141     __ orl(rax, rax);
 142     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 143                                         // value of at least 1, we give up and
 144                                         // assume a 486
 145     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 146     __ movl(Address(rsi, 0), rax);
 147     __ movl(Address(rsi, 4), rbx);
 148     __ movl(Address(rsi, 8), rcx);
 149     __ movl(Address(rsi,12), rdx);
 150 
 151     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 152     __ jccb(Assembler::belowEqual, std_cpuid4);
 153 
 154     //
 155     // cpuid(0xB) Processor Topology
 156     //
 157     __ movl(rax, 0xb);
 158     __ xorl(rcx, rcx);   // Threads level
 159     __ cpuid();
 160 
 161     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 162     __ movl(Address(rsi, 0), rax);
 163     __ movl(Address(rsi, 4), rbx);
 164     __ movl(Address(rsi, 8), rcx);
 165     __ movl(Address(rsi,12), rdx);
 166 
 167     __ movl(rax, 0xb);
 168     __ movl(rcx, 1);     // Cores level
 169     __ cpuid();
 170     __ push(rax);
 171     __ andl(rax, 0x1f);  // Determine if valid topology level
 172     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 173     __ andl(rax, 0xffff);
 174     __ pop(rax);
 175     __ jccb(Assembler::equal, std_cpuid4);
 176 
 177     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 178     __ movl(Address(rsi, 0), rax);
 179     __ movl(Address(rsi, 4), rbx);
 180     __ movl(Address(rsi, 8), rcx);
 181     __ movl(Address(rsi,12), rdx);
 182 
 183     __ movl(rax, 0xb);
 184     __ movl(rcx, 2);     // Packages level
 185     __ cpuid();
 186     __ push(rax);
 187     __ andl(rax, 0x1f);  // Determine if valid topology level
 188     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 189     __ andl(rax, 0xffff);
 190     __ pop(rax);
 191     __ jccb(Assembler::equal, std_cpuid4);
 192 
 193     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 194     __ movl(Address(rsi, 0), rax);
 195     __ movl(Address(rsi, 4), rbx);
 196     __ movl(Address(rsi, 8), rcx);
 197     __ movl(Address(rsi,12), rdx);
 198 
 199     //
 200     // cpuid(0x4) Deterministic cache params
 201     //
 202     __ bind(std_cpuid4);
 203     __ movl(rax, 4);
 204     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 205     __ jccb(Assembler::greater, std_cpuid1);
 206 
 207     __ xorl(rcx, rcx);   // L1 cache
 208     __ cpuid();
 209     __ push(rax);
 210     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 211     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 212     __ pop(rax);
 213     __ jccb(Assembler::equal, std_cpuid1);
 214 
 215     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 216     __ movl(Address(rsi, 0), rax);
 217     __ movl(Address(rsi, 4), rbx);
 218     __ movl(Address(rsi, 8), rcx);
 219     __ movl(Address(rsi,12), rdx);
 220 
 221     //
 222     // Standard cpuid(0x1)
 223     //
 224     __ bind(std_cpuid1);
 225     __ movl(rax, 1);
 226     __ cpuid();
 227     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 228     __ movl(Address(rsi, 0), rax);
 229     __ movl(Address(rsi, 4), rbx);
 230     __ movl(Address(rsi, 8), rcx);
 231     __ movl(Address(rsi,12), rdx);
 232 
 233     //
 234     // Check if OS has enabled XGETBV instruction to access XCR0
 235     // (OSXSAVE feature flag) and CPU supports AVX
 236     //
 237     __ andl(rcx, 0x18000000);
 238     __ cmpl(rcx, 0x18000000);
 239     __ jccb(Assembler::notEqual, sef_cpuid);
 240 
 241     //
 242     // XCR0, XFEATURE_ENABLED_MASK register
 243     //
 244     __ xorl(rcx, rcx);   // zero for XCR0 register
 245     __ xgetbv();
 246     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 247     __ movl(Address(rsi, 0), rax);
 248     __ movl(Address(rsi, 4), rdx);
 249 
 250     //
 251     // cpuid(0x7) Structured Extended Features
 252     //
 253     __ bind(sef_cpuid);
 254     __ movl(rax, 7);
 255     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 256     __ jccb(Assembler::greater, ext_cpuid);
 257 
 258     __ xorl(rcx, rcx);
 259     __ cpuid();
 260     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 261     __ movl(Address(rsi, 0), rax);
 262     __ movl(Address(rsi, 4), rbx);
 263 
 264     //
 265     // Extended cpuid(0x80000000)
 266     //
 267     __ bind(ext_cpuid);
 268     __ movl(rax, 0x80000000);
 269     __ cpuid();
 270     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 271     __ jcc(Assembler::belowEqual, done);
 272     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 273     __ jccb(Assembler::belowEqual, ext_cpuid1);
 274     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 275     __ jccb(Assembler::belowEqual, ext_cpuid5);
 276     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 277     __ jccb(Assembler::belowEqual, ext_cpuid7);
 278     //
 279     // Extended cpuid(0x80000008)
 280     //
 281     __ movl(rax, 0x80000008);
 282     __ cpuid();
 283     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 284     __ movl(Address(rsi, 0), rax);
 285     __ movl(Address(rsi, 4), rbx);
 286     __ movl(Address(rsi, 8), rcx);
 287     __ movl(Address(rsi,12), rdx);
 288 
 289     //
 290     // Extended cpuid(0x80000007)
 291     //
 292     __ bind(ext_cpuid7);
 293     __ movl(rax, 0x80000007);
 294     __ cpuid();
 295     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 296     __ movl(Address(rsi, 0), rax);
 297     __ movl(Address(rsi, 4), rbx);
 298     __ movl(Address(rsi, 8), rcx);
 299     __ movl(Address(rsi,12), rdx);
 300 
 301     //
 302     // Extended cpuid(0x80000005)
 303     //
 304     __ bind(ext_cpuid5);
 305     __ movl(rax, 0x80000005);
 306     __ cpuid();
 307     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 308     __ movl(Address(rsi, 0), rax);
 309     __ movl(Address(rsi, 4), rbx);
 310     __ movl(Address(rsi, 8), rcx);
 311     __ movl(Address(rsi,12), rdx);
 312 
 313     //
 314     // Extended cpuid(0x80000001)
 315     //
 316     __ bind(ext_cpuid1);
 317     __ movl(rax, 0x80000001);
 318     __ cpuid();
 319     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 320     __ movl(Address(rsi, 0), rax);
 321     __ movl(Address(rsi, 4), rbx);
 322     __ movl(Address(rsi, 8), rcx);
 323     __ movl(Address(rsi,12), rdx);
 324 
 325     //
 326     // return
 327     //
 328     __ bind(done);
 329     __ popf();
 330     __ pop(rsi);
 331     __ pop(rbx);
 332     __ pop(rbp);
 333     __ ret(0);
 334 
 335 #   undef __
 336 
 337     return start;
 338   };
 339 };
 340 
 341 
 342 void VM_Version::get_processor_features() {
 343 
 344   _cpu = 4; // 486 by default
 345   _model = 0;
 346   _stepping = 0;
 347   _cpuFeatures = 0;
 348   _logical_processors_per_package = 1;
 349 
 350   if (!Use486InstrsOnly) {
 351     // Get raw processor info
 352     getPsrInfo_stub(&_cpuid_info);
 353     assert_is_initialized();
 354     _cpu = extended_cpu_family();
 355     _model = extended_cpu_model();
 356     _stepping = cpu_stepping();
 357 
 358     if (cpu_family() > 4) { // it supports CPUID
 359       _cpuFeatures = feature_flags();
 360       // Logical processors are only available on P4s and above,
 361       // and only if hyperthreading is available.
 362       _logical_processors_per_package = logical_processor_count();
 363     }
 364   }
 365 
 366   _supports_cx8 = supports_cmpxchg8();
 367   // xchg and xadd instructions
 368   _supports_atomic_getset4 = true;
 369   _supports_atomic_getadd4 = true;
 370   LP64_ONLY(_supports_atomic_getset8 = true);
 371   LP64_ONLY(_supports_atomic_getadd8 = true);
 372 
 373 #ifdef _LP64
 374   // OS should support SSE for x64 and hardware should support at least SSE2.
 375   if (!VM_Version::supports_sse2()) {
 376     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 377   }
 378   // in 64 bit the use of SSE2 is the minimum
 379   if (UseSSE < 2) UseSSE = 2;
 380 #endif
 381 
 382 #ifdef AMD64
 383   // flush_icache_stub have to be generated first.
 384   // That is why Icache line size is hard coded in ICache class,
 385   // see icache_x86.hpp. It is also the reason why we can't use
 386   // clflush instruction in 32-bit VM since it could be running
 387   // on CPU which does not support it.
 388   //
 389   // The only thing we can do is to verify that flushed
 390   // ICache::line_size has correct value.
 391   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 392   // clflush_size is size in quadwords (8 bytes).
 393   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 394 #endif
 395 
 396   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 397   if (!os::supports_sse())
 398     _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 399 
 400   if (UseSSE < 4) {
 401     _cpuFeatures &= ~CPU_SSE4_1;
 402     _cpuFeatures &= ~CPU_SSE4_2;
 403   }
 404 
 405   if (UseSSE < 3) {
 406     _cpuFeatures &= ~CPU_SSE3;
 407     _cpuFeatures &= ~CPU_SSSE3;
 408     _cpuFeatures &= ~CPU_SSE4A;
 409   }
 410 
 411   if (UseSSE < 2)
 412     _cpuFeatures &= ~CPU_SSE2;
 413 
 414   if (UseSSE < 1)
 415     _cpuFeatures &= ~CPU_SSE;
 416 
 417   if (UseAVX < 2)
 418     _cpuFeatures &= ~CPU_AVX2;
 419 
 420   if (UseAVX < 1)
 421     _cpuFeatures &= ~CPU_AVX;
 422 
 423   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
 424     _cpuFeatures &= ~CPU_AES;
 425 
 426   if (logical_processors_per_package() == 1) {
 427     // HT processor could be installed on a system which doesn't support HT.
 428     _cpuFeatures &= ~CPU_HT;
 429   }
 430 
 431   char buf[256];
 432   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 433                cores_per_cpu(), threads_per_core(),
 434                cpu_family(), _model, _stepping,
 435                (supports_cmov() ? ", cmov" : ""),
 436                (supports_cmpxchg8() ? ", cx8" : ""),
 437                (supports_fxsr() ? ", fxsr" : ""),
 438                (supports_mmx()  ? ", mmx"  : ""),
 439                (supports_sse()  ? ", sse"  : ""),
 440                (supports_sse2() ? ", sse2" : ""),
 441                (supports_sse3() ? ", sse3" : ""),
 442                (supports_ssse3()? ", ssse3": ""),
 443                (supports_sse4_1() ? ", sse4.1" : ""),
 444                (supports_sse4_2() ? ", sse4.2" : ""),
 445                (supports_popcnt() ? ", popcnt" : ""),
 446                (supports_avx()    ? ", avx" : ""),
 447                (supports_avx2()   ? ", avx2" : ""),
 448                (supports_aes()    ? ", aes" : ""),
 449                (supports_mmx_ext() ? ", mmxext" : ""),
 450                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 451                (supports_lzcnt()   ? ", lzcnt": ""),
 452                (supports_sse4a()   ? ", sse4a": ""),
 453                (supports_ht() ? ", ht": ""),
 454                (supports_tsc() ? ", tsc": ""),
 455                (supports_tscinv_bit() ? ", tscinvbit": ""),
 456                (supports_tscinv() ? ", tscinv": ""));
 457   _features_str = strdup(buf);
 458 
 459   // UseSSE is set to the smaller of what hardware supports and what
 460   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 461   // older Pentiums which do not support it.
 462   if (UseSSE > 4) UseSSE=4;
 463   if (UseSSE < 0) UseSSE=0;
 464   if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
 465     UseSSE = MIN2((intx)3,UseSSE);
 466   if (!supports_sse3()) // Drop to 2 if no SSE3 support
 467     UseSSE = MIN2((intx)2,UseSSE);
 468   if (!supports_sse2()) // Drop to 1 if no SSE2 support
 469     UseSSE = MIN2((intx)1,UseSSE);
 470   if (!supports_sse ()) // Drop to 0 if no SSE  support
 471     UseSSE = 0;
 472 
 473   if (UseAVX > 2) UseAVX=2;
 474   if (UseAVX < 0) UseAVX=0;
 475   if (!supports_avx2()) // Drop to 1 if no AVX2 support
 476     UseAVX = MIN2((intx)1,UseAVX);
 477   if (!supports_avx ()) // Drop to 0 if no AVX  support
 478     UseAVX = 0;
 479 
 480   // Use AES instructions if available.
 481   if (supports_aes()) {
 482     if (FLAG_IS_DEFAULT(UseAES)) {
 483       UseAES = true;
 484     }
 485   } else if (UseAES) {
 486     if (!FLAG_IS_DEFAULT(UseAES))
 487       warning("AES instructions not available on this CPU");
 488     FLAG_SET_DEFAULT(UseAES, false);
 489   }
 490 
 491   // The AES intrinsic stubs require AES instruction support (of course)
 492   // but also require sse3 mode for instructions it use.
 493   if (UseAES && (UseSSE > 2)) {
 494     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 495       UseAESIntrinsics = true;
 496     }
 497   } else if (UseAESIntrinsics) {
 498     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 499       warning("AES intrinsics not available on this CPU");
 500     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 501   }
 502 
 503 #ifdef COMPILER2
 504   if (UseFPUForSpilling) {
 505     if (UseSSE < 2) {
 506       // Only supported with SSE2+
 507       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 508     }
 509   }
 510   if (MaxVectorSize > 0) {
 511     if (!is_power_of_2(MaxVectorSize)) {
 512       warning("MaxVectorSize must be a power of 2");
 513       FLAG_SET_DEFAULT(MaxVectorSize, 32);
 514     }
 515     if (MaxVectorSize > 32) {
 516       FLAG_SET_DEFAULT(MaxVectorSize, 32);
 517     }
 518     if (MaxVectorSize > 16 && UseAVX == 0) {
 519       // Only supported with AVX+
 520       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 521     }
 522     if (UseSSE < 2) {
 523       // Only supported with SSE2+
 524       FLAG_SET_DEFAULT(MaxVectorSize, 0);
 525     }
 526   }
 527 #endif
 528 
 529   // On new cpus instructions which update whole XMM register should be used
 530   // to prevent partial register stall due to dependencies on high half.
 531   //
 532   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
 533   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
 534   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
 535   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
 536 
 537   if( is_amd() ) { // AMD cpus specific settings
 538     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
 539       // Use it on new AMD cpus starting from Opteron.
 540       UseAddressNop = true;
 541     }
 542     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
 543       // Use it on new AMD cpus starting from Opteron.
 544       UseNewLongLShift = true;
 545     }
 546     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 547       if( supports_sse4a() ) {
 548         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
 549       } else {
 550         UseXmmLoadAndClearUpper = false;
 551       }
 552     }
 553     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 554       if( supports_sse4a() ) {
 555         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
 556       } else {
 557         UseXmmRegToRegMoveAll = false;
 558       }
 559     }
 560     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
 561       if( supports_sse4a() ) {
 562         UseXmmI2F = true;
 563       } else {
 564         UseXmmI2F = false;
 565       }
 566     }
 567     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
 568       if( supports_sse4a() ) {
 569         UseXmmI2D = true;
 570       } else {
 571         UseXmmI2D = false;
 572       }
 573     }
 574     if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
 575       if( supports_sse4_2() && UseSSE >= 4 ) {
 576         UseSSE42Intrinsics = true;
 577       }
 578     }
 579 
 580     // Use count leading zeros count instruction if available.
 581     if (supports_lzcnt()) {
 582       if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 583         UseCountLeadingZerosInstruction = true;
 584       }
 585     }
 586 
 587     // some defaults for AMD family 15h
 588     if ( cpu_family() == 0x15 ) {
 589       // On family 15h processors default is no sw prefetch
 590       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 591         AllocatePrefetchStyle = 0;
 592       }
 593       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
 594       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
 595         AllocatePrefetchInstr = 3;
 596       }
 597       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
 598       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 599         UseXMMForArrayCopy = true;
 600       }
 601       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 602         UseUnalignedLoadStores = true;
 603       }
 604     }
 605 
 606 #ifdef COMPILER2
 607     if (MaxVectorSize > 16) {
 608       // Limit vectors size to 16 bytes on current AMD cpus.
 609       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 610     }
 611 #endif // COMPILER2
 612   }
 613 
 614   if( is_intel() ) { // Intel cpus specific settings
 615     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
 616       UseStoreImmI16 = false; // don't use it on Intel cpus
 617     }
 618     if( cpu_family() == 6 || cpu_family() == 15 ) {
 619       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
 620         // Use it on all Intel cpus starting from PentiumPro
 621         UseAddressNop = true;
 622       }
 623     }
 624     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 625       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
 626     }
 627     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 628       if( supports_sse3() ) {
 629         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
 630       } else {
 631         UseXmmRegToRegMoveAll = false;
 632       }
 633     }
 634     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
 635 #ifdef COMPILER2
 636       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
 637         // For new Intel cpus do the next optimization:
 638         // don't align the beginning of a loop if there are enough instructions
 639         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
 640         // in current fetch line (OptoLoopAlignment) or the padding
 641         // is big (> MaxLoopPad).
 642         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
 643         // generated NOP instructions. 11 is the largest size of one
 644         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
 645         MaxLoopPad = 11;
 646       }
 647 #endif // COMPILER2
 648       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 649         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
 650       }
 651       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
 652         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 653           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 654         }
 655       }
 656       if (supports_sse4_2() && UseSSE >= 4) {
 657         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
 658           UseSSE42Intrinsics = true;
 659         }
 660       }
 661     }
 662   }
 663 
 664   // Use population count instruction if available.
 665   if (supports_popcnt()) {
 666     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 667       UsePopCountInstruction = true;
 668     }
 669   } else if (UsePopCountInstruction) {
 670     warning("POPCNT instruction is not available on this CPU");
 671     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 672   }
 673 
 674 #ifdef COMPILER2
 675   if (FLAG_IS_DEFAULT(AlignVector)) {
 676     // Modern processors allow misaligned memory operations for vectors.
 677     AlignVector = !UseUnalignedLoadStores;
 678   }
 679 #endif // COMPILER2
 680 
 681   assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
 682   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
 683 
 684   // set valid Prefetch instruction
 685   if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
 686   if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
 687   if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
 688   if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
 689 
 690   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
 691   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
 692   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
 693   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
 694 
 695   // Allocation prefetch settings
 696   intx cache_line_size = prefetch_data_size();
 697   if( cache_line_size > AllocatePrefetchStepSize )
 698     AllocatePrefetchStepSize = cache_line_size;
 699 
 700   assert(AllocatePrefetchLines > 0, "invalid value");
 701   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
 702     AllocatePrefetchLines = 3;
 703   assert(AllocateInstancePrefetchLines > 0, "invalid value");
 704   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
 705     AllocateInstancePrefetchLines = 1;
 706 
 707   AllocatePrefetchDistance = allocate_prefetch_distance();
 708   AllocatePrefetchStyle    = allocate_prefetch_style();
 709 
 710   if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
 711     if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
 712 #ifdef _LP64
 713       AllocatePrefetchDistance = 384;
 714 #else
 715       AllocatePrefetchDistance = 320;
 716 #endif
 717     }
 718     if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
 719       AllocatePrefetchDistance = 192;
 720       AllocatePrefetchLines = 4;
 721 #ifdef COMPILER2
 722       if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
 723         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 724       }
 725 #endif
 726     }
 727   }
 728   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
 729 
 730 #ifdef _LP64
 731   // Prefetch settings
 732   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
 733   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
 734   PrefetchFieldsAhead         = prefetch_fields_ahead();
 735 #endif
 736 
 737 #ifndef PRODUCT
 738   if (PrintMiscellaneous && Verbose) {
 739     tty->print_cr("Logical CPUs per core: %u",
 740                   logical_processors_per_package());
 741     tty->print("UseSSE=%d",UseSSE);
 742     if (UseAVX > 0) {
 743       tty->print("  UseAVX=%d",UseAVX);
 744     }
 745     if (UseAES) {
 746       tty->print("  UseAES=1");
 747     }
 748     tty->cr();
 749     tty->print("Allocation");
 750     if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
 751       tty->print_cr(": no prefetching");
 752     } else {
 753       tty->print(" prefetching: ");
 754       if (UseSSE == 0 && supports_3dnow_prefetch()) {
 755         tty->print("PREFETCHW");
 756       } else if (UseSSE >= 1) {
 757         if (AllocatePrefetchInstr == 0) {
 758           tty->print("PREFETCHNTA");
 759         } else if (AllocatePrefetchInstr == 1) {
 760           tty->print("PREFETCHT0");
 761         } else if (AllocatePrefetchInstr == 2) {
 762           tty->print("PREFETCHT2");
 763         } else if (AllocatePrefetchInstr == 3) {
 764           tty->print("PREFETCHW");
 765         }
 766       }
 767       if (AllocatePrefetchLines > 1) {
 768         tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
 769       } else {
 770         tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
 771       }
 772     }
 773 
 774     if (PrefetchCopyIntervalInBytes > 0) {
 775       tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
 776     }
 777     if (PrefetchScanIntervalInBytes > 0) {
 778       tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
 779     }
 780     if (PrefetchFieldsAhead > 0) {
 781       tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
 782     }
 783   }
 784 #endif // !PRODUCT
 785 }
 786 
 787 void VM_Version::initialize() {
 788   ResourceMark rm;
 789   // Making this stub must be FIRST use of assembler
 790 
 791   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
 792   if (stub_blob == NULL) {
 793     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
 794   }
 795   CodeBuffer c(stub_blob);
 796   VM_Version_StubGenerator g(&c);
 797   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
 798                                    g.generate_getPsrInfo());
 799 
 800   get_processor_features();
 801 }