472 
 473   if (UseAVX > 2) UseAVX=2;
 474   if (UseAVX < 0) UseAVX=0;
 475   if (!supports_avx2()) // Drop to 1 if no AVX2 support
 476     UseAVX = MIN2((intx)1,UseAVX);
 477   if (!supports_avx ()) // Drop to 0 if no AVX  support
 478     UseAVX = 0;
 479 
 480   // Use AES instructions if available.
 481   if (supports_aes()) {
 482     if (FLAG_IS_DEFAULT(UseAES)) {
 483       UseAES = true;
 484     }
 485   } else if (UseAES) {
 486     if (!FLAG_IS_DEFAULT(UseAES))
 487       warning("AES instructions not available on this CPU");
 488     FLAG_SET_DEFAULT(UseAES, false);
 489   }
 490 
 491   // The AES intrinsic stubs require AES instruction support (of course)
 492   // but also require AVX and sse3 modes for instructions it use.
 493   if (UseAES && (UseAVX > 0) && (UseSSE > 2)) {
 494     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 495       UseAESIntrinsics = true;
 496     }
 497   } else if (UseAESIntrinsics) {
 498     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 499       warning("AES intrinsics not available on this CPU");
 500     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 501   }
 502 
 503 #ifdef COMPILER2
 504   if (UseFPUForSpilling) {
 505     if (UseSSE < 2) {
 506       // Only supported with SSE2+
 507       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 508     }
 509   }
 510   if (MaxVectorSize > 0) {
 511     if (!is_power_of_2(MaxVectorSize)) {
 512       warning("MaxVectorSize must be a power of 2");
 513       FLAG_SET_DEFAULT(MaxVectorSize, 32);

 472 
 473   if (UseAVX > 2) UseAVX=2;
 474   if (UseAVX < 0) UseAVX=0;
 475   if (!supports_avx2()) // Drop to 1 if no AVX2 support
 476     UseAVX = MIN2((intx)1,UseAVX);
 477   if (!supports_avx ()) // Drop to 0 if no AVX  support
 478     UseAVX = 0;
 479 
 480   // Use AES instructions if available.
 481   if (supports_aes()) {
 482     if (FLAG_IS_DEFAULT(UseAES)) {
 483       UseAES = true;
 484     }
 485   } else if (UseAES) {
 486     if (!FLAG_IS_DEFAULT(UseAES))
 487       warning("AES instructions not available on this CPU");
 488     FLAG_SET_DEFAULT(UseAES, false);
 489   }
 490 
 491   // The AES intrinsic stubs require AES instruction support (of course)
 492   // but also require sse3 mode for instructions it use.
 493   if (UseAES && (UseSSE > 2)) {
 494     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 495       UseAESIntrinsics = true;
 496     }
 497   } else if (UseAESIntrinsics) {
 498     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 499       warning("AES intrinsics not available on this CPU");
 500     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 501   }
 502 
 503 #ifdef COMPILER2
 504   if (UseFPUForSpilling) {
 505     if (UseSSE < 2) {
 506       // Only supported with SSE2+
 507       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 508     }
 509   }
 510   if (MaxVectorSize > 0) {
 511     if (!is_power_of_2(MaxVectorSize)) {
 512       warning("MaxVectorSize must be a power of 2");
 513       FLAG_SET_DEFAULT(MaxVectorSize, 32);